diff --git a/.DS_Store b/.DS_Store index d7af12d..a29c04c 100644 Binary files a/.DS_Store and b/.DS_Store differ diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..5ceca99 --- /dev/null +++ b/.cproject @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..664e56c --- /dev/null +++ b/.mxproject @@ -0,0 +1,25 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/stm32f1xx_it.c;Core/Src/stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Core/Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Core/Src/system_stm32f1xx.c;;; +HeaderPath=Drivers/STM32F1xx_HAL_Driver/Inc;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F1xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Inc/stm32f1xx_it.h +HeaderFiles#1=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Inc/stm32f1xx_hal_conf.h +HeaderFiles#2=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Src/stm32f1xx_it.c +SourceFiles#1=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Src/stm32f1xx_hal_msp.c +SourceFiles#2=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/Core/Src +SourceFiles=; + diff --git a/.project b/.project new file mode 100644 index 0000000..754db7a --- /dev/null +++ b/.project @@ -0,0 +1,32 @@ + + + m3s + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..cfe68da --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..2e279ce --- /dev/null +++ b/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,74 @@ +com.st.stm32cube.ide.mcu.ide.oss.source.checker.libnano.problem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Float formatting support\\")"} +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=-Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")",checkMacro\=>true} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return value not evaluated\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol shadowing\\")",paramFuncParameters\=>true} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/.settings/org.eclipse.cdt.core.prefs b/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..c8ec5df --- /dev/null +++ b/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,6 @@ +doxygen/doxygen_new_line_after_brief=true +doxygen/doxygen_use_brief_tag=false +doxygen/doxygen_use_javadoc_tags=true +doxygen/doxygen_use_pre_tag=false +doxygen/doxygen_use_structural_commands=false +eclipse.preferences.version=1 diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..9f0c098 --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=GB2312 diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..767ab1b --- /dev/null +++ b/.settings/stm32cubeide.project.prefs @@ -0,0 +1,4 @@ +66BE74F758C12D739921AEA421D593D3=3 +8DF89ED150041C4CBC7CB9A9CAA90856=E458F13A42239457B89B956144879229 +DC22A860405A8BF2F2C095E5B6529F12=E458F13A42239457B89B956144879229 +eclipse.preferences.version=1 diff --git a/Core/Inc/main.h b/Core/Inc/main.h index e09b4d3..4de2e32 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -58,6 +58,8 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ +#define LCD_BL_Pin GPIO_PIN_0 +#define LCD_BL_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/Core/Inc/stm32f1xx_hal_conf.h b/Core/Inc/stm32f1xx_hal_conf.h index 5d9f0b3..cef193b 100644 --- a/Core/Inc/stm32f1xx_hal_conf.h +++ b/Core/Inc/stm32f1xx_hal_conf.h @@ -44,7 +44,7 @@ /*#define HAL_DMA_MODULE_ENABLED */ /*#define HAL_ETH_MODULE_ENABLED */ /*#define HAL_FLASH_MODULE_ENABLED */ -/*#define HAL_GPIO_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED /*#define HAL_I2C_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */ @@ -62,7 +62,7 @@ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SRAM_MODULE_ENABLED /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ diff --git a/Core/Src/main.c b/Core/Src/main.c index d6dc526..93452c2 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -22,7 +22,7 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ - +#include "Main_APP.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -40,6 +40,7 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +SRAM_HandleTypeDef hsram1; /* USER CODE BEGIN PV */ @@ -47,6 +48,8 @@ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_FSMC_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -83,8 +86,10 @@ int main(void) /* USER CODE END SysInit */ /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FSMC_Init(); /* USER CODE BEGIN 2 */ - + main_app(); /* USER CODE END 2 */ /* Infinite loop */ @@ -110,10 +115,13 @@ void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -122,17 +130,101 @@ void SystemClock_Config(void) */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } } +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : LCD_BL_Pin */ + GPIO_InitStruct.Pin = LCD_BL_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); + +} + +/* FSMC initialization function */ +static void MX_FSMC_Init(void) +{ + + /* USER CODE BEGIN FSMC_Init 0 */ + + /* USER CODE END FSMC_Init 0 */ + + FSMC_NORSRAM_TimingTypeDef Timing = {0}; + + /* USER CODE BEGIN FSMC_Init 1 */ + + /* USER CODE END FSMC_Init 1 */ + + /** Perform the SRAM1 memory initialization sequence + */ + hsram1.Instance = FSMC_NORSRAM_DEVICE; + hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + /* hsram1.Init */ + hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; + hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; + hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; + hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + /* Timing */ + Timing.AddressSetupTime = 0; + Timing.AddressHoldTime = 15; + Timing.DataSetupTime = 1; + Timing.BusTurnAroundDuration = 0; + Timing.CLKDivision = 16; + Timing.DataLatency = 17; + Timing.AccessMode = FSMC_ACCESS_MODE_A; + /* ExtTiming */ + + if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) + { + Error_Handler( ); + } + + /** Disconnect NADV + */ + + __HAL_AFIO_FSMCNADV_DISCONNECTED(); + + /* USER CODE BEGIN FSMC_Init 2 */ + + /* USER CODE END FSMC_Init 2 */ +} + /* USER CODE BEGIN 4 */ /* USER CODE END 4 */ diff --git a/Core/Src/stm32f1xx_hal_msp.c b/Core/Src/stm32f1xx_hal_msp.c index dda3977..cfd4af4 100644 --- a/Core/Src/stm32f1xx_hal_msp.c +++ b/Core/Src/stm32f1xx_hal_msp.c @@ -81,6 +81,137 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +static uint32_t FSMC_Initialized = 0; + +static void HAL_FSMC_MspInit(void){ + /* USER CODE BEGIN FSMC_MspInit 0 */ + + /* USER CODE END FSMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + if (FSMC_Initialized) { + return; + } + FSMC_Initialized = 1; + + /* Peripheral clock enable */ + __HAL_RCC_FSMC_CLK_ENABLE(); + + /** FSMC GPIO Configuration + PG0 ------> FSMC_A10 + PE7 ------> FSMC_D4 + PE8 ------> FSMC_D5 + PE9 ------> FSMC_D6 + PE10 ------> FSMC_D7 + PE11 ------> FSMC_D8 + PE12 ------> FSMC_D9 + PE13 ------> FSMC_D10 + PE14 ------> FSMC_D11 + PE15 ------> FSMC_D12 + PD8 ------> FSMC_D13 + PD9 ------> FSMC_D14 + PD10 ------> FSMC_D15 + PD14 ------> FSMC_D0 + PD15 ------> FSMC_D1 + PD0 ------> FSMC_D2 + PD1 ------> FSMC_D3 + PD4 ------> FSMC_NOE + PD5 ------> FSMC_NWE + PG12 ------> FSMC_NE4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 + |GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN FSMC_MspInit 1 */ + + /* USER CODE END FSMC_MspInit 1 */ +} + +void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ + /* USER CODE BEGIN SRAM_MspInit 0 */ + + /* USER CODE END SRAM_MspInit 0 */ + HAL_FSMC_MspInit(); + /* USER CODE BEGIN SRAM_MspInit 1 */ + + /* USER CODE END SRAM_MspInit 1 */ +} + +static uint32_t FSMC_DeInitialized = 0; + +static void HAL_FSMC_MspDeInit(void){ + /* USER CODE BEGIN FSMC_MspDeInit 0 */ + + /* USER CODE END FSMC_MspDeInit 0 */ + if (FSMC_DeInitialized) { + return; + } + FSMC_DeInitialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FSMC_CLK_DISABLE(); + + /** FSMC GPIO Configuration + PG0 ------> FSMC_A10 + PE7 ------> FSMC_D4 + PE8 ------> FSMC_D5 + PE9 ------> FSMC_D6 + PE10 ------> FSMC_D7 + PE11 ------> FSMC_D8 + PE12 ------> FSMC_D9 + PE13 ------> FSMC_D10 + PE14 ------> FSMC_D11 + PE15 ------> FSMC_D12 + PD8 ------> FSMC_D13 + PD9 ------> FSMC_D14 + PD10 ------> FSMC_D15 + PD14 ------> FSMC_D0 + PD15 ------> FSMC_D1 + PD0 ------> FSMC_D2 + PD1 ------> FSMC_D3 + PD4 ------> FSMC_NOE + PD5 ------> FSMC_NWE + PG12 ------> FSMC_NE4 + */ + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 + |GPIO_PIN_5); + + /* USER CODE BEGIN FSMC_MspDeInit 1 */ + + /* USER CODE END FSMC_MspDeInit 1 */ +} + +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){ + /* USER CODE BEGIN SRAM_MspDeInit 0 */ + + /* USER CODE END SRAM_MspDeInit 0 */ + HAL_FSMC_MspDeInit(); + /* USER CODE BEGIN SRAM_MspDeInit 1 */ + + /* USER CODE END SRAM_MspDeInit 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d new file mode 100644 index 0000000..b700b83 --- /dev/null +++ b/Debug/Core/Src/main.d @@ -0,0 +1,78 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \ + /Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/SW_APPs/Main_APP.h + +../Core/Inc/main.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: + +/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/SW_APPs/Main_APP.h: diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su new file mode 100644 index 0000000..02c7dfe --- /dev/null +++ b/Debug/Core/Src/main.su @@ -0,0 +1,5 @@ +main.c:66:5:main 8 static +main.c:110:6:SystemClock_Config 72 static +main.c:149:13:MX_GPIO_Init 40 static +main.c:172:13:MX_FSMC_Init 40 static +main.c:236:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Debug/Core/Src/stm32f1xx_hal_msp.d b/Debug/Core/Src/stm32f1xx_hal_msp.d new file mode 100644 index 0000000..515a1a9 --- /dev/null +++ b/Debug/Core/Src/stm32f1xx_hal_msp.d @@ -0,0 +1,75 @@ +Core/Src/stm32f1xx_hal_msp.o: ../Core/Src/stm32f1xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Core/Inc/main.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Core/Src/stm32f1xx_hal_msp.su b/Debug/Core/Src/stm32f1xx_hal_msp.su new file mode 100644 index 0000000..4ba6db9 --- /dev/null +++ b/Debug/Core/Src/stm32f1xx_hal_msp.su @@ -0,0 +1,5 @@ +stm32f1xx_hal_msp.c:64:6:HAL_MspInit 24 static +stm32f1xx_hal_msp.c:86:13:HAL_FSMC_MspInit 32 static +stm32f1xx_hal_msp.c:145:6:HAL_SRAM_MspInit 16 static +stm32f1xx_hal_msp.c:157:13:HAL_FSMC_MspDeInit 8 static +stm32f1xx_hal_msp.c:205:6:HAL_SRAM_MspDeInit 16 static diff --git a/Debug/Core/Src/stm32f1xx_it.d b/Debug/Core/Src/stm32f1xx_it.d new file mode 100644 index 0000000..8c68328 --- /dev/null +++ b/Debug/Core/Src/stm32f1xx_it.d @@ -0,0 +1,78 @@ +Core/Src/stm32f1xx_it.o: ../Core/Src/stm32f1xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h \ + ../Core/Inc/stm32f1xx_it.h + +../Core/Inc/main.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: + +../Core/Inc/stm32f1xx_it.h: diff --git a/Debug/Core/Src/stm32f1xx_it.su b/Debug/Core/Src/stm32f1xx_it.su new file mode 100644 index 0000000..c0a6d67 --- /dev/null +++ b/Debug/Core/Src/stm32f1xx_it.su @@ -0,0 +1,9 @@ +stm32f1xx_it.c:70:6:NMI_Handler 4 static +stm32f1xx_it.c:85:6:HardFault_Handler 4 static +stm32f1xx_it.c:100:6:MemManage_Handler 4 static +stm32f1xx_it.c:115:6:BusFault_Handler 4 static +stm32f1xx_it.c:130:6:UsageFault_Handler 4 static +stm32f1xx_it.c:145:6:SVC_Handler 4 static +stm32f1xx_it.c:158:6:DebugMon_Handler 4 static +stm32f1xx_it.c:171:6:PendSV_Handler 4 static +stm32f1xx_it.c:184:6:SysTick_Handler 8 static diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..d9be193 --- /dev/null +++ b/Debug/Core/Src/subdir.mk @@ -0,0 +1,35 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/main.c \ +../Core/Src/stm32f1xx_hal_msp.c \ +../Core/Src/stm32f1xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f1xx.c + +OBJS += \ +./Core/Src/main.o \ +./Core/Src/stm32f1xx_hal_msp.o \ +./Core/Src/stm32f1xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f1xx.o + +C_DEPS += \ +./Core/Src/main.d \ +./Core/Src/stm32f1xx_hal_msp.d \ +./Core/Src/stm32f1xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f1xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F103xE -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/SW_APPs" -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/HW_Devices" -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..8667c70 --- /dev/null +++ b/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..8afbb58 --- /dev/null +++ b/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +syscalls.c:45:6:initialise_monitor_handles 4 static +syscalls.c:49:5:_getpid 4 static +syscalls.c:54:5:_kill 16 static +syscalls.c:60:6:_exit 16 static +syscalls.c:66:27:_read 32 static +syscalls.c:78:27:_write 32 static +syscalls.c:89:5:_close 16 static +syscalls.c:95:5:_fstat 16 static +syscalls.c:101:5:_isatty 16 static +syscalls.c:106:5:_lseek 24 static +syscalls.c:111:5:_open 12 static +syscalls.c:117:5:_wait 16 static +syscalls.c:123:5:_unlink 16 static +syscalls.c:129:5:_times 16 static +syscalls.c:134:5:_stat 16 static +syscalls.c:140:5:_link 16 static +syscalls.c:146:5:_fork 8 static +syscalls.c:152:5:_execve 24 static diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..74fecf9 --- /dev/null +++ b/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..4474c68 --- /dev/null +++ b/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +sysmem.c:54:7:_sbrk 32 static diff --git a/Debug/Core/Src/system_stm32f1xx.d b/Debug/Core/Src/system_stm32f1xx.d new file mode 100644 index 0000000..53aefc0 --- /dev/null +++ b/Debug/Core/Src/system_stm32f1xx.d @@ -0,0 +1,73 @@ +Core/Src/system_stm32f1xx.o: ../Core/Src/system_stm32f1xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Core/Src/system_stm32f1xx.su b/Debug/Core/Src/system_stm32f1xx.su new file mode 100644 index 0000000..967fb21 --- /dev/null +++ b/Debug/Core/Src/system_stm32f1xx.su @@ -0,0 +1,2 @@ +system_stm32f1xx.c:176:6:SystemInit 4 static +system_stm32f1xx.c:225:6:SystemCoreClockUpdate 24 static diff --git a/Debug/Core/Startup/startup_stm32f103zetx.d b/Debug/Core/Startup/startup_stm32f103zetx.d new file mode 100644 index 0000000..b5ba0bc --- /dev/null +++ b/Debug/Core/Startup/startup_stm32f103zetx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f103zetx.o: \ + ../Core/Startup/startup_stm32f103zetx.s diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..c8f5c7c --- /dev/null +++ b/Debug/Core/Startup/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f103zetx.s + +OBJS += \ +./Core/Startup/startup_stm32f103zetx.o + +S_DEPS += \ +./Core/Startup/startup_stm32f103zetx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m3 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d new file mode 100644 index 0000000..f82985c --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su new file mode 100644 index 0000000..b50d33d --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su @@ -0,0 +1,25 @@ +stm32f1xx_hal.c:142:19:HAL_Init 8 static +stm32f1xx_hal.c:175:19:HAL_DeInit 8 static +stm32f1xx_hal.c:200:13:HAL_MspInit 4 static +stm32f1xx_hal.c:211:13:HAL_MspDeInit 4 static +stm32f1xx_hal.c:234:26:HAL_InitTick 16 static +stm32f1xx_hal.c:293:13:HAL_IncTick 4 static +stm32f1xx_hal.c:304:17:HAL_GetTick 4 static +stm32f1xx_hal.c:313:10:HAL_GetTickPrio 4 static +stm32f1xx_hal.c:322:19:HAL_SetTickFreq 24 static +stm32f1xx_hal.c:354:21:HAL_GetTickFreq 4 static +stm32f1xx_hal.c:370:13:HAL_Delay 24 static +stm32f1xx_hal.c:396:13:HAL_SuspendTick 4 static +stm32f1xx_hal.c:412:13:HAL_ResumeTick 4 static +stm32f1xx_hal.c:422:10:HAL_GetHalVersion 4 static +stm32f1xx_hal.c:438:10:HAL_GetREVID 4 static +stm32f1xx_hal.c:454:10:HAL_GetDEVID 4 static +stm32f1xx_hal.c:463:10:HAL_GetUIDw0 4 static +stm32f1xx_hal.c:472:10:HAL_GetUIDw1 4 static +stm32f1xx_hal.c:481:10:HAL_GetUIDw2 4 static +stm32f1xx_hal.c:490:6:HAL_DBGMCU_EnableDBGSleepMode 4 static +stm32f1xx_hal.c:506:6:HAL_DBGMCU_DisableDBGSleepMode 4 static +stm32f1xx_hal.c:536:6:HAL_DBGMCU_EnableDBGStopMode 4 static +stm32f1xx_hal.c:552:6:HAL_DBGMCU_DisableDBGStopMode 4 static +stm32f1xx_hal.c:568:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static +stm32f1xx_hal.c:584:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d new file mode 100644 index 0000000..8a9a3ec --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su new file mode 100644 index 0000000..634528a --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su @@ -0,0 +1,29 @@ +core_cm3.h:1480:22:__NVIC_SetPriorityGrouping 24 static +core_cm3.h:1499:26:__NVIC_GetPriorityGrouping 4 static +core_cm3.h:1511:22:__NVIC_EnableIRQ 16 static +core_cm3.h:1547:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +core_cm3.h:1566:26:__NVIC_GetPendingIRQ 16 static +core_cm3.h:1585:22:__NVIC_SetPendingIRQ 16 static +core_cm3.h:1600:22:__NVIC_ClearPendingIRQ 16 static +core_cm3.h:1617:26:__NVIC_GetActive 16 static +core_cm3.h:1639:22:__NVIC_SetPriority 16 static +core_cm3.h:1661:26:__NVIC_GetPriority 16 static +core_cm3.h:1686:26:NVIC_EncodePriority 40 static +core_cm3.h:1713:22:NVIC_DecodePriority 40 static +core_cm3.h:1762:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +core_cm3.h:1834:26:SysTick_Config 16 static +stm32f1xx_hal_cortex.c:143:6:HAL_NVIC_SetPriorityGrouping 16 static +stm32f1xx_hal_cortex.c:165:6:HAL_NVIC_SetPriority 32 static +stm32f1xx_hal_cortex.c:187:6:HAL_NVIC_EnableIRQ 16 static +stm32f1xx_hal_cortex.c:203:6:HAL_NVIC_DisableIRQ 16 static +stm32f1xx_hal_cortex.c:216:6:HAL_NVIC_SystemReset 8 static +stm32f1xx_hal_cortex.c:229:10:HAL_SYSTICK_Config 16 static +stm32f1xx_hal_cortex.c:344:10:HAL_NVIC_GetPriorityGrouping 8 static +stm32f1xx_hal_cortex.c:371:6:HAL_NVIC_GetPriority 24 static +stm32f1xx_hal_cortex.c:386:6:HAL_NVIC_SetPendingIRQ 16 static +stm32f1xx_hal_cortex.c:404:10:HAL_NVIC_GetPendingIRQ 16 static +stm32f1xx_hal_cortex.c:420:6:HAL_NVIC_ClearPendingIRQ 16 static +stm32f1xx_hal_cortex.c:437:10:HAL_NVIC_GetActive 16 static +stm32f1xx_hal_cortex.c:454:6:HAL_SYSTICK_CLKSourceConfig 16 static +stm32f1xx_hal_cortex.c:472:6:HAL_SYSTICK_IRQHandler 8 static +stm32f1xx_hal_cortex.c:481:13:HAL_SYSTICK_Callback 4 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d new file mode 100644 index 0000000..e948c36 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su new file mode 100644 index 0000000..5c24809 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su @@ -0,0 +1,13 @@ +stm32f1xx_hal_dma.c:143:19:HAL_DMA_Init 24 static +stm32f1xx_hal_dma.c:220:19:HAL_DMA_DeInit 16 static +stm32f1xx_hal_dma.c:319:19:HAL_DMA_Start 32 static +stm32f1xx_hal_dma.c:362:19:HAL_DMA_Start_IT 32 static +stm32f1xx_hal_dma.c:416:19:HAL_DMA_Abort 24 static +stm32f1xx_hal_dma.c:457:19:HAL_DMA_Abort_IT 24 static +stm32f1xx_hal_dma.c:502:19:HAL_DMA_PollForTransfer 32 static +stm32f1xx_hal_dma.c:603:6:HAL_DMA_IRQHandler 24 static +stm32f1xx_hal_dma.c:693:19:HAL_DMA_RegisterCallback 32 static +stm32f1xx_hal_dma.c:744:19:HAL_DMA_UnRegisterCallback 24 static +stm32f1xx_hal_dma.c:820:22:HAL_DMA_GetState 16 static +stm32f1xx_hal_dma.c:832:10:HAL_DMA_GetError 16 static +stm32f1xx_hal_dma.c:858:13:DMA_SetConfig 24 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d new file mode 100644 index 0000000..856e0d6 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su new file mode 100644 index 0000000..f6f8c99 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su @@ -0,0 +1,9 @@ +stm32f1xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 32 static +stm32f1xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 32 static +stm32f1xx_hal_exti.c:317:19:HAL_EXTI_ClearConfigLine 32 static +stm32f1xx_hal_exti.c:370:19:HAL_EXTI_RegisterCallback 32 static +stm32f1xx_hal_exti.c:395:19:HAL_EXTI_GetHandle 16 static +stm32f1xx_hal_exti.c:435:6:HAL_EXTI_IRQHandler 24 static +stm32f1xx_hal_exti.c:467:10:HAL_EXTI_GetPending 32 static +stm32f1xx_hal_exti.c:499:6:HAL_EXTI_ClearPending 24 static +stm32f1xx_hal_exti.c:523:6:HAL_EXTI_GenerateSWI 24 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d new file mode 100644 index 0000000..09f0007 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su new file mode 100644 index 0000000..9238093 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su @@ -0,0 +1,14 @@ +stm32f1xx_hal_flash.c:168:19:HAL_FLASH_Program 48 static +stm32f1xx_hal_flash.c:267:19:HAL_FLASH_Program_IT 32 static +stm32f1xx_hal_flash.c:332:6:HAL_FLASH_IRQHandler 16 static +stm32f1xx_hal_flash.c:606:13:HAL_FLASH_EndOfOperationCallback 16 static +stm32f1xx_hal_flash.c:624:13:HAL_FLASH_OperationErrorCallback 16 static +stm32f1xx_hal_flash.c:657:19:HAL_FLASH_Unlock 16 static +stm32f1xx_hal_flash.c:695:19:HAL_FLASH_Lock 4 static +stm32f1xx_hal_flash.c:712:19:HAL_FLASH_OB_Unlock 4 static +stm32f1xx_hal_flash.c:732:19:HAL_FLASH_OB_Lock 4 static +stm32f1xx_hal_flash.c:745:6:HAL_FLASH_OB_Launch 8 static +stm32f1xx_hal_flash.c:774:10:HAL_FLASH_GetError 4 static +stm32f1xx_hal_flash.c:797:13:FLASH_Program_HalfWord 16 static +stm32f1xx_hal_flash.c:826:19:FLASH_WaitForLastOperation 24 static +stm32f1xx_hal_flash.c:914:13:FLASH_SetErrorCode 16 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d new file mode 100644 index 0000000..24db26d --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su new file mode 100644 index 0000000..354b9bf --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su @@ -0,0 +1,16 @@ +stm32f1xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase 24 static +stm32f1xx_hal_flash_ex.c:319:19:HAL_FLASHEx_Erase_IT 24 static +stm32f1xx_hal_flash_ex.c:397:19:HAL_FLASHEx_OBErase 16 static +stm32f1xx_hal_flash_ex.c:446:19:HAL_FLASHEx_OBProgram 24 static +stm32f1xx_hal_flash_ex.c:527:6:HAL_FLASHEx_OBGetConfig 16 static +stm32f1xx_hal_flash_ex.c:549:10:HAL_FLASHEx_OBGetUserData 24 static +stm32f1xx_hal_flash_ex.c:595:13:FLASH_MassErase 16 static +stm32f1xx_hal_flash_ex.c:644:26:FLASH_OB_EnableWRP 32 static +stm32f1xx_hal_flash_ex.c:767:26:FLASH_OB_DisableWRP 32 static +stm32f1xx_hal_flash_ex.c:886:26:FLASH_OB_RDP_LevelConfig 24 static +stm32f1xx_hal_flash_ex.c:937:26:FLASH_OB_UserConfig 24 static +stm32f1xx_hal_flash_ex.c:988:26:FLASH_OB_ProgramData 24 static +stm32f1xx_hal_flash_ex.c:1021:17:FLASH_OB_GetWRP 4 static +stm32f1xx_hal_flash_ex.c:1034:17:FLASH_OB_GetRDP 16 static +stm32f1xx_hal_flash_ex.c:1060:16:FLASH_OB_GetUser 4 static +stm32f1xx_hal_flash_ex.c:1089:6:FLASH_PageErase 16 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d new file mode 100644 index 0000000..f1e1f59 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su new file mode 100644 index 0000000..27b52b4 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su @@ -0,0 +1,8 @@ +stm32f1xx_hal_gpio.c:178:6:HAL_GPIO_Init 48 static +stm32f1xx_hal_gpio.c:351:6:HAL_GPIO_DeInit 40 static +stm32f1xx_hal_gpio.c:431:15:HAL_GPIO_ReadPin 24 static +stm32f1xx_hal_gpio.c:465:6:HAL_GPIO_WritePin 16 static +stm32f1xx_hal_gpio.c:487:6:HAL_GPIO_TogglePin 24 static +stm32f1xx_hal_gpio.c:511:19:HAL_GPIO_LockPin 24 static +stm32f1xx_hal_gpio.c:546:6:HAL_GPIO_EXTI_IRQHandler 16 static +stm32f1xx_hal_gpio.c:561:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d new file mode 100644 index 0000000..fd58c87 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su new file mode 100644 index 0000000..87a538a --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su @@ -0,0 +1,3 @@ +stm32f1xx_hal_gpio_ex.c:81:6:HAL_GPIOEx_ConfigEventout 16 static +stm32f1xx_hal_gpio_ex.c:95:6:HAL_GPIOEx_EnableEventout 4 static +stm32f1xx_hal_gpio_ex.c:104:6:HAL_GPIOEx_DisableEventout 4 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d new file mode 100644 index 0000000..f99c505 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su new file mode 100644 index 0000000..3a73422 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su @@ -0,0 +1,18 @@ +stm32f1xx_hal_pwr.c:117:13:PWR_OverloadWfe 4 static,ignoring_inline_asm +stm32f1xx_hal_pwr.c:156:6:HAL_PWR_DeInit 4 static +stm32f1xx_hal_pwr.c:169:6:HAL_PWR_EnableBkUpAccess 4 static +stm32f1xx_hal_pwr.c:182:6:HAL_PWR_DisableBkUpAccess 4 static +stm32f1xx_hal_pwr.c:316:6:HAL_PWR_ConfigPVD 16 static +stm32f1xx_hal_pwr.c:359:6:HAL_PWR_EnablePVD 4 static +stm32f1xx_hal_pwr.c:369:6:HAL_PWR_DisablePVD 4 static +stm32f1xx_hal_pwr.c:382:6:HAL_PWR_EnableWakeUpPin 24 static,ignoring_inline_asm +stm32f1xx_hal_pwr.c:397:6:HAL_PWR_DisableWakeUpPin 24 static,ignoring_inline_asm +stm32f1xx_hal_pwr.c:417:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +stm32f1xx_hal_pwr.c:463:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm +stm32f1xx_hal_pwr.c:503:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +stm32f1xx_hal_pwr.c:528:6:HAL_PWR_EnableSleepOnExit 4 static +stm32f1xx_hal_pwr.c:541:6:HAL_PWR_DisableSleepOnExit 4 static +stm32f1xx_hal_pwr.c:554:6:HAL_PWR_EnableSEVOnPend 4 static +stm32f1xx_hal_pwr.c:567:6:HAL_PWR_DisableSEVOnPend 4 static +stm32f1xx_hal_pwr.c:580:6:HAL_PWR_PVD_IRQHandler 8 static +stm32f1xx_hal_pwr.c:597:13:HAL_PWR_PVDCallback 4 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d new file mode 100644 index 0000000..6ca99b2 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su new file mode 100644 index 0000000..aa05c10 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su @@ -0,0 +1,15 @@ +stm32f1xx_hal_rcc.c:202:19:HAL_RCC_DeInit 16 static +stm32f1xx_hal_rcc.c:347:19:HAL_RCC_OscConfig 32 static +stm32f1xx_hal_rcc.c:813:19:HAL_RCC_ClockConfig 24 static +stm32f1xx_hal_rcc.c:1002:6:HAL_RCC_MCOConfig 48 static +stm32f1xx_hal_rcc.c:1039:6:HAL_RCC_EnableCSS 4 static +stm32f1xx_hal_rcc.c:1048:6:HAL_RCC_DisableCSS 4 static +stm32f1xx_hal_rcc.c:1082:10:HAL_RCC_GetSysClockFreq 48 static +stm32f1xx_hal_rcc.c:1176:10:HAL_RCC_GetHCLKFreq 4 static +stm32f1xx_hal_rcc.c:1187:10:HAL_RCC_GetPCLK1Freq 8 static +stm32f1xx_hal_rcc.c:1199:10:HAL_RCC_GetPCLK2Freq 8 static +stm32f1xx_hal_rcc.c:1212:6:HAL_RCC_GetOscConfig 16 static +stm32f1xx_hal_rcc.c:1312:6:HAL_RCC_GetClockConfig 16 static +stm32f1xx_hal_rcc.c:1347:6:HAL_RCC_NMI_IRQHandler 8 static +stm32f1xx_hal_rcc.c:1365:13:RCC_Delay 24 static,ignoring_inline_asm +stm32f1xx_hal_rcc.c:1379:13:HAL_RCC_CSSCallback 4 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d new file mode 100644 index 0000000..5044612 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su new file mode 100644 index 0000000..dbe5d7b --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su @@ -0,0 +1,3 @@ +stm32f1xx_hal_rcc_ex.c:100:19:HAL_RCCEx_PeriphCLKConfig 32 static +stm32f1xx_hal_rcc_ex.c:294:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +stm32f1xx_hal_rcc_ex.c:387:10:HAL_RCCEx_GetPeriphCLKFreq 64 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.d new file mode 100644 index 0000000..8c49bad --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.su new file mode 100644 index 0000000..ea501b9 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.su @@ -0,0 +1,20 @@ +stm32f1xx_hal_sram.c:168:19:HAL_SRAM_Init 24 static +stm32f1xx_hal_sram.c:223:19:HAL_SRAM_DeInit 16 static +stm32f1xx_hal_sram.c:256:13:HAL_SRAM_MspInit 16 static +stm32f1xx_hal_sram.c:272:13:HAL_SRAM_MspDeInit 16 static +stm32f1xx_hal_sram.c:288:13:HAL_SRAM_DMA_XferCpltCallback 16 static +stm32f1xx_hal_sram.c:304:13:HAL_SRAM_DMA_XferErrorCallback 16 static +stm32f1xx_hal_sram.c:341:19:HAL_SRAM_Read_8b 40 static +stm32f1xx_hal_sram.c:389:19:HAL_SRAM_Write_8b 40 static +stm32f1xx_hal_sram.c:436:19:HAL_SRAM_Read_16b 40 static +stm32f1xx_hal_sram.c:496:19:HAL_SRAM_Write_16b 40 static +stm32f1xx_hal_sram.c:555:19:HAL_SRAM_Read_32b 40 static +stm32f1xx_hal_sram.c:603:19:HAL_SRAM_Write_32b 40 static +stm32f1xx_hal_sram.c:650:19:HAL_SRAM_Read_DMA 32 static +stm32f1xx_hal_sram.c:699:19:HAL_SRAM_Write_DMA 32 static +stm32f1xx_hal_sram.c:934:19:HAL_SRAM_WriteOperation_Enable 16 static +stm32f1xx_hal_sram.c:968:19:HAL_SRAM_WriteOperation_Disable 16 static +stm32f1xx_hal_sram.c:1021:23:HAL_SRAM_GetState 16 static +stm32f1xx_hal_sram.c:1039:13:SRAM_DMACplt 24 static +stm32f1xx_hal_sram.c:1061:13:SRAM_DMACpltProt 24 static +stm32f1xx_hal_sram.c:1083:13:SRAM_DMAError 24 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d new file mode 100644 index 0000000..4c54ad6 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d new file mode 100644 index 0000000..b9015cc --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.d b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.d new file mode 100644 index 0000000..fbfd944 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.d @@ -0,0 +1,74 @@ +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.o: \ + ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.su b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.su new file mode 100644 index 0000000..61234e3 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.su @@ -0,0 +1,18 @@ +stm32f1xx_ll_fsmc.c:207:20:FSMC_NORSRAM_Init 32 static +stm32f1xx_ll_fsmc.c:290:19:FSMC_NORSRAM_DeInit 24 static +stm32f1xx_ll_fsmc.c:327:19:FSMC_NORSRAM_Timing_Init 24 static +stm32f1xx_ll_fsmc.c:366:19:FSMC_NORSRAM_Extended_Timing_Init 24 static +stm32f1xx_ll_fsmc.c:438:19:FSMC_NORSRAM_WriteOperation_Enable 16 static +stm32f1xx_ll_fsmc.c:456:19:FSMC_NORSRAM_WriteOperation_Disable 16 static +stm32f1xx_ll_fsmc.c:528:19:FSMC_NAND_Init 16 static +stm32f1xx_ll_fsmc.c:575:19:FSMC_NAND_CommonSpace_Timing_Init 24 static +stm32f1xx_ll_fsmc.c:615:19:FSMC_NAND_AttributeSpace_Timing_Init 24 static +stm32f1xx_ll_fsmc.c:653:19:FSMC_NAND_DeInit 16 static +stm32f1xx_ll_fsmc.c:710:19:FSMC_NAND_ECC_Enable 16 static +stm32f1xx_ll_fsmc.c:736:19:FSMC_NAND_ECC_Disable 16 static +stm32f1xx_ll_fsmc.c:763:19:FSMC_NAND_GetECC 32 static +stm32f1xx_ll_fsmc.c:856:19:FSMC_PCCARD_Init 16 static +stm32f1xx_ll_fsmc.c:889:19:FSMC_PCCARD_CommonSpace_Timing_Init 16 static +stm32f1xx_ll_fsmc.c:918:19:FSMC_PCCARD_AttributeSpace_Timing_Init 16 static +stm32f1xx_ll_fsmc.c:947:19:FSMC_PCCARD_IOSpace_Timing_Init 16 static +stm32f1xx_ll_fsmc.c:974:19:FSMC_PCCARD_DeInit 16 static diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..2ea848c --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,62 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c + +OBJS += \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.o + +C_DEPS += \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F1xx_HAL_Driver/Src/%.o: ../Drivers/STM32F1xx_HAL_Driver/Src/%.c Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F103xE -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/SW_APPs" -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/HW_Devices" -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/HW_Devices/LCD.d b/Debug/HW_Devices/LCD.d new file mode 100644 index 0000000..b75de1a --- /dev/null +++ b/Debug/HW_Devices/LCD.d @@ -0,0 +1,77 @@ +HW_Devices/LCD.o: ../HW_Devices/LCD.c ../HW_Devices/LCD.h \ + ../Core/Inc/main.h ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +../HW_Devices/LCD.h: + +../Core/Inc/main.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/HW_Devices/LCD.su b/Debug/HW_Devices/LCD.su new file mode 100644 index 0000000..15174f3 --- /dev/null +++ b/Debug/HW_Devices/LCD.su @@ -0,0 +1,22 @@ +LCD.c:13:6:LCD_WR_REG 16 static +LCD.c:19:6:LCD_WR_DATA 16 static +LCD.c:25:10:LCD_RD_DATA 4 static +LCD.c:32:6:LCD_WriteReg 16 static +LCD.c:40:10:LCD_ReadReg 16 static +LCD.c:250:6:LCD_DisplayOn 8 static +LCD.c:256:6:LCD_DisplayOff 8 static +LCD.c:266:6:LCD_Scan_Dir 24 static +LCD.c:384:6:LCD_Display_Dir 16 static +LCD.c:449:6:LCDx_Init 8 static +LCD.c:532:6:LCD_SetCursor 16 static +LCD.c:562:6:LCD_Fast_DrawPoint 16 static +LCD.c:593:6:LCD_set_dot 16 static +LCD.c:602:6:LCD_Clear 24 static +LCD.c:626:6:LCD_Fill 40 static +LCD.c:659:6:LCD_Color_Fill 32 static +LCD.c:680:10:LCD_BGR2RGB 24 static +LCD.c:692:10:LCD_ReadPoint 24 static +LCD.c:720:6:LCD_DrawLine 64 static +LCD.c:758:6:Draw_Circle 40 static +LCD.c:791:6:LCD_ShowChar 32 static +LCD.c:829:6:LCD_ShowString 40 static diff --git a/Debug/HW_Devices/subdir.mk b/Debug/HW_Devices/subdir.mk new file mode 100644 index 0000000..3beb896 --- /dev/null +++ b/Debug/HW_Devices/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../HW_Devices/LCD.c + +OBJS += \ +./HW_Devices/LCD.o + +C_DEPS += \ +./HW_Devices/LCD.d + + +# Each subdirectory must supply rules for building sources it contributes +HW_Devices/%.o: ../HW_Devices/%.c HW_Devices/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F103xE -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/SW_APPs" -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/HW_Devices" -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/SW_APPs/Main_APP.d b/Debug/SW_APPs/Main_APP.d new file mode 100644 index 0000000..9944cd0 --- /dev/null +++ b/Debug/SW_APPs/Main_APP.d @@ -0,0 +1,78 @@ +SW_APPs/Main_APP.o: ../SW_APPs/Main_APP.c \ + /Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/HW_Devices/LCD.h \ + ../Core/Inc/main.h ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h \ + ../Core/Inc/stm32f1xx_hal_conf.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h \ + ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h + +/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/HW_Devices/LCD.h: + +../Core/Inc/main.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: + +../Core/Inc/stm32f1xx_hal_conf.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h: + +../Drivers/CMSIS/Include/core_cm3.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h: + +../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h: diff --git a/Debug/SW_APPs/Main_APP.su b/Debug/SW_APPs/Main_APP.su new file mode 100644 index 0000000..da6fdaa --- /dev/null +++ b/Debug/SW_APPs/Main_APP.su @@ -0,0 +1 @@ +Main_APP.c:9:6:main_app 8 static diff --git a/Debug/SW_APPs/subdir.mk b/Debug/SW_APPs/subdir.mk new file mode 100644 index 0000000..a9e554f --- /dev/null +++ b/Debug/SW_APPs/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../SW_APPs/Main_APP.c + +OBJS += \ +./SW_APPs/Main_APP.o + +C_DEPS += \ +./SW_APPs/Main_APP.d + + +# Each subdirectory must supply rules for building sources it contributes +SW_APPs/%.o: ../SW_APPs/%.c SW_APPs/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F103xE -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/SW_APPs" -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/HW_Devices" -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/m3s.bin b/Debug/m3s.bin new file mode 100755 index 0000000..ec20944 Binary files /dev/null and b/Debug/m3s.bin differ diff --git a/Debug/m3s.list b/Debug/m3s.list new file mode 100644 index 0000000..ae98813 --- /dev/null +++ b/Debug/m3s.list @@ -0,0 +1,10462 @@ + +m3s.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001e4 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000503c 080001e8 080001e8 000101e8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000404 08005228 08005228 00015228 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800562c 0800562c 000201dc 2**0 + CONTENTS + 4 .ARM 00000000 0800562c 0800562c 000201dc 2**0 + CONTENTS + 5 .preinit_array 00000000 0800562c 0800562c 000201dc 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800562c 0800562c 0001562c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08005630 08005630 00015630 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 000001dc 20000000 08005634 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000094 200001dc 08005810 000201dc 2**2 + ALLOC + 10 ._user_heap_stack 00000600 20000270 08005810 00020270 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 000201dc 2**0 + CONTENTS, READONLY + 12 .debug_info 00007a5c 00000000 00000000 00020205 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00001aca 00000000 00000000 00027c61 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000708 00000000 00000000 00029730 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_ranges 00000620 00000000 00000000 00029e38 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 00019f1e 00000000 00000000 0002a458 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 000084ed 00000000 00000000 00044376 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 00092ef2 00000000 00000000 0004c863 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000053 00000000 00000000 000df755 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002a3c 00000000 00000000 000df7a8 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080001e8 <__do_global_dtors_aux>: + 80001e8: b510 push {r4, lr} + 80001ea: 4c05 ldr r4, [pc, #20] ; (8000200 <__do_global_dtors_aux+0x18>) + 80001ec: 7823 ldrb r3, [r4, #0] + 80001ee: b933 cbnz r3, 80001fe <__do_global_dtors_aux+0x16> + 80001f0: 4b04 ldr r3, [pc, #16] ; (8000204 <__do_global_dtors_aux+0x1c>) + 80001f2: b113 cbz r3, 80001fa <__do_global_dtors_aux+0x12> + 80001f4: 4804 ldr r0, [pc, #16] ; (8000208 <__do_global_dtors_aux+0x20>) + 80001f6: f3af 8000 nop.w + 80001fa: 2301 movs r3, #1 + 80001fc: 7023 strb r3, [r4, #0] + 80001fe: bd10 pop {r4, pc} + 8000200: 200001dc .word 0x200001dc + 8000204: 00000000 .word 0x00000000 + 8000208: 0800520c .word 0x0800520c + +0800020c : + 800020c: b508 push {r3, lr} + 800020e: 4b03 ldr r3, [pc, #12] ; (800021c ) + 8000210: b11b cbz r3, 800021a + 8000212: 4903 ldr r1, [pc, #12] ; (8000220 ) + 8000214: 4803 ldr r0, [pc, #12] ; (8000224 ) + 8000216: f3af 8000 nop.w + 800021a: bd08 pop {r3, pc} + 800021c: 00000000 .word 0x00000000 + 8000220: 200001e0 .word 0x200001e0 + 8000224: 0800520c .word 0x0800520c + +08000228 : + 8000228: 4603 mov r3, r0 + 800022a: f813 2b01 ldrb.w r2, [r3], #1 + 800022e: 2a00 cmp r2, #0 + 8000230: d1fb bne.n 800022a + 8000232: 1a18 subs r0, r3, r0 + 8000234: 3801 subs r0, #1 + 8000236: 4770 bx lr + +08000238 <__aeabi_drsub>: + 8000238: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 800023c: e002 b.n 8000244 <__adddf3> + 800023e: bf00 nop + +08000240 <__aeabi_dsub>: + 8000240: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + +08000244 <__adddf3>: + 8000244: b530 push {r4, r5, lr} + 8000246: ea4f 0441 mov.w r4, r1, lsl #1 + 800024a: ea4f 0543 mov.w r5, r3, lsl #1 + 800024e: ea94 0f05 teq r4, r5 + 8000252: bf08 it eq + 8000254: ea90 0f02 teqeq r0, r2 + 8000258: bf1f itttt ne + 800025a: ea54 0c00 orrsne.w ip, r4, r0 + 800025e: ea55 0c02 orrsne.w ip, r5, r2 + 8000262: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 8000266: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 800026a: f000 80e2 beq.w 8000432 <__adddf3+0x1ee> + 800026e: ea4f 5454 mov.w r4, r4, lsr #21 + 8000272: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 8000276: bfb8 it lt + 8000278: 426d neglt r5, r5 + 800027a: dd0c ble.n 8000296 <__adddf3+0x52> + 800027c: 442c add r4, r5 + 800027e: ea80 0202 eor.w r2, r0, r2 + 8000282: ea81 0303 eor.w r3, r1, r3 + 8000286: ea82 0000 eor.w r0, r2, r0 + 800028a: ea83 0101 eor.w r1, r3, r1 + 800028e: ea80 0202 eor.w r2, r0, r2 + 8000292: ea81 0303 eor.w r3, r1, r3 + 8000296: 2d36 cmp r5, #54 ; 0x36 + 8000298: bf88 it hi + 800029a: bd30 pophi {r4, r5, pc} + 800029c: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 80002a0: ea4f 3101 mov.w r1, r1, lsl #12 + 80002a4: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 80002a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 80002ac: d002 beq.n 80002b4 <__adddf3+0x70> + 80002ae: 4240 negs r0, r0 + 80002b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80002b4: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 80002b8: ea4f 3303 mov.w r3, r3, lsl #12 + 80002bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 80002c0: d002 beq.n 80002c8 <__adddf3+0x84> + 80002c2: 4252 negs r2, r2 + 80002c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 80002c8: ea94 0f05 teq r4, r5 + 80002cc: f000 80a7 beq.w 800041e <__adddf3+0x1da> + 80002d0: f1a4 0401 sub.w r4, r4, #1 + 80002d4: f1d5 0e20 rsbs lr, r5, #32 + 80002d8: db0d blt.n 80002f6 <__adddf3+0xb2> + 80002da: fa02 fc0e lsl.w ip, r2, lr + 80002de: fa22 f205 lsr.w r2, r2, r5 + 80002e2: 1880 adds r0, r0, r2 + 80002e4: f141 0100 adc.w r1, r1, #0 + 80002e8: fa03 f20e lsl.w r2, r3, lr + 80002ec: 1880 adds r0, r0, r2 + 80002ee: fa43 f305 asr.w r3, r3, r5 + 80002f2: 4159 adcs r1, r3 + 80002f4: e00e b.n 8000314 <__adddf3+0xd0> + 80002f6: f1a5 0520 sub.w r5, r5, #32 + 80002fa: f10e 0e20 add.w lr, lr, #32 + 80002fe: 2a01 cmp r2, #1 + 8000300: fa03 fc0e lsl.w ip, r3, lr + 8000304: bf28 it cs + 8000306: f04c 0c02 orrcs.w ip, ip, #2 + 800030a: fa43 f305 asr.w r3, r3, r5 + 800030e: 18c0 adds r0, r0, r3 + 8000310: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 8000314: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000318: d507 bpl.n 800032a <__adddf3+0xe6> + 800031a: f04f 0e00 mov.w lr, #0 + 800031e: f1dc 0c00 rsbs ip, ip, #0 + 8000322: eb7e 0000 sbcs.w r0, lr, r0 + 8000326: eb6e 0101 sbc.w r1, lr, r1 + 800032a: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 800032e: d31b bcc.n 8000368 <__adddf3+0x124> + 8000330: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 8000334: d30c bcc.n 8000350 <__adddf3+0x10c> + 8000336: 0849 lsrs r1, r1, #1 + 8000338: ea5f 0030 movs.w r0, r0, rrx + 800033c: ea4f 0c3c mov.w ip, ip, rrx + 8000340: f104 0401 add.w r4, r4, #1 + 8000344: ea4f 5244 mov.w r2, r4, lsl #21 + 8000348: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 800034c: f080 809a bcs.w 8000484 <__adddf3+0x240> + 8000350: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 8000354: bf08 it eq + 8000356: ea5f 0c50 movseq.w ip, r0, lsr #1 + 800035a: f150 0000 adcs.w r0, r0, #0 + 800035e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8000362: ea41 0105 orr.w r1, r1, r5 + 8000366: bd30 pop {r4, r5, pc} + 8000368: ea5f 0c4c movs.w ip, ip, lsl #1 + 800036c: 4140 adcs r0, r0 + 800036e: eb41 0101 adc.w r1, r1, r1 + 8000372: 3c01 subs r4, #1 + 8000374: bf28 it cs + 8000376: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 + 800037a: d2e9 bcs.n 8000350 <__adddf3+0x10c> + 800037c: f091 0f00 teq r1, #0 + 8000380: bf04 itt eq + 8000382: 4601 moveq r1, r0 + 8000384: 2000 moveq r0, #0 + 8000386: fab1 f381 clz r3, r1 + 800038a: bf08 it eq + 800038c: 3320 addeq r3, #32 + 800038e: f1a3 030b sub.w r3, r3, #11 + 8000392: f1b3 0220 subs.w r2, r3, #32 + 8000396: da0c bge.n 80003b2 <__adddf3+0x16e> + 8000398: 320c adds r2, #12 + 800039a: dd08 ble.n 80003ae <__adddf3+0x16a> + 800039c: f102 0c14 add.w ip, r2, #20 + 80003a0: f1c2 020c rsb r2, r2, #12 + 80003a4: fa01 f00c lsl.w r0, r1, ip + 80003a8: fa21 f102 lsr.w r1, r1, r2 + 80003ac: e00c b.n 80003c8 <__adddf3+0x184> + 80003ae: f102 0214 add.w r2, r2, #20 + 80003b2: bfd8 it le + 80003b4: f1c2 0c20 rsble ip, r2, #32 + 80003b8: fa01 f102 lsl.w r1, r1, r2 + 80003bc: fa20 fc0c lsr.w ip, r0, ip + 80003c0: bfdc itt le + 80003c2: ea41 010c orrle.w r1, r1, ip + 80003c6: 4090 lslle r0, r2 + 80003c8: 1ae4 subs r4, r4, r3 + 80003ca: bfa2 ittt ge + 80003cc: eb01 5104 addge.w r1, r1, r4, lsl #20 + 80003d0: 4329 orrge r1, r5 + 80003d2: bd30 popge {r4, r5, pc} + 80003d4: ea6f 0404 mvn.w r4, r4 + 80003d8: 3c1f subs r4, #31 + 80003da: da1c bge.n 8000416 <__adddf3+0x1d2> + 80003dc: 340c adds r4, #12 + 80003de: dc0e bgt.n 80003fe <__adddf3+0x1ba> + 80003e0: f104 0414 add.w r4, r4, #20 + 80003e4: f1c4 0220 rsb r2, r4, #32 + 80003e8: fa20 f004 lsr.w r0, r0, r4 + 80003ec: fa01 f302 lsl.w r3, r1, r2 + 80003f0: ea40 0003 orr.w r0, r0, r3 + 80003f4: fa21 f304 lsr.w r3, r1, r4 + 80003f8: ea45 0103 orr.w r1, r5, r3 + 80003fc: bd30 pop {r4, r5, pc} + 80003fe: f1c4 040c rsb r4, r4, #12 + 8000402: f1c4 0220 rsb r2, r4, #32 + 8000406: fa20 f002 lsr.w r0, r0, r2 + 800040a: fa01 f304 lsl.w r3, r1, r4 + 800040e: ea40 0003 orr.w r0, r0, r3 + 8000412: 4629 mov r1, r5 + 8000414: bd30 pop {r4, r5, pc} + 8000416: fa21 f004 lsr.w r0, r1, r4 + 800041a: 4629 mov r1, r5 + 800041c: bd30 pop {r4, r5, pc} + 800041e: f094 0f00 teq r4, #0 + 8000422: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 8000426: bf06 itte eq + 8000428: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 800042c: 3401 addeq r4, #1 + 800042e: 3d01 subne r5, #1 + 8000430: e74e b.n 80002d0 <__adddf3+0x8c> + 8000432: ea7f 5c64 mvns.w ip, r4, asr #21 + 8000436: bf18 it ne + 8000438: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 800043c: d029 beq.n 8000492 <__adddf3+0x24e> + 800043e: ea94 0f05 teq r4, r5 + 8000442: bf08 it eq + 8000444: ea90 0f02 teqeq r0, r2 + 8000448: d005 beq.n 8000456 <__adddf3+0x212> + 800044a: ea54 0c00 orrs.w ip, r4, r0 + 800044e: bf04 itt eq + 8000450: 4619 moveq r1, r3 + 8000452: 4610 moveq r0, r2 + 8000454: bd30 pop {r4, r5, pc} + 8000456: ea91 0f03 teq r1, r3 + 800045a: bf1e ittt ne + 800045c: 2100 movne r1, #0 + 800045e: 2000 movne r0, #0 + 8000460: bd30 popne {r4, r5, pc} + 8000462: ea5f 5c54 movs.w ip, r4, lsr #21 + 8000466: d105 bne.n 8000474 <__adddf3+0x230> + 8000468: 0040 lsls r0, r0, #1 + 800046a: 4149 adcs r1, r1 + 800046c: bf28 it cs + 800046e: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 8000472: bd30 pop {r4, r5, pc} + 8000474: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 8000478: bf3c itt cc + 800047a: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 800047e: bd30 popcc {r4, r5, pc} + 8000480: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000484: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 8000488: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800048c: f04f 0000 mov.w r0, #0 + 8000490: bd30 pop {r4, r5, pc} + 8000492: ea7f 5c64 mvns.w ip, r4, asr #21 + 8000496: bf1a itte ne + 8000498: 4619 movne r1, r3 + 800049a: 4610 movne r0, r2 + 800049c: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 80004a0: bf1c itt ne + 80004a2: 460b movne r3, r1 + 80004a4: 4602 movne r2, r0 + 80004a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80004aa: bf06 itte eq + 80004ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 80004b0: ea91 0f03 teqeq r1, r3 + 80004b4: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 80004b8: bd30 pop {r4, r5, pc} + 80004ba: bf00 nop + +080004bc <__aeabi_ui2d>: + 80004bc: f090 0f00 teq r0, #0 + 80004c0: bf04 itt eq + 80004c2: 2100 moveq r1, #0 + 80004c4: 4770 bxeq lr + 80004c6: b530 push {r4, r5, lr} + 80004c8: f44f 6480 mov.w r4, #1024 ; 0x400 + 80004cc: f104 0432 add.w r4, r4, #50 ; 0x32 + 80004d0: f04f 0500 mov.w r5, #0 + 80004d4: f04f 0100 mov.w r1, #0 + 80004d8: e750 b.n 800037c <__adddf3+0x138> + 80004da: bf00 nop + +080004dc <__aeabi_i2d>: + 80004dc: f090 0f00 teq r0, #0 + 80004e0: bf04 itt eq + 80004e2: 2100 moveq r1, #0 + 80004e4: 4770 bxeq lr + 80004e6: b530 push {r4, r5, lr} + 80004e8: f44f 6480 mov.w r4, #1024 ; 0x400 + 80004ec: f104 0432 add.w r4, r4, #50 ; 0x32 + 80004f0: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 80004f4: bf48 it mi + 80004f6: 4240 negmi r0, r0 + 80004f8: f04f 0100 mov.w r1, #0 + 80004fc: e73e b.n 800037c <__adddf3+0x138> + 80004fe: bf00 nop + +08000500 <__aeabi_f2d>: + 8000500: 0042 lsls r2, r0, #1 + 8000502: ea4f 01e2 mov.w r1, r2, asr #3 + 8000506: ea4f 0131 mov.w r1, r1, rrx + 800050a: ea4f 7002 mov.w r0, r2, lsl #28 + 800050e: bf1f itttt ne + 8000510: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 8000514: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 8000518: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 800051c: 4770 bxne lr + 800051e: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 8000522: bf08 it eq + 8000524: 4770 bxeq lr + 8000526: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 800052a: bf04 itt eq + 800052c: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 8000530: 4770 bxeq lr + 8000532: b530 push {r4, r5, lr} + 8000534: f44f 7460 mov.w r4, #896 ; 0x380 + 8000538: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 800053c: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000540: e71c b.n 800037c <__adddf3+0x138> + 8000542: bf00 nop + +08000544 <__aeabi_ul2d>: + 8000544: ea50 0201 orrs.w r2, r0, r1 + 8000548: bf08 it eq + 800054a: 4770 bxeq lr + 800054c: b530 push {r4, r5, lr} + 800054e: f04f 0500 mov.w r5, #0 + 8000552: e00a b.n 800056a <__aeabi_l2d+0x16> + +08000554 <__aeabi_l2d>: + 8000554: ea50 0201 orrs.w r2, r0, r1 + 8000558: bf08 it eq + 800055a: 4770 bxeq lr + 800055c: b530 push {r4, r5, lr} + 800055e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 8000562: d502 bpl.n 800056a <__aeabi_l2d+0x16> + 8000564: 4240 negs r0, r0 + 8000566: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800056a: f44f 6480 mov.w r4, #1024 ; 0x400 + 800056e: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000572: ea5f 5c91 movs.w ip, r1, lsr #22 + 8000576: f43f aed8 beq.w 800032a <__adddf3+0xe6> + 800057a: f04f 0203 mov.w r2, #3 + 800057e: ea5f 0cdc movs.w ip, ip, lsr #3 + 8000582: bf18 it ne + 8000584: 3203 addne r2, #3 + 8000586: ea5f 0cdc movs.w ip, ip, lsr #3 + 800058a: bf18 it ne + 800058c: 3203 addne r2, #3 + 800058e: eb02 02dc add.w r2, r2, ip, lsr #3 + 8000592: f1c2 0320 rsb r3, r2, #32 + 8000596: fa00 fc03 lsl.w ip, r0, r3 + 800059a: fa20 f002 lsr.w r0, r0, r2 + 800059e: fa01 fe03 lsl.w lr, r1, r3 + 80005a2: ea40 000e orr.w r0, r0, lr + 80005a6: fa21 f102 lsr.w r1, r1, r2 + 80005aa: 4414 add r4, r2 + 80005ac: e6bd b.n 800032a <__adddf3+0xe6> + 80005ae: bf00 nop + +080005b0 <__aeabi_dmul>: + 80005b0: b570 push {r4, r5, r6, lr} + 80005b2: f04f 0cff mov.w ip, #255 ; 0xff + 80005b6: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 80005ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 80005be: bf1d ittte ne + 80005c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 80005c4: ea94 0f0c teqne r4, ip + 80005c8: ea95 0f0c teqne r5, ip + 80005cc: f000 f8de bleq 800078c <__aeabi_dmul+0x1dc> + 80005d0: 442c add r4, r5 + 80005d2: ea81 0603 eor.w r6, r1, r3 + 80005d6: ea21 514c bic.w r1, r1, ip, lsl #21 + 80005da: ea23 534c bic.w r3, r3, ip, lsl #21 + 80005de: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 80005e2: bf18 it ne + 80005e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 80005e8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80005ec: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 80005f0: d038 beq.n 8000664 <__aeabi_dmul+0xb4> + 80005f2: fba0 ce02 umull ip, lr, r0, r2 + 80005f6: f04f 0500 mov.w r5, #0 + 80005fa: fbe1 e502 umlal lr, r5, r1, r2 + 80005fe: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 8000602: fbe0 e503 umlal lr, r5, r0, r3 + 8000606: f04f 0600 mov.w r6, #0 + 800060a: fbe1 5603 umlal r5, r6, r1, r3 + 800060e: f09c 0f00 teq ip, #0 + 8000612: bf18 it ne + 8000614: f04e 0e01 orrne.w lr, lr, #1 + 8000618: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 800061c: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 8000620: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 8000624: d204 bcs.n 8000630 <__aeabi_dmul+0x80> + 8000626: ea5f 0e4e movs.w lr, lr, lsl #1 + 800062a: 416d adcs r5, r5 + 800062c: eb46 0606 adc.w r6, r6, r6 + 8000630: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 8000634: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8000638: ea4f 20c5 mov.w r0, r5, lsl #11 + 800063c: ea40 505e orr.w r0, r0, lr, lsr #21 + 8000640: ea4f 2ece mov.w lr, lr, lsl #11 + 8000644: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 8000648: bf88 it hi + 800064a: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 800064e: d81e bhi.n 800068e <__aeabi_dmul+0xde> + 8000650: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 8000654: bf08 it eq + 8000656: ea5f 0e50 movseq.w lr, r0, lsr #1 + 800065a: f150 0000 adcs.w r0, r0, #0 + 800065e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8000662: bd70 pop {r4, r5, r6, pc} + 8000664: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 8000668: ea46 0101 orr.w r1, r6, r1 + 800066c: ea40 0002 orr.w r0, r0, r2 + 8000670: ea81 0103 eor.w r1, r1, r3 + 8000674: ebb4 045c subs.w r4, r4, ip, lsr #1 + 8000678: bfc2 ittt gt + 800067a: ebd4 050c rsbsgt r5, r4, ip + 800067e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 8000682: bd70 popgt {r4, r5, r6, pc} + 8000684: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000688: f04f 0e00 mov.w lr, #0 + 800068c: 3c01 subs r4, #1 + 800068e: f300 80ab bgt.w 80007e8 <__aeabi_dmul+0x238> + 8000692: f114 0f36 cmn.w r4, #54 ; 0x36 + 8000696: bfde ittt le + 8000698: 2000 movle r0, #0 + 800069a: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 800069e: bd70 pople {r4, r5, r6, pc} + 80006a0: f1c4 0400 rsb r4, r4, #0 + 80006a4: 3c20 subs r4, #32 + 80006a6: da35 bge.n 8000714 <__aeabi_dmul+0x164> + 80006a8: 340c adds r4, #12 + 80006aa: dc1b bgt.n 80006e4 <__aeabi_dmul+0x134> + 80006ac: f104 0414 add.w r4, r4, #20 + 80006b0: f1c4 0520 rsb r5, r4, #32 + 80006b4: fa00 f305 lsl.w r3, r0, r5 + 80006b8: fa20 f004 lsr.w r0, r0, r4 + 80006bc: fa01 f205 lsl.w r2, r1, r5 + 80006c0: ea40 0002 orr.w r0, r0, r2 + 80006c4: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 80006c8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 80006cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 80006d0: fa21 f604 lsr.w r6, r1, r4 + 80006d4: eb42 0106 adc.w r1, r2, r6 + 80006d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80006dc: bf08 it eq + 80006de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80006e2: bd70 pop {r4, r5, r6, pc} + 80006e4: f1c4 040c rsb r4, r4, #12 + 80006e8: f1c4 0520 rsb r5, r4, #32 + 80006ec: fa00 f304 lsl.w r3, r0, r4 + 80006f0: fa20 f005 lsr.w r0, r0, r5 + 80006f4: fa01 f204 lsl.w r2, r1, r4 + 80006f8: ea40 0002 orr.w r0, r0, r2 + 80006fc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000700: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8000704: f141 0100 adc.w r1, r1, #0 + 8000708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800070c: bf08 it eq + 800070e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 8000712: bd70 pop {r4, r5, r6, pc} + 8000714: f1c4 0520 rsb r5, r4, #32 + 8000718: fa00 f205 lsl.w r2, r0, r5 + 800071c: ea4e 0e02 orr.w lr, lr, r2 + 8000720: fa20 f304 lsr.w r3, r0, r4 + 8000724: fa01 f205 lsl.w r2, r1, r5 + 8000728: ea43 0302 orr.w r3, r3, r2 + 800072c: fa21 f004 lsr.w r0, r1, r4 + 8000730: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000734: fa21 f204 lsr.w r2, r1, r4 + 8000738: ea20 0002 bic.w r0, r0, r2 + 800073c: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8000740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000744: bf08 it eq + 8000746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800074a: bd70 pop {r4, r5, r6, pc} + 800074c: f094 0f00 teq r4, #0 + 8000750: d10f bne.n 8000772 <__aeabi_dmul+0x1c2> + 8000752: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 8000756: 0040 lsls r0, r0, #1 + 8000758: eb41 0101 adc.w r1, r1, r1 + 800075c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000760: bf08 it eq + 8000762: 3c01 subeq r4, #1 + 8000764: d0f7 beq.n 8000756 <__aeabi_dmul+0x1a6> + 8000766: ea41 0106 orr.w r1, r1, r6 + 800076a: f095 0f00 teq r5, #0 + 800076e: bf18 it ne + 8000770: 4770 bxne lr + 8000772: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 8000776: 0052 lsls r2, r2, #1 + 8000778: eb43 0303 adc.w r3, r3, r3 + 800077c: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 8000780: bf08 it eq + 8000782: 3d01 subeq r5, #1 + 8000784: d0f7 beq.n 8000776 <__aeabi_dmul+0x1c6> + 8000786: ea43 0306 orr.w r3, r3, r6 + 800078a: 4770 bx lr + 800078c: ea94 0f0c teq r4, ip + 8000790: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8000794: bf18 it ne + 8000796: ea95 0f0c teqne r5, ip + 800079a: d00c beq.n 80007b6 <__aeabi_dmul+0x206> + 800079c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80007a0: bf18 it ne + 80007a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80007a6: d1d1 bne.n 800074c <__aeabi_dmul+0x19c> + 80007a8: ea81 0103 eor.w r1, r1, r3 + 80007ac: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80007b0: f04f 0000 mov.w r0, #0 + 80007b4: bd70 pop {r4, r5, r6, pc} + 80007b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80007ba: bf06 itte eq + 80007bc: 4610 moveq r0, r2 + 80007be: 4619 moveq r1, r3 + 80007c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80007c4: d019 beq.n 80007fa <__aeabi_dmul+0x24a> + 80007c6: ea94 0f0c teq r4, ip + 80007ca: d102 bne.n 80007d2 <__aeabi_dmul+0x222> + 80007cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 80007d0: d113 bne.n 80007fa <__aeabi_dmul+0x24a> + 80007d2: ea95 0f0c teq r5, ip + 80007d6: d105 bne.n 80007e4 <__aeabi_dmul+0x234> + 80007d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 80007dc: bf1c itt ne + 80007de: 4610 movne r0, r2 + 80007e0: 4619 movne r1, r3 + 80007e2: d10a bne.n 80007fa <__aeabi_dmul+0x24a> + 80007e4: ea81 0103 eor.w r1, r1, r3 + 80007e8: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80007ec: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 80007f0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 80007f4: f04f 0000 mov.w r0, #0 + 80007f8: bd70 pop {r4, r5, r6, pc} + 80007fa: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 80007fe: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 8000802: bd70 pop {r4, r5, r6, pc} + +08000804 <__aeabi_ddiv>: + 8000804: b570 push {r4, r5, r6, lr} + 8000806: f04f 0cff mov.w ip, #255 ; 0xff + 800080a: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 800080e: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 8000812: bf1d ittte ne + 8000814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000818: ea94 0f0c teqne r4, ip + 800081c: ea95 0f0c teqne r5, ip + 8000820: f000 f8a7 bleq 8000972 <__aeabi_ddiv+0x16e> + 8000824: eba4 0405 sub.w r4, r4, r5 + 8000828: ea81 0e03 eor.w lr, r1, r3 + 800082c: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000830: ea4f 3101 mov.w r1, r1, lsl #12 + 8000834: f000 8088 beq.w 8000948 <__aeabi_ddiv+0x144> + 8000838: ea4f 3303 mov.w r3, r3, lsl #12 + 800083c: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 8000840: ea45 1313 orr.w r3, r5, r3, lsr #4 + 8000844: ea43 6312 orr.w r3, r3, r2, lsr #24 + 8000848: ea4f 2202 mov.w r2, r2, lsl #8 + 800084c: ea45 1511 orr.w r5, r5, r1, lsr #4 + 8000850: ea45 6510 orr.w r5, r5, r0, lsr #24 + 8000854: ea4f 2600 mov.w r6, r0, lsl #8 + 8000858: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 800085c: 429d cmp r5, r3 + 800085e: bf08 it eq + 8000860: 4296 cmpeq r6, r2 + 8000862: f144 04fd adc.w r4, r4, #253 ; 0xfd + 8000866: f504 7440 add.w r4, r4, #768 ; 0x300 + 800086a: d202 bcs.n 8000872 <__aeabi_ddiv+0x6e> + 800086c: 085b lsrs r3, r3, #1 + 800086e: ea4f 0232 mov.w r2, r2, rrx + 8000872: 1ab6 subs r6, r6, r2 + 8000874: eb65 0503 sbc.w r5, r5, r3 + 8000878: 085b lsrs r3, r3, #1 + 800087a: ea4f 0232 mov.w r2, r2, rrx + 800087e: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 8000882: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 8000886: ebb6 0e02 subs.w lr, r6, r2 + 800088a: eb75 0e03 sbcs.w lr, r5, r3 + 800088e: bf22 ittt cs + 8000890: 1ab6 subcs r6, r6, r2 + 8000892: 4675 movcs r5, lr + 8000894: ea40 000c orrcs.w r0, r0, ip + 8000898: 085b lsrs r3, r3, #1 + 800089a: ea4f 0232 mov.w r2, r2, rrx + 800089e: ebb6 0e02 subs.w lr, r6, r2 + 80008a2: eb75 0e03 sbcs.w lr, r5, r3 + 80008a6: bf22 ittt cs + 80008a8: 1ab6 subcs r6, r6, r2 + 80008aa: 4675 movcs r5, lr + 80008ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 80008b0: 085b lsrs r3, r3, #1 + 80008b2: ea4f 0232 mov.w r2, r2, rrx + 80008b6: ebb6 0e02 subs.w lr, r6, r2 + 80008ba: eb75 0e03 sbcs.w lr, r5, r3 + 80008be: bf22 ittt cs + 80008c0: 1ab6 subcs r6, r6, r2 + 80008c2: 4675 movcs r5, lr + 80008c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 80008c8: 085b lsrs r3, r3, #1 + 80008ca: ea4f 0232 mov.w r2, r2, rrx + 80008ce: ebb6 0e02 subs.w lr, r6, r2 + 80008d2: eb75 0e03 sbcs.w lr, r5, r3 + 80008d6: bf22 ittt cs + 80008d8: 1ab6 subcs r6, r6, r2 + 80008da: 4675 movcs r5, lr + 80008dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 80008e0: ea55 0e06 orrs.w lr, r5, r6 + 80008e4: d018 beq.n 8000918 <__aeabi_ddiv+0x114> + 80008e6: ea4f 1505 mov.w r5, r5, lsl #4 + 80008ea: ea45 7516 orr.w r5, r5, r6, lsr #28 + 80008ee: ea4f 1606 mov.w r6, r6, lsl #4 + 80008f2: ea4f 03c3 mov.w r3, r3, lsl #3 + 80008f6: ea43 7352 orr.w r3, r3, r2, lsr #29 + 80008fa: ea4f 02c2 mov.w r2, r2, lsl #3 + 80008fe: ea5f 1c1c movs.w ip, ip, lsr #4 + 8000902: d1c0 bne.n 8000886 <__aeabi_ddiv+0x82> + 8000904: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000908: d10b bne.n 8000922 <__aeabi_ddiv+0x11e> + 800090a: ea41 0100 orr.w r1, r1, r0 + 800090e: f04f 0000 mov.w r0, #0 + 8000912: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 8000916: e7b6 b.n 8000886 <__aeabi_ddiv+0x82> + 8000918: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 800091c: bf04 itt eq + 800091e: 4301 orreq r1, r0 + 8000920: 2000 moveq r0, #0 + 8000922: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 8000926: bf88 it hi + 8000928: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 800092c: f63f aeaf bhi.w 800068e <__aeabi_dmul+0xde> + 8000930: ebb5 0c03 subs.w ip, r5, r3 + 8000934: bf04 itt eq + 8000936: ebb6 0c02 subseq.w ip, r6, r2 + 800093a: ea5f 0c50 movseq.w ip, r0, lsr #1 + 800093e: f150 0000 adcs.w r0, r0, #0 + 8000942: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8000946: bd70 pop {r4, r5, r6, pc} + 8000948: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 800094c: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 8000950: eb14 045c adds.w r4, r4, ip, lsr #1 + 8000954: bfc2 ittt gt + 8000956: ebd4 050c rsbsgt r5, r4, ip + 800095a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 800095e: bd70 popgt {r4, r5, r6, pc} + 8000960: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000964: f04f 0e00 mov.w lr, #0 + 8000968: 3c01 subs r4, #1 + 800096a: e690 b.n 800068e <__aeabi_dmul+0xde> + 800096c: ea45 0e06 orr.w lr, r5, r6 + 8000970: e68d b.n 800068e <__aeabi_dmul+0xde> + 8000972: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8000976: ea94 0f0c teq r4, ip + 800097a: bf08 it eq + 800097c: ea95 0f0c teqeq r5, ip + 8000980: f43f af3b beq.w 80007fa <__aeabi_dmul+0x24a> + 8000984: ea94 0f0c teq r4, ip + 8000988: d10a bne.n 80009a0 <__aeabi_ddiv+0x19c> + 800098a: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 800098e: f47f af34 bne.w 80007fa <__aeabi_dmul+0x24a> + 8000992: ea95 0f0c teq r5, ip + 8000996: f47f af25 bne.w 80007e4 <__aeabi_dmul+0x234> + 800099a: 4610 mov r0, r2 + 800099c: 4619 mov r1, r3 + 800099e: e72c b.n 80007fa <__aeabi_dmul+0x24a> + 80009a0: ea95 0f0c teq r5, ip + 80009a4: d106 bne.n 80009b4 <__aeabi_ddiv+0x1b0> + 80009a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 80009aa: f43f aefd beq.w 80007a8 <__aeabi_dmul+0x1f8> + 80009ae: 4610 mov r0, r2 + 80009b0: 4619 mov r1, r3 + 80009b2: e722 b.n 80007fa <__aeabi_dmul+0x24a> + 80009b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80009b8: bf18 it ne + 80009ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80009be: f47f aec5 bne.w 800074c <__aeabi_dmul+0x19c> + 80009c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 80009c6: f47f af0d bne.w 80007e4 <__aeabi_dmul+0x234> + 80009ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 80009ce: f47f aeeb bne.w 80007a8 <__aeabi_dmul+0x1f8> + 80009d2: e712 b.n 80007fa <__aeabi_dmul+0x24a> + +080009d4 <__gedf2>: + 80009d4: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff + 80009d8: e006 b.n 80009e8 <__cmpdf2+0x4> + 80009da: bf00 nop + +080009dc <__ledf2>: + 80009dc: f04f 0c01 mov.w ip, #1 + 80009e0: e002 b.n 80009e8 <__cmpdf2+0x4> + 80009e2: bf00 nop + +080009e4 <__cmpdf2>: + 80009e4: f04f 0c01 mov.w ip, #1 + 80009e8: f84d cd04 str.w ip, [sp, #-4]! + 80009ec: ea4f 0c41 mov.w ip, r1, lsl #1 + 80009f0: ea7f 5c6c mvns.w ip, ip, asr #21 + 80009f4: ea4f 0c43 mov.w ip, r3, lsl #1 + 80009f8: bf18 it ne + 80009fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 80009fe: d01b beq.n 8000a38 <__cmpdf2+0x54> + 8000a00: b001 add sp, #4 + 8000a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 8000a06: bf0c ite eq + 8000a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8000a0c: ea91 0f03 teqne r1, r3 + 8000a10: bf02 ittt eq + 8000a12: ea90 0f02 teqeq r0, r2 + 8000a16: 2000 moveq r0, #0 + 8000a18: 4770 bxeq lr + 8000a1a: f110 0f00 cmn.w r0, #0 + 8000a1e: ea91 0f03 teq r1, r3 + 8000a22: bf58 it pl + 8000a24: 4299 cmppl r1, r3 + 8000a26: bf08 it eq + 8000a28: 4290 cmpeq r0, r2 + 8000a2a: bf2c ite cs + 8000a2c: 17d8 asrcs r0, r3, #31 + 8000a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 + 8000a32: f040 0001 orr.w r0, r0, #1 + 8000a36: 4770 bx lr + 8000a38: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a3c: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a40: d102 bne.n 8000a48 <__cmpdf2+0x64> + 8000a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000a46: d107 bne.n 8000a58 <__cmpdf2+0x74> + 8000a48: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000a4c: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a50: d1d6 bne.n 8000a00 <__cmpdf2+0x1c> + 8000a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000a56: d0d3 beq.n 8000a00 <__cmpdf2+0x1c> + 8000a58: f85d 0b04 ldr.w r0, [sp], #4 + 8000a5c: 4770 bx lr + 8000a5e: bf00 nop + +08000a60 <__aeabi_cdrcmple>: + 8000a60: 4684 mov ip, r0 + 8000a62: 4610 mov r0, r2 + 8000a64: 4662 mov r2, ip + 8000a66: 468c mov ip, r1 + 8000a68: 4619 mov r1, r3 + 8000a6a: 4663 mov r3, ip + 8000a6c: e000 b.n 8000a70 <__aeabi_cdcmpeq> + 8000a6e: bf00 nop + +08000a70 <__aeabi_cdcmpeq>: + 8000a70: b501 push {r0, lr} + 8000a72: f7ff ffb7 bl 80009e4 <__cmpdf2> + 8000a76: 2800 cmp r0, #0 + 8000a78: bf48 it mi + 8000a7a: f110 0f00 cmnmi.w r0, #0 + 8000a7e: bd01 pop {r0, pc} + +08000a80 <__aeabi_dcmpeq>: + 8000a80: f84d ed08 str.w lr, [sp, #-8]! + 8000a84: f7ff fff4 bl 8000a70 <__aeabi_cdcmpeq> + 8000a88: bf0c ite eq + 8000a8a: 2001 moveq r0, #1 + 8000a8c: 2000 movne r0, #0 + 8000a8e: f85d fb08 ldr.w pc, [sp], #8 + 8000a92: bf00 nop + +08000a94 <__aeabi_dcmplt>: + 8000a94: f84d ed08 str.w lr, [sp, #-8]! + 8000a98: f7ff ffea bl 8000a70 <__aeabi_cdcmpeq> + 8000a9c: bf34 ite cc + 8000a9e: 2001 movcc r0, #1 + 8000aa0: 2000 movcs r0, #0 + 8000aa2: f85d fb08 ldr.w pc, [sp], #8 + 8000aa6: bf00 nop + +08000aa8 <__aeabi_dcmple>: + 8000aa8: f84d ed08 str.w lr, [sp, #-8]! + 8000aac: f7ff ffe0 bl 8000a70 <__aeabi_cdcmpeq> + 8000ab0: bf94 ite ls + 8000ab2: 2001 movls r0, #1 + 8000ab4: 2000 movhi r0, #0 + 8000ab6: f85d fb08 ldr.w pc, [sp], #8 + 8000aba: bf00 nop + +08000abc <__aeabi_dcmpge>: + 8000abc: f84d ed08 str.w lr, [sp, #-8]! + 8000ac0: f7ff ffce bl 8000a60 <__aeabi_cdrcmple> + 8000ac4: bf94 ite ls + 8000ac6: 2001 movls r0, #1 + 8000ac8: 2000 movhi r0, #0 + 8000aca: f85d fb08 ldr.w pc, [sp], #8 + 8000ace: bf00 nop + +08000ad0 <__aeabi_dcmpgt>: + 8000ad0: f84d ed08 str.w lr, [sp, #-8]! + 8000ad4: f7ff ffc4 bl 8000a60 <__aeabi_cdrcmple> + 8000ad8: bf34 ite cc + 8000ada: 2001 movcc r0, #1 + 8000adc: 2000 movcs r0, #0 + 8000ade: f85d fb08 ldr.w pc, [sp], #8 + 8000ae2: bf00 nop + +08000ae4 <__aeabi_dcmpun>: + 8000ae4: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000ae8: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000aec: d102 bne.n 8000af4 <__aeabi_dcmpun+0x10> + 8000aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000af2: d10a bne.n 8000b0a <__aeabi_dcmpun+0x26> + 8000af4: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000af8: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000afc: d102 bne.n 8000b04 <__aeabi_dcmpun+0x20> + 8000afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000b02: d102 bne.n 8000b0a <__aeabi_dcmpun+0x26> + 8000b04: f04f 0000 mov.w r0, #0 + 8000b08: 4770 bx lr + 8000b0a: f04f 0001 mov.w r0, #1 + 8000b0e: 4770 bx lr + +08000b10 <__aeabi_d2iz>: + 8000b10: ea4f 0241 mov.w r2, r1, lsl #1 + 8000b14: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000b18: d215 bcs.n 8000b46 <__aeabi_d2iz+0x36> + 8000b1a: d511 bpl.n 8000b40 <__aeabi_d2iz+0x30> + 8000b1c: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000b20: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000b24: d912 bls.n 8000b4c <__aeabi_d2iz+0x3c> + 8000b26: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000b2a: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000b32: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000b36: fa23 f002 lsr.w r0, r3, r2 + 8000b3a: bf18 it ne + 8000b3c: 4240 negne r0, r0 + 8000b3e: 4770 bx lr + 8000b40: f04f 0000 mov.w r0, #0 + 8000b44: 4770 bx lr + 8000b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000b4a: d105 bne.n 8000b58 <__aeabi_d2iz+0x48> + 8000b4c: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000b50: bf08 it eq + 8000b52: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000b56: 4770 bx lr + 8000b58: f04f 0000 mov.w r0, #0 + 8000b5c: 4770 bx lr + 8000b5e: bf00 nop + +08000b60
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000b60: b580 push {r7, lr} + 8000b62: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000b64: f000 fab2 bl 80010cc + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000b68: f000 f807 bl 8000b7a + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000b6c: f000 f84a bl 8000c04 + MX_FSMC_Init(); + 8000b70: f000 f89e bl 8000cb0 + /* USER CODE BEGIN 2 */ + main_app(); + 8000b74: f001 fe3e bl 80027f4 + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + 8000b78: e7fe b.n 8000b78 + +08000b7a : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000b7a: b580 push {r7, lr} + 8000b7c: b090 sub sp, #64 ; 0x40 + 8000b7e: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000b80: f107 0318 add.w r3, r7, #24 + 8000b84: 2228 movs r2, #40 ; 0x28 + 8000b86: 2100 movs r1, #0 + 8000b88: 4618 mov r0, r3 + 8000b8a: f001 fe63 bl 8002854 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000b8e: 1d3b adds r3, r7, #4 + 8000b90: 2200 movs r2, #0 + 8000b92: 601a str r2, [r3, #0] + 8000b94: 605a str r2, [r3, #4] + 8000b96: 609a str r2, [r3, #8] + 8000b98: 60da str r2, [r3, #12] + 8000b9a: 611a str r2, [r3, #16] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 8000b9c: 2301 movs r3, #1 + 8000b9e: 61bb str r3, [r7, #24] + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8000ba0: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8000ba4: 61fb str r3, [r7, #28] + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + 8000ba6: 2300 movs r3, #0 + 8000ba8: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000baa: 2301 movs r3, #1 + 8000bac: 62bb str r3, [r7, #40] ; 0x28 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000bae: 2302 movs r3, #2 + 8000bb0: 637b str r3, [r7, #52] ; 0x34 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8000bb2: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8000bb6: 63bb str r3, [r7, #56] ; 0x38 + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + 8000bb8: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 + 8000bbc: 63fb str r3, [r7, #60] ; 0x3c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000bbe: f107 0318 add.w r3, r7, #24 + 8000bc2: 4618 mov r0, r3 + 8000bc4: f000 fd98 bl 80016f8 + 8000bc8: 4603 mov r3, r0 + 8000bca: 2b00 cmp r3, #0 + 8000bcc: d001 beq.n 8000bd2 + { + Error_Handler(); + 8000bce: f000 f8d3 bl 8000d78 + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000bd2: 230f movs r3, #15 + 8000bd4: 607b str r3, [r7, #4] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8000bd6: 2302 movs r3, #2 + 8000bd8: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000bda: 2300 movs r3, #0 + 8000bdc: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 8000bde: f44f 6380 mov.w r3, #1024 ; 0x400 + 8000be2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000be4: 2300 movs r3, #0 + 8000be6: 617b str r3, [r7, #20] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 8000be8: 1d3b adds r3, r7, #4 + 8000bea: 2102 movs r1, #2 + 8000bec: 4618 mov r0, r3 + 8000bee: f001 f803 bl 8001bf8 + 8000bf2: 4603 mov r3, r0 + 8000bf4: 2b00 cmp r3, #0 + 8000bf6: d001 beq.n 8000bfc + { + Error_Handler(); + 8000bf8: f000 f8be bl 8000d78 + } +} + 8000bfc: bf00 nop + 8000bfe: 3740 adds r7, #64 ; 0x40 + 8000c00: 46bd mov sp, r7 + 8000c02: bd80 pop {r7, pc} + +08000c04 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000c04: b580 push {r7, lr} + 8000c06: b088 sub sp, #32 + 8000c08: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000c0a: f107 0310 add.w r3, r7, #16 + 8000c0e: 2200 movs r2, #0 + 8000c10: 601a str r2, [r3, #0] + 8000c12: 605a str r2, [r3, #4] + 8000c14: 609a str r2, [r3, #8] + 8000c16: 60da str r2, [r3, #12] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000c18: 4b23 ldr r3, [pc, #140] ; (8000ca8 ) + 8000c1a: 699b ldr r3, [r3, #24] + 8000c1c: 4a22 ldr r2, [pc, #136] ; (8000ca8 ) + 8000c1e: f043 0308 orr.w r3, r3, #8 + 8000c22: 6193 str r3, [r2, #24] + 8000c24: 4b20 ldr r3, [pc, #128] ; (8000ca8 ) + 8000c26: 699b ldr r3, [r3, #24] + 8000c28: f003 0308 and.w r3, r3, #8 + 8000c2c: 60fb str r3, [r7, #12] + 8000c2e: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8000c30: 4b1d ldr r3, [pc, #116] ; (8000ca8 ) + 8000c32: 699b ldr r3, [r3, #24] + 8000c34: 4a1c ldr r2, [pc, #112] ; (8000ca8 ) + 8000c36: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8000c3a: 6193 str r3, [r2, #24] + 8000c3c: 4b1a ldr r3, [pc, #104] ; (8000ca8 ) + 8000c3e: 699b ldr r3, [r3, #24] + 8000c40: f403 7380 and.w r3, r3, #256 ; 0x100 + 8000c44: 60bb str r3, [r7, #8] + 8000c46: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8000c48: 4b17 ldr r3, [pc, #92] ; (8000ca8 ) + 8000c4a: 699b ldr r3, [r3, #24] + 8000c4c: 4a16 ldr r2, [pc, #88] ; (8000ca8 ) + 8000c4e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8000c52: 6193 str r3, [r2, #24] + 8000c54: 4b14 ldr r3, [pc, #80] ; (8000ca8 ) + 8000c56: 699b ldr r3, [r3, #24] + 8000c58: f003 0340 and.w r3, r3, #64 ; 0x40 + 8000c5c: 607b str r3, [r7, #4] + 8000c5e: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8000c60: 4b11 ldr r3, [pc, #68] ; (8000ca8 ) + 8000c62: 699b ldr r3, [r3, #24] + 8000c64: 4a10 ldr r2, [pc, #64] ; (8000ca8 ) + 8000c66: f043 0320 orr.w r3, r3, #32 + 8000c6a: 6193 str r3, [r2, #24] + 8000c6c: 4b0e ldr r3, [pc, #56] ; (8000ca8 ) + 8000c6e: 699b ldr r3, [r3, #24] + 8000c70: f003 0320 and.w r3, r3, #32 + 8000c74: 603b str r3, [r7, #0] + 8000c76: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); + 8000c78: 2200 movs r2, #0 + 8000c7a: 2101 movs r1, #1 + 8000c7c: 480b ldr r0, [pc, #44] ; (8000cac ) + 8000c7e: f000 fd23 bl 80016c8 + + /*Configure GPIO pin : LCD_BL_Pin */ + GPIO_InitStruct.Pin = LCD_BL_Pin; + 8000c82: 2301 movs r3, #1 + 8000c84: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000c86: 2301 movs r3, #1 + 8000c88: 617b str r3, [r7, #20] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000c8a: 2300 movs r3, #0 + 8000c8c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000c8e: 2302 movs r3, #2 + 8000c90: 61fb str r3, [r7, #28] + HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); + 8000c92: f107 0310 add.w r3, r7, #16 + 8000c96: 4619 mov r1, r3 + 8000c98: 4804 ldr r0, [pc, #16] ; (8000cac ) + 8000c9a: f000 fb81 bl 80013a0 + +} + 8000c9e: bf00 nop + 8000ca0: 3720 adds r7, #32 + 8000ca2: 46bd mov sp, r7 + 8000ca4: bd80 pop {r7, pc} + 8000ca6: bf00 nop + 8000ca8: 40021000 .word 0x40021000 + 8000cac: 40010c00 .word 0x40010c00 + +08000cb0 : + +/* FSMC initialization function */ +static void MX_FSMC_Init(void) +{ + 8000cb0: b580 push {r7, lr} + 8000cb2: b088 sub sp, #32 + 8000cb4: af00 add r7, sp, #0 + + /* USER CODE BEGIN FSMC_Init 0 */ + + /* USER CODE END FSMC_Init 0 */ + + FSMC_NORSRAM_TimingTypeDef Timing = {0}; + 8000cb6: 1d3b adds r3, r7, #4 + 8000cb8: 2200 movs r2, #0 + 8000cba: 601a str r2, [r3, #0] + 8000cbc: 605a str r2, [r3, #4] + 8000cbe: 609a str r2, [r3, #8] + 8000cc0: 60da str r2, [r3, #12] + 8000cc2: 611a str r2, [r3, #16] + 8000cc4: 615a str r2, [r3, #20] + 8000cc6: 619a str r2, [r3, #24] + + /* USER CODE END FSMC_Init 1 */ + + /** Perform the SRAM1 memory initialization sequence + */ + hsram1.Instance = FSMC_NORSRAM_DEVICE; + 8000cc8: 4b28 ldr r3, [pc, #160] ; (8000d6c ) + 8000cca: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 + 8000cce: 601a str r2, [r3, #0] + hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + 8000cd0: 4b26 ldr r3, [pc, #152] ; (8000d6c ) + 8000cd2: 4a27 ldr r2, [pc, #156] ; (8000d70 ) + 8000cd4: 605a str r2, [r3, #4] + /* hsram1.Init */ + hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; + 8000cd6: 4b25 ldr r3, [pc, #148] ; (8000d6c ) + 8000cd8: 2206 movs r2, #6 + 8000cda: 609a str r2, [r3, #8] + hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + 8000cdc: 4b23 ldr r3, [pc, #140] ; (8000d6c ) + 8000cde: 2200 movs r2, #0 + 8000ce0: 60da str r2, [r3, #12] + hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + 8000ce2: 4b22 ldr r3, [pc, #136] ; (8000d6c ) + 8000ce4: 2200 movs r2, #0 + 8000ce6: 611a str r2, [r3, #16] + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; + 8000ce8: 4b20 ldr r3, [pc, #128] ; (8000d6c ) + 8000cea: 2210 movs r2, #16 + 8000cec: 615a str r2, [r3, #20] + hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + 8000cee: 4b1f ldr r3, [pc, #124] ; (8000d6c ) + 8000cf0: 2200 movs r2, #0 + 8000cf2: 619a str r2, [r3, #24] + hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + 8000cf4: 4b1d ldr r3, [pc, #116] ; (8000d6c ) + 8000cf6: 2200 movs r2, #0 + 8000cf8: 61da str r2, [r3, #28] + hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + 8000cfa: 4b1c ldr r3, [pc, #112] ; (8000d6c ) + 8000cfc: 2200 movs r2, #0 + 8000cfe: 621a str r2, [r3, #32] + hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + 8000d00: 4b1a ldr r3, [pc, #104] ; (8000d6c ) + 8000d02: 2200 movs r2, #0 + 8000d04: 625a str r2, [r3, #36] ; 0x24 + hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + 8000d06: 4b19 ldr r3, [pc, #100] ; (8000d6c ) + 8000d08: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8000d0c: 629a str r2, [r3, #40] ; 0x28 + hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + 8000d0e: 4b17 ldr r3, [pc, #92] ; (8000d6c ) + 8000d10: 2200 movs r2, #0 + 8000d12: 62da str r2, [r3, #44] ; 0x2c + hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; + 8000d14: 4b15 ldr r3, [pc, #84] ; (8000d6c ) + 8000d16: 2200 movs r2, #0 + 8000d18: 631a str r2, [r3, #48] ; 0x30 + hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + 8000d1a: 4b14 ldr r3, [pc, #80] ; (8000d6c ) + 8000d1c: 2200 movs r2, #0 + 8000d1e: 635a str r2, [r3, #52] ; 0x34 + hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + 8000d20: 4b12 ldr r3, [pc, #72] ; (8000d6c ) + 8000d22: 2200 movs r2, #0 + 8000d24: 639a str r2, [r3, #56] ; 0x38 + /* Timing */ + Timing.AddressSetupTime = 0; + 8000d26: 2300 movs r3, #0 + 8000d28: 607b str r3, [r7, #4] + Timing.AddressHoldTime = 15; + 8000d2a: 230f movs r3, #15 + 8000d2c: 60bb str r3, [r7, #8] + Timing.DataSetupTime = 1; + 8000d2e: 2301 movs r3, #1 + 8000d30: 60fb str r3, [r7, #12] + Timing.BusTurnAroundDuration = 0; + 8000d32: 2300 movs r3, #0 + 8000d34: 613b str r3, [r7, #16] + Timing.CLKDivision = 16; + 8000d36: 2310 movs r3, #16 + 8000d38: 617b str r3, [r7, #20] + Timing.DataLatency = 17; + 8000d3a: 2311 movs r3, #17 + 8000d3c: 61bb str r3, [r7, #24] + Timing.AccessMode = FSMC_ACCESS_MODE_A; + 8000d3e: 2300 movs r3, #0 + 8000d40: 61fb str r3, [r7, #28] + /* ExtTiming */ + + if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) + 8000d42: 1d3b adds r3, r7, #4 + 8000d44: 2200 movs r2, #0 + 8000d46: 4619 mov r1, r3 + 8000d48: 4808 ldr r0, [pc, #32] ; (8000d6c ) + 8000d4a: f001 f8bd bl 8001ec8 + 8000d4e: 4603 mov r3, r0 + 8000d50: 2b00 cmp r3, #0 + 8000d52: d001 beq.n 8000d58 + { + Error_Handler( ); + 8000d54: f000 f810 bl 8000d78 + } + + /** Disconnect NADV + */ + + __HAL_AFIO_FSMCNADV_DISCONNECTED(); + 8000d58: 4b06 ldr r3, [pc, #24] ; (8000d74 ) + 8000d5a: 69db ldr r3, [r3, #28] + 8000d5c: 4a05 ldr r2, [pc, #20] ; (8000d74 ) + 8000d5e: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8000d62: 61d3 str r3, [r2, #28] + + /* USER CODE BEGIN FSMC_Init 2 */ + + /* USER CODE END FSMC_Init 2 */ +} + 8000d64: bf00 nop + 8000d66: 3720 adds r7, #32 + 8000d68: 46bd mov sp, r7 + 8000d6a: bd80 pop {r7, pc} + 8000d6c: 20000208 .word 0x20000208 + 8000d70: a0000104 .word 0xa0000104 + 8000d74: 40010000 .word 0x40010000 + +08000d78 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000d78: b480 push {r7} + 8000d7a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000d7c: b672 cpsid i +} + 8000d7e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000d80: e7fe b.n 8000d80 + ... + +08000d84 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000d84: b480 push {r7} + 8000d86: b085 sub sp, #20 + 8000d88: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_AFIO_CLK_ENABLE(); + 8000d8a: 4b15 ldr r3, [pc, #84] ; (8000de0 ) + 8000d8c: 699b ldr r3, [r3, #24] + 8000d8e: 4a14 ldr r2, [pc, #80] ; (8000de0 ) + 8000d90: f043 0301 orr.w r3, r3, #1 + 8000d94: 6193 str r3, [r2, #24] + 8000d96: 4b12 ldr r3, [pc, #72] ; (8000de0 ) + 8000d98: 699b ldr r3, [r3, #24] + 8000d9a: f003 0301 and.w r3, r3, #1 + 8000d9e: 60bb str r3, [r7, #8] + 8000da0: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 8000da2: 4b0f ldr r3, [pc, #60] ; (8000de0 ) + 8000da4: 69db ldr r3, [r3, #28] + 8000da6: 4a0e ldr r2, [pc, #56] ; (8000de0 ) + 8000da8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8000dac: 61d3 str r3, [r2, #28] + 8000dae: 4b0c ldr r3, [pc, #48] ; (8000de0 ) + 8000db0: 69db ldr r3, [r3, #28] + 8000db2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8000db6: 607b str r3, [r7, #4] + 8000db8: 687b ldr r3, [r7, #4] + + /* System interrupt init*/ + + /** DISABLE: JTAG-DP Disabled and SW-DP Disabled + */ + __HAL_AFIO_REMAP_SWJ_DISABLE(); + 8000dba: 4b0a ldr r3, [pc, #40] ; (8000de4 ) + 8000dbc: 685b ldr r3, [r3, #4] + 8000dbe: 60fb str r3, [r7, #12] + 8000dc0: 68fb ldr r3, [r7, #12] + 8000dc2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 + 8000dc6: 60fb str r3, [r7, #12] + 8000dc8: 68fb ldr r3, [r7, #12] + 8000dca: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 8000dce: 60fb str r3, [r7, #12] + 8000dd0: 4a04 ldr r2, [pc, #16] ; (8000de4 ) + 8000dd2: 68fb ldr r3, [r7, #12] + 8000dd4: 6053 str r3, [r2, #4] + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000dd6: bf00 nop + 8000dd8: 3714 adds r7, #20 + 8000dda: 46bd mov sp, r7 + 8000ddc: bc80 pop {r7} + 8000dde: 4770 bx lr + 8000de0: 40021000 .word 0x40021000 + 8000de4: 40010000 .word 0x40010000 + +08000de8 : + +static uint32_t FSMC_Initialized = 0; + +static void HAL_FSMC_MspInit(void){ + 8000de8: b580 push {r7, lr} + 8000dea: b086 sub sp, #24 + 8000dec: af00 add r7, sp, #0 + /* USER CODE BEGIN FSMC_MspInit 0 */ + + /* USER CODE END FSMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + 8000dee: f107 0308 add.w r3, r7, #8 + 8000df2: 2200 movs r2, #0 + 8000df4: 601a str r2, [r3, #0] + 8000df6: 605a str r2, [r3, #4] + 8000df8: 609a str r2, [r3, #8] + 8000dfa: 60da str r2, [r3, #12] + if (FSMC_Initialized) { + 8000dfc: 4b1f ldr r3, [pc, #124] ; (8000e7c ) + 8000dfe: 681b ldr r3, [r3, #0] + 8000e00: 2b00 cmp r3, #0 + 8000e02: d136 bne.n 8000e72 + return; + } + FSMC_Initialized = 1; + 8000e04: 4b1d ldr r3, [pc, #116] ; (8000e7c ) + 8000e06: 2201 movs r2, #1 + 8000e08: 601a str r2, [r3, #0] + + /* Peripheral clock enable */ + __HAL_RCC_FSMC_CLK_ENABLE(); + 8000e0a: 4b1d ldr r3, [pc, #116] ; (8000e80 ) + 8000e0c: 695b ldr r3, [r3, #20] + 8000e0e: 4a1c ldr r2, [pc, #112] ; (8000e80 ) + 8000e10: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8000e14: 6153 str r3, [r2, #20] + 8000e16: 4b1a ldr r3, [pc, #104] ; (8000e80 ) + 8000e18: 695b ldr r3, [r3, #20] + 8000e1a: f403 7380 and.w r3, r3, #256 ; 0x100 + 8000e1e: 607b str r3, [r7, #4] + 8000e20: 687b ldr r3, [r7, #4] + PD1 ------> FSMC_D3 + PD4 ------> FSMC_NOE + PD5 ------> FSMC_NWE + PG12 ------> FSMC_NE4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; + 8000e22: f241 0301 movw r3, #4097 ; 0x1001 + 8000e26: 60bb str r3, [r7, #8] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000e28: 2302 movs r3, #2 + 8000e2a: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8000e2c: 2303 movs r3, #3 + 8000e2e: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + 8000e30: f107 0308 add.w r3, r7, #8 + 8000e34: 4619 mov r1, r3 + 8000e36: 4813 ldr r0, [pc, #76] ; (8000e84 ) + 8000e38: f000 fab2 bl 80013a0 + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + 8000e3c: f64f 7380 movw r3, #65408 ; 0xff80 + 8000e40: 60bb str r3, [r7, #8] + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000e42: 2302 movs r3, #2 + 8000e44: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8000e46: 2303 movs r3, #3 + 8000e48: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8000e4a: f107 0308 add.w r3, r7, #8 + 8000e4e: 4619 mov r1, r3 + 8000e50: 480d ldr r0, [pc, #52] ; (8000e88 ) + 8000e52: f000 faa5 bl 80013a0 + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + 8000e56: f24c 7333 movw r3, #50995 ; 0xc733 + 8000e5a: 60bb str r3, [r7, #8] + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 + |GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000e5c: 2302 movs r3, #2 + 8000e5e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8000e60: 2303 movs r3, #3 + 8000e62: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8000e64: f107 0308 add.w r3, r7, #8 + 8000e68: 4619 mov r1, r3 + 8000e6a: 4808 ldr r0, [pc, #32] ; (8000e8c ) + 8000e6c: f000 fa98 bl 80013a0 + 8000e70: e000 b.n 8000e74 + return; + 8000e72: bf00 nop + + /* USER CODE BEGIN FSMC_MspInit 1 */ + + /* USER CODE END FSMC_MspInit 1 */ +} + 8000e74: 3718 adds r7, #24 + 8000e76: 46bd mov sp, r7 + 8000e78: bd80 pop {r7, pc} + 8000e7a: bf00 nop + 8000e7c: 200001f8 .word 0x200001f8 + 8000e80: 40021000 .word 0x40021000 + 8000e84: 40012000 .word 0x40012000 + 8000e88: 40011800 .word 0x40011800 + 8000e8c: 40011400 .word 0x40011400 + +08000e90 : + +void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ + 8000e90: b580 push {r7, lr} + 8000e92: b082 sub sp, #8 + 8000e94: af00 add r7, sp, #0 + 8000e96: 6078 str r0, [r7, #4] + /* USER CODE BEGIN SRAM_MspInit 0 */ + + /* USER CODE END SRAM_MspInit 0 */ + HAL_FSMC_MspInit(); + 8000e98: f7ff ffa6 bl 8000de8 + /* USER CODE BEGIN SRAM_MspInit 1 */ + + /* USER CODE END SRAM_MspInit 1 */ +} + 8000e9c: bf00 nop + 8000e9e: 3708 adds r7, #8 + 8000ea0: 46bd mov sp, r7 + 8000ea2: bd80 pop {r7, pc} + +08000ea4 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000ea4: b480 push {r7} + 8000ea6: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000ea8: e7fe b.n 8000ea8 + +08000eaa : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000eaa: b480 push {r7} + 8000eac: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000eae: e7fe b.n 8000eae + +08000eb0 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000eb0: b480 push {r7} + 8000eb2: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000eb4: e7fe b.n 8000eb4 + +08000eb6 : + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000eb6: b480 push {r7} + 8000eb8: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000eba: e7fe b.n 8000eba + +08000ebc : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000ebc: b480 push {r7} + 8000ebe: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000ec0: e7fe b.n 8000ec0 + +08000ec2 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000ec2: b480 push {r7} + 8000ec4: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8000ec6: bf00 nop + 8000ec8: 46bd mov sp, r7 + 8000eca: bc80 pop {r7} + 8000ecc: 4770 bx lr + +08000ece : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000ece: b480 push {r7} + 8000ed0: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000ed2: bf00 nop + 8000ed4: 46bd mov sp, r7 + 8000ed6: bc80 pop {r7} + 8000ed8: 4770 bx lr + +08000eda : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000eda: b480 push {r7} + 8000edc: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000ede: bf00 nop + 8000ee0: 46bd mov sp, r7 + 8000ee2: bc80 pop {r7} + 8000ee4: 4770 bx lr + +08000ee6 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000ee6: b580 push {r7, lr} + 8000ee8: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000eea: f000 f935 bl 8001158 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000eee: bf00 nop + 8000ef0: bd80 pop {r7, pc} + +08000ef2 <_getpid>: +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + 8000ef2: b480 push {r7} + 8000ef4: af00 add r7, sp, #0 + return 1; + 8000ef6: 2301 movs r3, #1 +} + 8000ef8: 4618 mov r0, r3 + 8000efa: 46bd mov sp, r7 + 8000efc: bc80 pop {r7} + 8000efe: 4770 bx lr + +08000f00 <_kill>: + +int _kill(int pid, int sig) +{ + 8000f00: b580 push {r7, lr} + 8000f02: b082 sub sp, #8 + 8000f04: af00 add r7, sp, #0 + 8000f06: 6078 str r0, [r7, #4] + 8000f08: 6039 str r1, [r7, #0] + errno = EINVAL; + 8000f0a: f001 fc79 bl 8002800 <__errno> + 8000f0e: 4603 mov r3, r0 + 8000f10: 2216 movs r2, #22 + 8000f12: 601a str r2, [r3, #0] + return -1; + 8000f14: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 8000f18: 4618 mov r0, r3 + 8000f1a: 3708 adds r7, #8 + 8000f1c: 46bd mov sp, r7 + 8000f1e: bd80 pop {r7, pc} + +08000f20 <_exit>: + +void _exit (int status) +{ + 8000f20: b580 push {r7, lr} + 8000f22: b082 sub sp, #8 + 8000f24: af00 add r7, sp, #0 + 8000f26: 6078 str r0, [r7, #4] + _kill(status, -1); + 8000f28: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8000f2c: 6878 ldr r0, [r7, #4] + 8000f2e: f7ff ffe7 bl 8000f00 <_kill> + while (1) {} /* Make sure we hang here */ + 8000f32: e7fe b.n 8000f32 <_exit+0x12> + +08000f34 <_read>: +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + 8000f34: b580 push {r7, lr} + 8000f36: b086 sub sp, #24 + 8000f38: af00 add r7, sp, #0 + 8000f3a: 60f8 str r0, [r7, #12] + 8000f3c: 60b9 str r1, [r7, #8] + 8000f3e: 607a str r2, [r7, #4] + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000f40: 2300 movs r3, #0 + 8000f42: 617b str r3, [r7, #20] + 8000f44: e00a b.n 8000f5c <_read+0x28> + { + *ptr++ = __io_getchar(); + 8000f46: f3af 8000 nop.w + 8000f4a: 4601 mov r1, r0 + 8000f4c: 68bb ldr r3, [r7, #8] + 8000f4e: 1c5a adds r2, r3, #1 + 8000f50: 60ba str r2, [r7, #8] + 8000f52: b2ca uxtb r2, r1 + 8000f54: 701a strb r2, [r3, #0] + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000f56: 697b ldr r3, [r7, #20] + 8000f58: 3301 adds r3, #1 + 8000f5a: 617b str r3, [r7, #20] + 8000f5c: 697a ldr r2, [r7, #20] + 8000f5e: 687b ldr r3, [r7, #4] + 8000f60: 429a cmp r2, r3 + 8000f62: dbf0 blt.n 8000f46 <_read+0x12> + } + +return len; + 8000f64: 687b ldr r3, [r7, #4] +} + 8000f66: 4618 mov r0, r3 + 8000f68: 3718 adds r7, #24 + 8000f6a: 46bd mov sp, r7 + 8000f6c: bd80 pop {r7, pc} + +08000f6e <_write>: + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + 8000f6e: b580 push {r7, lr} + 8000f70: b086 sub sp, #24 + 8000f72: af00 add r7, sp, #0 + 8000f74: 60f8 str r0, [r7, #12] + 8000f76: 60b9 str r1, [r7, #8] + 8000f78: 607a str r2, [r7, #4] + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000f7a: 2300 movs r3, #0 + 8000f7c: 617b str r3, [r7, #20] + 8000f7e: e009 b.n 8000f94 <_write+0x26> + { + __io_putchar(*ptr++); + 8000f80: 68bb ldr r3, [r7, #8] + 8000f82: 1c5a adds r2, r3, #1 + 8000f84: 60ba str r2, [r7, #8] + 8000f86: 781b ldrb r3, [r3, #0] + 8000f88: 4618 mov r0, r3 + 8000f8a: f3af 8000 nop.w + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000f8e: 697b ldr r3, [r7, #20] + 8000f90: 3301 adds r3, #1 + 8000f92: 617b str r3, [r7, #20] + 8000f94: 697a ldr r2, [r7, #20] + 8000f96: 687b ldr r3, [r7, #4] + 8000f98: 429a cmp r2, r3 + 8000f9a: dbf1 blt.n 8000f80 <_write+0x12> + } + return len; + 8000f9c: 687b ldr r3, [r7, #4] +} + 8000f9e: 4618 mov r0, r3 + 8000fa0: 3718 adds r7, #24 + 8000fa2: 46bd mov sp, r7 + 8000fa4: bd80 pop {r7, pc} + +08000fa6 <_close>: + +int _close(int file) +{ + 8000fa6: b480 push {r7} + 8000fa8: b083 sub sp, #12 + 8000faa: af00 add r7, sp, #0 + 8000fac: 6078 str r0, [r7, #4] + return -1; + 8000fae: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff +} + 8000fb2: 4618 mov r0, r3 + 8000fb4: 370c adds r7, #12 + 8000fb6: 46bd mov sp, r7 + 8000fb8: bc80 pop {r7} + 8000fba: 4770 bx lr + +08000fbc <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + 8000fbc: b480 push {r7} + 8000fbe: b083 sub sp, #12 + 8000fc0: af00 add r7, sp, #0 + 8000fc2: 6078 str r0, [r7, #4] + 8000fc4: 6039 str r1, [r7, #0] + st->st_mode = S_IFCHR; + 8000fc6: 683b ldr r3, [r7, #0] + 8000fc8: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8000fcc: 605a str r2, [r3, #4] + return 0; + 8000fce: 2300 movs r3, #0 +} + 8000fd0: 4618 mov r0, r3 + 8000fd2: 370c adds r7, #12 + 8000fd4: 46bd mov sp, r7 + 8000fd6: bc80 pop {r7} + 8000fd8: 4770 bx lr + +08000fda <_isatty>: + +int _isatty(int file) +{ + 8000fda: b480 push {r7} + 8000fdc: b083 sub sp, #12 + 8000fde: af00 add r7, sp, #0 + 8000fe0: 6078 str r0, [r7, #4] + return 1; + 8000fe2: 2301 movs r3, #1 +} + 8000fe4: 4618 mov r0, r3 + 8000fe6: 370c adds r7, #12 + 8000fe8: 46bd mov sp, r7 + 8000fea: bc80 pop {r7} + 8000fec: 4770 bx lr + +08000fee <_lseek>: + +int _lseek(int file, int ptr, int dir) +{ + 8000fee: b480 push {r7} + 8000ff0: b085 sub sp, #20 + 8000ff2: af00 add r7, sp, #0 + 8000ff4: 60f8 str r0, [r7, #12] + 8000ff6: 60b9 str r1, [r7, #8] + 8000ff8: 607a str r2, [r7, #4] + return 0; + 8000ffa: 2300 movs r3, #0 +} + 8000ffc: 4618 mov r0, r3 + 8000ffe: 3714 adds r7, #20 + 8001000: 46bd mov sp, r7 + 8001002: bc80 pop {r7} + 8001004: 4770 bx lr + ... + +08001008 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8001008: b580 push {r7, lr} + 800100a: b086 sub sp, #24 + 800100c: af00 add r7, sp, #0 + 800100e: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8001010: 4a14 ldr r2, [pc, #80] ; (8001064 <_sbrk+0x5c>) + 8001012: 4b15 ldr r3, [pc, #84] ; (8001068 <_sbrk+0x60>) + 8001014: 1ad3 subs r3, r2, r3 + 8001016: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 8001018: 697b ldr r3, [r7, #20] + 800101a: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 800101c: 4b13 ldr r3, [pc, #76] ; (800106c <_sbrk+0x64>) + 800101e: 681b ldr r3, [r3, #0] + 8001020: 2b00 cmp r3, #0 + 8001022: d102 bne.n 800102a <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8001024: 4b11 ldr r3, [pc, #68] ; (800106c <_sbrk+0x64>) + 8001026: 4a12 ldr r2, [pc, #72] ; (8001070 <_sbrk+0x68>) + 8001028: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 800102a: 4b10 ldr r3, [pc, #64] ; (800106c <_sbrk+0x64>) + 800102c: 681a ldr r2, [r3, #0] + 800102e: 687b ldr r3, [r7, #4] + 8001030: 4413 add r3, r2 + 8001032: 693a ldr r2, [r7, #16] + 8001034: 429a cmp r2, r3 + 8001036: d207 bcs.n 8001048 <_sbrk+0x40> + { + errno = ENOMEM; + 8001038: f001 fbe2 bl 8002800 <__errno> + 800103c: 4603 mov r3, r0 + 800103e: 220c movs r2, #12 + 8001040: 601a str r2, [r3, #0] + return (void *)-1; + 8001042: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8001046: e009 b.n 800105c <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8001048: 4b08 ldr r3, [pc, #32] ; (800106c <_sbrk+0x64>) + 800104a: 681b ldr r3, [r3, #0] + 800104c: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 800104e: 4b07 ldr r3, [pc, #28] ; (800106c <_sbrk+0x64>) + 8001050: 681a ldr r2, [r3, #0] + 8001052: 687b ldr r3, [r7, #4] + 8001054: 4413 add r3, r2 + 8001056: 4a05 ldr r2, [pc, #20] ; (800106c <_sbrk+0x64>) + 8001058: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 800105a: 68fb ldr r3, [r7, #12] +} + 800105c: 4618 mov r0, r3 + 800105e: 3718 adds r7, #24 + 8001060: 46bd mov sp, r7 + 8001062: bd80 pop {r7, pc} + 8001064: 20010000 .word 0x20010000 + 8001068: 00000400 .word 0x00000400 + 800106c: 200001fc .word 0x200001fc + 8001070: 20000270 .word 0x20000270 + +08001074 : + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8001074: b480 push {r7} + 8001076: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8001078: bf00 nop + 800107a: 46bd mov sp, r7 + 800107c: bc80 pop {r7} + 800107e: 4770 bx lr + +08001080 : + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8001080: 480c ldr r0, [pc, #48] ; (80010b4 ) + ldr r1, =_edata + 8001082: 490d ldr r1, [pc, #52] ; (80010b8 ) + ldr r2, =_sidata + 8001084: 4a0d ldr r2, [pc, #52] ; (80010bc ) + movs r3, #0 + 8001086: 2300 movs r3, #0 + b LoopCopyDataInit + 8001088: e002 b.n 8001090 + +0800108a : + +CopyDataInit: + ldr r4, [r2, r3] + 800108a: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 800108c: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 800108e: 3304 adds r3, #4 + +08001090 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8001090: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8001092: 428c cmp r4, r1 + bcc CopyDataInit + 8001094: d3f9 bcc.n 800108a + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8001096: 4a0a ldr r2, [pc, #40] ; (80010c0 ) + ldr r4, =_ebss + 8001098: 4c0a ldr r4, [pc, #40] ; (80010c4 ) + movs r3, #0 + 800109a: 2300 movs r3, #0 + b LoopFillZerobss + 800109c: e001 b.n 80010a2 + +0800109e : + +FillZerobss: + str r3, [r2] + 800109e: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80010a0: 3204 adds r2, #4 + +080010a2 : + +LoopFillZerobss: + cmp r2, r4 + 80010a2: 42a2 cmp r2, r4 + bcc FillZerobss + 80010a4: d3fb bcc.n 800109e + +/* Call the clock system intitialization function.*/ + bl SystemInit + 80010a6: f7ff ffe5 bl 8001074 +/* Call static constructors */ + bl __libc_init_array + 80010aa: f001 fbaf bl 800280c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 80010ae: f7ff fd57 bl 8000b60
+ bx lr + 80010b2: 4770 bx lr + ldr r0, =_sdata + 80010b4: 20000000 .word 0x20000000 + ldr r1, =_edata + 80010b8: 200001dc .word 0x200001dc + ldr r2, =_sidata + 80010bc: 08005634 .word 0x08005634 + ldr r2, =_sbss + 80010c0: 200001dc .word 0x200001dc + ldr r4, =_ebss + 80010c4: 20000270 .word 0x20000270 + +080010c8 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80010c8: e7fe b.n 80010c8 + ... + +080010cc : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80010cc: b580 push {r7, lr} + 80010ce: af00 add r7, sp, #0 + defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ + defined(STM32F105xC) || defined(STM32F107xC) + + /* Prefetch buffer is not available on value line devices */ + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 80010d0: 4b08 ldr r3, [pc, #32] ; (80010f4 ) + 80010d2: 681b ldr r3, [r3, #0] + 80010d4: 4a07 ldr r2, [pc, #28] ; (80010f4 ) + 80010d6: f043 0310 orr.w r3, r3, #16 + 80010da: 6013 str r3, [r2, #0] +#endif +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 80010dc: 2003 movs r0, #3 + 80010de: f000 f92b bl 8001338 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 80010e2: 200f movs r0, #15 + 80010e4: f000 f808 bl 80010f8 + + /* Init the low level hardware */ + HAL_MspInit(); + 80010e8: f7ff fe4c bl 8000d84 + + /* Return function status */ + return HAL_OK; + 80010ec: 2300 movs r3, #0 +} + 80010ee: 4618 mov r0, r3 + 80010f0: bd80 pop {r7, pc} + 80010f2: bf00 nop + 80010f4: 40022000 .word 0x40022000 + +080010f8 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80010f8: b580 push {r7, lr} + 80010fa: b082 sub sp, #8 + 80010fc: af00 add r7, sp, #0 + 80010fe: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8001100: 4b12 ldr r3, [pc, #72] ; (800114c ) + 8001102: 681a ldr r2, [r3, #0] + 8001104: 4b12 ldr r3, [pc, #72] ; (8001150 ) + 8001106: 781b ldrb r3, [r3, #0] + 8001108: 4619 mov r1, r3 + 800110a: f44f 737a mov.w r3, #1000 ; 0x3e8 + 800110e: fbb3 f3f1 udiv r3, r3, r1 + 8001112: fbb2 f3f3 udiv r3, r2, r3 + 8001116: 4618 mov r0, r3 + 8001118: f000 f935 bl 8001386 + 800111c: 4603 mov r3, r0 + 800111e: 2b00 cmp r3, #0 + 8001120: d001 beq.n 8001126 + { + return HAL_ERROR; + 8001122: 2301 movs r3, #1 + 8001124: e00e b.n 8001144 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001126: 687b ldr r3, [r7, #4] + 8001128: 2b0f cmp r3, #15 + 800112a: d80a bhi.n 8001142 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 800112c: 2200 movs r2, #0 + 800112e: 6879 ldr r1, [r7, #4] + 8001130: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001134: f000 f90b bl 800134e + uwTickPrio = TickPriority; + 8001138: 4a06 ldr r2, [pc, #24] ; (8001154 ) + 800113a: 687b ldr r3, [r7, #4] + 800113c: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 800113e: 2300 movs r3, #0 + 8001140: e000 b.n 8001144 + return HAL_ERROR; + 8001142: 2301 movs r3, #1 +} + 8001144: 4618 mov r0, r3 + 8001146: 3708 adds r7, #8 + 8001148: 46bd mov sp, r7 + 800114a: bd80 pop {r7, pc} + 800114c: 20000000 .word 0x20000000 + 8001150: 20000008 .word 0x20000008 + 8001154: 20000004 .word 0x20000004 + +08001158 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001158: b480 push {r7} + 800115a: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 800115c: 4b05 ldr r3, [pc, #20] ; (8001174 ) + 800115e: 781b ldrb r3, [r3, #0] + 8001160: 461a mov r2, r3 + 8001162: 4b05 ldr r3, [pc, #20] ; (8001178 ) + 8001164: 681b ldr r3, [r3, #0] + 8001166: 4413 add r3, r2 + 8001168: 4a03 ldr r2, [pc, #12] ; (8001178 ) + 800116a: 6013 str r3, [r2, #0] +} + 800116c: bf00 nop + 800116e: 46bd mov sp, r7 + 8001170: bc80 pop {r7} + 8001172: 4770 bx lr + 8001174: 20000008 .word 0x20000008 + 8001178: 20000250 .word 0x20000250 + +0800117c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 800117c: b480 push {r7} + 800117e: af00 add r7, sp, #0 + return uwTick; + 8001180: 4b02 ldr r3, [pc, #8] ; (800118c ) + 8001182: 681b ldr r3, [r3, #0] +} + 8001184: 4618 mov r0, r3 + 8001186: 46bd mov sp, r7 + 8001188: bc80 pop {r7} + 800118a: 4770 bx lr + 800118c: 20000250 .word 0x20000250 + +08001190 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8001190: b580 push {r7, lr} + 8001192: b084 sub sp, #16 + 8001194: af00 add r7, sp, #0 + 8001196: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8001198: f7ff fff0 bl 800117c + 800119c: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 800119e: 687b ldr r3, [r7, #4] + 80011a0: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 80011a2: 68fb ldr r3, [r7, #12] + 80011a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80011a8: d005 beq.n 80011b6 + { + wait += (uint32_t)(uwTickFreq); + 80011aa: 4b0a ldr r3, [pc, #40] ; (80011d4 ) + 80011ac: 781b ldrb r3, [r3, #0] + 80011ae: 461a mov r2, r3 + 80011b0: 68fb ldr r3, [r7, #12] + 80011b2: 4413 add r3, r2 + 80011b4: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 80011b6: bf00 nop + 80011b8: f7ff ffe0 bl 800117c + 80011bc: 4602 mov r2, r0 + 80011be: 68bb ldr r3, [r7, #8] + 80011c0: 1ad3 subs r3, r2, r3 + 80011c2: 68fa ldr r2, [r7, #12] + 80011c4: 429a cmp r2, r3 + 80011c6: d8f7 bhi.n 80011b8 + { + } +} + 80011c8: bf00 nop + 80011ca: bf00 nop + 80011cc: 3710 adds r7, #16 + 80011ce: 46bd mov sp, r7 + 80011d0: bd80 pop {r7, pc} + 80011d2: bf00 nop + 80011d4: 20000008 .word 0x20000008 + +080011d8 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80011d8: b480 push {r7} + 80011da: b085 sub sp, #20 + 80011dc: af00 add r7, sp, #0 + 80011de: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80011e0: 687b ldr r3, [r7, #4] + 80011e2: f003 0307 and.w r3, r3, #7 + 80011e6: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80011e8: 4b0c ldr r3, [pc, #48] ; (800121c <__NVIC_SetPriorityGrouping+0x44>) + 80011ea: 68db ldr r3, [r3, #12] + 80011ec: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 80011ee: 68ba ldr r2, [r7, #8] + 80011f0: f64f 03ff movw r3, #63743 ; 0xf8ff + 80011f4: 4013 ands r3, r2 + 80011f6: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 80011f8: 68fb ldr r3, [r7, #12] + 80011fa: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 80011fc: 68bb ldr r3, [r7, #8] + 80011fe: 4313 orrs r3, r2 + reg_value = (reg_value | + 8001200: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8001204: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001208: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 800120a: 4a04 ldr r2, [pc, #16] ; (800121c <__NVIC_SetPriorityGrouping+0x44>) + 800120c: 68bb ldr r3, [r7, #8] + 800120e: 60d3 str r3, [r2, #12] +} + 8001210: bf00 nop + 8001212: 3714 adds r7, #20 + 8001214: 46bd mov sp, r7 + 8001216: bc80 pop {r7} + 8001218: 4770 bx lr + 800121a: bf00 nop + 800121c: e000ed00 .word 0xe000ed00 + +08001220 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001220: b480 push {r7} + 8001222: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001224: 4b04 ldr r3, [pc, #16] ; (8001238 <__NVIC_GetPriorityGrouping+0x18>) + 8001226: 68db ldr r3, [r3, #12] + 8001228: 0a1b lsrs r3, r3, #8 + 800122a: f003 0307 and.w r3, r3, #7 +} + 800122e: 4618 mov r0, r3 + 8001230: 46bd mov sp, r7 + 8001232: bc80 pop {r7} + 8001234: 4770 bx lr + 8001236: bf00 nop + 8001238: e000ed00 .word 0xe000ed00 + +0800123c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 800123c: b480 push {r7} + 800123e: b083 sub sp, #12 + 8001240: af00 add r7, sp, #0 + 8001242: 4603 mov r3, r0 + 8001244: 6039 str r1, [r7, #0] + 8001246: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001248: f997 3007 ldrsb.w r3, [r7, #7] + 800124c: 2b00 cmp r3, #0 + 800124e: db0a blt.n 8001266 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001250: 683b ldr r3, [r7, #0] + 8001252: b2da uxtb r2, r3 + 8001254: 490c ldr r1, [pc, #48] ; (8001288 <__NVIC_SetPriority+0x4c>) + 8001256: f997 3007 ldrsb.w r3, [r7, #7] + 800125a: 0112 lsls r2, r2, #4 + 800125c: b2d2 uxtb r2, r2 + 800125e: 440b add r3, r1 + 8001260: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8001264: e00a b.n 800127c <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001266: 683b ldr r3, [r7, #0] + 8001268: b2da uxtb r2, r3 + 800126a: 4908 ldr r1, [pc, #32] ; (800128c <__NVIC_SetPriority+0x50>) + 800126c: 79fb ldrb r3, [r7, #7] + 800126e: f003 030f and.w r3, r3, #15 + 8001272: 3b04 subs r3, #4 + 8001274: 0112 lsls r2, r2, #4 + 8001276: b2d2 uxtb r2, r2 + 8001278: 440b add r3, r1 + 800127a: 761a strb r2, [r3, #24] +} + 800127c: bf00 nop + 800127e: 370c adds r7, #12 + 8001280: 46bd mov sp, r7 + 8001282: bc80 pop {r7} + 8001284: 4770 bx lr + 8001286: bf00 nop + 8001288: e000e100 .word 0xe000e100 + 800128c: e000ed00 .word 0xe000ed00 + +08001290 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001290: b480 push {r7} + 8001292: b089 sub sp, #36 ; 0x24 + 8001294: af00 add r7, sp, #0 + 8001296: 60f8 str r0, [r7, #12] + 8001298: 60b9 str r1, [r7, #8] + 800129a: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 800129c: 68fb ldr r3, [r7, #12] + 800129e: f003 0307 and.w r3, r3, #7 + 80012a2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80012a4: 69fb ldr r3, [r7, #28] + 80012a6: f1c3 0307 rsb r3, r3, #7 + 80012aa: 2b04 cmp r3, #4 + 80012ac: bf28 it cs + 80012ae: 2304 movcs r3, #4 + 80012b0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 80012b2: 69fb ldr r3, [r7, #28] + 80012b4: 3304 adds r3, #4 + 80012b6: 2b06 cmp r3, #6 + 80012b8: d902 bls.n 80012c0 + 80012ba: 69fb ldr r3, [r7, #28] + 80012bc: 3b03 subs r3, #3 + 80012be: e000 b.n 80012c2 + 80012c0: 2300 movs r3, #0 + 80012c2: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80012c4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80012c8: 69bb ldr r3, [r7, #24] + 80012ca: fa02 f303 lsl.w r3, r2, r3 + 80012ce: 43da mvns r2, r3 + 80012d0: 68bb ldr r3, [r7, #8] + 80012d2: 401a ands r2, r3 + 80012d4: 697b ldr r3, [r7, #20] + 80012d6: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 80012d8: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 80012dc: 697b ldr r3, [r7, #20] + 80012de: fa01 f303 lsl.w r3, r1, r3 + 80012e2: 43d9 mvns r1, r3 + 80012e4: 687b ldr r3, [r7, #4] + 80012e6: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80012e8: 4313 orrs r3, r2 + ); +} + 80012ea: 4618 mov r0, r3 + 80012ec: 3724 adds r7, #36 ; 0x24 + 80012ee: 46bd mov sp, r7 + 80012f0: bc80 pop {r7} + 80012f2: 4770 bx lr + +080012f4 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 80012f4: b580 push {r7, lr} + 80012f6: b082 sub sp, #8 + 80012f8: af00 add r7, sp, #0 + 80012fa: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 80012fc: 687b ldr r3, [r7, #4] + 80012fe: 3b01 subs r3, #1 + 8001300: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8001304: d301 bcc.n 800130a + { + return (1UL); /* Reload value impossible */ + 8001306: 2301 movs r3, #1 + 8001308: e00f b.n 800132a + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 800130a: 4a0a ldr r2, [pc, #40] ; (8001334 ) + 800130c: 687b ldr r3, [r7, #4] + 800130e: 3b01 subs r3, #1 + 8001310: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001312: 210f movs r1, #15 + 8001314: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001318: f7ff ff90 bl 800123c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 800131c: 4b05 ldr r3, [pc, #20] ; (8001334 ) + 800131e: 2200 movs r2, #0 + 8001320: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001322: 4b04 ldr r3, [pc, #16] ; (8001334 ) + 8001324: 2207 movs r2, #7 + 8001326: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8001328: 2300 movs r3, #0 +} + 800132a: 4618 mov r0, r3 + 800132c: 3708 adds r7, #8 + 800132e: 46bd mov sp, r7 + 8001330: bd80 pop {r7, pc} + 8001332: bf00 nop + 8001334: e000e010 .word 0xe000e010 + +08001338 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001338: b580 push {r7, lr} + 800133a: b082 sub sp, #8 + 800133c: af00 add r7, sp, #0 + 800133e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001340: 6878 ldr r0, [r7, #4] + 8001342: f7ff ff49 bl 80011d8 <__NVIC_SetPriorityGrouping> +} + 8001346: bf00 nop + 8001348: 3708 adds r7, #8 + 800134a: 46bd mov sp, r7 + 800134c: bd80 pop {r7, pc} + +0800134e : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 800134e: b580 push {r7, lr} + 8001350: b086 sub sp, #24 + 8001352: af00 add r7, sp, #0 + 8001354: 4603 mov r3, r0 + 8001356: 60b9 str r1, [r7, #8] + 8001358: 607a str r2, [r7, #4] + 800135a: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 800135c: 2300 movs r3, #0 + 800135e: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001360: f7ff ff5e bl 8001220 <__NVIC_GetPriorityGrouping> + 8001364: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001366: 687a ldr r2, [r7, #4] + 8001368: 68b9 ldr r1, [r7, #8] + 800136a: 6978 ldr r0, [r7, #20] + 800136c: f7ff ff90 bl 8001290 + 8001370: 4602 mov r2, r0 + 8001372: f997 300f ldrsb.w r3, [r7, #15] + 8001376: 4611 mov r1, r2 + 8001378: 4618 mov r0, r3 + 800137a: f7ff ff5f bl 800123c <__NVIC_SetPriority> +} + 800137e: bf00 nop + 8001380: 3718 adds r7, #24 + 8001382: 46bd mov sp, r7 + 8001384: bd80 pop {r7, pc} + +08001386 : + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8001386: b580 push {r7, lr} + 8001388: b082 sub sp, #8 + 800138a: af00 add r7, sp, #0 + 800138c: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 800138e: 6878 ldr r0, [r7, #4] + 8001390: f7ff ffb0 bl 80012f4 + 8001394: 4603 mov r3, r0 +} + 8001396: 4618 mov r0, r3 + 8001398: 3708 adds r7, #8 + 800139a: 46bd mov sp, r7 + 800139c: bd80 pop {r7, pc} + ... + +080013a0 : + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80013a0: b480 push {r7} + 80013a2: b08b sub sp, #44 ; 0x2c + 80013a4: af00 add r7, sp, #0 + 80013a6: 6078 str r0, [r7, #4] + 80013a8: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 80013aa: 2300 movs r3, #0 + 80013ac: 627b str r3, [r7, #36] ; 0x24 + uint32_t ioposition; + uint32_t iocurrent; + uint32_t temp; + uint32_t config = 0x00u; + 80013ae: 2300 movs r3, #0 + 80013b0: 623b str r3, [r7, #32] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80013b2: e179 b.n 80016a8 + { + /* Get the IO position */ + ioposition = (0x01uL << position); + 80013b4: 2201 movs r2, #1 + 80013b6: 6a7b ldr r3, [r7, #36] ; 0x24 + 80013b8: fa02 f303 lsl.w r3, r2, r3 + 80013bc: 61fb str r3, [r7, #28] + + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 80013be: 683b ldr r3, [r7, #0] + 80013c0: 681b ldr r3, [r3, #0] + 80013c2: 69fa ldr r2, [r7, #28] + 80013c4: 4013 ands r3, r2 + 80013c6: 61bb str r3, [r7, #24] + + if (iocurrent == ioposition) + 80013c8: 69ba ldr r2, [r7, #24] + 80013ca: 69fb ldr r3, [r7, #28] + 80013cc: 429a cmp r2, r3 + 80013ce: f040 8168 bne.w 80016a2 + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + + /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ + switch (GPIO_Init->Mode) + 80013d2: 683b ldr r3, [r7, #0] + 80013d4: 685b ldr r3, [r3, #4] + 80013d6: 4aa0 ldr r2, [pc, #640] ; (8001658 ) + 80013d8: 4293 cmp r3, r2 + 80013da: d05e beq.n 800149a + 80013dc: 4a9e ldr r2, [pc, #632] ; (8001658 ) + 80013de: 4293 cmp r3, r2 + 80013e0: d875 bhi.n 80014ce + 80013e2: 4a9e ldr r2, [pc, #632] ; (800165c ) + 80013e4: 4293 cmp r3, r2 + 80013e6: d058 beq.n 800149a + 80013e8: 4a9c ldr r2, [pc, #624] ; (800165c ) + 80013ea: 4293 cmp r3, r2 + 80013ec: d86f bhi.n 80014ce + 80013ee: 4a9c ldr r2, [pc, #624] ; (8001660 ) + 80013f0: 4293 cmp r3, r2 + 80013f2: d052 beq.n 800149a + 80013f4: 4a9a ldr r2, [pc, #616] ; (8001660 ) + 80013f6: 4293 cmp r3, r2 + 80013f8: d869 bhi.n 80014ce + 80013fa: 4a9a ldr r2, [pc, #616] ; (8001664 ) + 80013fc: 4293 cmp r3, r2 + 80013fe: d04c beq.n 800149a + 8001400: 4a98 ldr r2, [pc, #608] ; (8001664 ) + 8001402: 4293 cmp r3, r2 + 8001404: d863 bhi.n 80014ce + 8001406: 4a98 ldr r2, [pc, #608] ; (8001668 ) + 8001408: 4293 cmp r3, r2 + 800140a: d046 beq.n 800149a + 800140c: 4a96 ldr r2, [pc, #600] ; (8001668 ) + 800140e: 4293 cmp r3, r2 + 8001410: d85d bhi.n 80014ce + 8001412: 2b12 cmp r3, #18 + 8001414: d82a bhi.n 800146c + 8001416: 2b12 cmp r3, #18 + 8001418: d859 bhi.n 80014ce + 800141a: a201 add r2, pc, #4 ; (adr r2, 8001420 ) + 800141c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8001420: 0800149b .word 0x0800149b + 8001424: 08001475 .word 0x08001475 + 8001428: 08001487 .word 0x08001487 + 800142c: 080014c9 .word 0x080014c9 + 8001430: 080014cf .word 0x080014cf + 8001434: 080014cf .word 0x080014cf + 8001438: 080014cf .word 0x080014cf + 800143c: 080014cf .word 0x080014cf + 8001440: 080014cf .word 0x080014cf + 8001444: 080014cf .word 0x080014cf + 8001448: 080014cf .word 0x080014cf + 800144c: 080014cf .word 0x080014cf + 8001450: 080014cf .word 0x080014cf + 8001454: 080014cf .word 0x080014cf + 8001458: 080014cf .word 0x080014cf + 800145c: 080014cf .word 0x080014cf + 8001460: 080014cf .word 0x080014cf + 8001464: 0800147d .word 0x0800147d + 8001468: 08001491 .word 0x08001491 + 800146c: 4a7f ldr r2, [pc, #508] ; (800166c ) + 800146e: 4293 cmp r3, r2 + 8001470: d013 beq.n 800149a + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + break; + + /* Parameters are checked with assert_param */ + default: + break; + 8001472: e02c b.n 80014ce + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; + 8001474: 683b ldr r3, [r7, #0] + 8001476: 68db ldr r3, [r3, #12] + 8001478: 623b str r3, [r7, #32] + break; + 800147a: e029 b.n 80014d0 + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; + 800147c: 683b ldr r3, [r7, #0] + 800147e: 68db ldr r3, [r3, #12] + 8001480: 3304 adds r3, #4 + 8001482: 623b str r3, [r7, #32] + break; + 8001484: e024 b.n 80014d0 + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; + 8001486: 683b ldr r3, [r7, #0] + 8001488: 68db ldr r3, [r3, #12] + 800148a: 3308 adds r3, #8 + 800148c: 623b str r3, [r7, #32] + break; + 800148e: e01f b.n 80014d0 + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; + 8001490: 683b ldr r3, [r7, #0] + 8001492: 68db ldr r3, [r3, #12] + 8001494: 330c adds r3, #12 + 8001496: 623b str r3, [r7, #32] + break; + 8001498: e01a b.n 80014d0 + if (GPIO_Init->Pull == GPIO_NOPULL) + 800149a: 683b ldr r3, [r7, #0] + 800149c: 689b ldr r3, [r3, #8] + 800149e: 2b00 cmp r3, #0 + 80014a0: d102 bne.n 80014a8 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; + 80014a2: 2304 movs r3, #4 + 80014a4: 623b str r3, [r7, #32] + break; + 80014a6: e013 b.n 80014d0 + else if (GPIO_Init->Pull == GPIO_PULLUP) + 80014a8: 683b ldr r3, [r7, #0] + 80014aa: 689b ldr r3, [r3, #8] + 80014ac: 2b01 cmp r3, #1 + 80014ae: d105 bne.n 80014bc + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + 80014b0: 2308 movs r3, #8 + 80014b2: 623b str r3, [r7, #32] + GPIOx->BSRR = ioposition; + 80014b4: 687b ldr r3, [r7, #4] + 80014b6: 69fa ldr r2, [r7, #28] + 80014b8: 611a str r2, [r3, #16] + break; + 80014ba: e009 b.n 80014d0 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + 80014bc: 2308 movs r3, #8 + 80014be: 623b str r3, [r7, #32] + GPIOx->BRR = ioposition; + 80014c0: 687b ldr r3, [r7, #4] + 80014c2: 69fa ldr r2, [r7, #28] + 80014c4: 615a str r2, [r3, #20] + break; + 80014c6: e003 b.n 80014d0 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + 80014c8: 2300 movs r3, #0 + 80014ca: 623b str r3, [r7, #32] + break; + 80014cc: e000 b.n 80014d0 + break; + 80014ce: bf00 nop + } + + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register*/ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + 80014d0: 69bb ldr r3, [r7, #24] + 80014d2: 2bff cmp r3, #255 ; 0xff + 80014d4: d801 bhi.n 80014da + 80014d6: 687b ldr r3, [r7, #4] + 80014d8: e001 b.n 80014de + 80014da: 687b ldr r3, [r7, #4] + 80014dc: 3304 adds r3, #4 + 80014de: 617b str r3, [r7, #20] + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + 80014e0: 69bb ldr r3, [r7, #24] + 80014e2: 2bff cmp r3, #255 ; 0xff + 80014e4: d802 bhi.n 80014ec + 80014e6: 6a7b ldr r3, [r7, #36] ; 0x24 + 80014e8: 009b lsls r3, r3, #2 + 80014ea: e002 b.n 80014f2 + 80014ec: 6a7b ldr r3, [r7, #36] ; 0x24 + 80014ee: 3b08 subs r3, #8 + 80014f0: 009b lsls r3, r3, #2 + 80014f2: 613b str r3, [r7, #16] + + /* Apply the new configuration of the pin to the register */ + MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); + 80014f4: 697b ldr r3, [r7, #20] + 80014f6: 681a ldr r2, [r3, #0] + 80014f8: 210f movs r1, #15 + 80014fa: 693b ldr r3, [r7, #16] + 80014fc: fa01 f303 lsl.w r3, r1, r3 + 8001500: 43db mvns r3, r3 + 8001502: 401a ands r2, r3 + 8001504: 6a39 ldr r1, [r7, #32] + 8001506: 693b ldr r3, [r7, #16] + 8001508: fa01 f303 lsl.w r3, r1, r3 + 800150c: 431a orrs r2, r3 + 800150e: 697b ldr r3, [r7, #20] + 8001510: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 8001512: 683b ldr r3, [r7, #0] + 8001514: 685b ldr r3, [r3, #4] + 8001516: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800151a: 2b00 cmp r3, #0 + 800151c: f000 80c1 beq.w 80016a2 + { + /* Enable AFIO Clock */ + __HAL_RCC_AFIO_CLK_ENABLE(); + 8001520: 4b53 ldr r3, [pc, #332] ; (8001670 ) + 8001522: 699b ldr r3, [r3, #24] + 8001524: 4a52 ldr r2, [pc, #328] ; (8001670 ) + 8001526: f043 0301 orr.w r3, r3, #1 + 800152a: 6193 str r3, [r2, #24] + 800152c: 4b50 ldr r3, [pc, #320] ; (8001670 ) + 800152e: 699b ldr r3, [r3, #24] + 8001530: f003 0301 and.w r3, r3, #1 + 8001534: 60bb str r3, [r7, #8] + 8001536: 68bb ldr r3, [r7, #8] + temp = AFIO->EXTICR[position >> 2u]; + 8001538: 4a4e ldr r2, [pc, #312] ; (8001674 ) + 800153a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800153c: 089b lsrs r3, r3, #2 + 800153e: 3302 adds r3, #2 + 8001540: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001544: 60fb str r3, [r7, #12] + CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); + 8001546: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001548: f003 0303 and.w r3, r3, #3 + 800154c: 009b lsls r3, r3, #2 + 800154e: 220f movs r2, #15 + 8001550: fa02 f303 lsl.w r3, r2, r3 + 8001554: 43db mvns r3, r3 + 8001556: 68fa ldr r2, [r7, #12] + 8001558: 4013 ands r3, r2 + 800155a: 60fb str r3, [r7, #12] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); + 800155c: 687b ldr r3, [r7, #4] + 800155e: 4a46 ldr r2, [pc, #280] ; (8001678 ) + 8001560: 4293 cmp r3, r2 + 8001562: d01f beq.n 80015a4 + 8001564: 687b ldr r3, [r7, #4] + 8001566: 4a45 ldr r2, [pc, #276] ; (800167c ) + 8001568: 4293 cmp r3, r2 + 800156a: d019 beq.n 80015a0 + 800156c: 687b ldr r3, [r7, #4] + 800156e: 4a44 ldr r2, [pc, #272] ; (8001680 ) + 8001570: 4293 cmp r3, r2 + 8001572: d013 beq.n 800159c + 8001574: 687b ldr r3, [r7, #4] + 8001576: 4a43 ldr r2, [pc, #268] ; (8001684 ) + 8001578: 4293 cmp r3, r2 + 800157a: d00d beq.n 8001598 + 800157c: 687b ldr r3, [r7, #4] + 800157e: 4a42 ldr r2, [pc, #264] ; (8001688 ) + 8001580: 4293 cmp r3, r2 + 8001582: d007 beq.n 8001594 + 8001584: 687b ldr r3, [r7, #4] + 8001586: 4a41 ldr r2, [pc, #260] ; (800168c ) + 8001588: 4293 cmp r3, r2 + 800158a: d101 bne.n 8001590 + 800158c: 2305 movs r3, #5 + 800158e: e00a b.n 80015a6 + 8001590: 2306 movs r3, #6 + 8001592: e008 b.n 80015a6 + 8001594: 2304 movs r3, #4 + 8001596: e006 b.n 80015a6 + 8001598: 2303 movs r3, #3 + 800159a: e004 b.n 80015a6 + 800159c: 2302 movs r3, #2 + 800159e: e002 b.n 80015a6 + 80015a0: 2301 movs r3, #1 + 80015a2: e000 b.n 80015a6 + 80015a4: 2300 movs r3, #0 + 80015a6: 6a7a ldr r2, [r7, #36] ; 0x24 + 80015a8: f002 0203 and.w r2, r2, #3 + 80015ac: 0092 lsls r2, r2, #2 + 80015ae: 4093 lsls r3, r2 + 80015b0: 68fa ldr r2, [r7, #12] + 80015b2: 4313 orrs r3, r2 + 80015b4: 60fb str r3, [r7, #12] + AFIO->EXTICR[position >> 2u] = temp; + 80015b6: 492f ldr r1, [pc, #188] ; (8001674 ) + 80015b8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80015ba: 089b lsrs r3, r3, #2 + 80015bc: 3302 adds r3, #2 + 80015be: 68fa ldr r2, [r7, #12] + 80015c0: f841 2023 str.w r2, [r1, r3, lsl #2] + + + /* Configure the interrupt mask */ + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80015c4: 683b ldr r3, [r7, #0] + 80015c6: 685b ldr r3, [r3, #4] + 80015c8: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80015cc: 2b00 cmp r3, #0 + 80015ce: d006 beq.n 80015de + { + SET_BIT(EXTI->IMR, iocurrent); + 80015d0: 4b2f ldr r3, [pc, #188] ; (8001690 ) + 80015d2: 681a ldr r2, [r3, #0] + 80015d4: 492e ldr r1, [pc, #184] ; (8001690 ) + 80015d6: 69bb ldr r3, [r7, #24] + 80015d8: 4313 orrs r3, r2 + 80015da: 600b str r3, [r1, #0] + 80015dc: e006 b.n 80015ec + } + else + { + CLEAR_BIT(EXTI->IMR, iocurrent); + 80015de: 4b2c ldr r3, [pc, #176] ; (8001690 ) + 80015e0: 681a ldr r2, [r3, #0] + 80015e2: 69bb ldr r3, [r7, #24] + 80015e4: 43db mvns r3, r3 + 80015e6: 492a ldr r1, [pc, #168] ; (8001690 ) + 80015e8: 4013 ands r3, r2 + 80015ea: 600b str r3, [r1, #0] + } + + /* Configure the event mask */ + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80015ec: 683b ldr r3, [r7, #0] + 80015ee: 685b ldr r3, [r3, #4] + 80015f0: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80015f4: 2b00 cmp r3, #0 + 80015f6: d006 beq.n 8001606 + { + SET_BIT(EXTI->EMR, iocurrent); + 80015f8: 4b25 ldr r3, [pc, #148] ; (8001690 ) + 80015fa: 685a ldr r2, [r3, #4] + 80015fc: 4924 ldr r1, [pc, #144] ; (8001690 ) + 80015fe: 69bb ldr r3, [r7, #24] + 8001600: 4313 orrs r3, r2 + 8001602: 604b str r3, [r1, #4] + 8001604: e006 b.n 8001614 + } + else + { + CLEAR_BIT(EXTI->EMR, iocurrent); + 8001606: 4b22 ldr r3, [pc, #136] ; (8001690 ) + 8001608: 685a ldr r2, [r3, #4] + 800160a: 69bb ldr r3, [r7, #24] + 800160c: 43db mvns r3, r3 + 800160e: 4920 ldr r1, [pc, #128] ; (8001690 ) + 8001610: 4013 ands r3, r2 + 8001612: 604b str r3, [r1, #4] + } + + /* Enable or disable the rising trigger */ + if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8001614: 683b ldr r3, [r7, #0] + 8001616: 685b ldr r3, [r3, #4] + 8001618: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800161c: 2b00 cmp r3, #0 + 800161e: d006 beq.n 800162e + { + SET_BIT(EXTI->RTSR, iocurrent); + 8001620: 4b1b ldr r3, [pc, #108] ; (8001690 ) + 8001622: 689a ldr r2, [r3, #8] + 8001624: 491a ldr r1, [pc, #104] ; (8001690 ) + 8001626: 69bb ldr r3, [r7, #24] + 8001628: 4313 orrs r3, r2 + 800162a: 608b str r3, [r1, #8] + 800162c: e006 b.n 800163c + } + else + { + CLEAR_BIT(EXTI->RTSR, iocurrent); + 800162e: 4b18 ldr r3, [pc, #96] ; (8001690 ) + 8001630: 689a ldr r2, [r3, #8] + 8001632: 69bb ldr r3, [r7, #24] + 8001634: 43db mvns r3, r3 + 8001636: 4916 ldr r1, [pc, #88] ; (8001690 ) + 8001638: 4013 ands r3, r2 + 800163a: 608b str r3, [r1, #8] + } + + /* Enable or disable the falling trigger */ + if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 800163c: 683b ldr r3, [r7, #0] + 800163e: 685b ldr r3, [r3, #4] + 8001640: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001644: 2b00 cmp r3, #0 + 8001646: d025 beq.n 8001694 + { + SET_BIT(EXTI->FTSR, iocurrent); + 8001648: 4b11 ldr r3, [pc, #68] ; (8001690 ) + 800164a: 68da ldr r2, [r3, #12] + 800164c: 4910 ldr r1, [pc, #64] ; (8001690 ) + 800164e: 69bb ldr r3, [r7, #24] + 8001650: 4313 orrs r3, r2 + 8001652: 60cb str r3, [r1, #12] + 8001654: e025 b.n 80016a2 + 8001656: bf00 nop + 8001658: 10320000 .word 0x10320000 + 800165c: 10310000 .word 0x10310000 + 8001660: 10220000 .word 0x10220000 + 8001664: 10210000 .word 0x10210000 + 8001668: 10120000 .word 0x10120000 + 800166c: 10110000 .word 0x10110000 + 8001670: 40021000 .word 0x40021000 + 8001674: 40010000 .word 0x40010000 + 8001678: 40010800 .word 0x40010800 + 800167c: 40010c00 .word 0x40010c00 + 8001680: 40011000 .word 0x40011000 + 8001684: 40011400 .word 0x40011400 + 8001688: 40011800 .word 0x40011800 + 800168c: 40011c00 .word 0x40011c00 + 8001690: 40010400 .word 0x40010400 + } + else + { + CLEAR_BIT(EXTI->FTSR, iocurrent); + 8001694: 4b0b ldr r3, [pc, #44] ; (80016c4 ) + 8001696: 68da ldr r2, [r3, #12] + 8001698: 69bb ldr r3, [r7, #24] + 800169a: 43db mvns r3, r3 + 800169c: 4909 ldr r1, [pc, #36] ; (80016c4 ) + 800169e: 4013 ands r3, r2 + 80016a0: 60cb str r3, [r1, #12] + } + } + } + + position++; + 80016a2: 6a7b ldr r3, [r7, #36] ; 0x24 + 80016a4: 3301 adds r3, #1 + 80016a6: 627b str r3, [r7, #36] ; 0x24 + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80016a8: 683b ldr r3, [r7, #0] + 80016aa: 681a ldr r2, [r3, #0] + 80016ac: 6a7b ldr r3, [r7, #36] ; 0x24 + 80016ae: fa22 f303 lsr.w r3, r2, r3 + 80016b2: 2b00 cmp r3, #0 + 80016b4: f47f ae7e bne.w 80013b4 + } +} + 80016b8: bf00 nop + 80016ba: bf00 nop + 80016bc: 372c adds r7, #44 ; 0x2c + 80016be: 46bd mov sp, r7 + 80016c0: bc80 pop {r7} + 80016c2: 4770 bx lr + 80016c4: 40010400 .word 0x40010400 + +080016c8 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80016c8: b480 push {r7} + 80016ca: b083 sub sp, #12 + 80016cc: af00 add r7, sp, #0 + 80016ce: 6078 str r0, [r7, #4] + 80016d0: 460b mov r3, r1 + 80016d2: 807b strh r3, [r7, #2] + 80016d4: 4613 mov r3, r2 + 80016d6: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 80016d8: 787b ldrb r3, [r7, #1] + 80016da: 2b00 cmp r3, #0 + 80016dc: d003 beq.n 80016e6 + { + GPIOx->BSRR = GPIO_Pin; + 80016de: 887a ldrh r2, [r7, #2] + 80016e0: 687b ldr r3, [r7, #4] + 80016e2: 611a str r2, [r3, #16] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + } +} + 80016e4: e003 b.n 80016ee + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + 80016e6: 887b ldrh r3, [r7, #2] + 80016e8: 041a lsls r2, r3, #16 + 80016ea: 687b ldr r3, [r7, #4] + 80016ec: 611a str r2, [r3, #16] +} + 80016ee: bf00 nop + 80016f0: 370c adds r7, #12 + 80016f2: 46bd mov sp, r7 + 80016f4: bc80 pop {r7} + 80016f6: 4770 bx lr + +080016f8 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80016f8: b580 push {r7, lr} + 80016fa: b086 sub sp, #24 + 80016fc: af00 add r7, sp, #0 + 80016fe: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8001700: 687b ldr r3, [r7, #4] + 8001702: 2b00 cmp r3, #0 + 8001704: d101 bne.n 800170a + { + return HAL_ERROR; + 8001706: 2301 movs r3, #1 + 8001708: e26c b.n 8001be4 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 800170a: 687b ldr r3, [r7, #4] + 800170c: 681b ldr r3, [r3, #0] + 800170e: f003 0301 and.w r3, r3, #1 + 8001712: 2b00 cmp r3, #0 + 8001714: f000 8087 beq.w 8001826 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 8001718: 4b92 ldr r3, [pc, #584] ; (8001964 ) + 800171a: 685b ldr r3, [r3, #4] + 800171c: f003 030c and.w r3, r3, #12 + 8001720: 2b04 cmp r3, #4 + 8001722: d00c beq.n 800173e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + 8001724: 4b8f ldr r3, [pc, #572] ; (8001964 ) + 8001726: 685b ldr r3, [r3, #4] + 8001728: f003 030c and.w r3, r3, #12 + 800172c: 2b08 cmp r3, #8 + 800172e: d112 bne.n 8001756 + 8001730: 4b8c ldr r3, [pc, #560] ; (8001964 ) + 8001732: 685b ldr r3, [r3, #4] + 8001734: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001738: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800173c: d10b bne.n 8001756 + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 800173e: 4b89 ldr r3, [pc, #548] ; (8001964 ) + 8001740: 681b ldr r3, [r3, #0] + 8001742: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001746: 2b00 cmp r3, #0 + 8001748: d06c beq.n 8001824 + 800174a: 687b ldr r3, [r7, #4] + 800174c: 685b ldr r3, [r3, #4] + 800174e: 2b00 cmp r3, #0 + 8001750: d168 bne.n 8001824 + { + return HAL_ERROR; + 8001752: 2301 movs r3, #1 + 8001754: e246 b.n 8001be4 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8001756: 687b ldr r3, [r7, #4] + 8001758: 685b ldr r3, [r3, #4] + 800175a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800175e: d106 bne.n 800176e + 8001760: 4b80 ldr r3, [pc, #512] ; (8001964 ) + 8001762: 681b ldr r3, [r3, #0] + 8001764: 4a7f ldr r2, [pc, #508] ; (8001964 ) + 8001766: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 800176a: 6013 str r3, [r2, #0] + 800176c: e02e b.n 80017cc + 800176e: 687b ldr r3, [r7, #4] + 8001770: 685b ldr r3, [r3, #4] + 8001772: 2b00 cmp r3, #0 + 8001774: d10c bne.n 8001790 + 8001776: 4b7b ldr r3, [pc, #492] ; (8001964 ) + 8001778: 681b ldr r3, [r3, #0] + 800177a: 4a7a ldr r2, [pc, #488] ; (8001964 ) + 800177c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8001780: 6013 str r3, [r2, #0] + 8001782: 4b78 ldr r3, [pc, #480] ; (8001964 ) + 8001784: 681b ldr r3, [r3, #0] + 8001786: 4a77 ldr r2, [pc, #476] ; (8001964 ) + 8001788: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 800178c: 6013 str r3, [r2, #0] + 800178e: e01d b.n 80017cc + 8001790: 687b ldr r3, [r7, #4] + 8001792: 685b ldr r3, [r3, #4] + 8001794: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8001798: d10c bne.n 80017b4 + 800179a: 4b72 ldr r3, [pc, #456] ; (8001964 ) + 800179c: 681b ldr r3, [r3, #0] + 800179e: 4a71 ldr r2, [pc, #452] ; (8001964 ) + 80017a0: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 80017a4: 6013 str r3, [r2, #0] + 80017a6: 4b6f ldr r3, [pc, #444] ; (8001964 ) + 80017a8: 681b ldr r3, [r3, #0] + 80017aa: 4a6e ldr r2, [pc, #440] ; (8001964 ) + 80017ac: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80017b0: 6013 str r3, [r2, #0] + 80017b2: e00b b.n 80017cc + 80017b4: 4b6b ldr r3, [pc, #428] ; (8001964 ) + 80017b6: 681b ldr r3, [r3, #0] + 80017b8: 4a6a ldr r2, [pc, #424] ; (8001964 ) + 80017ba: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80017be: 6013 str r3, [r2, #0] + 80017c0: 4b68 ldr r3, [pc, #416] ; (8001964 ) + 80017c2: 681b ldr r3, [r3, #0] + 80017c4: 4a67 ldr r2, [pc, #412] ; (8001964 ) + 80017c6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80017ca: 6013 str r3, [r2, #0] + + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80017cc: 687b ldr r3, [r7, #4] + 80017ce: 685b ldr r3, [r3, #4] + 80017d0: 2b00 cmp r3, #0 + 80017d2: d013 beq.n 80017fc + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80017d4: f7ff fcd2 bl 800117c + 80017d8: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80017da: e008 b.n 80017ee + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80017dc: f7ff fcce bl 800117c + 80017e0: 4602 mov r2, r0 + 80017e2: 693b ldr r3, [r7, #16] + 80017e4: 1ad3 subs r3, r2, r3 + 80017e6: 2b64 cmp r3, #100 ; 0x64 + 80017e8: d901 bls.n 80017ee + { + return HAL_TIMEOUT; + 80017ea: 2303 movs r3, #3 + 80017ec: e1fa b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80017ee: 4b5d ldr r3, [pc, #372] ; (8001964 ) + 80017f0: 681b ldr r3, [r3, #0] + 80017f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80017f6: 2b00 cmp r3, #0 + 80017f8: d0f0 beq.n 80017dc + 80017fa: e014 b.n 8001826 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80017fc: f7ff fcbe bl 800117c + 8001800: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8001802: e008 b.n 8001816 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8001804: f7ff fcba bl 800117c + 8001808: 4602 mov r2, r0 + 800180a: 693b ldr r3, [r7, #16] + 800180c: 1ad3 subs r3, r2, r3 + 800180e: 2b64 cmp r3, #100 ; 0x64 + 8001810: d901 bls.n 8001816 + { + return HAL_TIMEOUT; + 8001812: 2303 movs r3, #3 + 8001814: e1e6 b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8001816: 4b53 ldr r3, [pc, #332] ; (8001964 ) + 8001818: 681b ldr r3, [r3, #0] + 800181a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800181e: 2b00 cmp r3, #0 + 8001820: d1f0 bne.n 8001804 + 8001822: e000 b.n 8001826 + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001824: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8001826: 687b ldr r3, [r7, #4] + 8001828: 681b ldr r3, [r3, #0] + 800182a: f003 0302 and.w r3, r3, #2 + 800182e: 2b00 cmp r3, #0 + 8001830: d063 beq.n 80018fa + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 8001832: 4b4c ldr r3, [pc, #304] ; (8001964 ) + 8001834: 685b ldr r3, [r3, #4] + 8001836: f003 030c and.w r3, r3, #12 + 800183a: 2b00 cmp r3, #0 + 800183c: d00b beq.n 8001856 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) + 800183e: 4b49 ldr r3, [pc, #292] ; (8001964 ) + 8001840: 685b ldr r3, [r3, #4] + 8001842: f003 030c and.w r3, r3, #12 + 8001846: 2b08 cmp r3, #8 + 8001848: d11c bne.n 8001884 + 800184a: 4b46 ldr r3, [pc, #280] ; (8001964 ) + 800184c: 685b ldr r3, [r3, #4] + 800184e: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001852: 2b00 cmp r3, #0 + 8001854: d116 bne.n 8001884 + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001856: 4b43 ldr r3, [pc, #268] ; (8001964 ) + 8001858: 681b ldr r3, [r3, #0] + 800185a: f003 0302 and.w r3, r3, #2 + 800185e: 2b00 cmp r3, #0 + 8001860: d005 beq.n 800186e + 8001862: 687b ldr r3, [r7, #4] + 8001864: 691b ldr r3, [r3, #16] + 8001866: 2b01 cmp r3, #1 + 8001868: d001 beq.n 800186e + { + return HAL_ERROR; + 800186a: 2301 movs r3, #1 + 800186c: e1ba b.n 8001be4 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800186e: 4b3d ldr r3, [pc, #244] ; (8001964 ) + 8001870: 681b ldr r3, [r3, #0] + 8001872: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8001876: 687b ldr r3, [r7, #4] + 8001878: 695b ldr r3, [r3, #20] + 800187a: 00db lsls r3, r3, #3 + 800187c: 4939 ldr r1, [pc, #228] ; (8001964 ) + 800187e: 4313 orrs r3, r2 + 8001880: 600b str r3, [r1, #0] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001882: e03a b.n 80018fa + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8001884: 687b ldr r3, [r7, #4] + 8001886: 691b ldr r3, [r3, #16] + 8001888: 2b00 cmp r3, #0 + 800188a: d020 beq.n 80018ce + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800188c: 4b36 ldr r3, [pc, #216] ; (8001968 ) + 800188e: 2201 movs r2, #1 + 8001890: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001892: f7ff fc73 bl 800117c + 8001896: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8001898: e008 b.n 80018ac + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 800189a: f7ff fc6f bl 800117c + 800189e: 4602 mov r2, r0 + 80018a0: 693b ldr r3, [r7, #16] + 80018a2: 1ad3 subs r3, r2, r3 + 80018a4: 2b02 cmp r3, #2 + 80018a6: d901 bls.n 80018ac + { + return HAL_TIMEOUT; + 80018a8: 2303 movs r3, #3 + 80018aa: e19b b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80018ac: 4b2d ldr r3, [pc, #180] ; (8001964 ) + 80018ae: 681b ldr r3, [r3, #0] + 80018b0: f003 0302 and.w r3, r3, #2 + 80018b4: 2b00 cmp r3, #0 + 80018b6: d0f0 beq.n 800189a + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80018b8: 4b2a ldr r3, [pc, #168] ; (8001964 ) + 80018ba: 681b ldr r3, [r3, #0] + 80018bc: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80018c0: 687b ldr r3, [r7, #4] + 80018c2: 695b ldr r3, [r3, #20] + 80018c4: 00db lsls r3, r3, #3 + 80018c6: 4927 ldr r1, [pc, #156] ; (8001964 ) + 80018c8: 4313 orrs r3, r2 + 80018ca: 600b str r3, [r1, #0] + 80018cc: e015 b.n 80018fa + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80018ce: 4b26 ldr r3, [pc, #152] ; (8001968 ) + 80018d0: 2200 movs r2, #0 + 80018d2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80018d4: f7ff fc52 bl 800117c + 80018d8: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80018da: e008 b.n 80018ee + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80018dc: f7ff fc4e bl 800117c + 80018e0: 4602 mov r2, r0 + 80018e2: 693b ldr r3, [r7, #16] + 80018e4: 1ad3 subs r3, r2, r3 + 80018e6: 2b02 cmp r3, #2 + 80018e8: d901 bls.n 80018ee + { + return HAL_TIMEOUT; + 80018ea: 2303 movs r3, #3 + 80018ec: e17a b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80018ee: 4b1d ldr r3, [pc, #116] ; (8001964 ) + 80018f0: 681b ldr r3, [r3, #0] + 80018f2: f003 0302 and.w r3, r3, #2 + 80018f6: 2b00 cmp r3, #0 + 80018f8: d1f0 bne.n 80018dc + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80018fa: 687b ldr r3, [r7, #4] + 80018fc: 681b ldr r3, [r3, #0] + 80018fe: f003 0308 and.w r3, r3, #8 + 8001902: 2b00 cmp r3, #0 + 8001904: d03a beq.n 800197c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8001906: 687b ldr r3, [r7, #4] + 8001908: 699b ldr r3, [r3, #24] + 800190a: 2b00 cmp r3, #0 + 800190c: d019 beq.n 8001942 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800190e: 4b17 ldr r3, [pc, #92] ; (800196c ) + 8001910: 2201 movs r2, #1 + 8001912: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001914: f7ff fc32 bl 800117c + 8001918: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800191a: e008 b.n 800192e + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 800191c: f7ff fc2e bl 800117c + 8001920: 4602 mov r2, r0 + 8001922: 693b ldr r3, [r7, #16] + 8001924: 1ad3 subs r3, r2, r3 + 8001926: 2b02 cmp r3, #2 + 8001928: d901 bls.n 800192e + { + return HAL_TIMEOUT; + 800192a: 2303 movs r3, #3 + 800192c: e15a b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800192e: 4b0d ldr r3, [pc, #52] ; (8001964 ) + 8001930: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001932: f003 0302 and.w r3, r3, #2 + 8001936: 2b00 cmp r3, #0 + 8001938: d0f0 beq.n 800191c + } + } + /* To have a fully stabilized clock in the specified range, a software delay of 1ms + should be added.*/ + RCC_Delay(1); + 800193a: 2001 movs r0, #1 + 800193c: f000 faa6 bl 8001e8c + 8001940: e01c b.n 800197c + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001942: 4b0a ldr r3, [pc, #40] ; (800196c ) + 8001944: 2200 movs r2, #0 + 8001946: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001948: f7ff fc18 bl 800117c + 800194c: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 800194e: e00f b.n 8001970 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8001950: f7ff fc14 bl 800117c + 8001954: 4602 mov r2, r0 + 8001956: 693b ldr r3, [r7, #16] + 8001958: 1ad3 subs r3, r2, r3 + 800195a: 2b02 cmp r3, #2 + 800195c: d908 bls.n 8001970 + { + return HAL_TIMEOUT; + 800195e: 2303 movs r3, #3 + 8001960: e140 b.n 8001be4 + 8001962: bf00 nop + 8001964: 40021000 .word 0x40021000 + 8001968: 42420000 .word 0x42420000 + 800196c: 42420480 .word 0x42420480 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8001970: 4b9e ldr r3, [pc, #632] ; (8001bec ) + 8001972: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001974: f003 0302 and.w r3, r3, #2 + 8001978: 2b00 cmp r3, #0 + 800197a: d1e9 bne.n 8001950 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800197c: 687b ldr r3, [r7, #4] + 800197e: 681b ldr r3, [r3, #0] + 8001980: f003 0304 and.w r3, r3, #4 + 8001984: 2b00 cmp r3, #0 + 8001986: f000 80a6 beq.w 8001ad6 + { + FlagStatus pwrclkchanged = RESET; + 800198a: 2300 movs r3, #0 + 800198c: 75fb strb r3, [r7, #23] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800198e: 4b97 ldr r3, [pc, #604] ; (8001bec ) + 8001990: 69db ldr r3, [r3, #28] + 8001992: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001996: 2b00 cmp r3, #0 + 8001998: d10d bne.n 80019b6 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 800199a: 4b94 ldr r3, [pc, #592] ; (8001bec ) + 800199c: 69db ldr r3, [r3, #28] + 800199e: 4a93 ldr r2, [pc, #588] ; (8001bec ) + 80019a0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80019a4: 61d3 str r3, [r2, #28] + 80019a6: 4b91 ldr r3, [pc, #580] ; (8001bec ) + 80019a8: 69db ldr r3, [r3, #28] + 80019aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80019ae: 60bb str r3, [r7, #8] + 80019b0: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 80019b2: 2301 movs r3, #1 + 80019b4: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80019b6: 4b8e ldr r3, [pc, #568] ; (8001bf0 ) + 80019b8: 681b ldr r3, [r3, #0] + 80019ba: f403 7380 and.w r3, r3, #256 ; 0x100 + 80019be: 2b00 cmp r3, #0 + 80019c0: d118 bne.n 80019f4 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80019c2: 4b8b ldr r3, [pc, #556] ; (8001bf0 ) + 80019c4: 681b ldr r3, [r3, #0] + 80019c6: 4a8a ldr r2, [pc, #552] ; (8001bf0 ) + 80019c8: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80019cc: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80019ce: f7ff fbd5 bl 800117c + 80019d2: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80019d4: e008 b.n 80019e8 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80019d6: f7ff fbd1 bl 800117c + 80019da: 4602 mov r2, r0 + 80019dc: 693b ldr r3, [r7, #16] + 80019de: 1ad3 subs r3, r2, r3 + 80019e0: 2b64 cmp r3, #100 ; 0x64 + 80019e2: d901 bls.n 80019e8 + { + return HAL_TIMEOUT; + 80019e4: 2303 movs r3, #3 + 80019e6: e0fd b.n 8001be4 + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80019e8: 4b81 ldr r3, [pc, #516] ; (8001bf0 ) + 80019ea: 681b ldr r3, [r3, #0] + 80019ec: f403 7380 and.w r3, r3, #256 ; 0x100 + 80019f0: 2b00 cmp r3, #0 + 80019f2: d0f0 beq.n 80019d6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80019f4: 687b ldr r3, [r7, #4] + 80019f6: 68db ldr r3, [r3, #12] + 80019f8: 2b01 cmp r3, #1 + 80019fa: d106 bne.n 8001a0a + 80019fc: 4b7b ldr r3, [pc, #492] ; (8001bec ) + 80019fe: 6a1b ldr r3, [r3, #32] + 8001a00: 4a7a ldr r2, [pc, #488] ; (8001bec ) + 8001a02: f043 0301 orr.w r3, r3, #1 + 8001a06: 6213 str r3, [r2, #32] + 8001a08: e02d b.n 8001a66 + 8001a0a: 687b ldr r3, [r7, #4] + 8001a0c: 68db ldr r3, [r3, #12] + 8001a0e: 2b00 cmp r3, #0 + 8001a10: d10c bne.n 8001a2c + 8001a12: 4b76 ldr r3, [pc, #472] ; (8001bec ) + 8001a14: 6a1b ldr r3, [r3, #32] + 8001a16: 4a75 ldr r2, [pc, #468] ; (8001bec ) + 8001a18: f023 0301 bic.w r3, r3, #1 + 8001a1c: 6213 str r3, [r2, #32] + 8001a1e: 4b73 ldr r3, [pc, #460] ; (8001bec ) + 8001a20: 6a1b ldr r3, [r3, #32] + 8001a22: 4a72 ldr r2, [pc, #456] ; (8001bec ) + 8001a24: f023 0304 bic.w r3, r3, #4 + 8001a28: 6213 str r3, [r2, #32] + 8001a2a: e01c b.n 8001a66 + 8001a2c: 687b ldr r3, [r7, #4] + 8001a2e: 68db ldr r3, [r3, #12] + 8001a30: 2b05 cmp r3, #5 + 8001a32: d10c bne.n 8001a4e + 8001a34: 4b6d ldr r3, [pc, #436] ; (8001bec ) + 8001a36: 6a1b ldr r3, [r3, #32] + 8001a38: 4a6c ldr r2, [pc, #432] ; (8001bec ) + 8001a3a: f043 0304 orr.w r3, r3, #4 + 8001a3e: 6213 str r3, [r2, #32] + 8001a40: 4b6a ldr r3, [pc, #424] ; (8001bec ) + 8001a42: 6a1b ldr r3, [r3, #32] + 8001a44: 4a69 ldr r2, [pc, #420] ; (8001bec ) + 8001a46: f043 0301 orr.w r3, r3, #1 + 8001a4a: 6213 str r3, [r2, #32] + 8001a4c: e00b b.n 8001a66 + 8001a4e: 4b67 ldr r3, [pc, #412] ; (8001bec ) + 8001a50: 6a1b ldr r3, [r3, #32] + 8001a52: 4a66 ldr r2, [pc, #408] ; (8001bec ) + 8001a54: f023 0301 bic.w r3, r3, #1 + 8001a58: 6213 str r3, [r2, #32] + 8001a5a: 4b64 ldr r3, [pc, #400] ; (8001bec ) + 8001a5c: 6a1b ldr r3, [r3, #32] + 8001a5e: 4a63 ldr r2, [pc, #396] ; (8001bec ) + 8001a60: f023 0304 bic.w r3, r3, #4 + 8001a64: 6213 str r3, [r2, #32] + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8001a66: 687b ldr r3, [r7, #4] + 8001a68: 68db ldr r3, [r3, #12] + 8001a6a: 2b00 cmp r3, #0 + 8001a6c: d015 beq.n 8001a9a + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001a6e: f7ff fb85 bl 800117c + 8001a72: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8001a74: e00a b.n 8001a8c + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8001a76: f7ff fb81 bl 800117c + 8001a7a: 4602 mov r2, r0 + 8001a7c: 693b ldr r3, [r7, #16] + 8001a7e: 1ad3 subs r3, r2, r3 + 8001a80: f241 3288 movw r2, #5000 ; 0x1388 + 8001a84: 4293 cmp r3, r2 + 8001a86: d901 bls.n 8001a8c + { + return HAL_TIMEOUT; + 8001a88: 2303 movs r3, #3 + 8001a8a: e0ab b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8001a8c: 4b57 ldr r3, [pc, #348] ; (8001bec ) + 8001a8e: 6a1b ldr r3, [r3, #32] + 8001a90: f003 0302 and.w r3, r3, #2 + 8001a94: 2b00 cmp r3, #0 + 8001a96: d0ee beq.n 8001a76 + 8001a98: e014 b.n 8001ac4 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001a9a: f7ff fb6f bl 800117c + 8001a9e: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8001aa0: e00a b.n 8001ab8 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8001aa2: f7ff fb6b bl 800117c + 8001aa6: 4602 mov r2, r0 + 8001aa8: 693b ldr r3, [r7, #16] + 8001aaa: 1ad3 subs r3, r2, r3 + 8001aac: f241 3288 movw r2, #5000 ; 0x1388 + 8001ab0: 4293 cmp r3, r2 + 8001ab2: d901 bls.n 8001ab8 + { + return HAL_TIMEOUT; + 8001ab4: 2303 movs r3, #3 + 8001ab6: e095 b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8001ab8: 4b4c ldr r3, [pc, #304] ; (8001bec ) + 8001aba: 6a1b ldr r3, [r3, #32] + 8001abc: f003 0302 and.w r3, r3, #2 + 8001ac0: 2b00 cmp r3, #0 + 8001ac2: d1ee bne.n 8001aa2 + } + } + } + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + 8001ac4: 7dfb ldrb r3, [r7, #23] + 8001ac6: 2b01 cmp r3, #1 + 8001ac8: d105 bne.n 8001ad6 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001aca: 4b48 ldr r3, [pc, #288] ; (8001bec ) + 8001acc: 69db ldr r3, [r3, #28] + 8001ace: 4a47 ldr r2, [pc, #284] ; (8001bec ) + 8001ad0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8001ad4: 61d3 str r3, [r2, #28] + +#endif /* RCC_CR_PLL2ON */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8001ad6: 687b ldr r3, [r7, #4] + 8001ad8: 69db ldr r3, [r3, #28] + 8001ada: 2b00 cmp r3, #0 + 8001adc: f000 8081 beq.w 8001be2 + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001ae0: 4b42 ldr r3, [pc, #264] ; (8001bec ) + 8001ae2: 685b ldr r3, [r3, #4] + 8001ae4: f003 030c and.w r3, r3, #12 + 8001ae8: 2b08 cmp r3, #8 + 8001aea: d061 beq.n 8001bb0 + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8001aec: 687b ldr r3, [r7, #4] + 8001aee: 69db ldr r3, [r3, #28] + 8001af0: 2b02 cmp r3, #2 + 8001af2: d146 bne.n 8001b82 + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001af4: 4b3f ldr r3, [pc, #252] ; (8001bf4 ) + 8001af6: 2200 movs r2, #0 + 8001af8: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001afa: f7ff fb3f bl 800117c + 8001afe: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8001b00: e008 b.n 8001b14 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8001b02: f7ff fb3b bl 800117c + 8001b06: 4602 mov r2, r0 + 8001b08: 693b ldr r3, [r7, #16] + 8001b0a: 1ad3 subs r3, r2, r3 + 8001b0c: 2b02 cmp r3, #2 + 8001b0e: d901 bls.n 8001b14 + { + return HAL_TIMEOUT; + 8001b10: 2303 movs r3, #3 + 8001b12: e067 b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8001b14: 4b35 ldr r3, [pc, #212] ; (8001bec ) + 8001b16: 681b ldr r3, [r3, #0] + 8001b18: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8001b1c: 2b00 cmp r3, #0 + 8001b1e: d1f0 bne.n 8001b02 + } + } + + /* Configure the HSE prediv factor --------------------------------*/ + /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ + if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) + 8001b20: 687b ldr r3, [r7, #4] + 8001b22: 6a1b ldr r3, [r3, #32] + 8001b24: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8001b28: d108 bne.n 8001b3c + /* Set PREDIV1 source */ + SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Set PREDIV1 Value */ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + 8001b2a: 4b30 ldr r3, [pc, #192] ; (8001bec ) + 8001b2c: 685b ldr r3, [r3, #4] + 8001b2e: f423 3200 bic.w r2, r3, #131072 ; 0x20000 + 8001b32: 687b ldr r3, [r7, #4] + 8001b34: 689b ldr r3, [r3, #8] + 8001b36: 492d ldr r1, [pc, #180] ; (8001bec ) + 8001b38: 4313 orrs r3, r2 + 8001b3a: 604b str r3, [r1, #4] + } + + /* Configure the main PLL clock source and multiplication factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8001b3c: 4b2b ldr r3, [pc, #172] ; (8001bec ) + 8001b3e: 685b ldr r3, [r3, #4] + 8001b40: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 + 8001b44: 687b ldr r3, [r7, #4] + 8001b46: 6a19 ldr r1, [r3, #32] + 8001b48: 687b ldr r3, [r7, #4] + 8001b4a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001b4c: 430b orrs r3, r1 + 8001b4e: 4927 ldr r1, [pc, #156] ; (8001bec ) + 8001b50: 4313 orrs r3, r2 + 8001b52: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8001b54: 4b27 ldr r3, [pc, #156] ; (8001bf4 ) + 8001b56: 2201 movs r2, #1 + 8001b58: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001b5a: f7ff fb0f bl 800117c + 8001b5e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8001b60: e008 b.n 8001b74 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8001b62: f7ff fb0b bl 800117c + 8001b66: 4602 mov r2, r0 + 8001b68: 693b ldr r3, [r7, #16] + 8001b6a: 1ad3 subs r3, r2, r3 + 8001b6c: 2b02 cmp r3, #2 + 8001b6e: d901 bls.n 8001b74 + { + return HAL_TIMEOUT; + 8001b70: 2303 movs r3, #3 + 8001b72: e037 b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8001b74: 4b1d ldr r3, [pc, #116] ; (8001bec ) + 8001b76: 681b ldr r3, [r3, #0] + 8001b78: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8001b7c: 2b00 cmp r3, #0 + 8001b7e: d0f0 beq.n 8001b62 + 8001b80: e02f b.n 8001be2 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001b82: 4b1c ldr r3, [pc, #112] ; (8001bf4 ) + 8001b84: 2200 movs r2, #0 + 8001b86: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001b88: f7ff faf8 bl 800117c + 8001b8c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8001b8e: e008 b.n 8001ba2 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8001b90: f7ff faf4 bl 800117c + 8001b94: 4602 mov r2, r0 + 8001b96: 693b ldr r3, [r7, #16] + 8001b98: 1ad3 subs r3, r2, r3 + 8001b9a: 2b02 cmp r3, #2 + 8001b9c: d901 bls.n 8001ba2 + { + return HAL_TIMEOUT; + 8001b9e: 2303 movs r3, #3 + 8001ba0: e020 b.n 8001be4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8001ba2: 4b12 ldr r3, [pc, #72] ; (8001bec ) + 8001ba4: 681b ldr r3, [r3, #0] + 8001ba6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8001baa: 2b00 cmp r3, #0 + 8001bac: d1f0 bne.n 8001b90 + 8001bae: e018 b.n 8001be2 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8001bb0: 687b ldr r3, [r7, #4] + 8001bb2: 69db ldr r3, [r3, #28] + 8001bb4: 2b01 cmp r3, #1 + 8001bb6: d101 bne.n 8001bbc + { + return HAL_ERROR; + 8001bb8: 2301 movs r3, #1 + 8001bba: e013 b.n 8001be4 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8001bbc: 4b0b ldr r3, [pc, #44] ; (8001bec ) + 8001bbe: 685b ldr r3, [r3, #4] + 8001bc0: 60fb str r3, [r7, #12] + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001bc2: 68fb ldr r3, [r7, #12] + 8001bc4: f403 3280 and.w r2, r3, #65536 ; 0x10000 + 8001bc8: 687b ldr r3, [r7, #4] + 8001bca: 6a1b ldr r3, [r3, #32] + 8001bcc: 429a cmp r2, r3 + 8001bce: d106 bne.n 8001bde + (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) + 8001bd0: 68fb ldr r3, [r7, #12] + 8001bd2: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 + 8001bd6: 687b ldr r3, [r7, #4] + 8001bd8: 6a5b ldr r3, [r3, #36] ; 0x24 + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001bda: 429a cmp r2, r3 + 8001bdc: d001 beq.n 8001be2 + { + return HAL_ERROR; + 8001bde: 2301 movs r3, #1 + 8001be0: e000 b.n 8001be4 + } + } + } + } + + return HAL_OK; + 8001be2: 2300 movs r3, #0 +} + 8001be4: 4618 mov r0, r3 + 8001be6: 3718 adds r7, #24 + 8001be8: 46bd mov sp, r7 + 8001bea: bd80 pop {r7, pc} + 8001bec: 40021000 .word 0x40021000 + 8001bf0: 40007000 .word 0x40007000 + 8001bf4: 42420060 .word 0x42420060 + +08001bf8 : + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8001bf8: b580 push {r7, lr} + 8001bfa: b084 sub sp, #16 + 8001bfc: af00 add r7, sp, #0 + 8001bfe: 6078 str r0, [r7, #4] + 8001c00: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8001c02: 687b ldr r3, [r7, #4] + 8001c04: 2b00 cmp r3, #0 + 8001c06: d101 bne.n 8001c0c + { + return HAL_ERROR; + 8001c08: 2301 movs r3, #1 + 8001c0a: e0d0 b.n 8001dae + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + +#if defined(FLASH_ACR_LATENCY) + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8001c0c: 4b6a ldr r3, [pc, #424] ; (8001db8 ) + 8001c0e: 681b ldr r3, [r3, #0] + 8001c10: f003 0307 and.w r3, r3, #7 + 8001c14: 683a ldr r2, [r7, #0] + 8001c16: 429a cmp r2, r3 + 8001c18: d910 bls.n 8001c3c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001c1a: 4b67 ldr r3, [pc, #412] ; (8001db8 ) + 8001c1c: 681b ldr r3, [r3, #0] + 8001c1e: f023 0207 bic.w r2, r3, #7 + 8001c22: 4965 ldr r1, [pc, #404] ; (8001db8 ) + 8001c24: 683b ldr r3, [r7, #0] + 8001c26: 4313 orrs r3, r2 + 8001c28: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8001c2a: 4b63 ldr r3, [pc, #396] ; (8001db8 ) + 8001c2c: 681b ldr r3, [r3, #0] + 8001c2e: f003 0307 and.w r3, r3, #7 + 8001c32: 683a ldr r2, [r7, #0] + 8001c34: 429a cmp r2, r3 + 8001c36: d001 beq.n 8001c3c + { + return HAL_ERROR; + 8001c38: 2301 movs r3, #1 + 8001c3a: e0b8 b.n 8001dae + } +} + +#endif /* FLASH_ACR_LATENCY */ +/*-------------------------- HCLK Configuration --------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001c3c: 687b ldr r3, [r7, #4] + 8001c3e: 681b ldr r3, [r3, #0] + 8001c40: f003 0302 and.w r3, r3, #2 + 8001c44: 2b00 cmp r3, #0 + 8001c46: d020 beq.n 8001c8a + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001c48: 687b ldr r3, [r7, #4] + 8001c4a: 681b ldr r3, [r3, #0] + 8001c4c: f003 0304 and.w r3, r3, #4 + 8001c50: 2b00 cmp r3, #0 + 8001c52: d005 beq.n 8001c60 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8001c54: 4b59 ldr r3, [pc, #356] ; (8001dbc ) + 8001c56: 685b ldr r3, [r3, #4] + 8001c58: 4a58 ldr r2, [pc, #352] ; (8001dbc ) + 8001c5a: f443 63e0 orr.w r3, r3, #1792 ; 0x700 + 8001c5e: 6053 str r3, [r2, #4] + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001c60: 687b ldr r3, [r7, #4] + 8001c62: 681b ldr r3, [r3, #0] + 8001c64: f003 0308 and.w r3, r3, #8 + 8001c68: 2b00 cmp r3, #0 + 8001c6a: d005 beq.n 8001c78 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8001c6c: 4b53 ldr r3, [pc, #332] ; (8001dbc ) + 8001c6e: 685b ldr r3, [r3, #4] + 8001c70: 4a52 ldr r2, [pc, #328] ; (8001dbc ) + 8001c72: f443 5360 orr.w r3, r3, #14336 ; 0x3800 + 8001c76: 6053 str r3, [r2, #4] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8001c78: 4b50 ldr r3, [pc, #320] ; (8001dbc ) + 8001c7a: 685b ldr r3, [r3, #4] + 8001c7c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8001c80: 687b ldr r3, [r7, #4] + 8001c82: 689b ldr r3, [r3, #8] + 8001c84: 494d ldr r1, [pc, #308] ; (8001dbc ) + 8001c86: 4313 orrs r3, r2 + 8001c88: 604b str r3, [r1, #4] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001c8a: 687b ldr r3, [r7, #4] + 8001c8c: 681b ldr r3, [r3, #0] + 8001c8e: f003 0301 and.w r3, r3, #1 + 8001c92: 2b00 cmp r3, #0 + 8001c94: d040 beq.n 8001d18 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001c96: 687b ldr r3, [r7, #4] + 8001c98: 685b ldr r3, [r3, #4] + 8001c9a: 2b01 cmp r3, #1 + 8001c9c: d107 bne.n 8001cae + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8001c9e: 4b47 ldr r3, [pc, #284] ; (8001dbc ) + 8001ca0: 681b ldr r3, [r3, #0] + 8001ca2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001ca6: 2b00 cmp r3, #0 + 8001ca8: d115 bne.n 8001cd6 + { + return HAL_ERROR; + 8001caa: 2301 movs r3, #1 + 8001cac: e07f b.n 8001dae + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001cae: 687b ldr r3, [r7, #4] + 8001cb0: 685b ldr r3, [r3, #4] + 8001cb2: 2b02 cmp r3, #2 + 8001cb4: d107 bne.n 8001cc6 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8001cb6: 4b41 ldr r3, [pc, #260] ; (8001dbc ) + 8001cb8: 681b ldr r3, [r3, #0] + 8001cba: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8001cbe: 2b00 cmp r3, #0 + 8001cc0: d109 bne.n 8001cd6 + { + return HAL_ERROR; + 8001cc2: 2301 movs r3, #1 + 8001cc4: e073 b.n 8001dae + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8001cc6: 4b3d ldr r3, [pc, #244] ; (8001dbc ) + 8001cc8: 681b ldr r3, [r3, #0] + 8001cca: f003 0302 and.w r3, r3, #2 + 8001cce: 2b00 cmp r3, #0 + 8001cd0: d101 bne.n 8001cd6 + { + return HAL_ERROR; + 8001cd2: 2301 movs r3, #1 + 8001cd4: e06b b.n 8001dae + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001cd6: 4b39 ldr r3, [pc, #228] ; (8001dbc ) + 8001cd8: 685b ldr r3, [r3, #4] + 8001cda: f023 0203 bic.w r2, r3, #3 + 8001cde: 687b ldr r3, [r7, #4] + 8001ce0: 685b ldr r3, [r3, #4] + 8001ce2: 4936 ldr r1, [pc, #216] ; (8001dbc ) + 8001ce4: 4313 orrs r3, r2 + 8001ce6: 604b str r3, [r1, #4] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001ce8: f7ff fa48 bl 800117c + 8001cec: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8001cee: e00a b.n 8001d06 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001cf0: f7ff fa44 bl 800117c + 8001cf4: 4602 mov r2, r0 + 8001cf6: 68fb ldr r3, [r7, #12] + 8001cf8: 1ad3 subs r3, r2, r3 + 8001cfa: f241 3288 movw r2, #5000 ; 0x1388 + 8001cfe: 4293 cmp r3, r2 + 8001d00: d901 bls.n 8001d06 + { + return HAL_TIMEOUT; + 8001d02: 2303 movs r3, #3 + 8001d04: e053 b.n 8001dae + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8001d06: 4b2d ldr r3, [pc, #180] ; (8001dbc ) + 8001d08: 685b ldr r3, [r3, #4] + 8001d0a: f003 020c and.w r2, r3, #12 + 8001d0e: 687b ldr r3, [r7, #4] + 8001d10: 685b ldr r3, [r3, #4] + 8001d12: 009b lsls r3, r3, #2 + 8001d14: 429a cmp r2, r3 + 8001d16: d1eb bne.n 8001cf0 + } + } + +#if defined(FLASH_ACR_LATENCY) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8001d18: 4b27 ldr r3, [pc, #156] ; (8001db8 ) + 8001d1a: 681b ldr r3, [r3, #0] + 8001d1c: f003 0307 and.w r3, r3, #7 + 8001d20: 683a ldr r2, [r7, #0] + 8001d22: 429a cmp r2, r3 + 8001d24: d210 bcs.n 8001d48 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001d26: 4b24 ldr r3, [pc, #144] ; (8001db8 ) + 8001d28: 681b ldr r3, [r3, #0] + 8001d2a: f023 0207 bic.w r2, r3, #7 + 8001d2e: 4922 ldr r1, [pc, #136] ; (8001db8 ) + 8001d30: 683b ldr r3, [r7, #0] + 8001d32: 4313 orrs r3, r2 + 8001d34: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8001d36: 4b20 ldr r3, [pc, #128] ; (8001db8 ) + 8001d38: 681b ldr r3, [r3, #0] + 8001d3a: f003 0307 and.w r3, r3, #7 + 8001d3e: 683a ldr r2, [r7, #0] + 8001d40: 429a cmp r2, r3 + 8001d42: d001 beq.n 8001d48 + { + return HAL_ERROR; + 8001d44: 2301 movs r3, #1 + 8001d46: e032 b.n 8001dae + } +} +#endif /* FLASH_ACR_LATENCY */ + +/*-------------------------- PCLK1 Configuration ---------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001d48: 687b ldr r3, [r7, #4] + 8001d4a: 681b ldr r3, [r3, #0] + 8001d4c: f003 0304 and.w r3, r3, #4 + 8001d50: 2b00 cmp r3, #0 + 8001d52: d008 beq.n 8001d66 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001d54: 4b19 ldr r3, [pc, #100] ; (8001dbc ) + 8001d56: 685b ldr r3, [r3, #4] + 8001d58: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 8001d5c: 687b ldr r3, [r7, #4] + 8001d5e: 68db ldr r3, [r3, #12] + 8001d60: 4916 ldr r1, [pc, #88] ; (8001dbc ) + 8001d62: 4313 orrs r3, r2 + 8001d64: 604b str r3, [r1, #4] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001d66: 687b ldr r3, [r7, #4] + 8001d68: 681b ldr r3, [r3, #0] + 8001d6a: f003 0308 and.w r3, r3, #8 + 8001d6e: 2b00 cmp r3, #0 + 8001d70: d009 beq.n 8001d86 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8001d72: 4b12 ldr r3, [pc, #72] ; (8001dbc ) + 8001d74: 685b ldr r3, [r3, #4] + 8001d76: f423 5260 bic.w r2, r3, #14336 ; 0x3800 + 8001d7a: 687b ldr r3, [r7, #4] + 8001d7c: 691b ldr r3, [r3, #16] + 8001d7e: 00db lsls r3, r3, #3 + 8001d80: 490e ldr r1, [pc, #56] ; (8001dbc ) + 8001d82: 4313 orrs r3, r2 + 8001d84: 604b str r3, [r1, #4] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + 8001d86: f000 f821 bl 8001dcc + 8001d8a: 4602 mov r2, r0 + 8001d8c: 4b0b ldr r3, [pc, #44] ; (8001dbc ) + 8001d8e: 685b ldr r3, [r3, #4] + 8001d90: 091b lsrs r3, r3, #4 + 8001d92: f003 030f and.w r3, r3, #15 + 8001d96: 490a ldr r1, [pc, #40] ; (8001dc0 ) + 8001d98: 5ccb ldrb r3, [r1, r3] + 8001d9a: fa22 f303 lsr.w r3, r2, r3 + 8001d9e: 4a09 ldr r2, [pc, #36] ; (8001dc4 ) + 8001da0: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + 8001da2: 4b09 ldr r3, [pc, #36] ; (8001dc8 ) + 8001da4: 681b ldr r3, [r3, #0] + 8001da6: 4618 mov r0, r3 + 8001da8: f7ff f9a6 bl 80010f8 + + return HAL_OK; + 8001dac: 2300 movs r3, #0 +} + 8001dae: 4618 mov r0, r3 + 8001db0: 3710 adds r7, #16 + 8001db2: 46bd mov sp, r7 + 8001db4: bd80 pop {r7, pc} + 8001db6: bf00 nop + 8001db8: 40022000 .word 0x40022000 + 8001dbc: 40021000 .word 0x40021000 + 8001dc0: 08005238 .word 0x08005238 + 8001dc4: 20000000 .word 0x20000000 + 8001dc8: 20000004 .word 0x20000004 + +08001dcc : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001dcc: b490 push {r4, r7} + 8001dce: b08a sub sp, #40 ; 0x28 + 8001dd0: af00 add r7, sp, #0 +#if defined(RCC_CFGR2_PREDIV1SRC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + 8001dd2: 4b2a ldr r3, [pc, #168] ; (8001e7c ) + 8001dd4: 1d3c adds r4, r7, #4 + 8001dd6: cb0f ldmia r3, {r0, r1, r2, r3} + 8001dd8: e884 000f stmia.w r4, {r0, r1, r2, r3} +#if defined(RCC_CFGR2_PREDIV1) + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPredivFactorTable[2] = {1, 2}; + 8001ddc: f240 2301 movw r3, #513 ; 0x201 + 8001de0: 803b strh r3, [r7, #0] +#endif /*RCC_CFGR2_PREDIV1*/ + +#endif + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 8001de2: 2300 movs r3, #0 + 8001de4: 61fb str r3, [r7, #28] + 8001de6: 2300 movs r3, #0 + 8001de8: 61bb str r3, [r7, #24] + 8001dea: 2300 movs r3, #0 + 8001dec: 627b str r3, [r7, #36] ; 0x24 + 8001dee: 2300 movs r3, #0 + 8001df0: 617b str r3, [r7, #20] + uint32_t sysclockfreq = 0U; + 8001df2: 2300 movs r3, #0 + 8001df4: 623b str r3, [r7, #32] +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t prediv2 = 0U, pll2mul = 0U; +#endif /*RCC_CFGR2_PREDIV1SRC*/ + + tmpreg = RCC->CFGR; + 8001df6: 4b22 ldr r3, [pc, #136] ; (8001e80 ) + 8001df8: 685b ldr r3, [r3, #4] + 8001dfa: 61fb str r3, [r7, #28] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001dfc: 69fb ldr r3, [r7, #28] + 8001dfe: f003 030c and.w r3, r3, #12 + 8001e02: 2b04 cmp r3, #4 + 8001e04: d002 beq.n 8001e0c + 8001e06: 2b08 cmp r3, #8 + 8001e08: d003 beq.n 8001e12 + 8001e0a: e02d b.n 8001e68 + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001e0c: 4b1d ldr r3, [pc, #116] ; (8001e84 ) + 8001e0e: 623b str r3, [r7, #32] + break; + 8001e10: e02d b.n 8001e6e + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + 8001e12: 69fb ldr r3, [r7, #28] + 8001e14: 0c9b lsrs r3, r3, #18 + 8001e16: f003 030f and.w r3, r3, #15 + 8001e1a: f107 0228 add.w r2, r7, #40 ; 0x28 + 8001e1e: 4413 add r3, r2 + 8001e20: f813 3c24 ldrb.w r3, [r3, #-36] + 8001e24: 617b str r3, [r7, #20] + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + 8001e26: 69fb ldr r3, [r7, #28] + 8001e28: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001e2c: 2b00 cmp r3, #0 + 8001e2e: d013 beq.n 8001e58 + { +#if defined(RCC_CFGR2_PREDIV1) + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; + 8001e30: 4b13 ldr r3, [pc, #76] ; (8001e80 ) + 8001e32: 685b ldr r3, [r3, #4] + 8001e34: 0c5b lsrs r3, r3, #17 + 8001e36: f003 0301 and.w r3, r3, #1 + 8001e3a: f107 0228 add.w r2, r7, #40 ; 0x28 + 8001e3e: 4413 add r3, r2 + 8001e40: f813 3c28 ldrb.w r3, [r3, #-40] + 8001e44: 61bb str r3, [r7, #24] + { + pllclk = pllclk / 2; + } +#else + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); + 8001e46: 697b ldr r3, [r7, #20] + 8001e48: 4a0e ldr r2, [pc, #56] ; (8001e84 ) + 8001e4a: fb02 f203 mul.w r2, r2, r3 + 8001e4e: 69bb ldr r3, [r7, #24] + 8001e50: fbb2 f3f3 udiv r3, r2, r3 + 8001e54: 627b str r3, [r7, #36] ; 0x24 + 8001e56: e004 b.n 8001e62 +#endif /*RCC_CFGR2_PREDIV1SRC*/ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + 8001e58: 697b ldr r3, [r7, #20] + 8001e5a: 4a0b ldr r2, [pc, #44] ; (8001e88 ) + 8001e5c: fb02 f303 mul.w r3, r2, r3 + 8001e60: 627b str r3, [r7, #36] ; 0x24 + } + sysclockfreq = pllclk; + 8001e62: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001e64: 623b str r3, [r7, #32] + break; + 8001e66: e002 b.n 8001e6e + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + 8001e68: 4b06 ldr r3, [pc, #24] ; (8001e84 ) + 8001e6a: 623b str r3, [r7, #32] + break; + 8001e6c: bf00 nop + } + } + return sysclockfreq; + 8001e6e: 6a3b ldr r3, [r7, #32] +} + 8001e70: 4618 mov r0, r3 + 8001e72: 3728 adds r7, #40 ; 0x28 + 8001e74: 46bd mov sp, r7 + 8001e76: bc90 pop {r4, r7} + 8001e78: 4770 bx lr + 8001e7a: bf00 nop + 8001e7c: 08005228 .word 0x08005228 + 8001e80: 40021000 .word 0x40021000 + 8001e84: 007a1200 .word 0x007a1200 + 8001e88: 003d0900 .word 0x003d0900 + +08001e8c : + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + 8001e8c: b480 push {r7} + 8001e8e: b085 sub sp, #20 + 8001e90: af00 add r7, sp, #0 + 8001e92: 6078 str r0, [r7, #4] + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + 8001e94: 4b0a ldr r3, [pc, #40] ; (8001ec0 ) + 8001e96: 681b ldr r3, [r3, #0] + 8001e98: 4a0a ldr r2, [pc, #40] ; (8001ec4 ) + 8001e9a: fba2 2303 umull r2, r3, r2, r3 + 8001e9e: 0a5b lsrs r3, r3, #9 + 8001ea0: 687a ldr r2, [r7, #4] + 8001ea2: fb02 f303 mul.w r3, r2, r3 + 8001ea6: 60fb str r3, [r7, #12] + do + { + __NOP(); + 8001ea8: bf00 nop + } + while (Delay --); + 8001eaa: 68fb ldr r3, [r7, #12] + 8001eac: 1e5a subs r2, r3, #1 + 8001eae: 60fa str r2, [r7, #12] + 8001eb0: 2b00 cmp r3, #0 + 8001eb2: d1f9 bne.n 8001ea8 +} + 8001eb4: bf00 nop + 8001eb6: bf00 nop + 8001eb8: 3714 adds r7, #20 + 8001eba: 46bd mov sp, r7 + 8001ebc: bc80 pop {r7} + 8001ebe: 4770 bx lr + 8001ec0: 20000000 .word 0x20000000 + 8001ec4: 10624dd3 .word 0x10624dd3 + +08001ec8 : + * @param ExtTiming Pointer to SRAM extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + 8001ec8: b580 push {r7, lr} + 8001eca: b084 sub sp, #16 + 8001ecc: af00 add r7, sp, #0 + 8001ece: 60f8 str r0, [r7, #12] + 8001ed0: 60b9 str r1, [r7, #8] + 8001ed2: 607a str r2, [r7, #4] + /* Check the SRAM handle parameter */ + if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE)) + 8001ed4: 68fb ldr r3, [r7, #12] + 8001ed6: 2b00 cmp r3, #0 + 8001ed8: d004 beq.n 8001ee4 + 8001eda: 68fb ldr r3, [r7, #12] + 8001edc: 699b ldr r3, [r3, #24] + 8001ede: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8001ee2: d101 bne.n 8001ee8 + { + return HAL_ERROR; + 8001ee4: 2301 movs r3, #1 + 8001ee6: e038 b.n 8001f5a + } + + if (hsram->State == HAL_SRAM_STATE_RESET) + 8001ee8: 68fb ldr r3, [r7, #12] + 8001eea: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8001eee: b2db uxtb r3, r3 + 8001ef0: 2b00 cmp r3, #0 + 8001ef2: d106 bne.n 8001f02 + { + /* Allocate lock resource and initialize it */ + hsram->Lock = HAL_UNLOCKED; + 8001ef4: 68fb ldr r3, [r7, #12] + 8001ef6: 2200 movs r2, #0 + 8001ef8: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init the low level hardware */ + hsram->MspInitCallback(hsram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SRAM_MspInit(hsram); + 8001efc: 68f8 ldr r0, [r7, #12] + 8001efe: f7fe ffc7 bl 8000e90 +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + } + + /* Initialize SRAM control Interface */ + (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + 8001f02: 68fb ldr r3, [r7, #12] + 8001f04: 681a ldr r2, [r3, #0] + 8001f06: 68fb ldr r3, [r7, #12] + 8001f08: 3308 adds r3, #8 + 8001f0a: 4619 mov r1, r3 + 8001f0c: 4610 mov r0, r2 + 8001f0e: f000 f829 bl 8001f64 + + /* Initialize SRAM timing Interface */ + (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + 8001f12: 68fb ldr r3, [r7, #12] + 8001f14: 6818 ldr r0, [r3, #0] + 8001f16: 68fb ldr r3, [r7, #12] + 8001f18: 689b ldr r3, [r3, #8] + 8001f1a: 461a mov r2, r3 + 8001f1c: 68b9 ldr r1, [r7, #8] + 8001f1e: f000 f88b bl 8002038 + + /* Initialize SRAM extended mode timing Interface */ + (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + 8001f22: 68fb ldr r3, [r7, #12] + 8001f24: 6858 ldr r0, [r3, #4] + 8001f26: 68fb ldr r3, [r7, #12] + 8001f28: 689a ldr r2, [r3, #8] + 8001f2a: 68fb ldr r3, [r7, #12] + 8001f2c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001f2e: 6879 ldr r1, [r7, #4] + 8001f30: f000 f8b6 bl 80020a0 + hsram->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + 8001f34: 68fb ldr r3, [r7, #12] + 8001f36: 681b ldr r3, [r3, #0] + 8001f38: 68fa ldr r2, [r7, #12] + 8001f3a: 6892 ldr r2, [r2, #8] + 8001f3c: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8001f40: 68fb ldr r3, [r7, #12] + 8001f42: 681b ldr r3, [r3, #0] + 8001f44: 68fa ldr r2, [r7, #12] + 8001f46: 6892 ldr r2, [r2, #8] + 8001f48: f041 0101 orr.w r1, r1, #1 + 8001f4c: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Initialize the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + 8001f50: 68fb ldr r3, [r7, #12] + 8001f52: 2201 movs r2, #1 + 8001f54: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + return HAL_OK; + 8001f58: 2300 movs r3, #0 +} + 8001f5a: 4618 mov r0, r3 + 8001f5c: 3710 adds r7, #16 + 8001f5e: 46bd mov sp, r7 + 8001f60: bd80 pop {r7, pc} + ... + +08001f64 : + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init) +{ + 8001f64: b480 push {r7} + 8001f66: b087 sub sp, #28 + 8001f68: af00 add r7, sp, #0 + 8001f6a: 6078 str r0, [r7, #4] + 8001f6c: 6039 str r1, [r7, #0] + assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); + 8001f6e: 683b ldr r3, [r7, #0] + 8001f70: 681a ldr r2, [r3, #0] + 8001f72: 687b ldr r3, [r7, #4] + 8001f74: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001f78: 683a ldr r2, [r7, #0] + 8001f7a: 6812 ldr r2, [r2, #0] + 8001f7c: f023 0101 bic.w r1, r3, #1 + 8001f80: 687b ldr r3, [r7, #4] + 8001f82: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR) + 8001f86: 683b ldr r3, [r7, #0] + 8001f88: 689b ldr r3, [r3, #8] + 8001f8a: 2b08 cmp r3, #8 + 8001f8c: d102 bne.n 8001f94 + { + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + 8001f8e: 2340 movs r3, #64 ; 0x40 + 8001f90: 617b str r3, [r7, #20] + 8001f92: e001 b.n 8001f98 + } + else + { + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE; + 8001f94: 2300 movs r3, #0 + 8001f96: 617b str r3, [r7, #20] + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + 8001f98: 683b ldr r3, [r7, #0] + 8001f9a: 685a ldr r2, [r3, #4] + btcr_reg = (flashaccess | \ + 8001f9c: 697b ldr r3, [r7, #20] + 8001f9e: 431a orrs r2, r3 + Init->MemoryType | \ + 8001fa0: 683b ldr r3, [r7, #0] + 8001fa2: 689b ldr r3, [r3, #8] + Init->DataAddressMux | \ + 8001fa4: 431a orrs r2, r3 + Init->MemoryDataWidth | \ + 8001fa6: 683b ldr r3, [r7, #0] + 8001fa8: 68db ldr r3, [r3, #12] + Init->MemoryType | \ + 8001faa: 431a orrs r2, r3 + Init->BurstAccessMode | \ + 8001fac: 683b ldr r3, [r7, #0] + 8001fae: 691b ldr r3, [r3, #16] + Init->MemoryDataWidth | \ + 8001fb0: 431a orrs r2, r3 + Init->WaitSignalPolarity | \ + 8001fb2: 683b ldr r3, [r7, #0] + 8001fb4: 695b ldr r3, [r3, #20] + Init->BurstAccessMode | \ + 8001fb6: 431a orrs r2, r3 + Init->WaitSignalActive | \ + 8001fb8: 683b ldr r3, [r7, #0] + 8001fba: 69db ldr r3, [r3, #28] + Init->WaitSignalPolarity | \ + 8001fbc: 431a orrs r2, r3 + Init->WriteOperation | \ + 8001fbe: 683b ldr r3, [r7, #0] + 8001fc0: 6a1b ldr r3, [r3, #32] + Init->WaitSignalActive | \ + 8001fc2: 431a orrs r2, r3 + Init->WaitSignal | \ + 8001fc4: 683b ldr r3, [r7, #0] + 8001fc6: 6a5b ldr r3, [r3, #36] ; 0x24 + Init->WriteOperation | \ + 8001fc8: 431a orrs r2, r3 + Init->ExtendedMode | \ + 8001fca: 683b ldr r3, [r7, #0] + 8001fcc: 6a9b ldr r3, [r3, #40] ; 0x28 + Init->WaitSignal | \ + 8001fce: 431a orrs r2, r3 + Init->AsynchronousWait | \ + 8001fd0: 683b ldr r3, [r7, #0] + 8001fd2: 6adb ldr r3, [r3, #44] ; 0x2c + Init->ExtendedMode | \ + 8001fd4: 431a orrs r2, r3 + Init->WriteBurst); + 8001fd6: 683b ldr r3, [r7, #0] + 8001fd8: 6b1b ldr r3, [r3, #48] ; 0x30 + btcr_reg = (flashaccess | \ + 8001fda: 4313 orrs r3, r2 + 8001fdc: 613b str r3, [r7, #16] + + btcr_reg |= Init->WrapMode; + 8001fde: 683b ldr r3, [r7, #0] + 8001fe0: 699b ldr r3, [r3, #24] + 8001fe2: 693a ldr r2, [r7, #16] + 8001fe4: 4313 orrs r3, r2 + 8001fe6: 613b str r3, [r7, #16] + btcr_reg |= Init->PageSize; + 8001fe8: 683b ldr r3, [r7, #0] + 8001fea: 6b5b ldr r3, [r3, #52] ; 0x34 + 8001fec: 693a ldr r2, [r7, #16] + 8001fee: 4313 orrs r3, r2 + 8001ff0: 613b str r3, [r7, #16] + + mask = (FSMC_BCRx_MBKEN | + 8001ff2: 4b10 ldr r3, [pc, #64] ; (8002034 ) + 8001ff4: 60fb str r3, [r7, #12] + FSMC_BCRx_WAITEN | + FSMC_BCRx_EXTMOD | + FSMC_BCRx_ASYNCWAIT | + FSMC_BCRx_CBURSTRW); + + mask |= FSMC_BCRx_WRAPMOD; + 8001ff6: 68fb ldr r3, [r7, #12] + 8001ff8: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8001ffc: 60fb str r3, [r7, #12] + mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */ + 8001ffe: 68fb ldr r3, [r7, #12] + 8002000: f443 23e0 orr.w r3, r3, #458752 ; 0x70000 + 8002004: 60fb str r3, [r7, #12] + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + 8002006: 683b ldr r3, [r7, #0] + 8002008: 681a ldr r2, [r3, #0] + 800200a: 687b ldr r3, [r7, #4] + 800200c: f853 2022 ldr.w r2, [r3, r2, lsl #2] + 8002010: 68fb ldr r3, [r7, #12] + 8002012: 43db mvns r3, r3 + 8002014: ea02 0103 and.w r1, r2, r3 + 8002018: 683b ldr r3, [r7, #0] + 800201a: 681a ldr r2, [r3, #0] + 800201c: 693b ldr r3, [r7, #16] + 800201e: 4319 orrs r1, r3 + 8002020: 687b ldr r3, [r7, #4] + 8002022: f843 1022 str.w r1, [r3, r2, lsl #2] + + + return HAL_OK; + 8002026: 2300 movs r3, #0 +} + 8002028: 4618 mov r0, r3 + 800202a: 371c adds r7, #28 + 800202c: 46bd mov sp, r7 + 800202e: bc80 pop {r7} + 8002030: 4770 bx lr + 8002032: bf00 nop + 8002034: 0008fb7f .word 0x0008fb7f + +08002038 : + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + 8002038: b480 push {r7} + 800203a: b085 sub sp, #20 + 800203c: af00 add r7, sp, #0 + 800203e: 60f8 str r0, [r7, #12] + 8002040: 60b9 str r1, [r7, #8] + 8002042: 607a str r2, [r7, #4] + assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Set FSMC_NORSRAM device timing parameters */ + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + 8002044: 687b ldr r3, [r7, #4] + 8002046: 1c5a adds r2, r3, #1 + 8002048: 68fb ldr r3, [r7, #12] + 800204a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800204e: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000 + 8002052: 68bb ldr r3, [r7, #8] + 8002054: 681a ldr r2, [r3, #0] + 8002056: 68bb ldr r3, [r7, #8] + 8002058: 685b ldr r3, [r3, #4] + 800205a: 011b lsls r3, r3, #4 + 800205c: 431a orrs r2, r3 + 800205e: 68bb ldr r3, [r7, #8] + 8002060: 689b ldr r3, [r3, #8] + 8002062: 021b lsls r3, r3, #8 + 8002064: 431a orrs r2, r3 + 8002066: 68bb ldr r3, [r7, #8] + 8002068: 68db ldr r3, [r3, #12] + 800206a: 041b lsls r3, r3, #16 + 800206c: 431a orrs r2, r3 + 800206e: 68bb ldr r3, [r7, #8] + 8002070: 691b ldr r3, [r3, #16] + 8002072: 3b01 subs r3, #1 + 8002074: 051b lsls r3, r3, #20 + 8002076: 431a orrs r2, r3 + 8002078: 68bb ldr r3, [r7, #8] + 800207a: 695b ldr r3, [r3, #20] + 800207c: 3b02 subs r3, #2 + 800207e: 061b lsls r3, r3, #24 + 8002080: 431a orrs r2, r3 + 8002082: 68bb ldr r3, [r7, #8] + 8002084: 699b ldr r3, [r3, #24] + 8002086: 4313 orrs r3, r2 + 8002088: 687a ldr r2, [r7, #4] + 800208a: 3201 adds r2, #1 + 800208c: 4319 orrs r1, r3 + 800208e: 68fb ldr r3, [r7, #12] + 8002090: f843 1022 str.w r1, [r3, r2, lsl #2] + ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | + (Timing->AccessMode))); + + return HAL_OK; + 8002094: 2300 movs r3, #0 +} + 8002096: 4618 mov r0, r3 + 8002098: 3714 adds r7, #20 + 800209a: 46bd mov sp, r7 + 800209c: bc80 pop {r7} + 800209e: 4770 bx lr + +080020a0 : + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ + 80020a0: b480 push {r7} + 80020a2: b085 sub sp, #20 + 80020a4: af00 add r7, sp, #0 + 80020a6: 60f8 str r0, [r7, #12] + 80020a8: 60b9 str r1, [r7, #8] + 80020aa: 607a str r2, [r7, #4] + 80020ac: 603b str r3, [r7, #0] + /* Check the parameters */ + assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) + 80020ae: 683b ldr r3, [r7, #0] + 80020b0: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 80020b4: d11d bne.n 80020f2 + assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ +#if defined(FSMC_BWTRx_BUSTURN) + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + 80020b6: 68fb ldr r3, [r7, #12] + 80020b8: 687a ldr r2, [r7, #4] + 80020ba: f853 2022 ldr.w r2, [r3, r2, lsl #2] + 80020be: 4b13 ldr r3, [pc, #76] ; (800210c ) + 80020c0: 4013 ands r3, r2 + 80020c2: 68ba ldr r2, [r7, #8] + 80020c4: 6811 ldr r1, [r2, #0] + 80020c6: 68ba ldr r2, [r7, #8] + 80020c8: 6852 ldr r2, [r2, #4] + 80020ca: 0112 lsls r2, r2, #4 + 80020cc: 4311 orrs r1, r2 + 80020ce: 68ba ldr r2, [r7, #8] + 80020d0: 6892 ldr r2, [r2, #8] + 80020d2: 0212 lsls r2, r2, #8 + 80020d4: 4311 orrs r1, r2 + 80020d6: 68ba ldr r2, [r7, #8] + 80020d8: 6992 ldr r2, [r2, #24] + 80020da: 4311 orrs r1, r2 + 80020dc: 68ba ldr r2, [r7, #8] + 80020de: 68d2 ldr r2, [r2, #12] + 80020e0: 0412 lsls r2, r2, #16 + 80020e2: 430a orrs r2, r1 + 80020e4: ea43 0102 orr.w r1, r3, r2 + 80020e8: 68fb ldr r3, [r7, #12] + 80020ea: 687a ldr r2, [r7, #4] + 80020ec: f843 1022 str.w r1, [r3, r2, lsl #2] + 80020f0: e005 b.n 80020fe + (((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos))); +#endif /* FSMC_BWTRx_BUSTURN */ + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFFU; + 80020f2: 68fb ldr r3, [r7, #12] + 80020f4: 687a ldr r2, [r7, #4] + 80020f6: f06f 4170 mvn.w r1, #4026531840 ; 0xf0000000 + 80020fa: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + return HAL_OK; + 80020fe: 2300 movs r3, #0 +} + 8002100: 4618 mov r0, r3 + 8002102: 3714 adds r7, #20 + 8002104: 46bd mov sp, r7 + 8002106: bc80 pop {r7} + 8002108: 4770 bx lr + 800210a: bf00 nop + 800210c: cff00000 .word 0xcff00000 + +08002110 : +_lcd_dev lcddev; //管理LCD重要参数 +//**************************************************几种快速接口 +//写寄存器函数 +//regval:寄存器值 +void LCD_WR_REG(uint16_t regval) +{ + 8002110: b480 push {r7} + 8002112: b083 sub sp, #12 + 8002114: af00 add r7, sp, #0 + 8002116: 4603 mov r3, r0 + 8002118: 80fb strh r3, [r7, #6] + LCD_REG_ADDRESS=regval;//写入要写的寄存器序号 + 800211a: f04f 42d8 mov.w r2, #1811939328 ; 0x6c000000 + 800211e: 88fb ldrh r3, [r7, #6] + 8002120: 8013 strh r3, [r2, #0] +} + 8002122: bf00 nop + 8002124: 370c adds r7, #12 + 8002126: 46bd mov sp, r7 + 8002128: bc80 pop {r7} + 800212a: 4770 bx lr + +0800212c : +//写LCD数据 +//data:要写入的值 +void LCD_WR_DATA(uint16_t data) +{ + 800212c: b480 push {r7} + 800212e: b083 sub sp, #12 + 8002130: af00 add r7, sp, #0 + 8002132: 4603 mov r3, r0 + 8002134: 80fb strh r3, [r7, #6] + LCD_DATA_ADDRESS=data; + 8002136: 4a04 ldr r2, [pc, #16] ; (8002148 ) + 8002138: 88fb ldrh r3, [r7, #6] + 800213a: 8013 strh r3, [r2, #0] +} + 800213c: bf00 nop + 800213e: 370c adds r7, #12 + 8002140: 46bd mov sp, r7 + 8002142: bc80 pop {r7} + 8002144: 4770 bx lr + 8002146: bf00 nop + 8002148: 6c000800 .word 0x6c000800 + +0800214c : +} +//写寄存器 +//LCD_Reg:寄存器地址 +//LCD_RegValue:要写入的数据 +void LCD_WriteReg(uint16_t LCD_Reg, uint16_t LCD_RegValue) +{ + 800214c: b480 push {r7} + 800214e: b083 sub sp, #12 + 8002150: af00 add r7, sp, #0 + 8002152: 4603 mov r3, r0 + 8002154: 460a mov r2, r1 + 8002156: 80fb strh r3, [r7, #6] + 8002158: 4613 mov r3, r2 + 800215a: 80bb strh r3, [r7, #4] + LCD_REG_ADDRESS = LCD_Reg; //写入要写的寄存器序号 + 800215c: f04f 42d8 mov.w r2, #1811939328 ; 0x6c000000 + 8002160: 88fb ldrh r3, [r7, #6] + 8002162: 8013 strh r3, [r2, #0] + LCD_DATA_ADDRESS = LCD_RegValue;//写入数据 + 8002164: 4a03 ldr r2, [pc, #12] ; (8002174 ) + 8002166: 88bb ldrh r3, [r7, #4] + 8002168: 8013 strh r3, [r2, #0] +} + 800216a: bf00 nop + 800216c: 370c adds r7, #12 + 800216e: 46bd mov sp, r7 + 8002170: bc80 pop {r7} + 8002172: 4770 bx lr + 8002174: 6c000800 .word 0x6c000800 + +08002178 : +//读寄存器 +//LCD_Reg:寄存器地址 +//返回值:读到的数据 +uint16_t LCD_ReadReg(uint16_t LCD_Reg) +{ + 8002178: b480 push {r7} + 800217a: b083 sub sp, #12 + 800217c: af00 add r7, sp, #0 + 800217e: 4603 mov r3, r0 + 8002180: 80fb strh r3, [r7, #6] + LCD_REG_ADDRESS=LCD_Reg; //写入要读的寄存器序号 + 8002182: f04f 42d8 mov.w r2, #1811939328 ; 0x6c000000 + 8002186: 88fb ldrh r3, [r7, #6] + 8002188: 8013 strh r3, [r2, #0] + //delay_us(5); + return LCD_DATA_ADDRESS; //返回读到的值 + 800218a: 4b04 ldr r3, [pc, #16] ; (800219c ) + 800218c: 881b ldrh r3, [r3, #0] + 800218e: b29b uxth r3, r3 +} + 8002190: 4618 mov r0, r3 + 8002192: 370c adds r7, #12 + 8002194: 46bd mov sp, r7 + 8002196: bc80 pop {r7} + 8002198: 4770 bx lr + 800219a: bf00 nop + 800219c: 6c000800 .word 0x6c000800 + +080021a0 : +//注意:其他函数可能会受到此函数设置的影响(尤其是9341/6804这两个奇葩), +//所以,一般设置为L2R_U2D即可,如果设置为其他扫描方式,可能导致显示不正常. +//dir:0~7,代表8个方向(具体定义见lcd.h) +//9320/9325/9328/4531/4535/1505/b505/8989/5408/9341/5310等IC已经实际测试 +void LCD_Scan_Dir(uint8_t dir) +{ + 80021a0: b580 push {r7, lr} + 80021a2: b084 sub sp, #16 + 80021a4: af00 add r7, sp, #0 + 80021a6: 4603 mov r3, r0 + 80021a8: 71fb strb r3, [r7, #7] + uint16_t regval=0; + 80021aa: 2300 movs r3, #0 + 80021ac: 81fb strh r3, [r7, #14] + uint8_t dirreg=0; + 80021ae: 2300 movs r3, #0 + 80021b0: 737b strb r3, [r7, #13] + uint16_t temp; + if(lcddev.dir==1&&lcddev.id!=0X6804)//横屏时，对6804不改变扫描方向！ + 80021b2: 4ba8 ldr r3, [pc, #672] ; (8002454 ) + 80021b4: 799b ldrb r3, [r3, #6] + 80021b6: 2b01 cmp r3, #1 + 80021b8: d134 bne.n 8002224 + 80021ba: 4ba6 ldr r3, [pc, #664] ; (8002454 ) + 80021bc: 889b ldrh r3, [r3, #4] + 80021be: f646 0204 movw r2, #26628 ; 0x6804 + 80021c2: 4293 cmp r3, r2 + 80021c4: d02e beq.n 8002224 + { + switch(dir)//方向转换 + 80021c6: 79fb ldrb r3, [r7, #7] + 80021c8: 2b07 cmp r3, #7 + 80021ca: d82c bhi.n 8002226 + 80021cc: a201 add r2, pc, #4 ; (adr r2, 80021d4 ) + 80021ce: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80021d2: bf00 nop + 80021d4: 080021f5 .word 0x080021f5 + 80021d8: 080021fb .word 0x080021fb + 80021dc: 08002201 .word 0x08002201 + 80021e0: 08002207 .word 0x08002207 + 80021e4: 0800220d .word 0x0800220d + 80021e8: 08002213 .word 0x08002213 + 80021ec: 08002219 .word 0x08002219 + 80021f0: 0800221f .word 0x0800221f + { + case 0:dir=6;break; + 80021f4: 2306 movs r3, #6 + 80021f6: 71fb strb r3, [r7, #7] + 80021f8: e015 b.n 8002226 + case 1:dir=7;break; + 80021fa: 2307 movs r3, #7 + 80021fc: 71fb strb r3, [r7, #7] + 80021fe: e012 b.n 8002226 + case 2:dir=4;break; + 8002200: 2304 movs r3, #4 + 8002202: 71fb strb r3, [r7, #7] + 8002204: e00f b.n 8002226 + case 3:dir=5;break; + 8002206: 2305 movs r3, #5 + 8002208: 71fb strb r3, [r7, #7] + 800220a: e00c b.n 8002226 + case 4:dir=1;break; + 800220c: 2301 movs r3, #1 + 800220e: 71fb strb r3, [r7, #7] + 8002210: e009 b.n 8002226 + case 5:dir=0;break; + 8002212: 2300 movs r3, #0 + 8002214: 71fb strb r3, [r7, #7] + 8002216: e006 b.n 8002226 + case 6:dir=3;break; + 8002218: 2303 movs r3, #3 + 800221a: 71fb strb r3, [r7, #7] + 800221c: e003 b.n 8002226 + case 7:dir=2;break; + 800221e: 2302 movs r3, #2 + 8002220: 71fb strb r3, [r7, #7] + 8002222: e000 b.n 8002226 + } + } + 8002224: bf00 nop + if(lcddev.id==0x9341||lcddev.id==0X6804||lcddev.id==0X5310)//9341/6804/5310,很特殊 + 8002226: 4b8b ldr r3, [pc, #556] ; (8002454 ) + 8002228: 889b ldrh r3, [r3, #4] + 800222a: f249 3241 movw r2, #37697 ; 0x9341 + 800222e: 4293 cmp r3, r2 + 8002230: d00c beq.n 800224c + 8002232: 4b88 ldr r3, [pc, #544] ; (8002454 ) + 8002234: 889b ldrh r3, [r3, #4] + 8002236: f646 0204 movw r2, #26628 ; 0x6804 + 800223a: 4293 cmp r3, r2 + 800223c: d006 beq.n 800224c + 800223e: 4b85 ldr r3, [pc, #532] ; (8002454 ) + 8002240: 889b ldrh r3, [r3, #4] + 8002242: f245 3210 movw r2, #21264 ; 0x5310 + 8002246: 4293 cmp r3, r2 + 8002248: f040 80bb bne.w 80023c2 + { + switch(dir) + 800224c: 79fb ldrb r3, [r7, #7] + 800224e: 2b07 cmp r3, #7 + 8002250: d835 bhi.n 80022be + 8002252: a201 add r2, pc, #4 ; (adr r2, 8002258 ) + 8002254: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002258: 080022bf .word 0x080022bf + 800225c: 08002279 .word 0x08002279 + 8002260: 08002283 .word 0x08002283 + 8002264: 0800228d .word 0x0800228d + 8002268: 08002297 .word 0x08002297 + 800226c: 080022a1 .word 0x080022a1 + 8002270: 080022ab .word 0x080022ab + 8002274: 080022b5 .word 0x080022b5 + { + case L2R_U2D://从左到右,从上到下 + regval|=(0<<7)|(0<<6)|(0<<5); + break; + case L2R_D2U://从左到右,从下到上 + regval|=(1<<7)|(0<<6)|(0<<5); + 8002278: 89fb ldrh r3, [r7, #14] + 800227a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800227e: 81fb strh r3, [r7, #14] + break; + 8002280: e01d b.n 80022be + case R2L_U2D://从右到左,从上到下 + regval|=(0<<7)|(1<<6)|(0<<5); + 8002282: 89fb ldrh r3, [r7, #14] + 8002284: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002288: 81fb strh r3, [r7, #14] + break; + 800228a: e018 b.n 80022be + case R2L_D2U://从右到左,从下到上 + regval|=(1<<7)|(1<<6)|(0<<5); + 800228c: 89fb ldrh r3, [r7, #14] + 800228e: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 8002292: 81fb strh r3, [r7, #14] + break; + 8002294: e013 b.n 80022be + case U2D_L2R://从上到下,从左到右 + regval|=(0<<7)|(0<<6)|(1<<5); + 8002296: 89fb ldrh r3, [r7, #14] + 8002298: f043 0320 orr.w r3, r3, #32 + 800229c: 81fb strh r3, [r7, #14] + break; + 800229e: e00e b.n 80022be + case U2D_R2L://从上到下,从右到左 + regval|=(0<<7)|(1<<6)|(1<<5); + 80022a0: 89fb ldrh r3, [r7, #14] + 80022a2: f043 0360 orr.w r3, r3, #96 ; 0x60 + 80022a6: 81fb strh r3, [r7, #14] + break; + 80022a8: e009 b.n 80022be + case D2U_L2R://从下到上,从左到右 + regval|=(1<<7)|(0<<6)|(1<<5); + 80022aa: 89fb ldrh r3, [r7, #14] + 80022ac: f043 03a0 orr.w r3, r3, #160 ; 0xa0 + 80022b0: 81fb strh r3, [r7, #14] + break; + 80022b2: e004 b.n 80022be + case D2U_R2L://从下到上,从右到左 + regval|=(1<<7)|(1<<6)|(1<<5); + 80022b4: 89fb ldrh r3, [r7, #14] + 80022b6: f043 03e0 orr.w r3, r3, #224 ; 0xe0 + 80022ba: 81fb strh r3, [r7, #14] + break; + 80022bc: bf00 nop + } + dirreg=0X36; + 80022be: 2336 movs r3, #54 ; 0x36 + 80022c0: 737b strb r3, [r7, #13] + if(lcddev.id!=0X5310)regval|=0X08;//5310不需要BGR + 80022c2: 4b64 ldr r3, [pc, #400] ; (8002454 ) + 80022c4: 889b ldrh r3, [r3, #4] + 80022c6: f245 3210 movw r2, #21264 ; 0x5310 + 80022ca: 4293 cmp r3, r2 + 80022cc: d003 beq.n 80022d6 + 80022ce: 89fb ldrh r3, [r7, #14] + 80022d0: f043 0308 orr.w r3, r3, #8 + 80022d4: 81fb strh r3, [r7, #14] + if(lcddev.id==0X6804)regval|=0x02;//6804的BIT6和9341的反了 + 80022d6: 4b5f ldr r3, [pc, #380] ; (8002454 ) + 80022d8: 889b ldrh r3, [r3, #4] + 80022da: f646 0204 movw r2, #26628 ; 0x6804 + 80022de: 4293 cmp r3, r2 + 80022e0: d103 bne.n 80022ea + 80022e2: 89fb ldrh r3, [r7, #14] + 80022e4: f043 0302 orr.w r3, r3, #2 + 80022e8: 81fb strh r3, [r7, #14] + LCD_WriteReg(dirreg,regval); + 80022ea: 7b7b ldrb r3, [r7, #13] + 80022ec: b29b uxth r3, r3 + 80022ee: 89fa ldrh r2, [r7, #14] + 80022f0: 4611 mov r1, r2 + 80022f2: 4618 mov r0, r3 + 80022f4: f7ff ff2a bl 800214c + if((regval&0X20)||lcddev.dir==1) + 80022f8: 89fb ldrh r3, [r7, #14] + 80022fa: f003 0320 and.w r3, r3, #32 + 80022fe: 2b00 cmp r3, #0 + 8002300: d103 bne.n 800230a + 8002302: 4b54 ldr r3, [pc, #336] ; (8002454 ) + 8002304: 799b ldrb r3, [r3, #6] + 8002306: 2b01 cmp r3, #1 + 8002308: d110 bne.n 800232c + { + if(lcddev.width) + 800230c: 881a ldrh r2, [r3, #0] + 800230e: 4b51 ldr r3, [pc, #324] ; (8002454 ) + 8002310: 885b ldrh r3, [r3, #2] + 8002312: 429a cmp r2, r3 + 8002314: d21a bcs.n 800234c + { + temp=lcddev.width; + 8002316: 4b4f ldr r3, [pc, #316] ; (8002454 ) + 8002318: 881b ldrh r3, [r3, #0] + 800231a: 817b strh r3, [r7, #10] + lcddev.width=lcddev.height; + 800231c: 4b4d ldr r3, [pc, #308] ; (8002454 ) + 800231e: 885a ldrh r2, [r3, #2] + 8002320: 4b4c ldr r3, [pc, #304] ; (8002454 ) + 8002322: 801a strh r2, [r3, #0] + lcddev.height=temp; + 8002324: 4a4b ldr r2, [pc, #300] ; (8002454 ) + 8002326: 897b ldrh r3, [r7, #10] + 8002328: 8053 strh r3, [r2, #2] + if(lcddev.width + } + }else + { + if(lcddev.width>lcddev.height)//交换X,Y + 800232c: 4b49 ldr r3, [pc, #292] ; (8002454 ) + 800232e: 881a ldrh r2, [r3, #0] + 8002330: 4b48 ldr r3, [pc, #288] ; (8002454 ) + 8002332: 885b ldrh r3, [r3, #2] + 8002334: 429a cmp r2, r3 + 8002336: d909 bls.n 800234c + { + temp=lcddev.width; + 8002338: 4b46 ldr r3, [pc, #280] ; (8002454 ) + 800233a: 881b ldrh r3, [r3, #0] + 800233c: 817b strh r3, [r7, #10] + lcddev.width=lcddev.height; + 800233e: 4b45 ldr r3, [pc, #276] ; (8002454 ) + 8002340: 885a ldrh r2, [r3, #2] + 8002342: 4b44 ldr r3, [pc, #272] ; (8002454 ) + 8002344: 801a strh r2, [r3, #0] + lcddev.height=temp; + 8002346: 4a43 ldr r2, [pc, #268] ; (8002454 ) + 8002348: 897b ldrh r3, [r7, #10] + 800234a: 8053 strh r3, [r2, #2] + } + } + LCD_WR_REG(lcddev.setxcmd); + 800234c: 4b41 ldr r3, [pc, #260] ; (8002454 ) + 800234e: 7a1b ldrb r3, [r3, #8] + 8002350: b29b uxth r3, r3 + 8002352: 4618 mov r0, r3 + 8002354: f7ff fedc bl 8002110 + LCD_WR_DATA(0);LCD_WR_DATA(0); + 8002358: 2000 movs r0, #0 + 800235a: f7ff fee7 bl 800212c + 800235e: 2000 movs r0, #0 + 8002360: f7ff fee4 bl 800212c + LCD_WR_DATA((lcddev.width-1)>>8);LCD_WR_DATA((lcddev.width-1)&0XFF); + 8002364: 4b3b ldr r3, [pc, #236] ; (8002454 ) + 8002366: 881b ldrh r3, [r3, #0] + 8002368: 3b01 subs r3, #1 + 800236a: 121b asrs r3, r3, #8 + 800236c: b29b uxth r3, r3 + 800236e: 4618 mov r0, r3 + 8002370: f7ff fedc bl 800212c + 8002374: 4b37 ldr r3, [pc, #220] ; (8002454 ) + 8002376: 881b ldrh r3, [r3, #0] + 8002378: 3b01 subs r3, #1 + 800237a: b29b uxth r3, r3 + 800237c: b2db uxtb r3, r3 + 800237e: b29b uxth r3, r3 + 8002380: 4618 mov r0, r3 + 8002382: f7ff fed3 bl 800212c + LCD_WR_REG(lcddev.setycmd); + 8002386: 4b33 ldr r3, [pc, #204] ; (8002454 ) + 8002388: 7a5b ldrb r3, [r3, #9] + 800238a: b29b uxth r3, r3 + 800238c: 4618 mov r0, r3 + 800238e: f7ff febf bl 8002110 + LCD_WR_DATA(0);LCD_WR_DATA(0); + 8002392: 2000 movs r0, #0 + 8002394: f7ff feca bl 800212c + 8002398: 2000 movs r0, #0 + 800239a: f7ff fec7 bl 800212c + LCD_WR_DATA((lcddev.height-1)>>8);LCD_WR_DATA((lcddev.height-1)&0XFF); + 800239e: 4b2d ldr r3, [pc, #180] ; (8002454 ) + 80023a0: 885b ldrh r3, [r3, #2] + 80023a2: 3b01 subs r3, #1 + 80023a4: 121b asrs r3, r3, #8 + 80023a6: b29b uxth r3, r3 + 80023a8: 4618 mov r0, r3 + 80023aa: f7ff febf bl 800212c + 80023ae: 4b29 ldr r3, [pc, #164] ; (8002454 ) + 80023b0: 885b ldrh r3, [r3, #2] + 80023b2: 3b01 subs r3, #1 + 80023b4: b29b uxth r3, r3 + 80023b6: b2db uxtb r3, r3 + 80023b8: b29b uxth r3, r3 + 80023ba: 4618 mov r0, r3 + 80023bc: f7ff feb6 bl 800212c + 80023c0: e058 b.n 8002474 + }else + { + switch(dir) + 80023c2: 79fb ldrb r3, [r7, #7] + 80023c4: 2b07 cmp r3, #7 + 80023c6: d836 bhi.n 8002436 + 80023c8: a201 add r2, pc, #4 ; (adr r2, 80023d0 ) + 80023ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80023ce: bf00 nop + 80023d0: 080023f1 .word 0x080023f1 + 80023d4: 080023fb .word 0x080023fb + 80023d8: 08002405 .word 0x08002405 + 80023dc: 08002437 .word 0x08002437 + 80023e0: 0800240f .word 0x0800240f + 80023e4: 08002419 .word 0x08002419 + 80023e8: 08002423 .word 0x08002423 + 80023ec: 0800242d .word 0x0800242d + { + case L2R_U2D://从左到右,从上到下 + regval|=(1<<5)|(1<<4)|(0<<3); + 80023f0: 89fb ldrh r3, [r7, #14] + 80023f2: f043 0330 orr.w r3, r3, #48 ; 0x30 + 80023f6: 81fb strh r3, [r7, #14] + break; + 80023f8: e01d b.n 8002436 + case L2R_D2U://从左到右,从下到上 + regval|=(0<<5)|(1<<4)|(0<<3); + 80023fa: 89fb ldrh r3, [r7, #14] + 80023fc: f043 0310 orr.w r3, r3, #16 + 8002400: 81fb strh r3, [r7, #14] + break; + 8002402: e018 b.n 8002436 + case R2L_U2D://从右到左,从上到下 + regval|=(1<<5)|(0<<4)|(0<<3); + 8002404: 89fb ldrh r3, [r7, #14] + 8002406: f043 0320 orr.w r3, r3, #32 + 800240a: 81fb strh r3, [r7, #14] + break; + 800240c: e013 b.n 8002436 + case R2L_D2U://从右到左,从下到上 + regval|=(0<<5)|(0<<4)|(0<<3); + break; + case U2D_L2R://从上到下,从左到右 + regval|=(1<<5)|(1<<4)|(1<<3); + 800240e: 89fb ldrh r3, [r7, #14] + 8002410: f043 0338 orr.w r3, r3, #56 ; 0x38 + 8002414: 81fb strh r3, [r7, #14] + break; + 8002416: e00e b.n 8002436 + case U2D_R2L://从上到下,从右到左 + regval|=(1<<5)|(0<<4)|(1<<3); + 8002418: 89fb ldrh r3, [r7, #14] + 800241a: f043 0328 orr.w r3, r3, #40 ; 0x28 + 800241e: 81fb strh r3, [r7, #14] + break; + 8002420: e009 b.n 8002436 + case D2U_L2R://从下到上,从左到右 + regval|=(0<<5)|(1<<4)|(1<<3); + 8002422: 89fb ldrh r3, [r7, #14] + 8002424: f043 0318 orr.w r3, r3, #24 + 8002428: 81fb strh r3, [r7, #14] + break; + 800242a: e004 b.n 8002436 + case D2U_R2L://从下到上,从右到左 + regval|=(0<<5)|(0<<4)|(1<<3); + 800242c: 89fb ldrh r3, [r7, #14] + 800242e: f043 0308 orr.w r3, r3, #8 + 8002432: 81fb strh r3, [r7, #14] + break; + 8002434: bf00 nop + } + if(lcddev.id==0x8989)//8989 IC + 8002436: 4b07 ldr r3, [pc, #28] ; (8002454 ) + 8002438: 889b ldrh r3, [r3, #4] + 800243a: f648 1289 movw r2, #35209 ; 0x8989 + 800243e: 4293 cmp r3, r2 + 8002440: d10a bne.n 8002458 + { + dirreg=0X11; + 8002442: 2311 movs r3, #17 + 8002444: 737b strb r3, [r7, #13] + regval|=0X6040; //65K + 8002446: 89fb ldrh r3, [r7, #14] + 8002448: f443 43c0 orr.w r3, r3, #24576 ; 0x6000 + 800244c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002450: 81fb strh r3, [r7, #14] + 8002452: e007 b.n 8002464 + 8002454: 20000254 .word 0x20000254 + }else//其他驱动IC + { + dirreg=0X03; + 8002458: 2303 movs r3, #3 + 800245a: 737b strb r3, [r7, #13] + regval|=1<<12; + 800245c: 89fb ldrh r3, [r7, #14] + 800245e: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8002462: 81fb strh r3, [r7, #14] + } + LCD_WriteReg(dirreg,regval); + 8002464: 7b7b ldrb r3, [r7, #13] + 8002466: b29b uxth r3, r3 + 8002468: 89fa ldrh r2, [r7, #14] + 800246a: 4611 mov r1, r2 + 800246c: 4618 mov r0, r3 + 800246e: f7ff fe6d bl 800214c + } +} + 8002472: bf00 nop + 8002474: bf00 nop + 8002476: 3710 adds r7, #16 + 8002478: 46bd mov sp, r7 + 800247a: bd80 pop {r7, pc} + +0800247c : +//设置LCD显示方向 +//dir:0,竖屏；1,横屏 +void LCD_Display_Dir(uint8_t dir) +{ + 800247c: b580 push {r7, lr} + 800247e: b082 sub sp, #8 + 8002480: af00 add r7, sp, #0 + 8002482: 4603 mov r3, r0 + 8002484: 71fb strb r3, [r7, #7] + if(dir==0) //竖屏 + 8002486: 79fb ldrb r3, [r7, #7] + 8002488: 2b00 cmp r3, #0 + 800248a: d154 bne.n 8002536 + { + lcddev.dir=0; //竖屏 + 800248c: 4b5d ldr r3, [pc, #372] ; (8002604 ) + 800248e: 2200 movs r2, #0 + 8002490: 719a strb r2, [r3, #6] + lcddev.width=240; + 8002492: 4b5c ldr r3, [pc, #368] ; (8002604 ) + 8002494: 22f0 movs r2, #240 ; 0xf0 + 8002496: 801a strh r2, [r3, #0] + lcddev.height=320; + 8002498: 4b5a ldr r3, [pc, #360] ; (8002604 ) + 800249a: f44f 72a0 mov.w r2, #320 ; 0x140 + 800249e: 805a strh r2, [r3, #2] + if(lcddev.id==0X9341||lcddev.id==0X6804||lcddev.id==0X5310) + 80024a0: 4b58 ldr r3, [pc, #352] ; (8002604 ) + 80024a2: 889b ldrh r3, [r3, #4] + 80024a4: f249 3241 movw r2, #37697 ; 0x9341 + 80024a8: 4293 cmp r3, r2 + 80024aa: d00b beq.n 80024c4 + 80024ac: 4b55 ldr r3, [pc, #340] ; (8002604 ) + 80024ae: 889b ldrh r3, [r3, #4] + 80024b0: f646 0204 movw r2, #26628 ; 0x6804 + 80024b4: 4293 cmp r3, r2 + 80024b6: d005 beq.n 80024c4 + 80024b8: 4b52 ldr r3, [pc, #328] ; (8002604 ) + 80024ba: 889b ldrh r3, [r3, #4] + 80024bc: f245 3210 movw r2, #21264 ; 0x5310 + 80024c0: 4293 cmp r3, r2 + 80024c2: d11e bne.n 8002502 + { + lcddev.wramcmd=0X2C; + 80024c4: 4b4f ldr r3, [pc, #316] ; (8002604 ) + 80024c6: 222c movs r2, #44 ; 0x2c + 80024c8: 71da strb r2, [r3, #7] + lcddev.setxcmd=0X2A; + 80024ca: 4b4e ldr r3, [pc, #312] ; (8002604 ) + 80024cc: 222a movs r2, #42 ; 0x2a + 80024ce: 721a strb r2, [r3, #8] + lcddev.setycmd=0X2B; + 80024d0: 4b4c ldr r3, [pc, #304] ; (8002604 ) + 80024d2: 222b movs r2, #43 ; 0x2b + 80024d4: 725a strb r2, [r3, #9] + if(lcddev.id==0X6804||lcddev.id==0X5310) + 80024d6: 4b4b ldr r3, [pc, #300] ; (8002604 ) + 80024d8: 889b ldrh r3, [r3, #4] + 80024da: f646 0204 movw r2, #26628 ; 0x6804 + 80024de: 4293 cmp r3, r2 + 80024e0: d006 beq.n 80024f0 + 80024e2: 4b48 ldr r3, [pc, #288] ; (8002604 ) + 80024e4: 889b ldrh r3, [r3, #4] + 80024e6: f245 3210 movw r2, #21264 ; 0x5310 + 80024ea: 4293 cmp r3, r2 + 80024ec: f040 8081 bne.w 80025f2 + { + lcddev.width=320; + 80024f0: 4b44 ldr r3, [pc, #272] ; (8002604 ) + 80024f2: f44f 72a0 mov.w r2, #320 ; 0x140 + 80024f6: 801a strh r2, [r3, #0] + lcddev.height=480; + 80024f8: 4b42 ldr r3, [pc, #264] ; (8002604 ) + 80024fa: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 80024fe: 805a strh r2, [r3, #2] + if(lcddev.id==0X6804||lcddev.id==0X5310) + 8002500: e077 b.n 80025f2 + } + }else if(lcddev.id==0X8989) + 8002502: 4b40 ldr r3, [pc, #256] ; (8002604 ) + 8002504: 889b ldrh r3, [r3, #4] + 8002506: f648 1289 movw r2, #35209 ; 0x8989 + 800250a: 4293 cmp r3, r2 + 800250c: d109 bne.n 8002522 + { + lcddev.wramcmd=R34; + 800250e: 4b3d ldr r3, [pc, #244] ; (8002604 ) + 8002510: 2222 movs r2, #34 ; 0x22 + 8002512: 71da strb r2, [r3, #7] + lcddev.setxcmd=0X4E; + 8002514: 4b3b ldr r3, [pc, #236] ; (8002604 ) + 8002516: 224e movs r2, #78 ; 0x4e + 8002518: 721a strb r2, [r3, #8] + lcddev.setycmd=0X4F; + 800251a: 4b3a ldr r3, [pc, #232] ; (8002604 ) + 800251c: 224f movs r2, #79 ; 0x4f + 800251e: 725a strb r2, [r3, #9] + 8002520: e068 b.n 80025f4 + }else + { + lcddev.wramcmd=R34; + 8002522: 4b38 ldr r3, [pc, #224] ; (8002604 ) + 8002524: 2222 movs r2, #34 ; 0x22 + 8002526: 71da strb r2, [r3, #7] + lcddev.setxcmd=R32; + 8002528: 4b36 ldr r3, [pc, #216] ; (8002604 ) + 800252a: 2220 movs r2, #32 + 800252c: 721a strb r2, [r3, #8] + lcddev.setycmd=R33; + 800252e: 4b35 ldr r3, [pc, #212] ; (8002604 ) + 8002530: 2221 movs r2, #33 ; 0x21 + 8002532: 725a strb r2, [r3, #9] + 8002534: e05e b.n 80025f4 + } + }else //横屏 + { + lcddev.dir=1; //横屏 + 8002536: 4b33 ldr r3, [pc, #204] ; (8002604 ) + 8002538: 2201 movs r2, #1 + 800253a: 719a strb r2, [r3, #6] + lcddev.width=320; + 800253c: 4b31 ldr r3, [pc, #196] ; (8002604 ) + 800253e: f44f 72a0 mov.w r2, #320 ; 0x140 + 8002542: 801a strh r2, [r3, #0] + lcddev.height=240; + 8002544: 4b2f ldr r3, [pc, #188] ; (8002604 ) + 8002546: 22f0 movs r2, #240 ; 0xf0 + 8002548: 805a strh r2, [r3, #2] + if(lcddev.id==0X9341||lcddev.id==0X5310) + 800254a: 4b2e ldr r3, [pc, #184] ; (8002604 ) + 800254c: 889b ldrh r3, [r3, #4] + 800254e: f249 3241 movw r2, #37697 ; 0x9341 + 8002552: 4293 cmp r3, r2 + 8002554: d005 beq.n 8002562 + 8002556: 4b2b ldr r3, [pc, #172] ; (8002604 ) + 8002558: 889b ldrh r3, [r3, #4] + 800255a: f245 3210 movw r2, #21264 ; 0x5310 + 800255e: 4293 cmp r3, r2 + 8002560: d109 bne.n 8002576 + { + lcddev.wramcmd=0X2C; + 8002562: 4b28 ldr r3, [pc, #160] ; (8002604 ) + 8002564: 222c movs r2, #44 ; 0x2c + 8002566: 71da strb r2, [r3, #7] + lcddev.setxcmd=0X2A; + 8002568: 4b26 ldr r3, [pc, #152] ; (8002604 ) + 800256a: 222a movs r2, #42 ; 0x2a + 800256c: 721a strb r2, [r3, #8] + lcddev.setycmd=0X2B; + 800256e: 4b25 ldr r3, [pc, #148] ; (8002604 ) + 8002570: 222b movs r2, #43 ; 0x2b + 8002572: 725a strb r2, [r3, #9] + 8002574: e028 b.n 80025c8 + }else if(lcddev.id==0X6804) + 8002576: 4b23 ldr r3, [pc, #140] ; (8002604 ) + 8002578: 889b ldrh r3, [r3, #4] + 800257a: f646 0204 movw r2, #26628 ; 0x6804 + 800257e: 4293 cmp r3, r2 + 8002580: d109 bne.n 8002596 + { + lcddev.wramcmd=0X2C; + 8002582: 4b20 ldr r3, [pc, #128] ; (8002604 ) + 8002584: 222c movs r2, #44 ; 0x2c + 8002586: 71da strb r2, [r3, #7] + lcddev.setxcmd=0X2B; + 8002588: 4b1e ldr r3, [pc, #120] ; (8002604 ) + 800258a: 222b movs r2, #43 ; 0x2b + 800258c: 721a strb r2, [r3, #8] + lcddev.setycmd=0X2A; + 800258e: 4b1d ldr r3, [pc, #116] ; (8002604 ) + 8002590: 222a movs r2, #42 ; 0x2a + 8002592: 725a strb r2, [r3, #9] + 8002594: e018 b.n 80025c8 + }else if(lcddev.id==0X8989) + 8002596: 4b1b ldr r3, [pc, #108] ; (8002604 ) + 8002598: 889b ldrh r3, [r3, #4] + 800259a: f648 1289 movw r2, #35209 ; 0x8989 + 800259e: 4293 cmp r3, r2 + 80025a0: d109 bne.n 80025b6 + { + lcddev.wramcmd=R34; + 80025a2: 4b18 ldr r3, [pc, #96] ; (8002604 ) + 80025a4: 2222 movs r2, #34 ; 0x22 + 80025a6: 71da strb r2, [r3, #7] + lcddev.setxcmd=0X4F; + 80025a8: 4b16 ldr r3, [pc, #88] ; (8002604 ) + 80025aa: 224f movs r2, #79 ; 0x4f + 80025ac: 721a strb r2, [r3, #8] + lcddev.setycmd=0X4E; + 80025ae: 4b15 ldr r3, [pc, #84] ; (8002604 ) + 80025b0: 224e movs r2, #78 ; 0x4e + 80025b2: 725a strb r2, [r3, #9] + 80025b4: e008 b.n 80025c8 + }else + { + lcddev.wramcmd=R34; + 80025b6: 4b13 ldr r3, [pc, #76] ; (8002604 ) + 80025b8: 2222 movs r2, #34 ; 0x22 + 80025ba: 71da strb r2, [r3, #7] + lcddev.setxcmd=R33; + 80025bc: 4b11 ldr r3, [pc, #68] ; (8002604 ) + 80025be: 2221 movs r2, #33 ; 0x21 + 80025c0: 721a strb r2, [r3, #8] + lcddev.setycmd=R32; + 80025c2: 4b10 ldr r3, [pc, #64] ; (8002604 ) + 80025c4: 2220 movs r2, #32 + 80025c6: 725a strb r2, [r3, #9] + } + if(lcddev.id==0X6804||lcddev.id==0X5310) + 80025c8: 4b0e ldr r3, [pc, #56] ; (8002604 ) + 80025ca: 889b ldrh r3, [r3, #4] + 80025cc: f646 0204 movw r2, #26628 ; 0x6804 + 80025d0: 4293 cmp r3, r2 + 80025d2: d005 beq.n 80025e0 + 80025d4: 4b0b ldr r3, [pc, #44] ; (8002604 ) + 80025d6: 889b ldrh r3, [r3, #4] + 80025d8: f245 3210 movw r2, #21264 ; 0x5310 + 80025dc: 4293 cmp r3, r2 + 80025de: d109 bne.n 80025f4 + { + lcddev.width=480; + 80025e0: 4b08 ldr r3, [pc, #32] ; (8002604 ) + 80025e2: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 80025e6: 801a strh r2, [r3, #0] + lcddev.height=320; + 80025e8: 4b06 ldr r3, [pc, #24] ; (8002604 ) + 80025ea: f44f 72a0 mov.w r2, #320 ; 0x140 + 80025ee: 805a strh r2, [r3, #2] + 80025f0: e000 b.n 80025f4 + if(lcddev.id==0X6804||lcddev.id==0X5310) + 80025f2: bf00 nop + } + } + LCD_Scan_Dir(DFT_SCAN_DIR); //默认扫描方向 + 80025f4: 2000 movs r0, #0 + 80025f6: f7ff fdd3 bl 80021a0 +} + 80025fa: bf00 nop + 80025fc: 3708 adds r7, #8 + 80025fe: 46bd mov sp, r7 + 8002600: bd80 pop {r7, pc} + 8002602: bf00 nop + 8002604: 20000254 .word 0x20000254 + +08002608 : + +//初始化lcd +//该初始化函数可以初始化各种液晶! +void LCDx_Init(void) +{ + 8002608: b580 push {r7, lr} + 800260a: af00 add r7, sp, #0 + + + HAL_Delay(50); // delay 50 ms + 800260c: 2032 movs r0, #50 ; 0x32 + 800260e: f7fe fdbf bl 8001190 + LCD_WriteReg(0x0000,0x0001); + 8002612: 2101 movs r1, #1 + 8002614: 2000 movs r0, #0 + 8002616: f7ff fd99 bl 800214c + HAL_Delay(50); // delay 50 ms + 800261a: 2032 movs r0, #50 ; 0x32 + 800261c: f7fe fdb8 bl 8001190 + lcddev.id = LCD_ReadReg(0x0000); + 8002620: 2000 movs r0, #0 + 8002622: f7ff fda9 bl 8002178 + 8002626: 4603 mov r3, r0 + 8002628: 461a mov r2, r3 + 800262a: 4b70 ldr r3, [pc, #448] ; (80027ec ) + 800262c: 809a strh r2, [r3, #4] + + + LCD_WriteReg(0x00E5,0x78F0); + 800262e: f647 01f0 movw r1, #30960 ; 0x78f0 + 8002632: 20e5 movs r0, #229 ; 0xe5 + 8002634: f7ff fd8a bl 800214c + LCD_WriteReg(0x0001,0x0100); + 8002638: f44f 7180 mov.w r1, #256 ; 0x100 + 800263c: 2001 movs r0, #1 + 800263e: f7ff fd85 bl 800214c + LCD_WriteReg(0x0002,0x0700); + 8002642: f44f 61e0 mov.w r1, #1792 ; 0x700 + 8002646: 2002 movs r0, #2 + 8002648: f7ff fd80 bl 800214c + LCD_WriteReg(0x0003,0x1030); + 800264c: f241 0130 movw r1, #4144 ; 0x1030 + 8002650: 2003 movs r0, #3 + 8002652: f7ff fd7b bl 800214c + LCD_WriteReg(0x0004,0x0000); + 8002656: 2100 movs r1, #0 + 8002658: 2004 movs r0, #4 + 800265a: f7ff fd77 bl 800214c + LCD_WriteReg(0x0008,0x0202); + 800265e: f240 2102 movw r1, #514 ; 0x202 + 8002662: 2008 movs r0, #8 + 8002664: f7ff fd72 bl 800214c + LCD_WriteReg(0x0009,0x0000); + 8002668: 2100 movs r1, #0 + 800266a: 2009 movs r0, #9 + 800266c: f7ff fd6e bl 800214c + LCD_WriteReg(0x000A,0x0000); + 8002670: 2100 movs r1, #0 + 8002672: 200a movs r0, #10 + 8002674: f7ff fd6a bl 800214c + LCD_WriteReg(0x000C,0x0000); + 8002678: 2100 movs r1, #0 + 800267a: 200c movs r0, #12 + 800267c: f7ff fd66 bl 800214c + LCD_WriteReg(0x000D,0x0000); + 8002680: 2100 movs r1, #0 + 8002682: 200d movs r0, #13 + 8002684: f7ff fd62 bl 800214c + LCD_WriteReg(0x000F,0x0000); + 8002688: 2100 movs r1, #0 + 800268a: 200f movs r0, #15 + 800268c: f7ff fd5e bl 800214c + //power on sequence VGHVGL + LCD_WriteReg(0x0010,0x0000); + 8002690: 2100 movs r1, #0 + 8002692: 2010 movs r0, #16 + 8002694: f7ff fd5a bl 800214c + LCD_WriteReg(0x0011,0x0007); + 8002698: 2107 movs r1, #7 + 800269a: 2011 movs r0, #17 + 800269c: f7ff fd56 bl 800214c + LCD_WriteReg(0x0012,0x0000); + 80026a0: 2100 movs r1, #0 + 80026a2: 2012 movs r0, #18 + 80026a4: f7ff fd52 bl 800214c + LCD_WriteReg(0x0013,0x0000); + 80026a8: 2100 movs r1, #0 + 80026aa: 2013 movs r0, #19 + 80026ac: f7ff fd4e bl 800214c + LCD_WriteReg(0x0007,0x0000); + 80026b0: 2100 movs r1, #0 + 80026b2: 2007 movs r0, #7 + 80026b4: f7ff fd4a bl 800214c + //vgh + LCD_WriteReg(0x0010,0x1690); + 80026b8: f241 6190 movw r1, #5776 ; 0x1690 + 80026bc: 2010 movs r0, #16 + 80026be: f7ff fd45 bl 800214c + LCD_WriteReg(0x0011,0x0227); + 80026c2: f240 2127 movw r1, #551 ; 0x227 + 80026c6: 2011 movs r0, #17 + 80026c8: f7ff fd40 bl 800214c + //delayms(100); + //vregiout + LCD_WriteReg(0x0012,0x009D); //0x001b + 80026cc: 219d movs r1, #157 ; 0x9d + 80026ce: 2012 movs r0, #18 + 80026d0: f7ff fd3c bl 800214c + //delayms(100); + //vom amplitude + LCD_WriteReg(0x0013,0x1900); + 80026d4: f44f 51c8 mov.w r1, #6400 ; 0x1900 + 80026d8: 2013 movs r0, #19 + 80026da: f7ff fd37 bl 800214c + //delayms(100); + //vom H + LCD_WriteReg(0x0029,0x0025); + 80026de: 2125 movs r1, #37 ; 0x25 + 80026e0: 2029 movs r0, #41 ; 0x29 + 80026e2: f7ff fd33 bl 800214c + LCD_WriteReg(0x002B,0x000D); + 80026e6: 210d movs r1, #13 + 80026e8: 202b movs r0, #43 ; 0x2b + 80026ea: f7ff fd2f bl 800214c + //gamma + LCD_WriteReg(0x0030,0x0007); + 80026ee: 2107 movs r1, #7 + 80026f0: 2030 movs r0, #48 ; 0x30 + 80026f2: f7ff fd2b bl 800214c + LCD_WriteReg(0x0031,0x0303); + 80026f6: f240 3103 movw r1, #771 ; 0x303 + 80026fa: 2031 movs r0, #49 ; 0x31 + 80026fc: f7ff fd26 bl 800214c + LCD_WriteReg(0x0032,0x0003);// 0006 + 8002700: 2103 movs r1, #3 + 8002702: 2032 movs r0, #50 ; 0x32 + 8002704: f7ff fd22 bl 800214c + LCD_WriteReg(0x0035,0x0206); + 8002708: f240 2106 movw r1, #518 ; 0x206 + 800270c: 2035 movs r0, #53 ; 0x35 + 800270e: f7ff fd1d bl 800214c + LCD_WriteReg(0x0036,0x0008); + 8002712: 2108 movs r1, #8 + 8002714: 2036 movs r0, #54 ; 0x36 + 8002716: f7ff fd19 bl 800214c + LCD_WriteReg(0x0037,0x0406); + 800271a: f240 4106 movw r1, #1030 ; 0x406 + 800271e: 2037 movs r0, #55 ; 0x37 + 8002720: f7ff fd14 bl 800214c + LCD_WriteReg(0x0038,0x0304);//0200 + 8002724: f44f 7141 mov.w r1, #772 ; 0x304 + 8002728: 2038 movs r0, #56 ; 0x38 + 800272a: f7ff fd0f bl 800214c + LCD_WriteReg(0x0039,0x0007); + 800272e: 2107 movs r1, #7 + 8002730: 2039 movs r0, #57 ; 0x39 + 8002732: f7ff fd0b bl 800214c + LCD_WriteReg(0x003C,0x0602);// 0504 + 8002736: f240 6102 movw r1, #1538 ; 0x602 + 800273a: 203c movs r0, #60 ; 0x3c + 800273c: f7ff fd06 bl 800214c + LCD_WriteReg(0x003D,0x0008); + 8002740: 2108 movs r1, #8 + 8002742: 203d movs r0, #61 ; 0x3d + 8002744: f7ff fd02 bl 800214c + //ram + LCD_WriteReg(0x0050,0x0000); + 8002748: 2100 movs r1, #0 + 800274a: 2050 movs r0, #80 ; 0x50 + 800274c: f7ff fcfe bl 800214c + LCD_WriteReg(0x0051,0x00EF); + 8002750: 21ef movs r1, #239 ; 0xef + 8002752: 2051 movs r0, #81 ; 0x51 + 8002754: f7ff fcfa bl 800214c + LCD_WriteReg(0x0052,0x0000); + 8002758: 2100 movs r1, #0 + 800275a: 2052 movs r0, #82 ; 0x52 + 800275c: f7ff fcf6 bl 800214c + LCD_WriteReg(0x0053,0x013F); + 8002760: f240 113f movw r1, #319 ; 0x13f + 8002764: 2053 movs r0, #83 ; 0x53 + 8002766: f7ff fcf1 bl 800214c + LCD_WriteReg(0x0060,0xA700); + 800276a: f44f 4127 mov.w r1, #42752 ; 0xa700 + 800276e: 2060 movs r0, #96 ; 0x60 + 8002770: f7ff fcec bl 800214c + LCD_WriteReg(0x0061,0x0001); + 8002774: 2101 movs r1, #1 + 8002776: 2061 movs r0, #97 ; 0x61 + 8002778: f7ff fce8 bl 800214c + LCD_WriteReg(0x006A,0x0000); + 800277c: 2100 movs r1, #0 + 800277e: 206a movs r0, #106 ; 0x6a + 8002780: f7ff fce4 bl 800214c + // + LCD_WriteReg(0x0080,0x0000); + 8002784: 2100 movs r1, #0 + 8002786: 2080 movs r0, #128 ; 0x80 + 8002788: f7ff fce0 bl 800214c + LCD_WriteReg(0x0081,0x0000); + 800278c: 2100 movs r1, #0 + 800278e: 2081 movs r0, #129 ; 0x81 + 8002790: f7ff fcdc bl 800214c + LCD_WriteReg(0x0082,0x0000); + 8002794: 2100 movs r1, #0 + 8002796: 2082 movs r0, #130 ; 0x82 + 8002798: f7ff fcd8 bl 800214c + LCD_WriteReg(0x0083,0x0000); + 800279c: 2100 movs r1, #0 + 800279e: 2083 movs r0, #131 ; 0x83 + 80027a0: f7ff fcd4 bl 800214c + LCD_WriteReg(0x0084,0x0000); + 80027a4: 2100 movs r1, #0 + 80027a6: 2084 movs r0, #132 ; 0x84 + 80027a8: f7ff fcd0 bl 800214c + LCD_WriteReg(0x0085,0x0000); + 80027ac: 2100 movs r1, #0 + 80027ae: 2085 movs r0, #133 ; 0x85 + 80027b0: f7ff fccc bl 800214c + // + LCD_WriteReg(0x0090,0x0010); + 80027b4: 2110 movs r1, #16 + 80027b6: 2090 movs r0, #144 ; 0x90 + 80027b8: f7ff fcc8 bl 800214c + LCD_WriteReg(0x0092,0x0600); + 80027bc: f44f 61c0 mov.w r1, #1536 ; 0x600 + 80027c0: 2092 movs r0, #146 ; 0x92 + 80027c2: f7ff fcc3 bl 800214c + + LCD_WriteReg(0x0007,0x0133); + 80027c6: f240 1133 movw r1, #307 ; 0x133 + 80027ca: 2007 movs r0, #7 + 80027cc: f7ff fcbe bl 800214c + LCD_WriteReg(0x00,0x0022);// + 80027d0: 2122 movs r1, #34 ; 0x22 + 80027d2: 2000 movs r0, #0 + 80027d4: f7ff fcba bl 800214c + + + LCD_Display_Dir(1); //默认为h屏 + 80027d8: 2001 movs r0, #1 + 80027da: f7ff fe4f bl 800247c + + LCD_BL(0); + 80027de: 2200 movs r2, #0 + 80027e0: 2101 movs r1, #1 + 80027e2: 4803 ldr r0, [pc, #12] ; (80027f0 ) + 80027e4: f7fe ff70 bl 80016c8 + +} + 80027e8: bf00 nop + 80027ea: bd80 pop {r7, pc} + 80027ec: 20000254 .word 0x20000254 + 80027f0: 40010c00 .word 0x40010c00 + +080027f4 : + * Author: wuwenfeng + */ +#include "LCD.h" + +void main_app() +{ + 80027f4: b580 push {r7, lr} + 80027f6: af00 add r7, sp, #0 + LCDx_Init(); + 80027f8: f7ff ff06 bl 8002608 + + while(1) + 80027fc: e7fe b.n 80027fc + ... + +08002800 <__errno>: + 8002800: 4b01 ldr r3, [pc, #4] ; (8002808 <__errno+0x8>) + 8002802: 6818 ldr r0, [r3, #0] + 8002804: 4770 bx lr + 8002806: bf00 nop + 8002808: 2000000c .word 0x2000000c + +0800280c <__libc_init_array>: + 800280c: b570 push {r4, r5, r6, lr} + 800280e: 2600 movs r6, #0 + 8002810: 4d0c ldr r5, [pc, #48] ; (8002844 <__libc_init_array+0x38>) + 8002812: 4c0d ldr r4, [pc, #52] ; (8002848 <__libc_init_array+0x3c>) + 8002814: 1b64 subs r4, r4, r5 + 8002816: 10a4 asrs r4, r4, #2 + 8002818: 42a6 cmp r6, r4 + 800281a: d109 bne.n 8002830 <__libc_init_array+0x24> + 800281c: f002 fcf6 bl 800520c <_init> + 8002820: 2600 movs r6, #0 + 8002822: 4d0a ldr r5, [pc, #40] ; (800284c <__libc_init_array+0x40>) + 8002824: 4c0a ldr r4, [pc, #40] ; (8002850 <__libc_init_array+0x44>) + 8002826: 1b64 subs r4, r4, r5 + 8002828: 10a4 asrs r4, r4, #2 + 800282a: 42a6 cmp r6, r4 + 800282c: d105 bne.n 800283a <__libc_init_array+0x2e> + 800282e: bd70 pop {r4, r5, r6, pc} + 8002830: f855 3b04 ldr.w r3, [r5], #4 + 8002834: 4798 blx r3 + 8002836: 3601 adds r6, #1 + 8002838: e7ee b.n 8002818 <__libc_init_array+0xc> + 800283a: f855 3b04 ldr.w r3, [r5], #4 + 800283e: 4798 blx r3 + 8002840: 3601 adds r6, #1 + 8002842: e7f2 b.n 800282a <__libc_init_array+0x1e> + 8002844: 0800562c .word 0x0800562c + 8002848: 0800562c .word 0x0800562c + 800284c: 0800562c .word 0x0800562c + 8002850: 08005630 .word 0x08005630 + +08002854 : + 8002854: 4603 mov r3, r0 + 8002856: 4402 add r2, r0 + 8002858: 4293 cmp r3, r2 + 800285a: d100 bne.n 800285e + 800285c: 4770 bx lr + 800285e: f803 1b01 strb.w r1, [r3], #1 + 8002862: e7f9 b.n 8002858 + +08002864 <__cvt>: + 8002864: 2b00 cmp r3, #0 + 8002866: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800286a: 461f mov r7, r3 + 800286c: bfbb ittet lt + 800286e: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 + 8002872: 461f movlt r7, r3 + 8002874: 2300 movge r3, #0 + 8002876: 232d movlt r3, #45 ; 0x2d + 8002878: b088 sub sp, #32 + 800287a: 4614 mov r4, r2 + 800287c: 9a12 ldr r2, [sp, #72] ; 0x48 + 800287e: 9d10 ldr r5, [sp, #64] ; 0x40 + 8002880: 7013 strb r3, [r2, #0] + 8002882: 9b14 ldr r3, [sp, #80] ; 0x50 + 8002884: f8dd a04c ldr.w sl, [sp, #76] ; 0x4c + 8002888: f023 0820 bic.w r8, r3, #32 + 800288c: f1b8 0f46 cmp.w r8, #70 ; 0x46 + 8002890: d005 beq.n 800289e <__cvt+0x3a> + 8002892: f1b8 0f45 cmp.w r8, #69 ; 0x45 + 8002896: d100 bne.n 800289a <__cvt+0x36> + 8002898: 3501 adds r5, #1 + 800289a: 2302 movs r3, #2 + 800289c: e000 b.n 80028a0 <__cvt+0x3c> + 800289e: 2303 movs r3, #3 + 80028a0: aa07 add r2, sp, #28 + 80028a2: 9204 str r2, [sp, #16] + 80028a4: aa06 add r2, sp, #24 + 80028a6: e9cd a202 strd sl, r2, [sp, #8] + 80028aa: e9cd 3500 strd r3, r5, [sp] + 80028ae: 4622 mov r2, r4 + 80028b0: 463b mov r3, r7 + 80028b2: f000 fcc5 bl 8003240 <_dtoa_r> + 80028b6: f1b8 0f47 cmp.w r8, #71 ; 0x47 + 80028ba: 4606 mov r6, r0 + 80028bc: d102 bne.n 80028c4 <__cvt+0x60> + 80028be: 9b11 ldr r3, [sp, #68] ; 0x44 + 80028c0: 07db lsls r3, r3, #31 + 80028c2: d522 bpl.n 800290a <__cvt+0xa6> + 80028c4: f1b8 0f46 cmp.w r8, #70 ; 0x46 + 80028c8: eb06 0905 add.w r9, r6, r5 + 80028cc: d110 bne.n 80028f0 <__cvt+0x8c> + 80028ce: 7833 ldrb r3, [r6, #0] + 80028d0: 2b30 cmp r3, #48 ; 0x30 + 80028d2: d10a bne.n 80028ea <__cvt+0x86> + 80028d4: 2200 movs r2, #0 + 80028d6: 2300 movs r3, #0 + 80028d8: 4620 mov r0, r4 + 80028da: 4639 mov r1, r7 + 80028dc: f7fe f8d0 bl 8000a80 <__aeabi_dcmpeq> + 80028e0: b918 cbnz r0, 80028ea <__cvt+0x86> + 80028e2: f1c5 0501 rsb r5, r5, #1 + 80028e6: f8ca 5000 str.w r5, [sl] + 80028ea: f8da 3000 ldr.w r3, [sl] + 80028ee: 4499 add r9, r3 + 80028f0: 2200 movs r2, #0 + 80028f2: 2300 movs r3, #0 + 80028f4: 4620 mov r0, r4 + 80028f6: 4639 mov r1, r7 + 80028f8: f7fe f8c2 bl 8000a80 <__aeabi_dcmpeq> + 80028fc: b108 cbz r0, 8002902 <__cvt+0x9e> + 80028fe: f8cd 901c str.w r9, [sp, #28] + 8002902: 2230 movs r2, #48 ; 0x30 + 8002904: 9b07 ldr r3, [sp, #28] + 8002906: 454b cmp r3, r9 + 8002908: d307 bcc.n 800291a <__cvt+0xb6> + 800290a: 4630 mov r0, r6 + 800290c: 9b07 ldr r3, [sp, #28] + 800290e: 9a15 ldr r2, [sp, #84] ; 0x54 + 8002910: 1b9b subs r3, r3, r6 + 8002912: 6013 str r3, [r2, #0] + 8002914: b008 add sp, #32 + 8002916: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800291a: 1c59 adds r1, r3, #1 + 800291c: 9107 str r1, [sp, #28] + 800291e: 701a strb r2, [r3, #0] + 8002920: e7f0 b.n 8002904 <__cvt+0xa0> + +08002922 <__exponent>: + 8002922: 4603 mov r3, r0 + 8002924: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8002926: 2900 cmp r1, #0 + 8002928: f803 2b02 strb.w r2, [r3], #2 + 800292c: bfb6 itet lt + 800292e: 222d movlt r2, #45 ; 0x2d + 8002930: 222b movge r2, #43 ; 0x2b + 8002932: 4249 neglt r1, r1 + 8002934: 2909 cmp r1, #9 + 8002936: 7042 strb r2, [r0, #1] + 8002938: dd2b ble.n 8002992 <__exponent+0x70> + 800293a: f10d 0407 add.w r4, sp, #7 + 800293e: 46a4 mov ip, r4 + 8002940: 270a movs r7, #10 + 8002942: fb91 f6f7 sdiv r6, r1, r7 + 8002946: 460a mov r2, r1 + 8002948: 46a6 mov lr, r4 + 800294a: fb07 1516 mls r5, r7, r6, r1 + 800294e: 2a63 cmp r2, #99 ; 0x63 + 8002950: f105 0530 add.w r5, r5, #48 ; 0x30 + 8002954: 4631 mov r1, r6 + 8002956: f104 34ff add.w r4, r4, #4294967295 ; 0xffffffff + 800295a: f80e 5c01 strb.w r5, [lr, #-1] + 800295e: dcf0 bgt.n 8002942 <__exponent+0x20> + 8002960: 3130 adds r1, #48 ; 0x30 + 8002962: f1ae 0502 sub.w r5, lr, #2 + 8002966: f804 1c01 strb.w r1, [r4, #-1] + 800296a: 4629 mov r1, r5 + 800296c: 1c44 adds r4, r0, #1 + 800296e: 4561 cmp r1, ip + 8002970: d30a bcc.n 8002988 <__exponent+0x66> + 8002972: f10d 0209 add.w r2, sp, #9 + 8002976: eba2 020e sub.w r2, r2, lr + 800297a: 4565 cmp r5, ip + 800297c: bf88 it hi + 800297e: 2200 movhi r2, #0 + 8002980: 4413 add r3, r2 + 8002982: 1a18 subs r0, r3, r0 + 8002984: b003 add sp, #12 + 8002986: bdf0 pop {r4, r5, r6, r7, pc} + 8002988: f811 2b01 ldrb.w r2, [r1], #1 + 800298c: f804 2f01 strb.w r2, [r4, #1]! + 8002990: e7ed b.n 800296e <__exponent+0x4c> + 8002992: 2330 movs r3, #48 ; 0x30 + 8002994: 3130 adds r1, #48 ; 0x30 + 8002996: 7083 strb r3, [r0, #2] + 8002998: 70c1 strb r1, [r0, #3] + 800299a: 1d03 adds r3, r0, #4 + 800299c: e7f1 b.n 8002982 <__exponent+0x60> + ... + +080029a0 <_printf_float>: + 80029a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80029a4: b091 sub sp, #68 ; 0x44 + 80029a6: 460c mov r4, r1 + 80029a8: f8dd 8068 ldr.w r8, [sp, #104] ; 0x68 + 80029ac: 4616 mov r6, r2 + 80029ae: 461f mov r7, r3 + 80029b0: 4605 mov r5, r0 + 80029b2: f001 fa33 bl 8003e1c <_localeconv_r> + 80029b6: 6803 ldr r3, [r0, #0] + 80029b8: 4618 mov r0, r3 + 80029ba: 9309 str r3, [sp, #36] ; 0x24 + 80029bc: f7fd fc34 bl 8000228 + 80029c0: 2300 movs r3, #0 + 80029c2: 930e str r3, [sp, #56] ; 0x38 + 80029c4: f8d8 3000 ldr.w r3, [r8] + 80029c8: 900a str r0, [sp, #40] ; 0x28 + 80029ca: 3307 adds r3, #7 + 80029cc: f023 0307 bic.w r3, r3, #7 + 80029d0: f103 0208 add.w r2, r3, #8 + 80029d4: f894 9018 ldrb.w r9, [r4, #24] + 80029d8: f8d4 b000 ldr.w fp, [r4] + 80029dc: f8c8 2000 str.w r2, [r8] + 80029e0: e9d3 2300 ldrd r2, r3, [r3] + 80029e4: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 + 80029e8: e9d4 8a12 ldrd r8, sl, [r4, #72] ; 0x48 + 80029ec: f02a 4300 bic.w r3, sl, #2147483648 ; 0x80000000 + 80029f0: 930b str r3, [sp, #44] ; 0x2c + 80029f2: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80029f6: 4640 mov r0, r8 + 80029f8: 4b9c ldr r3, [pc, #624] ; (8002c6c <_printf_float+0x2cc>) + 80029fa: 990b ldr r1, [sp, #44] ; 0x2c + 80029fc: f7fe f872 bl 8000ae4 <__aeabi_dcmpun> + 8002a00: bb70 cbnz r0, 8002a60 <_printf_float+0xc0> + 8002a02: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8002a06: 4640 mov r0, r8 + 8002a08: 4b98 ldr r3, [pc, #608] ; (8002c6c <_printf_float+0x2cc>) + 8002a0a: 990b ldr r1, [sp, #44] ; 0x2c + 8002a0c: f7fe f84c bl 8000aa8 <__aeabi_dcmple> + 8002a10: bb30 cbnz r0, 8002a60 <_printf_float+0xc0> + 8002a12: 2200 movs r2, #0 + 8002a14: 2300 movs r3, #0 + 8002a16: 4640 mov r0, r8 + 8002a18: 4651 mov r1, sl + 8002a1a: f7fe f83b bl 8000a94 <__aeabi_dcmplt> + 8002a1e: b110 cbz r0, 8002a26 <_printf_float+0x86> + 8002a20: 232d movs r3, #45 ; 0x2d + 8002a22: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8002a26: 4b92 ldr r3, [pc, #584] ; (8002c70 <_printf_float+0x2d0>) + 8002a28: 4892 ldr r0, [pc, #584] ; (8002c74 <_printf_float+0x2d4>) + 8002a2a: f1b9 0f47 cmp.w r9, #71 ; 0x47 + 8002a2e: bf94 ite ls + 8002a30: 4698 movls r8, r3 + 8002a32: 4680 movhi r8, r0 + 8002a34: 2303 movs r3, #3 + 8002a36: f04f 0a00 mov.w sl, #0 + 8002a3a: 6123 str r3, [r4, #16] + 8002a3c: f02b 0304 bic.w r3, fp, #4 + 8002a40: 6023 str r3, [r4, #0] + 8002a42: 4633 mov r3, r6 + 8002a44: 4621 mov r1, r4 + 8002a46: 4628 mov r0, r5 + 8002a48: 9700 str r7, [sp, #0] + 8002a4a: aa0f add r2, sp, #60 ; 0x3c + 8002a4c: f000 f9d4 bl 8002df8 <_printf_common> + 8002a50: 3001 adds r0, #1 + 8002a52: f040 8090 bne.w 8002b76 <_printf_float+0x1d6> + 8002a56: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8002a5a: b011 add sp, #68 ; 0x44 + 8002a5c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8002a60: 4642 mov r2, r8 + 8002a62: 4653 mov r3, sl + 8002a64: 4640 mov r0, r8 + 8002a66: 4651 mov r1, sl + 8002a68: f7fe f83c bl 8000ae4 <__aeabi_dcmpun> + 8002a6c: b148 cbz r0, 8002a82 <_printf_float+0xe2> + 8002a6e: f1ba 0f00 cmp.w sl, #0 + 8002a72: bfb8 it lt + 8002a74: 232d movlt r3, #45 ; 0x2d + 8002a76: 4880 ldr r0, [pc, #512] ; (8002c78 <_printf_float+0x2d8>) + 8002a78: bfb8 it lt + 8002a7a: f884 3043 strblt.w r3, [r4, #67] ; 0x43 + 8002a7e: 4b7f ldr r3, [pc, #508] ; (8002c7c <_printf_float+0x2dc>) + 8002a80: e7d3 b.n 8002a2a <_printf_float+0x8a> + 8002a82: 6863 ldr r3, [r4, #4] + 8002a84: f009 01df and.w r1, r9, #223 ; 0xdf + 8002a88: 1c5a adds r2, r3, #1 + 8002a8a: d142 bne.n 8002b12 <_printf_float+0x172> + 8002a8c: 2306 movs r3, #6 + 8002a8e: 6063 str r3, [r4, #4] + 8002a90: 2200 movs r2, #0 + 8002a92: 9206 str r2, [sp, #24] + 8002a94: aa0e add r2, sp, #56 ; 0x38 + 8002a96: e9cd 9204 strd r9, r2, [sp, #16] + 8002a9a: aa0d add r2, sp, #52 ; 0x34 + 8002a9c: f44b 6380 orr.w r3, fp, #1024 ; 0x400 + 8002aa0: 9203 str r2, [sp, #12] + 8002aa2: f10d 0233 add.w r2, sp, #51 ; 0x33 + 8002aa6: e9cd 3201 strd r3, r2, [sp, #4] + 8002aaa: 6023 str r3, [r4, #0] + 8002aac: 6863 ldr r3, [r4, #4] + 8002aae: 4642 mov r2, r8 + 8002ab0: 9300 str r3, [sp, #0] + 8002ab2: 4628 mov r0, r5 + 8002ab4: 4653 mov r3, sl + 8002ab6: 910b str r1, [sp, #44] ; 0x2c + 8002ab8: f7ff fed4 bl 8002864 <__cvt> + 8002abc: 990b ldr r1, [sp, #44] ; 0x2c + 8002abe: 4680 mov r8, r0 + 8002ac0: 2947 cmp r1, #71 ; 0x47 + 8002ac2: 990d ldr r1, [sp, #52] ; 0x34 + 8002ac4: d108 bne.n 8002ad8 <_printf_float+0x138> + 8002ac6: 1cc8 adds r0, r1, #3 + 8002ac8: db02 blt.n 8002ad0 <_printf_float+0x130> + 8002aca: 6863 ldr r3, [r4, #4] + 8002acc: 4299 cmp r1, r3 + 8002ace: dd40 ble.n 8002b52 <_printf_float+0x1b2> + 8002ad0: f1a9 0902 sub.w r9, r9, #2 + 8002ad4: fa5f f989 uxtb.w r9, r9 + 8002ad8: f1b9 0f65 cmp.w r9, #101 ; 0x65 + 8002adc: d81f bhi.n 8002b1e <_printf_float+0x17e> + 8002ade: 464a mov r2, r9 + 8002ae0: 3901 subs r1, #1 + 8002ae2: f104 0050 add.w r0, r4, #80 ; 0x50 + 8002ae6: 910d str r1, [sp, #52] ; 0x34 + 8002ae8: f7ff ff1b bl 8002922 <__exponent> + 8002aec: 9a0e ldr r2, [sp, #56] ; 0x38 + 8002aee: 4682 mov sl, r0 + 8002af0: 1813 adds r3, r2, r0 + 8002af2: 2a01 cmp r2, #1 + 8002af4: 6123 str r3, [r4, #16] + 8002af6: dc02 bgt.n 8002afe <_printf_float+0x15e> + 8002af8: 6822 ldr r2, [r4, #0] + 8002afa: 07d2 lsls r2, r2, #31 + 8002afc: d501 bpl.n 8002b02 <_printf_float+0x162> + 8002afe: 3301 adds r3, #1 + 8002b00: 6123 str r3, [r4, #16] + 8002b02: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 + 8002b06: 2b00 cmp r3, #0 + 8002b08: d09b beq.n 8002a42 <_printf_float+0xa2> + 8002b0a: 232d movs r3, #45 ; 0x2d + 8002b0c: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8002b10: e797 b.n 8002a42 <_printf_float+0xa2> + 8002b12: 2947 cmp r1, #71 ; 0x47 + 8002b14: d1bc bne.n 8002a90 <_printf_float+0xf0> + 8002b16: 2b00 cmp r3, #0 + 8002b18: d1ba bne.n 8002a90 <_printf_float+0xf0> + 8002b1a: 2301 movs r3, #1 + 8002b1c: e7b7 b.n 8002a8e <_printf_float+0xee> + 8002b1e: f1b9 0f66 cmp.w r9, #102 ; 0x66 + 8002b22: d118 bne.n 8002b56 <_printf_float+0x1b6> + 8002b24: 2900 cmp r1, #0 + 8002b26: 6863 ldr r3, [r4, #4] + 8002b28: dd0b ble.n 8002b42 <_printf_float+0x1a2> + 8002b2a: 6121 str r1, [r4, #16] + 8002b2c: b913 cbnz r3, 8002b34 <_printf_float+0x194> + 8002b2e: 6822 ldr r2, [r4, #0] + 8002b30: 07d0 lsls r0, r2, #31 + 8002b32: d502 bpl.n 8002b3a <_printf_float+0x19a> + 8002b34: 3301 adds r3, #1 + 8002b36: 440b add r3, r1 + 8002b38: 6123 str r3, [r4, #16] + 8002b3a: f04f 0a00 mov.w sl, #0 + 8002b3e: 65a1 str r1, [r4, #88] ; 0x58 + 8002b40: e7df b.n 8002b02 <_printf_float+0x162> + 8002b42: b913 cbnz r3, 8002b4a <_printf_float+0x1aa> + 8002b44: 6822 ldr r2, [r4, #0] + 8002b46: 07d2 lsls r2, r2, #31 + 8002b48: d501 bpl.n 8002b4e <_printf_float+0x1ae> + 8002b4a: 3302 adds r3, #2 + 8002b4c: e7f4 b.n 8002b38 <_printf_float+0x198> + 8002b4e: 2301 movs r3, #1 + 8002b50: e7f2 b.n 8002b38 <_printf_float+0x198> + 8002b52: f04f 0967 mov.w r9, #103 ; 0x67 + 8002b56: 9b0e ldr r3, [sp, #56] ; 0x38 + 8002b58: 4299 cmp r1, r3 + 8002b5a: db05 blt.n 8002b68 <_printf_float+0x1c8> + 8002b5c: 6823 ldr r3, [r4, #0] + 8002b5e: 6121 str r1, [r4, #16] + 8002b60: 07d8 lsls r0, r3, #31 + 8002b62: d5ea bpl.n 8002b3a <_printf_float+0x19a> + 8002b64: 1c4b adds r3, r1, #1 + 8002b66: e7e7 b.n 8002b38 <_printf_float+0x198> + 8002b68: 2900 cmp r1, #0 + 8002b6a: bfcc ite gt + 8002b6c: 2201 movgt r2, #1 + 8002b6e: f1c1 0202 rsble r2, r1, #2 + 8002b72: 4413 add r3, r2 + 8002b74: e7e0 b.n 8002b38 <_printf_float+0x198> + 8002b76: 6823 ldr r3, [r4, #0] + 8002b78: 055a lsls r2, r3, #21 + 8002b7a: d407 bmi.n 8002b8c <_printf_float+0x1ec> + 8002b7c: 6923 ldr r3, [r4, #16] + 8002b7e: 4642 mov r2, r8 + 8002b80: 4631 mov r1, r6 + 8002b82: 4628 mov r0, r5 + 8002b84: 47b8 blx r7 + 8002b86: 3001 adds r0, #1 + 8002b88: d12b bne.n 8002be2 <_printf_float+0x242> + 8002b8a: e764 b.n 8002a56 <_printf_float+0xb6> + 8002b8c: f1b9 0f65 cmp.w r9, #101 ; 0x65 + 8002b90: f240 80dd bls.w 8002d4e <_printf_float+0x3ae> + 8002b94: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 8002b98: 2200 movs r2, #0 + 8002b9a: 2300 movs r3, #0 + 8002b9c: f7fd ff70 bl 8000a80 <__aeabi_dcmpeq> + 8002ba0: 2800 cmp r0, #0 + 8002ba2: d033 beq.n 8002c0c <_printf_float+0x26c> + 8002ba4: 2301 movs r3, #1 + 8002ba6: 4631 mov r1, r6 + 8002ba8: 4628 mov r0, r5 + 8002baa: 4a35 ldr r2, [pc, #212] ; (8002c80 <_printf_float+0x2e0>) + 8002bac: 47b8 blx r7 + 8002bae: 3001 adds r0, #1 + 8002bb0: f43f af51 beq.w 8002a56 <_printf_float+0xb6> + 8002bb4: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 + 8002bb8: 429a cmp r2, r3 + 8002bba: db02 blt.n 8002bc2 <_printf_float+0x222> + 8002bbc: 6823 ldr r3, [r4, #0] + 8002bbe: 07d8 lsls r0, r3, #31 + 8002bc0: d50f bpl.n 8002be2 <_printf_float+0x242> + 8002bc2: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 8002bc6: 4631 mov r1, r6 + 8002bc8: 4628 mov r0, r5 + 8002bca: 47b8 blx r7 + 8002bcc: 3001 adds r0, #1 + 8002bce: f43f af42 beq.w 8002a56 <_printf_float+0xb6> + 8002bd2: f04f 0800 mov.w r8, #0 + 8002bd6: f104 091a add.w r9, r4, #26 + 8002bda: 9b0e ldr r3, [sp, #56] ; 0x38 + 8002bdc: 3b01 subs r3, #1 + 8002bde: 4543 cmp r3, r8 + 8002be0: dc09 bgt.n 8002bf6 <_printf_float+0x256> + 8002be2: 6823 ldr r3, [r4, #0] + 8002be4: 079b lsls r3, r3, #30 + 8002be6: f100 8102 bmi.w 8002dee <_printf_float+0x44e> + 8002bea: 68e0 ldr r0, [r4, #12] + 8002bec: 9b0f ldr r3, [sp, #60] ; 0x3c + 8002bee: 4298 cmp r0, r3 + 8002bf0: bfb8 it lt + 8002bf2: 4618 movlt r0, r3 + 8002bf4: e731 b.n 8002a5a <_printf_float+0xba> + 8002bf6: 2301 movs r3, #1 + 8002bf8: 464a mov r2, r9 + 8002bfa: 4631 mov r1, r6 + 8002bfc: 4628 mov r0, r5 + 8002bfe: 47b8 blx r7 + 8002c00: 3001 adds r0, #1 + 8002c02: f43f af28 beq.w 8002a56 <_printf_float+0xb6> + 8002c06: f108 0801 add.w r8, r8, #1 + 8002c0a: e7e6 b.n 8002bda <_printf_float+0x23a> + 8002c0c: 9b0d ldr r3, [sp, #52] ; 0x34 + 8002c0e: 2b00 cmp r3, #0 + 8002c10: dc38 bgt.n 8002c84 <_printf_float+0x2e4> + 8002c12: 2301 movs r3, #1 + 8002c14: 4631 mov r1, r6 + 8002c16: 4628 mov r0, r5 + 8002c18: 4a19 ldr r2, [pc, #100] ; (8002c80 <_printf_float+0x2e0>) + 8002c1a: 47b8 blx r7 + 8002c1c: 3001 adds r0, #1 + 8002c1e: f43f af1a beq.w 8002a56 <_printf_float+0xb6> + 8002c22: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 + 8002c26: 4313 orrs r3, r2 + 8002c28: d102 bne.n 8002c30 <_printf_float+0x290> + 8002c2a: 6823 ldr r3, [r4, #0] + 8002c2c: 07d9 lsls r1, r3, #31 + 8002c2e: d5d8 bpl.n 8002be2 <_printf_float+0x242> + 8002c30: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 8002c34: 4631 mov r1, r6 + 8002c36: 4628 mov r0, r5 + 8002c38: 47b8 blx r7 + 8002c3a: 3001 adds r0, #1 + 8002c3c: f43f af0b beq.w 8002a56 <_printf_float+0xb6> + 8002c40: f04f 0900 mov.w r9, #0 + 8002c44: f104 0a1a add.w sl, r4, #26 + 8002c48: 9b0d ldr r3, [sp, #52] ; 0x34 + 8002c4a: 425b negs r3, r3 + 8002c4c: 454b cmp r3, r9 + 8002c4e: dc01 bgt.n 8002c54 <_printf_float+0x2b4> + 8002c50: 9b0e ldr r3, [sp, #56] ; 0x38 + 8002c52: e794 b.n 8002b7e <_printf_float+0x1de> + 8002c54: 2301 movs r3, #1 + 8002c56: 4652 mov r2, sl + 8002c58: 4631 mov r1, r6 + 8002c5a: 4628 mov r0, r5 + 8002c5c: 47b8 blx r7 + 8002c5e: 3001 adds r0, #1 + 8002c60: f43f aef9 beq.w 8002a56 <_printf_float+0xb6> + 8002c64: f109 0901 add.w r9, r9, #1 + 8002c68: e7ee b.n 8002c48 <_printf_float+0x2a8> + 8002c6a: bf00 nop + 8002c6c: 7fefffff .word 0x7fefffff + 8002c70: 0800524c .word 0x0800524c + 8002c74: 08005250 .word 0x08005250 + 8002c78: 08005258 .word 0x08005258 + 8002c7c: 08005254 .word 0x08005254 + 8002c80: 0800525c .word 0x0800525c + 8002c84: 9a0e ldr r2, [sp, #56] ; 0x38 + 8002c86: 6da3 ldr r3, [r4, #88] ; 0x58 + 8002c88: 429a cmp r2, r3 + 8002c8a: bfa8 it ge + 8002c8c: 461a movge r2, r3 + 8002c8e: 2a00 cmp r2, #0 + 8002c90: 4691 mov r9, r2 + 8002c92: dc37 bgt.n 8002d04 <_printf_float+0x364> + 8002c94: f04f 0b00 mov.w fp, #0 + 8002c98: ea29 79e9 bic.w r9, r9, r9, asr #31 + 8002c9c: f104 021a add.w r2, r4, #26 + 8002ca0: f8d4 a058 ldr.w sl, [r4, #88] ; 0x58 + 8002ca4: ebaa 0309 sub.w r3, sl, r9 + 8002ca8: 455b cmp r3, fp + 8002caa: dc33 bgt.n 8002d14 <_printf_float+0x374> + 8002cac: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 + 8002cb0: 429a cmp r2, r3 + 8002cb2: db3b blt.n 8002d2c <_printf_float+0x38c> + 8002cb4: 6823 ldr r3, [r4, #0] + 8002cb6: 07da lsls r2, r3, #31 + 8002cb8: d438 bmi.n 8002d2c <_printf_float+0x38c> + 8002cba: 9a0e ldr r2, [sp, #56] ; 0x38 + 8002cbc: 990d ldr r1, [sp, #52] ; 0x34 + 8002cbe: eba2 030a sub.w r3, r2, sl + 8002cc2: eba2 0901 sub.w r9, r2, r1 + 8002cc6: 4599 cmp r9, r3 + 8002cc8: bfa8 it ge + 8002cca: 4699 movge r9, r3 + 8002ccc: f1b9 0f00 cmp.w r9, #0 + 8002cd0: dc34 bgt.n 8002d3c <_printf_float+0x39c> + 8002cd2: f04f 0800 mov.w r8, #0 + 8002cd6: ea29 79e9 bic.w r9, r9, r9, asr #31 + 8002cda: f104 0a1a add.w sl, r4, #26 + 8002cde: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 + 8002ce2: 1a9b subs r3, r3, r2 + 8002ce4: eba3 0309 sub.w r3, r3, r9 + 8002ce8: 4543 cmp r3, r8 + 8002cea: f77f af7a ble.w 8002be2 <_printf_float+0x242> + 8002cee: 2301 movs r3, #1 + 8002cf0: 4652 mov r2, sl + 8002cf2: 4631 mov r1, r6 + 8002cf4: 4628 mov r0, r5 + 8002cf6: 47b8 blx r7 + 8002cf8: 3001 adds r0, #1 + 8002cfa: f43f aeac beq.w 8002a56 <_printf_float+0xb6> + 8002cfe: f108 0801 add.w r8, r8, #1 + 8002d02: e7ec b.n 8002cde <_printf_float+0x33e> + 8002d04: 4613 mov r3, r2 + 8002d06: 4631 mov r1, r6 + 8002d08: 4642 mov r2, r8 + 8002d0a: 4628 mov r0, r5 + 8002d0c: 47b8 blx r7 + 8002d0e: 3001 adds r0, #1 + 8002d10: d1c0 bne.n 8002c94 <_printf_float+0x2f4> + 8002d12: e6a0 b.n 8002a56 <_printf_float+0xb6> + 8002d14: 2301 movs r3, #1 + 8002d16: 4631 mov r1, r6 + 8002d18: 4628 mov r0, r5 + 8002d1a: 920b str r2, [sp, #44] ; 0x2c + 8002d1c: 47b8 blx r7 + 8002d1e: 3001 adds r0, #1 + 8002d20: f43f ae99 beq.w 8002a56 <_printf_float+0xb6> + 8002d24: 9a0b ldr r2, [sp, #44] ; 0x2c + 8002d26: f10b 0b01 add.w fp, fp, #1 + 8002d2a: e7b9 b.n 8002ca0 <_printf_float+0x300> + 8002d2c: 4631 mov r1, r6 + 8002d2e: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 8002d32: 4628 mov r0, r5 + 8002d34: 47b8 blx r7 + 8002d36: 3001 adds r0, #1 + 8002d38: d1bf bne.n 8002cba <_printf_float+0x31a> + 8002d3a: e68c b.n 8002a56 <_printf_float+0xb6> + 8002d3c: 464b mov r3, r9 + 8002d3e: 4631 mov r1, r6 + 8002d40: 4628 mov r0, r5 + 8002d42: eb08 020a add.w r2, r8, sl + 8002d46: 47b8 blx r7 + 8002d48: 3001 adds r0, #1 + 8002d4a: d1c2 bne.n 8002cd2 <_printf_float+0x332> + 8002d4c: e683 b.n 8002a56 <_printf_float+0xb6> + 8002d4e: 9a0e ldr r2, [sp, #56] ; 0x38 + 8002d50: 2a01 cmp r2, #1 + 8002d52: dc01 bgt.n 8002d58 <_printf_float+0x3b8> + 8002d54: 07db lsls r3, r3, #31 + 8002d56: d537 bpl.n 8002dc8 <_printf_float+0x428> + 8002d58: 2301 movs r3, #1 + 8002d5a: 4642 mov r2, r8 + 8002d5c: 4631 mov r1, r6 + 8002d5e: 4628 mov r0, r5 + 8002d60: 47b8 blx r7 + 8002d62: 3001 adds r0, #1 + 8002d64: f43f ae77 beq.w 8002a56 <_printf_float+0xb6> + 8002d68: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 8002d6c: 4631 mov r1, r6 + 8002d6e: 4628 mov r0, r5 + 8002d70: 47b8 blx r7 + 8002d72: 3001 adds r0, #1 + 8002d74: f43f ae6f beq.w 8002a56 <_printf_float+0xb6> + 8002d78: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 8002d7c: 2200 movs r2, #0 + 8002d7e: 2300 movs r3, #0 + 8002d80: f7fd fe7e bl 8000a80 <__aeabi_dcmpeq> + 8002d84: b9d8 cbnz r0, 8002dbe <_printf_float+0x41e> + 8002d86: 9b0e ldr r3, [sp, #56] ; 0x38 + 8002d88: f108 0201 add.w r2, r8, #1 + 8002d8c: 3b01 subs r3, #1 + 8002d8e: 4631 mov r1, r6 + 8002d90: 4628 mov r0, r5 + 8002d92: 47b8 blx r7 + 8002d94: 3001 adds r0, #1 + 8002d96: d10e bne.n 8002db6 <_printf_float+0x416> + 8002d98: e65d b.n 8002a56 <_printf_float+0xb6> + 8002d9a: 2301 movs r3, #1 + 8002d9c: 464a mov r2, r9 + 8002d9e: 4631 mov r1, r6 + 8002da0: 4628 mov r0, r5 + 8002da2: 47b8 blx r7 + 8002da4: 3001 adds r0, #1 + 8002da6: f43f ae56 beq.w 8002a56 <_printf_float+0xb6> + 8002daa: f108 0801 add.w r8, r8, #1 + 8002dae: 9b0e ldr r3, [sp, #56] ; 0x38 + 8002db0: 3b01 subs r3, #1 + 8002db2: 4543 cmp r3, r8 + 8002db4: dcf1 bgt.n 8002d9a <_printf_float+0x3fa> + 8002db6: 4653 mov r3, sl + 8002db8: f104 0250 add.w r2, r4, #80 ; 0x50 + 8002dbc: e6e0 b.n 8002b80 <_printf_float+0x1e0> + 8002dbe: f04f 0800 mov.w r8, #0 + 8002dc2: f104 091a add.w r9, r4, #26 + 8002dc6: e7f2 b.n 8002dae <_printf_float+0x40e> + 8002dc8: 2301 movs r3, #1 + 8002dca: 4642 mov r2, r8 + 8002dcc: e7df b.n 8002d8e <_printf_float+0x3ee> + 8002dce: 2301 movs r3, #1 + 8002dd0: 464a mov r2, r9 + 8002dd2: 4631 mov r1, r6 + 8002dd4: 4628 mov r0, r5 + 8002dd6: 47b8 blx r7 + 8002dd8: 3001 adds r0, #1 + 8002dda: f43f ae3c beq.w 8002a56 <_printf_float+0xb6> + 8002dde: f108 0801 add.w r8, r8, #1 + 8002de2: 68e3 ldr r3, [r4, #12] + 8002de4: 990f ldr r1, [sp, #60] ; 0x3c + 8002de6: 1a5b subs r3, r3, r1 + 8002de8: 4543 cmp r3, r8 + 8002dea: dcf0 bgt.n 8002dce <_printf_float+0x42e> + 8002dec: e6fd b.n 8002bea <_printf_float+0x24a> + 8002dee: f04f 0800 mov.w r8, #0 + 8002df2: f104 0919 add.w r9, r4, #25 + 8002df6: e7f4 b.n 8002de2 <_printf_float+0x442> + +08002df8 <_printf_common>: + 8002df8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8002dfc: 4616 mov r6, r2 + 8002dfe: 4699 mov r9, r3 + 8002e00: 688a ldr r2, [r1, #8] + 8002e02: 690b ldr r3, [r1, #16] + 8002e04: 4607 mov r7, r0 + 8002e06: 4293 cmp r3, r2 + 8002e08: bfb8 it lt + 8002e0a: 4613 movlt r3, r2 + 8002e0c: 6033 str r3, [r6, #0] + 8002e0e: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 8002e12: 460c mov r4, r1 + 8002e14: f8dd 8020 ldr.w r8, [sp, #32] + 8002e18: b10a cbz r2, 8002e1e <_printf_common+0x26> + 8002e1a: 3301 adds r3, #1 + 8002e1c: 6033 str r3, [r6, #0] + 8002e1e: 6823 ldr r3, [r4, #0] + 8002e20: 0699 lsls r1, r3, #26 + 8002e22: bf42 ittt mi + 8002e24: 6833 ldrmi r3, [r6, #0] + 8002e26: 3302 addmi r3, #2 + 8002e28: 6033 strmi r3, [r6, #0] + 8002e2a: 6825 ldr r5, [r4, #0] + 8002e2c: f015 0506 ands.w r5, r5, #6 + 8002e30: d106 bne.n 8002e40 <_printf_common+0x48> + 8002e32: f104 0a19 add.w sl, r4, #25 + 8002e36: 68e3 ldr r3, [r4, #12] + 8002e38: 6832 ldr r2, [r6, #0] + 8002e3a: 1a9b subs r3, r3, r2 + 8002e3c: 42ab cmp r3, r5 + 8002e3e: dc28 bgt.n 8002e92 <_printf_common+0x9a> + 8002e40: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 8002e44: 1e13 subs r3, r2, #0 + 8002e46: 6822 ldr r2, [r4, #0] + 8002e48: bf18 it ne + 8002e4a: 2301 movne r3, #1 + 8002e4c: 0692 lsls r2, r2, #26 + 8002e4e: d42d bmi.n 8002eac <_printf_common+0xb4> + 8002e50: 4649 mov r1, r9 + 8002e52: 4638 mov r0, r7 + 8002e54: f104 0243 add.w r2, r4, #67 ; 0x43 + 8002e58: 47c0 blx r8 + 8002e5a: 3001 adds r0, #1 + 8002e5c: d020 beq.n 8002ea0 <_printf_common+0xa8> + 8002e5e: 6823 ldr r3, [r4, #0] + 8002e60: 68e5 ldr r5, [r4, #12] + 8002e62: f003 0306 and.w r3, r3, #6 + 8002e66: 2b04 cmp r3, #4 + 8002e68: bf18 it ne + 8002e6a: 2500 movne r5, #0 + 8002e6c: 6832 ldr r2, [r6, #0] + 8002e6e: f04f 0600 mov.w r6, #0 + 8002e72: 68a3 ldr r3, [r4, #8] + 8002e74: bf08 it eq + 8002e76: 1aad subeq r5, r5, r2 + 8002e78: 6922 ldr r2, [r4, #16] + 8002e7a: bf08 it eq + 8002e7c: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 8002e80: 4293 cmp r3, r2 + 8002e82: bfc4 itt gt + 8002e84: 1a9b subgt r3, r3, r2 + 8002e86: 18ed addgt r5, r5, r3 + 8002e88: 341a adds r4, #26 + 8002e8a: 42b5 cmp r5, r6 + 8002e8c: d11a bne.n 8002ec4 <_printf_common+0xcc> + 8002e8e: 2000 movs r0, #0 + 8002e90: e008 b.n 8002ea4 <_printf_common+0xac> + 8002e92: 2301 movs r3, #1 + 8002e94: 4652 mov r2, sl + 8002e96: 4649 mov r1, r9 + 8002e98: 4638 mov r0, r7 + 8002e9a: 47c0 blx r8 + 8002e9c: 3001 adds r0, #1 + 8002e9e: d103 bne.n 8002ea8 <_printf_common+0xb0> + 8002ea0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8002ea4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8002ea8: 3501 adds r5, #1 + 8002eaa: e7c4 b.n 8002e36 <_printf_common+0x3e> + 8002eac: 2030 movs r0, #48 ; 0x30 + 8002eae: 18e1 adds r1, r4, r3 + 8002eb0: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 8002eb4: 1c5a adds r2, r3, #1 + 8002eb6: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 8002eba: 4422 add r2, r4 + 8002ebc: 3302 adds r3, #2 + 8002ebe: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 8002ec2: e7c5 b.n 8002e50 <_printf_common+0x58> + 8002ec4: 2301 movs r3, #1 + 8002ec6: 4622 mov r2, r4 + 8002ec8: 4649 mov r1, r9 + 8002eca: 4638 mov r0, r7 + 8002ecc: 47c0 blx r8 + 8002ece: 3001 adds r0, #1 + 8002ed0: d0e6 beq.n 8002ea0 <_printf_common+0xa8> + 8002ed2: 3601 adds r6, #1 + 8002ed4: e7d9 b.n 8002e8a <_printf_common+0x92> + ... + +08002ed8 <_printf_i>: + 8002ed8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8002edc: 460c mov r4, r1 + 8002ede: 7e27 ldrb r7, [r4, #24] + 8002ee0: 4691 mov r9, r2 + 8002ee2: 2f78 cmp r7, #120 ; 0x78 + 8002ee4: 4680 mov r8, r0 + 8002ee6: 469a mov sl, r3 + 8002ee8: 990c ldr r1, [sp, #48] ; 0x30 + 8002eea: f104 0243 add.w r2, r4, #67 ; 0x43 + 8002eee: d807 bhi.n 8002f00 <_printf_i+0x28> + 8002ef0: 2f62 cmp r7, #98 ; 0x62 + 8002ef2: d80a bhi.n 8002f0a <_printf_i+0x32> + 8002ef4: 2f00 cmp r7, #0 + 8002ef6: f000 80d9 beq.w 80030ac <_printf_i+0x1d4> + 8002efa: 2f58 cmp r7, #88 ; 0x58 + 8002efc: f000 80a4 beq.w 8003048 <_printf_i+0x170> + 8002f00: f104 0642 add.w r6, r4, #66 ; 0x42 + 8002f04: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 8002f08: e03a b.n 8002f80 <_printf_i+0xa8> + 8002f0a: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 8002f0e: 2b15 cmp r3, #21 + 8002f10: d8f6 bhi.n 8002f00 <_printf_i+0x28> + 8002f12: a001 add r0, pc, #4 ; (adr r0, 8002f18 <_printf_i+0x40>) + 8002f14: f850 f023 ldr.w pc, [r0, r3, lsl #2] + 8002f18: 08002f71 .word 0x08002f71 + 8002f1c: 08002f85 .word 0x08002f85 + 8002f20: 08002f01 .word 0x08002f01 + 8002f24: 08002f01 .word 0x08002f01 + 8002f28: 08002f01 .word 0x08002f01 + 8002f2c: 08002f01 .word 0x08002f01 + 8002f30: 08002f85 .word 0x08002f85 + 8002f34: 08002f01 .word 0x08002f01 + 8002f38: 08002f01 .word 0x08002f01 + 8002f3c: 08002f01 .word 0x08002f01 + 8002f40: 08002f01 .word 0x08002f01 + 8002f44: 08003093 .word 0x08003093 + 8002f48: 08002fb5 .word 0x08002fb5 + 8002f4c: 08003075 .word 0x08003075 + 8002f50: 08002f01 .word 0x08002f01 + 8002f54: 08002f01 .word 0x08002f01 + 8002f58: 080030b5 .word 0x080030b5 + 8002f5c: 08002f01 .word 0x08002f01 + 8002f60: 08002fb5 .word 0x08002fb5 + 8002f64: 08002f01 .word 0x08002f01 + 8002f68: 08002f01 .word 0x08002f01 + 8002f6c: 0800307d .word 0x0800307d + 8002f70: 680b ldr r3, [r1, #0] + 8002f72: f104 0642 add.w r6, r4, #66 ; 0x42 + 8002f76: 1d1a adds r2, r3, #4 + 8002f78: 681b ldr r3, [r3, #0] + 8002f7a: 600a str r2, [r1, #0] + 8002f7c: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 8002f80: 2301 movs r3, #1 + 8002f82: e0a4 b.n 80030ce <_printf_i+0x1f6> + 8002f84: 6825 ldr r5, [r4, #0] + 8002f86: 6808 ldr r0, [r1, #0] + 8002f88: 062e lsls r6, r5, #24 + 8002f8a: f100 0304 add.w r3, r0, #4 + 8002f8e: d50a bpl.n 8002fa6 <_printf_i+0xce> + 8002f90: 6805 ldr r5, [r0, #0] + 8002f92: 600b str r3, [r1, #0] + 8002f94: 2d00 cmp r5, #0 + 8002f96: da03 bge.n 8002fa0 <_printf_i+0xc8> + 8002f98: 232d movs r3, #45 ; 0x2d + 8002f9a: 426d negs r5, r5 + 8002f9c: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8002fa0: 230a movs r3, #10 + 8002fa2: 485e ldr r0, [pc, #376] ; (800311c <_printf_i+0x244>) + 8002fa4: e019 b.n 8002fda <_printf_i+0x102> + 8002fa6: f015 0f40 tst.w r5, #64 ; 0x40 + 8002faa: 6805 ldr r5, [r0, #0] + 8002fac: 600b str r3, [r1, #0] + 8002fae: bf18 it ne + 8002fb0: b22d sxthne r5, r5 + 8002fb2: e7ef b.n 8002f94 <_printf_i+0xbc> + 8002fb4: 680b ldr r3, [r1, #0] + 8002fb6: 6825 ldr r5, [r4, #0] + 8002fb8: 1d18 adds r0, r3, #4 + 8002fba: 6008 str r0, [r1, #0] + 8002fbc: 0628 lsls r0, r5, #24 + 8002fbe: d501 bpl.n 8002fc4 <_printf_i+0xec> + 8002fc0: 681d ldr r5, [r3, #0] + 8002fc2: e002 b.n 8002fca <_printf_i+0xf2> + 8002fc4: 0669 lsls r1, r5, #25 + 8002fc6: d5fb bpl.n 8002fc0 <_printf_i+0xe8> + 8002fc8: 881d ldrh r5, [r3, #0] + 8002fca: 2f6f cmp r7, #111 ; 0x6f + 8002fcc: bf0c ite eq + 8002fce: 2308 moveq r3, #8 + 8002fd0: 230a movne r3, #10 + 8002fd2: 4852 ldr r0, [pc, #328] ; (800311c <_printf_i+0x244>) + 8002fd4: 2100 movs r1, #0 + 8002fd6: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 8002fda: 6866 ldr r6, [r4, #4] + 8002fdc: 2e00 cmp r6, #0 + 8002fde: bfa8 it ge + 8002fe0: 6821 ldrge r1, [r4, #0] + 8002fe2: 60a6 str r6, [r4, #8] + 8002fe4: bfa4 itt ge + 8002fe6: f021 0104 bicge.w r1, r1, #4 + 8002fea: 6021 strge r1, [r4, #0] + 8002fec: b90d cbnz r5, 8002ff2 <_printf_i+0x11a> + 8002fee: 2e00 cmp r6, #0 + 8002ff0: d04d beq.n 800308e <_printf_i+0x1b6> + 8002ff2: 4616 mov r6, r2 + 8002ff4: fbb5 f1f3 udiv r1, r5, r3 + 8002ff8: fb03 5711 mls r7, r3, r1, r5 + 8002ffc: 5dc7 ldrb r7, [r0, r7] + 8002ffe: f806 7d01 strb.w r7, [r6, #-1]! + 8003002: 462f mov r7, r5 + 8003004: 42bb cmp r3, r7 + 8003006: 460d mov r5, r1 + 8003008: d9f4 bls.n 8002ff4 <_printf_i+0x11c> + 800300a: 2b08 cmp r3, #8 + 800300c: d10b bne.n 8003026 <_printf_i+0x14e> + 800300e: 6823 ldr r3, [r4, #0] + 8003010: 07df lsls r7, r3, #31 + 8003012: d508 bpl.n 8003026 <_printf_i+0x14e> + 8003014: 6923 ldr r3, [r4, #16] + 8003016: 6861 ldr r1, [r4, #4] + 8003018: 4299 cmp r1, r3 + 800301a: bfde ittt le + 800301c: 2330 movle r3, #48 ; 0x30 + 800301e: f806 3c01 strble.w r3, [r6, #-1] + 8003022: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff + 8003026: 1b92 subs r2, r2, r6 + 8003028: 6122 str r2, [r4, #16] + 800302a: 464b mov r3, r9 + 800302c: 4621 mov r1, r4 + 800302e: 4640 mov r0, r8 + 8003030: f8cd a000 str.w sl, [sp] + 8003034: aa03 add r2, sp, #12 + 8003036: f7ff fedf bl 8002df8 <_printf_common> + 800303a: 3001 adds r0, #1 + 800303c: d14c bne.n 80030d8 <_printf_i+0x200> + 800303e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8003042: b004 add sp, #16 + 8003044: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8003048: 4834 ldr r0, [pc, #208] ; (800311c <_printf_i+0x244>) + 800304a: f884 7045 strb.w r7, [r4, #69] ; 0x45 + 800304e: 680e ldr r6, [r1, #0] + 8003050: 6823 ldr r3, [r4, #0] + 8003052: f856 5b04 ldr.w r5, [r6], #4 + 8003056: 061f lsls r7, r3, #24 + 8003058: 600e str r6, [r1, #0] + 800305a: d514 bpl.n 8003086 <_printf_i+0x1ae> + 800305c: 07d9 lsls r1, r3, #31 + 800305e: bf44 itt mi + 8003060: f043 0320 orrmi.w r3, r3, #32 + 8003064: 6023 strmi r3, [r4, #0] + 8003066: b91d cbnz r5, 8003070 <_printf_i+0x198> + 8003068: 6823 ldr r3, [r4, #0] + 800306a: f023 0320 bic.w r3, r3, #32 + 800306e: 6023 str r3, [r4, #0] + 8003070: 2310 movs r3, #16 + 8003072: e7af b.n 8002fd4 <_printf_i+0xfc> + 8003074: 6823 ldr r3, [r4, #0] + 8003076: f043 0320 orr.w r3, r3, #32 + 800307a: 6023 str r3, [r4, #0] + 800307c: 2378 movs r3, #120 ; 0x78 + 800307e: 4828 ldr r0, [pc, #160] ; (8003120 <_printf_i+0x248>) + 8003080: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 8003084: e7e3 b.n 800304e <_printf_i+0x176> + 8003086: 065e lsls r6, r3, #25 + 8003088: bf48 it mi + 800308a: b2ad uxthmi r5, r5 + 800308c: e7e6 b.n 800305c <_printf_i+0x184> + 800308e: 4616 mov r6, r2 + 8003090: e7bb b.n 800300a <_printf_i+0x132> + 8003092: 680b ldr r3, [r1, #0] + 8003094: 6826 ldr r6, [r4, #0] + 8003096: 1d1d adds r5, r3, #4 + 8003098: 6960 ldr r0, [r4, #20] + 800309a: 600d str r5, [r1, #0] + 800309c: 0635 lsls r5, r6, #24 + 800309e: 681b ldr r3, [r3, #0] + 80030a0: d501 bpl.n 80030a6 <_printf_i+0x1ce> + 80030a2: 6018 str r0, [r3, #0] + 80030a4: e002 b.n 80030ac <_printf_i+0x1d4> + 80030a6: 0671 lsls r1, r6, #25 + 80030a8: d5fb bpl.n 80030a2 <_printf_i+0x1ca> + 80030aa: 8018 strh r0, [r3, #0] + 80030ac: 2300 movs r3, #0 + 80030ae: 4616 mov r6, r2 + 80030b0: 6123 str r3, [r4, #16] + 80030b2: e7ba b.n 800302a <_printf_i+0x152> + 80030b4: 680b ldr r3, [r1, #0] + 80030b6: 1d1a adds r2, r3, #4 + 80030b8: 600a str r2, [r1, #0] + 80030ba: 681e ldr r6, [r3, #0] + 80030bc: 2100 movs r1, #0 + 80030be: 4630 mov r0, r6 + 80030c0: 6862 ldr r2, [r4, #4] + 80030c2: f000 feb7 bl 8003e34 + 80030c6: b108 cbz r0, 80030cc <_printf_i+0x1f4> + 80030c8: 1b80 subs r0, r0, r6 + 80030ca: 6060 str r0, [r4, #4] + 80030cc: 6863 ldr r3, [r4, #4] + 80030ce: 6123 str r3, [r4, #16] + 80030d0: 2300 movs r3, #0 + 80030d2: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80030d6: e7a8 b.n 800302a <_printf_i+0x152> + 80030d8: 4632 mov r2, r6 + 80030da: 4649 mov r1, r9 + 80030dc: 4640 mov r0, r8 + 80030de: 6923 ldr r3, [r4, #16] + 80030e0: 47d0 blx sl + 80030e2: 3001 adds r0, #1 + 80030e4: d0ab beq.n 800303e <_printf_i+0x166> + 80030e6: 6823 ldr r3, [r4, #0] + 80030e8: 079b lsls r3, r3, #30 + 80030ea: d413 bmi.n 8003114 <_printf_i+0x23c> + 80030ec: 68e0 ldr r0, [r4, #12] + 80030ee: 9b03 ldr r3, [sp, #12] + 80030f0: 4298 cmp r0, r3 + 80030f2: bfb8 it lt + 80030f4: 4618 movlt r0, r3 + 80030f6: e7a4 b.n 8003042 <_printf_i+0x16a> + 80030f8: 2301 movs r3, #1 + 80030fa: 4632 mov r2, r6 + 80030fc: 4649 mov r1, r9 + 80030fe: 4640 mov r0, r8 + 8003100: 47d0 blx sl + 8003102: 3001 adds r0, #1 + 8003104: d09b beq.n 800303e <_printf_i+0x166> + 8003106: 3501 adds r5, #1 + 8003108: 68e3 ldr r3, [r4, #12] + 800310a: 9903 ldr r1, [sp, #12] + 800310c: 1a5b subs r3, r3, r1 + 800310e: 42ab cmp r3, r5 + 8003110: dcf2 bgt.n 80030f8 <_printf_i+0x220> + 8003112: e7eb b.n 80030ec <_printf_i+0x214> + 8003114: 2500 movs r5, #0 + 8003116: f104 0619 add.w r6, r4, #25 + 800311a: e7f5 b.n 8003108 <_printf_i+0x230> + 800311c: 0800525e .word 0x0800525e + 8003120: 0800526f .word 0x0800526f + +08003124 : + 8003124: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8003128: 6903 ldr r3, [r0, #16] + 800312a: 690c ldr r4, [r1, #16] + 800312c: 4607 mov r7, r0 + 800312e: 42a3 cmp r3, r4 + 8003130: f2c0 8083 blt.w 800323a + 8003134: 3c01 subs r4, #1 + 8003136: f100 0514 add.w r5, r0, #20 + 800313a: f101 0814 add.w r8, r1, #20 + 800313e: eb05 0384 add.w r3, r5, r4, lsl #2 + 8003142: 9301 str r3, [sp, #4] + 8003144: f858 3024 ldr.w r3, [r8, r4, lsl #2] + 8003148: f855 2024 ldr.w r2, [r5, r4, lsl #2] + 800314c: 3301 adds r3, #1 + 800314e: 429a cmp r2, r3 + 8003150: fbb2 f6f3 udiv r6, r2, r3 + 8003154: ea4f 0b84 mov.w fp, r4, lsl #2 + 8003158: eb08 0984 add.w r9, r8, r4, lsl #2 + 800315c: d332 bcc.n 80031c4 + 800315e: f04f 0e00 mov.w lr, #0 + 8003162: 4640 mov r0, r8 + 8003164: 46ac mov ip, r5 + 8003166: 46f2 mov sl, lr + 8003168: f850 2b04 ldr.w r2, [r0], #4 + 800316c: b293 uxth r3, r2 + 800316e: fb06 e303 mla r3, r6, r3, lr + 8003172: 0c12 lsrs r2, r2, #16 + 8003174: ea4f 4e13 mov.w lr, r3, lsr #16 + 8003178: fb06 e202 mla r2, r6, r2, lr + 800317c: b29b uxth r3, r3 + 800317e: ebaa 0303 sub.w r3, sl, r3 + 8003182: f8dc a000 ldr.w sl, [ip] + 8003186: ea4f 4e12 mov.w lr, r2, lsr #16 + 800318a: fa1f fa8a uxth.w sl, sl + 800318e: 4453 add r3, sl + 8003190: fa1f fa82 uxth.w sl, r2 + 8003194: f8dc 2000 ldr.w r2, [ip] + 8003198: 4581 cmp r9, r0 + 800319a: ebca 4212 rsb r2, sl, r2, lsr #16 + 800319e: eb02 4223 add.w r2, r2, r3, asr #16 + 80031a2: b29b uxth r3, r3 + 80031a4: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80031a8: ea4f 4a22 mov.w sl, r2, asr #16 + 80031ac: f84c 3b04 str.w r3, [ip], #4 + 80031b0: d2da bcs.n 8003168 + 80031b2: f855 300b ldr.w r3, [r5, fp] + 80031b6: b92b cbnz r3, 80031c4 + 80031b8: 9b01 ldr r3, [sp, #4] + 80031ba: 3b04 subs r3, #4 + 80031bc: 429d cmp r5, r3 + 80031be: 461a mov r2, r3 + 80031c0: d32f bcc.n 8003222 + 80031c2: 613c str r4, [r7, #16] + 80031c4: 4638 mov r0, r7 + 80031c6: f001 f8cb bl 8004360 <__mcmp> + 80031ca: 2800 cmp r0, #0 + 80031cc: db25 blt.n 800321a + 80031ce: 4628 mov r0, r5 + 80031d0: f04f 0c00 mov.w ip, #0 + 80031d4: 3601 adds r6, #1 + 80031d6: f858 1b04 ldr.w r1, [r8], #4 + 80031da: f8d0 e000 ldr.w lr, [r0] + 80031de: b28b uxth r3, r1 + 80031e0: ebac 0303 sub.w r3, ip, r3 + 80031e4: fa1f f28e uxth.w r2, lr + 80031e8: 4413 add r3, r2 + 80031ea: 0c0a lsrs r2, r1, #16 + 80031ec: ebc2 421e rsb r2, r2, lr, lsr #16 + 80031f0: eb02 4223 add.w r2, r2, r3, asr #16 + 80031f4: b29b uxth r3, r3 + 80031f6: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80031fa: 45c1 cmp r9, r8 + 80031fc: ea4f 4c22 mov.w ip, r2, asr #16 + 8003200: f840 3b04 str.w r3, [r0], #4 + 8003204: d2e7 bcs.n 80031d6 + 8003206: f855 2024 ldr.w r2, [r5, r4, lsl #2] + 800320a: eb05 0384 add.w r3, r5, r4, lsl #2 + 800320e: b922 cbnz r2, 800321a + 8003210: 3b04 subs r3, #4 + 8003212: 429d cmp r5, r3 + 8003214: 461a mov r2, r3 + 8003216: d30a bcc.n 800322e + 8003218: 613c str r4, [r7, #16] + 800321a: 4630 mov r0, r6 + 800321c: b003 add sp, #12 + 800321e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8003222: 6812 ldr r2, [r2, #0] + 8003224: 3b04 subs r3, #4 + 8003226: 2a00 cmp r2, #0 + 8003228: d1cb bne.n 80031c2 + 800322a: 3c01 subs r4, #1 + 800322c: e7c6 b.n 80031bc + 800322e: 6812 ldr r2, [r2, #0] + 8003230: 3b04 subs r3, #4 + 8003232: 2a00 cmp r2, #0 + 8003234: d1f0 bne.n 8003218 + 8003236: 3c01 subs r4, #1 + 8003238: e7eb b.n 8003212 + 800323a: 2000 movs r0, #0 + 800323c: e7ee b.n 800321c + ... + +08003240 <_dtoa_r>: + 8003240: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8003244: 4616 mov r6, r2 + 8003246: 461f mov r7, r3 + 8003248: 6a44 ldr r4, [r0, #36] ; 0x24 + 800324a: b099 sub sp, #100 ; 0x64 + 800324c: 4605 mov r5, r0 + 800324e: e9cd 6704 strd r6, r7, [sp, #16] + 8003252: f8dd 8094 ldr.w r8, [sp, #148] ; 0x94 + 8003256: b974 cbnz r4, 8003276 <_dtoa_r+0x36> + 8003258: 2010 movs r0, #16 + 800325a: f000 fde3 bl 8003e24 + 800325e: 4602 mov r2, r0 + 8003260: 6268 str r0, [r5, #36] ; 0x24 + 8003262: b920 cbnz r0, 800326e <_dtoa_r+0x2e> + 8003264: 21ea movs r1, #234 ; 0xea + 8003266: 4bae ldr r3, [pc, #696] ; (8003520 <_dtoa_r+0x2e0>) + 8003268: 48ae ldr r0, [pc, #696] ; (8003524 <_dtoa_r+0x2e4>) + 800326a: f001 fa45 bl 80046f8 <__assert_func> + 800326e: e9c0 4401 strd r4, r4, [r0, #4] + 8003272: 6004 str r4, [r0, #0] + 8003274: 60c4 str r4, [r0, #12] + 8003276: 6a6b ldr r3, [r5, #36] ; 0x24 + 8003278: 6819 ldr r1, [r3, #0] + 800327a: b151 cbz r1, 8003292 <_dtoa_r+0x52> + 800327c: 685a ldr r2, [r3, #4] + 800327e: 2301 movs r3, #1 + 8003280: 4093 lsls r3, r2 + 8003282: 604a str r2, [r1, #4] + 8003284: 608b str r3, [r1, #8] + 8003286: 4628 mov r0, r5 + 8003288: f000 fe30 bl 8003eec <_Bfree> + 800328c: 2200 movs r2, #0 + 800328e: 6a6b ldr r3, [r5, #36] ; 0x24 + 8003290: 601a str r2, [r3, #0] + 8003292: 1e3b subs r3, r7, #0 + 8003294: bfaf iteee ge + 8003296: 2300 movge r3, #0 + 8003298: 2201 movlt r2, #1 + 800329a: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 + 800329e: 9305 strlt r3, [sp, #20] + 80032a0: bfa8 it ge + 80032a2: f8c8 3000 strge.w r3, [r8] + 80032a6: f8dd 9014 ldr.w r9, [sp, #20] + 80032aa: 4b9f ldr r3, [pc, #636] ; (8003528 <_dtoa_r+0x2e8>) + 80032ac: bfb8 it lt + 80032ae: f8c8 2000 strlt.w r2, [r8] + 80032b2: ea33 0309 bics.w r3, r3, r9 + 80032b6: d119 bne.n 80032ec <_dtoa_r+0xac> + 80032b8: f242 730f movw r3, #9999 ; 0x270f + 80032bc: 9a24 ldr r2, [sp, #144] ; 0x90 + 80032be: 6013 str r3, [r2, #0] + 80032c0: f3c9 0313 ubfx r3, r9, #0, #20 + 80032c4: 4333 orrs r3, r6 + 80032c6: f000 8580 beq.w 8003dca <_dtoa_r+0xb8a> + 80032ca: 9b26 ldr r3, [sp, #152] ; 0x98 + 80032cc: b953 cbnz r3, 80032e4 <_dtoa_r+0xa4> + 80032ce: 4b97 ldr r3, [pc, #604] ; (800352c <_dtoa_r+0x2ec>) + 80032d0: e022 b.n 8003318 <_dtoa_r+0xd8> + 80032d2: 4b97 ldr r3, [pc, #604] ; (8003530 <_dtoa_r+0x2f0>) + 80032d4: 9308 str r3, [sp, #32] + 80032d6: 3308 adds r3, #8 + 80032d8: 9a26 ldr r2, [sp, #152] ; 0x98 + 80032da: 6013 str r3, [r2, #0] + 80032dc: 9808 ldr r0, [sp, #32] + 80032de: b019 add sp, #100 ; 0x64 + 80032e0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80032e4: 4b91 ldr r3, [pc, #580] ; (800352c <_dtoa_r+0x2ec>) + 80032e6: 9308 str r3, [sp, #32] + 80032e8: 3303 adds r3, #3 + 80032ea: e7f5 b.n 80032d8 <_dtoa_r+0x98> + 80032ec: e9dd 3404 ldrd r3, r4, [sp, #16] + 80032f0: e9cd 340c strd r3, r4, [sp, #48] ; 0x30 + 80032f4: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 80032f8: 2200 movs r2, #0 + 80032fa: 2300 movs r3, #0 + 80032fc: f7fd fbc0 bl 8000a80 <__aeabi_dcmpeq> + 8003300: 4680 mov r8, r0 + 8003302: b158 cbz r0, 800331c <_dtoa_r+0xdc> + 8003304: 2301 movs r3, #1 + 8003306: 9a24 ldr r2, [sp, #144] ; 0x90 + 8003308: 6013 str r3, [r2, #0] + 800330a: 9b26 ldr r3, [sp, #152] ; 0x98 + 800330c: 2b00 cmp r3, #0 + 800330e: f000 8559 beq.w 8003dc4 <_dtoa_r+0xb84> + 8003312: 4888 ldr r0, [pc, #544] ; (8003534 <_dtoa_r+0x2f4>) + 8003314: 6018 str r0, [r3, #0] + 8003316: 1e43 subs r3, r0, #1 + 8003318: 9308 str r3, [sp, #32] + 800331a: e7df b.n 80032dc <_dtoa_r+0x9c> + 800331c: ab16 add r3, sp, #88 ; 0x58 + 800331e: 9301 str r3, [sp, #4] + 8003320: ab17 add r3, sp, #92 ; 0x5c + 8003322: 9300 str r3, [sp, #0] + 8003324: 4628 mov r0, r5 + 8003326: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 + 800332a: f001 f8c5 bl 80044b8 <__d2b> + 800332e: f3c9 540a ubfx r4, r9, #20, #11 + 8003332: 4682 mov sl, r0 + 8003334: 2c00 cmp r4, #0 + 8003336: d07e beq.n 8003436 <_dtoa_r+0x1f6> + 8003338: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 800333c: 9b0d ldr r3, [sp, #52] ; 0x34 + 800333e: f2a4 34ff subw r4, r4, #1023 ; 0x3ff + 8003342: f3c3 0313 ubfx r3, r3, #0, #20 + 8003346: f043 517f orr.w r1, r3, #1069547520 ; 0x3fc00000 + 800334a: f441 1140 orr.w r1, r1, #3145728 ; 0x300000 + 800334e: f8cd 804c str.w r8, [sp, #76] ; 0x4c + 8003352: 2200 movs r2, #0 + 8003354: 4b78 ldr r3, [pc, #480] ; (8003538 <_dtoa_r+0x2f8>) + 8003356: f7fc ff73 bl 8000240 <__aeabi_dsub> + 800335a: a36b add r3, pc, #428 ; (adr r3, 8003508 <_dtoa_r+0x2c8>) + 800335c: e9d3 2300 ldrd r2, r3, [r3] + 8003360: f7fd f926 bl 80005b0 <__aeabi_dmul> + 8003364: a36a add r3, pc, #424 ; (adr r3, 8003510 <_dtoa_r+0x2d0>) + 8003366: e9d3 2300 ldrd r2, r3, [r3] + 800336a: f7fc ff6b bl 8000244 <__adddf3> + 800336e: 4606 mov r6, r0 + 8003370: 4620 mov r0, r4 + 8003372: 460f mov r7, r1 + 8003374: f7fd f8b2 bl 80004dc <__aeabi_i2d> + 8003378: a367 add r3, pc, #412 ; (adr r3, 8003518 <_dtoa_r+0x2d8>) + 800337a: e9d3 2300 ldrd r2, r3, [r3] + 800337e: f7fd f917 bl 80005b0 <__aeabi_dmul> + 8003382: 4602 mov r2, r0 + 8003384: 460b mov r3, r1 + 8003386: 4630 mov r0, r6 + 8003388: 4639 mov r1, r7 + 800338a: f7fc ff5b bl 8000244 <__adddf3> + 800338e: 4606 mov r6, r0 + 8003390: 460f mov r7, r1 + 8003392: f7fd fbbd bl 8000b10 <__aeabi_d2iz> + 8003396: 2200 movs r2, #0 + 8003398: 4681 mov r9, r0 + 800339a: 2300 movs r3, #0 + 800339c: 4630 mov r0, r6 + 800339e: 4639 mov r1, r7 + 80033a0: f7fd fb78 bl 8000a94 <__aeabi_dcmplt> + 80033a4: b148 cbz r0, 80033ba <_dtoa_r+0x17a> + 80033a6: 4648 mov r0, r9 + 80033a8: f7fd f898 bl 80004dc <__aeabi_i2d> + 80033ac: 4632 mov r2, r6 + 80033ae: 463b mov r3, r7 + 80033b0: f7fd fb66 bl 8000a80 <__aeabi_dcmpeq> + 80033b4: b908 cbnz r0, 80033ba <_dtoa_r+0x17a> + 80033b6: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff + 80033ba: f1b9 0f16 cmp.w r9, #22 + 80033be: d857 bhi.n 8003470 <_dtoa_r+0x230> + 80033c0: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 80033c4: 4b5d ldr r3, [pc, #372] ; (800353c <_dtoa_r+0x2fc>) + 80033c6: eb03 03c9 add.w r3, r3, r9, lsl #3 + 80033ca: e9d3 2300 ldrd r2, r3, [r3] + 80033ce: f7fd fb61 bl 8000a94 <__aeabi_dcmplt> + 80033d2: 2800 cmp r0, #0 + 80033d4: d04e beq.n 8003474 <_dtoa_r+0x234> + 80033d6: 2300 movs r3, #0 + 80033d8: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff + 80033dc: 930f str r3, [sp, #60] ; 0x3c + 80033de: 9b16 ldr r3, [sp, #88] ; 0x58 + 80033e0: 1b1c subs r4, r3, r4 + 80033e2: 1e63 subs r3, r4, #1 + 80033e4: 9309 str r3, [sp, #36] ; 0x24 + 80033e6: bf49 itett mi + 80033e8: f1c4 0301 rsbmi r3, r4, #1 + 80033ec: 2300 movpl r3, #0 + 80033ee: 9306 strmi r3, [sp, #24] + 80033f0: 2300 movmi r3, #0 + 80033f2: bf54 ite pl + 80033f4: 9306 strpl r3, [sp, #24] + 80033f6: 9309 strmi r3, [sp, #36] ; 0x24 + 80033f8: f1b9 0f00 cmp.w r9, #0 + 80033fc: db3c blt.n 8003478 <_dtoa_r+0x238> + 80033fe: 9b09 ldr r3, [sp, #36] ; 0x24 + 8003400: f8cd 9038 str.w r9, [sp, #56] ; 0x38 + 8003404: 444b add r3, r9 + 8003406: 9309 str r3, [sp, #36] ; 0x24 + 8003408: 2300 movs r3, #0 + 800340a: 930a str r3, [sp, #40] ; 0x28 + 800340c: 9b22 ldr r3, [sp, #136] ; 0x88 + 800340e: 2b09 cmp r3, #9 + 8003410: d86c bhi.n 80034ec <_dtoa_r+0x2ac> + 8003412: 2b05 cmp r3, #5 + 8003414: bfc4 itt gt + 8003416: 3b04 subgt r3, #4 + 8003418: 9322 strgt r3, [sp, #136] ; 0x88 + 800341a: 9b22 ldr r3, [sp, #136] ; 0x88 + 800341c: bfc8 it gt + 800341e: 2400 movgt r4, #0 + 8003420: f1a3 0302 sub.w r3, r3, #2 + 8003424: bfd8 it le + 8003426: 2401 movle r4, #1 + 8003428: 2b03 cmp r3, #3 + 800342a: f200 808b bhi.w 8003544 <_dtoa_r+0x304> + 800342e: e8df f003 tbb [pc, r3] + 8003432: 4f2d .short 0x4f2d + 8003434: 5b4d .short 0x5b4d + 8003436: e9dd 4316 ldrd r4, r3, [sp, #88] ; 0x58 + 800343a: 441c add r4, r3 + 800343c: f204 4332 addw r3, r4, #1074 ; 0x432 + 8003440: 2b20 cmp r3, #32 + 8003442: bfc3 ittte gt + 8003444: f1c3 0340 rsbgt r3, r3, #64 ; 0x40 + 8003448: f204 4012 addwgt r0, r4, #1042 ; 0x412 + 800344c: fa09 f303 lslgt.w r3, r9, r3 + 8003450: f1c3 0320 rsble r3, r3, #32 + 8003454: bfc6 itte gt + 8003456: fa26 f000 lsrgt.w r0, r6, r0 + 800345a: 4318 orrgt r0, r3 + 800345c: fa06 f003 lslle.w r0, r6, r3 + 8003460: f7fd f82c bl 80004bc <__aeabi_ui2d> + 8003464: 2301 movs r3, #1 + 8003466: f1a1 71f8 sub.w r1, r1, #32505856 ; 0x1f00000 + 800346a: 3c01 subs r4, #1 + 800346c: 9313 str r3, [sp, #76] ; 0x4c + 800346e: e770 b.n 8003352 <_dtoa_r+0x112> + 8003470: 2301 movs r3, #1 + 8003472: e7b3 b.n 80033dc <_dtoa_r+0x19c> + 8003474: 900f str r0, [sp, #60] ; 0x3c + 8003476: e7b2 b.n 80033de <_dtoa_r+0x19e> + 8003478: 9b06 ldr r3, [sp, #24] + 800347a: eba3 0309 sub.w r3, r3, r9 + 800347e: 9306 str r3, [sp, #24] + 8003480: f1c9 0300 rsb r3, r9, #0 + 8003484: 930a str r3, [sp, #40] ; 0x28 + 8003486: 2300 movs r3, #0 + 8003488: 930e str r3, [sp, #56] ; 0x38 + 800348a: e7bf b.n 800340c <_dtoa_r+0x1cc> + 800348c: 2300 movs r3, #0 + 800348e: 930b str r3, [sp, #44] ; 0x2c + 8003490: 9b23 ldr r3, [sp, #140] ; 0x8c + 8003492: 2b00 cmp r3, #0 + 8003494: dc59 bgt.n 800354a <_dtoa_r+0x30a> + 8003496: f04f 0b01 mov.w fp, #1 + 800349a: 465b mov r3, fp + 800349c: f8cd b008 str.w fp, [sp, #8] + 80034a0: f8cd b08c str.w fp, [sp, #140] ; 0x8c + 80034a4: 2200 movs r2, #0 + 80034a6: 6a68 ldr r0, [r5, #36] ; 0x24 + 80034a8: 6042 str r2, [r0, #4] + 80034aa: 2204 movs r2, #4 + 80034ac: f102 0614 add.w r6, r2, #20 + 80034b0: 429e cmp r6, r3 + 80034b2: 6841 ldr r1, [r0, #4] + 80034b4: d94f bls.n 8003556 <_dtoa_r+0x316> + 80034b6: 4628 mov r0, r5 + 80034b8: f000 fcd8 bl 8003e6c <_Balloc> + 80034bc: 9008 str r0, [sp, #32] + 80034be: 2800 cmp r0, #0 + 80034c0: d14d bne.n 800355e <_dtoa_r+0x31e> + 80034c2: 4602 mov r2, r0 + 80034c4: f44f 71d5 mov.w r1, #426 ; 0x1aa + 80034c8: 4b1d ldr r3, [pc, #116] ; (8003540 <_dtoa_r+0x300>) + 80034ca: e6cd b.n 8003268 <_dtoa_r+0x28> + 80034cc: 2301 movs r3, #1 + 80034ce: e7de b.n 800348e <_dtoa_r+0x24e> + 80034d0: 2300 movs r3, #0 + 80034d2: 930b str r3, [sp, #44] ; 0x2c + 80034d4: 9b23 ldr r3, [sp, #140] ; 0x8c + 80034d6: eb09 0b03 add.w fp, r9, r3 + 80034da: f10b 0301 add.w r3, fp, #1 + 80034de: 2b01 cmp r3, #1 + 80034e0: 9302 str r3, [sp, #8] + 80034e2: bfb8 it lt + 80034e4: 2301 movlt r3, #1 + 80034e6: e7dd b.n 80034a4 <_dtoa_r+0x264> + 80034e8: 2301 movs r3, #1 + 80034ea: e7f2 b.n 80034d2 <_dtoa_r+0x292> + 80034ec: 2401 movs r4, #1 + 80034ee: 2300 movs r3, #0 + 80034f0: 940b str r4, [sp, #44] ; 0x2c + 80034f2: 9322 str r3, [sp, #136] ; 0x88 + 80034f4: f04f 3bff mov.w fp, #4294967295 ; 0xffffffff + 80034f8: 2200 movs r2, #0 + 80034fa: 2312 movs r3, #18 + 80034fc: f8cd b008 str.w fp, [sp, #8] + 8003500: 9223 str r2, [sp, #140] ; 0x8c + 8003502: e7cf b.n 80034a4 <_dtoa_r+0x264> + 8003504: f3af 8000 nop.w + 8003508: 636f4361 .word 0x636f4361 + 800350c: 3fd287a7 .word 0x3fd287a7 + 8003510: 8b60c8b3 .word 0x8b60c8b3 + 8003514: 3fc68a28 .word 0x3fc68a28 + 8003518: 509f79fb .word 0x509f79fb + 800351c: 3fd34413 .word 0x3fd34413 + 8003520: 0800528d .word 0x0800528d + 8003524: 080052a4 .word 0x080052a4 + 8003528: 7ff00000 .word 0x7ff00000 + 800352c: 08005289 .word 0x08005289 + 8003530: 08005280 .word 0x08005280 + 8003534: 0800525d .word 0x0800525d + 8003538: 3ff80000 .word 0x3ff80000 + 800353c: 080053a0 .word 0x080053a0 + 8003540: 08005303 .word 0x08005303 + 8003544: 2301 movs r3, #1 + 8003546: 930b str r3, [sp, #44] ; 0x2c + 8003548: e7d4 b.n 80034f4 <_dtoa_r+0x2b4> + 800354a: f8dd b08c ldr.w fp, [sp, #140] ; 0x8c + 800354e: 465b mov r3, fp + 8003550: f8cd b008 str.w fp, [sp, #8] + 8003554: e7a6 b.n 80034a4 <_dtoa_r+0x264> + 8003556: 3101 adds r1, #1 + 8003558: 6041 str r1, [r0, #4] + 800355a: 0052 lsls r2, r2, #1 + 800355c: e7a6 b.n 80034ac <_dtoa_r+0x26c> + 800355e: 6a6b ldr r3, [r5, #36] ; 0x24 + 8003560: 9a08 ldr r2, [sp, #32] + 8003562: 601a str r2, [r3, #0] + 8003564: 9b02 ldr r3, [sp, #8] + 8003566: 2b0e cmp r3, #14 + 8003568: f200 80a8 bhi.w 80036bc <_dtoa_r+0x47c> + 800356c: 2c00 cmp r4, #0 + 800356e: f000 80a5 beq.w 80036bc <_dtoa_r+0x47c> + 8003572: f1b9 0f00 cmp.w r9, #0 + 8003576: dd34 ble.n 80035e2 <_dtoa_r+0x3a2> + 8003578: 4a9a ldr r2, [pc, #616] ; (80037e4 <_dtoa_r+0x5a4>) + 800357a: f009 030f and.w r3, r9, #15 + 800357e: eb02 03c3 add.w r3, r2, r3, lsl #3 + 8003582: f419 7f80 tst.w r9, #256 ; 0x100 + 8003586: e9d3 3400 ldrd r3, r4, [r3] + 800358a: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 + 800358e: ea4f 1429 mov.w r4, r9, asr #4 + 8003592: d016 beq.n 80035c2 <_dtoa_r+0x382> + 8003594: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 8003598: 4b93 ldr r3, [pc, #588] ; (80037e8 <_dtoa_r+0x5a8>) + 800359a: 2703 movs r7, #3 + 800359c: e9d3 2308 ldrd r2, r3, [r3, #32] + 80035a0: f7fd f930 bl 8000804 <__aeabi_ddiv> + 80035a4: e9cd 0104 strd r0, r1, [sp, #16] + 80035a8: f004 040f and.w r4, r4, #15 + 80035ac: 4e8e ldr r6, [pc, #568] ; (80037e8 <_dtoa_r+0x5a8>) + 80035ae: b954 cbnz r4, 80035c6 <_dtoa_r+0x386> + 80035b0: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 80035b4: e9dd 0104 ldrd r0, r1, [sp, #16] + 80035b8: f7fd f924 bl 8000804 <__aeabi_ddiv> + 80035bc: e9cd 0104 strd r0, r1, [sp, #16] + 80035c0: e029 b.n 8003616 <_dtoa_r+0x3d6> + 80035c2: 2702 movs r7, #2 + 80035c4: e7f2 b.n 80035ac <_dtoa_r+0x36c> + 80035c6: 07e1 lsls r1, r4, #31 + 80035c8: d508 bpl.n 80035dc <_dtoa_r+0x39c> + 80035ca: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 80035ce: e9d6 2300 ldrd r2, r3, [r6] + 80035d2: f7fc ffed bl 80005b0 <__aeabi_dmul> + 80035d6: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 + 80035da: 3701 adds r7, #1 + 80035dc: 1064 asrs r4, r4, #1 + 80035de: 3608 adds r6, #8 + 80035e0: e7e5 b.n 80035ae <_dtoa_r+0x36e> + 80035e2: f000 80a5 beq.w 8003730 <_dtoa_r+0x4f0> + 80035e6: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 + 80035ea: f1c9 0400 rsb r4, r9, #0 + 80035ee: 4b7d ldr r3, [pc, #500] ; (80037e4 <_dtoa_r+0x5a4>) + 80035f0: f004 020f and.w r2, r4, #15 + 80035f4: eb03 03c2 add.w r3, r3, r2, lsl #3 + 80035f8: e9d3 2300 ldrd r2, r3, [r3] + 80035fc: f7fc ffd8 bl 80005b0 <__aeabi_dmul> + 8003600: 2702 movs r7, #2 + 8003602: 2300 movs r3, #0 + 8003604: e9cd 0104 strd r0, r1, [sp, #16] + 8003608: 4e77 ldr r6, [pc, #476] ; (80037e8 <_dtoa_r+0x5a8>) + 800360a: 1124 asrs r4, r4, #4 + 800360c: 2c00 cmp r4, #0 + 800360e: f040 8084 bne.w 800371a <_dtoa_r+0x4da> + 8003612: 2b00 cmp r3, #0 + 8003614: d1d2 bne.n 80035bc <_dtoa_r+0x37c> + 8003616: 9b0f ldr r3, [sp, #60] ; 0x3c + 8003618: 2b00 cmp r3, #0 + 800361a: f000 808b beq.w 8003734 <_dtoa_r+0x4f4> + 800361e: e9dd 3404 ldrd r3, r4, [sp, #16] + 8003622: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 + 8003626: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 800362a: 2200 movs r2, #0 + 800362c: 4b6f ldr r3, [pc, #444] ; (80037ec <_dtoa_r+0x5ac>) + 800362e: f7fd fa31 bl 8000a94 <__aeabi_dcmplt> + 8003632: 2800 cmp r0, #0 + 8003634: d07e beq.n 8003734 <_dtoa_r+0x4f4> + 8003636: 9b02 ldr r3, [sp, #8] + 8003638: 2b00 cmp r3, #0 + 800363a: d07b beq.n 8003734 <_dtoa_r+0x4f4> + 800363c: f1bb 0f00 cmp.w fp, #0 + 8003640: dd38 ble.n 80036b4 <_dtoa_r+0x474> + 8003642: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 8003646: 2200 movs r2, #0 + 8003648: 4b69 ldr r3, [pc, #420] ; (80037f0 <_dtoa_r+0x5b0>) + 800364a: f7fc ffb1 bl 80005b0 <__aeabi_dmul> + 800364e: 465c mov r4, fp + 8003650: e9cd 0104 strd r0, r1, [sp, #16] + 8003654: f109 38ff add.w r8, r9, #4294967295 ; 0xffffffff + 8003658: 3701 adds r7, #1 + 800365a: 4638 mov r0, r7 + 800365c: f7fc ff3e bl 80004dc <__aeabi_i2d> + 8003660: e9dd 2304 ldrd r2, r3, [sp, #16] + 8003664: f7fc ffa4 bl 80005b0 <__aeabi_dmul> + 8003668: 2200 movs r2, #0 + 800366a: 4b62 ldr r3, [pc, #392] ; (80037f4 <_dtoa_r+0x5b4>) + 800366c: f7fc fdea bl 8000244 <__adddf3> + 8003670: f1a1 7650 sub.w r6, r1, #54525952 ; 0x3400000 + 8003674: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 + 8003678: 9611 str r6, [sp, #68] ; 0x44 + 800367a: 2c00 cmp r4, #0 + 800367c: d15d bne.n 800373a <_dtoa_r+0x4fa> + 800367e: e9dd 0104 ldrd r0, r1, [sp, #16] + 8003682: 2200 movs r2, #0 + 8003684: 4b5c ldr r3, [pc, #368] ; (80037f8 <_dtoa_r+0x5b8>) + 8003686: f7fc fddb bl 8000240 <__aeabi_dsub> + 800368a: 4602 mov r2, r0 + 800368c: 460b mov r3, r1 + 800368e: e9cd 2304 strd r2, r3, [sp, #16] + 8003692: 4633 mov r3, r6 + 8003694: 9a10 ldr r2, [sp, #64] ; 0x40 + 8003696: f7fd fa1b bl 8000ad0 <__aeabi_dcmpgt> + 800369a: 2800 cmp r0, #0 + 800369c: f040 829e bne.w 8003bdc <_dtoa_r+0x99c> + 80036a0: e9dd 0104 ldrd r0, r1, [sp, #16] + 80036a4: 9a10 ldr r2, [sp, #64] ; 0x40 + 80036a6: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 + 80036aa: f7fd f9f3 bl 8000a94 <__aeabi_dcmplt> + 80036ae: 2800 cmp r0, #0 + 80036b0: f040 8292 bne.w 8003bd8 <_dtoa_r+0x998> + 80036b4: e9dd 340c ldrd r3, r4, [sp, #48] ; 0x30 + 80036b8: e9cd 3404 strd r3, r4, [sp, #16] + 80036bc: 9b17 ldr r3, [sp, #92] ; 0x5c + 80036be: 2b00 cmp r3, #0 + 80036c0: f2c0 8153 blt.w 800396a <_dtoa_r+0x72a> + 80036c4: f1b9 0f0e cmp.w r9, #14 + 80036c8: f300 814f bgt.w 800396a <_dtoa_r+0x72a> + 80036cc: 4b45 ldr r3, [pc, #276] ; (80037e4 <_dtoa_r+0x5a4>) + 80036ce: eb03 03c9 add.w r3, r3, r9, lsl #3 + 80036d2: e9d3 3400 ldrd r3, r4, [r3] + 80036d6: e9cd 3406 strd r3, r4, [sp, #24] + 80036da: 9b23 ldr r3, [sp, #140] ; 0x8c + 80036dc: 2b00 cmp r3, #0 + 80036de: f280 80db bge.w 8003898 <_dtoa_r+0x658> + 80036e2: 9b02 ldr r3, [sp, #8] + 80036e4: 2b00 cmp r3, #0 + 80036e6: f300 80d7 bgt.w 8003898 <_dtoa_r+0x658> + 80036ea: f040 8274 bne.w 8003bd6 <_dtoa_r+0x996> + 80036ee: e9dd 0106 ldrd r0, r1, [sp, #24] + 80036f2: 2200 movs r2, #0 + 80036f4: 4b40 ldr r3, [pc, #256] ; (80037f8 <_dtoa_r+0x5b8>) + 80036f6: f7fc ff5b bl 80005b0 <__aeabi_dmul> + 80036fa: e9dd 2304 ldrd r2, r3, [sp, #16] + 80036fe: f7fd f9dd bl 8000abc <__aeabi_dcmpge> + 8003702: 9c02 ldr r4, [sp, #8] + 8003704: 4626 mov r6, r4 + 8003706: 2800 cmp r0, #0 + 8003708: f040 824a bne.w 8003ba0 <_dtoa_r+0x960> + 800370c: 2331 movs r3, #49 ; 0x31 + 800370e: 9f08 ldr r7, [sp, #32] + 8003710: f109 0901 add.w r9, r9, #1 + 8003714: f807 3b01 strb.w r3, [r7], #1 + 8003718: e246 b.n 8003ba8 <_dtoa_r+0x968> + 800371a: 07e2 lsls r2, r4, #31 + 800371c: d505 bpl.n 800372a <_dtoa_r+0x4ea> + 800371e: e9d6 2300 ldrd r2, r3, [r6] + 8003722: f7fc ff45 bl 80005b0 <__aeabi_dmul> + 8003726: 2301 movs r3, #1 + 8003728: 3701 adds r7, #1 + 800372a: 1064 asrs r4, r4, #1 + 800372c: 3608 adds r6, #8 + 800372e: e76d b.n 800360c <_dtoa_r+0x3cc> + 8003730: 2702 movs r7, #2 + 8003732: e770 b.n 8003616 <_dtoa_r+0x3d6> + 8003734: 46c8 mov r8, r9 + 8003736: 9c02 ldr r4, [sp, #8] + 8003738: e78f b.n 800365a <_dtoa_r+0x41a> + 800373a: 9908 ldr r1, [sp, #32] + 800373c: 4b29 ldr r3, [pc, #164] ; (80037e4 <_dtoa_r+0x5a4>) + 800373e: 4421 add r1, r4 + 8003740: 9112 str r1, [sp, #72] ; 0x48 + 8003742: 990b ldr r1, [sp, #44] ; 0x2c + 8003744: eb03 03c4 add.w r3, r3, r4, lsl #3 + 8003748: e9dd 6710 ldrd r6, r7, [sp, #64] ; 0x40 + 800374c: e953 2302 ldrd r2, r3, [r3, #-8] + 8003750: 2900 cmp r1, #0 + 8003752: d055 beq.n 8003800 <_dtoa_r+0x5c0> + 8003754: 2000 movs r0, #0 + 8003756: 4929 ldr r1, [pc, #164] ; (80037fc <_dtoa_r+0x5bc>) + 8003758: f7fd f854 bl 8000804 <__aeabi_ddiv> + 800375c: 463b mov r3, r7 + 800375e: 4632 mov r2, r6 + 8003760: f7fc fd6e bl 8000240 <__aeabi_dsub> + 8003764: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 + 8003768: 9f08 ldr r7, [sp, #32] + 800376a: e9dd 0104 ldrd r0, r1, [sp, #16] + 800376e: f7fd f9cf bl 8000b10 <__aeabi_d2iz> + 8003772: 4604 mov r4, r0 + 8003774: f7fc feb2 bl 80004dc <__aeabi_i2d> + 8003778: 4602 mov r2, r0 + 800377a: 460b mov r3, r1 + 800377c: e9dd 0104 ldrd r0, r1, [sp, #16] + 8003780: f7fc fd5e bl 8000240 <__aeabi_dsub> + 8003784: 4602 mov r2, r0 + 8003786: 460b mov r3, r1 + 8003788: 3430 adds r4, #48 ; 0x30 + 800378a: e9cd 2304 strd r2, r3, [sp, #16] + 800378e: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 8003792: f807 4b01 strb.w r4, [r7], #1 + 8003796: f7fd f97d bl 8000a94 <__aeabi_dcmplt> + 800379a: 2800 cmp r0, #0 + 800379c: d174 bne.n 8003888 <_dtoa_r+0x648> + 800379e: e9dd 2304 ldrd r2, r3, [sp, #16] + 80037a2: 2000 movs r0, #0 + 80037a4: 4911 ldr r1, [pc, #68] ; (80037ec <_dtoa_r+0x5ac>) + 80037a6: f7fc fd4b bl 8000240 <__aeabi_dsub> + 80037aa: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 80037ae: f7fd f971 bl 8000a94 <__aeabi_dcmplt> + 80037b2: 2800 cmp r0, #0 + 80037b4: f040 80b6 bne.w 8003924 <_dtoa_r+0x6e4> + 80037b8: 9b12 ldr r3, [sp, #72] ; 0x48 + 80037ba: 429f cmp r7, r3 + 80037bc: f43f af7a beq.w 80036b4 <_dtoa_r+0x474> + 80037c0: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 80037c4: 2200 movs r2, #0 + 80037c6: 4b0a ldr r3, [pc, #40] ; (80037f0 <_dtoa_r+0x5b0>) + 80037c8: f7fc fef2 bl 80005b0 <__aeabi_dmul> + 80037cc: 2200 movs r2, #0 + 80037ce: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 + 80037d2: e9dd 0104 ldrd r0, r1, [sp, #16] + 80037d6: 4b06 ldr r3, [pc, #24] ; (80037f0 <_dtoa_r+0x5b0>) + 80037d8: f7fc feea bl 80005b0 <__aeabi_dmul> + 80037dc: e9cd 0104 strd r0, r1, [sp, #16] + 80037e0: e7c3 b.n 800376a <_dtoa_r+0x52a> + 80037e2: bf00 nop + 80037e4: 080053a0 .word 0x080053a0 + 80037e8: 08005378 .word 0x08005378 + 80037ec: 3ff00000 .word 0x3ff00000 + 80037f0: 40240000 .word 0x40240000 + 80037f4: 401c0000 .word 0x401c0000 + 80037f8: 40140000 .word 0x40140000 + 80037fc: 3fe00000 .word 0x3fe00000 + 8003800: 4630 mov r0, r6 + 8003802: 4639 mov r1, r7 + 8003804: f7fc fed4 bl 80005b0 <__aeabi_dmul> + 8003808: 9b12 ldr r3, [sp, #72] ; 0x48 + 800380a: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 + 800380e: 9c08 ldr r4, [sp, #32] + 8003810: 9314 str r3, [sp, #80] ; 0x50 + 8003812: e9dd 0104 ldrd r0, r1, [sp, #16] + 8003816: f7fd f97b bl 8000b10 <__aeabi_d2iz> + 800381a: 9015 str r0, [sp, #84] ; 0x54 + 800381c: f7fc fe5e bl 80004dc <__aeabi_i2d> + 8003820: 4602 mov r2, r0 + 8003822: 460b mov r3, r1 + 8003824: e9dd 0104 ldrd r0, r1, [sp, #16] + 8003828: f7fc fd0a bl 8000240 <__aeabi_dsub> + 800382c: 9b15 ldr r3, [sp, #84] ; 0x54 + 800382e: 4606 mov r6, r0 + 8003830: 3330 adds r3, #48 ; 0x30 + 8003832: f804 3b01 strb.w r3, [r4], #1 + 8003836: 9b12 ldr r3, [sp, #72] ; 0x48 + 8003838: 460f mov r7, r1 + 800383a: 429c cmp r4, r3 + 800383c: f04f 0200 mov.w r2, #0 + 8003840: d124 bne.n 800388c <_dtoa_r+0x64c> + 8003842: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 + 8003846: 4bb3 ldr r3, [pc, #716] ; (8003b14 <_dtoa_r+0x8d4>) + 8003848: f7fc fcfc bl 8000244 <__adddf3> + 800384c: 4602 mov r2, r0 + 800384e: 460b mov r3, r1 + 8003850: 4630 mov r0, r6 + 8003852: 4639 mov r1, r7 + 8003854: f7fd f93c bl 8000ad0 <__aeabi_dcmpgt> + 8003858: 2800 cmp r0, #0 + 800385a: d162 bne.n 8003922 <_dtoa_r+0x6e2> + 800385c: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 8003860: 2000 movs r0, #0 + 8003862: 49ac ldr r1, [pc, #688] ; (8003b14 <_dtoa_r+0x8d4>) + 8003864: f7fc fcec bl 8000240 <__aeabi_dsub> + 8003868: 4602 mov r2, r0 + 800386a: 460b mov r3, r1 + 800386c: 4630 mov r0, r6 + 800386e: 4639 mov r1, r7 + 8003870: f7fd f910 bl 8000a94 <__aeabi_dcmplt> + 8003874: 2800 cmp r0, #0 + 8003876: f43f af1d beq.w 80036b4 <_dtoa_r+0x474> + 800387a: 9f14 ldr r7, [sp, #80] ; 0x50 + 800387c: 1e7b subs r3, r7, #1 + 800387e: 9314 str r3, [sp, #80] ; 0x50 + 8003880: f817 3c01 ldrb.w r3, [r7, #-1] + 8003884: 2b30 cmp r3, #48 ; 0x30 + 8003886: d0f8 beq.n 800387a <_dtoa_r+0x63a> + 8003888: 46c1 mov r9, r8 + 800388a: e03a b.n 8003902 <_dtoa_r+0x6c2> + 800388c: 4ba2 ldr r3, [pc, #648] ; (8003b18 <_dtoa_r+0x8d8>) + 800388e: f7fc fe8f bl 80005b0 <__aeabi_dmul> + 8003892: e9cd 0104 strd r0, r1, [sp, #16] + 8003896: e7bc b.n 8003812 <_dtoa_r+0x5d2> + 8003898: 9f08 ldr r7, [sp, #32] + 800389a: e9dd 2306 ldrd r2, r3, [sp, #24] + 800389e: e9dd 0104 ldrd r0, r1, [sp, #16] + 80038a2: f7fc ffaf bl 8000804 <__aeabi_ddiv> + 80038a6: f7fd f933 bl 8000b10 <__aeabi_d2iz> + 80038aa: 4604 mov r4, r0 + 80038ac: f7fc fe16 bl 80004dc <__aeabi_i2d> + 80038b0: e9dd 2306 ldrd r2, r3, [sp, #24] + 80038b4: f7fc fe7c bl 80005b0 <__aeabi_dmul> + 80038b8: f104 0630 add.w r6, r4, #48 ; 0x30 + 80038bc: 460b mov r3, r1 + 80038be: 4602 mov r2, r0 + 80038c0: e9dd 0104 ldrd r0, r1, [sp, #16] + 80038c4: f7fc fcbc bl 8000240 <__aeabi_dsub> + 80038c8: f807 6b01 strb.w r6, [r7], #1 + 80038cc: 9e08 ldr r6, [sp, #32] + 80038ce: 9b02 ldr r3, [sp, #8] + 80038d0: 1bbe subs r6, r7, r6 + 80038d2: 42b3 cmp r3, r6 + 80038d4: d13a bne.n 800394c <_dtoa_r+0x70c> + 80038d6: 4602 mov r2, r0 + 80038d8: 460b mov r3, r1 + 80038da: f7fc fcb3 bl 8000244 <__adddf3> + 80038de: 4602 mov r2, r0 + 80038e0: 460b mov r3, r1 + 80038e2: e9cd 2302 strd r2, r3, [sp, #8] + 80038e6: e9dd 2306 ldrd r2, r3, [sp, #24] + 80038ea: f7fd f8f1 bl 8000ad0 <__aeabi_dcmpgt> + 80038ee: bb58 cbnz r0, 8003948 <_dtoa_r+0x708> + 80038f0: e9dd 2306 ldrd r2, r3, [sp, #24] + 80038f4: e9dd 0102 ldrd r0, r1, [sp, #8] + 80038f8: f7fd f8c2 bl 8000a80 <__aeabi_dcmpeq> + 80038fc: b108 cbz r0, 8003902 <_dtoa_r+0x6c2> + 80038fe: 07e1 lsls r1, r4, #31 + 8003900: d422 bmi.n 8003948 <_dtoa_r+0x708> + 8003902: 4628 mov r0, r5 + 8003904: 4651 mov r1, sl + 8003906: f000 faf1 bl 8003eec <_Bfree> + 800390a: 2300 movs r3, #0 + 800390c: 703b strb r3, [r7, #0] + 800390e: 9b24 ldr r3, [sp, #144] ; 0x90 + 8003910: f109 0001 add.w r0, r9, #1 + 8003914: 6018 str r0, [r3, #0] + 8003916: 9b26 ldr r3, [sp, #152] ; 0x98 + 8003918: 2b00 cmp r3, #0 + 800391a: f43f acdf beq.w 80032dc <_dtoa_r+0x9c> + 800391e: 601f str r7, [r3, #0] + 8003920: e4dc b.n 80032dc <_dtoa_r+0x9c> + 8003922: 4627 mov r7, r4 + 8003924: 463b mov r3, r7 + 8003926: 461f mov r7, r3 + 8003928: f813 2d01 ldrb.w r2, [r3, #-1]! + 800392c: 2a39 cmp r2, #57 ; 0x39 + 800392e: d107 bne.n 8003940 <_dtoa_r+0x700> + 8003930: 9a08 ldr r2, [sp, #32] + 8003932: 429a cmp r2, r3 + 8003934: d1f7 bne.n 8003926 <_dtoa_r+0x6e6> + 8003936: 2230 movs r2, #48 ; 0x30 + 8003938: 9908 ldr r1, [sp, #32] + 800393a: f108 0801 add.w r8, r8, #1 + 800393e: 700a strb r2, [r1, #0] + 8003940: 781a ldrb r2, [r3, #0] + 8003942: 3201 adds r2, #1 + 8003944: 701a strb r2, [r3, #0] + 8003946: e79f b.n 8003888 <_dtoa_r+0x648> + 8003948: 46c8 mov r8, r9 + 800394a: e7eb b.n 8003924 <_dtoa_r+0x6e4> + 800394c: 2200 movs r2, #0 + 800394e: 4b72 ldr r3, [pc, #456] ; (8003b18 <_dtoa_r+0x8d8>) + 8003950: f7fc fe2e bl 80005b0 <__aeabi_dmul> + 8003954: 4602 mov r2, r0 + 8003956: 460b mov r3, r1 + 8003958: e9cd 2304 strd r2, r3, [sp, #16] + 800395c: 2200 movs r2, #0 + 800395e: 2300 movs r3, #0 + 8003960: f7fd f88e bl 8000a80 <__aeabi_dcmpeq> + 8003964: 2800 cmp r0, #0 + 8003966: d098 beq.n 800389a <_dtoa_r+0x65a> + 8003968: e7cb b.n 8003902 <_dtoa_r+0x6c2> + 800396a: 9a0b ldr r2, [sp, #44] ; 0x2c + 800396c: 2a00 cmp r2, #0 + 800396e: f000 80cd beq.w 8003b0c <_dtoa_r+0x8cc> + 8003972: 9a22 ldr r2, [sp, #136] ; 0x88 + 8003974: 2a01 cmp r2, #1 + 8003976: f300 80af bgt.w 8003ad8 <_dtoa_r+0x898> + 800397a: 9a13 ldr r2, [sp, #76] ; 0x4c + 800397c: 2a00 cmp r2, #0 + 800397e: f000 80a7 beq.w 8003ad0 <_dtoa_r+0x890> + 8003982: f203 4333 addw r3, r3, #1075 ; 0x433 + 8003986: 9c0a ldr r4, [sp, #40] ; 0x28 + 8003988: 9f06 ldr r7, [sp, #24] + 800398a: 9a06 ldr r2, [sp, #24] + 800398c: 2101 movs r1, #1 + 800398e: 441a add r2, r3 + 8003990: 9206 str r2, [sp, #24] + 8003992: 9a09 ldr r2, [sp, #36] ; 0x24 + 8003994: 4628 mov r0, r5 + 8003996: 441a add r2, r3 + 8003998: 9209 str r2, [sp, #36] ; 0x24 + 800399a: f000 fb61 bl 8004060 <__i2b> + 800399e: 4606 mov r6, r0 + 80039a0: 2f00 cmp r7, #0 + 80039a2: dd0c ble.n 80039be <_dtoa_r+0x77e> + 80039a4: 9b09 ldr r3, [sp, #36] ; 0x24 + 80039a6: 2b00 cmp r3, #0 + 80039a8: dd09 ble.n 80039be <_dtoa_r+0x77e> + 80039aa: 42bb cmp r3, r7 + 80039ac: bfa8 it ge + 80039ae: 463b movge r3, r7 + 80039b0: 9a06 ldr r2, [sp, #24] + 80039b2: 1aff subs r7, r7, r3 + 80039b4: 1ad2 subs r2, r2, r3 + 80039b6: 9206 str r2, [sp, #24] + 80039b8: 9a09 ldr r2, [sp, #36] ; 0x24 + 80039ba: 1ad3 subs r3, r2, r3 + 80039bc: 9309 str r3, [sp, #36] ; 0x24 + 80039be: 9b0a ldr r3, [sp, #40] ; 0x28 + 80039c0: b1f3 cbz r3, 8003a00 <_dtoa_r+0x7c0> + 80039c2: 9b0b ldr r3, [sp, #44] ; 0x2c + 80039c4: 2b00 cmp r3, #0 + 80039c6: f000 80a9 beq.w 8003b1c <_dtoa_r+0x8dc> + 80039ca: 2c00 cmp r4, #0 + 80039cc: dd10 ble.n 80039f0 <_dtoa_r+0x7b0> + 80039ce: 4631 mov r1, r6 + 80039d0: 4622 mov r2, r4 + 80039d2: 4628 mov r0, r5 + 80039d4: f000 fbfe bl 80041d4 <__pow5mult> + 80039d8: 4652 mov r2, sl + 80039da: 4601 mov r1, r0 + 80039dc: 4606 mov r6, r0 + 80039de: 4628 mov r0, r5 + 80039e0: f000 fb54 bl 800408c <__multiply> + 80039e4: 4680 mov r8, r0 + 80039e6: 4651 mov r1, sl + 80039e8: 4628 mov r0, r5 + 80039ea: f000 fa7f bl 8003eec <_Bfree> + 80039ee: 46c2 mov sl, r8 + 80039f0: 9b0a ldr r3, [sp, #40] ; 0x28 + 80039f2: 1b1a subs r2, r3, r4 + 80039f4: d004 beq.n 8003a00 <_dtoa_r+0x7c0> + 80039f6: 4651 mov r1, sl + 80039f8: 4628 mov r0, r5 + 80039fa: f000 fbeb bl 80041d4 <__pow5mult> + 80039fe: 4682 mov sl, r0 + 8003a00: 2101 movs r1, #1 + 8003a02: 4628 mov r0, r5 + 8003a04: f000 fb2c bl 8004060 <__i2b> + 8003a08: 9b0e ldr r3, [sp, #56] ; 0x38 + 8003a0a: 4604 mov r4, r0 + 8003a0c: 2b00 cmp r3, #0 + 8003a0e: f340 8087 ble.w 8003b20 <_dtoa_r+0x8e0> + 8003a12: 461a mov r2, r3 + 8003a14: 4601 mov r1, r0 + 8003a16: 4628 mov r0, r5 + 8003a18: f000 fbdc bl 80041d4 <__pow5mult> + 8003a1c: 9b22 ldr r3, [sp, #136] ; 0x88 + 8003a1e: 4604 mov r4, r0 + 8003a20: 2b01 cmp r3, #1 + 8003a22: f340 8080 ble.w 8003b26 <_dtoa_r+0x8e6> + 8003a26: f04f 0800 mov.w r8, #0 + 8003a2a: 6923 ldr r3, [r4, #16] + 8003a2c: eb04 0383 add.w r3, r4, r3, lsl #2 + 8003a30: 6918 ldr r0, [r3, #16] + 8003a32: f000 fac7 bl 8003fc4 <__hi0bits> + 8003a36: f1c0 0020 rsb r0, r0, #32 + 8003a3a: 9b09 ldr r3, [sp, #36] ; 0x24 + 8003a3c: 4418 add r0, r3 + 8003a3e: f010 001f ands.w r0, r0, #31 + 8003a42: f000 8092 beq.w 8003b6a <_dtoa_r+0x92a> + 8003a46: f1c0 0320 rsb r3, r0, #32 + 8003a4a: 2b04 cmp r3, #4 + 8003a4c: f340 808a ble.w 8003b64 <_dtoa_r+0x924> + 8003a50: f1c0 001c rsb r0, r0, #28 + 8003a54: 9b06 ldr r3, [sp, #24] + 8003a56: 4407 add r7, r0 + 8003a58: 4403 add r3, r0 + 8003a5a: 9306 str r3, [sp, #24] + 8003a5c: 9b09 ldr r3, [sp, #36] ; 0x24 + 8003a5e: 4403 add r3, r0 + 8003a60: 9309 str r3, [sp, #36] ; 0x24 + 8003a62: 9b06 ldr r3, [sp, #24] + 8003a64: 2b00 cmp r3, #0 + 8003a66: dd05 ble.n 8003a74 <_dtoa_r+0x834> + 8003a68: 4651 mov r1, sl + 8003a6a: 461a mov r2, r3 + 8003a6c: 4628 mov r0, r5 + 8003a6e: f000 fc0b bl 8004288 <__lshift> + 8003a72: 4682 mov sl, r0 + 8003a74: 9b09 ldr r3, [sp, #36] ; 0x24 + 8003a76: 2b00 cmp r3, #0 + 8003a78: dd05 ble.n 8003a86 <_dtoa_r+0x846> + 8003a7a: 4621 mov r1, r4 + 8003a7c: 461a mov r2, r3 + 8003a7e: 4628 mov r0, r5 + 8003a80: f000 fc02 bl 8004288 <__lshift> + 8003a84: 4604 mov r4, r0 + 8003a86: 9b0f ldr r3, [sp, #60] ; 0x3c + 8003a88: 2b00 cmp r3, #0 + 8003a8a: d070 beq.n 8003b6e <_dtoa_r+0x92e> + 8003a8c: 4621 mov r1, r4 + 8003a8e: 4650 mov r0, sl + 8003a90: f000 fc66 bl 8004360 <__mcmp> + 8003a94: 2800 cmp r0, #0 + 8003a96: da6a bge.n 8003b6e <_dtoa_r+0x92e> + 8003a98: 2300 movs r3, #0 + 8003a9a: 4651 mov r1, sl + 8003a9c: 220a movs r2, #10 + 8003a9e: 4628 mov r0, r5 + 8003aa0: f000 fa46 bl 8003f30 <__multadd> + 8003aa4: 9b0b ldr r3, [sp, #44] ; 0x2c + 8003aa6: 4682 mov sl, r0 + 8003aa8: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff + 8003aac: 2b00 cmp r3, #0 + 8003aae: f000 8193 beq.w 8003dd8 <_dtoa_r+0xb98> + 8003ab2: 4631 mov r1, r6 + 8003ab4: 2300 movs r3, #0 + 8003ab6: 220a movs r2, #10 + 8003ab8: 4628 mov r0, r5 + 8003aba: f000 fa39 bl 8003f30 <__multadd> + 8003abe: f1bb 0f00 cmp.w fp, #0 + 8003ac2: 4606 mov r6, r0 + 8003ac4: f300 8093 bgt.w 8003bee <_dtoa_r+0x9ae> + 8003ac8: 9b22 ldr r3, [sp, #136] ; 0x88 + 8003aca: 2b02 cmp r3, #2 + 8003acc: dc57 bgt.n 8003b7e <_dtoa_r+0x93e> + 8003ace: e08e b.n 8003bee <_dtoa_r+0x9ae> + 8003ad0: 9b16 ldr r3, [sp, #88] ; 0x58 + 8003ad2: f1c3 0336 rsb r3, r3, #54 ; 0x36 + 8003ad6: e756 b.n 8003986 <_dtoa_r+0x746> + 8003ad8: 9b02 ldr r3, [sp, #8] + 8003ada: 1e5c subs r4, r3, #1 + 8003adc: 9b0a ldr r3, [sp, #40] ; 0x28 + 8003ade: 42a3 cmp r3, r4 + 8003ae0: bfb7 itett lt + 8003ae2: 9b0a ldrlt r3, [sp, #40] ; 0x28 + 8003ae4: 1b1c subge r4, r3, r4 + 8003ae6: 1ae2 sublt r2, r4, r3 + 8003ae8: 9b0e ldrlt r3, [sp, #56] ; 0x38 + 8003aea: bfbe ittt lt + 8003aec: 940a strlt r4, [sp, #40] ; 0x28 + 8003aee: 189b addlt r3, r3, r2 + 8003af0: 930e strlt r3, [sp, #56] ; 0x38 + 8003af2: 9b02 ldr r3, [sp, #8] + 8003af4: bfb8 it lt + 8003af6: 2400 movlt r4, #0 + 8003af8: 2b00 cmp r3, #0 + 8003afa: bfbb ittet lt + 8003afc: 9b06 ldrlt r3, [sp, #24] + 8003afe: 9a02 ldrlt r2, [sp, #8] + 8003b00: 9f06 ldrge r7, [sp, #24] + 8003b02: 1a9f sublt r7, r3, r2 + 8003b04: bfac ite ge + 8003b06: 9b02 ldrge r3, [sp, #8] + 8003b08: 2300 movlt r3, #0 + 8003b0a: e73e b.n 800398a <_dtoa_r+0x74a> + 8003b0c: 9c0a ldr r4, [sp, #40] ; 0x28 + 8003b0e: 9f06 ldr r7, [sp, #24] + 8003b10: 9e0b ldr r6, [sp, #44] ; 0x2c + 8003b12: e745 b.n 80039a0 <_dtoa_r+0x760> + 8003b14: 3fe00000 .word 0x3fe00000 + 8003b18: 40240000 .word 0x40240000 + 8003b1c: 9a0a ldr r2, [sp, #40] ; 0x28 + 8003b1e: e76a b.n 80039f6 <_dtoa_r+0x7b6> + 8003b20: 9b22 ldr r3, [sp, #136] ; 0x88 + 8003b22: 2b01 cmp r3, #1 + 8003b24: dc19 bgt.n 8003b5a <_dtoa_r+0x91a> + 8003b26: 9b04 ldr r3, [sp, #16] + 8003b28: b9bb cbnz r3, 8003b5a <_dtoa_r+0x91a> + 8003b2a: 9b05 ldr r3, [sp, #20] + 8003b2c: f3c3 0313 ubfx r3, r3, #0, #20 + 8003b30: b99b cbnz r3, 8003b5a <_dtoa_r+0x91a> + 8003b32: 9b05 ldr r3, [sp, #20] + 8003b34: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8003b38: 0d1b lsrs r3, r3, #20 + 8003b3a: 051b lsls r3, r3, #20 + 8003b3c: b183 cbz r3, 8003b60 <_dtoa_r+0x920> + 8003b3e: f04f 0801 mov.w r8, #1 + 8003b42: 9b06 ldr r3, [sp, #24] + 8003b44: 3301 adds r3, #1 + 8003b46: 9306 str r3, [sp, #24] + 8003b48: 9b09 ldr r3, [sp, #36] ; 0x24 + 8003b4a: 3301 adds r3, #1 + 8003b4c: 9309 str r3, [sp, #36] ; 0x24 + 8003b4e: 9b0e ldr r3, [sp, #56] ; 0x38 + 8003b50: 2b00 cmp r3, #0 + 8003b52: f47f af6a bne.w 8003a2a <_dtoa_r+0x7ea> + 8003b56: 2001 movs r0, #1 + 8003b58: e76f b.n 8003a3a <_dtoa_r+0x7fa> + 8003b5a: f04f 0800 mov.w r8, #0 + 8003b5e: e7f6 b.n 8003b4e <_dtoa_r+0x90e> + 8003b60: 4698 mov r8, r3 + 8003b62: e7f4 b.n 8003b4e <_dtoa_r+0x90e> + 8003b64: f43f af7d beq.w 8003a62 <_dtoa_r+0x822> + 8003b68: 4618 mov r0, r3 + 8003b6a: 301c adds r0, #28 + 8003b6c: e772 b.n 8003a54 <_dtoa_r+0x814> + 8003b6e: 9b02 ldr r3, [sp, #8] + 8003b70: 2b00 cmp r3, #0 + 8003b72: dc36 bgt.n 8003be2 <_dtoa_r+0x9a2> + 8003b74: 9b22 ldr r3, [sp, #136] ; 0x88 + 8003b76: 2b02 cmp r3, #2 + 8003b78: dd33 ble.n 8003be2 <_dtoa_r+0x9a2> + 8003b7a: f8dd b008 ldr.w fp, [sp, #8] + 8003b7e: f1bb 0f00 cmp.w fp, #0 + 8003b82: d10d bne.n 8003ba0 <_dtoa_r+0x960> + 8003b84: 4621 mov r1, r4 + 8003b86: 465b mov r3, fp + 8003b88: 2205 movs r2, #5 + 8003b8a: 4628 mov r0, r5 + 8003b8c: f000 f9d0 bl 8003f30 <__multadd> + 8003b90: 4601 mov r1, r0 + 8003b92: 4604 mov r4, r0 + 8003b94: 4650 mov r0, sl + 8003b96: f000 fbe3 bl 8004360 <__mcmp> + 8003b9a: 2800 cmp r0, #0 + 8003b9c: f73f adb6 bgt.w 800370c <_dtoa_r+0x4cc> + 8003ba0: 9b23 ldr r3, [sp, #140] ; 0x8c + 8003ba2: 9f08 ldr r7, [sp, #32] + 8003ba4: ea6f 0903 mvn.w r9, r3 + 8003ba8: f04f 0800 mov.w r8, #0 + 8003bac: 4621 mov r1, r4 + 8003bae: 4628 mov r0, r5 + 8003bb0: f000 f99c bl 8003eec <_Bfree> + 8003bb4: 2e00 cmp r6, #0 + 8003bb6: f43f aea4 beq.w 8003902 <_dtoa_r+0x6c2> + 8003bba: f1b8 0f00 cmp.w r8, #0 + 8003bbe: d005 beq.n 8003bcc <_dtoa_r+0x98c> + 8003bc0: 45b0 cmp r8, r6 + 8003bc2: d003 beq.n 8003bcc <_dtoa_r+0x98c> + 8003bc4: 4641 mov r1, r8 + 8003bc6: 4628 mov r0, r5 + 8003bc8: f000 f990 bl 8003eec <_Bfree> + 8003bcc: 4631 mov r1, r6 + 8003bce: 4628 mov r0, r5 + 8003bd0: f000 f98c bl 8003eec <_Bfree> + 8003bd4: e695 b.n 8003902 <_dtoa_r+0x6c2> + 8003bd6: 2400 movs r4, #0 + 8003bd8: 4626 mov r6, r4 + 8003bda: e7e1 b.n 8003ba0 <_dtoa_r+0x960> + 8003bdc: 46c1 mov r9, r8 + 8003bde: 4626 mov r6, r4 + 8003be0: e594 b.n 800370c <_dtoa_r+0x4cc> + 8003be2: 9b0b ldr r3, [sp, #44] ; 0x2c + 8003be4: f8dd b008 ldr.w fp, [sp, #8] + 8003be8: 2b00 cmp r3, #0 + 8003bea: f000 80fc beq.w 8003de6 <_dtoa_r+0xba6> + 8003bee: 2f00 cmp r7, #0 + 8003bf0: dd05 ble.n 8003bfe <_dtoa_r+0x9be> + 8003bf2: 4631 mov r1, r6 + 8003bf4: 463a mov r2, r7 + 8003bf6: 4628 mov r0, r5 + 8003bf8: f000 fb46 bl 8004288 <__lshift> + 8003bfc: 4606 mov r6, r0 + 8003bfe: f1b8 0f00 cmp.w r8, #0 + 8003c02: d05c beq.n 8003cbe <_dtoa_r+0xa7e> + 8003c04: 4628 mov r0, r5 + 8003c06: 6871 ldr r1, [r6, #4] + 8003c08: f000 f930 bl 8003e6c <_Balloc> + 8003c0c: 4607 mov r7, r0 + 8003c0e: b928 cbnz r0, 8003c1c <_dtoa_r+0x9dc> + 8003c10: 4602 mov r2, r0 + 8003c12: f240 21ea movw r1, #746 ; 0x2ea + 8003c16: 4b7e ldr r3, [pc, #504] ; (8003e10 <_dtoa_r+0xbd0>) + 8003c18: f7ff bb26 b.w 8003268 <_dtoa_r+0x28> + 8003c1c: 6932 ldr r2, [r6, #16] + 8003c1e: f106 010c add.w r1, r6, #12 + 8003c22: 3202 adds r2, #2 + 8003c24: 0092 lsls r2, r2, #2 + 8003c26: 300c adds r0, #12 + 8003c28: f000 f912 bl 8003e50 + 8003c2c: 2201 movs r2, #1 + 8003c2e: 4639 mov r1, r7 + 8003c30: 4628 mov r0, r5 + 8003c32: f000 fb29 bl 8004288 <__lshift> + 8003c36: 46b0 mov r8, r6 + 8003c38: 4606 mov r6, r0 + 8003c3a: 9b08 ldr r3, [sp, #32] + 8003c3c: 3301 adds r3, #1 + 8003c3e: 9302 str r3, [sp, #8] + 8003c40: 9b08 ldr r3, [sp, #32] + 8003c42: 445b add r3, fp + 8003c44: 930a str r3, [sp, #40] ; 0x28 + 8003c46: 9b04 ldr r3, [sp, #16] + 8003c48: f003 0301 and.w r3, r3, #1 + 8003c4c: 9309 str r3, [sp, #36] ; 0x24 + 8003c4e: 9b02 ldr r3, [sp, #8] + 8003c50: 4621 mov r1, r4 + 8003c52: 4650 mov r0, sl + 8003c54: f103 3bff add.w fp, r3, #4294967295 ; 0xffffffff + 8003c58: f7ff fa64 bl 8003124 + 8003c5c: 4603 mov r3, r0 + 8003c5e: 4641 mov r1, r8 + 8003c60: 3330 adds r3, #48 ; 0x30 + 8003c62: 9004 str r0, [sp, #16] + 8003c64: 4650 mov r0, sl + 8003c66: 930b str r3, [sp, #44] ; 0x2c + 8003c68: f000 fb7a bl 8004360 <__mcmp> + 8003c6c: 4632 mov r2, r6 + 8003c6e: 9006 str r0, [sp, #24] + 8003c70: 4621 mov r1, r4 + 8003c72: 4628 mov r0, r5 + 8003c74: f000 fb90 bl 8004398 <__mdiff> + 8003c78: 68c2 ldr r2, [r0, #12] + 8003c7a: 4607 mov r7, r0 + 8003c7c: 9b0b ldr r3, [sp, #44] ; 0x2c + 8003c7e: bb02 cbnz r2, 8003cc2 <_dtoa_r+0xa82> + 8003c80: 4601 mov r1, r0 + 8003c82: 4650 mov r0, sl + 8003c84: f000 fb6c bl 8004360 <__mcmp> + 8003c88: 4602 mov r2, r0 + 8003c8a: 9b0b ldr r3, [sp, #44] ; 0x2c + 8003c8c: 4639 mov r1, r7 + 8003c8e: 4628 mov r0, r5 + 8003c90: e9cd 320b strd r3, r2, [sp, #44] ; 0x2c + 8003c94: f000 f92a bl 8003eec <_Bfree> + 8003c98: 9b22 ldr r3, [sp, #136] ; 0x88 + 8003c9a: 9a0c ldr r2, [sp, #48] ; 0x30 + 8003c9c: 9f02 ldr r7, [sp, #8] + 8003c9e: ea43 0102 orr.w r1, r3, r2 + 8003ca2: 9b09 ldr r3, [sp, #36] ; 0x24 + 8003ca4: 430b orrs r3, r1 + 8003ca6: 9b0b ldr r3, [sp, #44] ; 0x2c + 8003ca8: d10d bne.n 8003cc6 <_dtoa_r+0xa86> + 8003caa: 2b39 cmp r3, #57 ; 0x39 + 8003cac: d027 beq.n 8003cfe <_dtoa_r+0xabe> + 8003cae: 9a06 ldr r2, [sp, #24] + 8003cb0: 2a00 cmp r2, #0 + 8003cb2: dd01 ble.n 8003cb8 <_dtoa_r+0xa78> + 8003cb4: 9b04 ldr r3, [sp, #16] + 8003cb6: 3331 adds r3, #49 ; 0x31 + 8003cb8: f88b 3000 strb.w r3, [fp] + 8003cbc: e776 b.n 8003bac <_dtoa_r+0x96c> + 8003cbe: 4630 mov r0, r6 + 8003cc0: e7b9 b.n 8003c36 <_dtoa_r+0x9f6> + 8003cc2: 2201 movs r2, #1 + 8003cc4: e7e2 b.n 8003c8c <_dtoa_r+0xa4c> + 8003cc6: 9906 ldr r1, [sp, #24] + 8003cc8: 2900 cmp r1, #0 + 8003cca: db04 blt.n 8003cd6 <_dtoa_r+0xa96> + 8003ccc: 9822 ldr r0, [sp, #136] ; 0x88 + 8003cce: 4301 orrs r1, r0 + 8003cd0: 9809 ldr r0, [sp, #36] ; 0x24 + 8003cd2: 4301 orrs r1, r0 + 8003cd4: d120 bne.n 8003d18 <_dtoa_r+0xad8> + 8003cd6: 2a00 cmp r2, #0 + 8003cd8: ddee ble.n 8003cb8 <_dtoa_r+0xa78> + 8003cda: 4651 mov r1, sl + 8003cdc: 2201 movs r2, #1 + 8003cde: 4628 mov r0, r5 + 8003ce0: 9302 str r3, [sp, #8] + 8003ce2: f000 fad1 bl 8004288 <__lshift> + 8003ce6: 4621 mov r1, r4 + 8003ce8: 4682 mov sl, r0 + 8003cea: f000 fb39 bl 8004360 <__mcmp> + 8003cee: 2800 cmp r0, #0 + 8003cf0: 9b02 ldr r3, [sp, #8] + 8003cf2: dc02 bgt.n 8003cfa <_dtoa_r+0xaba> + 8003cf4: d1e0 bne.n 8003cb8 <_dtoa_r+0xa78> + 8003cf6: 07da lsls r2, r3, #31 + 8003cf8: d5de bpl.n 8003cb8 <_dtoa_r+0xa78> + 8003cfa: 2b39 cmp r3, #57 ; 0x39 + 8003cfc: d1da bne.n 8003cb4 <_dtoa_r+0xa74> + 8003cfe: 2339 movs r3, #57 ; 0x39 + 8003d00: f88b 3000 strb.w r3, [fp] + 8003d04: 463b mov r3, r7 + 8003d06: 461f mov r7, r3 + 8003d08: f817 2c01 ldrb.w r2, [r7, #-1] + 8003d0c: 3b01 subs r3, #1 + 8003d0e: 2a39 cmp r2, #57 ; 0x39 + 8003d10: d050 beq.n 8003db4 <_dtoa_r+0xb74> + 8003d12: 3201 adds r2, #1 + 8003d14: 701a strb r2, [r3, #0] + 8003d16: e749 b.n 8003bac <_dtoa_r+0x96c> + 8003d18: 2a00 cmp r2, #0 + 8003d1a: dd03 ble.n 8003d24 <_dtoa_r+0xae4> + 8003d1c: 2b39 cmp r3, #57 ; 0x39 + 8003d1e: d0ee beq.n 8003cfe <_dtoa_r+0xabe> + 8003d20: 3301 adds r3, #1 + 8003d22: e7c9 b.n 8003cb8 <_dtoa_r+0xa78> + 8003d24: 9a02 ldr r2, [sp, #8] + 8003d26: 990a ldr r1, [sp, #40] ; 0x28 + 8003d28: f802 3c01 strb.w r3, [r2, #-1] + 8003d2c: 428a cmp r2, r1 + 8003d2e: d02a beq.n 8003d86 <_dtoa_r+0xb46> + 8003d30: 4651 mov r1, sl + 8003d32: 2300 movs r3, #0 + 8003d34: 220a movs r2, #10 + 8003d36: 4628 mov r0, r5 + 8003d38: f000 f8fa bl 8003f30 <__multadd> + 8003d3c: 45b0 cmp r8, r6 + 8003d3e: 4682 mov sl, r0 + 8003d40: f04f 0300 mov.w r3, #0 + 8003d44: f04f 020a mov.w r2, #10 + 8003d48: 4641 mov r1, r8 + 8003d4a: 4628 mov r0, r5 + 8003d4c: d107 bne.n 8003d5e <_dtoa_r+0xb1e> + 8003d4e: f000 f8ef bl 8003f30 <__multadd> + 8003d52: 4680 mov r8, r0 + 8003d54: 4606 mov r6, r0 + 8003d56: 9b02 ldr r3, [sp, #8] + 8003d58: 3301 adds r3, #1 + 8003d5a: 9302 str r3, [sp, #8] + 8003d5c: e777 b.n 8003c4e <_dtoa_r+0xa0e> + 8003d5e: f000 f8e7 bl 8003f30 <__multadd> + 8003d62: 4631 mov r1, r6 + 8003d64: 4680 mov r8, r0 + 8003d66: 2300 movs r3, #0 + 8003d68: 220a movs r2, #10 + 8003d6a: 4628 mov r0, r5 + 8003d6c: f000 f8e0 bl 8003f30 <__multadd> + 8003d70: 4606 mov r6, r0 + 8003d72: e7f0 b.n 8003d56 <_dtoa_r+0xb16> + 8003d74: f1bb 0f00 cmp.w fp, #0 + 8003d78: bfcc ite gt + 8003d7a: 465f movgt r7, fp + 8003d7c: 2701 movle r7, #1 + 8003d7e: f04f 0800 mov.w r8, #0 + 8003d82: 9a08 ldr r2, [sp, #32] + 8003d84: 4417 add r7, r2 + 8003d86: 4651 mov r1, sl + 8003d88: 2201 movs r2, #1 + 8003d8a: 4628 mov r0, r5 + 8003d8c: 9302 str r3, [sp, #8] + 8003d8e: f000 fa7b bl 8004288 <__lshift> + 8003d92: 4621 mov r1, r4 + 8003d94: 4682 mov sl, r0 + 8003d96: f000 fae3 bl 8004360 <__mcmp> + 8003d9a: 2800 cmp r0, #0 + 8003d9c: dcb2 bgt.n 8003d04 <_dtoa_r+0xac4> + 8003d9e: d102 bne.n 8003da6 <_dtoa_r+0xb66> + 8003da0: 9b02 ldr r3, [sp, #8] + 8003da2: 07db lsls r3, r3, #31 + 8003da4: d4ae bmi.n 8003d04 <_dtoa_r+0xac4> + 8003da6: 463b mov r3, r7 + 8003da8: 461f mov r7, r3 + 8003daa: f813 2d01 ldrb.w r2, [r3, #-1]! + 8003dae: 2a30 cmp r2, #48 ; 0x30 + 8003db0: d0fa beq.n 8003da8 <_dtoa_r+0xb68> + 8003db2: e6fb b.n 8003bac <_dtoa_r+0x96c> + 8003db4: 9a08 ldr r2, [sp, #32] + 8003db6: 429a cmp r2, r3 + 8003db8: d1a5 bne.n 8003d06 <_dtoa_r+0xac6> + 8003dba: 2331 movs r3, #49 ; 0x31 + 8003dbc: f109 0901 add.w r9, r9, #1 + 8003dc0: 7013 strb r3, [r2, #0] + 8003dc2: e6f3 b.n 8003bac <_dtoa_r+0x96c> + 8003dc4: 4b13 ldr r3, [pc, #76] ; (8003e14 <_dtoa_r+0xbd4>) + 8003dc6: f7ff baa7 b.w 8003318 <_dtoa_r+0xd8> + 8003dca: 9b26 ldr r3, [sp, #152] ; 0x98 + 8003dcc: 2b00 cmp r3, #0 + 8003dce: f47f aa80 bne.w 80032d2 <_dtoa_r+0x92> + 8003dd2: 4b11 ldr r3, [pc, #68] ; (8003e18 <_dtoa_r+0xbd8>) + 8003dd4: f7ff baa0 b.w 8003318 <_dtoa_r+0xd8> + 8003dd8: f1bb 0f00 cmp.w fp, #0 + 8003ddc: dc03 bgt.n 8003de6 <_dtoa_r+0xba6> + 8003dde: 9b22 ldr r3, [sp, #136] ; 0x88 + 8003de0: 2b02 cmp r3, #2 + 8003de2: f73f aecc bgt.w 8003b7e <_dtoa_r+0x93e> + 8003de6: 9f08 ldr r7, [sp, #32] + 8003de8: 4621 mov r1, r4 + 8003dea: 4650 mov r0, sl + 8003dec: f7ff f99a bl 8003124 + 8003df0: 9a08 ldr r2, [sp, #32] + 8003df2: f100 0330 add.w r3, r0, #48 ; 0x30 + 8003df6: f807 3b01 strb.w r3, [r7], #1 + 8003dfa: 1aba subs r2, r7, r2 + 8003dfc: 4593 cmp fp, r2 + 8003dfe: ddb9 ble.n 8003d74 <_dtoa_r+0xb34> + 8003e00: 4651 mov r1, sl + 8003e02: 2300 movs r3, #0 + 8003e04: 220a movs r2, #10 + 8003e06: 4628 mov r0, r5 + 8003e08: f000 f892 bl 8003f30 <__multadd> + 8003e0c: 4682 mov sl, r0 + 8003e0e: e7eb b.n 8003de8 <_dtoa_r+0xba8> + 8003e10: 08005303 .word 0x08005303 + 8003e14: 0800525c .word 0x0800525c + 8003e18: 08005280 .word 0x08005280 + +08003e1c <_localeconv_r>: + 8003e1c: 4800 ldr r0, [pc, #0] ; (8003e20 <_localeconv_r+0x4>) + 8003e1e: 4770 bx lr + 8003e20: 20000160 .word 0x20000160 + +08003e24 : + 8003e24: 4b02 ldr r3, [pc, #8] ; (8003e30 ) + 8003e26: 4601 mov r1, r0 + 8003e28: 6818 ldr r0, [r3, #0] + 8003e2a: f000 bbfb b.w 8004624 <_malloc_r> + 8003e2e: bf00 nop + 8003e30: 2000000c .word 0x2000000c + +08003e34 : + 8003e34: 4603 mov r3, r0 + 8003e36: b510 push {r4, lr} + 8003e38: b2c9 uxtb r1, r1 + 8003e3a: 4402 add r2, r0 + 8003e3c: 4293 cmp r3, r2 + 8003e3e: 4618 mov r0, r3 + 8003e40: d101 bne.n 8003e46 + 8003e42: 2000 movs r0, #0 + 8003e44: e003 b.n 8003e4e + 8003e46: 7804 ldrb r4, [r0, #0] + 8003e48: 3301 adds r3, #1 + 8003e4a: 428c cmp r4, r1 + 8003e4c: d1f6 bne.n 8003e3c + 8003e4e: bd10 pop {r4, pc} + +08003e50 : + 8003e50: 440a add r2, r1 + 8003e52: 4291 cmp r1, r2 + 8003e54: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 8003e58: d100 bne.n 8003e5c + 8003e5a: 4770 bx lr + 8003e5c: b510 push {r4, lr} + 8003e5e: f811 4b01 ldrb.w r4, [r1], #1 + 8003e62: 4291 cmp r1, r2 + 8003e64: f803 4f01 strb.w r4, [r3, #1]! + 8003e68: d1f9 bne.n 8003e5e + 8003e6a: bd10 pop {r4, pc} + +08003e6c <_Balloc>: + 8003e6c: b570 push {r4, r5, r6, lr} + 8003e6e: 6a46 ldr r6, [r0, #36] ; 0x24 + 8003e70: 4604 mov r4, r0 + 8003e72: 460d mov r5, r1 + 8003e74: b976 cbnz r6, 8003e94 <_Balloc+0x28> + 8003e76: 2010 movs r0, #16 + 8003e78: f7ff ffd4 bl 8003e24 + 8003e7c: 4602 mov r2, r0 + 8003e7e: 6260 str r0, [r4, #36] ; 0x24 + 8003e80: b920 cbnz r0, 8003e8c <_Balloc+0x20> + 8003e82: 2166 movs r1, #102 ; 0x66 + 8003e84: 4b17 ldr r3, [pc, #92] ; (8003ee4 <_Balloc+0x78>) + 8003e86: 4818 ldr r0, [pc, #96] ; (8003ee8 <_Balloc+0x7c>) + 8003e88: f000 fc36 bl 80046f8 <__assert_func> + 8003e8c: e9c0 6601 strd r6, r6, [r0, #4] + 8003e90: 6006 str r6, [r0, #0] + 8003e92: 60c6 str r6, [r0, #12] + 8003e94: 6a66 ldr r6, [r4, #36] ; 0x24 + 8003e96: 68f3 ldr r3, [r6, #12] + 8003e98: b183 cbz r3, 8003ebc <_Balloc+0x50> + 8003e9a: 6a63 ldr r3, [r4, #36] ; 0x24 + 8003e9c: 68db ldr r3, [r3, #12] + 8003e9e: f853 0025 ldr.w r0, [r3, r5, lsl #2] + 8003ea2: b9b8 cbnz r0, 8003ed4 <_Balloc+0x68> + 8003ea4: 2101 movs r1, #1 + 8003ea6: fa01 f605 lsl.w r6, r1, r5 + 8003eaa: 1d72 adds r2, r6, #5 + 8003eac: 4620 mov r0, r4 + 8003eae: 0092 lsls r2, r2, #2 + 8003eb0: f000 fb5e bl 8004570 <_calloc_r> + 8003eb4: b160 cbz r0, 8003ed0 <_Balloc+0x64> + 8003eb6: e9c0 5601 strd r5, r6, [r0, #4] + 8003eba: e00e b.n 8003eda <_Balloc+0x6e> + 8003ebc: 2221 movs r2, #33 ; 0x21 + 8003ebe: 2104 movs r1, #4 + 8003ec0: 4620 mov r0, r4 + 8003ec2: f000 fb55 bl 8004570 <_calloc_r> + 8003ec6: 6a63 ldr r3, [r4, #36] ; 0x24 + 8003ec8: 60f0 str r0, [r6, #12] + 8003eca: 68db ldr r3, [r3, #12] + 8003ecc: 2b00 cmp r3, #0 + 8003ece: d1e4 bne.n 8003e9a <_Balloc+0x2e> + 8003ed0: 2000 movs r0, #0 + 8003ed2: bd70 pop {r4, r5, r6, pc} + 8003ed4: 6802 ldr r2, [r0, #0] + 8003ed6: f843 2025 str.w r2, [r3, r5, lsl #2] + 8003eda: 2300 movs r3, #0 + 8003edc: e9c0 3303 strd r3, r3, [r0, #12] + 8003ee0: e7f7 b.n 8003ed2 <_Balloc+0x66> + 8003ee2: bf00 nop + 8003ee4: 0800528d .word 0x0800528d + 8003ee8: 08005314 .word 0x08005314 + +08003eec <_Bfree>: + 8003eec: b570 push {r4, r5, r6, lr} + 8003eee: 6a46 ldr r6, [r0, #36] ; 0x24 + 8003ef0: 4605 mov r5, r0 + 8003ef2: 460c mov r4, r1 + 8003ef4: b976 cbnz r6, 8003f14 <_Bfree+0x28> + 8003ef6: 2010 movs r0, #16 + 8003ef8: f7ff ff94 bl 8003e24 + 8003efc: 4602 mov r2, r0 + 8003efe: 6268 str r0, [r5, #36] ; 0x24 + 8003f00: b920 cbnz r0, 8003f0c <_Bfree+0x20> + 8003f02: 218a movs r1, #138 ; 0x8a + 8003f04: 4b08 ldr r3, [pc, #32] ; (8003f28 <_Bfree+0x3c>) + 8003f06: 4809 ldr r0, [pc, #36] ; (8003f2c <_Bfree+0x40>) + 8003f08: f000 fbf6 bl 80046f8 <__assert_func> + 8003f0c: e9c0 6601 strd r6, r6, [r0, #4] + 8003f10: 6006 str r6, [r0, #0] + 8003f12: 60c6 str r6, [r0, #12] + 8003f14: b13c cbz r4, 8003f26 <_Bfree+0x3a> + 8003f16: 6a6b ldr r3, [r5, #36] ; 0x24 + 8003f18: 6862 ldr r2, [r4, #4] + 8003f1a: 68db ldr r3, [r3, #12] + 8003f1c: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8003f20: 6021 str r1, [r4, #0] + 8003f22: f843 4022 str.w r4, [r3, r2, lsl #2] + 8003f26: bd70 pop {r4, r5, r6, pc} + 8003f28: 0800528d .word 0x0800528d + 8003f2c: 08005314 .word 0x08005314 + +08003f30 <__multadd>: + 8003f30: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8003f34: 4698 mov r8, r3 + 8003f36: 460c mov r4, r1 + 8003f38: 2300 movs r3, #0 + 8003f3a: 690e ldr r6, [r1, #16] + 8003f3c: 4607 mov r7, r0 + 8003f3e: f101 0014 add.w r0, r1, #20 + 8003f42: 6805 ldr r5, [r0, #0] + 8003f44: 3301 adds r3, #1 + 8003f46: b2a9 uxth r1, r5 + 8003f48: fb02 8101 mla r1, r2, r1, r8 + 8003f4c: 0c2d lsrs r5, r5, #16 + 8003f4e: ea4f 4c11 mov.w ip, r1, lsr #16 + 8003f52: fb02 c505 mla r5, r2, r5, ip + 8003f56: b289 uxth r1, r1 + 8003f58: eb01 4105 add.w r1, r1, r5, lsl #16 + 8003f5c: 429e cmp r6, r3 + 8003f5e: ea4f 4815 mov.w r8, r5, lsr #16 + 8003f62: f840 1b04 str.w r1, [r0], #4 + 8003f66: dcec bgt.n 8003f42 <__multadd+0x12> + 8003f68: f1b8 0f00 cmp.w r8, #0 + 8003f6c: d022 beq.n 8003fb4 <__multadd+0x84> + 8003f6e: 68a3 ldr r3, [r4, #8] + 8003f70: 42b3 cmp r3, r6 + 8003f72: dc19 bgt.n 8003fa8 <__multadd+0x78> + 8003f74: 6861 ldr r1, [r4, #4] + 8003f76: 4638 mov r0, r7 + 8003f78: 3101 adds r1, #1 + 8003f7a: f7ff ff77 bl 8003e6c <_Balloc> + 8003f7e: 4605 mov r5, r0 + 8003f80: b928 cbnz r0, 8003f8e <__multadd+0x5e> + 8003f82: 4602 mov r2, r0 + 8003f84: 21b5 movs r1, #181 ; 0xb5 + 8003f86: 4b0d ldr r3, [pc, #52] ; (8003fbc <__multadd+0x8c>) + 8003f88: 480d ldr r0, [pc, #52] ; (8003fc0 <__multadd+0x90>) + 8003f8a: f000 fbb5 bl 80046f8 <__assert_func> + 8003f8e: 6922 ldr r2, [r4, #16] + 8003f90: f104 010c add.w r1, r4, #12 + 8003f94: 3202 adds r2, #2 + 8003f96: 0092 lsls r2, r2, #2 + 8003f98: 300c adds r0, #12 + 8003f9a: f7ff ff59 bl 8003e50 + 8003f9e: 4621 mov r1, r4 + 8003fa0: 4638 mov r0, r7 + 8003fa2: f7ff ffa3 bl 8003eec <_Bfree> + 8003fa6: 462c mov r4, r5 + 8003fa8: eb04 0386 add.w r3, r4, r6, lsl #2 + 8003fac: 3601 adds r6, #1 + 8003fae: f8c3 8014 str.w r8, [r3, #20] + 8003fb2: 6126 str r6, [r4, #16] + 8003fb4: 4620 mov r0, r4 + 8003fb6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8003fba: bf00 nop + 8003fbc: 08005303 .word 0x08005303 + 8003fc0: 08005314 .word 0x08005314 + +08003fc4 <__hi0bits>: + 8003fc4: 0c02 lsrs r2, r0, #16 + 8003fc6: 0412 lsls r2, r2, #16 + 8003fc8: 4603 mov r3, r0 + 8003fca: b9ca cbnz r2, 8004000 <__hi0bits+0x3c> + 8003fcc: 0403 lsls r3, r0, #16 + 8003fce: 2010 movs r0, #16 + 8003fd0: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 + 8003fd4: bf04 itt eq + 8003fd6: 021b lsleq r3, r3, #8 + 8003fd8: 3008 addeq r0, #8 + 8003fda: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 + 8003fde: bf04 itt eq + 8003fe0: 011b lsleq r3, r3, #4 + 8003fe2: 3004 addeq r0, #4 + 8003fe4: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 + 8003fe8: bf04 itt eq + 8003fea: 009b lsleq r3, r3, #2 + 8003fec: 3002 addeq r0, #2 + 8003fee: 2b00 cmp r3, #0 + 8003ff0: db05 blt.n 8003ffe <__hi0bits+0x3a> + 8003ff2: f013 4f80 tst.w r3, #1073741824 ; 0x40000000 + 8003ff6: f100 0001 add.w r0, r0, #1 + 8003ffa: bf08 it eq + 8003ffc: 2020 moveq r0, #32 + 8003ffe: 4770 bx lr + 8004000: 2000 movs r0, #0 + 8004002: e7e5 b.n 8003fd0 <__hi0bits+0xc> + +08004004 <__lo0bits>: + 8004004: 6803 ldr r3, [r0, #0] + 8004006: 4602 mov r2, r0 + 8004008: f013 0007 ands.w r0, r3, #7 + 800400c: d00b beq.n 8004026 <__lo0bits+0x22> + 800400e: 07d9 lsls r1, r3, #31 + 8004010: d422 bmi.n 8004058 <__lo0bits+0x54> + 8004012: 0798 lsls r0, r3, #30 + 8004014: bf49 itett mi + 8004016: 085b lsrmi r3, r3, #1 + 8004018: 089b lsrpl r3, r3, #2 + 800401a: 2001 movmi r0, #1 + 800401c: 6013 strmi r3, [r2, #0] + 800401e: bf5c itt pl + 8004020: 2002 movpl r0, #2 + 8004022: 6013 strpl r3, [r2, #0] + 8004024: 4770 bx lr + 8004026: b299 uxth r1, r3 + 8004028: b909 cbnz r1, 800402e <__lo0bits+0x2a> + 800402a: 2010 movs r0, #16 + 800402c: 0c1b lsrs r3, r3, #16 + 800402e: f013 0fff tst.w r3, #255 ; 0xff + 8004032: bf04 itt eq + 8004034: 0a1b lsreq r3, r3, #8 + 8004036: 3008 addeq r0, #8 + 8004038: 0719 lsls r1, r3, #28 + 800403a: bf04 itt eq + 800403c: 091b lsreq r3, r3, #4 + 800403e: 3004 addeq r0, #4 + 8004040: 0799 lsls r1, r3, #30 + 8004042: bf04 itt eq + 8004044: 089b lsreq r3, r3, #2 + 8004046: 3002 addeq r0, #2 + 8004048: 07d9 lsls r1, r3, #31 + 800404a: d403 bmi.n 8004054 <__lo0bits+0x50> + 800404c: 085b lsrs r3, r3, #1 + 800404e: f100 0001 add.w r0, r0, #1 + 8004052: d003 beq.n 800405c <__lo0bits+0x58> + 8004054: 6013 str r3, [r2, #0] + 8004056: 4770 bx lr + 8004058: 2000 movs r0, #0 + 800405a: 4770 bx lr + 800405c: 2020 movs r0, #32 + 800405e: 4770 bx lr + +08004060 <__i2b>: + 8004060: b510 push {r4, lr} + 8004062: 460c mov r4, r1 + 8004064: 2101 movs r1, #1 + 8004066: f7ff ff01 bl 8003e6c <_Balloc> + 800406a: 4602 mov r2, r0 + 800406c: b928 cbnz r0, 800407a <__i2b+0x1a> + 800406e: f44f 71a0 mov.w r1, #320 ; 0x140 + 8004072: 4b04 ldr r3, [pc, #16] ; (8004084 <__i2b+0x24>) + 8004074: 4804 ldr r0, [pc, #16] ; (8004088 <__i2b+0x28>) + 8004076: f000 fb3f bl 80046f8 <__assert_func> + 800407a: 2301 movs r3, #1 + 800407c: 6144 str r4, [r0, #20] + 800407e: 6103 str r3, [r0, #16] + 8004080: bd10 pop {r4, pc} + 8004082: bf00 nop + 8004084: 08005303 .word 0x08005303 + 8004088: 08005314 .word 0x08005314 + +0800408c <__multiply>: + 800408c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8004090: 4614 mov r4, r2 + 8004092: 690a ldr r2, [r1, #16] + 8004094: 6923 ldr r3, [r4, #16] + 8004096: 460d mov r5, r1 + 8004098: 429a cmp r2, r3 + 800409a: bfbe ittt lt + 800409c: 460b movlt r3, r1 + 800409e: 4625 movlt r5, r4 + 80040a0: 461c movlt r4, r3 + 80040a2: f8d5 a010 ldr.w sl, [r5, #16] + 80040a6: f8d4 9010 ldr.w r9, [r4, #16] + 80040aa: 68ab ldr r3, [r5, #8] + 80040ac: 6869 ldr r1, [r5, #4] + 80040ae: eb0a 0709 add.w r7, sl, r9 + 80040b2: 42bb cmp r3, r7 + 80040b4: b085 sub sp, #20 + 80040b6: bfb8 it lt + 80040b8: 3101 addlt r1, #1 + 80040ba: f7ff fed7 bl 8003e6c <_Balloc> + 80040be: b930 cbnz r0, 80040ce <__multiply+0x42> + 80040c0: 4602 mov r2, r0 + 80040c2: f240 115d movw r1, #349 ; 0x15d + 80040c6: 4b41 ldr r3, [pc, #260] ; (80041cc <__multiply+0x140>) + 80040c8: 4841 ldr r0, [pc, #260] ; (80041d0 <__multiply+0x144>) + 80040ca: f000 fb15 bl 80046f8 <__assert_func> + 80040ce: f100 0614 add.w r6, r0, #20 + 80040d2: 4633 mov r3, r6 + 80040d4: 2200 movs r2, #0 + 80040d6: eb06 0887 add.w r8, r6, r7, lsl #2 + 80040da: 4543 cmp r3, r8 + 80040dc: d31e bcc.n 800411c <__multiply+0x90> + 80040de: f105 0c14 add.w ip, r5, #20 + 80040e2: f104 0314 add.w r3, r4, #20 + 80040e6: eb0c 0c8a add.w ip, ip, sl, lsl #2 + 80040ea: eb03 0289 add.w r2, r3, r9, lsl #2 + 80040ee: 9202 str r2, [sp, #8] + 80040f0: ebac 0205 sub.w r2, ip, r5 + 80040f4: 3a15 subs r2, #21 + 80040f6: f022 0203 bic.w r2, r2, #3 + 80040fa: 3204 adds r2, #4 + 80040fc: f105 0115 add.w r1, r5, #21 + 8004100: 458c cmp ip, r1 + 8004102: bf38 it cc + 8004104: 2204 movcc r2, #4 + 8004106: 9201 str r2, [sp, #4] + 8004108: 9a02 ldr r2, [sp, #8] + 800410a: 9303 str r3, [sp, #12] + 800410c: 429a cmp r2, r3 + 800410e: d808 bhi.n 8004122 <__multiply+0x96> + 8004110: 2f00 cmp r7, #0 + 8004112: dc55 bgt.n 80041c0 <__multiply+0x134> + 8004114: 6107 str r7, [r0, #16] + 8004116: b005 add sp, #20 + 8004118: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800411c: f843 2b04 str.w r2, [r3], #4 + 8004120: e7db b.n 80040da <__multiply+0x4e> + 8004122: f8b3 a000 ldrh.w sl, [r3] + 8004126: f1ba 0f00 cmp.w sl, #0 + 800412a: d020 beq.n 800416e <__multiply+0xe2> + 800412c: 46b1 mov r9, r6 + 800412e: 2200 movs r2, #0 + 8004130: f105 0e14 add.w lr, r5, #20 + 8004134: f85e 4b04 ldr.w r4, [lr], #4 + 8004138: f8d9 b000 ldr.w fp, [r9] + 800413c: b2a1 uxth r1, r4 + 800413e: fa1f fb8b uxth.w fp, fp + 8004142: fb0a b101 mla r1, sl, r1, fp + 8004146: 4411 add r1, r2 + 8004148: f8d9 2000 ldr.w r2, [r9] + 800414c: 0c24 lsrs r4, r4, #16 + 800414e: 0c12 lsrs r2, r2, #16 + 8004150: fb0a 2404 mla r4, sl, r4, r2 + 8004154: eb04 4411 add.w r4, r4, r1, lsr #16 + 8004158: b289 uxth r1, r1 + 800415a: ea41 4104 orr.w r1, r1, r4, lsl #16 + 800415e: 45f4 cmp ip, lr + 8004160: ea4f 4214 mov.w r2, r4, lsr #16 + 8004164: f849 1b04 str.w r1, [r9], #4 + 8004168: d8e4 bhi.n 8004134 <__multiply+0xa8> + 800416a: 9901 ldr r1, [sp, #4] + 800416c: 5072 str r2, [r6, r1] + 800416e: 9a03 ldr r2, [sp, #12] + 8004170: 3304 adds r3, #4 + 8004172: f8b2 9002 ldrh.w r9, [r2, #2] + 8004176: f1b9 0f00 cmp.w r9, #0 + 800417a: d01f beq.n 80041bc <__multiply+0x130> + 800417c: 46b6 mov lr, r6 + 800417e: f04f 0a00 mov.w sl, #0 + 8004182: 6834 ldr r4, [r6, #0] + 8004184: f105 0114 add.w r1, r5, #20 + 8004188: 880a ldrh r2, [r1, #0] + 800418a: f8be b002 ldrh.w fp, [lr, #2] + 800418e: b2a4 uxth r4, r4 + 8004190: fb09 b202 mla r2, r9, r2, fp + 8004194: 4492 add sl, r2 + 8004196: ea44 440a orr.w r4, r4, sl, lsl #16 + 800419a: f84e 4b04 str.w r4, [lr], #4 + 800419e: f851 4b04 ldr.w r4, [r1], #4 + 80041a2: f8be 2000 ldrh.w r2, [lr] + 80041a6: 0c24 lsrs r4, r4, #16 + 80041a8: fb09 2404 mla r4, r9, r4, r2 + 80041ac: 458c cmp ip, r1 + 80041ae: eb04 441a add.w r4, r4, sl, lsr #16 + 80041b2: ea4f 4a14 mov.w sl, r4, lsr #16 + 80041b6: d8e7 bhi.n 8004188 <__multiply+0xfc> + 80041b8: 9a01 ldr r2, [sp, #4] + 80041ba: 50b4 str r4, [r6, r2] + 80041bc: 3604 adds r6, #4 + 80041be: e7a3 b.n 8004108 <__multiply+0x7c> + 80041c0: f858 3d04 ldr.w r3, [r8, #-4]! + 80041c4: 2b00 cmp r3, #0 + 80041c6: d1a5 bne.n 8004114 <__multiply+0x88> + 80041c8: 3f01 subs r7, #1 + 80041ca: e7a1 b.n 8004110 <__multiply+0x84> + 80041cc: 08005303 .word 0x08005303 + 80041d0: 08005314 .word 0x08005314 + +080041d4 <__pow5mult>: + 80041d4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 80041d8: 4615 mov r5, r2 + 80041da: f012 0203 ands.w r2, r2, #3 + 80041de: 4606 mov r6, r0 + 80041e0: 460f mov r7, r1 + 80041e2: d007 beq.n 80041f4 <__pow5mult+0x20> + 80041e4: 4c25 ldr r4, [pc, #148] ; (800427c <__pow5mult+0xa8>) + 80041e6: 3a01 subs r2, #1 + 80041e8: 2300 movs r3, #0 + 80041ea: f854 2022 ldr.w r2, [r4, r2, lsl #2] + 80041ee: f7ff fe9f bl 8003f30 <__multadd> + 80041f2: 4607 mov r7, r0 + 80041f4: 10ad asrs r5, r5, #2 + 80041f6: d03d beq.n 8004274 <__pow5mult+0xa0> + 80041f8: 6a74 ldr r4, [r6, #36] ; 0x24 + 80041fa: b97c cbnz r4, 800421c <__pow5mult+0x48> + 80041fc: 2010 movs r0, #16 + 80041fe: f7ff fe11 bl 8003e24 + 8004202: 4602 mov r2, r0 + 8004204: 6270 str r0, [r6, #36] ; 0x24 + 8004206: b928 cbnz r0, 8004214 <__pow5mult+0x40> + 8004208: f44f 71d7 mov.w r1, #430 ; 0x1ae + 800420c: 4b1c ldr r3, [pc, #112] ; (8004280 <__pow5mult+0xac>) + 800420e: 481d ldr r0, [pc, #116] ; (8004284 <__pow5mult+0xb0>) + 8004210: f000 fa72 bl 80046f8 <__assert_func> + 8004214: e9c0 4401 strd r4, r4, [r0, #4] + 8004218: 6004 str r4, [r0, #0] + 800421a: 60c4 str r4, [r0, #12] + 800421c: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 + 8004220: f8d8 4008 ldr.w r4, [r8, #8] + 8004224: b94c cbnz r4, 800423a <__pow5mult+0x66> + 8004226: f240 2171 movw r1, #625 ; 0x271 + 800422a: 4630 mov r0, r6 + 800422c: f7ff ff18 bl 8004060 <__i2b> + 8004230: 2300 movs r3, #0 + 8004232: 4604 mov r4, r0 + 8004234: f8c8 0008 str.w r0, [r8, #8] + 8004238: 6003 str r3, [r0, #0] + 800423a: f04f 0900 mov.w r9, #0 + 800423e: 07eb lsls r3, r5, #31 + 8004240: d50a bpl.n 8004258 <__pow5mult+0x84> + 8004242: 4639 mov r1, r7 + 8004244: 4622 mov r2, r4 + 8004246: 4630 mov r0, r6 + 8004248: f7ff ff20 bl 800408c <__multiply> + 800424c: 4680 mov r8, r0 + 800424e: 4639 mov r1, r7 + 8004250: 4630 mov r0, r6 + 8004252: f7ff fe4b bl 8003eec <_Bfree> + 8004256: 4647 mov r7, r8 + 8004258: 106d asrs r5, r5, #1 + 800425a: d00b beq.n 8004274 <__pow5mult+0xa0> + 800425c: 6820 ldr r0, [r4, #0] + 800425e: b938 cbnz r0, 8004270 <__pow5mult+0x9c> + 8004260: 4622 mov r2, r4 + 8004262: 4621 mov r1, r4 + 8004264: 4630 mov r0, r6 + 8004266: f7ff ff11 bl 800408c <__multiply> + 800426a: 6020 str r0, [r4, #0] + 800426c: f8c0 9000 str.w r9, [r0] + 8004270: 4604 mov r4, r0 + 8004272: e7e4 b.n 800423e <__pow5mult+0x6a> + 8004274: 4638 mov r0, r7 + 8004276: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800427a: bf00 nop + 800427c: 08005468 .word 0x08005468 + 8004280: 0800528d .word 0x0800528d + 8004284: 08005314 .word 0x08005314 + +08004288 <__lshift>: + 8004288: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800428c: 460c mov r4, r1 + 800428e: 4607 mov r7, r0 + 8004290: 4691 mov r9, r2 + 8004292: 6923 ldr r3, [r4, #16] + 8004294: 6849 ldr r1, [r1, #4] + 8004296: eb03 1862 add.w r8, r3, r2, asr #5 + 800429a: 68a3 ldr r3, [r4, #8] + 800429c: ea4f 1a62 mov.w sl, r2, asr #5 + 80042a0: f108 0601 add.w r6, r8, #1 + 80042a4: 42b3 cmp r3, r6 + 80042a6: db0b blt.n 80042c0 <__lshift+0x38> + 80042a8: 4638 mov r0, r7 + 80042aa: f7ff fddf bl 8003e6c <_Balloc> + 80042ae: 4605 mov r5, r0 + 80042b0: b948 cbnz r0, 80042c6 <__lshift+0x3e> + 80042b2: 4602 mov r2, r0 + 80042b4: f240 11d9 movw r1, #473 ; 0x1d9 + 80042b8: 4b27 ldr r3, [pc, #156] ; (8004358 <__lshift+0xd0>) + 80042ba: 4828 ldr r0, [pc, #160] ; (800435c <__lshift+0xd4>) + 80042bc: f000 fa1c bl 80046f8 <__assert_func> + 80042c0: 3101 adds r1, #1 + 80042c2: 005b lsls r3, r3, #1 + 80042c4: e7ee b.n 80042a4 <__lshift+0x1c> + 80042c6: 2300 movs r3, #0 + 80042c8: f100 0114 add.w r1, r0, #20 + 80042cc: f100 0210 add.w r2, r0, #16 + 80042d0: 4618 mov r0, r3 + 80042d2: 4553 cmp r3, sl + 80042d4: db33 blt.n 800433e <__lshift+0xb6> + 80042d6: 6920 ldr r0, [r4, #16] + 80042d8: ea2a 7aea bic.w sl, sl, sl, asr #31 + 80042dc: f104 0314 add.w r3, r4, #20 + 80042e0: f019 091f ands.w r9, r9, #31 + 80042e4: eb01 018a add.w r1, r1, sl, lsl #2 + 80042e8: eb03 0c80 add.w ip, r3, r0, lsl #2 + 80042ec: d02b beq.n 8004346 <__lshift+0xbe> + 80042ee: 468a mov sl, r1 + 80042f0: 2200 movs r2, #0 + 80042f2: f1c9 0e20 rsb lr, r9, #32 + 80042f6: 6818 ldr r0, [r3, #0] + 80042f8: fa00 f009 lsl.w r0, r0, r9 + 80042fc: 4302 orrs r2, r0 + 80042fe: f84a 2b04 str.w r2, [sl], #4 + 8004302: f853 2b04 ldr.w r2, [r3], #4 + 8004306: 459c cmp ip, r3 + 8004308: fa22 f20e lsr.w r2, r2, lr + 800430c: d8f3 bhi.n 80042f6 <__lshift+0x6e> + 800430e: ebac 0304 sub.w r3, ip, r4 + 8004312: 3b15 subs r3, #21 + 8004314: f023 0303 bic.w r3, r3, #3 + 8004318: 3304 adds r3, #4 + 800431a: f104 0015 add.w r0, r4, #21 + 800431e: 4584 cmp ip, r0 + 8004320: bf38 it cc + 8004322: 2304 movcc r3, #4 + 8004324: 50ca str r2, [r1, r3] + 8004326: b10a cbz r2, 800432c <__lshift+0xa4> + 8004328: f108 0602 add.w r6, r8, #2 + 800432c: 3e01 subs r6, #1 + 800432e: 4638 mov r0, r7 + 8004330: 4621 mov r1, r4 + 8004332: 612e str r6, [r5, #16] + 8004334: f7ff fdda bl 8003eec <_Bfree> + 8004338: 4628 mov r0, r5 + 800433a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800433e: f842 0f04 str.w r0, [r2, #4]! + 8004342: 3301 adds r3, #1 + 8004344: e7c5 b.n 80042d2 <__lshift+0x4a> + 8004346: 3904 subs r1, #4 + 8004348: f853 2b04 ldr.w r2, [r3], #4 + 800434c: 459c cmp ip, r3 + 800434e: f841 2f04 str.w r2, [r1, #4]! + 8004352: d8f9 bhi.n 8004348 <__lshift+0xc0> + 8004354: e7ea b.n 800432c <__lshift+0xa4> + 8004356: bf00 nop + 8004358: 08005303 .word 0x08005303 + 800435c: 08005314 .word 0x08005314 + +08004360 <__mcmp>: + 8004360: 4603 mov r3, r0 + 8004362: 690a ldr r2, [r1, #16] + 8004364: 6900 ldr r0, [r0, #16] + 8004366: b530 push {r4, r5, lr} + 8004368: 1a80 subs r0, r0, r2 + 800436a: d10d bne.n 8004388 <__mcmp+0x28> + 800436c: 3314 adds r3, #20 + 800436e: 3114 adds r1, #20 + 8004370: eb03 0482 add.w r4, r3, r2, lsl #2 + 8004374: eb01 0182 add.w r1, r1, r2, lsl #2 + 8004378: f854 5d04 ldr.w r5, [r4, #-4]! + 800437c: f851 2d04 ldr.w r2, [r1, #-4]! + 8004380: 4295 cmp r5, r2 + 8004382: d002 beq.n 800438a <__mcmp+0x2a> + 8004384: d304 bcc.n 8004390 <__mcmp+0x30> + 8004386: 2001 movs r0, #1 + 8004388: bd30 pop {r4, r5, pc} + 800438a: 42a3 cmp r3, r4 + 800438c: d3f4 bcc.n 8004378 <__mcmp+0x18> + 800438e: e7fb b.n 8004388 <__mcmp+0x28> + 8004390: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8004394: e7f8 b.n 8004388 <__mcmp+0x28> + ... + +08004398 <__mdiff>: + 8004398: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800439c: 460c mov r4, r1 + 800439e: 4606 mov r6, r0 + 80043a0: 4611 mov r1, r2 + 80043a2: 4620 mov r0, r4 + 80043a4: 4692 mov sl, r2 + 80043a6: f7ff ffdb bl 8004360 <__mcmp> + 80043aa: 1e05 subs r5, r0, #0 + 80043ac: d111 bne.n 80043d2 <__mdiff+0x3a> + 80043ae: 4629 mov r1, r5 + 80043b0: 4630 mov r0, r6 + 80043b2: f7ff fd5b bl 8003e6c <_Balloc> + 80043b6: 4602 mov r2, r0 + 80043b8: b928 cbnz r0, 80043c6 <__mdiff+0x2e> + 80043ba: f240 2132 movw r1, #562 ; 0x232 + 80043be: 4b3c ldr r3, [pc, #240] ; (80044b0 <__mdiff+0x118>) + 80043c0: 483c ldr r0, [pc, #240] ; (80044b4 <__mdiff+0x11c>) + 80043c2: f000 f999 bl 80046f8 <__assert_func> + 80043c6: 2301 movs r3, #1 + 80043c8: e9c0 3504 strd r3, r5, [r0, #16] + 80043cc: 4610 mov r0, r2 + 80043ce: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80043d2: bfa4 itt ge + 80043d4: 4653 movge r3, sl + 80043d6: 46a2 movge sl, r4 + 80043d8: 4630 mov r0, r6 + 80043da: f8da 1004 ldr.w r1, [sl, #4] + 80043de: bfa6 itte ge + 80043e0: 461c movge r4, r3 + 80043e2: 2500 movge r5, #0 + 80043e4: 2501 movlt r5, #1 + 80043e6: f7ff fd41 bl 8003e6c <_Balloc> + 80043ea: 4602 mov r2, r0 + 80043ec: b918 cbnz r0, 80043f6 <__mdiff+0x5e> + 80043ee: f44f 7110 mov.w r1, #576 ; 0x240 + 80043f2: 4b2f ldr r3, [pc, #188] ; (80044b0 <__mdiff+0x118>) + 80043f4: e7e4 b.n 80043c0 <__mdiff+0x28> + 80043f6: f100 0814 add.w r8, r0, #20 + 80043fa: f8da 7010 ldr.w r7, [sl, #16] + 80043fe: 60c5 str r5, [r0, #12] + 8004400: f04f 0c00 mov.w ip, #0 + 8004404: f10a 0514 add.w r5, sl, #20 + 8004408: f10a 0010 add.w r0, sl, #16 + 800440c: 46c2 mov sl, r8 + 800440e: 6926 ldr r6, [r4, #16] + 8004410: f104 0914 add.w r9, r4, #20 + 8004414: eb05 0e87 add.w lr, r5, r7, lsl #2 + 8004418: eb09 0686 add.w r6, r9, r6, lsl #2 + 800441c: f850 bf04 ldr.w fp, [r0, #4]! + 8004420: f859 3b04 ldr.w r3, [r9], #4 + 8004424: fa1f f18b uxth.w r1, fp + 8004428: 4461 add r1, ip + 800442a: fa1f fc83 uxth.w ip, r3 + 800442e: 0c1b lsrs r3, r3, #16 + 8004430: eba1 010c sub.w r1, r1, ip + 8004434: ebc3 431b rsb r3, r3, fp, lsr #16 + 8004438: eb03 4321 add.w r3, r3, r1, asr #16 + 800443c: b289 uxth r1, r1 + 800443e: ea4f 4c23 mov.w ip, r3, asr #16 + 8004442: 454e cmp r6, r9 + 8004444: ea41 4303 orr.w r3, r1, r3, lsl #16 + 8004448: f84a 3b04 str.w r3, [sl], #4 + 800444c: d8e6 bhi.n 800441c <__mdiff+0x84> + 800444e: 1b33 subs r3, r6, r4 + 8004450: 3b15 subs r3, #21 + 8004452: f023 0303 bic.w r3, r3, #3 + 8004456: 3415 adds r4, #21 + 8004458: 3304 adds r3, #4 + 800445a: 42a6 cmp r6, r4 + 800445c: bf38 it cc + 800445e: 2304 movcc r3, #4 + 8004460: 441d add r5, r3 + 8004462: 4443 add r3, r8 + 8004464: 461e mov r6, r3 + 8004466: 462c mov r4, r5 + 8004468: 4574 cmp r4, lr + 800446a: d30e bcc.n 800448a <__mdiff+0xf2> + 800446c: f10e 0103 add.w r1, lr, #3 + 8004470: 1b49 subs r1, r1, r5 + 8004472: f021 0103 bic.w r1, r1, #3 + 8004476: 3d03 subs r5, #3 + 8004478: 45ae cmp lr, r5 + 800447a: bf38 it cc + 800447c: 2100 movcc r1, #0 + 800447e: 4419 add r1, r3 + 8004480: f851 3d04 ldr.w r3, [r1, #-4]! + 8004484: b18b cbz r3, 80044aa <__mdiff+0x112> + 8004486: 6117 str r7, [r2, #16] + 8004488: e7a0 b.n 80043cc <__mdiff+0x34> + 800448a: f854 8b04 ldr.w r8, [r4], #4 + 800448e: fa1f f188 uxth.w r1, r8 + 8004492: 4461 add r1, ip + 8004494: 1408 asrs r0, r1, #16 + 8004496: eb00 4018 add.w r0, r0, r8, lsr #16 + 800449a: b289 uxth r1, r1 + 800449c: ea41 4100 orr.w r1, r1, r0, lsl #16 + 80044a0: ea4f 4c20 mov.w ip, r0, asr #16 + 80044a4: f846 1b04 str.w r1, [r6], #4 + 80044a8: e7de b.n 8004468 <__mdiff+0xd0> + 80044aa: 3f01 subs r7, #1 + 80044ac: e7e8 b.n 8004480 <__mdiff+0xe8> + 80044ae: bf00 nop + 80044b0: 08005303 .word 0x08005303 + 80044b4: 08005314 .word 0x08005314 + +080044b8 <__d2b>: + 80044b8: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 80044bc: 2101 movs r1, #1 + 80044be: e9dd 7608 ldrd r7, r6, [sp, #32] + 80044c2: 4690 mov r8, r2 + 80044c4: 461d mov r5, r3 + 80044c6: f7ff fcd1 bl 8003e6c <_Balloc> + 80044ca: 4604 mov r4, r0 + 80044cc: b930 cbnz r0, 80044dc <__d2b+0x24> + 80044ce: 4602 mov r2, r0 + 80044d0: f240 310a movw r1, #778 ; 0x30a + 80044d4: 4b24 ldr r3, [pc, #144] ; (8004568 <__d2b+0xb0>) + 80044d6: 4825 ldr r0, [pc, #148] ; (800456c <__d2b+0xb4>) + 80044d8: f000 f90e bl 80046f8 <__assert_func> + 80044dc: f3c5 0313 ubfx r3, r5, #0, #20 + 80044e0: f3c5 550a ubfx r5, r5, #20, #11 + 80044e4: bb2d cbnz r5, 8004532 <__d2b+0x7a> + 80044e6: 9301 str r3, [sp, #4] + 80044e8: f1b8 0300 subs.w r3, r8, #0 + 80044ec: d026 beq.n 800453c <__d2b+0x84> + 80044ee: 4668 mov r0, sp + 80044f0: 9300 str r3, [sp, #0] + 80044f2: f7ff fd87 bl 8004004 <__lo0bits> + 80044f6: 9900 ldr r1, [sp, #0] + 80044f8: b1f0 cbz r0, 8004538 <__d2b+0x80> + 80044fa: 9a01 ldr r2, [sp, #4] + 80044fc: f1c0 0320 rsb r3, r0, #32 + 8004500: fa02 f303 lsl.w r3, r2, r3 + 8004504: 430b orrs r3, r1 + 8004506: 40c2 lsrs r2, r0 + 8004508: 6163 str r3, [r4, #20] + 800450a: 9201 str r2, [sp, #4] + 800450c: 9b01 ldr r3, [sp, #4] + 800450e: 2b00 cmp r3, #0 + 8004510: bf14 ite ne + 8004512: 2102 movne r1, #2 + 8004514: 2101 moveq r1, #1 + 8004516: 61a3 str r3, [r4, #24] + 8004518: 6121 str r1, [r4, #16] + 800451a: b1c5 cbz r5, 800454e <__d2b+0x96> + 800451c: f2a5 4533 subw r5, r5, #1075 ; 0x433 + 8004520: 4405 add r5, r0 + 8004522: f1c0 0035 rsb r0, r0, #53 ; 0x35 + 8004526: 603d str r5, [r7, #0] + 8004528: 6030 str r0, [r6, #0] + 800452a: 4620 mov r0, r4 + 800452c: b002 add sp, #8 + 800452e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8004532: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8004536: e7d6 b.n 80044e6 <__d2b+0x2e> + 8004538: 6161 str r1, [r4, #20] + 800453a: e7e7 b.n 800450c <__d2b+0x54> + 800453c: a801 add r0, sp, #4 + 800453e: f7ff fd61 bl 8004004 <__lo0bits> + 8004542: 2101 movs r1, #1 + 8004544: 9b01 ldr r3, [sp, #4] + 8004546: 6121 str r1, [r4, #16] + 8004548: 6163 str r3, [r4, #20] + 800454a: 3020 adds r0, #32 + 800454c: e7e5 b.n 800451a <__d2b+0x62> + 800454e: eb04 0381 add.w r3, r4, r1, lsl #2 + 8004552: f2a0 4032 subw r0, r0, #1074 ; 0x432 + 8004556: 6038 str r0, [r7, #0] + 8004558: 6918 ldr r0, [r3, #16] + 800455a: f7ff fd33 bl 8003fc4 <__hi0bits> + 800455e: ebc0 1141 rsb r1, r0, r1, lsl #5 + 8004562: 6031 str r1, [r6, #0] + 8004564: e7e1 b.n 800452a <__d2b+0x72> + 8004566: bf00 nop + 8004568: 08005303 .word 0x08005303 + 800456c: 08005314 .word 0x08005314 + +08004570 <_calloc_r>: + 8004570: b538 push {r3, r4, r5, lr} + 8004572: fb02 f501 mul.w r5, r2, r1 + 8004576: 4629 mov r1, r5 + 8004578: f000 f854 bl 8004624 <_malloc_r> + 800457c: 4604 mov r4, r0 + 800457e: b118 cbz r0, 8004588 <_calloc_r+0x18> + 8004580: 462a mov r2, r5 + 8004582: 2100 movs r1, #0 + 8004584: f7fe f966 bl 8002854 + 8004588: 4620 mov r0, r4 + 800458a: bd38 pop {r3, r4, r5, pc} + +0800458c <_free_r>: + 800458c: b538 push {r3, r4, r5, lr} + 800458e: 4605 mov r5, r0 + 8004590: 2900 cmp r1, #0 + 8004592: d043 beq.n 800461c <_free_r+0x90> + 8004594: f851 3c04 ldr.w r3, [r1, #-4] + 8004598: 1f0c subs r4, r1, #4 + 800459a: 2b00 cmp r3, #0 + 800459c: bfb8 it lt + 800459e: 18e4 addlt r4, r4, r3 + 80045a0: f000 f8ec bl 800477c <__malloc_lock> + 80045a4: 4a1e ldr r2, [pc, #120] ; (8004620 <_free_r+0x94>) + 80045a6: 6813 ldr r3, [r2, #0] + 80045a8: 4610 mov r0, r2 + 80045aa: b933 cbnz r3, 80045ba <_free_r+0x2e> + 80045ac: 6063 str r3, [r4, #4] + 80045ae: 6014 str r4, [r2, #0] + 80045b0: 4628 mov r0, r5 + 80045b2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 80045b6: f000 b8e7 b.w 8004788 <__malloc_unlock> + 80045ba: 42a3 cmp r3, r4 + 80045bc: d90a bls.n 80045d4 <_free_r+0x48> + 80045be: 6821 ldr r1, [r4, #0] + 80045c0: 1862 adds r2, r4, r1 + 80045c2: 4293 cmp r3, r2 + 80045c4: bf01 itttt eq + 80045c6: 681a ldreq r2, [r3, #0] + 80045c8: 685b ldreq r3, [r3, #4] + 80045ca: 1852 addeq r2, r2, r1 + 80045cc: 6022 streq r2, [r4, #0] + 80045ce: 6063 str r3, [r4, #4] + 80045d0: 6004 str r4, [r0, #0] + 80045d2: e7ed b.n 80045b0 <_free_r+0x24> + 80045d4: 461a mov r2, r3 + 80045d6: 685b ldr r3, [r3, #4] + 80045d8: b10b cbz r3, 80045de <_free_r+0x52> + 80045da: 42a3 cmp r3, r4 + 80045dc: d9fa bls.n 80045d4 <_free_r+0x48> + 80045de: 6811 ldr r1, [r2, #0] + 80045e0: 1850 adds r0, r2, r1 + 80045e2: 42a0 cmp r0, r4 + 80045e4: d10b bne.n 80045fe <_free_r+0x72> + 80045e6: 6820 ldr r0, [r4, #0] + 80045e8: 4401 add r1, r0 + 80045ea: 1850 adds r0, r2, r1 + 80045ec: 4283 cmp r3, r0 + 80045ee: 6011 str r1, [r2, #0] + 80045f0: d1de bne.n 80045b0 <_free_r+0x24> + 80045f2: 6818 ldr r0, [r3, #0] + 80045f4: 685b ldr r3, [r3, #4] + 80045f6: 4401 add r1, r0 + 80045f8: 6011 str r1, [r2, #0] + 80045fa: 6053 str r3, [r2, #4] + 80045fc: e7d8 b.n 80045b0 <_free_r+0x24> + 80045fe: d902 bls.n 8004606 <_free_r+0x7a> + 8004600: 230c movs r3, #12 + 8004602: 602b str r3, [r5, #0] + 8004604: e7d4 b.n 80045b0 <_free_r+0x24> + 8004606: 6820 ldr r0, [r4, #0] + 8004608: 1821 adds r1, r4, r0 + 800460a: 428b cmp r3, r1 + 800460c: bf01 itttt eq + 800460e: 6819 ldreq r1, [r3, #0] + 8004610: 685b ldreq r3, [r3, #4] + 8004612: 1809 addeq r1, r1, r0 + 8004614: 6021 streq r1, [r4, #0] + 8004616: 6063 str r3, [r4, #4] + 8004618: 6054 str r4, [r2, #4] + 800461a: e7c9 b.n 80045b0 <_free_r+0x24> + 800461c: bd38 pop {r3, r4, r5, pc} + 800461e: bf00 nop + 8004620: 20000200 .word 0x20000200 + +08004624 <_malloc_r>: + 8004624: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004626: 1ccd adds r5, r1, #3 + 8004628: f025 0503 bic.w r5, r5, #3 + 800462c: 3508 adds r5, #8 + 800462e: 2d0c cmp r5, #12 + 8004630: bf38 it cc + 8004632: 250c movcc r5, #12 + 8004634: 2d00 cmp r5, #0 + 8004636: 4606 mov r6, r0 + 8004638: db01 blt.n 800463e <_malloc_r+0x1a> + 800463a: 42a9 cmp r1, r5 + 800463c: d903 bls.n 8004646 <_malloc_r+0x22> + 800463e: 230c movs r3, #12 + 8004640: 6033 str r3, [r6, #0] + 8004642: 2000 movs r0, #0 + 8004644: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004646: f000 f899 bl 800477c <__malloc_lock> + 800464a: 4921 ldr r1, [pc, #132] ; (80046d0 <_malloc_r+0xac>) + 800464c: 680a ldr r2, [r1, #0] + 800464e: 4614 mov r4, r2 + 8004650: b99c cbnz r4, 800467a <_malloc_r+0x56> + 8004652: 4f20 ldr r7, [pc, #128] ; (80046d4 <_malloc_r+0xb0>) + 8004654: 683b ldr r3, [r7, #0] + 8004656: b923 cbnz r3, 8004662 <_malloc_r+0x3e> + 8004658: 4621 mov r1, r4 + 800465a: 4630 mov r0, r6 + 800465c: f000 f83c bl 80046d8 <_sbrk_r> + 8004660: 6038 str r0, [r7, #0] + 8004662: 4629 mov r1, r5 + 8004664: 4630 mov r0, r6 + 8004666: f000 f837 bl 80046d8 <_sbrk_r> + 800466a: 1c43 adds r3, r0, #1 + 800466c: d123 bne.n 80046b6 <_malloc_r+0x92> + 800466e: 230c movs r3, #12 + 8004670: 4630 mov r0, r6 + 8004672: 6033 str r3, [r6, #0] + 8004674: f000 f888 bl 8004788 <__malloc_unlock> + 8004678: e7e3 b.n 8004642 <_malloc_r+0x1e> + 800467a: 6823 ldr r3, [r4, #0] + 800467c: 1b5b subs r3, r3, r5 + 800467e: d417 bmi.n 80046b0 <_malloc_r+0x8c> + 8004680: 2b0b cmp r3, #11 + 8004682: d903 bls.n 800468c <_malloc_r+0x68> + 8004684: 6023 str r3, [r4, #0] + 8004686: 441c add r4, r3 + 8004688: 6025 str r5, [r4, #0] + 800468a: e004 b.n 8004696 <_malloc_r+0x72> + 800468c: 6863 ldr r3, [r4, #4] + 800468e: 42a2 cmp r2, r4 + 8004690: bf0c ite eq + 8004692: 600b streq r3, [r1, #0] + 8004694: 6053 strne r3, [r2, #4] + 8004696: 4630 mov r0, r6 + 8004698: f000 f876 bl 8004788 <__malloc_unlock> + 800469c: f104 000b add.w r0, r4, #11 + 80046a0: 1d23 adds r3, r4, #4 + 80046a2: f020 0007 bic.w r0, r0, #7 + 80046a6: 1ac2 subs r2, r0, r3 + 80046a8: d0cc beq.n 8004644 <_malloc_r+0x20> + 80046aa: 1a1b subs r3, r3, r0 + 80046ac: 50a3 str r3, [r4, r2] + 80046ae: e7c9 b.n 8004644 <_malloc_r+0x20> + 80046b0: 4622 mov r2, r4 + 80046b2: 6864 ldr r4, [r4, #4] + 80046b4: e7cc b.n 8004650 <_malloc_r+0x2c> + 80046b6: 1cc4 adds r4, r0, #3 + 80046b8: f024 0403 bic.w r4, r4, #3 + 80046bc: 42a0 cmp r0, r4 + 80046be: d0e3 beq.n 8004688 <_malloc_r+0x64> + 80046c0: 1a21 subs r1, r4, r0 + 80046c2: 4630 mov r0, r6 + 80046c4: f000 f808 bl 80046d8 <_sbrk_r> + 80046c8: 3001 adds r0, #1 + 80046ca: d1dd bne.n 8004688 <_malloc_r+0x64> + 80046cc: e7cf b.n 800466e <_malloc_r+0x4a> + 80046ce: bf00 nop + 80046d0: 20000200 .word 0x20000200 + 80046d4: 20000204 .word 0x20000204 + +080046d8 <_sbrk_r>: + 80046d8: b538 push {r3, r4, r5, lr} + 80046da: 2300 movs r3, #0 + 80046dc: 4d05 ldr r5, [pc, #20] ; (80046f4 <_sbrk_r+0x1c>) + 80046de: 4604 mov r4, r0 + 80046e0: 4608 mov r0, r1 + 80046e2: 602b str r3, [r5, #0] + 80046e4: f7fc fc90 bl 8001008 <_sbrk> + 80046e8: 1c43 adds r3, r0, #1 + 80046ea: d102 bne.n 80046f2 <_sbrk_r+0x1a> + 80046ec: 682b ldr r3, [r5, #0] + 80046ee: b103 cbz r3, 80046f2 <_sbrk_r+0x1a> + 80046f0: 6023 str r3, [r4, #0] + 80046f2: bd38 pop {r3, r4, r5, pc} + 80046f4: 20000260 .word 0x20000260 + +080046f8 <__assert_func>: + 80046f8: b51f push {r0, r1, r2, r3, r4, lr} + 80046fa: 4614 mov r4, r2 + 80046fc: 461a mov r2, r3 + 80046fe: 4b09 ldr r3, [pc, #36] ; (8004724 <__assert_func+0x2c>) + 8004700: 4605 mov r5, r0 + 8004702: 681b ldr r3, [r3, #0] + 8004704: 68d8 ldr r0, [r3, #12] + 8004706: b14c cbz r4, 800471c <__assert_func+0x24> + 8004708: 4b07 ldr r3, [pc, #28] ; (8004728 <__assert_func+0x30>) + 800470a: e9cd 3401 strd r3, r4, [sp, #4] + 800470e: 9100 str r1, [sp, #0] + 8004710: 462b mov r3, r5 + 8004712: 4906 ldr r1, [pc, #24] ; (800472c <__assert_func+0x34>) + 8004714: f000 f80e bl 8004734 + 8004718: f000 fa62 bl 8004be0 + 800471c: 4b04 ldr r3, [pc, #16] ; (8004730 <__assert_func+0x38>) + 800471e: 461c mov r4, r3 + 8004720: e7f3 b.n 800470a <__assert_func+0x12> + 8004722: bf00 nop + 8004724: 2000000c .word 0x2000000c + 8004728: 08005474 .word 0x08005474 + 800472c: 08005481 .word 0x08005481 + 8004730: 080054af .word 0x080054af + +08004734 : + 8004734: b40e push {r1, r2, r3} + 8004736: b503 push {r0, r1, lr} + 8004738: 4601 mov r1, r0 + 800473a: ab03 add r3, sp, #12 + 800473c: 4805 ldr r0, [pc, #20] ; (8004754 ) + 800473e: f853 2b04 ldr.w r2, [r3], #4 + 8004742: 6800 ldr r0, [r0, #0] + 8004744: 9301 str r3, [sp, #4] + 8004746: f000 f84d bl 80047e4 <_vfiprintf_r> + 800474a: b002 add sp, #8 + 800474c: f85d eb04 ldr.w lr, [sp], #4 + 8004750: b003 add sp, #12 + 8004752: 4770 bx lr + 8004754: 2000000c .word 0x2000000c + +08004758 <__ascii_mbtowc>: + 8004758: b082 sub sp, #8 + 800475a: b901 cbnz r1, 800475e <__ascii_mbtowc+0x6> + 800475c: a901 add r1, sp, #4 + 800475e: b142 cbz r2, 8004772 <__ascii_mbtowc+0x1a> + 8004760: b14b cbz r3, 8004776 <__ascii_mbtowc+0x1e> + 8004762: 7813 ldrb r3, [r2, #0] + 8004764: 600b str r3, [r1, #0] + 8004766: 7812 ldrb r2, [r2, #0] + 8004768: 1e10 subs r0, r2, #0 + 800476a: bf18 it ne + 800476c: 2001 movne r0, #1 + 800476e: b002 add sp, #8 + 8004770: 4770 bx lr + 8004772: 4610 mov r0, r2 + 8004774: e7fb b.n 800476e <__ascii_mbtowc+0x16> + 8004776: f06f 0001 mvn.w r0, #1 + 800477a: e7f8 b.n 800476e <__ascii_mbtowc+0x16> + +0800477c <__malloc_lock>: + 800477c: 4801 ldr r0, [pc, #4] ; (8004784 <__malloc_lock+0x8>) + 800477e: f000 bbef b.w 8004f60 <__retarget_lock_acquire_recursive> + 8004782: bf00 nop + 8004784: 20000268 .word 0x20000268 + +08004788 <__malloc_unlock>: + 8004788: 4801 ldr r0, [pc, #4] ; (8004790 <__malloc_unlock+0x8>) + 800478a: f000 bbea b.w 8004f62 <__retarget_lock_release_recursive> + 800478e: bf00 nop + 8004790: 20000268 .word 0x20000268 + +08004794 <__sfputc_r>: + 8004794: 6893 ldr r3, [r2, #8] + 8004796: b410 push {r4} + 8004798: 3b01 subs r3, #1 + 800479a: 2b00 cmp r3, #0 + 800479c: 6093 str r3, [r2, #8] + 800479e: da07 bge.n 80047b0 <__sfputc_r+0x1c> + 80047a0: 6994 ldr r4, [r2, #24] + 80047a2: 42a3 cmp r3, r4 + 80047a4: db01 blt.n 80047aa <__sfputc_r+0x16> + 80047a6: 290a cmp r1, #10 + 80047a8: d102 bne.n 80047b0 <__sfputc_r+0x1c> + 80047aa: bc10 pop {r4} + 80047ac: f000 b94a b.w 8004a44 <__swbuf_r> + 80047b0: 6813 ldr r3, [r2, #0] + 80047b2: 1c58 adds r0, r3, #1 + 80047b4: 6010 str r0, [r2, #0] + 80047b6: 7019 strb r1, [r3, #0] + 80047b8: 4608 mov r0, r1 + 80047ba: bc10 pop {r4} + 80047bc: 4770 bx lr + +080047be <__sfputs_r>: + 80047be: b5f8 push {r3, r4, r5, r6, r7, lr} + 80047c0: 4606 mov r6, r0 + 80047c2: 460f mov r7, r1 + 80047c4: 4614 mov r4, r2 + 80047c6: 18d5 adds r5, r2, r3 + 80047c8: 42ac cmp r4, r5 + 80047ca: d101 bne.n 80047d0 <__sfputs_r+0x12> + 80047cc: 2000 movs r0, #0 + 80047ce: e007 b.n 80047e0 <__sfputs_r+0x22> + 80047d0: 463a mov r2, r7 + 80047d2: 4630 mov r0, r6 + 80047d4: f814 1b01 ldrb.w r1, [r4], #1 + 80047d8: f7ff ffdc bl 8004794 <__sfputc_r> + 80047dc: 1c43 adds r3, r0, #1 + 80047de: d1f3 bne.n 80047c8 <__sfputs_r+0xa> + 80047e0: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +080047e4 <_vfiprintf_r>: + 80047e4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80047e8: 460d mov r5, r1 + 80047ea: 4614 mov r4, r2 + 80047ec: 4698 mov r8, r3 + 80047ee: 4606 mov r6, r0 + 80047f0: b09d sub sp, #116 ; 0x74 + 80047f2: b118 cbz r0, 80047fc <_vfiprintf_r+0x18> + 80047f4: 6983 ldr r3, [r0, #24] + 80047f6: b90b cbnz r3, 80047fc <_vfiprintf_r+0x18> + 80047f8: f000 fb14 bl 8004e24 <__sinit> + 80047fc: 4b89 ldr r3, [pc, #548] ; (8004a24 <_vfiprintf_r+0x240>) + 80047fe: 429d cmp r5, r3 + 8004800: d11b bne.n 800483a <_vfiprintf_r+0x56> + 8004802: 6875 ldr r5, [r6, #4] + 8004804: 6e6b ldr r3, [r5, #100] ; 0x64 + 8004806: 07d9 lsls r1, r3, #31 + 8004808: d405 bmi.n 8004816 <_vfiprintf_r+0x32> + 800480a: 89ab ldrh r3, [r5, #12] + 800480c: 059a lsls r2, r3, #22 + 800480e: d402 bmi.n 8004816 <_vfiprintf_r+0x32> + 8004810: 6da8 ldr r0, [r5, #88] ; 0x58 + 8004812: f000 fba5 bl 8004f60 <__retarget_lock_acquire_recursive> + 8004816: 89ab ldrh r3, [r5, #12] + 8004818: 071b lsls r3, r3, #28 + 800481a: d501 bpl.n 8004820 <_vfiprintf_r+0x3c> + 800481c: 692b ldr r3, [r5, #16] + 800481e: b9eb cbnz r3, 800485c <_vfiprintf_r+0x78> + 8004820: 4629 mov r1, r5 + 8004822: 4630 mov r0, r6 + 8004824: f000 f96e bl 8004b04 <__swsetup_r> + 8004828: b1c0 cbz r0, 800485c <_vfiprintf_r+0x78> + 800482a: 6e6b ldr r3, [r5, #100] ; 0x64 + 800482c: 07dc lsls r4, r3, #31 + 800482e: d50e bpl.n 800484e <_vfiprintf_r+0x6a> + 8004830: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8004834: b01d add sp, #116 ; 0x74 + 8004836: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800483a: 4b7b ldr r3, [pc, #492] ; (8004a28 <_vfiprintf_r+0x244>) + 800483c: 429d cmp r5, r3 + 800483e: d101 bne.n 8004844 <_vfiprintf_r+0x60> + 8004840: 68b5 ldr r5, [r6, #8] + 8004842: e7df b.n 8004804 <_vfiprintf_r+0x20> + 8004844: 4b79 ldr r3, [pc, #484] ; (8004a2c <_vfiprintf_r+0x248>) + 8004846: 429d cmp r5, r3 + 8004848: bf08 it eq + 800484a: 68f5 ldreq r5, [r6, #12] + 800484c: e7da b.n 8004804 <_vfiprintf_r+0x20> + 800484e: 89ab ldrh r3, [r5, #12] + 8004850: 0598 lsls r0, r3, #22 + 8004852: d4ed bmi.n 8004830 <_vfiprintf_r+0x4c> + 8004854: 6da8 ldr r0, [r5, #88] ; 0x58 + 8004856: f000 fb84 bl 8004f62 <__retarget_lock_release_recursive> + 800485a: e7e9 b.n 8004830 <_vfiprintf_r+0x4c> + 800485c: 2300 movs r3, #0 + 800485e: 9309 str r3, [sp, #36] ; 0x24 + 8004860: 2320 movs r3, #32 + 8004862: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 8004866: 2330 movs r3, #48 ; 0x30 + 8004868: f04f 0901 mov.w r9, #1 + 800486c: f8cd 800c str.w r8, [sp, #12] + 8004870: f8df 81bc ldr.w r8, [pc, #444] ; 8004a30 <_vfiprintf_r+0x24c> + 8004874: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 8004878: 4623 mov r3, r4 + 800487a: 469a mov sl, r3 + 800487c: f813 2b01 ldrb.w r2, [r3], #1 + 8004880: b10a cbz r2, 8004886 <_vfiprintf_r+0xa2> + 8004882: 2a25 cmp r2, #37 ; 0x25 + 8004884: d1f9 bne.n 800487a <_vfiprintf_r+0x96> + 8004886: ebba 0b04 subs.w fp, sl, r4 + 800488a: d00b beq.n 80048a4 <_vfiprintf_r+0xc0> + 800488c: 465b mov r3, fp + 800488e: 4622 mov r2, r4 + 8004890: 4629 mov r1, r5 + 8004892: 4630 mov r0, r6 + 8004894: f7ff ff93 bl 80047be <__sfputs_r> + 8004898: 3001 adds r0, #1 + 800489a: f000 80aa beq.w 80049f2 <_vfiprintf_r+0x20e> + 800489e: 9a09 ldr r2, [sp, #36] ; 0x24 + 80048a0: 445a add r2, fp + 80048a2: 9209 str r2, [sp, #36] ; 0x24 + 80048a4: f89a 3000 ldrb.w r3, [sl] + 80048a8: 2b00 cmp r3, #0 + 80048aa: f000 80a2 beq.w 80049f2 <_vfiprintf_r+0x20e> + 80048ae: 2300 movs r3, #0 + 80048b0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80048b4: e9cd 2305 strd r2, r3, [sp, #20] + 80048b8: f10a 0a01 add.w sl, sl, #1 + 80048bc: 9304 str r3, [sp, #16] + 80048be: 9307 str r3, [sp, #28] + 80048c0: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 80048c4: 931a str r3, [sp, #104] ; 0x68 + 80048c6: 4654 mov r4, sl + 80048c8: 2205 movs r2, #5 + 80048ca: f814 1b01 ldrb.w r1, [r4], #1 + 80048ce: 4858 ldr r0, [pc, #352] ; (8004a30 <_vfiprintf_r+0x24c>) + 80048d0: f7ff fab0 bl 8003e34 + 80048d4: 9a04 ldr r2, [sp, #16] + 80048d6: b9d8 cbnz r0, 8004910 <_vfiprintf_r+0x12c> + 80048d8: 06d1 lsls r1, r2, #27 + 80048da: bf44 itt mi + 80048dc: 2320 movmi r3, #32 + 80048de: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80048e2: 0713 lsls r3, r2, #28 + 80048e4: bf44 itt mi + 80048e6: 232b movmi r3, #43 ; 0x2b + 80048e8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80048ec: f89a 3000 ldrb.w r3, [sl] + 80048f0: 2b2a cmp r3, #42 ; 0x2a + 80048f2: d015 beq.n 8004920 <_vfiprintf_r+0x13c> + 80048f4: 4654 mov r4, sl + 80048f6: 2000 movs r0, #0 + 80048f8: f04f 0c0a mov.w ip, #10 + 80048fc: 9a07 ldr r2, [sp, #28] + 80048fe: 4621 mov r1, r4 + 8004900: f811 3b01 ldrb.w r3, [r1], #1 + 8004904: 3b30 subs r3, #48 ; 0x30 + 8004906: 2b09 cmp r3, #9 + 8004908: d94e bls.n 80049a8 <_vfiprintf_r+0x1c4> + 800490a: b1b0 cbz r0, 800493a <_vfiprintf_r+0x156> + 800490c: 9207 str r2, [sp, #28] + 800490e: e014 b.n 800493a <_vfiprintf_r+0x156> + 8004910: eba0 0308 sub.w r3, r0, r8 + 8004914: fa09 f303 lsl.w r3, r9, r3 + 8004918: 4313 orrs r3, r2 + 800491a: 46a2 mov sl, r4 + 800491c: 9304 str r3, [sp, #16] + 800491e: e7d2 b.n 80048c6 <_vfiprintf_r+0xe2> + 8004920: 9b03 ldr r3, [sp, #12] + 8004922: 1d19 adds r1, r3, #4 + 8004924: 681b ldr r3, [r3, #0] + 8004926: 9103 str r1, [sp, #12] + 8004928: 2b00 cmp r3, #0 + 800492a: bfbb ittet lt + 800492c: 425b neglt r3, r3 + 800492e: f042 0202 orrlt.w r2, r2, #2 + 8004932: 9307 strge r3, [sp, #28] + 8004934: 9307 strlt r3, [sp, #28] + 8004936: bfb8 it lt + 8004938: 9204 strlt r2, [sp, #16] + 800493a: 7823 ldrb r3, [r4, #0] + 800493c: 2b2e cmp r3, #46 ; 0x2e + 800493e: d10c bne.n 800495a <_vfiprintf_r+0x176> + 8004940: 7863 ldrb r3, [r4, #1] + 8004942: 2b2a cmp r3, #42 ; 0x2a + 8004944: d135 bne.n 80049b2 <_vfiprintf_r+0x1ce> + 8004946: 9b03 ldr r3, [sp, #12] + 8004948: 3402 adds r4, #2 + 800494a: 1d1a adds r2, r3, #4 + 800494c: 681b ldr r3, [r3, #0] + 800494e: 9203 str r2, [sp, #12] + 8004950: 2b00 cmp r3, #0 + 8004952: bfb8 it lt + 8004954: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff + 8004958: 9305 str r3, [sp, #20] + 800495a: f8df a0e4 ldr.w sl, [pc, #228] ; 8004a40 <_vfiprintf_r+0x25c> + 800495e: 2203 movs r2, #3 + 8004960: 4650 mov r0, sl + 8004962: 7821 ldrb r1, [r4, #0] + 8004964: f7ff fa66 bl 8003e34 + 8004968: b140 cbz r0, 800497c <_vfiprintf_r+0x198> + 800496a: 2340 movs r3, #64 ; 0x40 + 800496c: eba0 000a sub.w r0, r0, sl + 8004970: fa03 f000 lsl.w r0, r3, r0 + 8004974: 9b04 ldr r3, [sp, #16] + 8004976: 3401 adds r4, #1 + 8004978: 4303 orrs r3, r0 + 800497a: 9304 str r3, [sp, #16] + 800497c: f814 1b01 ldrb.w r1, [r4], #1 + 8004980: 2206 movs r2, #6 + 8004982: 482c ldr r0, [pc, #176] ; (8004a34 <_vfiprintf_r+0x250>) + 8004984: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 8004988: f7ff fa54 bl 8003e34 + 800498c: 2800 cmp r0, #0 + 800498e: d03f beq.n 8004a10 <_vfiprintf_r+0x22c> + 8004990: 4b29 ldr r3, [pc, #164] ; (8004a38 <_vfiprintf_r+0x254>) + 8004992: bb1b cbnz r3, 80049dc <_vfiprintf_r+0x1f8> + 8004994: 9b03 ldr r3, [sp, #12] + 8004996: 3307 adds r3, #7 + 8004998: f023 0307 bic.w r3, r3, #7 + 800499c: 3308 adds r3, #8 + 800499e: 9303 str r3, [sp, #12] + 80049a0: 9b09 ldr r3, [sp, #36] ; 0x24 + 80049a2: 443b add r3, r7 + 80049a4: 9309 str r3, [sp, #36] ; 0x24 + 80049a6: e767 b.n 8004878 <_vfiprintf_r+0x94> + 80049a8: 460c mov r4, r1 + 80049aa: 2001 movs r0, #1 + 80049ac: fb0c 3202 mla r2, ip, r2, r3 + 80049b0: e7a5 b.n 80048fe <_vfiprintf_r+0x11a> + 80049b2: 2300 movs r3, #0 + 80049b4: f04f 0c0a mov.w ip, #10 + 80049b8: 4619 mov r1, r3 + 80049ba: 3401 adds r4, #1 + 80049bc: 9305 str r3, [sp, #20] + 80049be: 4620 mov r0, r4 + 80049c0: f810 2b01 ldrb.w r2, [r0], #1 + 80049c4: 3a30 subs r2, #48 ; 0x30 + 80049c6: 2a09 cmp r2, #9 + 80049c8: d903 bls.n 80049d2 <_vfiprintf_r+0x1ee> + 80049ca: 2b00 cmp r3, #0 + 80049cc: d0c5 beq.n 800495a <_vfiprintf_r+0x176> + 80049ce: 9105 str r1, [sp, #20] + 80049d0: e7c3 b.n 800495a <_vfiprintf_r+0x176> + 80049d2: 4604 mov r4, r0 + 80049d4: 2301 movs r3, #1 + 80049d6: fb0c 2101 mla r1, ip, r1, r2 + 80049da: e7f0 b.n 80049be <_vfiprintf_r+0x1da> + 80049dc: ab03 add r3, sp, #12 + 80049de: 9300 str r3, [sp, #0] + 80049e0: 462a mov r2, r5 + 80049e2: 4630 mov r0, r6 + 80049e4: 4b15 ldr r3, [pc, #84] ; (8004a3c <_vfiprintf_r+0x258>) + 80049e6: a904 add r1, sp, #16 + 80049e8: f7fd ffda bl 80029a0 <_printf_float> + 80049ec: 4607 mov r7, r0 + 80049ee: 1c78 adds r0, r7, #1 + 80049f0: d1d6 bne.n 80049a0 <_vfiprintf_r+0x1bc> + 80049f2: 6e6b ldr r3, [r5, #100] ; 0x64 + 80049f4: 07d9 lsls r1, r3, #31 + 80049f6: d405 bmi.n 8004a04 <_vfiprintf_r+0x220> + 80049f8: 89ab ldrh r3, [r5, #12] + 80049fa: 059a lsls r2, r3, #22 + 80049fc: d402 bmi.n 8004a04 <_vfiprintf_r+0x220> + 80049fe: 6da8 ldr r0, [r5, #88] ; 0x58 + 8004a00: f000 faaf bl 8004f62 <__retarget_lock_release_recursive> + 8004a04: 89ab ldrh r3, [r5, #12] + 8004a06: 065b lsls r3, r3, #25 + 8004a08: f53f af12 bmi.w 8004830 <_vfiprintf_r+0x4c> + 8004a0c: 9809 ldr r0, [sp, #36] ; 0x24 + 8004a0e: e711 b.n 8004834 <_vfiprintf_r+0x50> + 8004a10: ab03 add r3, sp, #12 + 8004a12: 9300 str r3, [sp, #0] + 8004a14: 462a mov r2, r5 + 8004a16: 4630 mov r0, r6 + 8004a18: 4b08 ldr r3, [pc, #32] ; (8004a3c <_vfiprintf_r+0x258>) + 8004a1a: a904 add r1, sp, #16 + 8004a1c: f7fe fa5c bl 8002ed8 <_printf_i> + 8004a20: e7e4 b.n 80049ec <_vfiprintf_r+0x208> + 8004a22: bf00 nop + 8004a24: 080055ec .word 0x080055ec + 8004a28: 0800560c .word 0x0800560c + 8004a2c: 080055cc .word 0x080055cc + 8004a30: 080054ba .word 0x080054ba + 8004a34: 080054c4 .word 0x080054c4 + 8004a38: 080029a1 .word 0x080029a1 + 8004a3c: 080047bf .word 0x080047bf + 8004a40: 080054c0 .word 0x080054c0 + +08004a44 <__swbuf_r>: + 8004a44: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004a46: 460e mov r6, r1 + 8004a48: 4614 mov r4, r2 + 8004a4a: 4605 mov r5, r0 + 8004a4c: b118 cbz r0, 8004a56 <__swbuf_r+0x12> + 8004a4e: 6983 ldr r3, [r0, #24] + 8004a50: b90b cbnz r3, 8004a56 <__swbuf_r+0x12> + 8004a52: f000 f9e7 bl 8004e24 <__sinit> + 8004a56: 4b21 ldr r3, [pc, #132] ; (8004adc <__swbuf_r+0x98>) + 8004a58: 429c cmp r4, r3 + 8004a5a: d12b bne.n 8004ab4 <__swbuf_r+0x70> + 8004a5c: 686c ldr r4, [r5, #4] + 8004a5e: 69a3 ldr r3, [r4, #24] + 8004a60: 60a3 str r3, [r4, #8] + 8004a62: 89a3 ldrh r3, [r4, #12] + 8004a64: 071a lsls r2, r3, #28 + 8004a66: d52f bpl.n 8004ac8 <__swbuf_r+0x84> + 8004a68: 6923 ldr r3, [r4, #16] + 8004a6a: b36b cbz r3, 8004ac8 <__swbuf_r+0x84> + 8004a6c: 6923 ldr r3, [r4, #16] + 8004a6e: 6820 ldr r0, [r4, #0] + 8004a70: b2f6 uxtb r6, r6 + 8004a72: 1ac0 subs r0, r0, r3 + 8004a74: 6963 ldr r3, [r4, #20] + 8004a76: 4637 mov r7, r6 + 8004a78: 4283 cmp r3, r0 + 8004a7a: dc04 bgt.n 8004a86 <__swbuf_r+0x42> + 8004a7c: 4621 mov r1, r4 + 8004a7e: 4628 mov r0, r5 + 8004a80: f000 f93c bl 8004cfc <_fflush_r> + 8004a84: bb30 cbnz r0, 8004ad4 <__swbuf_r+0x90> + 8004a86: 68a3 ldr r3, [r4, #8] + 8004a88: 3001 adds r0, #1 + 8004a8a: 3b01 subs r3, #1 + 8004a8c: 60a3 str r3, [r4, #8] + 8004a8e: 6823 ldr r3, [r4, #0] + 8004a90: 1c5a adds r2, r3, #1 + 8004a92: 6022 str r2, [r4, #0] + 8004a94: 701e strb r6, [r3, #0] + 8004a96: 6963 ldr r3, [r4, #20] + 8004a98: 4283 cmp r3, r0 + 8004a9a: d004 beq.n 8004aa6 <__swbuf_r+0x62> + 8004a9c: 89a3 ldrh r3, [r4, #12] + 8004a9e: 07db lsls r3, r3, #31 + 8004aa0: d506 bpl.n 8004ab0 <__swbuf_r+0x6c> + 8004aa2: 2e0a cmp r6, #10 + 8004aa4: d104 bne.n 8004ab0 <__swbuf_r+0x6c> + 8004aa6: 4621 mov r1, r4 + 8004aa8: 4628 mov r0, r5 + 8004aaa: f000 f927 bl 8004cfc <_fflush_r> + 8004aae: b988 cbnz r0, 8004ad4 <__swbuf_r+0x90> + 8004ab0: 4638 mov r0, r7 + 8004ab2: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004ab4: 4b0a ldr r3, [pc, #40] ; (8004ae0 <__swbuf_r+0x9c>) + 8004ab6: 429c cmp r4, r3 + 8004ab8: d101 bne.n 8004abe <__swbuf_r+0x7a> + 8004aba: 68ac ldr r4, [r5, #8] + 8004abc: e7cf b.n 8004a5e <__swbuf_r+0x1a> + 8004abe: 4b09 ldr r3, [pc, #36] ; (8004ae4 <__swbuf_r+0xa0>) + 8004ac0: 429c cmp r4, r3 + 8004ac2: bf08 it eq + 8004ac4: 68ec ldreq r4, [r5, #12] + 8004ac6: e7ca b.n 8004a5e <__swbuf_r+0x1a> + 8004ac8: 4621 mov r1, r4 + 8004aca: 4628 mov r0, r5 + 8004acc: f000 f81a bl 8004b04 <__swsetup_r> + 8004ad0: 2800 cmp r0, #0 + 8004ad2: d0cb beq.n 8004a6c <__swbuf_r+0x28> + 8004ad4: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff + 8004ad8: e7ea b.n 8004ab0 <__swbuf_r+0x6c> + 8004ada: bf00 nop + 8004adc: 080055ec .word 0x080055ec + 8004ae0: 0800560c .word 0x0800560c + 8004ae4: 080055cc .word 0x080055cc + +08004ae8 <__ascii_wctomb>: + 8004ae8: 4603 mov r3, r0 + 8004aea: 4608 mov r0, r1 + 8004aec: b141 cbz r1, 8004b00 <__ascii_wctomb+0x18> + 8004aee: 2aff cmp r2, #255 ; 0xff + 8004af0: d904 bls.n 8004afc <__ascii_wctomb+0x14> + 8004af2: 228a movs r2, #138 ; 0x8a + 8004af4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8004af8: 601a str r2, [r3, #0] + 8004afa: 4770 bx lr + 8004afc: 2001 movs r0, #1 + 8004afe: 700a strb r2, [r1, #0] + 8004b00: 4770 bx lr + ... + +08004b04 <__swsetup_r>: + 8004b04: 4b32 ldr r3, [pc, #200] ; (8004bd0 <__swsetup_r+0xcc>) + 8004b06: b570 push {r4, r5, r6, lr} + 8004b08: 681d ldr r5, [r3, #0] + 8004b0a: 4606 mov r6, r0 + 8004b0c: 460c mov r4, r1 + 8004b0e: b125 cbz r5, 8004b1a <__swsetup_r+0x16> + 8004b10: 69ab ldr r3, [r5, #24] + 8004b12: b913 cbnz r3, 8004b1a <__swsetup_r+0x16> + 8004b14: 4628 mov r0, r5 + 8004b16: f000 f985 bl 8004e24 <__sinit> + 8004b1a: 4b2e ldr r3, [pc, #184] ; (8004bd4 <__swsetup_r+0xd0>) + 8004b1c: 429c cmp r4, r3 + 8004b1e: d10f bne.n 8004b40 <__swsetup_r+0x3c> + 8004b20: 686c ldr r4, [r5, #4] + 8004b22: 89a3 ldrh r3, [r4, #12] + 8004b24: f9b4 200c ldrsh.w r2, [r4, #12] + 8004b28: 0719 lsls r1, r3, #28 + 8004b2a: d42c bmi.n 8004b86 <__swsetup_r+0x82> + 8004b2c: 06dd lsls r5, r3, #27 + 8004b2e: d411 bmi.n 8004b54 <__swsetup_r+0x50> + 8004b30: 2309 movs r3, #9 + 8004b32: 6033 str r3, [r6, #0] + 8004b34: f042 0340 orr.w r3, r2, #64 ; 0x40 + 8004b38: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8004b3c: 81a3 strh r3, [r4, #12] + 8004b3e: e03e b.n 8004bbe <__swsetup_r+0xba> + 8004b40: 4b25 ldr r3, [pc, #148] ; (8004bd8 <__swsetup_r+0xd4>) + 8004b42: 429c cmp r4, r3 + 8004b44: d101 bne.n 8004b4a <__swsetup_r+0x46> + 8004b46: 68ac ldr r4, [r5, #8] + 8004b48: e7eb b.n 8004b22 <__swsetup_r+0x1e> + 8004b4a: 4b24 ldr r3, [pc, #144] ; (8004bdc <__swsetup_r+0xd8>) + 8004b4c: 429c cmp r4, r3 + 8004b4e: bf08 it eq + 8004b50: 68ec ldreq r4, [r5, #12] + 8004b52: e7e6 b.n 8004b22 <__swsetup_r+0x1e> + 8004b54: 0758 lsls r0, r3, #29 + 8004b56: d512 bpl.n 8004b7e <__swsetup_r+0x7a> + 8004b58: 6b61 ldr r1, [r4, #52] ; 0x34 + 8004b5a: b141 cbz r1, 8004b6e <__swsetup_r+0x6a> + 8004b5c: f104 0344 add.w r3, r4, #68 ; 0x44 + 8004b60: 4299 cmp r1, r3 + 8004b62: d002 beq.n 8004b6a <__swsetup_r+0x66> + 8004b64: 4630 mov r0, r6 + 8004b66: f7ff fd11 bl 800458c <_free_r> + 8004b6a: 2300 movs r3, #0 + 8004b6c: 6363 str r3, [r4, #52] ; 0x34 + 8004b6e: 89a3 ldrh r3, [r4, #12] + 8004b70: f023 0324 bic.w r3, r3, #36 ; 0x24 + 8004b74: 81a3 strh r3, [r4, #12] + 8004b76: 2300 movs r3, #0 + 8004b78: 6063 str r3, [r4, #4] + 8004b7a: 6923 ldr r3, [r4, #16] + 8004b7c: 6023 str r3, [r4, #0] + 8004b7e: 89a3 ldrh r3, [r4, #12] + 8004b80: f043 0308 orr.w r3, r3, #8 + 8004b84: 81a3 strh r3, [r4, #12] + 8004b86: 6923 ldr r3, [r4, #16] + 8004b88: b94b cbnz r3, 8004b9e <__swsetup_r+0x9a> + 8004b8a: 89a3 ldrh r3, [r4, #12] + 8004b8c: f403 7320 and.w r3, r3, #640 ; 0x280 + 8004b90: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8004b94: d003 beq.n 8004b9e <__swsetup_r+0x9a> + 8004b96: 4621 mov r1, r4 + 8004b98: 4630 mov r0, r6 + 8004b9a: f000 fa07 bl 8004fac <__smakebuf_r> + 8004b9e: 89a0 ldrh r0, [r4, #12] + 8004ba0: f9b4 200c ldrsh.w r2, [r4, #12] + 8004ba4: f010 0301 ands.w r3, r0, #1 + 8004ba8: d00a beq.n 8004bc0 <__swsetup_r+0xbc> + 8004baa: 2300 movs r3, #0 + 8004bac: 60a3 str r3, [r4, #8] + 8004bae: 6963 ldr r3, [r4, #20] + 8004bb0: 425b negs r3, r3 + 8004bb2: 61a3 str r3, [r4, #24] + 8004bb4: 6923 ldr r3, [r4, #16] + 8004bb6: b943 cbnz r3, 8004bca <__swsetup_r+0xc6> + 8004bb8: f010 0080 ands.w r0, r0, #128 ; 0x80 + 8004bbc: d1ba bne.n 8004b34 <__swsetup_r+0x30> + 8004bbe: bd70 pop {r4, r5, r6, pc} + 8004bc0: 0781 lsls r1, r0, #30 + 8004bc2: bf58 it pl + 8004bc4: 6963 ldrpl r3, [r4, #20] + 8004bc6: 60a3 str r3, [r4, #8] + 8004bc8: e7f4 b.n 8004bb4 <__swsetup_r+0xb0> + 8004bca: 2000 movs r0, #0 + 8004bcc: e7f7 b.n 8004bbe <__swsetup_r+0xba> + 8004bce: bf00 nop + 8004bd0: 2000000c .word 0x2000000c + 8004bd4: 080055ec .word 0x080055ec + 8004bd8: 0800560c .word 0x0800560c + 8004bdc: 080055cc .word 0x080055cc + +08004be0 : + 8004be0: 2006 movs r0, #6 + 8004be2: b508 push {r3, lr} + 8004be4: f000 fa4a bl 800507c + 8004be8: 2001 movs r0, #1 + 8004bea: f7fc f999 bl 8000f20 <_exit> + ... + +08004bf0 <__sflush_r>: + 8004bf0: 898a ldrh r2, [r1, #12] + 8004bf2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8004bf6: 4605 mov r5, r0 + 8004bf8: 0710 lsls r0, r2, #28 + 8004bfa: 460c mov r4, r1 + 8004bfc: d458 bmi.n 8004cb0 <__sflush_r+0xc0> + 8004bfe: 684b ldr r3, [r1, #4] + 8004c00: 2b00 cmp r3, #0 + 8004c02: dc05 bgt.n 8004c10 <__sflush_r+0x20> + 8004c04: 6c0b ldr r3, [r1, #64] ; 0x40 + 8004c06: 2b00 cmp r3, #0 + 8004c08: dc02 bgt.n 8004c10 <__sflush_r+0x20> + 8004c0a: 2000 movs r0, #0 + 8004c0c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8004c10: 6ae6 ldr r6, [r4, #44] ; 0x2c + 8004c12: 2e00 cmp r6, #0 + 8004c14: d0f9 beq.n 8004c0a <__sflush_r+0x1a> + 8004c16: 2300 movs r3, #0 + 8004c18: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 8004c1c: 682f ldr r7, [r5, #0] + 8004c1e: 602b str r3, [r5, #0] + 8004c20: d032 beq.n 8004c88 <__sflush_r+0x98> + 8004c22: 6d60 ldr r0, [r4, #84] ; 0x54 + 8004c24: 89a3 ldrh r3, [r4, #12] + 8004c26: 075a lsls r2, r3, #29 + 8004c28: d505 bpl.n 8004c36 <__sflush_r+0x46> + 8004c2a: 6863 ldr r3, [r4, #4] + 8004c2c: 1ac0 subs r0, r0, r3 + 8004c2e: 6b63 ldr r3, [r4, #52] ; 0x34 + 8004c30: b10b cbz r3, 8004c36 <__sflush_r+0x46> + 8004c32: 6c23 ldr r3, [r4, #64] ; 0x40 + 8004c34: 1ac0 subs r0, r0, r3 + 8004c36: 2300 movs r3, #0 + 8004c38: 4602 mov r2, r0 + 8004c3a: 6ae6 ldr r6, [r4, #44] ; 0x2c + 8004c3c: 4628 mov r0, r5 + 8004c3e: 6a21 ldr r1, [r4, #32] + 8004c40: 47b0 blx r6 + 8004c42: 1c43 adds r3, r0, #1 + 8004c44: 89a3 ldrh r3, [r4, #12] + 8004c46: d106 bne.n 8004c56 <__sflush_r+0x66> + 8004c48: 6829 ldr r1, [r5, #0] + 8004c4a: 291d cmp r1, #29 + 8004c4c: d82c bhi.n 8004ca8 <__sflush_r+0xb8> + 8004c4e: 4a2a ldr r2, [pc, #168] ; (8004cf8 <__sflush_r+0x108>) + 8004c50: 40ca lsrs r2, r1 + 8004c52: 07d6 lsls r6, r2, #31 + 8004c54: d528 bpl.n 8004ca8 <__sflush_r+0xb8> + 8004c56: 2200 movs r2, #0 + 8004c58: 6062 str r2, [r4, #4] + 8004c5a: 6922 ldr r2, [r4, #16] + 8004c5c: 04d9 lsls r1, r3, #19 + 8004c5e: 6022 str r2, [r4, #0] + 8004c60: d504 bpl.n 8004c6c <__sflush_r+0x7c> + 8004c62: 1c42 adds r2, r0, #1 + 8004c64: d101 bne.n 8004c6a <__sflush_r+0x7a> + 8004c66: 682b ldr r3, [r5, #0] + 8004c68: b903 cbnz r3, 8004c6c <__sflush_r+0x7c> + 8004c6a: 6560 str r0, [r4, #84] ; 0x54 + 8004c6c: 6b61 ldr r1, [r4, #52] ; 0x34 + 8004c6e: 602f str r7, [r5, #0] + 8004c70: 2900 cmp r1, #0 + 8004c72: d0ca beq.n 8004c0a <__sflush_r+0x1a> + 8004c74: f104 0344 add.w r3, r4, #68 ; 0x44 + 8004c78: 4299 cmp r1, r3 + 8004c7a: d002 beq.n 8004c82 <__sflush_r+0x92> + 8004c7c: 4628 mov r0, r5 + 8004c7e: f7ff fc85 bl 800458c <_free_r> + 8004c82: 2000 movs r0, #0 + 8004c84: 6360 str r0, [r4, #52] ; 0x34 + 8004c86: e7c1 b.n 8004c0c <__sflush_r+0x1c> + 8004c88: 6a21 ldr r1, [r4, #32] + 8004c8a: 2301 movs r3, #1 + 8004c8c: 4628 mov r0, r5 + 8004c8e: 47b0 blx r6 + 8004c90: 1c41 adds r1, r0, #1 + 8004c92: d1c7 bne.n 8004c24 <__sflush_r+0x34> + 8004c94: 682b ldr r3, [r5, #0] + 8004c96: 2b00 cmp r3, #0 + 8004c98: d0c4 beq.n 8004c24 <__sflush_r+0x34> + 8004c9a: 2b1d cmp r3, #29 + 8004c9c: d001 beq.n 8004ca2 <__sflush_r+0xb2> + 8004c9e: 2b16 cmp r3, #22 + 8004ca0: d101 bne.n 8004ca6 <__sflush_r+0xb6> + 8004ca2: 602f str r7, [r5, #0] + 8004ca4: e7b1 b.n 8004c0a <__sflush_r+0x1a> + 8004ca6: 89a3 ldrh r3, [r4, #12] + 8004ca8: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8004cac: 81a3 strh r3, [r4, #12] + 8004cae: e7ad b.n 8004c0c <__sflush_r+0x1c> + 8004cb0: 690f ldr r7, [r1, #16] + 8004cb2: 2f00 cmp r7, #0 + 8004cb4: d0a9 beq.n 8004c0a <__sflush_r+0x1a> + 8004cb6: 0793 lsls r3, r2, #30 + 8004cb8: bf18 it ne + 8004cba: 2300 movne r3, #0 + 8004cbc: 680e ldr r6, [r1, #0] + 8004cbe: bf08 it eq + 8004cc0: 694b ldreq r3, [r1, #20] + 8004cc2: eba6 0807 sub.w r8, r6, r7 + 8004cc6: 600f str r7, [r1, #0] + 8004cc8: 608b str r3, [r1, #8] + 8004cca: f1b8 0f00 cmp.w r8, #0 + 8004cce: dd9c ble.n 8004c0a <__sflush_r+0x1a> + 8004cd0: 4643 mov r3, r8 + 8004cd2: 463a mov r2, r7 + 8004cd4: 4628 mov r0, r5 + 8004cd6: 6a21 ldr r1, [r4, #32] + 8004cd8: 6aa6 ldr r6, [r4, #40] ; 0x28 + 8004cda: 47b0 blx r6 + 8004cdc: 2800 cmp r0, #0 + 8004cde: dc06 bgt.n 8004cee <__sflush_r+0xfe> + 8004ce0: 89a3 ldrh r3, [r4, #12] + 8004ce2: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8004ce6: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8004cea: 81a3 strh r3, [r4, #12] + 8004cec: e78e b.n 8004c0c <__sflush_r+0x1c> + 8004cee: 4407 add r7, r0 + 8004cf0: eba8 0800 sub.w r8, r8, r0 + 8004cf4: e7e9 b.n 8004cca <__sflush_r+0xda> + 8004cf6: bf00 nop + 8004cf8: 20400001 .word 0x20400001 + +08004cfc <_fflush_r>: + 8004cfc: b538 push {r3, r4, r5, lr} + 8004cfe: 690b ldr r3, [r1, #16] + 8004d00: 4605 mov r5, r0 + 8004d02: 460c mov r4, r1 + 8004d04: b913 cbnz r3, 8004d0c <_fflush_r+0x10> + 8004d06: 2500 movs r5, #0 + 8004d08: 4628 mov r0, r5 + 8004d0a: bd38 pop {r3, r4, r5, pc} + 8004d0c: b118 cbz r0, 8004d16 <_fflush_r+0x1a> + 8004d0e: 6983 ldr r3, [r0, #24] + 8004d10: b90b cbnz r3, 8004d16 <_fflush_r+0x1a> + 8004d12: f000 f887 bl 8004e24 <__sinit> + 8004d16: 4b14 ldr r3, [pc, #80] ; (8004d68 <_fflush_r+0x6c>) + 8004d18: 429c cmp r4, r3 + 8004d1a: d11b bne.n 8004d54 <_fflush_r+0x58> + 8004d1c: 686c ldr r4, [r5, #4] + 8004d1e: f9b4 300c ldrsh.w r3, [r4, #12] + 8004d22: 2b00 cmp r3, #0 + 8004d24: d0ef beq.n 8004d06 <_fflush_r+0xa> + 8004d26: 6e62 ldr r2, [r4, #100] ; 0x64 + 8004d28: 07d0 lsls r0, r2, #31 + 8004d2a: d404 bmi.n 8004d36 <_fflush_r+0x3a> + 8004d2c: 0599 lsls r1, r3, #22 + 8004d2e: d402 bmi.n 8004d36 <_fflush_r+0x3a> + 8004d30: 6da0 ldr r0, [r4, #88] ; 0x58 + 8004d32: f000 f915 bl 8004f60 <__retarget_lock_acquire_recursive> + 8004d36: 4628 mov r0, r5 + 8004d38: 4621 mov r1, r4 + 8004d3a: f7ff ff59 bl 8004bf0 <__sflush_r> + 8004d3e: 6e63 ldr r3, [r4, #100] ; 0x64 + 8004d40: 4605 mov r5, r0 + 8004d42: 07da lsls r2, r3, #31 + 8004d44: d4e0 bmi.n 8004d08 <_fflush_r+0xc> + 8004d46: 89a3 ldrh r3, [r4, #12] + 8004d48: 059b lsls r3, r3, #22 + 8004d4a: d4dd bmi.n 8004d08 <_fflush_r+0xc> + 8004d4c: 6da0 ldr r0, [r4, #88] ; 0x58 + 8004d4e: f000 f908 bl 8004f62 <__retarget_lock_release_recursive> + 8004d52: e7d9 b.n 8004d08 <_fflush_r+0xc> + 8004d54: 4b05 ldr r3, [pc, #20] ; (8004d6c <_fflush_r+0x70>) + 8004d56: 429c cmp r4, r3 + 8004d58: d101 bne.n 8004d5e <_fflush_r+0x62> + 8004d5a: 68ac ldr r4, [r5, #8] + 8004d5c: e7df b.n 8004d1e <_fflush_r+0x22> + 8004d5e: 4b04 ldr r3, [pc, #16] ; (8004d70 <_fflush_r+0x74>) + 8004d60: 429c cmp r4, r3 + 8004d62: bf08 it eq + 8004d64: 68ec ldreq r4, [r5, #12] + 8004d66: e7da b.n 8004d1e <_fflush_r+0x22> + 8004d68: 080055ec .word 0x080055ec + 8004d6c: 0800560c .word 0x0800560c + 8004d70: 080055cc .word 0x080055cc + +08004d74 : + 8004d74: 2300 movs r3, #0 + 8004d76: b510 push {r4, lr} + 8004d78: 4604 mov r4, r0 + 8004d7a: e9c0 3300 strd r3, r3, [r0] + 8004d7e: e9c0 3304 strd r3, r3, [r0, #16] + 8004d82: 6083 str r3, [r0, #8] + 8004d84: 8181 strh r1, [r0, #12] + 8004d86: 6643 str r3, [r0, #100] ; 0x64 + 8004d88: 81c2 strh r2, [r0, #14] + 8004d8a: 6183 str r3, [r0, #24] + 8004d8c: 4619 mov r1, r3 + 8004d8e: 2208 movs r2, #8 + 8004d90: 305c adds r0, #92 ; 0x5c + 8004d92: f7fd fd5f bl 8002854 + 8004d96: 4b05 ldr r3, [pc, #20] ; (8004dac ) + 8004d98: 6224 str r4, [r4, #32] + 8004d9a: 6263 str r3, [r4, #36] ; 0x24 + 8004d9c: 4b04 ldr r3, [pc, #16] ; (8004db0 ) + 8004d9e: 62a3 str r3, [r4, #40] ; 0x28 + 8004da0: 4b04 ldr r3, [pc, #16] ; (8004db4 ) + 8004da2: 62e3 str r3, [r4, #44] ; 0x2c + 8004da4: 4b04 ldr r3, [pc, #16] ; (8004db8 ) + 8004da6: 6323 str r3, [r4, #48] ; 0x30 + 8004da8: bd10 pop {r4, pc} + 8004daa: bf00 nop + 8004dac: 080050b5 .word 0x080050b5 + 8004db0: 080050d7 .word 0x080050d7 + 8004db4: 0800510f .word 0x0800510f + 8004db8: 08005133 .word 0x08005133 + +08004dbc <_cleanup_r>: + 8004dbc: 4901 ldr r1, [pc, #4] ; (8004dc4 <_cleanup_r+0x8>) + 8004dbe: f000 b8af b.w 8004f20 <_fwalk_reent> + 8004dc2: bf00 nop + 8004dc4: 08004cfd .word 0x08004cfd + +08004dc8 <__sfmoreglue>: + 8004dc8: b570 push {r4, r5, r6, lr} + 8004dca: 2568 movs r5, #104 ; 0x68 + 8004dcc: 1e4a subs r2, r1, #1 + 8004dce: 4355 muls r5, r2 + 8004dd0: 460e mov r6, r1 + 8004dd2: f105 0174 add.w r1, r5, #116 ; 0x74 + 8004dd6: f7ff fc25 bl 8004624 <_malloc_r> + 8004dda: 4604 mov r4, r0 + 8004ddc: b140 cbz r0, 8004df0 <__sfmoreglue+0x28> + 8004dde: 2100 movs r1, #0 + 8004de0: e9c0 1600 strd r1, r6, [r0] + 8004de4: 300c adds r0, #12 + 8004de6: 60a0 str r0, [r4, #8] + 8004de8: f105 0268 add.w r2, r5, #104 ; 0x68 + 8004dec: f7fd fd32 bl 8002854 + 8004df0: 4620 mov r0, r4 + 8004df2: bd70 pop {r4, r5, r6, pc} + +08004df4 <__sfp_lock_acquire>: + 8004df4: 4801 ldr r0, [pc, #4] ; (8004dfc <__sfp_lock_acquire+0x8>) + 8004df6: f000 b8b3 b.w 8004f60 <__retarget_lock_acquire_recursive> + 8004dfa: bf00 nop + 8004dfc: 2000026c .word 0x2000026c + +08004e00 <__sfp_lock_release>: + 8004e00: 4801 ldr r0, [pc, #4] ; (8004e08 <__sfp_lock_release+0x8>) + 8004e02: f000 b8ae b.w 8004f62 <__retarget_lock_release_recursive> + 8004e06: bf00 nop + 8004e08: 2000026c .word 0x2000026c + +08004e0c <__sinit_lock_acquire>: + 8004e0c: 4801 ldr r0, [pc, #4] ; (8004e14 <__sinit_lock_acquire+0x8>) + 8004e0e: f000 b8a7 b.w 8004f60 <__retarget_lock_acquire_recursive> + 8004e12: bf00 nop + 8004e14: 20000267 .word 0x20000267 + +08004e18 <__sinit_lock_release>: + 8004e18: 4801 ldr r0, [pc, #4] ; (8004e20 <__sinit_lock_release+0x8>) + 8004e1a: f000 b8a2 b.w 8004f62 <__retarget_lock_release_recursive> + 8004e1e: bf00 nop + 8004e20: 20000267 .word 0x20000267 + +08004e24 <__sinit>: + 8004e24: b510 push {r4, lr} + 8004e26: 4604 mov r4, r0 + 8004e28: f7ff fff0 bl 8004e0c <__sinit_lock_acquire> + 8004e2c: 69a3 ldr r3, [r4, #24] + 8004e2e: b11b cbz r3, 8004e38 <__sinit+0x14> + 8004e30: e8bd 4010 ldmia.w sp!, {r4, lr} + 8004e34: f7ff bff0 b.w 8004e18 <__sinit_lock_release> + 8004e38: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 + 8004e3c: 6523 str r3, [r4, #80] ; 0x50 + 8004e3e: 4b13 ldr r3, [pc, #76] ; (8004e8c <__sinit+0x68>) + 8004e40: 4a13 ldr r2, [pc, #76] ; (8004e90 <__sinit+0x6c>) + 8004e42: 681b ldr r3, [r3, #0] + 8004e44: 62a2 str r2, [r4, #40] ; 0x28 + 8004e46: 42a3 cmp r3, r4 + 8004e48: bf08 it eq + 8004e4a: 2301 moveq r3, #1 + 8004e4c: 4620 mov r0, r4 + 8004e4e: bf08 it eq + 8004e50: 61a3 streq r3, [r4, #24] + 8004e52: f000 f81f bl 8004e94 <__sfp> + 8004e56: 6060 str r0, [r4, #4] + 8004e58: 4620 mov r0, r4 + 8004e5a: f000 f81b bl 8004e94 <__sfp> + 8004e5e: 60a0 str r0, [r4, #8] + 8004e60: 4620 mov r0, r4 + 8004e62: f000 f817 bl 8004e94 <__sfp> + 8004e66: 2200 movs r2, #0 + 8004e68: 2104 movs r1, #4 + 8004e6a: 60e0 str r0, [r4, #12] + 8004e6c: 6860 ldr r0, [r4, #4] + 8004e6e: f7ff ff81 bl 8004d74 + 8004e72: 2201 movs r2, #1 + 8004e74: 2109 movs r1, #9 + 8004e76: 68a0 ldr r0, [r4, #8] + 8004e78: f7ff ff7c bl 8004d74 + 8004e7c: 2202 movs r2, #2 + 8004e7e: 2112 movs r1, #18 + 8004e80: 68e0 ldr r0, [r4, #12] + 8004e82: f7ff ff77 bl 8004d74 + 8004e86: 2301 movs r3, #1 + 8004e88: 61a3 str r3, [r4, #24] + 8004e8a: e7d1 b.n 8004e30 <__sinit+0xc> + 8004e8c: 08005248 .word 0x08005248 + 8004e90: 08004dbd .word 0x08004dbd + +08004e94 <__sfp>: + 8004e94: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004e96: 4607 mov r7, r0 + 8004e98: f7ff ffac bl 8004df4 <__sfp_lock_acquire> + 8004e9c: 4b1e ldr r3, [pc, #120] ; (8004f18 <__sfp+0x84>) + 8004e9e: 681e ldr r6, [r3, #0] + 8004ea0: 69b3 ldr r3, [r6, #24] + 8004ea2: b913 cbnz r3, 8004eaa <__sfp+0x16> + 8004ea4: 4630 mov r0, r6 + 8004ea6: f7ff ffbd bl 8004e24 <__sinit> + 8004eaa: 3648 adds r6, #72 ; 0x48 + 8004eac: e9d6 3401 ldrd r3, r4, [r6, #4] + 8004eb0: 3b01 subs r3, #1 + 8004eb2: d503 bpl.n 8004ebc <__sfp+0x28> + 8004eb4: 6833 ldr r3, [r6, #0] + 8004eb6: b30b cbz r3, 8004efc <__sfp+0x68> + 8004eb8: 6836 ldr r6, [r6, #0] + 8004eba: e7f7 b.n 8004eac <__sfp+0x18> + 8004ebc: f9b4 500c ldrsh.w r5, [r4, #12] + 8004ec0: b9d5 cbnz r5, 8004ef8 <__sfp+0x64> + 8004ec2: 4b16 ldr r3, [pc, #88] ; (8004f1c <__sfp+0x88>) + 8004ec4: f104 0058 add.w r0, r4, #88 ; 0x58 + 8004ec8: 60e3 str r3, [r4, #12] + 8004eca: 6665 str r5, [r4, #100] ; 0x64 + 8004ecc: f000 f847 bl 8004f5e <__retarget_lock_init_recursive> + 8004ed0: f7ff ff96 bl 8004e00 <__sfp_lock_release> + 8004ed4: 2208 movs r2, #8 + 8004ed6: 4629 mov r1, r5 + 8004ed8: e9c4 5501 strd r5, r5, [r4, #4] + 8004edc: e9c4 5504 strd r5, r5, [r4, #16] + 8004ee0: 6025 str r5, [r4, #0] + 8004ee2: 61a5 str r5, [r4, #24] + 8004ee4: f104 005c add.w r0, r4, #92 ; 0x5c + 8004ee8: f7fd fcb4 bl 8002854 + 8004eec: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 + 8004ef0: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 + 8004ef4: 4620 mov r0, r4 + 8004ef6: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004ef8: 3468 adds r4, #104 ; 0x68 + 8004efa: e7d9 b.n 8004eb0 <__sfp+0x1c> + 8004efc: 2104 movs r1, #4 + 8004efe: 4638 mov r0, r7 + 8004f00: f7ff ff62 bl 8004dc8 <__sfmoreglue> + 8004f04: 4604 mov r4, r0 + 8004f06: 6030 str r0, [r6, #0] + 8004f08: 2800 cmp r0, #0 + 8004f0a: d1d5 bne.n 8004eb8 <__sfp+0x24> + 8004f0c: f7ff ff78 bl 8004e00 <__sfp_lock_release> + 8004f10: 230c movs r3, #12 + 8004f12: 603b str r3, [r7, #0] + 8004f14: e7ee b.n 8004ef4 <__sfp+0x60> + 8004f16: bf00 nop + 8004f18: 08005248 .word 0x08005248 + 8004f1c: ffff0001 .word 0xffff0001 + +08004f20 <_fwalk_reent>: + 8004f20: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8004f24: 4606 mov r6, r0 + 8004f26: 4688 mov r8, r1 + 8004f28: 2700 movs r7, #0 + 8004f2a: f100 0448 add.w r4, r0, #72 ; 0x48 + 8004f2e: e9d4 9501 ldrd r9, r5, [r4, #4] + 8004f32: f1b9 0901 subs.w r9, r9, #1 + 8004f36: d505 bpl.n 8004f44 <_fwalk_reent+0x24> + 8004f38: 6824 ldr r4, [r4, #0] + 8004f3a: 2c00 cmp r4, #0 + 8004f3c: d1f7 bne.n 8004f2e <_fwalk_reent+0xe> + 8004f3e: 4638 mov r0, r7 + 8004f40: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8004f44: 89ab ldrh r3, [r5, #12] + 8004f46: 2b01 cmp r3, #1 + 8004f48: d907 bls.n 8004f5a <_fwalk_reent+0x3a> + 8004f4a: f9b5 300e ldrsh.w r3, [r5, #14] + 8004f4e: 3301 adds r3, #1 + 8004f50: d003 beq.n 8004f5a <_fwalk_reent+0x3a> + 8004f52: 4629 mov r1, r5 + 8004f54: 4630 mov r0, r6 + 8004f56: 47c0 blx r8 + 8004f58: 4307 orrs r7, r0 + 8004f5a: 3568 adds r5, #104 ; 0x68 + 8004f5c: e7e9 b.n 8004f32 <_fwalk_reent+0x12> + +08004f5e <__retarget_lock_init_recursive>: + 8004f5e: 4770 bx lr + +08004f60 <__retarget_lock_acquire_recursive>: + 8004f60: 4770 bx lr + +08004f62 <__retarget_lock_release_recursive>: + 8004f62: 4770 bx lr + +08004f64 <__swhatbuf_r>: + 8004f64: b570 push {r4, r5, r6, lr} + 8004f66: 460e mov r6, r1 + 8004f68: f9b1 100e ldrsh.w r1, [r1, #14] + 8004f6c: 4614 mov r4, r2 + 8004f6e: 2900 cmp r1, #0 + 8004f70: 461d mov r5, r3 + 8004f72: b096 sub sp, #88 ; 0x58 + 8004f74: da07 bge.n 8004f86 <__swhatbuf_r+0x22> + 8004f76: 2300 movs r3, #0 + 8004f78: 602b str r3, [r5, #0] + 8004f7a: 89b3 ldrh r3, [r6, #12] + 8004f7c: 061a lsls r2, r3, #24 + 8004f7e: d410 bmi.n 8004fa2 <__swhatbuf_r+0x3e> + 8004f80: f44f 6380 mov.w r3, #1024 ; 0x400 + 8004f84: e00e b.n 8004fa4 <__swhatbuf_r+0x40> + 8004f86: 466a mov r2, sp + 8004f88: f000 f8fa bl 8005180 <_fstat_r> + 8004f8c: 2800 cmp r0, #0 + 8004f8e: dbf2 blt.n 8004f76 <__swhatbuf_r+0x12> + 8004f90: 9a01 ldr r2, [sp, #4] + 8004f92: f402 4270 and.w r2, r2, #61440 ; 0xf000 + 8004f96: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 + 8004f9a: 425a negs r2, r3 + 8004f9c: 415a adcs r2, r3 + 8004f9e: 602a str r2, [r5, #0] + 8004fa0: e7ee b.n 8004f80 <__swhatbuf_r+0x1c> + 8004fa2: 2340 movs r3, #64 ; 0x40 + 8004fa4: 2000 movs r0, #0 + 8004fa6: 6023 str r3, [r4, #0] + 8004fa8: b016 add sp, #88 ; 0x58 + 8004faa: bd70 pop {r4, r5, r6, pc} + +08004fac <__smakebuf_r>: + 8004fac: 898b ldrh r3, [r1, #12] + 8004fae: b573 push {r0, r1, r4, r5, r6, lr} + 8004fb0: 079d lsls r5, r3, #30 + 8004fb2: 4606 mov r6, r0 + 8004fb4: 460c mov r4, r1 + 8004fb6: d507 bpl.n 8004fc8 <__smakebuf_r+0x1c> + 8004fb8: f104 0347 add.w r3, r4, #71 ; 0x47 + 8004fbc: 6023 str r3, [r4, #0] + 8004fbe: 6123 str r3, [r4, #16] + 8004fc0: 2301 movs r3, #1 + 8004fc2: 6163 str r3, [r4, #20] + 8004fc4: b002 add sp, #8 + 8004fc6: bd70 pop {r4, r5, r6, pc} + 8004fc8: 466a mov r2, sp + 8004fca: ab01 add r3, sp, #4 + 8004fcc: f7ff ffca bl 8004f64 <__swhatbuf_r> + 8004fd0: 9900 ldr r1, [sp, #0] + 8004fd2: 4605 mov r5, r0 + 8004fd4: 4630 mov r0, r6 + 8004fd6: f7ff fb25 bl 8004624 <_malloc_r> + 8004fda: b948 cbnz r0, 8004ff0 <__smakebuf_r+0x44> + 8004fdc: f9b4 300c ldrsh.w r3, [r4, #12] + 8004fe0: 059a lsls r2, r3, #22 + 8004fe2: d4ef bmi.n 8004fc4 <__smakebuf_r+0x18> + 8004fe4: f023 0303 bic.w r3, r3, #3 + 8004fe8: f043 0302 orr.w r3, r3, #2 + 8004fec: 81a3 strh r3, [r4, #12] + 8004fee: e7e3 b.n 8004fb8 <__smakebuf_r+0xc> + 8004ff0: 4b0d ldr r3, [pc, #52] ; (8005028 <__smakebuf_r+0x7c>) + 8004ff2: 62b3 str r3, [r6, #40] ; 0x28 + 8004ff4: 89a3 ldrh r3, [r4, #12] + 8004ff6: 6020 str r0, [r4, #0] + 8004ff8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8004ffc: 81a3 strh r3, [r4, #12] + 8004ffe: 9b00 ldr r3, [sp, #0] + 8005000: 6120 str r0, [r4, #16] + 8005002: 6163 str r3, [r4, #20] + 8005004: 9b01 ldr r3, [sp, #4] + 8005006: b15b cbz r3, 8005020 <__smakebuf_r+0x74> + 8005008: 4630 mov r0, r6 + 800500a: f9b4 100e ldrsh.w r1, [r4, #14] + 800500e: f000 f8c9 bl 80051a4 <_isatty_r> + 8005012: b128 cbz r0, 8005020 <__smakebuf_r+0x74> + 8005014: 89a3 ldrh r3, [r4, #12] + 8005016: f023 0303 bic.w r3, r3, #3 + 800501a: f043 0301 orr.w r3, r3, #1 + 800501e: 81a3 strh r3, [r4, #12] + 8005020: 89a0 ldrh r0, [r4, #12] + 8005022: 4305 orrs r5, r0 + 8005024: 81a5 strh r5, [r4, #12] + 8005026: e7cd b.n 8004fc4 <__smakebuf_r+0x18> + 8005028: 08004dbd .word 0x08004dbd + +0800502c <_raise_r>: + 800502c: 291f cmp r1, #31 + 800502e: b538 push {r3, r4, r5, lr} + 8005030: 4604 mov r4, r0 + 8005032: 460d mov r5, r1 + 8005034: d904 bls.n 8005040 <_raise_r+0x14> + 8005036: 2316 movs r3, #22 + 8005038: 6003 str r3, [r0, #0] + 800503a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800503e: bd38 pop {r3, r4, r5, pc} + 8005040: 6c42 ldr r2, [r0, #68] ; 0x44 + 8005042: b112 cbz r2, 800504a <_raise_r+0x1e> + 8005044: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 8005048: b94b cbnz r3, 800505e <_raise_r+0x32> + 800504a: 4620 mov r0, r4 + 800504c: f000 f830 bl 80050b0 <_getpid_r> + 8005050: 462a mov r2, r5 + 8005052: 4601 mov r1, r0 + 8005054: 4620 mov r0, r4 + 8005056: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800505a: f000 b817 b.w 800508c <_kill_r> + 800505e: 2b01 cmp r3, #1 + 8005060: d00a beq.n 8005078 <_raise_r+0x4c> + 8005062: 1c59 adds r1, r3, #1 + 8005064: d103 bne.n 800506e <_raise_r+0x42> + 8005066: 2316 movs r3, #22 + 8005068: 6003 str r3, [r0, #0] + 800506a: 2001 movs r0, #1 + 800506c: e7e7 b.n 800503e <_raise_r+0x12> + 800506e: 2400 movs r4, #0 + 8005070: 4628 mov r0, r5 + 8005072: f842 4025 str.w r4, [r2, r5, lsl #2] + 8005076: 4798 blx r3 + 8005078: 2000 movs r0, #0 + 800507a: e7e0 b.n 800503e <_raise_r+0x12> + +0800507c : + 800507c: 4b02 ldr r3, [pc, #8] ; (8005088 ) + 800507e: 4601 mov r1, r0 + 8005080: 6818 ldr r0, [r3, #0] + 8005082: f7ff bfd3 b.w 800502c <_raise_r> + 8005086: bf00 nop + 8005088: 2000000c .word 0x2000000c + +0800508c <_kill_r>: + 800508c: b538 push {r3, r4, r5, lr} + 800508e: 2300 movs r3, #0 + 8005090: 4d06 ldr r5, [pc, #24] ; (80050ac <_kill_r+0x20>) + 8005092: 4604 mov r4, r0 + 8005094: 4608 mov r0, r1 + 8005096: 4611 mov r1, r2 + 8005098: 602b str r3, [r5, #0] + 800509a: f7fb ff31 bl 8000f00 <_kill> + 800509e: 1c43 adds r3, r0, #1 + 80050a0: d102 bne.n 80050a8 <_kill_r+0x1c> + 80050a2: 682b ldr r3, [r5, #0] + 80050a4: b103 cbz r3, 80050a8 <_kill_r+0x1c> + 80050a6: 6023 str r3, [r4, #0] + 80050a8: bd38 pop {r3, r4, r5, pc} + 80050aa: bf00 nop + 80050ac: 20000260 .word 0x20000260 + +080050b0 <_getpid_r>: + 80050b0: f7fb bf1f b.w 8000ef2 <_getpid> + +080050b4 <__sread>: + 80050b4: b510 push {r4, lr} + 80050b6: 460c mov r4, r1 + 80050b8: f9b1 100e ldrsh.w r1, [r1, #14] + 80050bc: f000 f894 bl 80051e8 <_read_r> + 80050c0: 2800 cmp r0, #0 + 80050c2: bfab itete ge + 80050c4: 6d63 ldrge r3, [r4, #84] ; 0x54 + 80050c6: 89a3 ldrhlt r3, [r4, #12] + 80050c8: 181b addge r3, r3, r0 + 80050ca: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 80050ce: bfac ite ge + 80050d0: 6563 strge r3, [r4, #84] ; 0x54 + 80050d2: 81a3 strhlt r3, [r4, #12] + 80050d4: bd10 pop {r4, pc} + +080050d6 <__swrite>: + 80050d6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80050da: 461f mov r7, r3 + 80050dc: 898b ldrh r3, [r1, #12] + 80050de: 4605 mov r5, r0 + 80050e0: 05db lsls r3, r3, #23 + 80050e2: 460c mov r4, r1 + 80050e4: 4616 mov r6, r2 + 80050e6: d505 bpl.n 80050f4 <__swrite+0x1e> + 80050e8: 2302 movs r3, #2 + 80050ea: 2200 movs r2, #0 + 80050ec: f9b1 100e ldrsh.w r1, [r1, #14] + 80050f0: f000 f868 bl 80051c4 <_lseek_r> + 80050f4: 89a3 ldrh r3, [r4, #12] + 80050f6: 4632 mov r2, r6 + 80050f8: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 80050fc: 81a3 strh r3, [r4, #12] + 80050fe: 4628 mov r0, r5 + 8005100: 463b mov r3, r7 + 8005102: f9b4 100e ldrsh.w r1, [r4, #14] + 8005106: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800510a: f000 b817 b.w 800513c <_write_r> + +0800510e <__sseek>: + 800510e: b510 push {r4, lr} + 8005110: 460c mov r4, r1 + 8005112: f9b1 100e ldrsh.w r1, [r1, #14] + 8005116: f000 f855 bl 80051c4 <_lseek_r> + 800511a: 1c43 adds r3, r0, #1 + 800511c: 89a3 ldrh r3, [r4, #12] + 800511e: bf15 itete ne + 8005120: 6560 strne r0, [r4, #84] ; 0x54 + 8005122: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 8005126: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 800512a: 81a3 strheq r3, [r4, #12] + 800512c: bf18 it ne + 800512e: 81a3 strhne r3, [r4, #12] + 8005130: bd10 pop {r4, pc} + +08005132 <__sclose>: + 8005132: f9b1 100e ldrsh.w r1, [r1, #14] + 8005136: f000 b813 b.w 8005160 <_close_r> + ... + +0800513c <_write_r>: + 800513c: b538 push {r3, r4, r5, lr} + 800513e: 4604 mov r4, r0 + 8005140: 4608 mov r0, r1 + 8005142: 4611 mov r1, r2 + 8005144: 2200 movs r2, #0 + 8005146: 4d05 ldr r5, [pc, #20] ; (800515c <_write_r+0x20>) + 8005148: 602a str r2, [r5, #0] + 800514a: 461a mov r2, r3 + 800514c: f7fb ff0f bl 8000f6e <_write> + 8005150: 1c43 adds r3, r0, #1 + 8005152: d102 bne.n 800515a <_write_r+0x1e> + 8005154: 682b ldr r3, [r5, #0] + 8005156: b103 cbz r3, 800515a <_write_r+0x1e> + 8005158: 6023 str r3, [r4, #0] + 800515a: bd38 pop {r3, r4, r5, pc} + 800515c: 20000260 .word 0x20000260 + +08005160 <_close_r>: + 8005160: b538 push {r3, r4, r5, lr} + 8005162: 2300 movs r3, #0 + 8005164: 4d05 ldr r5, [pc, #20] ; (800517c <_close_r+0x1c>) + 8005166: 4604 mov r4, r0 + 8005168: 4608 mov r0, r1 + 800516a: 602b str r3, [r5, #0] + 800516c: f7fb ff1b bl 8000fa6 <_close> + 8005170: 1c43 adds r3, r0, #1 + 8005172: d102 bne.n 800517a <_close_r+0x1a> + 8005174: 682b ldr r3, [r5, #0] + 8005176: b103 cbz r3, 800517a <_close_r+0x1a> + 8005178: 6023 str r3, [r4, #0] + 800517a: bd38 pop {r3, r4, r5, pc} + 800517c: 20000260 .word 0x20000260 + +08005180 <_fstat_r>: + 8005180: b538 push {r3, r4, r5, lr} + 8005182: 2300 movs r3, #0 + 8005184: 4d06 ldr r5, [pc, #24] ; (80051a0 <_fstat_r+0x20>) + 8005186: 4604 mov r4, r0 + 8005188: 4608 mov r0, r1 + 800518a: 4611 mov r1, r2 + 800518c: 602b str r3, [r5, #0] + 800518e: f7fb ff15 bl 8000fbc <_fstat> + 8005192: 1c43 adds r3, r0, #1 + 8005194: d102 bne.n 800519c <_fstat_r+0x1c> + 8005196: 682b ldr r3, [r5, #0] + 8005198: b103 cbz r3, 800519c <_fstat_r+0x1c> + 800519a: 6023 str r3, [r4, #0] + 800519c: bd38 pop {r3, r4, r5, pc} + 800519e: bf00 nop + 80051a0: 20000260 .word 0x20000260 + +080051a4 <_isatty_r>: + 80051a4: b538 push {r3, r4, r5, lr} + 80051a6: 2300 movs r3, #0 + 80051a8: 4d05 ldr r5, [pc, #20] ; (80051c0 <_isatty_r+0x1c>) + 80051aa: 4604 mov r4, r0 + 80051ac: 4608 mov r0, r1 + 80051ae: 602b str r3, [r5, #0] + 80051b0: f7fb ff13 bl 8000fda <_isatty> + 80051b4: 1c43 adds r3, r0, #1 + 80051b6: d102 bne.n 80051be <_isatty_r+0x1a> + 80051b8: 682b ldr r3, [r5, #0] + 80051ba: b103 cbz r3, 80051be <_isatty_r+0x1a> + 80051bc: 6023 str r3, [r4, #0] + 80051be: bd38 pop {r3, r4, r5, pc} + 80051c0: 20000260 .word 0x20000260 + +080051c4 <_lseek_r>: + 80051c4: b538 push {r3, r4, r5, lr} + 80051c6: 4604 mov r4, r0 + 80051c8: 4608 mov r0, r1 + 80051ca: 4611 mov r1, r2 + 80051cc: 2200 movs r2, #0 + 80051ce: 4d05 ldr r5, [pc, #20] ; (80051e4 <_lseek_r+0x20>) + 80051d0: 602a str r2, [r5, #0] + 80051d2: 461a mov r2, r3 + 80051d4: f7fb ff0b bl 8000fee <_lseek> + 80051d8: 1c43 adds r3, r0, #1 + 80051da: d102 bne.n 80051e2 <_lseek_r+0x1e> + 80051dc: 682b ldr r3, [r5, #0] + 80051de: b103 cbz r3, 80051e2 <_lseek_r+0x1e> + 80051e0: 6023 str r3, [r4, #0] + 80051e2: bd38 pop {r3, r4, r5, pc} + 80051e4: 20000260 .word 0x20000260 + +080051e8 <_read_r>: + 80051e8: b538 push {r3, r4, r5, lr} + 80051ea: 4604 mov r4, r0 + 80051ec: 4608 mov r0, r1 + 80051ee: 4611 mov r1, r2 + 80051f0: 2200 movs r2, #0 + 80051f2: 4d05 ldr r5, [pc, #20] ; (8005208 <_read_r+0x20>) + 80051f4: 602a str r2, [r5, #0] + 80051f6: 461a mov r2, r3 + 80051f8: f7fb fe9c bl 8000f34 <_read> + 80051fc: 1c43 adds r3, r0, #1 + 80051fe: d102 bne.n 8005206 <_read_r+0x1e> + 8005200: 682b ldr r3, [r5, #0] + 8005202: b103 cbz r3, 8005206 <_read_r+0x1e> + 8005204: 6023 str r3, [r4, #0] + 8005206: bd38 pop {r3, r4, r5, pc} + 8005208: 20000260 .word 0x20000260 + +0800520c <_init>: + 800520c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800520e: bf00 nop + 8005210: bcf8 pop {r3, r4, r5, r6, r7} + 8005212: bc08 pop {r3} + 8005214: 469e mov lr, r3 + 8005216: 4770 bx lr + +08005218 <_fini>: + 8005218: b5f8 push {r3, r4, r5, r6, r7, lr} + 800521a: bf00 nop + 800521c: bcf8 pop {r3, r4, r5, r6, r7} + 800521e: bc08 pop {r3} + 8005220: 469e mov lr, r3 + 8005222: 4770 bx lr diff --git a/Debug/m3s.map b/Debug/m3s.map new file mode 100644 index 0000000..a03188c --- /dev/null +++ b/Debug/m3s.map @@ -0,0 +1,3747 @@ +Archive member included to satisfy reference by file (symbol) + +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(lib_a-errno.o) + ./Core/Src/syscalls.o (__errno) +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(lib_a-exit.o) + /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o (exit) +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(lib_a-impure.o) + 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/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v7-m/nofp/libgcc.a(_arm_fixdfsi.o) diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..1985a08 --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,102 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include SW_APPs/subdir.mk +-include HW_Devices/subdir.mk +-include Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := m3s +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +m3s.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +m3s.list \ + +OBJCOPY_BIN += \ +m3s.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: m3s.elf secondary-outputs + +# Tool invocations +m3s.elf: $(OBJS) $(USER_OBJS) /Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/STM32F103ZETX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "m3s.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/m3s/STM32F103ZETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="m3s.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -u _printf_float -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +m3s.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "m3s.list" + @echo 'Finished building: $@' + @echo ' ' + +m3s.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "m3s.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(SIZE_OUTPUT)$(OBJDUMP_LIST)$(EXECUTABLES)$(OBJS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(OBJCOPY_BIN) m3s.elf + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..00e3442 --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,24 @@ +"./Core/Src/main.o" +"./Core/Src/stm32f1xx_hal_msp.o" +"./Core/Src/stm32f1xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32f1xx.o" +"./Core/Startup/startup_stm32f103zetx.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.o" +"./HW_Devices/LCD.o" +"./SW_APPs/Main_APP.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..e12976d --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..f6a21d6 --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,28 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +SIZE_OUTPUT := +OBJDUMP_LIST := +EXECUTABLES := +OBJS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := +OBJCOPY_BIN := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F1xx_HAL_Driver/Src \ +HW_Devices \ +SW_APPs \ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h new file mode 100644 index 0000000..3b0d4ee --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h @@ -0,0 +1,235 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_sram.h + * @author MCD Application Team + * @brief Header file of SRAM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_SRAM_H +#define STM32F1xx_HAL_SRAM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(FSMC_BANK1) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_fsmc.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ +/** @addtogroup SRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Types SRAM Exported Types + * @{ + */ +/** + * @brief HAL SRAM State structures definition + */ +typedef enum +{ + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ + +} HAL_SRAM_StateTypeDef; + +/** + * @brief SRAM handle Structure definition + */ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +typedef struct __SRAM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +{ + FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + + FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ + + FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} SRAM_HandleTypeDef; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SRAM Callback ID enumeration definition + */ +typedef enum +{ + HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ + HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ + HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ + HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ +} HAL_SRAM_CallbackIDTypeDef; + +/** + * @brief HAL SRAM Callback pointer definition + */ +typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); +typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Macros SRAM Exported Macros + * @{ + */ + +/** @brief Reset SRAM handle state + * @param __HANDLE__ SRAM handle + * @retval None + */ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/* SRAM callback registering/unregistering */ +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group3 Control functions + * @{ + */ + +/* SRAM Control functions ****************************************************/ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @{ + */ + +/* SRAM State functions ******************************************************/ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FSMC_BANK1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_SRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h new file mode 100644 index 0000000..3197b80 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h @@ -0,0 +1,965 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_fsmc.h + * @author MCD Application Team + * @brief Header file of FSMC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_LL_FSMC_H +#define STM32F1xx_LL_FSMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FSMC_LL + * @{ + */ + +/** @addtogroup FSMC_LL_Private_Macros + * @{ + */ +#if defined(FSMC_BANK1) + +#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ + ((__BANK__) == FSMC_NORSRAM_BANK2) || \ + ((__BANK__) == FSMC_NORSRAM_BANK3) || \ + ((__BANK__) == FSMC_NORSRAM_BANK4)) +#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) +#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_1024)) +#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) +#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) +#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) +#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) +#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) +#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) +#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) +#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) + +#endif /* FSMC_BANK1 */ +#if defined(FSMC_BANK3) + +#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) +#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) +#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) +#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FSMC_NAND_ECC_ENABLE)) + +#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) + +#endif /* FSMC_BANK3 */ +#if defined(FSMC_BANK4) +#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) + +#endif /* FSMC_BANK4 */ + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types + * @{ + */ + +#if defined(FSMC_BANK1) +#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef +#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef +#endif /* FSMC_BANK1 */ +#if defined(FSMC_BANK3) +#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef +#endif /* FSMC_BANK3 */ +#if defined(FSMC_BANK4) +#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef +#endif /* FSMC_BANK4 */ + +#if defined(FSMC_BANK1) +#define FSMC_NORSRAM_DEVICE FSMC_Bank1 +#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E +#endif /* FSMC_BANK1 */ +#if defined(FSMC_BANK3) +#define FSMC_NAND_DEVICE FSMC_Bank2_3 +#endif /* FSMC_BANK3 */ +#if defined(FSMC_BANK4) +#define FSMC_PCCARD_DEVICE FSMC_Bank4 +#endif /* FSMC_BANK4 */ + +#if defined(FSMC_BANK1) +/** + * @brief FSMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FSMC_Page_Size */ +} FSMC_NORSRAM_InitTypeDef; + +/** + * @brief FSMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +} FSMC_NORSRAM_TimingTypeDef; +#endif /* FSMC_BANK1 */ + +#if defined(FSMC_BANK3) +/** + * @brief FSMC NAND Configuration Structure definition + */ +typedef struct +{ + uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_NAND_Data_Width */ + + uint32_t EccComputation; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +} FSMC_NAND_InitTypeDef; +#endif + +#if defined(FSMC_BANK3) || defined(FSMC_BANK4) +/** + * @brief FSMC NAND Timing parameters structure definition + */ +typedef struct +{ + uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ + + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FSMC_NAND_PCC_TimingTypeDef; +#endif /* FSMC_BANK3 */ + +#if defined(FSMC_BANK4) +/** + * @brief FSMC PCCARD Configuration Structure definition + */ +typedef struct +{ + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +}FSMC_PCCARD_InitTypeDef; +#endif + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants + * @{ + */ +#if defined(FSMC_BANK1) + +/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank + * @{ + */ +#define FSMC_NORSRAM_BANK1 (0x00000000U) +#define FSMC_NORSRAM_BANK2 (0x00000002U) +#define FSMC_NORSRAM_BANK3 (0x00000004U) +#define FSMC_NORSRAM_BANK4 (0x00000006U) +/** + * @} + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing + * @{ + */ +#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type FSMC Memory Type + * @{ + */ +#define FSMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FSMC_MEMORY_TYPE_NOR (0x00000008U) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width + * @{ + */ +#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access + * @{ + */ +#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode + * @{ + */ +#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity + * @{ + */ +#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode + * @{ + */ +#define FSMC_WRAP_MODE_DISABLE (0x00000000U) +#define FSMC_WRAP_MODE_ENABLE (0x00000400U) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing FSMC Wait Timing + * @{ + */ +#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation FSMC Write Operation + * @{ + */ +#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal FSMC Wait Signal + * @{ + */ +#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode FSMC Extended Mode + * @{ + */ +#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait + * @{ + */ +#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) +/** + * @} + */ + +/** @defgroup FSMC_Page_Size FSMC Page Size + * @{ + */ +#define FSMC_PAGE_SIZE_NONE (0x00000000U) +#define FSMC_PAGE_SIZE_128 (0x00010000U) +#define FSMC_PAGE_SIZE_256 (0x00020000U) +#define FSMC_PAGE_SIZE_512 (0x00030000U) +#define FSMC_PAGE_SIZE_1024 (0x00040000U) +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst FSMC Write Burst + * @{ + */ +#define FSMC_WRITE_BURST_DISABLE (0x00000000U) +#define FSMC_WRITE_BURST_ENABLE (0x00080000U) +/** + * @} + */ + +/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock + * @{ + */ +#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode FSMC Access Mode + * @{ + */ +#define FSMC_ACCESS_MODE_A (0x00000000U) +#define FSMC_ACCESS_MODE_B (0x10000000U) +#define FSMC_ACCESS_MODE_C (0x20000000U) +#define FSMC_ACCESS_MODE_D (0x30000000U) +/** + * @} + */ + +/** + * @} + */ +#endif /* FSMC_BANK1 */ + +#if defined(FSMC_BANK3) || defined(FSMC_BANK4) + +/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller + * @{ + */ +/** @defgroup FSMC_NAND_Bank FSMC NAND Bank + * @{ + */ +#define FSMC_NAND_BANK2 (0x00000010U) +#define FSMC_NAND_BANK3 (0x00000100U) +/** + * @} + */ + +/** @defgroup FSMC_Wait_feature FSMC Wait feature + * @{ + */ +#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type + * @{ + */ +#if defined(FSMC_BANK4) +#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) +#endif +#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width + * @{ + */ +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) +/** + * @} + */ + +/** @defgroup FSMC_ECC FSMC ECC + * @{ + */ +#define FSMC_NAND_ECC_DISABLE (0x00000000U) +#define FSMC_NAND_ECC_ENABLE (0x00000040U) +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size + * @{ + */ +#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) +/** + * @} + */ + +/** + * @} + */ +#endif /* FSMC_BANK3 */ + + +/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition + * @{ + */ +#if defined(FSMC_BANK3) || defined(FSMC_BANK4) +#define FSMC_IT_RISING_EDGE (0x00000008U) +#define FSMC_IT_LEVEL (0x00000010U) +#define FSMC_IT_FALLING_EDGE (0x00000020U) +#endif /* FSMC_BANK3 */ +/** + * @} + */ + +/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition + * @{ + */ +#if defined(FSMC_BANK3) || defined(FSMC_BANK4) +#define FSMC_FLAG_RISING_EDGE (0x00000001U) +#define FSMC_FLAG_LEVEL (0x00000002U) +#define FSMC_FLAG_FALLING_EDGE (0x00000004U) +#define FSMC_FLAG_FEMPT (0x00000040U) +#endif /* FSMC_BANK3 */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros + * @{ + */ +#if defined(FSMC_BANK1) +/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__ FSMC_NORSRAM Instance + * @param __BANK__ FSMC_NORSRAM Bank + * @retval None + */ +#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FSMC_BCRx_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__ FSMC_NORSRAM Instance + * @param __BANK__ FSMC_NORSRAM Bank + * @retval None + */ +#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FSMC_BCRx_MBKEN) + +/** + * @} + */ +#endif /* FSMC_BANK1 */ + +#if defined(FSMC_BANK3) +/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ + +/** + * @brief Enable the NAND device access. + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @retval None + */ +#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \ + ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN)) + +/** + * @brief Disable the NAND device access. + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @retval None + */ +#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ + CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) + +/** + * @} + */ +#endif + +#if defined(FSMC_BANK4) +/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros + * @brief macros to handle PCCARD read/write operations + * @{ + */ +/** + * @brief Enable the PCCARD device access. + * @param __INSTANCE__ FSMC_PCCARD Instance + * @retval None + */ +#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN) + +/** + * @brief Disable the PCCARD device access. + * @param __INSTANCE__ FSMC_PCCARD Instance + * @retval None + */ +#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN) +/** + * @} + */ + +#endif +#if defined(FSMC_BANK3) +/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ + */ + +/** + * @brief Enable the NAND device interrupt. + * @param __INSTANCE__ FSMC_NAND instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) + +/** + * @brief Disable the NAND device interrupt. + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) + +/** + * @brief Get flag status of the NAND device. + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) + +/** + * @brief Clear flag status of the NAND device. + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) + +/** + * @} + */ +#endif /* FSMC_BANK3 */ + +#if defined(FSMC_BANK4) +/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt + * @brief macros to handle PCCARD interrupts + * @{ + */ + +/** + * @brief Enable the PCCARD device interrupt. + * @param __INSTANCE__ FSMC_PCCARD instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) + +/** + * @brief Disable the PCCARD device interrupt. + * @param __INSTANCE__ FSMC_PCCARD instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the PCCARD device. + * @param __INSTANCE__ FSMC_PCCARD instance + * @param __FLAG__ FSMC_PCCARD flag + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the PCCARD device. + * @param __INSTANCE__ FSMC_PCCARD instance + * @param __FLAG__ FSMC_PCCARD flag + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions + * @{ + */ + +#if defined(FSMC_BANK1) +/** @defgroup FSMC_LL_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ +#endif /* FSMC_BANK1 */ + +#if defined(FSMC_BANK3) +/** @defgroup FSMC_LL_NAND NAND + * @{ + */ +/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions + * @{ + */ +HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); +/** + * @} + */ +/** + * @} + */ +#endif /* FSMC_BANK3 */ + +#if defined(FSMC_BANK4) +/** @defgroup FSMC_LL_PCCARD PCCARD + * @{ + */ +/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); +/** + * @} + */ +/** + * @} + */ +#endif /* FSMC_BANK4 */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_LL_FSMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c new file mode 100644 index 0000000..8f22029 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c @@ -0,0 +1,1112 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_sram.c + * @author MCD Application Team + * @brief SRAM HAL module driver. + * This file provides a generic firmware to drive SRAM memories + * mounted as external device. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SRAM memories. It uses the FSMC layer functions to interface + with SRAM devices. + The following sequence should be followed to configure the FSMC to interface + with SRAM/PSRAM memories: + + (#) Declare a SRAM_HandleTypeDef handle structure, for example: + SRAM_HandleTypeDef hsram; and: + + (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SRAM device + + (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined + base register instance for NOR or SRAM extended mode + + (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended + mode timings; for example: + FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() + (##) Control register configuration using the FSMC NORSRAM interface function + FSMC_NORSRAM_Init() + (##) Timing register configuration using the FSMC NORSRAM interface function + FSMC_NORSRAM_Timing_Init() + (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function + FSMC_NORSRAM_Extended_Timing_Init() + (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE() + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access + (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ + HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation + + (#) You can continuously monitor the SRAM device HAL state by calling the function + HAL_SRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SRAM MspInit. + (+) MspDeInitCallback : SRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) MspInitCallback : SRAM MspInit. + (+) MspDeInitCallback : SRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init + and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit + or @ref HAL_SRAM_Init function. + + When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +#if defined(FSMC_BANK1) + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_SRAM_MODULE_ENABLED + +/** @defgroup SRAM SRAM + * @brief SRAM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SRAM_DMAError(DMA_HandleTypeDef *hdma); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * + @verbatim + ============================================================================== + ##### SRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize/de-initialize + the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SRAM device initialization sequence + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + /* Check the SRAM handle parameter */ + if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE)) + { + return HAL_ERROR; + } + + if (hsram->State == HAL_SRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsram->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + if (hsram->MspInitCallback == NULL) + { + hsram->MspInitCallback = HAL_SRAM_MspInit; + } + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsram->MspInitCallback(hsram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SRAM_MspInit(hsram); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + } + + /* Initialize SRAM control Interface */ + (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + + /* Initialize SRAM timing Interface */ + (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + + /* Initialize SRAM extended mode timing Interface */ + (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + + /* Initialize the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Performs the SRAM device De-initialization sequence. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) +{ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + if (hsram->MspDeInitCallback == NULL) + { + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsram->MspDeInitCallback(hsram); +#else + /* De-Initialize the low level hardware (MSP) */ + HAL_SRAM_MspDeInit(hsram); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + + /* Configure the SRAM registers with their reset values */ + (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + + /* Reset the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief SRAM MSP Init. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SRAM MSP DeInit. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 8-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 16-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + uint8_t limit; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Read data from memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + psramaddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 16-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + uint8_t limit; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Write data to memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *psramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U); + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 32-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 32-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SRAM memory using DMA transfer. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SRAM_STATE_READY) + { + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + } + else + { + hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; + } + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a Words data buffer to SRAM memory using DMA transfer. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SRAM Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} + +/** + * @brief Unregister a User SRAM Callback + * SRAM Callback is redirected to the weak (surcharged) predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (state == HAL_SRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} + +/** + * @brief Register a User SRAM Callback for DMA transfers + * To be used instead of the weak (surcharged) predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### SRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SRAM write operation. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) +{ + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Enable write operation */ + (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically SRAM write operation. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) +{ + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Disable write operation */ + (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SRAM controller state + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL state + */ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +{ + return hsram->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_ERROR; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferErrorCallback(hdma); +#else + HAL_SRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_SRAM_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* FSMC_BANK1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c new file mode 100644 index 0000000..dc1cf50 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c @@ -0,0 +1,1014 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_fsmc.c + * @author MCD Application Team + * @brief FSMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FSMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FSMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FSMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND/PC Card memory controller + + [..] The FSMC functional block makes the interface with synchronous and asynchronous static + memories and 16-bit PC memory cards. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FSMC performs + only one access at a time to an external device. + The main features of the FSMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) 16-bit PC Card compatible devices + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) + +/** @defgroup FSMC_LL FSMC Low Layer + * @brief FSMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FSMC registers bit mask --------------------------- */ + +#if defined(FSMC_BANK1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\ + FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\ + FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\ + FSMC_BTRx_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#if defined(FSMC_BWTRx_BUSTURN) +#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\ + FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\ + FSMC_BWTRx_ACCMOD)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\ + FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD |\ + FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT)) +#endif /* FSMC_BWTRx_BUSTURN */ +#endif /* FSMC_BANK1 */ +#if defined(FSMC_BANK3) + +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \ + FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \ + FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \ + FSMC_PCRx_TAR | FSMC_PCRx_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\ + FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\ + FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx)) + +#endif /* FSMC_BANK3 */ +#if defined(FSMC_BANK4) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \ + FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \ + FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \ + FSMC_PCR4_TAR | FSMC_PCR4_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\ + FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\ + FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4)) + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ + FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) + +#endif /* FSMC_BANK4 */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions + * @{ + */ + +#if defined(FSMC_BANK1) + +/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() + (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() + (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() + (+) FSMC NORSRAM bank extended timing configuration using the function + FSMC_NORSRAM_Extended_Timing_Init() + (+) FSMC NORSRAM bank enable/disable write operation using the functions + FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() + +@endverbatim + * @{ + */ + +/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FSMC NORSRAM interface + (+) De-initialize the FSMC NORSRAM interface + (+) Configure the FSMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FSMC_NORSRAM device according to the specified + * control parameters in the FSMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FSMC_MUX(Init->DataAddressMux)); + assert_param(IS_FSMC_MEMORY(Init->MemoryType)); + assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR) + { + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->WrapMode; + btcr_reg |= Init->PageSize; + + mask = (FSMC_BCRx_MBKEN | + FSMC_BCRx_MUXEN | + FSMC_BCRx_MTYP | + FSMC_BCRx_MWID | + FSMC_BCRx_FACCEN | + FSMC_BCRx_BURSTEN | + FSMC_BCRx_WAITPOL | + FSMC_BCRx_WAITCFG | + FSMC_BCRx_WREN | + FSMC_BCRx_WAITEN | + FSMC_BCRx_EXTMOD | + FSMC_BCRx_ASYNCWAIT | + FSMC_BCRx_CBURSTRW); + + mask |= FSMC_BCRx_WRAPMOD; + mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */ + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + + + return HAL_OK; +} + +/** + * @brief DeInitialize the FSMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Disable the FSMC_NORSRAM device */ + __FSMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FSMC_NORSRAM device */ + /* FSMC_NORSRAM_BANK1 */ + if (Bank == FSMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DBU; + } + /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2U; + } + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + + return HAL_OK; +} + +/** + * @brief Initialize the FSMC_NORSRAM Timing according to the specified + * parameters in the FSMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Set FSMC_NORSRAM device timing parameters */ + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | + (Timing->AccessMode))); + + return HAL_OK; +} + +/** + * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FSMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @param ExtendedMode FSMC Extended Mode + * This parameter can be one of the following values: + * @arg FSMC_EXTENDED_MODE_DISABLE + * @arg FSMC_EXTENDED_MODE_ENABLE + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ + /* Check the parameters */ + assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); +#if defined(FSMC_BWTRx_BUSTURN) + assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); +#else + assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); +#endif /* FSMC_BWTRx_BUSTURN */ + assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ +#if defined(FSMC_BWTRx_BUSTURN) + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos))); +#else + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | + Timing->AccessMode | + (((Timing->CLKDivision) - 1U) << FSMC_BWTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos))); +#endif /* FSMC_BWTRx_BUSTURN */ + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFFU; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FSMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FSMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FSMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FSMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* FSMC_BANK1 */ + +#if defined(FSMC_BANK3) + +/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FSMC NAND banks in order + to run the NAND external devices. + + (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() + (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() + (+) FSMC NAND bank common space timing configuration using the function + FSMC_NAND_CommonSpace_Timing_Init() + (+) FSMC NAND bank attribute space timing configuration using the function + FSMC_NAND_AttributeSpace_Timing_Init() + (+) FSMC NAND bank enable/disable ECC correction feature using the functions + FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() + (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FSMC NAND interface + (+) De-initialize the FSMC NAND interface + (+) Configure the FSMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FSMC_NAND device according to the specified + * control parameters in the FSMC_NAND_HandleTypeDef + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); + + /* Set NAND device control parameters */ + if (Init->NandBank == FSMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos))); + } + else + { + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos))); + } + + return HAL_OK; +} + +/** + * @brief Initializes the FSMC_NAND Common space Timing according to the specified + * parameters in the FSMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + + /* Set FSMC_NAND device timing parameters */ + if (Bank == FSMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos))); + } + else + { + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos))); + } + + return HAL_OK; +} + +/** + * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified + * parameters in the FSMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + + /* Set FSMC_NAND device timing parameters */ + if (Bank == FSMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); + } + else + { + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); + } + + return HAL_OK; +} + +/** + * @brief DeInitializes the FSMC_NAND device + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FSMC_NAND_DISABLE(Device, Bank); + + /* De-initialize the NAND Bank */ + if (Bank == FSMC_NAND_BANK2) + { + /* Set the FSMC_NAND_BANK2 registers to their reset values */ + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FSMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FSMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FSMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ + if (Bank == FSMC_NAND_BANK2) + { + SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN); + } + else + { + SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN); + } + + return HAL_OK; +} + + +/** + * @brief Disables dynamically FSMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ + if (Bank == FSMC_NAND_BANK2) + { + CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN); + } + else + { + CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN); + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically FSMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FIFO is empty */ + while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + if (Bank == FSMC_NAND_BANK2) + { + /* Get the ECCR2 register value */ + *ECCval = (uint32_t)Device->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + *ECCval = (uint32_t)Device->ECCR3; + } + + return HAL_OK; +} + +/** + * @} + */ +#endif /* FSMC_BANK3 */ + +#if defined(FSMC_BANK4) + +/** @addtogroup FSMC_LL_PCCARD + * @brief PCCARD Controller functions + * + @verbatim + ============================================================================== + ##### How to use PCCARD device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FSMC PCCARD bank in order + to run the PCCARD/compact flash external devices. + + (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() + (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() + (+) FSMC PCCARD bank common space timing configuration using the function + FSMC_PCCARD_CommonSpace_Timing_Init() + (+) FSMC PCCARD bank attribute space timing configuration using the function + FSMC_PCCARD_AttributeSpace_Timing_Init() + (+) FSMC PCCARD bank IO space timing configuration using the function + FSMC_PCCARD_IOSpace_Timing_Init() +@endverbatim + * @{ + */ + +/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FSMC PCCARD interface + (+) De-initialize the FSMC PCCARD interface + (+) Configure the FSMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FSMC_PCCARD device according to the specified + * control parameters in the FSMC_PCCARD_HandleTypeDef + * @param Device Pointer to PCCARD device instance + * @param Init Pointer to PCCARD Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_BANK3) + assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); +#endif /* FSMC_BANK3 */ + + /* Set FSMC_PCCARD device control parameters */ + MODIFY_REG(Device->PCR4, + (FSMC_PCRx_PTYP | + FSMC_PCRx_PWAITEN | + FSMC_PCRx_PWID | + FSMC_PCRx_TCLR | + FSMC_PCRx_TAR), + (FSMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) | + (Init->TARSetupTime << FSMC_PCRx_TAR_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified + * parameters in the FSMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) +{ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_BANK3) + assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_BANK3 */ + + /* Set PCCARD timing parameters */ + MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified + * parameters in the FSMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) +{ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_BANK3) + assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_BANK3 */ + + /* Set PCCARD timing parameters */ + MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified + * parameters in the FSMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) +{ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_BANK3) + assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_BANK3 */ + + /* Set FSMC_PCCARD device timing parameters */ + MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, + (Timing->SetupTime | + (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos))); + + return HAL_OK; +} + +/** + * @brief DeInitializes the FSMC_PCCARD device + * @param Device Pointer to PCCARD device instance + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) +{ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); + + /* Disable the FSMC_PCCARD device */ + __FSMC_PCCARD_DISABLE(Device); + + /* De-initialize the FSMC_PCCARD device */ + Device->PCR4 = 0x00000018U; + Device->SR4 = 0x00000040U; + Device->PMEM4 = 0xFCFCFCFCU; + Device->PATT4 = 0xFCFCFCFCU; + Device->PIO4 = 0xFCFCFCFCU; + + return HAL_OK; +} + +/** + * @} + */ +#endif /* FSMC_BANK4 */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/HW_Devices/LCD.c b/HW_Devices/LCD.c new file mode 100644 index 0000000..4eebe8c --- /dev/null +++ b/HW_Devices/LCD.c @@ -0,0 +1,847 @@ +/* + * LCD.c + * + * Created on: Aug 6, 2021 + * Author: wuwenfeng + */ +#include "LCD.h" + +_lcd_dev lcddev; //管理LCD重要参数 +//**************************************************几种快速接口 +//写寄存器函数 +//regval:寄存器值 +void LCD_WR_REG(uint16_t regval) +{ + LCD_REG_ADDRESS=regval;//写入要写的寄存器序号 +} +//写LCD数据 +//data:要写入的值 +void LCD_WR_DATA(uint16_t data) +{ + LCD_DATA_ADDRESS=data; +} +//读LCD数据 +//返回值:读到的值 +uint16_t LCD_RD_DATA(void) +{ + return LCD_DATA_ADDRESS; +} +//写寄存器 +//LCD_Reg:寄存器地址 +//LCD_RegValue:要写入的数据 +void LCD_WriteReg(uint16_t LCD_Reg, uint16_t LCD_RegValue) +{ + LCD_REG_ADDRESS = LCD_Reg; //写入要写的寄存器序号 + LCD_DATA_ADDRESS = LCD_RegValue;//写入数据 +} +//读寄存器 +//LCD_Reg:寄存器地址 +//返回值:读到的数据 +uint16_t LCD_ReadReg(uint16_t LCD_Reg) +{ + LCD_REG_ADDRESS=LCD_Reg; //写入要读的寄存器序号 + //delay_us(5); + return LCD_DATA_ADDRESS; //返回读到的值 +} +//**************************************************************LCD底层 + +//常用ASCII表 +//偏移量32 +//ASCII字符集 +//偏移量32 +//大小:12*6 +const unsigned char asc2_1206[95][12]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/ +{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/ +{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/ +{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/ +{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/ +{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/ +{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/ +{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/ +{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/ +{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/ +{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/ +{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/ +{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/ +{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/ +{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/ +{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/ +{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/ +{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/ +{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/ +{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/ +{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/ +{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/ +{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/ +{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/ +{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/ +{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/ +{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/ +{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/ +{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/ +{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/ +{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/ +{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/ +{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/ +{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/ +{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/ +{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/ +{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/ +{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/ +{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/ +{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/ +{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/ +{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/ +{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/ +{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/ +{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/ +{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/ +{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/ +{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/ +{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/ +{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/ +{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/ +{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/ +{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/ +{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/ +{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/ +}; +const unsigned char asc2_1608[95][16]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/ +{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/ +{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/ +{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/ +{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/ +{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/ +{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/ +{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/ +{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/ +{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/ +{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/ +{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/ +{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/ +{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/ +{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/ +{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/ +{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/ +{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/ +{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/ +{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/ +{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/ +{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/ +{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/ +{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/ +{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/ +{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/ +{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/ +{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/ +{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/ +{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/ +{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/ +{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/ +{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/ +{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/ +{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/ +{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/ +{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/ +{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/ +{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/ +{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/ +{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/ +{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/ +{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/ +{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/ +{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/ +{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/ +}; + +_lcd_dev lcddev; +//LCD开启显示 +void LCD_DisplayOn(void) +{ + if(lcddev.id==0X9341||lcddev.id==0X6804||lcddev.id==0X5310)LCD_WR_REG(0X29); //开启显示 + else LCD_WriteReg(R7,0x0173); //开启显示 +} +//LCD关闭显示 +void LCD_DisplayOff(void) +{ + if(lcddev.id==0X9341||lcddev.id==0X6804||lcddev.id==0X5310)LCD_WR_REG(0X28); //关闭显示 + else LCD_WriteReg(R7,0x0);//关闭显示 +} +//设置LCD的自动扫描方向 +//注意:其他函数可能会受到此函数设置的影响(尤其是9341/6804这两个奇葩), +//所以,一般设置为L2R_U2D即可,如果设置为其他扫描方式,可能导致显示不正常. +//dir:0~7,代表8个方向(具体定义见lcd.h) +//9320/9325/9328/4531/4535/1505/b505/8989/5408/9341/5310等IC已经实际测试 +void LCD_Scan_Dir(uint8_t dir) +{ + uint16_t regval=0; + uint8_t dirreg=0; + uint16_t temp; + if(lcddev.dir==1&&lcddev.id!=0X6804)//横屏时，对6804不改变扫描方向！ + { + switch(dir)//方向转换 + { + case 0:dir=6;break; + case 1:dir=7;break; + case 2:dir=4;break; + case 3:dir=5;break; + case 4:dir=1;break; + case 5:dir=0;break; + case 6:dir=3;break; + case 7:dir=2;break; + } + } + if(lcddev.id==0x9341||lcddev.id==0X6804||lcddev.id==0X5310)//9341/6804/5310,很特殊 + { + switch(dir) + { + case L2R_U2D://从左到右,从上到下 + regval|=(0<<7)|(0<<6)|(0<<5); + break; + case L2R_D2U://从左到右,从下到上 + regval|=(1<<7)|(0<<6)|(0<<5); + break; + case R2L_U2D://从右到左,从上到下 + regval|=(0<<7)|(1<<6)|(0<<5); + break; + case R2L_D2U://从右到左,从下到上 + regval|=(1<<7)|(1<<6)|(0<<5); + break; + case U2D_L2R://从上到下,从左到右 + regval|=(0<<7)|(0<<6)|(1<<5); + break; + case U2D_R2L://从上到下,从右到左 + regval|=(0<<7)|(1<<6)|(1<<5); + break; + case D2U_L2R://从下到上,从左到右 + regval|=(1<<7)|(0<<6)|(1<<5); + break; + case D2U_R2L://从下到上,从右到左 + regval|=(1<<7)|(1<<6)|(1<<5); + break; + } + dirreg=0X36; + if(lcddev.id!=0X5310)regval|=0X08;//5310不需要BGR + if(lcddev.id==0X6804)regval|=0x02;//6804的BIT6和9341的反了 + LCD_WriteReg(dirreg,regval); + if((regval&0X20)||lcddev.dir==1) + { + if(lcddev.widthlcddev.height)//交换X,Y + { + temp=lcddev.width; + lcddev.width=lcddev.height; + lcddev.height=temp; + } + } + LCD_WR_REG(lcddev.setxcmd); + LCD_WR_DATA(0);LCD_WR_DATA(0); + LCD_WR_DATA((lcddev.width-1)>>8);LCD_WR_DATA((lcddev.width-1)&0XFF); + LCD_WR_REG(lcddev.setycmd); + LCD_WR_DATA(0);LCD_WR_DATA(0); + LCD_WR_DATA((lcddev.height-1)>>8);LCD_WR_DATA((lcddev.height-1)&0XFF); + }else + { + switch(dir) + { + case L2R_U2D://从左到右,从上到下 + regval|=(1<<5)|(1<<4)|(0<<3); + break; + case L2R_D2U://从左到右,从下到上 + regval|=(0<<5)|(1<<4)|(0<<3); + break; + case R2L_U2D://从右到左,从上到下 + regval|=(1<<5)|(0<<4)|(0<<3); + break; + case R2L_D2U://从右到左,从下到上 + regval|=(0<<5)|(0<<4)|(0<<3); + break; + case U2D_L2R://从上到下,从左到右 + regval|=(1<<5)|(1<<4)|(1<<3); + break; + case U2D_R2L://从上到下,从右到左 + regval|=(1<<5)|(0<<4)|(1<<3); + break; + case D2U_L2R://从下到上,从左到右 + regval|=(0<<5)|(1<<4)|(1<<3); + break; + case D2U_R2L://从下到上,从右到左 + regval|=(0<<5)|(0<<4)|(1<<3); + break; + } + if(lcddev.id==0x8989)//8989 IC + { + dirreg=0X11; + regval|=0X6040; //65K + }else//其他驱动IC + { + dirreg=0X03; + regval|=1<<12; + } + LCD_WriteReg(dirreg,regval); + } +} +//设置LCD显示方向 +//dir:0,竖屏；1,横屏 +void LCD_Display_Dir(uint8_t dir) +{ + if(dir==0) //竖屏 + { + lcddev.dir=0; //竖屏 + lcddev.width=240; + lcddev.height=320; + if(lcddev.id==0X9341||lcddev.id==0X6804||lcddev.id==0X5310) + { + lcddev.wramcmd=0X2C; + lcddev.setxcmd=0X2A; + lcddev.setycmd=0X2B; + if(lcddev.id==0X6804||lcddev.id==0X5310) + { + lcddev.width=320; + lcddev.height=480; + } + }else if(lcddev.id==0X8989) + { + lcddev.wramcmd=R34; + lcddev.setxcmd=0X4E; + lcddev.setycmd=0X4F; + }else + { + lcddev.wramcmd=R34; + lcddev.setxcmd=R32; + lcddev.setycmd=R33; + } + }else //横屏 + { + lcddev.dir=1; //横屏 + lcddev.width=320; + lcddev.height=240; + if(lcddev.id==0X9341||lcddev.id==0X5310) + { + lcddev.wramcmd=0X2C; + lcddev.setxcmd=0X2A; + lcddev.setycmd=0X2B; + }else if(lcddev.id==0X6804) + { + lcddev.wramcmd=0X2C; + lcddev.setxcmd=0X2B; + lcddev.setycmd=0X2A; + }else if(lcddev.id==0X8989) + { + lcddev.wramcmd=R34; + lcddev.setxcmd=0X4F; + lcddev.setycmd=0X4E; + }else + { + lcddev.wramcmd=R34; + lcddev.setxcmd=R33; + lcddev.setycmd=R32; + } + if(lcddev.id==0X6804||lcddev.id==0X5310) + { + lcddev.width=480; + lcddev.height=320; + } + } + LCD_Scan_Dir(DFT_SCAN_DIR); //默认扫描方向 +} + +//初始化lcd +//该初始化函数可以初始化各种液晶! +void LCDx_Init(void) +{ + + + HAL_Delay(50); // delay 50 ms + LCD_WriteReg(0x0000,0x0001); + HAL_Delay(50); // delay 50 ms + lcddev.id = LCD_ReadReg(0x0000); + + + LCD_WriteReg(0x00E5,0x78F0); + LCD_WriteReg(0x0001,0x0100); + LCD_WriteReg(0x0002,0x0700); + LCD_WriteReg(0x0003,0x1030); + LCD_WriteReg(0x0004,0x0000); + LCD_WriteReg(0x0008,0x0202); + LCD_WriteReg(0x0009,0x0000); + LCD_WriteReg(0x000A,0x0000); + LCD_WriteReg(0x000C,0x0000); + LCD_WriteReg(0x000D,0x0000); + LCD_WriteReg(0x000F,0x0000); + //power on sequence VGHVGL + LCD_WriteReg(0x0010,0x0000); + LCD_WriteReg(0x0011,0x0007); + LCD_WriteReg(0x0012,0x0000); + LCD_WriteReg(0x0013,0x0000); + LCD_WriteReg(0x0007,0x0000); + //vgh + LCD_WriteReg(0x0010,0x1690); + LCD_WriteReg(0x0011,0x0227); + //delayms(100); + //vregiout + LCD_WriteReg(0x0012,0x009D); //0x001b + //delayms(100); + //vom amplitude + LCD_WriteReg(0x0013,0x1900); + //delayms(100); + //vom H + LCD_WriteReg(0x0029,0x0025); + LCD_WriteReg(0x002B,0x000D); + //gamma + LCD_WriteReg(0x0030,0x0007); + LCD_WriteReg(0x0031,0x0303); + LCD_WriteReg(0x0032,0x0003);// 0006 + LCD_WriteReg(0x0035,0x0206); + LCD_WriteReg(0x0036,0x0008); + LCD_WriteReg(0x0037,0x0406); + LCD_WriteReg(0x0038,0x0304);//0200 + LCD_WriteReg(0x0039,0x0007); + LCD_WriteReg(0x003C,0x0602);// 0504 + LCD_WriteReg(0x003D,0x0008); + //ram + LCD_WriteReg(0x0050,0x0000); + LCD_WriteReg(0x0051,0x00EF); + LCD_WriteReg(0x0052,0x0000); + LCD_WriteReg(0x0053,0x013F); + LCD_WriteReg(0x0060,0xA700); + LCD_WriteReg(0x0061,0x0001); + LCD_WriteReg(0x006A,0x0000); + // + LCD_WriteReg(0x0080,0x0000); + LCD_WriteReg(0x0081,0x0000); + LCD_WriteReg(0x0082,0x0000); + LCD_WriteReg(0x0083,0x0000); + LCD_WriteReg(0x0084,0x0000); + LCD_WriteReg(0x0085,0x0000); + // + LCD_WriteReg(0x0090,0x0010); + LCD_WriteReg(0x0092,0x0600); + + LCD_WriteReg(0x0007,0x0133); + LCD_WriteReg(0x00,0x0022);// + + + LCD_Display_Dir(1); //默认为h屏 + + LCD_BL(0); + +} +//***********************************************************打点 读点 什么的 +//设置光标位置 +//Xpos:横坐标 +//Ypos:纵坐标 +void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos) +{ + if(lcddev.id==0X9341||lcddev.id==0X5310) + { + LCD_WR_REG(lcddev.setxcmd); + LCD_WR_DATA(Xpos>>8); + LCD_WR_DATA(Xpos&0XFF); + LCD_WR_REG(lcddev.setycmd); + LCD_WR_DATA(Ypos>>8); + LCD_WR_DATA(Ypos&0XFF); + }else if(lcddev.id==0X6804) + { + if(lcddev.dir==1)Xpos=lcddev.width-1-Xpos;//横屏时处理 + LCD_WR_REG(lcddev.setxcmd); + LCD_WR_DATA(Xpos>>8); + LCD_WR_DATA(Xpos&0XFF); + LCD_WR_REG(lcddev.setycmd); + LCD_WR_DATA(Ypos>>8); + LCD_WR_DATA(Ypos&0XFF); + }else + { + if(lcddev.dir==1)Xpos=lcddev.width-1-Xpos;//横屏其实就是调转x,y坐标 + LCD_WriteReg(lcddev.setxcmd, Xpos); + LCD_WriteReg(lcddev.setycmd, Ypos); + } +} + +//快速画点 +//x,y:坐标 +//color:颜色 +void LCD_Fast_DrawPoint(uint16_t x,uint16_t y,uint16_t color) +{ + if(lcddev.id==0X9341||lcddev.id==0X5310) + { + LCD_WR_REG(lcddev.setxcmd); + LCD_WR_DATA(x>>8); + LCD_WR_DATA(x&0XFF); + LCD_WR_REG(lcddev.setycmd); + LCD_WR_DATA(y>>8); + LCD_WR_DATA(y&0XFF); + }else if(lcddev.id==0X6804) + { + if(lcddev.dir==1)x=lcddev.width-1-x;//横屏时处理 + LCD_WR_REG(lcddev.setxcmd); + LCD_WR_DATA(x>>8); + LCD_WR_DATA(x&0XFF); + LCD_WR_REG(lcddev.setycmd); + LCD_WR_DATA(y>>8); + LCD_WR_DATA(y&0XFF); + }else + { + if(lcddev.dir==1)x=lcddev.width-1-x;//横屏其实就是调转x,y坐标 + LCD_WriteReg(lcddev.setxcmd,x); + LCD_WriteReg(lcddev.setycmd,y); + } + LCD_REG_ADDRESS=lcddev.wramcmd; + LCD_DATA_ADDRESS=color; +} +//画点 +//x,y:坐标 +//POINT_COLOR:此点的颜色 +void LCD_set_dot(uint16_t x,uint16_t y,uint16_t color) +{ + LCD_SetCursor(x,y); //设置光标位置 + LCD_REG_ADDRESS=lcddev.wramcmd; //开始写入GRAM + LCD_DATA_ADDRESS=color; +} + +//清屏函数 +//color:要清屏的填充色 +void LCD_Clear(uint16_t color) +{ + uint32_t index=0; + uint32_t totalpoint=lcddev.width; + totalpoint*=lcddev.height; //得到总点数 + if((lcddev.id==0X6804)&&(lcddev.dir==1))//6804横屏的时候特殊处理 + { + lcddev.dir=0; + lcddev.setxcmd=0X2A; + lcddev.setycmd=0X2B; + LCD_SetCursor(0x00,0x0000); //设置光标位置 + lcddev.dir=1; + lcddev.setxcmd=0X2B; + lcddev.setycmd=0X2A; + }else LCD_SetCursor(0x00,0x0000); //设置光标位置 + LCD_REG_ADDRESS=lcddev.wramcmd; //开始写入GRAM + for(index=0;index>0)&0x1f; + g=(c>>5)&0x3f; + r=(c>>11)&0x1f; + rgb=(b<<11)+(g<<5)+(r<<0); + return(rgb); +} +//读取个某点的颜色值 +//x,y:坐标 +//返回值:此点的颜色 +uint16_t LCD_ReadPoint(uint16_t x,uint16_t y) +{ + uint16_t r=0,g=0,b=0; + if(x>=lcddev.width||y>=lcddev.height)return 0; //超过了范围,直接返回 + LCD_SetCursor(x,y); + if(lcddev.id==0X9341||lcddev.id==0X6804||lcddev.id==0X5310)LCD_WR_REG(0X2E);//9341/6804/3510 发送读GRAM指令 + else LCD_WR_REG(R34); //其他IC发送读GRAM指令 + //if(lcddev.id==0X9320)opt_delay(2); //FOR 9320,延时2us + if(LCD_DATA_ADDRESS)r=0; //dummy Read + //opt_delay(2); + r=LCD_DATA_ADDRESS; //实际坐标颜色 + if(lcddev.id==0X9341||lcddev.id==0X5310) //9341/NT35310要分2次读出 + { + //opt_delay(2); + b=LCD_DATA_ADDRESS; + g=r&0XFF;//对于9341/5310,第一次读取的是RG的值,R在前,G在后,各占8位 + g<<=8; + }else if(lcddev.id==0X6804)r=LCD_DATA_ADDRESS; //6804第二次读取的才是真实值 + if(lcddev.id==0X9325||lcddev.id==0X4535||lcddev.id==0X4531||lcddev.id==0X8989||lcddev.id==0XB505)return r;//这几种IC直接返回颜色值 + else if(lcddev.id==0X9341||lcddev.id==0X5310)return (((r>>11)<<11)|((g>>10)<<5)|(b>>11)); //ILI9341/NT35310需要公式转换一下 + else return LCD_BGR2RGB(r); //其他IC +} + + +//***********************************2D +//画线 +//x1,y1:起点坐标 +//x2,y2:终点坐标 +void LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2,uint16_t color) +{ + uint16_t t; + int xerr=0,yerr=0,delta_x,delta_y,distance; + int incx,incy,uRow,uCol; + delta_x=x2-x1; //计算坐标增量 + delta_y=y2-y1; + uRow=x1; + uCol=y1; + if(delta_x>0)incx=1; //设置单步方向 + else if(delta_x==0)incx=0;//垂直线 + else {incx=-1;delta_x=-delta_x;} + if(delta_y>0)incy=1; + else if(delta_y==0)incy=0;//水平线 + else{incy=-1;delta_y=-delta_y;} + if( delta_x>delta_y)distance=delta_x; //选取基本增量坐标轴 + else distance=delta_y; + for(t=0;t<=distance+1;t++ )//画线输出 + { + LCD_set_dot(uRow,uCol,color);//画点 + xerr+=delta_x ; + yerr+=delta_y ; + if(xerr>distance) + { + xerr-=distance; + uRow+=incx; + } + if(yerr>distance) + { + yerr-=distance; + uCol+=incy; + } + } +} + +//在指定位置画一个指定大小的圆 +//(x,y):中心点 +//r :半径 +void Draw_Circle(uint16_t x0,uint16_t y0,uint16_t r,uint16_t color) +{ + int a,b; + int di; + a=0;b=r; + di=3-(r<<1); //判断下个点位置的标志 + while(a<=b) + { + LCD_set_dot(x0+a,y0-b,color); //5 + LCD_set_dot(x0+b,y0-a,color); //0 + LCD_set_dot(x0+b,y0+a,color); //4 + LCD_set_dot(x0+a,y0+b,color); //6 + LCD_set_dot(x0-a,y0+b,color); //1 + LCD_set_dot(x0-b,y0+a,color); + LCD_set_dot(x0-a,y0-b,color); //2 + LCD_set_dot(x0-b,y0-a,color); //7 + a++; + //使用Bresenham算法画圆 + if(di<0)di +=4*a+6; + else + { + di+=10+4*(a-b); + b--; + } + } +} + +//在指定位置显示一个字符 +//x,y:起始坐标 +//num:要显示的字符:" "--->"~" +//size:字体大小 12/16 +//mode:叠加方式(1)还是非叠加方式(0) + +void LCD_ShowChar(uint16_t x,uint16_t y,uint8_t num,uint8_t size,uint16_t bg,uint16_t color) +{ + uint8_t temp,t1,t; + uint16_t y0=y; + + //设置窗口 + num=num-' ';//得到偏移后的值 + + for(t=0;t=lcddev.width){return;}//超区域了 + if((y-y0)==size) + { + y=y0; + x++; + if(x>=lcddev.width){return;}//超区域了 + break; + } + } + } + + + +} + +//显示字符串 +//x,y:起点坐标 +//width,height:区域大小 +//size:字体大小 +//*p:字符串起始地址 + +void LCD_ShowString(uint16_t x,uint16_t y,uint8_t *p,uint8_t size,uint16_t bg,uint16_t color) +{ + while(*p!='\0') + { + + if(x>=lcddev.width||*p=='\n') + { + x=0; + y+=size; + }else + { + LCD_ShowChar(x,y,*p,size,bg,color); + x+=(size/2); + } + p++; + + } +} + diff --git a/HW_Devices/LCD.h b/HW_Devices/LCD.h new file mode 100644 index 0000000..0fd8dcf --- /dev/null +++ b/HW_Devices/LCD.h @@ -0,0 +1,256 @@ +/* + * LCD.h + * + * Created on: Aug 6, 2021 + * Author: wuwenfeng + */ + +#ifndef LCD_H_ +#define LCD_H_ +#include "main.h" +#define LCD_BL(x) HAL_GPIO_WritePin(LCD_BL_GPIO_Port,LCD_BL_Pin,x) +//LCD重要参数集 +typedef struct +{ + uint16_t width; //LCD 宽度 + uint16_t height; //LCD 高度 + uint16_t id; //LCD ID + uint8_t dir; //横屏还是竖屏控制：0，竖屏；1，横屏。 + uint8_t wramcmd; //开始写gram指令 + uint8_t setxcmd; //设置x坐标指令 + uint8_t setycmd; //设置y坐标指令 +}_lcd_dev; + +extern _lcd_dev lcddev; //管理LCD重要参数 + +#define LCD_REG_ADDRESS *(__IO uint16_t *)(0x6C000000) +#define LCD_DATA_ADDRESS *(__IO uint16_t *)(0x6C000800) + +//扫描方向定义 +#define L2R_U2D 0 //从左到右,从上到下 +#define L2R_D2U 1 //从左到右,从下到上 +#define R2L_U2D 2 //从右到左,从上到下 +#define R2L_D2U 3 //从右到左,从下到上 + +#define U2D_L2R 4 //从上到下,从左到右 +#define U2D_R2L 5 //从上到下,从右到左 +#define D2U_L2R 6 //从下到上,从左到右 +#define D2U_R2L 7 //从下到上,从右到左 + +#define DFT_SCAN_DIR L2R_U2D //默认的扫描方向 + +#define COLOR_16 unsigned int +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define BLUE 0x001F +#define BRED 0XF81F +#define GRED 0XFFE0 +#define GBLUE 0X07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 +#define BROWN 0XBC40 //棕色 +#define BRRED 0XFC07 //棕红色 +#define GRAY 0X8430 //灰色 +//GUI颜色 + +#define DARKBLUE 0X01CF //深蓝色 +#define LIGHTBLUE 0X7D7C //浅蓝色 +#define GRAYBLUE 0X5458 //灰蓝色 +//以上三色为PANEL的颜色 + +#define LIGHTGREEN 0X841F //浅绿色 +//#define LIGHTGRAY 0XEF5B //浅灰色(PANNEL) +#define LGRAY 0XC618 //浅灰色(PANNEL),窗体背景色 + +#define LGRAYBLUE 0XA651 //浅灰蓝色(中间层颜色) +#define LBBLUE 0X2B12 //浅棕蓝色(选择条目的反色) +//9320/9325 LCD寄存器 +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R4 0x04 +#define R5 0x05 +#define R6 0x06 +#define R7 0x07 +#define R8 0x08 +#define R9 0x09 +#define R10 0x0A +#define R12 0x0C +#define R13 0x0D +#define R14 0x0E +#define R15 0x0F +#define R16 0x10 +#define R17 0x11 +#define R18 0x12 +#define R19 0x13 +#define R20 0x14 +#define R21 0x15 +#define R22 0x16 +#define R23 0x17 +#define R24 0x18 +#define R25 0x19 +#define R26 0x1A +#define R27 0x1B +#define R28 0x1C +#define R29 0x1D +#define R30 0x1E +#define R31 0x1F +#define R32 0x20 +#define R33 0x21 +#define R34 0x22 +#define R36 0x24 +#define R37 0x25 +#define R40 0x28 +#define R41 0x29 +#define R43 0x2B +#define R45 0x2D +#define R48 0x30 +#define R49 0x31 +#define R50 0x32 +#define R51 0x33 +#define R52 0x34 +#define R53 0x35 +#define R54 0x36 +#define R55 0x37 +#define R56 0x38 +#define R57 0x39 +#define R59 0x3B +#define R60 0x3C +#define R61 0x3D +#define R62 0x3E +#define R63 0x3F +#define R64 0x40 +#define R65 0x41 +#define R66 0x42 +#define R67 0x43 +#define R68 0x44 +#define R69 0x45 +#define R70 0x46 +#define R71 0x47 +#define R72 0x48 +#define R73 0x49 +#define R74 0x4A +#define R75 0x4B +#define R76 0x4C +#define R77 0x4D +#define R78 0x4E +#define R79 0x4F +#define R80 0x50 +#define R81 0x51 +#define R82 0x52 +#define R83 0x53 +#define R96 0x60 +#define R97 0x61 +#define R106 0x6A +#define R118 0x76 +#define R128 0x80 +#define R129 0x81 +#define R130 0x82 +#define R131 0x83 +#define R132 0x84 +#define R133 0x85 +#define R134 0x86 +#define R135 0x87 +#define R136 0x88 +#define R137 0x89 +#define R139 0x8B +#define R140 0x8C +#define R141 0x8D +#define R143 0x8F +#define R144 0x90 +#define R145 0x91 +#define R146 0x92 +#define R147 0x93 +#define R148 0x94 +#define R149 0x95 +#define R150 0x96 +#define R151 0x97 +#define R152 0x98 +#define R153 0x99 +#define R154 0x9A +#define R157 0x9D +#define R192 0xC0 +#define R193 0xC1 +#define R229 0xE5 + +//*************************************************** + + +//**************************************************几种快速接口 +//写寄存器函数 +//regval:寄存器值 +void LCD_WR_REG(uint16_t regval); +//写LCD数据 +//data:要写入的值 +void LCD_WR_DATA(uint16_t data); +//读LCD数据 +//返回值:读到的值 +uint16_t LCD_RD_DATA(void); +//写寄存器 +//LCD_Reg:寄存器地址 +//LCD_RegValue:要写入的数据 +void LCD_WriteReg(uint16_t LCD_Reg, uint16_t LCD_RegValue); +//读寄存器 +//LCD_Reg:寄存器地址 +//返回值:读到的数据 +uint16_t LCD_ReadReg(uint16_t LCD_Reg); +//初始化lcd +//该初始化函数可以初始化各种液晶! +void LCDx_Init(void); +//LCD开启显示 +void LCD_DisplayOn(void); +//LCD关闭显示 +void LCD_DisplayOff(void); +//设置光标位置 +//Xpos:横坐标 +//Ypos:纵坐标 +void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos); +//快速画点 +//x,y:坐标 +//color:颜色 +void LCD_Fast_DrawPoint(uint16_t x,uint16_t y,uint16_t color); +//画点 +//x,y:坐标 +//POINT_COLOR:此点的颜色 +void LCD_set_dot(uint16_t x,uint16_t y,uint16_t color); +//清屏函数 +//color:要清屏的填充色 +void LCD_Clear(uint16_t color); +//在指定区域内填充单个颜色 +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//color:要填充的颜色 +void LCD_Fill(uint16_t sx,uint16_t sy,uint16_t ex,uint16_t ey,uint16_t color); +//在指定区域内填充指定颜色块 +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//color:要填充的颜色 +void LCD_Color_Fill(uint16_t sx,uint16_t sy,uint16_t ex,uint16_t ey,const uint16_t *color); +//从ILI93xx读出的数据为GBR格式，而我们写入的时候为RGB格式。 +//通过该函数转换 +//c:GBR格式的颜色值 +//返回值：RGB格式的颜色值 +uint16_t LCD_BGR2RGB(uint16_t c); +//读取个某点的颜色值 +//x,y:坐标 +//返回值:此点的颜色 +uint16_t LCD_ReadPoint(uint16_t x,uint16_t y); +//显示字符串 +//x,y:起点坐标 +//width,height:区域大小 +//size:字体大小 +//*p:字符串起始地址 +//***********************************2D +void LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2,uint16_t color); +//在指定位置画一个指定大小的圆 +//(x,y):中心点 +//r :半径 +void Draw_Circle(uint16_t x0,uint16_t y0,uint16_t r,uint16_t color); + +void LCD_ShowString(uint16_t x,uint16_t y,uint8_t *p,uint8_t size,uint16_t bg,uint16_t color); + + + +#endif /* LCD_H_ */ diff --git a/README.md b/README.md deleted file mode 100644 index a58bb2c..0000000 --- a/README.md +++ /dev/null @@ -1,4 +0,0 @@ -## M3s_stm32 - -绠楁硶鍚堥泦缁冧範 - diff --git a/STM32F103ZETX_FLASH.ld b/STM32F103ZETX_FLASH.ld index 8e7a3c7..d977d8e 100644 --- a/STM32F103ZETX_FLASH.ld +++ b/STM32F103ZETX_FLASH.ld @@ -39,8 +39,8 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ +_Min_Heap_Size = 0x200 ; /* required amount of heap */ +_Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY diff --git a/SW_APPs/Main_APP.c b/SW_APPs/Main_APP.c new file mode 100644 index 0000000..17fcddd --- /dev/null +++ b/SW_APPs/Main_APP.c @@ -0,0 +1,20 @@ +/* + * Main_APP.c + * + * Created on: Aug 6, 2021 + * Author: wuwenfeng + */ +#include "LCD.h" + +void main_app() +{ + LCDx_Init(); + + while(1) + { + + + } + +} + diff --git a/SW_APPs/Main_APP.h b/SW_APPs/Main_APP.h new file mode 100644 index 0000000..8887003 --- /dev/null +++ b/SW_APPs/Main_APP.h @@ -0,0 +1,13 @@ +/* + * Main_APP.h + * + * Created on: Aug 6, 2021 + * Author: wuwenfeng + */ + +#ifndef MAIN_APP_H_ +#define MAIN_APP_H_ + +void main_app(); + +#endif /* MAIN_APP_H_ */ diff --git a/m3s Debug.launch b/m3s Debug.launch new file mode 100644 index 0000000..852998c --- /dev/null +++ b/m3s Debug.launch @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/m3s.ioc b/m3s.ioc index 8e045dd..bed174c 100644 --- a/m3s.ioc +++ b/m3s.ioc @@ -1,16 +1,44 @@ #MicroXplorer Configuration settings - do not modify +FSMC.AddressSetupTime1=0 +FSMC.BusTurnAroundDuration1=0 +FSMC.DataSetupTime1=1 +FSMC.IPParameters=AddressSetupTime1,DataSetupTime1,BusTurnAroundDuration1 File.Version=6 KeepUserPlacement=false Mcu.Family=STM32F1 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IPNb=3 +Mcu.IP0=FSMC +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IPNb=4 Mcu.Name=STM32F103Z(C-D-E)Tx Mcu.Package=LQFP144 -Mcu.Pin0=VP_SYS_VS_ND -Mcu.Pin1=VP_SYS_VS_Systick -Mcu.PinsNb=2 +Mcu.Pin0=OSC_IN +Mcu.Pin1=OSC_OUT +Mcu.Pin10=PE13 +Mcu.Pin11=PE14 +Mcu.Pin12=PE15 +Mcu.Pin13=PD8 +Mcu.Pin14=PD9 +Mcu.Pin15=PD10 +Mcu.Pin16=PD14 +Mcu.Pin17=PD15 +Mcu.Pin18=PD0 +Mcu.Pin19=PD1 +Mcu.Pin2=PB0 +Mcu.Pin20=PD4 +Mcu.Pin21=PD5 +Mcu.Pin22=PG12 +Mcu.Pin23=VP_SYS_VS_ND +Mcu.Pin24=VP_SYS_VS_Systick +Mcu.Pin3=PG0 +Mcu.Pin4=PE7 +Mcu.Pin5=PE8 +Mcu.Pin6=PE9 +Mcu.Pin7=PE10 +Mcu.Pin8=PE11 +Mcu.Pin9=PE12 +Mcu.PinsNb=25 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103ZETx @@ -27,6 +55,35 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +OSC_IN.Mode=HSE-External-Oscillator +OSC_IN.Signal=RCC_OSC_IN +OSC_OUT.Mode=HSE-External-Oscillator +OSC_OUT.Signal=RCC_OSC_OUT +PB0.GPIOParameters=GPIO_Label +PB0.GPIO_Label=LCD_BL +PB0.Locked=true +PB0.Signal=GPIO_Output +PD0.Signal=FSMC_D2_DA2 +PD1.Signal=FSMC_D3_DA3 +PD10.Signal=FSMC_D15_DA15 +PD14.Signal=FSMC_D0_DA0 +PD15.Signal=FSMC_D1_DA1 +PD4.Signal=FSMC_NOE +PD5.Signal=FSMC_NWE +PD8.Signal=FSMC_D13_DA13 +PD9.Signal=FSMC_D14_DA14 +PE10.Signal=FSMC_D7_DA7 +PE11.Signal=FSMC_D8_DA8 +PE12.Signal=FSMC_D9_DA9 +PE13.Signal=FSMC_D10_DA10 +PE14.Signal=FSMC_D11_DA11 +PE15.Signal=FSMC_D12_DA12 +PE7.Signal=FSMC_D4_DA4 +PE8.Signal=FSMC_D5_DA5 +PE9.Signal=FSMC_D6_DA6 +PG0.Signal=FSMC_A10 +PG12.Mode=NorPsramChipSelect4_1 +PG12.Signal=FSMC_NE4 PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false @@ -46,7 +103,7 @@ ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= +ProjectManager.PreviousToolchain=STM32CubeIDE ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=m3s.ioc ProjectManager.ProjectName=m3s @@ -55,14 +112,71 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false -RCC.APB1Freq_Value=8000000 -RCC.APB2Freq_Value=8000000 +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FSMC_Init-FSMC-false-HAL-true +RCC.ADCFreqValue=36000000 +RCC.AHBFreq_Value=72000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV2 +RCC.APB1Freq_Value=36000000 +RCC.APB1TimFreq_Value=72000000 +RCC.APB2Freq_Value=72000000 +RCC.APB2TimFreq_Value=72000000 +RCC.FCLKCortexFreq_Value=72000000 +RCC.FSMCFreq_Value=72000000 RCC.FamilyName=M -RCC.IPParameters=APB1Freq_Value,APB2Freq_Value,FamilyName,PLLCLKFreq_Value,PLLMCOFreq_Value,TimSysFreq_Value -RCC.PLLCLKFreq_Value=8000000 -RCC.PLLMCOFreq_Value=4000000 -RCC.TimSysFreq_Value=8000000 +RCC.HCLKFreq_Value=72000000 +RCC.I2S2Freq_Value=72000000 +RCC.I2S3Freq_Value=72000000 +RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value +RCC.MCOFreq_Value=72000000 +RCC.PLLCLKFreq_Value=72000000 +RCC.PLLMCOFreq_Value=36000000 +RCC.PLLMUL=RCC_PLL_MUL9 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.SDIOFreq_Value=72000000 +RCC.SDIOHCLKDiv2FreqValue=36000000 +RCC.SYSCLKFreq_VALUE=72000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TimSysFreq_Value=72000000 +RCC.USBFreq_Value=72000000 +RCC.VCOOutput2Freq_Value=8000000 +SH.FSMC_A10.0=FSMC_A10,A10_1 +SH.FSMC_A10.ConfNb=1 +SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1 +SH.FSMC_D0_DA0.ConfNb=1 +SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1 +SH.FSMC_D10_DA10.ConfNb=1 +SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1 +SH.FSMC_D11_DA11.ConfNb=1 +SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1 +SH.FSMC_D12_DA12.ConfNb=1 +SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1 +SH.FSMC_D13_DA13.ConfNb=1 +SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1 +SH.FSMC_D14_DA14.ConfNb=1 +SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1 +SH.FSMC_D15_DA15.ConfNb=1 +SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1 +SH.FSMC_D1_DA1.ConfNb=1 +SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1 +SH.FSMC_D2_DA2.ConfNb=1 +SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1 +SH.FSMC_D3_DA3.ConfNb=1 +SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1 +SH.FSMC_D4_DA4.ConfNb=1 +SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1 +SH.FSMC_D5_DA5.ConfNb=1 +SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1 +SH.FSMC_D6_DA6.ConfNb=1 +SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1 +SH.FSMC_D7_DA7.ConfNb=1 +SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1 +SH.FSMC_D8_DA8.ConfNb=1 +SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1 +SH.FSMC_D9_DA9.ConfNb=1 +SH.FSMC_NOE.0=FSMC_NOE,Lcd1 +SH.FSMC_NOE.ConfNb=1 +SH.FSMC_NWE.0=FSMC_NWE,Lcd1 +SH.FSMC_NWE.ConfNb=1 VP_SYS_VS_ND.Mode=No_Debug VP_SYS_VS_ND.Signal=SYS_VS_ND VP_SYS_VS_Systick.Mode=SysTick