: /** * @brief The application entry point. * @retval int */ int main(void) { 8001108: b580 push {r7, lr} 800110a: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800110c: f000 fb64 bl 80017d8 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001110: f000 f809 bl 8001126 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001114: f000 f87a bl 800120c MX_FSMC_Init(); 8001118: f000 f910 bl 800133c MX_I2C2_Init(); 800111c: f000 f848 bl 80011b0 /* USER CODE BEGIN 2 */ main_app(); 8001120: f004 f87c bl 800521c /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8001124: e7fe b.n 8001124 08001126 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001126: b580 push {r7, lr} 8001128: b090 sub sp, #64 ; 0x40 800112a: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800112c: f107 0318 add.w r3, r7, #24 8001130: 2228 movs r2, #40 ; 0x28 8001132: 2100 movs r1, #0 8001134: 4618 mov r0, r3 8001136: f004 fc35 bl 80059a4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800113a: 1d3b adds r3, r7, #4 800113c: 2200 movs r2, #0 800113e: 601a str r2, [r3, #0] 8001140: 605a str r2, [r3, #4] 8001142: 609a str r2, [r3, #8] 8001144: 60da str r2, [r3, #12] 8001146: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001148: 2301 movs r3, #1 800114a: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800114c: f44f 3380 mov.w r3, #65536 ; 0x10000 8001150: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8001152: 2300 movs r3, #0 8001154: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001156: 2301 movs r3, #1 8001158: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800115a: 2302 movs r3, #2 800115c: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800115e: f44f 3380 mov.w r3, #65536 ; 0x10000 8001162: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8001164: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8001168: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800116a: f107 0318 add.w r3, r7, #24 800116e: 4618 mov r0, r3 8001170: f001 fe60 bl 8002e34 8001174: 4603 mov r3, r0 8001176: 2b00 cmp r3, #0 8001178: d001 beq.n 800117e { Error_Handler(); 800117a: f000 f943 bl 8001404 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800117e: 230f movs r3, #15 8001180: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8001182: 2302 movs r3, #2 8001184: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001186: 2300 movs r3, #0 8001188: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800118a: f44f 6380 mov.w r3, #1024 ; 0x400 800118e: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001190: 2300 movs r3, #0 8001192: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001194: 1d3b adds r3, r7, #4 8001196: 2102 movs r1, #2 8001198: 4618 mov r0, r3 800119a: f002 f8cb bl 8003334 800119e: 4603 mov r3, r0 80011a0: 2b00 cmp r3, #0 80011a2: d001 beq.n 80011a8 { Error_Handler(); 80011a4: f000 f92e bl 8001404 } } 80011a8: bf00 nop 80011aa: 3740 adds r7, #64 ; 0x40 80011ac: 46bd mov sp, r7 80011ae: bd80 pop {r7, pc} 080011b0 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 80011b0: b580 push {r7, lr} 80011b2: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 80011b4: 4b12 ldr r3, [pc, #72] ; (8001200 ) 80011b6: 4a13 ldr r2, [pc, #76] ; (8001204 ) 80011b8: 601a str r2, [r3, #0] hi2c2.Init.ClockSpeed = 100000; 80011ba: 4b11 ldr r3, [pc, #68] ; (8001200 ) 80011bc: 4a12 ldr r2, [pc, #72] ; (8001208 ) 80011be: 605a str r2, [r3, #4] hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2; 80011c0: 4b0f ldr r3, [pc, #60] ; (8001200 ) 80011c2: 2200 movs r2, #0 80011c4: 609a str r2, [r3, #8] hi2c2.Init.OwnAddress1 = 0; 80011c6: 4b0e ldr r3, [pc, #56] ; (8001200 ) 80011c8: 2200 movs r2, #0 80011ca: 60da str r2, [r3, #12] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80011cc: 4b0c ldr r3, [pc, #48] ; (8001200 ) 80011ce: f44f 4280 mov.w r2, #16384 ; 0x4000 80011d2: 611a str r2, [r3, #16] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80011d4: 4b0a ldr r3, [pc, #40] ; (8001200 ) 80011d6: 2200 movs r2, #0 80011d8: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2 = 0; 80011da: 4b09 ldr r3, [pc, #36] ; (8001200 ) 80011dc: 2200 movs r2, #0 80011de: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80011e0: 4b07 ldr r3, [pc, #28] ; (8001200 ) 80011e2: 2200 movs r2, #0 80011e4: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80011e6: 4b06 ldr r3, [pc, #24] ; (8001200 ) 80011e8: 2200 movs r2, #0 80011ea: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 80011ec: 4804 ldr r0, [pc, #16] ; (8001200 ) 80011ee: f000 fe21 bl 8001e34 80011f2: 4603 mov r3, r0 80011f4: 2b00 cmp r3, #0 80011f6: d001 beq.n 80011fc { Error_Handler(); 80011f8: f000 f904 bl 8001404 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 80011fc: bf00 nop 80011fe: bd80 pop {r7, pc} 8001200: 20000208 .word 0x20000208 8001204: 40005800 .word 0x40005800 8001208: 000186a0 .word 0x000186a0 0800120c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800120c: b580 push {r7, lr} 800120e: b08a sub sp, #40 ; 0x28 8001210: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001212: f107 0318 add.w r3, r7, #24 8001216: 2200 movs r2, #0 8001218: 601a str r2, [r3, #0] 800121a: 605a str r2, [r3, #4] 800121c: 609a str r2, [r3, #8] 800121e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8001220: 4b43 ldr r3, [pc, #268] ; (8001330 ) 8001222: 699b ldr r3, [r3, #24] 8001224: 4a42 ldr r2, [pc, #264] ; (8001330 ) 8001226: f043 0380 orr.w r3, r3, #128 ; 0x80 800122a: 6193 str r3, [r2, #24] 800122c: 4b40 ldr r3, [pc, #256] ; (8001330 ) 800122e: 699b ldr r3, [r3, #24] 8001230: f003 0380 and.w r3, r3, #128 ; 0x80 8001234: 617b str r3, [r7, #20] 8001236: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001238: 4b3d ldr r3, [pc, #244] ; (8001330 ) 800123a: 699b ldr r3, [r3, #24] 800123c: 4a3c ldr r2, [pc, #240] ; (8001330 ) 800123e: f043 0308 orr.w r3, r3, #8 8001242: 6193 str r3, [r2, #24] 8001244: 4b3a ldr r3, [pc, #232] ; (8001330 ) 8001246: 699b ldr r3, [r3, #24] 8001248: f003 0308 and.w r3, r3, #8 800124c: 613b str r3, [r7, #16] 800124e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 8001250: 4b37 ldr r3, [pc, #220] ; (8001330 ) 8001252: 699b ldr r3, [r3, #24] 8001254: 4a36 ldr r2, [pc, #216] ; (8001330 ) 8001256: f443 7380 orr.w r3, r3, #256 ; 0x100 800125a: 6193 str r3, [r2, #24] 800125c: 4b34 ldr r3, [pc, #208] ; (8001330 ) 800125e: 699b ldr r3, [r3, #24] 8001260: f403 7380 and.w r3, r3, #256 ; 0x100 8001264: 60fb str r3, [r7, #12] 8001266: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001268: 4b31 ldr r3, [pc, #196] ; (8001330 ) 800126a: 699b ldr r3, [r3, #24] 800126c: 4a30 ldr r2, [pc, #192] ; (8001330 ) 800126e: f043 0340 orr.w r3, r3, #64 ; 0x40 8001272: 6193 str r3, [r2, #24] 8001274: 4b2e ldr r3, [pc, #184] ; (8001330 ) 8001276: 699b ldr r3, [r3, #24] 8001278: f003 0340 and.w r3, r3, #64 ; 0x40 800127c: 60bb str r3, [r7, #8] 800127e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001280: 4b2b ldr r3, [pc, #172] ; (8001330 ) 8001282: 699b ldr r3, [r3, #24] 8001284: 4a2a ldr r2, [pc, #168] ; (8001330 ) 8001286: f043 0320 orr.w r3, r3, #32 800128a: 6193 str r3, [r2, #24] 800128c: 4b28 ldr r3, [pc, #160] ; (8001330 ) 800128e: 699b ldr r3, [r3, #24] 8001290: f003 0320 and.w r3, r3, #32 8001294: 607b str r3, [r7, #4] 8001296: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TDIN_GPIO_Port, TDIN_Pin, GPIO_PIN_SET); 8001298: 2201 movs r2, #1 800129a: f44f 7100 mov.w r1, #512 ; 0x200 800129e: 4825 ldr r0, [pc, #148] ; (8001334 ) 80012a0: f000 fdaf bl 8001e02 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); 80012a4: 2200 movs r2, #0 80012a6: 2101 movs r1, #1 80012a8: 4823 ldr r0, [pc, #140] ; (8001338 ) 80012aa: f000 fdaa bl 8001e02 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, TCLK_Pin|TCS_Pin, GPIO_PIN_SET); 80012ae: 2201 movs r2, #1 80012b0: 2106 movs r1, #6 80012b2: 4821 ldr r0, [pc, #132] ; (8001338 ) 80012b4: f000 fda5 bl 8001e02 /*Configure GPIO pins : TDOUT_Pin TPEN_Pin */ GPIO_InitStruct.Pin = TDOUT_Pin|TPEN_Pin; 80012b8: f44f 63a0 mov.w r3, #1280 ; 0x500 80012bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80012be: 2300 movs r3, #0 80012c0: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012c2: 2300 movs r3, #0 80012c4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 80012c6: f107 0318 add.w r3, r7, #24 80012ca: 4619 mov r1, r3 80012cc: 4819 ldr r0, [pc, #100] ; (8001334 ) 80012ce: f000 fbed bl 8001aac /*Configure GPIO pin : TDIN_Pin */ GPIO_InitStruct.Pin = TDIN_Pin; 80012d2: f44f 7300 mov.w r3, #512 ; 0x200 80012d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80012d8: 2301 movs r3, #1 80012da: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012dc: 2300 movs r3, #0 80012de: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80012e0: 2303 movs r3, #3 80012e2: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(TDIN_GPIO_Port, &GPIO_InitStruct); 80012e4: f107 0318 add.w r3, r7, #24 80012e8: 4619 mov r1, r3 80012ea: 4812 ldr r0, [pc, #72] ; (8001334 ) 80012ec: f000 fbde bl 8001aac /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 80012f0: 2301 movs r3, #1 80012f2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80012f4: 2301 movs r3, #1 80012f6: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012f8: 2300 movs r3, #0 80012fa: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80012fc: 2302 movs r3, #2 80012fe: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 8001300: f107 0318 add.w r3, r7, #24 8001304: 4619 mov r1, r3 8001306: 480c ldr r0, [pc, #48] ; (8001338 ) 8001308: f000 fbd0 bl 8001aac /*Configure GPIO pins : TCLK_Pin TCS_Pin */ GPIO_InitStruct.Pin = TCLK_Pin|TCS_Pin; 800130c: 2306 movs r3, #6 800130e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001310: 2301 movs r3, #1 8001312: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001314: 2300 movs r3, #0 8001316: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001318: 2303 movs r3, #3 800131a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800131c: f107 0318 add.w r3, r7, #24 8001320: 4619 mov r1, r3 8001322: 4805 ldr r0, [pc, #20] ; (8001338 ) 8001324: f000 fbc2 bl 8001aac } 8001328: bf00 nop 800132a: 3728 adds r7, #40 ; 0x28 800132c: 46bd mov sp, r7 800132e: bd80 pop {r7, pc} 8001330: 40021000 .word 0x40021000 8001334: 40011c00 .word 0x40011c00 8001338: 40010c00 .word 0x40010c00 0800133c : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 800133c: b580 push {r7, lr} 800133e: b088 sub sp, #32 8001340: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 8001342: 1d3b adds r3, r7, #4 8001344: 2200 movs r2, #0 8001346: 601a str r2, [r3, #0] 8001348: 605a str r2, [r3, #4] 800134a: 609a str r2, [r3, #8] 800134c: 60da str r2, [r3, #12] 800134e: 611a str r2, [r3, #16] 8001350: 615a str r2, [r3, #20] 8001352: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 8001354: 4b28 ldr r3, [pc, #160] ; (80013f8 ) 8001356: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 800135a: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 800135c: 4b26 ldr r3, [pc, #152] ; (80013f8 ) 800135e: 4a27 ldr r2, [pc, #156] ; (80013fc ) 8001360: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 8001362: 4b25 ldr r3, [pc, #148] ; (80013f8 ) 8001364: 2206 movs r2, #6 8001366: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 8001368: 4b23 ldr r3, [pc, #140] ; (80013f8 ) 800136a: 2200 movs r2, #0 800136c: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 800136e: 4b22 ldr r3, [pc, #136] ; (80013f8 ) 8001370: 2200 movs r2, #0 8001372: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 8001374: 4b20 ldr r3, [pc, #128] ; (80013f8 ) 8001376: 2210 movs r2, #16 8001378: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 800137a: 4b1f ldr r3, [pc, #124] ; (80013f8 ) 800137c: 2200 movs r2, #0 800137e: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 8001380: 4b1d ldr r3, [pc, #116] ; (80013f8 ) 8001382: 2200 movs r2, #0 8001384: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 8001386: 4b1c ldr r3, [pc, #112] ; (80013f8 ) 8001388: 2200 movs r2, #0 800138a: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 800138c: 4b1a ldr r3, [pc, #104] ; (80013f8 ) 800138e: 2200 movs r2, #0 8001390: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 8001392: 4b19 ldr r3, [pc, #100] ; (80013f8 ) 8001394: f44f 5280 mov.w r2, #4096 ; 0x1000 8001398: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 800139a: 4b17 ldr r3, [pc, #92] ; (80013f8 ) 800139c: 2200 movs r2, #0 800139e: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 80013a0: 4b15 ldr r3, [pc, #84] ; (80013f8 ) 80013a2: 2200 movs r2, #0 80013a4: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 80013a6: 4b14 ldr r3, [pc, #80] ; (80013f8 ) 80013a8: 2200 movs r2, #0 80013aa: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 80013ac: 4b12 ldr r3, [pc, #72] ; (80013f8 ) 80013ae: 2200 movs r2, #0 80013b0: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 80013b2: 2300 movs r3, #0 80013b4: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 80013b6: 230f movs r3, #15 80013b8: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 80013ba: 2301 movs r3, #1 80013bc: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 0; 80013be: 2300 movs r3, #0 80013c0: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 80013c2: 2310 movs r3, #16 80013c4: 617b str r3, [r7, #20] Timing.DataLatency = 17; 80013c6: 2311 movs r3, #17 80013c8: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 80013ca: 2300 movs r3, #0 80013cc: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 80013ce: 1d3b adds r3, r7, #4 80013d0: 2200 movs r2, #0 80013d2: 4619 mov r1, r3 80013d4: 4808 ldr r0, [pc, #32] ; (80013f8 ) 80013d6: f002 f933 bl 8003640 80013da: 4603 mov r3, r0 80013dc: 2b00 cmp r3, #0 80013de: d001 beq.n 80013e4 { Error_Handler( ); 80013e0: f000 f810 bl 8001404 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 80013e4: 4b06 ldr r3, [pc, #24] ; (8001400 ) 80013e6: 69db ldr r3, [r3, #28] 80013e8: 4a05 ldr r2, [pc, #20] ; (8001400 ) 80013ea: f443 6380 orr.w r3, r3, #1024 ; 0x400 80013ee: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 80013f0: bf00 nop 80013f2: 3720 adds r7, #32 80013f4: 46bd mov sp, r7 80013f6: bd80 pop {r7, pc} 80013f8: 2000025c .word 0x2000025c 80013fc: a0000104 .word 0xa0000104 8001400: 40010000 .word 0x40010000 08001404 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001404: b480 push {r7} 8001406: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001408: b672 cpsid i } 800140a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800140c: e7fe b.n 800140c ... 08001410 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001410: b480 push {r7} 8001412: b085 sub sp, #20 8001414: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001416: 4b15 ldr r3, [pc, #84] ; (800146c ) 8001418: 699b ldr r3, [r3, #24] 800141a: 4a14 ldr r2, [pc, #80] ; (800146c ) 800141c: f043 0301 orr.w r3, r3, #1 8001420: 6193 str r3, [r2, #24] 8001422: 4b12 ldr r3, [pc, #72] ; (800146c ) 8001424: 699b ldr r3, [r3, #24] 8001426: f003 0301 and.w r3, r3, #1 800142a: 60bb str r3, [r7, #8] 800142c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800142e: 4b0f ldr r3, [pc, #60] ; (800146c ) 8001430: 69db ldr r3, [r3, #28] 8001432: 4a0e ldr r2, [pc, #56] ; (800146c ) 8001434: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001438: 61d3 str r3, [r2, #28] 800143a: 4b0c ldr r3, [pc, #48] ; (800146c ) 800143c: 69db ldr r3, [r3, #28] 800143e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001442: 607b str r3, [r7, #4] 8001444: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 8001446: 4b0a ldr r3, [pc, #40] ; (8001470 ) 8001448: 685b ldr r3, [r3, #4] 800144a: 60fb str r3, [r7, #12] 800144c: 68fb ldr r3, [r7, #12] 800144e: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8001452: 60fb str r3, [r7, #12] 8001454: 68fb ldr r3, [r7, #12] 8001456: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 800145a: 60fb str r3, [r7, #12] 800145c: 4a04 ldr r2, [pc, #16] ; (8001470 ) 800145e: 68fb ldr r3, [r7, #12] 8001460: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001462: bf00 nop 8001464: 3714 adds r7, #20 8001466: 46bd mov sp, r7 8001468: bc80 pop {r7} 800146a: 4770 bx lr 800146c: 40021000 .word 0x40021000 8001470: 40010000 .word 0x40010000 08001474 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8001474: b580 push {r7, lr} 8001476: b088 sub sp, #32 8001478: af00 add r7, sp, #0 800147a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800147c: f107 0310 add.w r3, r7, #16 8001480: 2200 movs r2, #0 8001482: 601a str r2, [r3, #0] 8001484: 605a str r2, [r3, #4] 8001486: 609a str r2, [r3, #8] 8001488: 60da str r2, [r3, #12] if(hi2c->Instance==I2C2) 800148a: 687b ldr r3, [r7, #4] 800148c: 681b ldr r3, [r3, #0] 800148e: 4a16 ldr r2, [pc, #88] ; (80014e8 ) 8001490: 4293 cmp r3, r2 8001492: d124 bne.n 80014de { /* USER CODE BEGIN I2C2_MspInit 0 */ /* USER CODE END I2C2_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8001494: 4b15 ldr r3, [pc, #84] ; (80014ec ) 8001496: 699b ldr r3, [r3, #24] 8001498: 4a14 ldr r2, [pc, #80] ; (80014ec ) 800149a: f043 0308 orr.w r3, r3, #8 800149e: 6193 str r3, [r2, #24] 80014a0: 4b12 ldr r3, [pc, #72] ; (80014ec ) 80014a2: 699b ldr r3, [r3, #24] 80014a4: f003 0308 and.w r3, r3, #8 80014a8: 60fb str r3, [r7, #12] 80014aa: 68fb ldr r3, [r7, #12] /**I2C2 GPIO Configuration PB10 ------> I2C2_SCL PB11 ------> I2C2_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 80014ac: f44f 6340 mov.w r3, #3072 ; 0xc00 80014b0: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80014b2: 2312 movs r3, #18 80014b4: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80014b6: 2303 movs r3, #3 80014b8: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80014ba: f107 0310 add.w r3, r7, #16 80014be: 4619 mov r1, r3 80014c0: 480b ldr r0, [pc, #44] ; (80014f0 ) 80014c2: f000 faf3 bl 8001aac /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); 80014c6: 4b09 ldr r3, [pc, #36] ; (80014ec ) 80014c8: 69db ldr r3, [r3, #28] 80014ca: 4a08 ldr r2, [pc, #32] ; (80014ec ) 80014cc: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 80014d0: 61d3 str r3, [r2, #28] 80014d2: 4b06 ldr r3, [pc, #24] ; (80014ec ) 80014d4: 69db ldr r3, [r3, #28] 80014d6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 80014da: 60bb str r3, [r7, #8] 80014dc: 68bb ldr r3, [r7, #8] /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ } } 80014de: bf00 nop 80014e0: 3720 adds r7, #32 80014e2: 46bd mov sp, r7 80014e4: bd80 pop {r7, pc} 80014e6: bf00 nop 80014e8: 40005800 .word 0x40005800 80014ec: 40021000 .word 0x40021000 80014f0: 40010c00 .word 0x40010c00 080014f4 : } static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 80014f4: b580 push {r7, lr} 80014f6: b086 sub sp, #24 80014f8: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 80014fa: f107 0308 add.w r3, r7, #8 80014fe: 2200 movs r2, #0 8001500: 601a str r2, [r3, #0] 8001502: 605a str r2, [r3, #4] 8001504: 609a str r2, [r3, #8] 8001506: 60da str r2, [r3, #12] if (FSMC_Initialized) { 8001508: 4b1f ldr r3, [pc, #124] ; (8001588 ) 800150a: 681b ldr r3, [r3, #0] 800150c: 2b00 cmp r3, #0 800150e: d136 bne.n 800157e return; } FSMC_Initialized = 1; 8001510: 4b1d ldr r3, [pc, #116] ; (8001588 ) 8001512: 2201 movs r2, #1 8001514: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 8001516: 4b1d ldr r3, [pc, #116] ; (800158c ) 8001518: 695b ldr r3, [r3, #20] 800151a: 4a1c ldr r2, [pc, #112] ; (800158c ) 800151c: f443 7380 orr.w r3, r3, #256 ; 0x100 8001520: 6153 str r3, [r2, #20] 8001522: 4b1a ldr r3, [pc, #104] ; (800158c ) 8001524: 695b ldr r3, [r3, #20] 8001526: f403 7380 and.w r3, r3, #256 ; 0x100 800152a: 607b str r3, [r7, #4] 800152c: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 800152e: f241 0301 movw r3, #4097 ; 0x1001 8001532: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001534: 2302 movs r3, #2 8001536: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001538: 2303 movs r3, #3 800153a: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800153c: f107 0308 add.w r3, r7, #8 8001540: 4619 mov r1, r3 8001542: 4813 ldr r0, [pc, #76] ; (8001590 ) 8001544: f000 fab2 bl 8001aac GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001548: f64f 7380 movw r3, #65408 ; 0xff80 800154c: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800154e: 2302 movs r3, #2 8001550: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001552: 2303 movs r3, #3 8001554: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001556: f107 0308 add.w r3, r7, #8 800155a: 4619 mov r1, r3 800155c: 480d ldr r0, [pc, #52] ; (8001594 ) 800155e: f000 faa5 bl 8001aac GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 8001562: f24c 7333 movw r3, #50995 ; 0xc733 8001566: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001568: 2302 movs r3, #2 800156a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800156c: 2303 movs r3, #3 800156e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001570: f107 0308 add.w r3, r7, #8 8001574: 4619 mov r1, r3 8001576: 4808 ldr r0, [pc, #32] ; (8001598 ) 8001578: f000 fa98 bl 8001aac 800157c: e000 b.n 8001580 return; 800157e: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 8001580: 3718 adds r7, #24 8001582: 46bd mov sp, r7 8001584: bd80 pop {r7, pc} 8001586: bf00 nop 8001588: 200001f8 .word 0x200001f8 800158c: 40021000 .word 0x40021000 8001590: 40012000 .word 0x40012000 8001594: 40011800 .word 0x40011800 8001598: 40011400 .word 0x40011400 0800159c : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 800159c: b580 push {r7, lr} 800159e: b082 sub sp, #8 80015a0: af00 add r7, sp, #0 80015a2: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 80015a4: f7ff ffa6 bl 80014f4 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 80015a8: bf00 nop 80015aa: 3708 adds r7, #8 80015ac: 46bd mov sp, r7 80015ae: bd80 pop {r7, pc} 080015b0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80015b0: b480 push {r7} 80015b2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80015b4: e7fe b.n 80015b4 080015b6 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80015b6: b480 push {r7} 80015b8: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80015ba: e7fe b.n 80015ba 080015bc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80015bc: b480 push {r7} 80015be: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80015c0: e7fe b.n 80015c0 080015c2 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80015c2: b480 push {r7} 80015c4: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80015c6: e7fe b.n 80015c6 080015c8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80015c8: b480 push {r7} 80015ca: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80015cc: e7fe b.n 80015cc 080015ce : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80015ce: b480 push {r7} 80015d0: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80015d2: bf00 nop 80015d4: 46bd mov sp, r7 80015d6: bc80 pop {r7} 80015d8: 4770 bx lr 080015da : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80015da: b480 push {r7} 80015dc: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80015de: bf00 nop 80015e0: 46bd mov sp, r7 80015e2: bc80 pop {r7} 80015e4: 4770 bx lr 080015e6 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80015e6: b480 push {r7} 80015e8: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80015ea: bf00 nop 80015ec: 46bd mov sp, r7 80015ee: bc80 pop {r7} 80015f0: 4770 bx lr 080015f2 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80015f2: b580 push {r7, lr} 80015f4: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80015f6: f000 f935 bl 8001864 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80015fa: bf00 nop 80015fc: bd80 pop {r7, pc} 080015fe <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 80015fe: b480 push {r7} 8001600: af00 add r7, sp, #0 return 1; 8001602: 2301 movs r3, #1 } 8001604: 4618 mov r0, r3 8001606: 46bd mov sp, r7 8001608: bc80 pop {r7} 800160a: 4770 bx lr 0800160c <_kill>: int _kill(int pid, int sig) { 800160c: b580 push {r7, lr} 800160e: b082 sub sp, #8 8001610: af00 add r7, sp, #0 8001612: 6078 str r0, [r7, #4] 8001614: 6039 str r1, [r7, #0] errno = EINVAL; 8001616: f004 f98b bl 8005930 <__errno> 800161a: 4603 mov r3, r0 800161c: 2216 movs r2, #22 800161e: 601a str r2, [r3, #0] return -1; 8001620: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001624: 4618 mov r0, r3 8001626: 3708 adds r7, #8 8001628: 46bd mov sp, r7 800162a: bd80 pop {r7, pc} 0800162c <_exit>: void _exit (int status) { 800162c: b580 push {r7, lr} 800162e: b082 sub sp, #8 8001630: af00 add r7, sp, #0 8001632: 6078 str r0, [r7, #4] _kill(status, -1); 8001634: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001638: 6878 ldr r0, [r7, #4] 800163a: f7ff ffe7 bl 800160c <_kill> while (1) {} /* Make sure we hang here */ 800163e: e7fe b.n 800163e <_exit+0x12> 08001640 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001640: b580 push {r7, lr} 8001642: b086 sub sp, #24 8001644: af00 add r7, sp, #0 8001646: 60f8 str r0, [r7, #12] 8001648: 60b9 str r1, [r7, #8] 800164a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800164c: 2300 movs r3, #0 800164e: 617b str r3, [r7, #20] 8001650: e00a b.n 8001668 <_read+0x28> { *ptr++ = __io_getchar(); 8001652: f3af 8000 nop.w 8001656: 4601 mov r1, r0 8001658: 68bb ldr r3, [r7, #8] 800165a: 1c5a adds r2, r3, #1 800165c: 60ba str r2, [r7, #8] 800165e: b2ca uxtb r2, r1 8001660: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8001662: 697b ldr r3, [r7, #20] 8001664: 3301 adds r3, #1 8001666: 617b str r3, [r7, #20] 8001668: 697a ldr r2, [r7, #20] 800166a: 687b ldr r3, [r7, #4] 800166c: 429a cmp r2, r3 800166e: dbf0 blt.n 8001652 <_read+0x12> } return len; 8001670: 687b ldr r3, [r7, #4] } 8001672: 4618 mov r0, r3 8001674: 3718 adds r7, #24 8001676: 46bd mov sp, r7 8001678: bd80 pop {r7, pc} 0800167a <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 800167a: b580 push {r7, lr} 800167c: b086 sub sp, #24 800167e: af00 add r7, sp, #0 8001680: 60f8 str r0, [r7, #12] 8001682: 60b9 str r1, [r7, #8] 8001684: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001686: 2300 movs r3, #0 8001688: 617b str r3, [r7, #20] 800168a: e009 b.n 80016a0 <_write+0x26> { __io_putchar(*ptr++); 800168c: 68bb ldr r3, [r7, #8] 800168e: 1c5a adds r2, r3, #1 8001690: 60ba str r2, [r7, #8] 8001692: 781b ldrb r3, [r3, #0] 8001694: 4618 mov r0, r3 8001696: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 800169a: 697b ldr r3, [r7, #20] 800169c: 3301 adds r3, #1 800169e: 617b str r3, [r7, #20] 80016a0: 697a ldr r2, [r7, #20] 80016a2: 687b ldr r3, [r7, #4] 80016a4: 429a cmp r2, r3 80016a6: dbf1 blt.n 800168c <_write+0x12> } return len; 80016a8: 687b ldr r3, [r7, #4] } 80016aa: 4618 mov r0, r3 80016ac: 3718 adds r7, #24 80016ae: 46bd mov sp, r7 80016b0: bd80 pop {r7, pc} 080016b2 <_close>: int _close(int file) { 80016b2: b480 push {r7} 80016b4: b083 sub sp, #12 80016b6: af00 add r7, sp, #0 80016b8: 6078 str r0, [r7, #4] return -1; 80016ba: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 80016be: 4618 mov r0, r3 80016c0: 370c adds r7, #12 80016c2: 46bd mov sp, r7 80016c4: bc80 pop {r7} 80016c6: 4770 bx lr 080016c8 <_fstat>: int _fstat(int file, struct stat *st) { 80016c8: b480 push {r7} 80016ca: b083 sub sp, #12 80016cc: af00 add r7, sp, #0 80016ce: 6078 str r0, [r7, #4] 80016d0: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 80016d2: 683b ldr r3, [r7, #0] 80016d4: f44f 5200 mov.w r2, #8192 ; 0x2000 80016d8: 605a str r2, [r3, #4] return 0; 80016da: 2300 movs r3, #0 } 80016dc: 4618 mov r0, r3 80016de: 370c adds r7, #12 80016e0: 46bd mov sp, r7 80016e2: bc80 pop {r7} 80016e4: 4770 bx lr 080016e6 <_isatty>: int _isatty(int file) { 80016e6: b480 push {r7} 80016e8: b083 sub sp, #12 80016ea: af00 add r7, sp, #0 80016ec: 6078 str r0, [r7, #4] return 1; 80016ee: 2301 movs r3, #1 } 80016f0: 4618 mov r0, r3 80016f2: 370c adds r7, #12 80016f4: 46bd mov sp, r7 80016f6: bc80 pop {r7} 80016f8: 4770 bx lr 080016fa <_lseek>: int _lseek(int file, int ptr, int dir) { 80016fa: b480 push {r7} 80016fc: b085 sub sp, #20 80016fe: af00 add r7, sp, #0 8001700: 60f8 str r0, [r7, #12] 8001702: 60b9 str r1, [r7, #8] 8001704: 607a str r2, [r7, #4] return 0; 8001706: 2300 movs r3, #0 } 8001708: 4618 mov r0, r3 800170a: 3714 adds r7, #20 800170c: 46bd mov sp, r7 800170e: bc80 pop {r7} 8001710: 4770 bx lr ... 08001714 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001714: b580 push {r7, lr} 8001716: b086 sub sp, #24 8001718: af00 add r7, sp, #0 800171a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800171c: 4a14 ldr r2, [pc, #80] ; (8001770 <_sbrk+0x5c>) 800171e: 4b15 ldr r3, [pc, #84] ; (8001774 <_sbrk+0x60>) 8001720: 1ad3 subs r3, r2, r3 8001722: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001724: 697b ldr r3, [r7, #20] 8001726: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001728: 4b13 ldr r3, [pc, #76] ; (8001778 <_sbrk+0x64>) 800172a: 681b ldr r3, [r3, #0] 800172c: 2b00 cmp r3, #0 800172e: d102 bne.n 8001736 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001730: 4b11 ldr r3, [pc, #68] ; (8001778 <_sbrk+0x64>) 8001732: 4a12 ldr r2, [pc, #72] ; (800177c <_sbrk+0x68>) 8001734: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001736: 4b10 ldr r3, [pc, #64] ; (8001778 <_sbrk+0x64>) 8001738: 681a ldr r2, [r3, #0] 800173a: 687b ldr r3, [r7, #4] 800173c: 4413 add r3, r2 800173e: 693a ldr r2, [r7, #16] 8001740: 429a cmp r2, r3 8001742: d207 bcs.n 8001754 <_sbrk+0x40> { errno = ENOMEM; 8001744: f004 f8f4 bl 8005930 <__errno> 8001748: 4603 mov r3, r0 800174a: 220c movs r2, #12 800174c: 601a str r2, [r3, #0] return (void *)-1; 800174e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8001752: e009 b.n 8001768 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8001754: 4b08 ldr r3, [pc, #32] ; (8001778 <_sbrk+0x64>) 8001756: 681b ldr r3, [r3, #0] 8001758: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800175a: 4b07 ldr r3, [pc, #28] ; (8001778 <_sbrk+0x64>) 800175c: 681a ldr r2, [r3, #0] 800175e: 687b ldr r3, [r7, #4] 8001760: 4413 add r3, r2 8001762: 4a05 ldr r2, [pc, #20] ; (8001778 <_sbrk+0x64>) 8001764: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8001766: 68fb ldr r3, [r7, #12] } 8001768: 4618 mov r0, r3 800176a: 3718 adds r7, #24 800176c: 46bd mov sp, r7 800176e: bd80 pop {r7, pc} 8001770: 20010000 .word 0x20010000 8001774: 00000400 .word 0x00000400 8001778: 200001fc .word 0x200001fc 800177c: 20000300 .word 0x20000300 08001780 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8001780: b480 push {r7} 8001782: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001784: bf00 nop 8001786: 46bd mov sp, r7 8001788: bc80 pop {r7} 800178a: 4770 bx lr 0800178c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800178c: 480c ldr r0, [pc, #48] ; (80017c0 ) ldr r1, =_edata 800178e: 490d ldr r1, [pc, #52] ; (80017c4 ) ldr r2, =_sidata 8001790: 4a0d ldr r2, [pc, #52] ; (80017c8 ) movs r3, #0 8001792: 2300 movs r3, #0 b LoopCopyDataInit 8001794: e002 b.n 800179c 08001796 : CopyDataInit: ldr r4, [r2, r3] 8001796: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001798: 50c4 str r4, [r0, r3] adds r3, r3, #4 800179a: 3304 adds r3, #4 0800179c : LoopCopyDataInit: adds r4, r0, r3 800179c: 18c4 adds r4, r0, r3 cmp r4, r1 800179e: 428c cmp r4, r1 bcc CopyDataInit 80017a0: d3f9 bcc.n 8001796 /* Zero fill the bss segment. */ ldr r2, =_sbss 80017a2: 4a0a ldr r2, [pc, #40] ; (80017cc ) ldr r4, =_ebss 80017a4: 4c0a ldr r4, [pc, #40] ; (80017d0 ) movs r3, #0 80017a6: 2300 movs r3, #0 b LoopFillZerobss 80017a8: e001 b.n 80017ae 080017aa : FillZerobss: str r3, [r2] 80017aa: 6013 str r3, [r2, #0] adds r2, r2, #4 80017ac: 3204 adds r2, #4 080017ae : LoopFillZerobss: cmp r2, r4 80017ae: 42a2 cmp r2, r4 bcc FillZerobss 80017b0: d3fb bcc.n 80017aa /* Call the clock system intitialization function.*/ bl SystemInit 80017b2: f7ff ffe5 bl 8001780 /* Call static constructors */ bl __libc_init_array 80017b6: f004 f8c1 bl 800593c <__libc_init_array> /* Call the application's entry point.*/ bl main 80017ba: f7ff fca5 bl 8001108

bx lr 80017be: 4770 bx lr ldr r0, =_sdata 80017c0: 20000000 .word 0x20000000 ldr r1, =_edata 80017c4: 200001dc .word 0x200001dc ldr r2, =_sidata 80017c8: 0800963c .word 0x0800963c ldr r2, =_sbss 80017cc: 200001dc .word 0x200001dc ldr r4, =_ebss 80017d0: 20000300 .word 0x20000300 080017d4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80017d4: e7fe b.n 80017d4 ... 080017d8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80017d8: b580 push {r7, lr} 80017da: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80017dc: 4b08 ldr r3, [pc, #32] ; (8001800 ) 80017de: 681b ldr r3, [r3, #0] 80017e0: 4a07 ldr r2, [pc, #28] ; (8001800 ) 80017e2: f043 0310 orr.w r3, r3, #16 80017e6: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80017e8: 2003 movs r0, #3 80017ea: f000 f92b bl 8001a44 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80017ee: 200f movs r0, #15 80017f0: f000 f808 bl 8001804 /* Init the low level hardware */ HAL_MspInit(); 80017f4: f7ff fe0c bl 8001410 /* Return function status */ return HAL_OK; 80017f8: 2300 movs r3, #0 } 80017fa: 4618 mov r0, r3 80017fc: bd80 pop {r7, pc} 80017fe: bf00 nop 8001800: 40022000 .word 0x40022000 08001804 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001804: b580 push {r7, lr} 8001806: b082 sub sp, #8 8001808: af00 add r7, sp, #0 800180a: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800180c: 4b12 ldr r3, [pc, #72] ; (8001858 ) 800180e: 681a ldr r2, [r3, #0] 8001810: 4b12 ldr r3, [pc, #72] ; (800185c ) 8001812: 781b ldrb r3, [r3, #0] 8001814: 4619 mov r1, r3 8001816: f44f 737a mov.w r3, #1000 ; 0x3e8 800181a: fbb3 f3f1 udiv r3, r3, r1 800181e: fbb2 f3f3 udiv r3, r2, r3 8001822: 4618 mov r0, r3 8001824: f000 f935 bl 8001a92 8001828: 4603 mov r3, r0 800182a: 2b00 cmp r3, #0 800182c: d001 beq.n 8001832 { return HAL_ERROR; 800182e: 2301 movs r3, #1 8001830: e00e b.n 8001850 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001832: 687b ldr r3, [r7, #4] 8001834: 2b0f cmp r3, #15 8001836: d80a bhi.n 800184e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001838: 2200 movs r2, #0 800183a: 6879 ldr r1, [r7, #4] 800183c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001840: f000 f90b bl 8001a5a uwTickPrio = TickPriority; 8001844: 4a06 ldr r2, [pc, #24] ; (8001860 ) 8001846: 687b ldr r3, [r7, #4] 8001848: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800184a: 2300 movs r3, #0 800184c: e000 b.n 8001850 return HAL_ERROR; 800184e: 2301 movs r3, #1 } 8001850: 4618 mov r0, r3 8001852: 3708 adds r7, #8 8001854: 46bd mov sp, r7 8001856: bd80 pop {r7, pc} 8001858: 20000000 .word 0x20000000 800185c: 20000008 .word 0x20000008 8001860: 20000004 .word 0x20000004 08001864 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001864: b480 push {r7} 8001866: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001868: 4b05 ldr r3, [pc, #20] ; (8001880 ) 800186a: 781b ldrb r3, [r3, #0] 800186c: 461a mov r2, r3 800186e: 4b05 ldr r3, [pc, #20] ; (8001884 ) 8001870: 681b ldr r3, [r3, #0] 8001872: 4413 add r3, r2 8001874: 4a03 ldr r2, [pc, #12] ; (8001884 ) 8001876: 6013 str r3, [r2, #0] } 8001878: bf00 nop 800187a: 46bd mov sp, r7 800187c: bc80 pop {r7} 800187e: 4770 bx lr 8001880: 20000008 .word 0x20000008 8001884: 200002a4 .word 0x200002a4 08001888 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001888: b480 push {r7} 800188a: af00 add r7, sp, #0 return uwTick; 800188c: 4b02 ldr r3, [pc, #8] ; (8001898 ) 800188e: 681b ldr r3, [r3, #0] } 8001890: 4618 mov r0, r3 8001892: 46bd mov sp, r7 8001894: bc80 pop {r7} 8001896: 4770 bx lr 8001898: 200002a4 .word 0x200002a4 0800189c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800189c: b580 push {r7, lr} 800189e: b084 sub sp, #16 80018a0: af00 add r7, sp, #0 80018a2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80018a4: f7ff fff0 bl 8001888 80018a8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80018aa: 687b ldr r3, [r7, #4] 80018ac: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80018ae: 68fb ldr r3, [r7, #12] 80018b0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80018b4: d005 beq.n 80018c2 { wait += (uint32_t)(uwTickFreq); 80018b6: 4b0a ldr r3, [pc, #40] ; (80018e0 ) 80018b8: 781b ldrb r3, [r3, #0] 80018ba: 461a mov r2, r3 80018bc: 68fb ldr r3, [r7, #12] 80018be: 4413 add r3, r2 80018c0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80018c2: bf00 nop 80018c4: f7ff ffe0 bl 8001888 80018c8: 4602 mov r2, r0 80018ca: 68bb ldr r3, [r7, #8] 80018cc: 1ad3 subs r3, r2, r3 80018ce: 68fa ldr r2, [r7, #12] 80018d0: 429a cmp r2, r3 80018d2: d8f7 bhi.n 80018c4 { } } 80018d4: bf00 nop 80018d6: bf00 nop 80018d8: 3710 adds r7, #16 80018da: 46bd mov sp, r7 80018dc: bd80 pop {r7, pc} 80018de: bf00 nop 80018e0: 20000008 .word 0x20000008 080018e4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80018e4: b480 push {r7} 80018e6: b085 sub sp, #20 80018e8: af00 add r7, sp, #0 80018ea: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80018ec: 687b ldr r3, [r7, #4] 80018ee: f003 0307 and.w r3, r3, #7 80018f2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80018f4: 4b0c ldr r3, [pc, #48] ; (8001928 <__NVIC_SetPriorityGrouping+0x44>) 80018f6: 68db ldr r3, [r3, #12] 80018f8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80018fa: 68ba ldr r2, [r7, #8] 80018fc: f64f 03ff movw r3, #63743 ; 0xf8ff 8001900: 4013 ands r3, r2 8001902: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001904: 68fb ldr r3, [r7, #12] 8001906: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001908: 68bb ldr r3, [r7, #8] 800190a: 4313 orrs r3, r2 reg_value = (reg_value | 800190c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001910: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001914: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001916: 4a04 ldr r2, [pc, #16] ; (8001928 <__NVIC_SetPriorityGrouping+0x44>) 8001918: 68bb ldr r3, [r7, #8] 800191a: 60d3 str r3, [r2, #12] } 800191c: bf00 nop 800191e: 3714 adds r7, #20 8001920: 46bd mov sp, r7 8001922: bc80 pop {r7} 8001924: 4770 bx lr 8001926: bf00 nop 8001928: e000ed00 .word 0xe000ed00 0800192c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800192c: b480 push {r7} 800192e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001930: 4b04 ldr r3, [pc, #16] ; (8001944 <__NVIC_GetPriorityGrouping+0x18>) 8001932: 68db ldr r3, [r3, #12] 8001934: 0a1b lsrs r3, r3, #8 8001936: f003 0307 and.w r3, r3, #7 } 800193a: 4618 mov r0, r3 800193c: 46bd mov sp, r7 800193e: bc80 pop {r7} 8001940: 4770 bx lr 8001942: bf00 nop 8001944: e000ed00 .word 0xe000ed00 08001948 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001948: b480 push {r7} 800194a: b083 sub sp, #12 800194c: af00 add r7, sp, #0 800194e: 4603 mov r3, r0 8001950: 6039 str r1, [r7, #0] 8001952: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001954: f997 3007 ldrsb.w r3, [r7, #7] 8001958: 2b00 cmp r3, #0 800195a: db0a blt.n 8001972 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800195c: 683b ldr r3, [r7, #0] 800195e: b2da uxtb r2, r3 8001960: 490c ldr r1, [pc, #48] ; (8001994 <__NVIC_SetPriority+0x4c>) 8001962: f997 3007 ldrsb.w r3, [r7, #7] 8001966: 0112 lsls r2, r2, #4 8001968: b2d2 uxtb r2, r2 800196a: 440b add r3, r1 800196c: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001970: e00a b.n 8001988 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001972: 683b ldr r3, [r7, #0] 8001974: b2da uxtb r2, r3 8001976: 4908 ldr r1, [pc, #32] ; (8001998 <__NVIC_SetPriority+0x50>) 8001978: 79fb ldrb r3, [r7, #7] 800197a: f003 030f and.w r3, r3, #15 800197e: 3b04 subs r3, #4 8001980: 0112 lsls r2, r2, #4 8001982: b2d2 uxtb r2, r2 8001984: 440b add r3, r1 8001986: 761a strb r2, [r3, #24] } 8001988: bf00 nop 800198a: 370c adds r7, #12 800198c: 46bd mov sp, r7 800198e: bc80 pop {r7} 8001990: 4770 bx lr 8001992: bf00 nop 8001994: e000e100 .word 0xe000e100 8001998: e000ed00 .word 0xe000ed00 0800199c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 800199c: b480 push {r7} 800199e: b089 sub sp, #36 ; 0x24 80019a0: af00 add r7, sp, #0 80019a2: 60f8 str r0, [r7, #12] 80019a4: 60b9 str r1, [r7, #8] 80019a6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80019a8: 68fb ldr r3, [r7, #12] 80019aa: f003 0307 and.w r3, r3, #7 80019ae: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80019b0: 69fb ldr r3, [r7, #28] 80019b2: f1c3 0307 rsb r3, r3, #7 80019b6: 2b04 cmp r3, #4 80019b8: bf28 it cs 80019ba: 2304 movcs r3, #4 80019bc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80019be: 69fb ldr r3, [r7, #28] 80019c0: 3304 adds r3, #4 80019c2: 2b06 cmp r3, #6 80019c4: d902 bls.n 80019cc 80019c6: 69fb ldr r3, [r7, #28] 80019c8: 3b03 subs r3, #3 80019ca: e000 b.n 80019ce 80019cc: 2300 movs r3, #0 80019ce: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80019d0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80019d4: 69bb ldr r3, [r7, #24] 80019d6: fa02 f303 lsl.w r3, r2, r3 80019da: 43da mvns r2, r3 80019dc: 68bb ldr r3, [r7, #8] 80019de: 401a ands r2, r3 80019e0: 697b ldr r3, [r7, #20] 80019e2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80019e4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80019e8: 697b ldr r3, [r7, #20] 80019ea: fa01 f303 lsl.w r3, r1, r3 80019ee: 43d9 mvns r1, r3 80019f0: 687b ldr r3, [r7, #4] 80019f2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80019f4: 4313 orrs r3, r2 ); } 80019f6: 4618 mov r0, r3 80019f8: 3724 adds r7, #36 ; 0x24 80019fa: 46bd mov sp, r7 80019fc: bc80 pop {r7} 80019fe: 4770 bx lr 08001a00 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001a00: b580 push {r7, lr} 8001a02: b082 sub sp, #8 8001a04: af00 add r7, sp, #0 8001a06: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001a08: 687b ldr r3, [r7, #4] 8001a0a: 3b01 subs r3, #1 8001a0c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001a10: d301 bcc.n 8001a16 { return (1UL); /* Reload value impossible */ 8001a12: 2301 movs r3, #1 8001a14: e00f b.n 8001a36 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001a16: 4a0a ldr r2, [pc, #40] ; (8001a40 ) 8001a18: 687b ldr r3, [r7, #4] 8001a1a: 3b01 subs r3, #1 8001a1c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001a1e: 210f movs r1, #15 8001a20: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001a24: f7ff ff90 bl 8001948 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001a28: 4b05 ldr r3, [pc, #20] ; (8001a40 ) 8001a2a: 2200 movs r2, #0 8001a2c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001a2e: 4b04 ldr r3, [pc, #16] ; (8001a40 ) 8001a30: 2207 movs r2, #7 8001a32: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001a34: 2300 movs r3, #0 } 8001a36: 4618 mov r0, r3 8001a38: 3708 adds r7, #8 8001a3a: 46bd mov sp, r7 8001a3c: bd80 pop {r7, pc} 8001a3e: bf00 nop 8001a40: e000e010 .word 0xe000e010 08001a44 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a44: b580 push {r7, lr} 8001a46: b082 sub sp, #8 8001a48: af00 add r7, sp, #0 8001a4a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001a4c: 6878 ldr r0, [r7, #4] 8001a4e: f7ff ff49 bl 80018e4 <__NVIC_SetPriorityGrouping> } 8001a52: bf00 nop 8001a54: 3708 adds r7, #8 8001a56: 46bd mov sp, r7 8001a58: bd80 pop {r7, pc} 08001a5a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001a5a: b580 push {r7, lr} 8001a5c: b086 sub sp, #24 8001a5e: af00 add r7, sp, #0 8001a60: 4603 mov r3, r0 8001a62: 60b9 str r1, [r7, #8] 8001a64: 607a str r2, [r7, #4] 8001a66: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001a68: 2300 movs r3, #0 8001a6a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001a6c: f7ff ff5e bl 800192c <__NVIC_GetPriorityGrouping> 8001a70: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001a72: 687a ldr r2, [r7, #4] 8001a74: 68b9 ldr r1, [r7, #8] 8001a76: 6978 ldr r0, [r7, #20] 8001a78: f7ff ff90 bl 800199c 8001a7c: 4602 mov r2, r0 8001a7e: f997 300f ldrsb.w r3, [r7, #15] 8001a82: 4611 mov r1, r2 8001a84: 4618 mov r0, r3 8001a86: f7ff ff5f bl 8001948 <__NVIC_SetPriority> } 8001a8a: bf00 nop 8001a8c: 3718 adds r7, #24 8001a8e: 46bd mov sp, r7 8001a90: bd80 pop {r7, pc} 08001a92 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001a92: b580 push {r7, lr} 8001a94: b082 sub sp, #8 8001a96: af00 add r7, sp, #0 8001a98: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001a9a: 6878 ldr r0, [r7, #4] 8001a9c: f7ff ffb0 bl 8001a00 8001aa0: 4603 mov r3, r0 } 8001aa2: 4618 mov r0, r3 8001aa4: 3708 adds r7, #8 8001aa6: 46bd mov sp, r7 8001aa8: bd80 pop {r7, pc} ... 08001aac : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001aac: b480 push {r7} 8001aae: b08b sub sp, #44 ; 0x2c 8001ab0: af00 add r7, sp, #0 8001ab2: 6078 str r0, [r7, #4] 8001ab4: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8001ab6: 2300 movs r3, #0 8001ab8: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8001aba: 2300 movs r3, #0 8001abc: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8001abe: e179 b.n 8001db4 { /* Get the IO position */ ioposition = (0x01uL << position); 8001ac0: 2201 movs r2, #1 8001ac2: 6a7b ldr r3, [r7, #36] ; 0x24 8001ac4: fa02 f303 lsl.w r3, r2, r3 8001ac8: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001aca: 683b ldr r3, [r7, #0] 8001acc: 681b ldr r3, [r3, #0] 8001ace: 69fa ldr r2, [r7, #28] 8001ad0: 4013 ands r3, r2 8001ad2: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8001ad4: 69ba ldr r2, [r7, #24] 8001ad6: 69fb ldr r3, [r7, #28] 8001ad8: 429a cmp r2, r3 8001ada: f040 8168 bne.w 8001dae { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8001ade: 683b ldr r3, [r7, #0] 8001ae0: 685b ldr r3, [r3, #4] 8001ae2: 4aa0 ldr r2, [pc, #640] ; (8001d64 ) 8001ae4: 4293 cmp r3, r2 8001ae6: d05e beq.n 8001ba6 8001ae8: 4a9e ldr r2, [pc, #632] ; (8001d64 ) 8001aea: 4293 cmp r3, r2 8001aec: d875 bhi.n 8001bda 8001aee: 4a9e ldr r2, [pc, #632] ; (8001d68 ) 8001af0: 4293 cmp r3, r2 8001af2: d058 beq.n 8001ba6 8001af4: 4a9c ldr r2, [pc, #624] ; (8001d68 ) 8001af6: 4293 cmp r3, r2 8001af8: d86f bhi.n 8001bda 8001afa: 4a9c ldr r2, [pc, #624] ; (8001d6c ) 8001afc: 4293 cmp r3, r2 8001afe: d052 beq.n 8001ba6 8001b00: 4a9a ldr r2, [pc, #616] ; (8001d6c ) 8001b02: 4293 cmp r3, r2 8001b04: d869 bhi.n 8001bda 8001b06: 4a9a ldr r2, [pc, #616] ; (8001d70 ) 8001b08: 4293 cmp r3, r2 8001b0a: d04c beq.n 8001ba6 8001b0c: 4a98 ldr r2, [pc, #608] ; (8001d70 ) 8001b0e: 4293 cmp r3, r2 8001b10: d863 bhi.n 8001bda 8001b12: 4a98 ldr r2, [pc, #608] ; (8001d74 ) 8001b14: 4293 cmp r3, r2 8001b16: d046 beq.n 8001ba6 8001b18: 4a96 ldr r2, [pc, #600] ; (8001d74 ) 8001b1a: 4293 cmp r3, r2 8001b1c: d85d bhi.n 8001bda 8001b1e: 2b12 cmp r3, #18 8001b20: d82a bhi.n 8001b78 8001b22: 2b12 cmp r3, #18 8001b24: d859 bhi.n 8001bda 8001b26: a201 add r2, pc, #4 ; (adr r2, 8001b2c ) 8001b28: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001b2c: 08001ba7 .word 0x08001ba7 8001b30: 08001b81 .word 0x08001b81 8001b34: 08001b93 .word 0x08001b93 8001b38: 08001bd5 .word 0x08001bd5 8001b3c: 08001bdb .word 0x08001bdb 8001b40: 08001bdb .word 0x08001bdb 8001b44: 08001bdb .word 0x08001bdb 8001b48: 08001bdb .word 0x08001bdb 8001b4c: 08001bdb .word 0x08001bdb 8001b50: 08001bdb .word 0x08001bdb 8001b54: 08001bdb .word 0x08001bdb 8001b58: 08001bdb .word 0x08001bdb 8001b5c: 08001bdb .word 0x08001bdb 8001b60: 08001bdb .word 0x08001bdb 8001b64: 08001bdb .word 0x08001bdb 8001b68: 08001bdb .word 0x08001bdb 8001b6c: 08001bdb .word 0x08001bdb 8001b70: 08001b89 .word 0x08001b89 8001b74: 08001b9d .word 0x08001b9d 8001b78: 4a7f ldr r2, [pc, #508] ; (8001d78 ) 8001b7a: 4293 cmp r3, r2 8001b7c: d013 beq.n 8001ba6 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001b7e: e02c b.n 8001bda config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001b80: 683b ldr r3, [r7, #0] 8001b82: 68db ldr r3, [r3, #12] 8001b84: 623b str r3, [r7, #32] break; 8001b86: e029 b.n 8001bdc config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8001b88: 683b ldr r3, [r7, #0] 8001b8a: 68db ldr r3, [r3, #12] 8001b8c: 3304 adds r3, #4 8001b8e: 623b str r3, [r7, #32] break; 8001b90: e024 b.n 8001bdc config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001b92: 683b ldr r3, [r7, #0] 8001b94: 68db ldr r3, [r3, #12] 8001b96: 3308 adds r3, #8 8001b98: 623b str r3, [r7, #32] break; 8001b9a: e01f b.n 8001bdc config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001b9c: 683b ldr r3, [r7, #0] 8001b9e: 68db ldr r3, [r3, #12] 8001ba0: 330c adds r3, #12 8001ba2: 623b str r3, [r7, #32] break; 8001ba4: e01a b.n 8001bdc if (GPIO_Init->Pull == GPIO_NOPULL) 8001ba6: 683b ldr r3, [r7, #0] 8001ba8: 689b ldr r3, [r3, #8] 8001baa: 2b00 cmp r3, #0 8001bac: d102 bne.n 8001bb4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001bae: 2304 movs r3, #4 8001bb0: 623b str r3, [r7, #32] break; 8001bb2: e013 b.n 8001bdc else if (GPIO_Init->Pull == GPIO_PULLUP) 8001bb4: 683b ldr r3, [r7, #0] 8001bb6: 689b ldr r3, [r3, #8] 8001bb8: 2b01 cmp r3, #1 8001bba: d105 bne.n 8001bc8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001bbc: 2308 movs r3, #8 8001bbe: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001bc0: 687b ldr r3, [r7, #4] 8001bc2: 69fa ldr r2, [r7, #28] 8001bc4: 611a str r2, [r3, #16] break; 8001bc6: e009 b.n 8001bdc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001bc8: 2308 movs r3, #8 8001bca: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001bcc: 687b ldr r3, [r7, #4] 8001bce: 69fa ldr r2, [r7, #28] 8001bd0: 615a str r2, [r3, #20] break; 8001bd2: e003 b.n 8001bdc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8001bd4: 2300 movs r3, #0 8001bd6: 623b str r3, [r7, #32] break; 8001bd8: e000 b.n 8001bdc break; 8001bda: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001bdc: 69bb ldr r3, [r7, #24] 8001bde: 2bff cmp r3, #255 ; 0xff 8001be0: d801 bhi.n 8001be6 8001be2: 687b ldr r3, [r7, #4] 8001be4: e001 b.n 8001bea 8001be6: 687b ldr r3, [r7, #4] 8001be8: 3304 adds r3, #4 8001bea: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001bec: 69bb ldr r3, [r7, #24] 8001bee: 2bff cmp r3, #255 ; 0xff 8001bf0: d802 bhi.n 8001bf8 8001bf2: 6a7b ldr r3, [r7, #36] ; 0x24 8001bf4: 009b lsls r3, r3, #2 8001bf6: e002 b.n 8001bfe 8001bf8: 6a7b ldr r3, [r7, #36] ; 0x24 8001bfa: 3b08 subs r3, #8 8001bfc: 009b lsls r3, r3, #2 8001bfe: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001c00: 697b ldr r3, [r7, #20] 8001c02: 681a ldr r2, [r3, #0] 8001c04: 210f movs r1, #15 8001c06: 693b ldr r3, [r7, #16] 8001c08: fa01 f303 lsl.w r3, r1, r3 8001c0c: 43db mvns r3, r3 8001c0e: 401a ands r2, r3 8001c10: 6a39 ldr r1, [r7, #32] 8001c12: 693b ldr r3, [r7, #16] 8001c14: fa01 f303 lsl.w r3, r1, r3 8001c18: 431a orrs r2, r3 8001c1a: 697b ldr r3, [r7, #20] 8001c1c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001c1e: 683b ldr r3, [r7, #0] 8001c20: 685b ldr r3, [r3, #4] 8001c22: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001c26: 2b00 cmp r3, #0 8001c28: f000 80c1 beq.w 8001dae { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001c2c: 4b53 ldr r3, [pc, #332] ; (8001d7c ) 8001c2e: 699b ldr r3, [r3, #24] 8001c30: 4a52 ldr r2, [pc, #328] ; (8001d7c ) 8001c32: f043 0301 orr.w r3, r3, #1 8001c36: 6193 str r3, [r2, #24] 8001c38: 4b50 ldr r3, [pc, #320] ; (8001d7c ) 8001c3a: 699b ldr r3, [r3, #24] 8001c3c: f003 0301 and.w r3, r3, #1 8001c40: 60bb str r3, [r7, #8] 8001c42: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001c44: 4a4e ldr r2, [pc, #312] ; (8001d80 ) 8001c46: 6a7b ldr r3, [r7, #36] ; 0x24 8001c48: 089b lsrs r3, r3, #2 8001c4a: 3302 adds r3, #2 8001c4c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001c50: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001c52: 6a7b ldr r3, [r7, #36] ; 0x24 8001c54: f003 0303 and.w r3, r3, #3 8001c58: 009b lsls r3, r3, #2 8001c5a: 220f movs r2, #15 8001c5c: fa02 f303 lsl.w r3, r2, r3 8001c60: 43db mvns r3, r3 8001c62: 68fa ldr r2, [r7, #12] 8001c64: 4013 ands r3, r2 8001c66: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8001c68: 687b ldr r3, [r7, #4] 8001c6a: 4a46 ldr r2, [pc, #280] ; (8001d84 ) 8001c6c: 4293 cmp r3, r2 8001c6e: d01f beq.n 8001cb0 8001c70: 687b ldr r3, [r7, #4] 8001c72: 4a45 ldr r2, [pc, #276] ; (8001d88 ) 8001c74: 4293 cmp r3, r2 8001c76: d019 beq.n 8001cac 8001c78: 687b ldr r3, [r7, #4] 8001c7a: 4a44 ldr r2, [pc, #272] ; (8001d8c ) 8001c7c: 4293 cmp r3, r2 8001c7e: d013 beq.n 8001ca8 8001c80: 687b ldr r3, [r7, #4] 8001c82: 4a43 ldr r2, [pc, #268] ; (8001d90 ) 8001c84: 4293 cmp r3, r2 8001c86: d00d beq.n 8001ca4 8001c88: 687b ldr r3, [r7, #4] 8001c8a: 4a42 ldr r2, [pc, #264] ; (8001d94 ) 8001c8c: 4293 cmp r3, r2 8001c8e: d007 beq.n 8001ca0 8001c90: 687b ldr r3, [r7, #4] 8001c92: 4a41 ldr r2, [pc, #260] ; (8001d98 ) 8001c94: 4293 cmp r3, r2 8001c96: d101 bne.n 8001c9c 8001c98: 2305 movs r3, #5 8001c9a: e00a b.n 8001cb2 8001c9c: 2306 movs r3, #6 8001c9e: e008 b.n 8001cb2 8001ca0: 2304 movs r3, #4 8001ca2: e006 b.n 8001cb2 8001ca4: 2303 movs r3, #3 8001ca6: e004 b.n 8001cb2 8001ca8: 2302 movs r3, #2 8001caa: e002 b.n 8001cb2 8001cac: 2301 movs r3, #1 8001cae: e000 b.n 8001cb2 8001cb0: 2300 movs r3, #0 8001cb2: 6a7a ldr r2, [r7, #36] ; 0x24 8001cb4: f002 0203 and.w r2, r2, #3 8001cb8: 0092 lsls r2, r2, #2 8001cba: 4093 lsls r3, r2 8001cbc: 68fa ldr r2, [r7, #12] 8001cbe: 4313 orrs r3, r2 8001cc0: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001cc2: 492f ldr r1, [pc, #188] ; (8001d80 ) 8001cc4: 6a7b ldr r3, [r7, #36] ; 0x24 8001cc6: 089b lsrs r3, r3, #2 8001cc8: 3302 adds r3, #2 8001cca: 68fa ldr r2, [r7, #12] 8001ccc: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8001cd0: 683b ldr r3, [r7, #0] 8001cd2: 685b ldr r3, [r3, #4] 8001cd4: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001cd8: 2b00 cmp r3, #0 8001cda: d006 beq.n 8001cea { SET_BIT(EXTI->IMR, iocurrent); 8001cdc: 4b2f ldr r3, [pc, #188] ; (8001d9c ) 8001cde: 681a ldr r2, [r3, #0] 8001ce0: 492e ldr r1, [pc, #184] ; (8001d9c ) 8001ce2: 69bb ldr r3, [r7, #24] 8001ce4: 4313 orrs r3, r2 8001ce6: 600b str r3, [r1, #0] 8001ce8: e006 b.n 8001cf8 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8001cea: 4b2c ldr r3, [pc, #176] ; (8001d9c ) 8001cec: 681a ldr r2, [r3, #0] 8001cee: 69bb ldr r3, [r7, #24] 8001cf0: 43db mvns r3, r3 8001cf2: 492a ldr r1, [pc, #168] ; (8001d9c ) 8001cf4: 4013 ands r3, r2 8001cf6: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8001cf8: 683b ldr r3, [r7, #0] 8001cfa: 685b ldr r3, [r3, #4] 8001cfc: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001d00: 2b00 cmp r3, #0 8001d02: d006 beq.n 8001d12 { SET_BIT(EXTI->EMR, iocurrent); 8001d04: 4b25 ldr r3, [pc, #148] ; (8001d9c ) 8001d06: 685a ldr r2, [r3, #4] 8001d08: 4924 ldr r1, [pc, #144] ; (8001d9c ) 8001d0a: 69bb ldr r3, [r7, #24] 8001d0c: 4313 orrs r3, r2 8001d0e: 604b str r3, [r1, #4] 8001d10: e006 b.n 8001d20 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8001d12: 4b22 ldr r3, [pc, #136] ; (8001d9c ) 8001d14: 685a ldr r2, [r3, #4] 8001d16: 69bb ldr r3, [r7, #24] 8001d18: 43db mvns r3, r3 8001d1a: 4920 ldr r1, [pc, #128] ; (8001d9c ) 8001d1c: 4013 ands r3, r2 8001d1e: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001d20: 683b ldr r3, [r7, #0] 8001d22: 685b ldr r3, [r3, #4] 8001d24: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001d28: 2b00 cmp r3, #0 8001d2a: d006 beq.n 8001d3a { SET_BIT(EXTI->RTSR, iocurrent); 8001d2c: 4b1b ldr r3, [pc, #108] ; (8001d9c ) 8001d2e: 689a ldr r2, [r3, #8] 8001d30: 491a ldr r1, [pc, #104] ; (8001d9c ) 8001d32: 69bb ldr r3, [r7, #24] 8001d34: 4313 orrs r3, r2 8001d36: 608b str r3, [r1, #8] 8001d38: e006 b.n 8001d48 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8001d3a: 4b18 ldr r3, [pc, #96] ; (8001d9c ) 8001d3c: 689a ldr r2, [r3, #8] 8001d3e: 69bb ldr r3, [r7, #24] 8001d40: 43db mvns r3, r3 8001d42: 4916 ldr r1, [pc, #88] ; (8001d9c ) 8001d44: 4013 ands r3, r2 8001d46: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8001d48: 683b ldr r3, [r7, #0] 8001d4a: 685b ldr r3, [r3, #4] 8001d4c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001d50: 2b00 cmp r3, #0 8001d52: d025 beq.n 8001da0 { SET_BIT(EXTI->FTSR, iocurrent); 8001d54: 4b11 ldr r3, [pc, #68] ; (8001d9c ) 8001d56: 68da ldr r2, [r3, #12] 8001d58: 4910 ldr r1, [pc, #64] ; (8001d9c ) 8001d5a: 69bb ldr r3, [r7, #24] 8001d5c: 4313 orrs r3, r2 8001d5e: 60cb str r3, [r1, #12] 8001d60: e025 b.n 8001dae 8001d62: bf00 nop 8001d64: 10320000 .word 0x10320000 8001d68: 10310000 .word 0x10310000 8001d6c: 10220000 .word 0x10220000 8001d70: 10210000 .word 0x10210000 8001d74: 10120000 .word 0x10120000 8001d78: 10110000 .word 0x10110000 8001d7c: 40021000 .word 0x40021000 8001d80: 40010000 .word 0x40010000 8001d84: 40010800 .word 0x40010800 8001d88: 40010c00 .word 0x40010c00 8001d8c: 40011000 .word 0x40011000 8001d90: 40011400 .word 0x40011400 8001d94: 40011800 .word 0x40011800 8001d98: 40011c00 .word 0x40011c00 8001d9c: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001da0: 4b0b ldr r3, [pc, #44] ; (8001dd0 ) 8001da2: 68da ldr r2, [r3, #12] 8001da4: 69bb ldr r3, [r7, #24] 8001da6: 43db mvns r3, r3 8001da8: 4909 ldr r1, [pc, #36] ; (8001dd0 ) 8001daa: 4013 ands r3, r2 8001dac: 60cb str r3, [r1, #12] } } } position++; 8001dae: 6a7b ldr r3, [r7, #36] ; 0x24 8001db0: 3301 adds r3, #1 8001db2: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8001db4: 683b ldr r3, [r7, #0] 8001db6: 681a ldr r2, [r3, #0] 8001db8: 6a7b ldr r3, [r7, #36] ; 0x24 8001dba: fa22 f303 lsr.w r3, r2, r3 8001dbe: 2b00 cmp r3, #0 8001dc0: f47f ae7e bne.w 8001ac0 } } 8001dc4: bf00 nop 8001dc6: bf00 nop 8001dc8: 372c adds r7, #44 ; 0x2c 8001dca: 46bd mov sp, r7 8001dcc: bc80 pop {r7} 8001dce: 4770 bx lr 8001dd0: 40010400 .word 0x40010400 08001dd4 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001dd4: b480 push {r7} 8001dd6: b085 sub sp, #20 8001dd8: af00 add r7, sp, #0 8001dda: 6078 str r0, [r7, #4] 8001ddc: 460b mov r3, r1 8001dde: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001de0: 687b ldr r3, [r7, #4] 8001de2: 689a ldr r2, [r3, #8] 8001de4: 887b ldrh r3, [r7, #2] 8001de6: 4013 ands r3, r2 8001de8: 2b00 cmp r3, #0 8001dea: d002 beq.n 8001df2 { bitstatus = GPIO_PIN_SET; 8001dec: 2301 movs r3, #1 8001dee: 73fb strb r3, [r7, #15] 8001df0: e001 b.n 8001df6 } else { bitstatus = GPIO_PIN_RESET; 8001df2: 2300 movs r3, #0 8001df4: 73fb strb r3, [r7, #15] } return bitstatus; 8001df6: 7bfb ldrb r3, [r7, #15] } 8001df8: 4618 mov r0, r3 8001dfa: 3714 adds r7, #20 8001dfc: 46bd mov sp, r7 8001dfe: bc80 pop {r7} 8001e00: 4770 bx lr 08001e02 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001e02: b480 push {r7} 8001e04: b083 sub sp, #12 8001e06: af00 add r7, sp, #0 8001e08: 6078 str r0, [r7, #4] 8001e0a: 460b mov r3, r1 8001e0c: 807b strh r3, [r7, #2] 8001e0e: 4613 mov r3, r2 8001e10: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001e12: 787b ldrb r3, [r7, #1] 8001e14: 2b00 cmp r3, #0 8001e16: d003 beq.n 8001e20 { GPIOx->BSRR = GPIO_Pin; 8001e18: 887a ldrh r2, [r7, #2] 8001e1a: 687b ldr r3, [r7, #4] 8001e1c: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8001e1e: e003 b.n 8001e28 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8001e20: 887b ldrh r3, [r7, #2] 8001e22: 041a lsls r2, r3, #16 8001e24: 687b ldr r3, [r7, #4] 8001e26: 611a str r2, [r3, #16] } 8001e28: bf00 nop 8001e2a: 370c adds r7, #12 8001e2c: 46bd mov sp, r7 8001e2e: bc80 pop {r7} 8001e30: 4770 bx lr ... 08001e34 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8001e34: b580 push {r7, lr} 8001e36: b084 sub sp, #16 8001e38: af00 add r7, sp, #0 8001e3a: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 2b00 cmp r3, #0 8001e40: d101 bne.n 8001e46 { return HAL_ERROR; 8001e42: 2301 movs r3, #1 8001e44: e12b b.n 800209e assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8001e46: 687b ldr r3, [r7, #4] 8001e48: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001e4c: b2db uxtb r3, r3 8001e4e: 2b00 cmp r3, #0 8001e50: d106 bne.n 8001e60 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8001e52: 687b ldr r3, [r7, #4] 8001e54: 2200 movs r2, #0 8001e56: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8001e5a: 6878 ldr r0, [r7, #4] 8001e5c: f7ff fb0a bl 8001474 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8001e60: 687b ldr r3, [r7, #4] 8001e62: 2224 movs r2, #36 ; 0x24 8001e64: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 681a ldr r2, [r3, #0] 8001e6e: 687b ldr r3, [r7, #4] 8001e70: 681b ldr r3, [r3, #0] 8001e72: f022 0201 bic.w r2, r2, #1 8001e76: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 681b ldr r3, [r3, #0] 8001e7c: 681a ldr r2, [r3, #0] 8001e7e: 687b ldr r3, [r7, #4] 8001e80: 681b ldr r3, [r3, #0] 8001e82: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8001e86: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8001e88: 687b ldr r3, [r7, #4] 8001e8a: 681b ldr r3, [r3, #0] 8001e8c: 681a ldr r2, [r3, #0] 8001e8e: 687b ldr r3, [r7, #4] 8001e90: 681b ldr r3, [r3, #0] 8001e92: f422 4200 bic.w r2, r2, #32768 ; 0x8000 8001e96: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8001e98: f001 fba0 bl 80035dc 8001e9c: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8001e9e: 687b ldr r3, [r7, #4] 8001ea0: 685b ldr r3, [r3, #4] 8001ea2: 4a81 ldr r2, [pc, #516] ; (80020a8 ) 8001ea4: 4293 cmp r3, r2 8001ea6: d807 bhi.n 8001eb8 8001ea8: 68fb ldr r3, [r7, #12] 8001eaa: 4a80 ldr r2, [pc, #512] ; (80020ac ) 8001eac: 4293 cmp r3, r2 8001eae: bf94 ite ls 8001eb0: 2301 movls r3, #1 8001eb2: 2300 movhi r3, #0 8001eb4: b2db uxtb r3, r3 8001eb6: e006 b.n 8001ec6 8001eb8: 68fb ldr r3, [r7, #12] 8001eba: 4a7d ldr r2, [pc, #500] ; (80020b0 ) 8001ebc: 4293 cmp r3, r2 8001ebe: bf94 ite ls 8001ec0: 2301 movls r3, #1 8001ec2: 2300 movhi r3, #0 8001ec4: b2db uxtb r3, r3 8001ec6: 2b00 cmp r3, #0 8001ec8: d001 beq.n 8001ece { return HAL_ERROR; 8001eca: 2301 movs r3, #1 8001ecc: e0e7 b.n 800209e } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8001ece: 68fb ldr r3, [r7, #12] 8001ed0: 4a78 ldr r2, [pc, #480] ; (80020b4 ) 8001ed2: fba2 2303 umull r2, r3, r2, r3 8001ed6: 0c9b lsrs r3, r3, #18 8001ed8: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8001eda: 687b ldr r3, [r7, #4] 8001edc: 681b ldr r3, [r3, #0] 8001ede: 685b ldr r3, [r3, #4] 8001ee0: f023 013f bic.w r1, r3, #63 ; 0x3f 8001ee4: 687b ldr r3, [r7, #4] 8001ee6: 681b ldr r3, [r3, #0] 8001ee8: 68ba ldr r2, [r7, #8] 8001eea: 430a orrs r2, r1 8001eec: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8001eee: 687b ldr r3, [r7, #4] 8001ef0: 681b ldr r3, [r3, #0] 8001ef2: 6a1b ldr r3, [r3, #32] 8001ef4: f023 013f bic.w r1, r3, #63 ; 0x3f 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 685b ldr r3, [r3, #4] 8001efc: 4a6a ldr r2, [pc, #424] ; (80020a8 ) 8001efe: 4293 cmp r3, r2 8001f00: d802 bhi.n 8001f08 8001f02: 68bb ldr r3, [r7, #8] 8001f04: 3301 adds r3, #1 8001f06: e009 b.n 8001f1c 8001f08: 68bb ldr r3, [r7, #8] 8001f0a: f44f 7296 mov.w r2, #300 ; 0x12c 8001f0e: fb02 f303 mul.w r3, r2, r3 8001f12: 4a69 ldr r2, [pc, #420] ; (80020b8 ) 8001f14: fba2 2303 umull r2, r3, r2, r3 8001f18: 099b lsrs r3, r3, #6 8001f1a: 3301 adds r3, #1 8001f1c: 687a ldr r2, [r7, #4] 8001f1e: 6812 ldr r2, [r2, #0] 8001f20: 430b orrs r3, r1 8001f22: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8001f24: 687b ldr r3, [r7, #4] 8001f26: 681b ldr r3, [r3, #0] 8001f28: 69db ldr r3, [r3, #28] 8001f2a: f423 424f bic.w r2, r3, #52992 ; 0xcf00 8001f2e: f022 02ff bic.w r2, r2, #255 ; 0xff 8001f32: 687b ldr r3, [r7, #4] 8001f34: 685b ldr r3, [r3, #4] 8001f36: 495c ldr r1, [pc, #368] ; (80020a8 ) 8001f38: 428b cmp r3, r1 8001f3a: d819 bhi.n 8001f70 8001f3c: 68fb ldr r3, [r7, #12] 8001f3e: 1e59 subs r1, r3, #1 8001f40: 687b ldr r3, [r7, #4] 8001f42: 685b ldr r3, [r3, #4] 8001f44: 005b lsls r3, r3, #1 8001f46: fbb1 f3f3 udiv r3, r1, r3 8001f4a: 1c59 adds r1, r3, #1 8001f4c: f640 73fc movw r3, #4092 ; 0xffc 8001f50: 400b ands r3, r1 8001f52: 2b00 cmp r3, #0 8001f54: d00a beq.n 8001f6c 8001f56: 68fb ldr r3, [r7, #12] 8001f58: 1e59 subs r1, r3, #1 8001f5a: 687b ldr r3, [r7, #4] 8001f5c: 685b ldr r3, [r3, #4] 8001f5e: 005b lsls r3, r3, #1 8001f60: fbb1 f3f3 udiv r3, r1, r3 8001f64: 3301 adds r3, #1 8001f66: f3c3 030b ubfx r3, r3, #0, #12 8001f6a: e051 b.n 8002010 8001f6c: 2304 movs r3, #4 8001f6e: e04f b.n 8002010 8001f70: 687b ldr r3, [r7, #4] 8001f72: 689b ldr r3, [r3, #8] 8001f74: 2b00 cmp r3, #0 8001f76: d111 bne.n 8001f9c 8001f78: 68fb ldr r3, [r7, #12] 8001f7a: 1e58 subs r0, r3, #1 8001f7c: 687b ldr r3, [r7, #4] 8001f7e: 6859 ldr r1, [r3, #4] 8001f80: 460b mov r3, r1 8001f82: 005b lsls r3, r3, #1 8001f84: 440b add r3, r1 8001f86: fbb0 f3f3 udiv r3, r0, r3 8001f8a: 3301 adds r3, #1 8001f8c: f3c3 030b ubfx r3, r3, #0, #12 8001f90: 2b00 cmp r3, #0 8001f92: bf0c ite eq 8001f94: 2301 moveq r3, #1 8001f96: 2300 movne r3, #0 8001f98: b2db uxtb r3, r3 8001f9a: e012 b.n 8001fc2 8001f9c: 68fb ldr r3, [r7, #12] 8001f9e: 1e58 subs r0, r3, #1 8001fa0: 687b ldr r3, [r7, #4] 8001fa2: 6859 ldr r1, [r3, #4] 8001fa4: 460b mov r3, r1 8001fa6: 009b lsls r3, r3, #2 8001fa8: 440b add r3, r1 8001faa: 0099 lsls r1, r3, #2 8001fac: 440b add r3, r1 8001fae: fbb0 f3f3 udiv r3, r0, r3 8001fb2: 3301 adds r3, #1 8001fb4: f3c3 030b ubfx r3, r3, #0, #12 8001fb8: 2b00 cmp r3, #0 8001fba: bf0c ite eq 8001fbc: 2301 moveq r3, #1 8001fbe: 2300 movne r3, #0 8001fc0: b2db uxtb r3, r3 8001fc2: 2b00 cmp r3, #0 8001fc4: d001 beq.n 8001fca 8001fc6: 2301 movs r3, #1 8001fc8: e022 b.n 8002010 8001fca: 687b ldr r3, [r7, #4] 8001fcc: 689b ldr r3, [r3, #8] 8001fce: 2b00 cmp r3, #0 8001fd0: d10e bne.n 8001ff0 8001fd2: 68fb ldr r3, [r7, #12] 8001fd4: 1e58 subs r0, r3, #1 8001fd6: 687b ldr r3, [r7, #4] 8001fd8: 6859 ldr r1, [r3, #4] 8001fda: 460b mov r3, r1 8001fdc: 005b lsls r3, r3, #1 8001fde: 440b add r3, r1 8001fe0: fbb0 f3f3 udiv r3, r0, r3 8001fe4: 3301 adds r3, #1 8001fe6: f3c3 030b ubfx r3, r3, #0, #12 8001fea: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8001fee: e00f b.n 8002010 8001ff0: 68fb ldr r3, [r7, #12] 8001ff2: 1e58 subs r0, r3, #1 8001ff4: 687b ldr r3, [r7, #4] 8001ff6: 6859 ldr r1, [r3, #4] 8001ff8: 460b mov r3, r1 8001ffa: 009b lsls r3, r3, #2 8001ffc: 440b add r3, r1 8001ffe: 0099 lsls r1, r3, #2 8002000: 440b add r3, r1 8002002: fbb0 f3f3 udiv r3, r0, r3 8002006: 3301 adds r3, #1 8002008: f3c3 030b ubfx r3, r3, #0, #12 800200c: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8002010: 6879 ldr r1, [r7, #4] 8002012: 6809 ldr r1, [r1, #0] 8002014: 4313 orrs r3, r2 8002016: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002018: 687b ldr r3, [r7, #4] 800201a: 681b ldr r3, [r3, #0] 800201c: 681b ldr r3, [r3, #0] 800201e: f023 01c0 bic.w r1, r3, #192 ; 0xc0 8002022: 687b ldr r3, [r7, #4] 8002024: 69da ldr r2, [r3, #28] 8002026: 687b ldr r3, [r7, #4] 8002028: 6a1b ldr r3, [r3, #32] 800202a: 431a orrs r2, r3 800202c: 687b ldr r3, [r7, #4] 800202e: 681b ldr r3, [r3, #0] 8002030: 430a orrs r2, r1 8002032: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: 689b ldr r3, [r3, #8] 800203a: f423 4303 bic.w r3, r3, #33536 ; 0x8300 800203e: f023 03ff bic.w r3, r3, #255 ; 0xff 8002042: 687a ldr r2, [r7, #4] 8002044: 6911 ldr r1, [r2, #16] 8002046: 687a ldr r2, [r7, #4] 8002048: 68d2 ldr r2, [r2, #12] 800204a: 4311 orrs r1, r2 800204c: 687a ldr r2, [r7, #4] 800204e: 6812 ldr r2, [r2, #0] 8002050: 430b orrs r3, r1 8002052: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002054: 687b ldr r3, [r7, #4] 8002056: 681b ldr r3, [r3, #0] 8002058: 68db ldr r3, [r3, #12] 800205a: f023 01ff bic.w r1, r3, #255 ; 0xff 800205e: 687b ldr r3, [r7, #4] 8002060: 695a ldr r2, [r3, #20] 8002062: 687b ldr r3, [r7, #4] 8002064: 699b ldr r3, [r3, #24] 8002066: 431a orrs r2, r3 8002068: 687b ldr r3, [r7, #4] 800206a: 681b ldr r3, [r3, #0] 800206c: 430a orrs r2, r1 800206e: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002070: 687b ldr r3, [r7, #4] 8002072: 681b ldr r3, [r3, #0] 8002074: 681a ldr r2, [r3, #0] 8002076: 687b ldr r3, [r7, #4] 8002078: 681b ldr r3, [r3, #0] 800207a: f042 0201 orr.w r2, r2, #1 800207e: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002080: 687b ldr r3, [r7, #4] 8002082: 2200 movs r2, #0 8002084: 641a str r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002086: 687b ldr r3, [r7, #4] 8002088: 2220 movs r2, #32 800208a: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->PreviousState = I2C_STATE_NONE; 800208e: 687b ldr r3, [r7, #4] 8002090: 2200 movs r2, #0 8002092: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002094: 687b ldr r3, [r7, #4] 8002096: 2200 movs r2, #0 8002098: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 800209c: 2300 movs r3, #0 } 800209e: 4618 mov r0, r3 80020a0: 3710 adds r7, #16 80020a2: 46bd mov sp, r7 80020a4: bd80 pop {r7, pc} 80020a6: bf00 nop 80020a8: 000186a0 .word 0x000186a0 80020ac: 001e847f .word 0x001e847f 80020b0: 003d08ff .word 0x003d08ff 80020b4: 431bde83 .word 0x431bde83 80020b8: 10624dd3 .word 0x10624dd3 080020bc : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80020bc: b580 push {r7, lr} 80020be: b088 sub sp, #32 80020c0: af02 add r7, sp, #8 80020c2: 60f8 str r0, [r7, #12] 80020c4: 4608 mov r0, r1 80020c6: 4611 mov r1, r2 80020c8: 461a mov r2, r3 80020ca: 4603 mov r3, r0 80020cc: 817b strh r3, [r7, #10] 80020ce: 460b mov r3, r1 80020d0: 813b strh r3, [r7, #8] 80020d2: 4613 mov r3, r2 80020d4: 80fb strh r3, [r7, #6] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 80020d6: f7ff fbd7 bl 8001888 80020da: 6178 str r0, [r7, #20] /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80020dc: 68fb ldr r3, [r7, #12] 80020de: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80020e2: b2db uxtb r3, r3 80020e4: 2b20 cmp r3, #32 80020e6: f040 80d9 bne.w 800229c { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 80020ea: 697b ldr r3, [r7, #20] 80020ec: 9300 str r3, [sp, #0] 80020ee: 2319 movs r3, #25 80020f0: 2201 movs r2, #1 80020f2: 496d ldr r1, [pc, #436] ; (80022a8 ) 80020f4: 68f8 ldr r0, [r7, #12] 80020f6: f000 fcc1 bl 8002a7c 80020fa: 4603 mov r3, r0 80020fc: 2b00 cmp r3, #0 80020fe: d001 beq.n 8002104 { return HAL_BUSY; 8002100: 2302 movs r3, #2 8002102: e0cc b.n 800229e } /* Process Locked */ __HAL_LOCK(hi2c); 8002104: 68fb ldr r3, [r7, #12] 8002106: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800210a: 2b01 cmp r3, #1 800210c: d101 bne.n 8002112 800210e: 2302 movs r3, #2 8002110: e0c5 b.n 800229e 8002112: 68fb ldr r3, [r7, #12] 8002114: 2201 movs r2, #1 8002116: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 800211a: 68fb ldr r3, [r7, #12] 800211c: 681b ldr r3, [r3, #0] 800211e: 681b ldr r3, [r3, #0] 8002120: f003 0301 and.w r3, r3, #1 8002124: 2b01 cmp r3, #1 8002126: d007 beq.n 8002138 { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002128: 68fb ldr r3, [r7, #12] 800212a: 681b ldr r3, [r3, #0] 800212c: 681a ldr r2, [r3, #0] 800212e: 68fb ldr r3, [r7, #12] 8002130: 681b ldr r3, [r3, #0] 8002132: f042 0201 orr.w r2, r2, #1 8002136: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8002138: 68fb ldr r3, [r7, #12] 800213a: 681b ldr r3, [r3, #0] 800213c: 681a ldr r2, [r3, #0] 800213e: 68fb ldr r3, [r7, #12] 8002140: 681b ldr r3, [r3, #0] 8002142: f422 6200 bic.w r2, r2, #2048 ; 0x800 8002146: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_TX; 8002148: 68fb ldr r3, [r7, #12] 800214a: 2221 movs r2, #33 ; 0x21 800214c: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 8002150: 68fb ldr r3, [r7, #12] 8002152: 2240 movs r2, #64 ; 0x40 8002154: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002158: 68fb ldr r3, [r7, #12] 800215a: 2200 movs r2, #0 800215c: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 800215e: 68fb ldr r3, [r7, #12] 8002160: 6a3a ldr r2, [r7, #32] 8002162: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8002164: 68fb ldr r3, [r7, #12] 8002166: 8cba ldrh r2, [r7, #36] ; 0x24 8002168: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 800216a: 68fb ldr r3, [r7, #12] 800216c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800216e: b29a uxth r2, r3 8002170: 68fb ldr r3, [r7, #12] 8002172: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002174: 68fb ldr r3, [r7, #12] 8002176: 4a4d ldr r2, [pc, #308] ; (80022ac ) 8002178: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 800217a: 88f8 ldrh r0, [r7, #6] 800217c: 893a ldrh r2, [r7, #8] 800217e: 8979 ldrh r1, [r7, #10] 8002180: 697b ldr r3, [r7, #20] 8002182: 9301 str r3, [sp, #4] 8002184: 6abb ldr r3, [r7, #40] ; 0x28 8002186: 9300 str r3, [sp, #0] 8002188: 4603 mov r3, r0 800218a: 68f8 ldr r0, [r7, #12] 800218c: f000 faf8 bl 8002780 8002190: 4603 mov r3, r0 8002192: 2b00 cmp r3, #0 8002194: d052 beq.n 800223c { return HAL_ERROR; 8002196: 2301 movs r3, #1 8002198: e081 b.n 800229e } while (hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 800219a: 697a ldr r2, [r7, #20] 800219c: 6ab9 ldr r1, [r7, #40] ; 0x28 800219e: 68f8 ldr r0, [r7, #12] 80021a0: f000 fd42 bl 8002c28 80021a4: 4603 mov r3, r0 80021a6: 2b00 cmp r3, #0 80021a8: d00d beq.n 80021c6 { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 80021aa: 68fb ldr r3, [r7, #12] 80021ac: 6c1b ldr r3, [r3, #64] ; 0x40 80021ae: 2b04 cmp r3, #4 80021b0: d107 bne.n 80021c2 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80021b2: 68fb ldr r3, [r7, #12] 80021b4: 681b ldr r3, [r3, #0] 80021b6: 681a ldr r2, [r3, #0] 80021b8: 68fb ldr r3, [r7, #12] 80021ba: 681b ldr r3, [r3, #0] 80021bc: f442 7200 orr.w r2, r2, #512 ; 0x200 80021c0: 601a str r2, [r3, #0] } return HAL_ERROR; 80021c2: 2301 movs r3, #1 80021c4: e06b b.n 800229e } /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 80021c6: 68fb ldr r3, [r7, #12] 80021c8: 6a5b ldr r3, [r3, #36] ; 0x24 80021ca: 781a ldrb r2, [r3, #0] 80021cc: 68fb ldr r3, [r7, #12] 80021ce: 681b ldr r3, [r3, #0] 80021d0: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80021d2: 68fb ldr r3, [r7, #12] 80021d4: 6a5b ldr r3, [r3, #36] ; 0x24 80021d6: 1c5a adds r2, r3, #1 80021d8: 68fb ldr r3, [r7, #12] 80021da: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80021dc: 68fb ldr r3, [r7, #12] 80021de: 8d1b ldrh r3, [r3, #40] ; 0x28 80021e0: 3b01 subs r3, #1 80021e2: b29a uxth r2, r3 80021e4: 68fb ldr r3, [r7, #12] 80021e6: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80021e8: 68fb ldr r3, [r7, #12] 80021ea: 8d5b ldrh r3, [r3, #42] ; 0x2a 80021ec: b29b uxth r3, r3 80021ee: 3b01 subs r3, #1 80021f0: b29a uxth r2, r3 80021f2: 68fb ldr r3, [r7, #12] 80021f4: 855a strh r2, [r3, #42] ; 0x2a if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 80021f6: 68fb ldr r3, [r7, #12] 80021f8: 681b ldr r3, [r3, #0] 80021fa: 695b ldr r3, [r3, #20] 80021fc: f003 0304 and.w r3, r3, #4 8002200: 2b04 cmp r3, #4 8002202: d11b bne.n 800223c 8002204: 68fb ldr r3, [r7, #12] 8002206: 8d1b ldrh r3, [r3, #40] ; 0x28 8002208: 2b00 cmp r3, #0 800220a: d017 beq.n 800223c { /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 800220c: 68fb ldr r3, [r7, #12] 800220e: 6a5b ldr r3, [r3, #36] ; 0x24 8002210: 781a ldrb r2, [r3, #0] 8002212: 68fb ldr r3, [r7, #12] 8002214: 681b ldr r3, [r3, #0] 8002216: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002218: 68fb ldr r3, [r7, #12] 800221a: 6a5b ldr r3, [r3, #36] ; 0x24 800221c: 1c5a adds r2, r3, #1 800221e: 68fb ldr r3, [r7, #12] 8002220: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002222: 68fb ldr r3, [r7, #12] 8002224: 8d1b ldrh r3, [r3, #40] ; 0x28 8002226: 3b01 subs r3, #1 8002228: b29a uxth r2, r3 800222a: 68fb ldr r3, [r7, #12] 800222c: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800222e: 68fb ldr r3, [r7, #12] 8002230: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002232: b29b uxth r3, r3 8002234: 3b01 subs r3, #1 8002236: b29a uxth r2, r3 8002238: 68fb ldr r3, [r7, #12] 800223a: 855a strh r2, [r3, #42] ; 0x2a while (hi2c->XferSize > 0U) 800223c: 68fb ldr r3, [r7, #12] 800223e: 8d1b ldrh r3, [r3, #40] ; 0x28 8002240: 2b00 cmp r3, #0 8002242: d1aa bne.n 800219a } } /* Wait until BTF flag is set */ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8002244: 697a ldr r2, [r7, #20] 8002246: 6ab9 ldr r1, [r7, #40] ; 0x28 8002248: 68f8 ldr r0, [r7, #12] 800224a: f000 fd2e bl 8002caa 800224e: 4603 mov r3, r0 8002250: 2b00 cmp r3, #0 8002252: d00d beq.n 8002270 { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 8002254: 68fb ldr r3, [r7, #12] 8002256: 6c1b ldr r3, [r3, #64] ; 0x40 8002258: 2b04 cmp r3, #4 800225a: d107 bne.n 800226c { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 800225c: 68fb ldr r3, [r7, #12] 800225e: 681b ldr r3, [r3, #0] 8002260: 681a ldr r2, [r3, #0] 8002262: 68fb ldr r3, [r7, #12] 8002264: 681b ldr r3, [r3, #0] 8002266: f442 7200 orr.w r2, r2, #512 ; 0x200 800226a: 601a str r2, [r3, #0] } return HAL_ERROR; 800226c: 2301 movs r3, #1 800226e: e016 b.n 800229e } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002270: 68fb ldr r3, [r7, #12] 8002272: 681b ldr r3, [r3, #0] 8002274: 681a ldr r2, [r3, #0] 8002276: 68fb ldr r3, [r7, #12] 8002278: 681b ldr r3, [r3, #0] 800227a: f442 7200 orr.w r2, r2, #512 ; 0x200 800227e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8002280: 68fb ldr r3, [r7, #12] 8002282: 2220 movs r2, #32 8002284: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8002288: 68fb ldr r3, [r7, #12] 800228a: 2200 movs r2, #0 800228c: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002290: 68fb ldr r3, [r7, #12] 8002292: 2200 movs r2, #0 8002294: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8002298: 2300 movs r3, #0 800229a: e000 b.n 800229e } else { return HAL_BUSY; 800229c: 2302 movs r3, #2 } } 800229e: 4618 mov r0, r3 80022a0: 3718 adds r7, #24 80022a2: 46bd mov sp, r7 80022a4: bd80 pop {r7, pc} 80022a6: bf00 nop 80022a8: 00100002 .word 0x00100002 80022ac: ffff0000 .word 0xffff0000 080022b0 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80022b0: b580 push {r7, lr} 80022b2: b08c sub sp, #48 ; 0x30 80022b4: af02 add r7, sp, #8 80022b6: 60f8 str r0, [r7, #12] 80022b8: 4608 mov r0, r1 80022ba: 4611 mov r1, r2 80022bc: 461a mov r2, r3 80022be: 4603 mov r3, r0 80022c0: 817b strh r3, [r7, #10] 80022c2: 460b mov r3, r1 80022c4: 813b strh r3, [r7, #8] 80022c6: 4613 mov r3, r2 80022c8: 80fb strh r3, [r7, #6] __IO uint32_t count = 0U; 80022ca: 2300 movs r3, #0 80022cc: 623b str r3, [r7, #32] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 80022ce: f7ff fadb bl 8001888 80022d2: 6278 str r0, [r7, #36] ; 0x24 /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80022d4: 68fb ldr r3, [r7, #12] 80022d6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80022da: b2db uxtb r3, r3 80022dc: 2b20 cmp r3, #32 80022de: f040 8244 bne.w 800276a { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 80022e2: 6a7b ldr r3, [r7, #36] ; 0x24 80022e4: 9300 str r3, [sp, #0] 80022e6: 2319 movs r3, #25 80022e8: 2201 movs r2, #1 80022ea: 4982 ldr r1, [pc, #520] ; (80024f4 ) 80022ec: 68f8 ldr r0, [r7, #12] 80022ee: f000 fbc5 bl 8002a7c 80022f2: 4603 mov r3, r0 80022f4: 2b00 cmp r3, #0 80022f6: d001 beq.n 80022fc { return HAL_BUSY; 80022f8: 2302 movs r3, #2 80022fa: e237 b.n 800276c } /* Process Locked */ __HAL_LOCK(hi2c); 80022fc: 68fb ldr r3, [r7, #12] 80022fe: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002302: 2b01 cmp r3, #1 8002304: d101 bne.n 800230a 8002306: 2302 movs r3, #2 8002308: e230 b.n 800276c 800230a: 68fb ldr r3, [r7, #12] 800230c: 2201 movs r2, #1 800230e: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 8002312: 68fb ldr r3, [r7, #12] 8002314: 681b ldr r3, [r3, #0] 8002316: 681b ldr r3, [r3, #0] 8002318: f003 0301 and.w r3, r3, #1 800231c: 2b01 cmp r3, #1 800231e: d007 beq.n 8002330 { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002320: 68fb ldr r3, [r7, #12] 8002322: 681b ldr r3, [r3, #0] 8002324: 681a ldr r2, [r3, #0] 8002326: 68fb ldr r3, [r7, #12] 8002328: 681b ldr r3, [r3, #0] 800232a: f042 0201 orr.w r2, r2, #1 800232e: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8002330: 68fb ldr r3, [r7, #12] 8002332: 681b ldr r3, [r3, #0] 8002334: 681a ldr r2, [r3, #0] 8002336: 68fb ldr r3, [r7, #12] 8002338: 681b ldr r3, [r3, #0] 800233a: f422 6200 bic.w r2, r2, #2048 ; 0x800 800233e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_RX; 8002340: 68fb ldr r3, [r7, #12] 8002342: 2222 movs r2, #34 ; 0x22 8002344: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 8002348: 68fb ldr r3, [r7, #12] 800234a: 2240 movs r2, #64 ; 0x40 800234c: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002350: 68fb ldr r3, [r7, #12] 8002352: 2200 movs r2, #0 8002354: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8002356: 68fb ldr r3, [r7, #12] 8002358: 6b3a ldr r2, [r7, #48] ; 0x30 800235a: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 800235c: 68fb ldr r3, [r7, #12] 800235e: 8eba ldrh r2, [r7, #52] ; 0x34 8002360: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 8002362: 68fb ldr r3, [r7, #12] 8002364: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002366: b29a uxth r2, r3 8002368: 68fb ldr r3, [r7, #12] 800236a: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 800236c: 68fb ldr r3, [r7, #12] 800236e: 4a62 ldr r2, [pc, #392] ; (80024f8 ) 8002370: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 8002372: 88f8 ldrh r0, [r7, #6] 8002374: 893a ldrh r2, [r7, #8] 8002376: 8979 ldrh r1, [r7, #10] 8002378: 6a7b ldr r3, [r7, #36] ; 0x24 800237a: 9301 str r3, [sp, #4] 800237c: 6bbb ldr r3, [r7, #56] ; 0x38 800237e: 9300 str r3, [sp, #0] 8002380: 4603 mov r3, r0 8002382: 68f8 ldr r0, [r7, #12] 8002384: f000 fa92 bl 80028ac 8002388: 4603 mov r3, r0 800238a: 2b00 cmp r3, #0 800238c: d001 beq.n 8002392 { return HAL_ERROR; 800238e: 2301 movs r3, #1 8002390: e1ec b.n 800276c } if (hi2c->XferSize == 0U) 8002392: 68fb ldr r3, [r7, #12] 8002394: 8d1b ldrh r3, [r3, #40] ; 0x28 8002396: 2b00 cmp r3, #0 8002398: d113 bne.n 80023c2 { /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 800239a: 2300 movs r3, #0 800239c: 61fb str r3, [r7, #28] 800239e: 68fb ldr r3, [r7, #12] 80023a0: 681b ldr r3, [r3, #0] 80023a2: 695b ldr r3, [r3, #20] 80023a4: 61fb str r3, [r7, #28] 80023a6: 68fb ldr r3, [r7, #12] 80023a8: 681b ldr r3, [r3, #0] 80023aa: 699b ldr r3, [r3, #24] 80023ac: 61fb str r3, [r7, #28] 80023ae: 69fb ldr r3, [r7, #28] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80023b0: 68fb ldr r3, [r7, #12] 80023b2: 681b ldr r3, [r3, #0] 80023b4: 681a ldr r2, [r3, #0] 80023b6: 68fb ldr r3, [r7, #12] 80023b8: 681b ldr r3, [r3, #0] 80023ba: f442 7200 orr.w r2, r2, #512 ; 0x200 80023be: 601a str r2, [r3, #0] 80023c0: e1c0 b.n 8002744 } else if (hi2c->XferSize == 1U) 80023c2: 68fb ldr r3, [r7, #12] 80023c4: 8d1b ldrh r3, [r3, #40] ; 0x28 80023c6: 2b01 cmp r3, #1 80023c8: d11e bne.n 8002408 { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80023ca: 68fb ldr r3, [r7, #12] 80023cc: 681b ldr r3, [r3, #0] 80023ce: 681a ldr r2, [r3, #0] 80023d0: 68fb ldr r3, [r7, #12] 80023d2: 681b ldr r3, [r3, #0] 80023d4: f422 6280 bic.w r2, r2, #1024 ; 0x400 80023d8: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 80023da: b672 cpsid i } 80023dc: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 80023de: 2300 movs r3, #0 80023e0: 61bb str r3, [r7, #24] 80023e2: 68fb ldr r3, [r7, #12] 80023e4: 681b ldr r3, [r3, #0] 80023e6: 695b ldr r3, [r3, #20] 80023e8: 61bb str r3, [r7, #24] 80023ea: 68fb ldr r3, [r7, #12] 80023ec: 681b ldr r3, [r3, #0] 80023ee: 699b ldr r3, [r3, #24] 80023f0: 61bb str r3, [r7, #24] 80023f2: 69bb ldr r3, [r7, #24] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80023f4: 68fb ldr r3, [r7, #12] 80023f6: 681b ldr r3, [r3, #0] 80023f8: 681a ldr r2, [r3, #0] 80023fa: 68fb ldr r3, [r7, #12] 80023fc: 681b ldr r3, [r3, #0] 80023fe: f442 7200 orr.w r2, r2, #512 ; 0x200 8002402: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8002404: b662 cpsie i } 8002406: e035 b.n 8002474 /* Re-enable IRQs */ __enable_irq(); } else if (hi2c->XferSize == 2U) 8002408: 68fb ldr r3, [r7, #12] 800240a: 8d1b ldrh r3, [r3, #40] ; 0x28 800240c: 2b02 cmp r3, #2 800240e: d11e bne.n 800244e { /* Enable Pos */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8002410: 68fb ldr r3, [r7, #12] 8002412: 681b ldr r3, [r3, #0] 8002414: 681a ldr r2, [r3, #0] 8002416: 68fb ldr r3, [r7, #12] 8002418: 681b ldr r3, [r3, #0] 800241a: f442 6200 orr.w r2, r2, #2048 ; 0x800 800241e: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8002420: b672 cpsid i } 8002422: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8002424: 2300 movs r3, #0 8002426: 617b str r3, [r7, #20] 8002428: 68fb ldr r3, [r7, #12] 800242a: 681b ldr r3, [r3, #0] 800242c: 695b ldr r3, [r3, #20] 800242e: 617b str r3, [r7, #20] 8002430: 68fb ldr r3, [r7, #12] 8002432: 681b ldr r3, [r3, #0] 8002434: 699b ldr r3, [r3, #24] 8002436: 617b str r3, [r7, #20] 8002438: 697b ldr r3, [r7, #20] /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 800243a: 68fb ldr r3, [r7, #12] 800243c: 681b ldr r3, [r3, #0] 800243e: 681a ldr r2, [r3, #0] 8002440: 68fb ldr r3, [r7, #12] 8002442: 681b ldr r3, [r3, #0] 8002444: f422 6280 bic.w r2, r2, #1024 ; 0x400 8002448: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 800244a: b662 cpsie i } 800244c: e012 b.n 8002474 __enable_irq(); } else { /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 800244e: 68fb ldr r3, [r7, #12] 8002450: 681b ldr r3, [r3, #0] 8002452: 681a ldr r2, [r3, #0] 8002454: 68fb ldr r3, [r7, #12] 8002456: 681b ldr r3, [r3, #0] 8002458: f442 6280 orr.w r2, r2, #1024 ; 0x400 800245c: 601a str r2, [r3, #0] /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 800245e: 2300 movs r3, #0 8002460: 613b str r3, [r7, #16] 8002462: 68fb ldr r3, [r7, #12] 8002464: 681b ldr r3, [r3, #0] 8002466: 695b ldr r3, [r3, #20] 8002468: 613b str r3, [r7, #16] 800246a: 68fb ldr r3, [r7, #12] 800246c: 681b ldr r3, [r3, #0] 800246e: 699b ldr r3, [r3, #24] 8002470: 613b str r3, [r7, #16] 8002472: 693b ldr r3, [r7, #16] } while (hi2c->XferSize > 0U) 8002474: e166 b.n 8002744 { if (hi2c->XferSize <= 3U) 8002476: 68fb ldr r3, [r7, #12] 8002478: 8d1b ldrh r3, [r3, #40] ; 0x28 800247a: 2b03 cmp r3, #3 800247c: f200 811f bhi.w 80026be { /* One byte */ if (hi2c->XferSize == 1U) 8002480: 68fb ldr r3, [r7, #12] 8002482: 8d1b ldrh r3, [r3, #40] ; 0x28 8002484: 2b01 cmp r3, #1 8002486: d123 bne.n 80024d0 { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8002488: 6a7a ldr r2, [r7, #36] ; 0x24 800248a: 6bb9 ldr r1, [r7, #56] ; 0x38 800248c: 68f8 ldr r0, [r7, #12] 800248e: f000 fc4d bl 8002d2c 8002492: 4603 mov r3, r0 8002494: 2b00 cmp r3, #0 8002496: d001 beq.n 800249c { return HAL_ERROR; 8002498: 2301 movs r3, #1 800249a: e167 b.n 800276c } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 800249c: 68fb ldr r3, [r7, #12] 800249e: 681b ldr r3, [r3, #0] 80024a0: 691a ldr r2, [r3, #16] 80024a2: 68fb ldr r3, [r7, #12] 80024a4: 6a5b ldr r3, [r3, #36] ; 0x24 80024a6: b2d2 uxtb r2, r2 80024a8: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80024aa: 68fb ldr r3, [r7, #12] 80024ac: 6a5b ldr r3, [r3, #36] ; 0x24 80024ae: 1c5a adds r2, r3, #1 80024b0: 68fb ldr r3, [r7, #12] 80024b2: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80024b4: 68fb ldr r3, [r7, #12] 80024b6: 8d1b ldrh r3, [r3, #40] ; 0x28 80024b8: 3b01 subs r3, #1 80024ba: b29a uxth r2, r3 80024bc: 68fb ldr r3, [r7, #12] 80024be: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80024c0: 68fb ldr r3, [r7, #12] 80024c2: 8d5b ldrh r3, [r3, #42] ; 0x2a 80024c4: b29b uxth r3, r3 80024c6: 3b01 subs r3, #1 80024c8: b29a uxth r2, r3 80024ca: 68fb ldr r3, [r7, #12] 80024cc: 855a strh r2, [r3, #42] ; 0x2a 80024ce: e139 b.n 8002744 } /* Two bytes */ else if (hi2c->XferSize == 2U) 80024d0: 68fb ldr r3, [r7, #12] 80024d2: 8d1b ldrh r3, [r3, #40] ; 0x28 80024d4: 2b02 cmp r3, #2 80024d6: d152 bne.n 800257e { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 80024d8: 6a7b ldr r3, [r7, #36] ; 0x24 80024da: 9300 str r3, [sp, #0] 80024dc: 6bbb ldr r3, [r7, #56] ; 0x38 80024de: 2200 movs r2, #0 80024e0: 4906 ldr r1, [pc, #24] ; (80024fc ) 80024e2: 68f8 ldr r0, [r7, #12] 80024e4: f000 faca bl 8002a7c 80024e8: 4603 mov r3, r0 80024ea: 2b00 cmp r3, #0 80024ec: d008 beq.n 8002500 { return HAL_ERROR; 80024ee: 2301 movs r3, #1 80024f0: e13c b.n 800276c 80024f2: bf00 nop 80024f4: 00100002 .word 0x00100002 80024f8: ffff0000 .word 0xffff0000 80024fc: 00010004 .word 0x00010004 __ASM volatile ("cpsid i" : : : "memory"); 8002500: b672 cpsid i } 8002502: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002504: 68fb ldr r3, [r7, #12] 8002506: 681b ldr r3, [r3, #0] 8002508: 681a ldr r2, [r3, #0] 800250a: 68fb ldr r3, [r7, #12] 800250c: 681b ldr r3, [r3, #0] 800250e: f442 7200 orr.w r2, r2, #512 ; 0x200 8002512: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002514: 68fb ldr r3, [r7, #12] 8002516: 681b ldr r3, [r3, #0] 8002518: 691a ldr r2, [r3, #16] 800251a: 68fb ldr r3, [r7, #12] 800251c: 6a5b ldr r3, [r3, #36] ; 0x24 800251e: b2d2 uxtb r2, r2 8002520: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002522: 68fb ldr r3, [r7, #12] 8002524: 6a5b ldr r3, [r3, #36] ; 0x24 8002526: 1c5a adds r2, r3, #1 8002528: 68fb ldr r3, [r7, #12] 800252a: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800252c: 68fb ldr r3, [r7, #12] 800252e: 8d1b ldrh r3, [r3, #40] ; 0x28 8002530: 3b01 subs r3, #1 8002532: b29a uxth r2, r3 8002534: 68fb ldr r3, [r7, #12] 8002536: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002538: 68fb ldr r3, [r7, #12] 800253a: 8d5b ldrh r3, [r3, #42] ; 0x2a 800253c: b29b uxth r3, r3 800253e: 3b01 subs r3, #1 8002540: b29a uxth r2, r3 8002542: 68fb ldr r3, [r7, #12] 8002544: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 8002546: b662 cpsie i } 8002548: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 800254a: 68fb ldr r3, [r7, #12] 800254c: 681b ldr r3, [r3, #0] 800254e: 691a ldr r2, [r3, #16] 8002550: 68fb ldr r3, [r7, #12] 8002552: 6a5b ldr r3, [r3, #36] ; 0x24 8002554: b2d2 uxtb r2, r2 8002556: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002558: 68fb ldr r3, [r7, #12] 800255a: 6a5b ldr r3, [r3, #36] ; 0x24 800255c: 1c5a adds r2, r3, #1 800255e: 68fb ldr r3, [r7, #12] 8002560: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002562: 68fb ldr r3, [r7, #12] 8002564: 8d1b ldrh r3, [r3, #40] ; 0x28 8002566: 3b01 subs r3, #1 8002568: b29a uxth r2, r3 800256a: 68fb ldr r3, [r7, #12] 800256c: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800256e: 68fb ldr r3, [r7, #12] 8002570: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002572: b29b uxth r3, r3 8002574: 3b01 subs r3, #1 8002576: b29a uxth r2, r3 8002578: 68fb ldr r3, [r7, #12] 800257a: 855a strh r2, [r3, #42] ; 0x2a 800257c: e0e2 b.n 8002744 } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 800257e: 6a7b ldr r3, [r7, #36] ; 0x24 8002580: 9300 str r3, [sp, #0] 8002582: 6bbb ldr r3, [r7, #56] ; 0x38 8002584: 2200 movs r2, #0 8002586: 497b ldr r1, [pc, #492] ; (8002774 ) 8002588: 68f8 ldr r0, [r7, #12] 800258a: f000 fa77 bl 8002a7c 800258e: 4603 mov r3, r0 8002590: 2b00 cmp r3, #0 8002592: d001 beq.n 8002598 { return HAL_ERROR; 8002594: 2301 movs r3, #1 8002596: e0e9 b.n 800276c } /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8002598: 68fb ldr r3, [r7, #12] 800259a: 681b ldr r3, [r3, #0] 800259c: 681a ldr r2, [r3, #0] 800259e: 68fb ldr r3, [r7, #12] 80025a0: 681b ldr r3, [r3, #0] 80025a2: f422 6280 bic.w r2, r2, #1024 ; 0x400 80025a6: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 80025a8: b672 cpsid i } 80025aa: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80025ac: 68fb ldr r3, [r7, #12] 80025ae: 681b ldr r3, [r3, #0] 80025b0: 691a ldr r2, [r3, #16] 80025b2: 68fb ldr r3, [r7, #12] 80025b4: 6a5b ldr r3, [r3, #36] ; 0x24 80025b6: b2d2 uxtb r2, r2 80025b8: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80025ba: 68fb ldr r3, [r7, #12] 80025bc: 6a5b ldr r3, [r3, #36] ; 0x24 80025be: 1c5a adds r2, r3, #1 80025c0: 68fb ldr r3, [r7, #12] 80025c2: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80025c4: 68fb ldr r3, [r7, #12] 80025c6: 8d1b ldrh r3, [r3, #40] ; 0x28 80025c8: 3b01 subs r3, #1 80025ca: b29a uxth r2, r3 80025cc: 68fb ldr r3, [r7, #12] 80025ce: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80025d0: 68fb ldr r3, [r7, #12] 80025d2: 8d5b ldrh r3, [r3, #42] ; 0x2a 80025d4: b29b uxth r3, r3 80025d6: 3b01 subs r3, #1 80025d8: b29a uxth r2, r3 80025da: 68fb ldr r3, [r7, #12] 80025dc: 855a strh r2, [r3, #42] ; 0x2a /* Wait until BTF flag is set */ count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 80025de: 4b66 ldr r3, [pc, #408] ; (8002778 ) 80025e0: 681b ldr r3, [r3, #0] 80025e2: 08db lsrs r3, r3, #3 80025e4: 4a65 ldr r2, [pc, #404] ; (800277c ) 80025e6: fba2 2303 umull r2, r3, r2, r3 80025ea: 0a1a lsrs r2, r3, #8 80025ec: 4613 mov r3, r2 80025ee: 009b lsls r3, r3, #2 80025f0: 4413 add r3, r2 80025f2: 00da lsls r2, r3, #3 80025f4: 1ad3 subs r3, r2, r3 80025f6: 623b str r3, [r7, #32] do { count--; 80025f8: 6a3b ldr r3, [r7, #32] 80025fa: 3b01 subs r3, #1 80025fc: 623b str r3, [r7, #32] if (count == 0U) 80025fe: 6a3b ldr r3, [r7, #32] 8002600: 2b00 cmp r3, #0 8002602: d118 bne.n 8002636 { hi2c->PreviousState = I2C_STATE_NONE; 8002604: 68fb ldr r3, [r7, #12] 8002606: 2200 movs r2, #0 8002608: 631a str r2, [r3, #48] ; 0x30 hi2c->State = HAL_I2C_STATE_READY; 800260a: 68fb ldr r3, [r7, #12] 800260c: 2220 movs r2, #32 800260e: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8002612: 68fb ldr r3, [r7, #12] 8002614: 2200 movs r2, #0 8002616: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 800261a: 68fb ldr r3, [r7, #12] 800261c: 6c1b ldr r3, [r3, #64] ; 0x40 800261e: f043 0220 orr.w r2, r3, #32 8002622: 68fb ldr r3, [r7, #12] 8002624: 641a str r2, [r3, #64] ; 0x40 __ASM volatile ("cpsie i" : : : "memory"); 8002626: b662 cpsie i } 8002628: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800262a: 68fb ldr r3, [r7, #12] 800262c: 2200 movs r2, #0 800262e: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_ERROR; 8002632: 2301 movs r3, #1 8002634: e09a b.n 800276c } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 8002636: 68fb ldr r3, [r7, #12] 8002638: 681b ldr r3, [r3, #0] 800263a: 695b ldr r3, [r3, #20] 800263c: f003 0304 and.w r3, r3, #4 8002640: 2b04 cmp r3, #4 8002642: d1d9 bne.n 80025f8 /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002644: 68fb ldr r3, [r7, #12] 8002646: 681b ldr r3, [r3, #0] 8002648: 681a ldr r2, [r3, #0] 800264a: 68fb ldr r3, [r7, #12] 800264c: 681b ldr r3, [r3, #0] 800264e: f442 7200 orr.w r2, r2, #512 ; 0x200 8002652: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002654: 68fb ldr r3, [r7, #12] 8002656: 681b ldr r3, [r3, #0] 8002658: 691a ldr r2, [r3, #16] 800265a: 68fb ldr r3, [r7, #12] 800265c: 6a5b ldr r3, [r3, #36] ; 0x24 800265e: b2d2 uxtb r2, r2 8002660: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002662: 68fb ldr r3, [r7, #12] 8002664: 6a5b ldr r3, [r3, #36] ; 0x24 8002666: 1c5a adds r2, r3, #1 8002668: 68fb ldr r3, [r7, #12] 800266a: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800266c: 68fb ldr r3, [r7, #12] 800266e: 8d1b ldrh r3, [r3, #40] ; 0x28 8002670: 3b01 subs r3, #1 8002672: b29a uxth r2, r3 8002674: 68fb ldr r3, [r7, #12] 8002676: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002678: 68fb ldr r3, [r7, #12] 800267a: 8d5b ldrh r3, [r3, #42] ; 0x2a 800267c: b29b uxth r3, r3 800267e: 3b01 subs r3, #1 8002680: b29a uxth r2, r3 8002682: 68fb ldr r3, [r7, #12] 8002684: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 8002686: b662 cpsie i } 8002688: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 800268a: 68fb ldr r3, [r7, #12] 800268c: 681b ldr r3, [r3, #0] 800268e: 691a ldr r2, [r3, #16] 8002690: 68fb ldr r3, [r7, #12] 8002692: 6a5b ldr r3, [r3, #36] ; 0x24 8002694: b2d2 uxtb r2, r2 8002696: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002698: 68fb ldr r3, [r7, #12] 800269a: 6a5b ldr r3, [r3, #36] ; 0x24 800269c: 1c5a adds r2, r3, #1 800269e: 68fb ldr r3, [r7, #12] 80026a0: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80026a2: 68fb ldr r3, [r7, #12] 80026a4: 8d1b ldrh r3, [r3, #40] ; 0x28 80026a6: 3b01 subs r3, #1 80026a8: b29a uxth r2, r3 80026aa: 68fb ldr r3, [r7, #12] 80026ac: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80026ae: 68fb ldr r3, [r7, #12] 80026b0: 8d5b ldrh r3, [r3, #42] ; 0x2a 80026b2: b29b uxth r3, r3 80026b4: 3b01 subs r3, #1 80026b6: b29a uxth r2, r3 80026b8: 68fb ldr r3, [r7, #12] 80026ba: 855a strh r2, [r3, #42] ; 0x2a 80026bc: e042 b.n 8002744 } } else { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80026be: 6a7a ldr r2, [r7, #36] ; 0x24 80026c0: 6bb9 ldr r1, [r7, #56] ; 0x38 80026c2: 68f8 ldr r0, [r7, #12] 80026c4: f000 fb32 bl 8002d2c 80026c8: 4603 mov r3, r0 80026ca: 2b00 cmp r3, #0 80026cc: d001 beq.n 80026d2 { return HAL_ERROR; 80026ce: 2301 movs r3, #1 80026d0: e04c b.n 800276c } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80026d2: 68fb ldr r3, [r7, #12] 80026d4: 681b ldr r3, [r3, #0] 80026d6: 691a ldr r2, [r3, #16] 80026d8: 68fb ldr r3, [r7, #12] 80026da: 6a5b ldr r3, [r3, #36] ; 0x24 80026dc: b2d2 uxtb r2, r2 80026de: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80026e0: 68fb ldr r3, [r7, #12] 80026e2: 6a5b ldr r3, [r3, #36] ; 0x24 80026e4: 1c5a adds r2, r3, #1 80026e6: 68fb ldr r3, [r7, #12] 80026e8: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80026ea: 68fb ldr r3, [r7, #12] 80026ec: 8d1b ldrh r3, [r3, #40] ; 0x28 80026ee: 3b01 subs r3, #1 80026f0: b29a uxth r2, r3 80026f2: 68fb ldr r3, [r7, #12] 80026f4: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80026f6: 68fb ldr r3, [r7, #12] 80026f8: 8d5b ldrh r3, [r3, #42] ; 0x2a 80026fa: b29b uxth r3, r3 80026fc: 3b01 subs r3, #1 80026fe: b29a uxth r2, r3 8002700: 68fb ldr r3, [r7, #12] 8002702: 855a strh r2, [r3, #42] ; 0x2a if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 8002704: 68fb ldr r3, [r7, #12] 8002706: 681b ldr r3, [r3, #0] 8002708: 695b ldr r3, [r3, #20] 800270a: f003 0304 and.w r3, r3, #4 800270e: 2b04 cmp r3, #4 8002710: d118 bne.n 8002744 { /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002712: 68fb ldr r3, [r7, #12] 8002714: 681b ldr r3, [r3, #0] 8002716: 691a ldr r2, [r3, #16] 8002718: 68fb ldr r3, [r7, #12] 800271a: 6a5b ldr r3, [r3, #36] ; 0x24 800271c: b2d2 uxtb r2, r2 800271e: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002720: 68fb ldr r3, [r7, #12] 8002722: 6a5b ldr r3, [r3, #36] ; 0x24 8002724: 1c5a adds r2, r3, #1 8002726: 68fb ldr r3, [r7, #12] 8002728: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800272a: 68fb ldr r3, [r7, #12] 800272c: 8d1b ldrh r3, [r3, #40] ; 0x28 800272e: 3b01 subs r3, #1 8002730: b29a uxth r2, r3 8002732: 68fb ldr r3, [r7, #12] 8002734: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002736: 68fb ldr r3, [r7, #12] 8002738: 8d5b ldrh r3, [r3, #42] ; 0x2a 800273a: b29b uxth r3, r3 800273c: 3b01 subs r3, #1 800273e: b29a uxth r2, r3 8002740: 68fb ldr r3, [r7, #12] 8002742: 855a strh r2, [r3, #42] ; 0x2a while (hi2c->XferSize > 0U) 8002744: 68fb ldr r3, [r7, #12] 8002746: 8d1b ldrh r3, [r3, #40] ; 0x28 8002748: 2b00 cmp r3, #0 800274a: f47f ae94 bne.w 8002476 } } } hi2c->State = HAL_I2C_STATE_READY; 800274e: 68fb ldr r3, [r7, #12] 8002750: 2220 movs r2, #32 8002752: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8002756: 68fb ldr r3, [r7, #12] 8002758: 2200 movs r2, #0 800275a: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800275e: 68fb ldr r3, [r7, #12] 8002760: 2200 movs r2, #0 8002762: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8002766: 2300 movs r3, #0 8002768: e000 b.n 800276c } else { return HAL_BUSY; 800276a: 2302 movs r3, #2 } } 800276c: 4618 mov r0, r3 800276e: 3728 adds r7, #40 ; 0x28 8002770: 46bd mov sp, r7 8002772: bd80 pop {r7, pc} 8002774: 00010004 .word 0x00010004 8002778: 20000000 .word 0x20000000 800277c: 14f8b589 .word 0x14f8b589 08002780