: /** * @brief The application entry point. * @retval int */ int main(void) { 8001220: b580 push {r7, lr} 8001222: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001224: f000 fb8e bl 8001944 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001228: f000 f809 bl 800123e /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800122c: f000 f87a bl 8001324 MX_FSMC_Init(); 8001230: f000 f93a bl 80014a8 MX_I2C2_Init(); 8001234: f000 f848 bl 80012c8 /* USER CODE BEGIN 2 */ main_app(); 8001238: f005 f8b8 bl 80063ac /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 800123c: e7fe b.n 800123c 0800123e : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800123e: b580 push {r7, lr} 8001240: b090 sub sp, #64 ; 0x40 8001242: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001244: f107 0318 add.w r3, r7, #24 8001248: 2228 movs r2, #40 ; 0x28 800124a: 2100 movs r1, #0 800124c: 4618 mov r0, r3 800124e: f005 fc17 bl 8006a80 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001252: 1d3b adds r3, r7, #4 8001254: 2200 movs r2, #0 8001256: 601a str r2, [r3, #0] 8001258: 605a str r2, [r3, #4] 800125a: 609a str r2, [r3, #8] 800125c: 60da str r2, [r3, #12] 800125e: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001260: 2301 movs r3, #1 8001262: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001264: f44f 3380 mov.w r3, #65536 ; 0x10000 8001268: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 800126a: 2300 movs r3, #0 800126c: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800126e: 2301 movs r3, #1 8001270: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8001272: 2302 movs r3, #2 8001274: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8001276: f44f 3380 mov.w r3, #65536 ; 0x10000 800127a: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800127c: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8001280: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001282: f107 0318 add.w r3, r7, #24 8001286: 4618 mov r0, r3 8001288: f001 fe8a bl 8002fa0 800128c: 4603 mov r3, r0 800128e: 2b00 cmp r3, #0 8001290: d001 beq.n 8001296 { Error_Handler(); 8001292: f000 f96d bl 8001570 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001296: 230f movs r3, #15 8001298: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800129a: 2302 movs r3, #2 800129c: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800129e: 2300 movs r3, #0 80012a0: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80012a2: f44f 6380 mov.w r3, #1024 ; 0x400 80012a6: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80012a8: 2300 movs r3, #0 80012aa: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80012ac: 1d3b adds r3, r7, #4 80012ae: 2102 movs r1, #2 80012b0: 4618 mov r0, r3 80012b2: f002 f8f5 bl 80034a0 80012b6: 4603 mov r3, r0 80012b8: 2b00 cmp r3, #0 80012ba: d001 beq.n 80012c0 { Error_Handler(); 80012bc: f000 f958 bl 8001570 } } 80012c0: bf00 nop 80012c2: 3740 adds r7, #64 ; 0x40 80012c4: 46bd mov sp, r7 80012c6: bd80 pop {r7, pc} 080012c8 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 80012c8: b580 push {r7, lr} 80012ca: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 80012cc: 4b12 ldr r3, [pc, #72] ; (8001318 ) 80012ce: 4a13 ldr r2, [pc, #76] ; (800131c ) 80012d0: 601a str r2, [r3, #0] hi2c2.Init.ClockSpeed = 100000; 80012d2: 4b11 ldr r3, [pc, #68] ; (8001318 ) 80012d4: 4a12 ldr r2, [pc, #72] ; (8001320 ) 80012d6: 605a str r2, [r3, #4] hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2; 80012d8: 4b0f ldr r3, [pc, #60] ; (8001318 ) 80012da: 2200 movs r2, #0 80012dc: 609a str r2, [r3, #8] hi2c2.Init.OwnAddress1 = 0; 80012de: 4b0e ldr r3, [pc, #56] ; (8001318 ) 80012e0: 2200 movs r2, #0 80012e2: 60da str r2, [r3, #12] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80012e4: 4b0c ldr r3, [pc, #48] ; (8001318 ) 80012e6: f44f 4280 mov.w r2, #16384 ; 0x4000 80012ea: 611a str r2, [r3, #16] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80012ec: 4b0a ldr r3, [pc, #40] ; (8001318 ) 80012ee: 2200 movs r2, #0 80012f0: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2 = 0; 80012f2: 4b09 ldr r3, [pc, #36] ; (8001318 ) 80012f4: 2200 movs r2, #0 80012f6: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80012f8: 4b07 ldr r3, [pc, #28] ; (8001318 ) 80012fa: 2200 movs r2, #0 80012fc: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80012fe: 4b06 ldr r3, [pc, #24] ; (8001318 ) 8001300: 2200 movs r2, #0 8001302: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 8001304: 4804 ldr r0, [pc, #16] ; (8001318 ) 8001306: f000 fe4b bl 8001fa0 800130a: 4603 mov r3, r0 800130c: 2b00 cmp r3, #0 800130e: d001 beq.n 8001314 { Error_Handler(); 8001310: f000 f92e bl 8001570 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 8001314: bf00 nop 8001316: bd80 pop {r7, pc} 8001318: 20000218 .word 0x20000218 800131c: 40005800 .word 0x40005800 8001320: 000186a0 .word 0x000186a0 08001324 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001324: b580 push {r7, lr} 8001326: b08a sub sp, #40 ; 0x28 8001328: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800132a: f107 0318 add.w r3, r7, #24 800132e: 2200 movs r2, #0 8001330: 601a str r2, [r3, #0] 8001332: 605a str r2, [r3, #4] 8001334: 609a str r2, [r3, #8] 8001336: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8001338: 4b58 ldr r3, [pc, #352] ; (800149c ) 800133a: 699b ldr r3, [r3, #24] 800133c: 4a57 ldr r2, [pc, #348] ; (800149c ) 800133e: f043 0380 orr.w r3, r3, #128 ; 0x80 8001342: 6193 str r3, [r2, #24] 8001344: 4b55 ldr r3, [pc, #340] ; (800149c ) 8001346: 699b ldr r3, [r3, #24] 8001348: f003 0380 and.w r3, r3, #128 ; 0x80 800134c: 617b str r3, [r7, #20] 800134e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001350: 4b52 ldr r3, [pc, #328] ; (800149c ) 8001352: 699b ldr r3, [r3, #24] 8001354: 4a51 ldr r2, [pc, #324] ; (800149c ) 8001356: f043 0308 orr.w r3, r3, #8 800135a: 6193 str r3, [r2, #24] 800135c: 4b4f ldr r3, [pc, #316] ; (800149c ) 800135e: 699b ldr r3, [r3, #24] 8001360: f003 0308 and.w r3, r3, #8 8001364: 613b str r3, [r7, #16] 8001366: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 8001368: 4b4c ldr r3, [pc, #304] ; (800149c ) 800136a: 699b ldr r3, [r3, #24] 800136c: 4a4b ldr r2, [pc, #300] ; (800149c ) 800136e: f443 7380 orr.w r3, r3, #256 ; 0x100 8001372: 6193 str r3, [r2, #24] 8001374: 4b49 ldr r3, [pc, #292] ; (800149c ) 8001376: 699b ldr r3, [r3, #24] 8001378: f403 7380 and.w r3, r3, #256 ; 0x100 800137c: 60fb str r3, [r7, #12] 800137e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001380: 4b46 ldr r3, [pc, #280] ; (800149c ) 8001382: 699b ldr r3, [r3, #24] 8001384: 4a45 ldr r2, [pc, #276] ; (800149c ) 8001386: f043 0340 orr.w r3, r3, #64 ; 0x40 800138a: 6193 str r3, [r2, #24] 800138c: 4b43 ldr r3, [pc, #268] ; (800149c ) 800138e: 699b ldr r3, [r3, #24] 8001390: f003 0340 and.w r3, r3, #64 ; 0x40 8001394: 60bb str r3, [r7, #8] 8001396: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001398: 4b40 ldr r3, [pc, #256] ; (800149c ) 800139a: 699b ldr r3, [r3, #24] 800139c: 4a3f ldr r2, [pc, #252] ; (800149c ) 800139e: f043 0320 orr.w r3, r3, #32 80013a2: 6193 str r3, [r2, #24] 80013a4: 4b3d ldr r3, [pc, #244] ; (800149c ) 80013a6: 699b ldr r3, [r3, #24] 80013a8: f003 0320 and.w r3, r3, #32 80013ac: 607b str r3, [r7, #4] 80013ae: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TDIN_GPIO_Port, TDIN_Pin, GPIO_PIN_SET); 80013b0: 2201 movs r2, #1 80013b2: f44f 7100 mov.w r1, #512 ; 0x200 80013b6: 483a ldr r0, [pc, #232] ; (80014a0 ) 80013b8: f000 fdd9 bl 8001f6e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); 80013bc: 2200 movs r2, #0 80013be: 2101 movs r1, #1 80013c0: 4838 ldr r0, [pc, #224] ; (80014a4 ) 80013c2: f000 fdd4 bl 8001f6e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, TCLK_Pin|TCS_Pin|MAX_IRD_Pin|MAX_RD_Pin, GPIO_PIN_SET); 80013c6: 2201 movs r2, #1 80013c8: f245 0106 movw r1, #20486 ; 0x5006 80013cc: 4835 ldr r0, [pc, #212] ; (80014a4 ) 80013ce: f000 fdce bl 8001f6e /*Configure GPIO pin : TDOUT_Pin */ GPIO_InitStruct.Pin = TDOUT_Pin; 80013d2: f44f 7380 mov.w r3, #256 ; 0x100 80013d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80013d8: 2300 movs r3, #0 80013da: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013dc: 2300 movs r3, #0 80013de: 623b str r3, [r7, #32] HAL_GPIO_Init(TDOUT_GPIO_Port, &GPIO_InitStruct); 80013e0: f107 0318 add.w r3, r7, #24 80013e4: 4619 mov r1, r3 80013e6: 482e ldr r0, [pc, #184] ; (80014a0 ) 80013e8: f000 fc16 bl 8001c18 /*Configure GPIO pin : TDIN_Pin */ GPIO_InitStruct.Pin = TDIN_Pin; 80013ec: f44f 7300 mov.w r3, #512 ; 0x200 80013f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80013f2: 2301 movs r3, #1 80013f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013f6: 2300 movs r3, #0 80013f8: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80013fa: 2303 movs r3, #3 80013fc: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(TDIN_GPIO_Port, &GPIO_InitStruct); 80013fe: f107 0318 add.w r3, r7, #24 8001402: 4619 mov r1, r3 8001404: 4826 ldr r0, [pc, #152] ; (80014a0 ) 8001406: f000 fc07 bl 8001c18 /*Configure GPIO pin : TPEN_Pin */ GPIO_InitStruct.Pin = TPEN_Pin; 800140a: f44f 6380 mov.w r3, #1024 ; 0x400 800140e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001410: 2300 movs r3, #0 8001412: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001414: 2301 movs r3, #1 8001416: 623b str r3, [r7, #32] HAL_GPIO_Init(TPEN_GPIO_Port, &GPIO_InitStruct); 8001418: f107 0318 add.w r3, r7, #24 800141c: 4619 mov r1, r3 800141e: 4820 ldr r0, [pc, #128] ; (80014a0 ) 8001420: f000 fbfa bl 8001c18 /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 8001424: 2301 movs r3, #1 8001426: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001428: 2301 movs r3, #1 800142a: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800142c: 2300 movs r3, #0 800142e: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001430: 2302 movs r3, #2 8001432: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 8001434: f107 0318 add.w r3, r7, #24 8001438: 4619 mov r1, r3 800143a: 481a ldr r0, [pc, #104] ; (80014a4 ) 800143c: f000 fbec bl 8001c18 /*Configure GPIO pins : TCLK_Pin TCS_Pin */ GPIO_InitStruct.Pin = TCLK_Pin|TCS_Pin; 8001440: 2306 movs r3, #6 8001442: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001444: 2301 movs r3, #1 8001446: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001448: 2300 movs r3, #0 800144a: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800144c: 2303 movs r3, #3 800144e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001450: f107 0318 add.w r3, r7, #24 8001454: 4619 mov r1, r3 8001456: 4813 ldr r0, [pc, #76] ; (80014a4 ) 8001458: f000 fbde bl 8001c18 /*Configure GPIO pins : MAX_IRD_Pin MAX_RD_Pin */ GPIO_InitStruct.Pin = MAX_IRD_Pin|MAX_RD_Pin; 800145c: f44f 43a0 mov.w r3, #20480 ; 0x5000 8001460: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001462: 2301 movs r3, #1 8001464: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001466: 2301 movs r3, #1 8001468: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800146a: 2303 movs r3, #3 800146c: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800146e: f107 0318 add.w r3, r7, #24 8001472: 4619 mov r1, r3 8001474: 480b ldr r0, [pc, #44] ; (80014a4 ) 8001476: f000 fbcf bl 8001c18 /*Configure GPIO pin : MAX_INT_Pin */ GPIO_InitStruct.Pin = MAX_INT_Pin; 800147a: f44f 5300 mov.w r3, #8192 ; 0x2000 800147e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001480: 2300 movs r3, #0 8001482: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001484: 2301 movs r3, #1 8001486: 623b str r3, [r7, #32] HAL_GPIO_Init(MAX_INT_GPIO_Port, &GPIO_InitStruct); 8001488: f107 0318 add.w r3, r7, #24 800148c: 4619 mov r1, r3 800148e: 4805 ldr r0, [pc, #20] ; (80014a4 ) 8001490: f000 fbc2 bl 8001c18 } 8001494: bf00 nop 8001496: 3728 adds r7, #40 ; 0x28 8001498: 46bd mov sp, r7 800149a: bd80 pop {r7, pc} 800149c: 40021000 .word 0x40021000 80014a0: 40011c00 .word 0x40011c00 80014a4: 40010c00 .word 0x40010c00 080014a8 : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 80014a8: b580 push {r7, lr} 80014aa: b088 sub sp, #32 80014ac: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 80014ae: 1d3b adds r3, r7, #4 80014b0: 2200 movs r2, #0 80014b2: 601a str r2, [r3, #0] 80014b4: 605a str r2, [r3, #4] 80014b6: 609a str r2, [r3, #8] 80014b8: 60da str r2, [r3, #12] 80014ba: 611a str r2, [r3, #16] 80014bc: 615a str r2, [r3, #20] 80014be: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 80014c0: 4b28 ldr r3, [pc, #160] ; (8001564 ) 80014c2: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 80014c6: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 80014c8: 4b26 ldr r3, [pc, #152] ; (8001564 ) 80014ca: 4a27 ldr r2, [pc, #156] ; (8001568 ) 80014cc: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 80014ce: 4b25 ldr r3, [pc, #148] ; (8001564 ) 80014d0: 2206 movs r2, #6 80014d2: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 80014d4: 4b23 ldr r3, [pc, #140] ; (8001564 ) 80014d6: 2200 movs r2, #0 80014d8: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 80014da: 4b22 ldr r3, [pc, #136] ; (8001564 ) 80014dc: 2200 movs r2, #0 80014de: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 80014e0: 4b20 ldr r3, [pc, #128] ; (8001564 ) 80014e2: 2210 movs r2, #16 80014e4: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 80014e6: 4b1f ldr r3, [pc, #124] ; (8001564 ) 80014e8: 2200 movs r2, #0 80014ea: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 80014ec: 4b1d ldr r3, [pc, #116] ; (8001564 ) 80014ee: 2200 movs r2, #0 80014f0: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 80014f2: 4b1c ldr r3, [pc, #112] ; (8001564 ) 80014f4: 2200 movs r2, #0 80014f6: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 80014f8: 4b1a ldr r3, [pc, #104] ; (8001564 ) 80014fa: 2200 movs r2, #0 80014fc: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 80014fe: 4b19 ldr r3, [pc, #100] ; (8001564 ) 8001500: f44f 5280 mov.w r2, #4096 ; 0x1000 8001504: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 8001506: 4b17 ldr r3, [pc, #92] ; (8001564 ) 8001508: 2200 movs r2, #0 800150a: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 800150c: 4b15 ldr r3, [pc, #84] ; (8001564 ) 800150e: 2200 movs r2, #0 8001510: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 8001512: 4b14 ldr r3, [pc, #80] ; (8001564 ) 8001514: 2200 movs r2, #0 8001516: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 8001518: 4b12 ldr r3, [pc, #72] ; (8001564 ) 800151a: 2200 movs r2, #0 800151c: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 800151e: 2300 movs r3, #0 8001520: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 8001522: 230f movs r3, #15 8001524: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 8001526: 2301 movs r3, #1 8001528: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 0; 800152a: 2300 movs r3, #0 800152c: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 800152e: 2310 movs r3, #16 8001530: 617b str r3, [r7, #20] Timing.DataLatency = 17; 8001532: 2311 movs r3, #17 8001534: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 8001536: 2300 movs r3, #0 8001538: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 800153a: 1d3b adds r3, r7, #4 800153c: 2200 movs r2, #0 800153e: 4619 mov r1, r3 8001540: 4808 ldr r0, [pc, #32] ; (8001564 ) 8001542: f002 f933 bl 80037ac 8001546: 4603 mov r3, r0 8001548: 2b00 cmp r3, #0 800154a: d001 beq.n 8001550 { Error_Handler( ); 800154c: f000 f810 bl 8001570 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 8001550: 4b06 ldr r3, [pc, #24] ; (800156c ) 8001552: 69db ldr r3, [r3, #28] 8001554: 4a05 ldr r2, [pc, #20] ; (800156c ) 8001556: f443 6380 orr.w r3, r3, #1024 ; 0x400 800155a: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 800155c: bf00 nop 800155e: 3720 adds r7, #32 8001560: 46bd mov sp, r7 8001562: bd80 pop {r7, pc} 8001564: 2000026c .word 0x2000026c 8001568: a0000104 .word 0xa0000104 800156c: 40010000 .word 0x40010000 08001570 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001570: b480 push {r7} 8001572: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001574: b672 cpsid i } 8001576: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001578: e7fe b.n 8001578 ... 0800157c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800157c: b480 push {r7} 800157e: b085 sub sp, #20 8001580: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001582: 4b15 ldr r3, [pc, #84] ; (80015d8 ) 8001584: 699b ldr r3, [r3, #24] 8001586: 4a14 ldr r2, [pc, #80] ; (80015d8 ) 8001588: f043 0301 orr.w r3, r3, #1 800158c: 6193 str r3, [r2, #24] 800158e: 4b12 ldr r3, [pc, #72] ; (80015d8 ) 8001590: 699b ldr r3, [r3, #24] 8001592: f003 0301 and.w r3, r3, #1 8001596: 60bb str r3, [r7, #8] 8001598: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800159a: 4b0f ldr r3, [pc, #60] ; (80015d8 ) 800159c: 69db ldr r3, [r3, #28] 800159e: 4a0e ldr r2, [pc, #56] ; (80015d8 ) 80015a0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80015a4: 61d3 str r3, [r2, #28] 80015a6: 4b0c ldr r3, [pc, #48] ; (80015d8 ) 80015a8: 69db ldr r3, [r3, #28] 80015aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80015ae: 607b str r3, [r7, #4] 80015b0: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 80015b2: 4b0a ldr r3, [pc, #40] ; (80015dc ) 80015b4: 685b ldr r3, [r3, #4] 80015b6: 60fb str r3, [r7, #12] 80015b8: 68fb ldr r3, [r7, #12] 80015ba: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80015be: 60fb str r3, [r7, #12] 80015c0: 68fb ldr r3, [r7, #12] 80015c2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 80015c6: 60fb str r3, [r7, #12] 80015c8: 4a04 ldr r2, [pc, #16] ; (80015dc ) 80015ca: 68fb ldr r3, [r7, #12] 80015cc: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80015ce: bf00 nop 80015d0: 3714 adds r7, #20 80015d2: 46bd mov sp, r7 80015d4: bc80 pop {r7} 80015d6: 4770 bx lr 80015d8: 40021000 .word 0x40021000 80015dc: 40010000 .word 0x40010000 080015e0 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 80015e0: b580 push {r7, lr} 80015e2: b088 sub sp, #32 80015e4: af00 add r7, sp, #0 80015e6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80015e8: f107 0310 add.w r3, r7, #16 80015ec: 2200 movs r2, #0 80015ee: 601a str r2, [r3, #0] 80015f0: 605a str r2, [r3, #4] 80015f2: 609a str r2, [r3, #8] 80015f4: 60da str r2, [r3, #12] if(hi2c->Instance==I2C2) 80015f6: 687b ldr r3, [r7, #4] 80015f8: 681b ldr r3, [r3, #0] 80015fa: 4a16 ldr r2, [pc, #88] ; (8001654 ) 80015fc: 4293 cmp r3, r2 80015fe: d124 bne.n 800164a { /* USER CODE BEGIN I2C2_MspInit 0 */ /* USER CODE END I2C2_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8001600: 4b15 ldr r3, [pc, #84] ; (8001658 ) 8001602: 699b ldr r3, [r3, #24] 8001604: 4a14 ldr r2, [pc, #80] ; (8001658 ) 8001606: f043 0308 orr.w r3, r3, #8 800160a: 6193 str r3, [r2, #24] 800160c: 4b12 ldr r3, [pc, #72] ; (8001658 ) 800160e: 699b ldr r3, [r3, #24] 8001610: f003 0308 and.w r3, r3, #8 8001614: 60fb str r3, [r7, #12] 8001616: 68fb ldr r3, [r7, #12] /**I2C2 GPIO Configuration PB10 ------> I2C2_SCL PB11 ------> I2C2_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8001618: f44f 6340 mov.w r3, #3072 ; 0xc00 800161c: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800161e: 2312 movs r3, #18 8001620: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001622: 2303 movs r3, #3 8001624: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001626: f107 0310 add.w r3, r7, #16 800162a: 4619 mov r1, r3 800162c: 480b ldr r0, [pc, #44] ; (800165c ) 800162e: f000 faf3 bl 8001c18 /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); 8001632: 4b09 ldr r3, [pc, #36] ; (8001658 ) 8001634: 69db ldr r3, [r3, #28] 8001636: 4a08 ldr r2, [pc, #32] ; (8001658 ) 8001638: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 800163c: 61d3 str r3, [r2, #28] 800163e: 4b06 ldr r3, [pc, #24] ; (8001658 ) 8001640: 69db ldr r3, [r3, #28] 8001642: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8001646: 60bb str r3, [r7, #8] 8001648: 68bb ldr r3, [r7, #8] /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ } } 800164a: bf00 nop 800164c: 3720 adds r7, #32 800164e: 46bd mov sp, r7 8001650: bd80 pop {r7, pc} 8001652: bf00 nop 8001654: 40005800 .word 0x40005800 8001658: 40021000 .word 0x40021000 800165c: 40010c00 .word 0x40010c00 08001660 : } static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 8001660: b580 push {r7, lr} 8001662: b086 sub sp, #24 8001664: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 8001666: f107 0308 add.w r3, r7, #8 800166a: 2200 movs r2, #0 800166c: 601a str r2, [r3, #0] 800166e: 605a str r2, [r3, #4] 8001670: 609a str r2, [r3, #8] 8001672: 60da str r2, [r3, #12] if (FSMC_Initialized) { 8001674: 4b1f ldr r3, [pc, #124] ; (80016f4 ) 8001676: 681b ldr r3, [r3, #0] 8001678: 2b00 cmp r3, #0 800167a: d136 bne.n 80016ea return; } FSMC_Initialized = 1; 800167c: 4b1d ldr r3, [pc, #116] ; (80016f4 ) 800167e: 2201 movs r2, #1 8001680: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 8001682: 4b1d ldr r3, [pc, #116] ; (80016f8 ) 8001684: 695b ldr r3, [r3, #20] 8001686: 4a1c ldr r2, [pc, #112] ; (80016f8 ) 8001688: f443 7380 orr.w r3, r3, #256 ; 0x100 800168c: 6153 str r3, [r2, #20] 800168e: 4b1a ldr r3, [pc, #104] ; (80016f8 ) 8001690: 695b ldr r3, [r3, #20] 8001692: f403 7380 and.w r3, r3, #256 ; 0x100 8001696: 607b str r3, [r7, #4] 8001698: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 800169a: f241 0301 movw r3, #4097 ; 0x1001 800169e: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016a0: 2302 movs r3, #2 80016a2: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80016a4: 2303 movs r3, #3 80016a6: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 80016a8: f107 0308 add.w r3, r7, #8 80016ac: 4619 mov r1, r3 80016ae: 4813 ldr r0, [pc, #76] ; (80016fc ) 80016b0: f000 fab2 bl 8001c18 GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 80016b4: f64f 7380 movw r3, #65408 ; 0xff80 80016b8: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016ba: 2302 movs r3, #2 80016bc: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80016be: 2303 movs r3, #3 80016c0: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80016c2: f107 0308 add.w r3, r7, #8 80016c6: 4619 mov r1, r3 80016c8: 480d ldr r0, [pc, #52] ; (8001700 ) 80016ca: f000 faa5 bl 8001c18 GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 80016ce: f24c 7333 movw r3, #50995 ; 0xc733 80016d2: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016d4: 2302 movs r3, #2 80016d6: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80016d8: 2303 movs r3, #3 80016da: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016dc: f107 0308 add.w r3, r7, #8 80016e0: 4619 mov r1, r3 80016e2: 4808 ldr r0, [pc, #32] ; (8001704 ) 80016e4: f000 fa98 bl 8001c18 80016e8: e000 b.n 80016ec return; 80016ea: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 80016ec: 3718 adds r7, #24 80016ee: 46bd mov sp, r7 80016f0: bd80 pop {r7, pc} 80016f2: bf00 nop 80016f4: 200001fc .word 0x200001fc 80016f8: 40021000 .word 0x40021000 80016fc: 40012000 .word 0x40012000 8001700: 40011800 .word 0x40011800 8001704: 40011400 .word 0x40011400 08001708 : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 8001708: b580 push {r7, lr} 800170a: b082 sub sp, #8 800170c: af00 add r7, sp, #0 800170e: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 8001710: f7ff ffa6 bl 8001660 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 8001714: bf00 nop 8001716: 3708 adds r7, #8 8001718: 46bd mov sp, r7 800171a: bd80 pop {r7, pc} 0800171c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800171c: b480 push {r7} 800171e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001720: e7fe b.n 8001720 08001722 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001722: b480 push {r7} 8001724: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001726: e7fe b.n 8001726 08001728 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001728: b480 push {r7} 800172a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800172c: e7fe b.n 800172c 0800172e : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800172e: b480 push {r7} 8001730: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001732: e7fe b.n 8001732 08001734 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001734: b480 push {r7} 8001736: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001738: e7fe b.n 8001738 0800173a : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800173a: b480 push {r7} 800173c: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800173e: bf00 nop 8001740: 46bd mov sp, r7 8001742: bc80 pop {r7} 8001744: 4770 bx lr 08001746 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001746: b480 push {r7} 8001748: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800174a: bf00 nop 800174c: 46bd mov sp, r7 800174e: bc80 pop {r7} 8001750: 4770 bx lr 08001752 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001752: b480 push {r7} 8001754: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001756: bf00 nop 8001758: 46bd mov sp, r7 800175a: bc80 pop {r7} 800175c: 4770 bx lr 0800175e : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800175e: b580 push {r7, lr} 8001760: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001762: f000 f935 bl 80019d0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001766: bf00 nop 8001768: bd80 pop {r7, pc} 0800176a <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800176a: b480 push {r7} 800176c: af00 add r7, sp, #0 return 1; 800176e: 2301 movs r3, #1 } 8001770: 4618 mov r0, r3 8001772: 46bd mov sp, r7 8001774: bc80 pop {r7} 8001776: 4770 bx lr 08001778 <_kill>: int _kill(int pid, int sig) { 8001778: b580 push {r7, lr} 800177a: b082 sub sp, #8 800177c: af00 add r7, sp, #0 800177e: 6078 str r0, [r7, #4] 8001780: 6039 str r1, [r7, #0] errno = EINVAL; 8001782: f005 f943 bl 8006a0c <__errno> 8001786: 4603 mov r3, r0 8001788: 2216 movs r2, #22 800178a: 601a str r2, [r3, #0] return -1; 800178c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001790: 4618 mov r0, r3 8001792: 3708 adds r7, #8 8001794: 46bd mov sp, r7 8001796: bd80 pop {r7, pc} 08001798 <_exit>: void _exit (int status) { 8001798: b580 push {r7, lr} 800179a: b082 sub sp, #8 800179c: af00 add r7, sp, #0 800179e: 6078 str r0, [r7, #4] _kill(status, -1); 80017a0: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80017a4: 6878 ldr r0, [r7, #4] 80017a6: f7ff ffe7 bl 8001778 <_kill> while (1) {} /* Make sure we hang here */ 80017aa: e7fe b.n 80017aa <_exit+0x12> 080017ac <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80017ac: b580 push {r7, lr} 80017ae: b086 sub sp, #24 80017b0: af00 add r7, sp, #0 80017b2: 60f8 str r0, [r7, #12] 80017b4: 60b9 str r1, [r7, #8] 80017b6: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80017b8: 2300 movs r3, #0 80017ba: 617b str r3, [r7, #20] 80017bc: e00a b.n 80017d4 <_read+0x28> { *ptr++ = __io_getchar(); 80017be: f3af 8000 nop.w 80017c2: 4601 mov r1, r0 80017c4: 68bb ldr r3, [r7, #8] 80017c6: 1c5a adds r2, r3, #1 80017c8: 60ba str r2, [r7, #8] 80017ca: b2ca uxtb r2, r1 80017cc: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80017ce: 697b ldr r3, [r7, #20] 80017d0: 3301 adds r3, #1 80017d2: 617b str r3, [r7, #20] 80017d4: 697a ldr r2, [r7, #20] 80017d6: 687b ldr r3, [r7, #4] 80017d8: 429a cmp r2, r3 80017da: dbf0 blt.n 80017be <_read+0x12> } return len; 80017dc: 687b ldr r3, [r7, #4] } 80017de: 4618 mov r0, r3 80017e0: 3718 adds r7, #24 80017e2: 46bd mov sp, r7 80017e4: bd80 pop {r7, pc} 080017e6 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 80017e6: b580 push {r7, lr} 80017e8: b086 sub sp, #24 80017ea: af00 add r7, sp, #0 80017ec: 60f8 str r0, [r7, #12] 80017ee: 60b9 str r1, [r7, #8] 80017f0: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80017f2: 2300 movs r3, #0 80017f4: 617b str r3, [r7, #20] 80017f6: e009 b.n 800180c <_write+0x26> { __io_putchar(*ptr++); 80017f8: 68bb ldr r3, [r7, #8] 80017fa: 1c5a adds r2, r3, #1 80017fc: 60ba str r2, [r7, #8] 80017fe: 781b ldrb r3, [r3, #0] 8001800: 4618 mov r0, r3 8001802: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 8001806: 697b ldr r3, [r7, #20] 8001808: 3301 adds r3, #1 800180a: 617b str r3, [r7, #20] 800180c: 697a ldr r2, [r7, #20] 800180e: 687b ldr r3, [r7, #4] 8001810: 429a cmp r2, r3 8001812: dbf1 blt.n 80017f8 <_write+0x12> } return len; 8001814: 687b ldr r3, [r7, #4] } 8001816: 4618 mov r0, r3 8001818: 3718 adds r7, #24 800181a: 46bd mov sp, r7 800181c: bd80 pop {r7, pc} 0800181e <_close>: int _close(int file) { 800181e: b480 push {r7} 8001820: b083 sub sp, #12 8001822: af00 add r7, sp, #0 8001824: 6078 str r0, [r7, #4] return -1; 8001826: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 800182a: 4618 mov r0, r3 800182c: 370c adds r7, #12 800182e: 46bd mov sp, r7 8001830: bc80 pop {r7} 8001832: 4770 bx lr 08001834 <_fstat>: int _fstat(int file, struct stat *st) { 8001834: b480 push {r7} 8001836: b083 sub sp, #12 8001838: af00 add r7, sp, #0 800183a: 6078 str r0, [r7, #4] 800183c: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 800183e: 683b ldr r3, [r7, #0] 8001840: f44f 5200 mov.w r2, #8192 ; 0x2000 8001844: 605a str r2, [r3, #4] return 0; 8001846: 2300 movs r3, #0 } 8001848: 4618 mov r0, r3 800184a: 370c adds r7, #12 800184c: 46bd mov sp, r7 800184e: bc80 pop {r7} 8001850: 4770 bx lr 08001852 <_isatty>: int _isatty(int file) { 8001852: b480 push {r7} 8001854: b083 sub sp, #12 8001856: af00 add r7, sp, #0 8001858: 6078 str r0, [r7, #4] return 1; 800185a: 2301 movs r3, #1 } 800185c: 4618 mov r0, r3 800185e: 370c adds r7, #12 8001860: 46bd mov sp, r7 8001862: bc80 pop {r7} 8001864: 4770 bx lr 08001866 <_lseek>: int _lseek(int file, int ptr, int dir) { 8001866: b480 push {r7} 8001868: b085 sub sp, #20 800186a: af00 add r7, sp, #0 800186c: 60f8 str r0, [r7, #12] 800186e: 60b9 str r1, [r7, #8] 8001870: 607a str r2, [r7, #4] return 0; 8001872: 2300 movs r3, #0 } 8001874: 4618 mov r0, r3 8001876: 3714 adds r7, #20 8001878: 46bd mov sp, r7 800187a: bc80 pop {r7} 800187c: 4770 bx lr ... 08001880 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001880: b580 push {r7, lr} 8001882: b086 sub sp, #24 8001884: af00 add r7, sp, #0 8001886: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8001888: 4a14 ldr r2, [pc, #80] ; (80018dc <_sbrk+0x5c>) 800188a: 4b15 ldr r3, [pc, #84] ; (80018e0 <_sbrk+0x60>) 800188c: 1ad3 subs r3, r2, r3 800188e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001890: 697b ldr r3, [r7, #20] 8001892: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001894: 4b13 ldr r3, [pc, #76] ; (80018e4 <_sbrk+0x64>) 8001896: 681b ldr r3, [r3, #0] 8001898: 2b00 cmp r3, #0 800189a: d102 bne.n 80018a2 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800189c: 4b11 ldr r3, [pc, #68] ; (80018e4 <_sbrk+0x64>) 800189e: 4a12 ldr r2, [pc, #72] ; (80018e8 <_sbrk+0x68>) 80018a0: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80018a2: 4b10 ldr r3, [pc, #64] ; (80018e4 <_sbrk+0x64>) 80018a4: 681a ldr r2, [r3, #0] 80018a6: 687b ldr r3, [r7, #4] 80018a8: 4413 add r3, r2 80018aa: 693a ldr r2, [r7, #16] 80018ac: 429a cmp r2, r3 80018ae: d207 bcs.n 80018c0 <_sbrk+0x40> { errno = ENOMEM; 80018b0: f005 f8ac bl 8006a0c <__errno> 80018b4: 4603 mov r3, r0 80018b6: 220c movs r2, #12 80018b8: 601a str r2, [r3, #0] return (void *)-1; 80018ba: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 80018be: e009 b.n 80018d4 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80018c0: 4b08 ldr r3, [pc, #32] ; (80018e4 <_sbrk+0x64>) 80018c2: 681b ldr r3, [r3, #0] 80018c4: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80018c6: 4b07 ldr r3, [pc, #28] ; (80018e4 <_sbrk+0x64>) 80018c8: 681a ldr r2, [r3, #0] 80018ca: 687b ldr r3, [r7, #4] 80018cc: 4413 add r3, r2 80018ce: 4a05 ldr r2, [pc, #20] ; (80018e4 <_sbrk+0x64>) 80018d0: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80018d2: 68fb ldr r3, [r7, #12] } 80018d4: 4618 mov r0, r3 80018d6: 3718 adds r7, #24 80018d8: 46bd mov sp, r7 80018da: bd80 pop {r7, pc} 80018dc: 20010000 .word 0x20010000 80018e0: 00000800 .word 0x00000800 80018e4: 20000200 .word 0x20000200 80018e8: 20002468 .word 0x20002468 080018ec : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80018ec: b480 push {r7} 80018ee: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80018f0: bf00 nop 80018f2: 46bd mov sp, r7 80018f4: bc80 pop {r7} 80018f6: 4770 bx lr 080018f8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80018f8: 480c ldr r0, [pc, #48] ; (800192c ) ldr r1, =_edata 80018fa: 490d ldr r1, [pc, #52] ; (8001930 ) ldr r2, =_sidata 80018fc: 4a0d ldr r2, [pc, #52] ; (8001934 ) movs r3, #0 80018fe: 2300 movs r3, #0 b LoopCopyDataInit 8001900: e002 b.n 8001908 08001902 : CopyDataInit: ldr r4, [r2, r3] 8001902: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001904: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001906: 3304 adds r3, #4 08001908 : LoopCopyDataInit: adds r4, r0, r3 8001908: 18c4 adds r4, r0, r3 cmp r4, r1 800190a: 428c cmp r4, r1 bcc CopyDataInit 800190c: d3f9 bcc.n 8001902 /* Zero fill the bss segment. */ ldr r2, =_sbss 800190e: 4a0a ldr r2, [pc, #40] ; (8001938 ) ldr r4, =_ebss 8001910: 4c0a ldr r4, [pc, #40] ; (800193c ) movs r3, #0 8001912: 2300 movs r3, #0 b LoopFillZerobss 8001914: e001 b.n 800191a 08001916 : FillZerobss: str r3, [r2] 8001916: 6013 str r3, [r2, #0] adds r2, r2, #4 8001918: 3204 adds r2, #4 0800191a : LoopFillZerobss: cmp r2, r4 800191a: 42a2 cmp r2, r4 bcc FillZerobss 800191c: d3fb bcc.n 8001916 /* Call the clock system intitialization function.*/ bl SystemInit 800191e: f7ff ffe5 bl 80018ec /* Call static constructors */ bl __libc_init_array 8001922: f005 f879 bl 8006a18 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001926: f7ff fc7b bl 8001220

bx lr 800192a: 4770 bx lr ldr r0, =_sdata 800192c: 20000000 .word 0x20000000 ldr r1, =_edata 8001930: 200001e0 .word 0x200001e0 ldr r2, =_sidata 8001934: 0800ab54 .word 0x0800ab54 ldr r2, =_sbss 8001938: 200001e0 .word 0x200001e0 ldr r4, =_ebss 800193c: 20002464 .word 0x20002464 08001940 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001940: e7fe b.n 8001940 ... 08001944 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001944: b580 push {r7, lr} 8001946: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001948: 4b08 ldr r3, [pc, #32] ; (800196c ) 800194a: 681b ldr r3, [r3, #0] 800194c: 4a07 ldr r2, [pc, #28] ; (800196c ) 800194e: f043 0310 orr.w r3, r3, #16 8001952: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001954: 2003 movs r0, #3 8001956: f000 f92b bl 8001bb0 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800195a: 200f movs r0, #15 800195c: f000 f808 bl 8001970 /* Init the low level hardware */ HAL_MspInit(); 8001960: f7ff fe0c bl 800157c /* Return function status */ return HAL_OK; 8001964: 2300 movs r3, #0 } 8001966: 4618 mov r0, r3 8001968: bd80 pop {r7, pc} 800196a: bf00 nop 800196c: 40022000 .word 0x40022000 08001970 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001970: b580 push {r7, lr} 8001972: b082 sub sp, #8 8001974: af00 add r7, sp, #0 8001976: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001978: 4b12 ldr r3, [pc, #72] ; (80019c4 ) 800197a: 681a ldr r2, [r3, #0] 800197c: 4b12 ldr r3, [pc, #72] ; (80019c8 ) 800197e: 781b ldrb r3, [r3, #0] 8001980: 4619 mov r1, r3 8001982: f44f 737a mov.w r3, #1000 ; 0x3e8 8001986: fbb3 f3f1 udiv r3, r3, r1 800198a: fbb2 f3f3 udiv r3, r2, r3 800198e: 4618 mov r0, r3 8001990: f000 f935 bl 8001bfe 8001994: 4603 mov r3, r0 8001996: 2b00 cmp r3, #0 8001998: d001 beq.n 800199e { return HAL_ERROR; 800199a: 2301 movs r3, #1 800199c: e00e b.n 80019bc } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800199e: 687b ldr r3, [r7, #4] 80019a0: 2b0f cmp r3, #15 80019a2: d80a bhi.n 80019ba { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80019a4: 2200 movs r2, #0 80019a6: 6879 ldr r1, [r7, #4] 80019a8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80019ac: f000 f90b bl 8001bc6 uwTickPrio = TickPriority; 80019b0: 4a06 ldr r2, [pc, #24] ; (80019cc ) 80019b2: 687b ldr r3, [r7, #4] 80019b4: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80019b6: 2300 movs r3, #0 80019b8: e000 b.n 80019bc return HAL_ERROR; 80019ba: 2301 movs r3, #1 } 80019bc: 4618 mov r0, r3 80019be: 3708 adds r7, #8 80019c0: 46bd mov sp, r7 80019c2: bd80 pop {r7, pc} 80019c4: 20000000 .word 0x20000000 80019c8: 20000008 .word 0x20000008 80019cc: 20000004 .word 0x20000004 080019d0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80019d0: b480 push {r7} 80019d2: af00 add r7, sp, #0 uwTick += uwTickFreq; 80019d4: 4b05 ldr r3, [pc, #20] ; (80019ec ) 80019d6: 781b ldrb r3, [r3, #0] 80019d8: 461a mov r2, r3 80019da: 4b05 ldr r3, [pc, #20] ; (80019f0 ) 80019dc: 681b ldr r3, [r3, #0] 80019de: 4413 add r3, r2 80019e0: 4a03 ldr r2, [pc, #12] ; (80019f0 ) 80019e2: 6013 str r3, [r2, #0] } 80019e4: bf00 nop 80019e6: 46bd mov sp, r7 80019e8: bc80 pop {r7} 80019ea: 4770 bx lr 80019ec: 20000008 .word 0x20000008 80019f0: 200002b4 .word 0x200002b4 080019f4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80019f4: b480 push {r7} 80019f6: af00 add r7, sp, #0 return uwTick; 80019f8: 4b02 ldr r3, [pc, #8] ; (8001a04 ) 80019fa: 681b ldr r3, [r3, #0] } 80019fc: 4618 mov r0, r3 80019fe: 46bd mov sp, r7 8001a00: bc80 pop {r7} 8001a02: 4770 bx lr 8001a04: 200002b4 .word 0x200002b4 08001a08 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001a08: b580 push {r7, lr} 8001a0a: b084 sub sp, #16 8001a0c: af00 add r7, sp, #0 8001a0e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001a10: f7ff fff0 bl 80019f4 8001a14: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001a16: 687b ldr r3, [r7, #4] 8001a18: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001a1a: 68fb ldr r3, [r7, #12] 8001a1c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8001a20: d005 beq.n 8001a2e { wait += (uint32_t)(uwTickFreq); 8001a22: 4b0a ldr r3, [pc, #40] ; (8001a4c ) 8001a24: 781b ldrb r3, [r3, #0] 8001a26: 461a mov r2, r3 8001a28: 68fb ldr r3, [r7, #12] 8001a2a: 4413 add r3, r2 8001a2c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001a2e: bf00 nop 8001a30: f7ff ffe0 bl 80019f4 8001a34: 4602 mov r2, r0 8001a36: 68bb ldr r3, [r7, #8] 8001a38: 1ad3 subs r3, r2, r3 8001a3a: 68fa ldr r2, [r7, #12] 8001a3c: 429a cmp r2, r3 8001a3e: d8f7 bhi.n 8001a30 { } } 8001a40: bf00 nop 8001a42: bf00 nop 8001a44: 3710 adds r7, #16 8001a46: 46bd mov sp, r7 8001a48: bd80 pop {r7, pc} 8001a4a: bf00 nop 8001a4c: 20000008 .word 0x20000008 08001a50 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a50: b480 push {r7} 8001a52: b085 sub sp, #20 8001a54: af00 add r7, sp, #0 8001a56: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001a58: 687b ldr r3, [r7, #4] 8001a5a: f003 0307 and.w r3, r3, #7 8001a5e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001a60: 4b0c ldr r3, [pc, #48] ; (8001a94 <__NVIC_SetPriorityGrouping+0x44>) 8001a62: 68db ldr r3, [r3, #12] 8001a64: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001a66: 68ba ldr r2, [r7, #8] 8001a68: f64f 03ff movw r3, #63743 ; 0xf8ff 8001a6c: 4013 ands r3, r2 8001a6e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001a70: 68fb ldr r3, [r7, #12] 8001a72: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001a74: 68bb ldr r3, [r7, #8] 8001a76: 4313 orrs r3, r2 reg_value = (reg_value | 8001a78: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001a7c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001a80: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001a82: 4a04 ldr r2, [pc, #16] ; (8001a94 <__NVIC_SetPriorityGrouping+0x44>) 8001a84: 68bb ldr r3, [r7, #8] 8001a86: 60d3 str r3, [r2, #12] } 8001a88: bf00 nop 8001a8a: 3714 adds r7, #20 8001a8c: 46bd mov sp, r7 8001a8e: bc80 pop {r7} 8001a90: 4770 bx lr 8001a92: bf00 nop 8001a94: e000ed00 .word 0xe000ed00 08001a98 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001a98: b480 push {r7} 8001a9a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001a9c: 4b04 ldr r3, [pc, #16] ; (8001ab0 <__NVIC_GetPriorityGrouping+0x18>) 8001a9e: 68db ldr r3, [r3, #12] 8001aa0: 0a1b lsrs r3, r3, #8 8001aa2: f003 0307 and.w r3, r3, #7 } 8001aa6: 4618 mov r0, r3 8001aa8: 46bd mov sp, r7 8001aaa: bc80 pop {r7} 8001aac: 4770 bx lr 8001aae: bf00 nop 8001ab0: e000ed00 .word 0xe000ed00 08001ab4 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001ab4: b480 push {r7} 8001ab6: b083 sub sp, #12 8001ab8: af00 add r7, sp, #0 8001aba: 4603 mov r3, r0 8001abc: 6039 str r1, [r7, #0] 8001abe: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001ac0: f997 3007 ldrsb.w r3, [r7, #7] 8001ac4: 2b00 cmp r3, #0 8001ac6: db0a blt.n 8001ade <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ac8: 683b ldr r3, [r7, #0] 8001aca: b2da uxtb r2, r3 8001acc: 490c ldr r1, [pc, #48] ; (8001b00 <__NVIC_SetPriority+0x4c>) 8001ace: f997 3007 ldrsb.w r3, [r7, #7] 8001ad2: 0112 lsls r2, r2, #4 8001ad4: b2d2 uxtb r2, r2 8001ad6: 440b add r3, r1 8001ad8: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001adc: e00a b.n 8001af4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ade: 683b ldr r3, [r7, #0] 8001ae0: b2da uxtb r2, r3 8001ae2: 4908 ldr r1, [pc, #32] ; (8001b04 <__NVIC_SetPriority+0x50>) 8001ae4: 79fb ldrb r3, [r7, #7] 8001ae6: f003 030f and.w r3, r3, #15 8001aea: 3b04 subs r3, #4 8001aec: 0112 lsls r2, r2, #4 8001aee: b2d2 uxtb r2, r2 8001af0: 440b add r3, r1 8001af2: 761a strb r2, [r3, #24] } 8001af4: bf00 nop 8001af6: 370c adds r7, #12 8001af8: 46bd mov sp, r7 8001afa: bc80 pop {r7} 8001afc: 4770 bx lr 8001afe: bf00 nop 8001b00: e000e100 .word 0xe000e100 8001b04: e000ed00 .word 0xe000ed00 08001b08 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001b08: b480 push {r7} 8001b0a: b089 sub sp, #36 ; 0x24 8001b0c: af00 add r7, sp, #0 8001b0e: 60f8 str r0, [r7, #12] 8001b10: 60b9 str r1, [r7, #8] 8001b12: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001b14: 68fb ldr r3, [r7, #12] 8001b16: f003 0307 and.w r3, r3, #7 8001b1a: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001b1c: 69fb ldr r3, [r7, #28] 8001b1e: f1c3 0307 rsb r3, r3, #7 8001b22: 2b04 cmp r3, #4 8001b24: bf28 it cs 8001b26: 2304 movcs r3, #4 8001b28: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001b2a: 69fb ldr r3, [r7, #28] 8001b2c: 3304 adds r3, #4 8001b2e: 2b06 cmp r3, #6 8001b30: d902 bls.n 8001b38 8001b32: 69fb ldr r3, [r7, #28] 8001b34: 3b03 subs r3, #3 8001b36: e000 b.n 8001b3a 8001b38: 2300 movs r3, #0 8001b3a: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b3c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8001b40: 69bb ldr r3, [r7, #24] 8001b42: fa02 f303 lsl.w r3, r2, r3 8001b46: 43da mvns r2, r3 8001b48: 68bb ldr r3, [r7, #8] 8001b4a: 401a ands r2, r3 8001b4c: 697b ldr r3, [r7, #20] 8001b4e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001b50: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001b54: 697b ldr r3, [r7, #20] 8001b56: fa01 f303 lsl.w r3, r1, r3 8001b5a: 43d9 mvns r1, r3 8001b5c: 687b ldr r3, [r7, #4] 8001b5e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b60: 4313 orrs r3, r2 ); } 8001b62: 4618 mov r0, r3 8001b64: 3724 adds r7, #36 ; 0x24 8001b66: 46bd mov sp, r7 8001b68: bc80 pop {r7} 8001b6a: 4770 bx lr 08001b6c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001b6c: b580 push {r7, lr} 8001b6e: b082 sub sp, #8 8001b70: af00 add r7, sp, #0 8001b72: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001b74: 687b ldr r3, [r7, #4] 8001b76: 3b01 subs r3, #1 8001b78: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001b7c: d301 bcc.n 8001b82 { return (1UL); /* Reload value impossible */ 8001b7e: 2301 movs r3, #1 8001b80: e00f b.n 8001ba2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001b82: 4a0a ldr r2, [pc, #40] ; (8001bac ) 8001b84: 687b ldr r3, [r7, #4] 8001b86: 3b01 subs r3, #1 8001b88: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001b8a: 210f movs r1, #15 8001b8c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001b90: f7ff ff90 bl 8001ab4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001b94: 4b05 ldr r3, [pc, #20] ; (8001bac ) 8001b96: 2200 movs r2, #0 8001b98: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001b9a: 4b04 ldr r3, [pc, #16] ; (8001bac ) 8001b9c: 2207 movs r2, #7 8001b9e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001ba0: 2300 movs r3, #0 } 8001ba2: 4618 mov r0, r3 8001ba4: 3708 adds r7, #8 8001ba6: 46bd mov sp, r7 8001ba8: bd80 pop {r7, pc} 8001baa: bf00 nop 8001bac: e000e010 .word 0xe000e010 08001bb0 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001bb0: b580 push {r7, lr} 8001bb2: b082 sub sp, #8 8001bb4: af00 add r7, sp, #0 8001bb6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001bb8: 6878 ldr r0, [r7, #4] 8001bba: f7ff ff49 bl 8001a50 <__NVIC_SetPriorityGrouping> } 8001bbe: bf00 nop 8001bc0: 3708 adds r7, #8 8001bc2: 46bd mov sp, r7 8001bc4: bd80 pop {r7, pc} 08001bc6 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001bc6: b580 push {r7, lr} 8001bc8: b086 sub sp, #24 8001bca: af00 add r7, sp, #0 8001bcc: 4603 mov r3, r0 8001bce: 60b9 str r1, [r7, #8] 8001bd0: 607a str r2, [r7, #4] 8001bd2: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001bd4: 2300 movs r3, #0 8001bd6: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001bd8: f7ff ff5e bl 8001a98 <__NVIC_GetPriorityGrouping> 8001bdc: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001bde: 687a ldr r2, [r7, #4] 8001be0: 68b9 ldr r1, [r7, #8] 8001be2: 6978 ldr r0, [r7, #20] 8001be4: f7ff ff90 bl 8001b08 8001be8: 4602 mov r2, r0 8001bea: f997 300f ldrsb.w r3, [r7, #15] 8001bee: 4611 mov r1, r2 8001bf0: 4618 mov r0, r3 8001bf2: f7ff ff5f bl 8001ab4 <__NVIC_SetPriority> } 8001bf6: bf00 nop 8001bf8: 3718 adds r7, #24 8001bfa: 46bd mov sp, r7 8001bfc: bd80 pop {r7, pc} 08001bfe : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001bfe: b580 push {r7, lr} 8001c00: b082 sub sp, #8 8001c02: af00 add r7, sp, #0 8001c04: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001c06: 6878 ldr r0, [r7, #4] 8001c08: f7ff ffb0 bl 8001b6c 8001c0c: 4603 mov r3, r0 } 8001c0e: 4618 mov r0, r3 8001c10: 3708 adds r7, #8 8001c12: 46bd mov sp, r7 8001c14: bd80 pop {r7, pc} ... 08001c18 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001c18: b480 push {r7} 8001c1a: b08b sub sp, #44 ; 0x2c 8001c1c: af00 add r7, sp, #0 8001c1e: 6078 str r0, [r7, #4] 8001c20: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8001c22: 2300 movs r3, #0 8001c24: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8001c26: 2300 movs r3, #0 8001c28: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8001c2a: e179 b.n 8001f20 { /* Get the IO position */ ioposition = (0x01uL << position); 8001c2c: 2201 movs r2, #1 8001c2e: 6a7b ldr r3, [r7, #36] ; 0x24 8001c30: fa02 f303 lsl.w r3, r2, r3 8001c34: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001c36: 683b ldr r3, [r7, #0] 8001c38: 681b ldr r3, [r3, #0] 8001c3a: 69fa ldr r2, [r7, #28] 8001c3c: 4013 ands r3, r2 8001c3e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8001c40: 69ba ldr r2, [r7, #24] 8001c42: 69fb ldr r3, [r7, #28] 8001c44: 429a cmp r2, r3 8001c46: f040 8168 bne.w 8001f1a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8001c4a: 683b ldr r3, [r7, #0] 8001c4c: 685b ldr r3, [r3, #4] 8001c4e: 4aa0 ldr r2, [pc, #640] ; (8001ed0 ) 8001c50: 4293 cmp r3, r2 8001c52: d05e beq.n 8001d12 8001c54: 4a9e ldr r2, [pc, #632] ; (8001ed0 ) 8001c56: 4293 cmp r3, r2 8001c58: d875 bhi.n 8001d46 8001c5a: 4a9e ldr r2, [pc, #632] ; (8001ed4 ) 8001c5c: 4293 cmp r3, r2 8001c5e: d058 beq.n 8001d12 8001c60: 4a9c ldr r2, [pc, #624] ; (8001ed4 ) 8001c62: 4293 cmp r3, r2 8001c64: d86f bhi.n 8001d46 8001c66: 4a9c ldr r2, [pc, #624] ; (8001ed8 ) 8001c68: 4293 cmp r3, r2 8001c6a: d052 beq.n 8001d12 8001c6c: 4a9a ldr r2, [pc, #616] ; (8001ed8 ) 8001c6e: 4293 cmp r3, r2 8001c70: d869 bhi.n 8001d46 8001c72: 4a9a ldr r2, [pc, #616] ; (8001edc ) 8001c74: 4293 cmp r3, r2 8001c76: d04c beq.n 8001d12 8001c78: 4a98 ldr r2, [pc, #608] ; (8001edc ) 8001c7a: 4293 cmp r3, r2 8001c7c: d863 bhi.n 8001d46 8001c7e: 4a98 ldr r2, [pc, #608] ; (8001ee0 ) 8001c80: 4293 cmp r3, r2 8001c82: d046 beq.n 8001d12 8001c84: 4a96 ldr r2, [pc, #600] ; (8001ee0 ) 8001c86: 4293 cmp r3, r2 8001c88: d85d bhi.n 8001d46 8001c8a: 2b12 cmp r3, #18 8001c8c: d82a bhi.n 8001ce4 8001c8e: 2b12 cmp r3, #18 8001c90: d859 bhi.n 8001d46 8001c92: a201 add r2, pc, #4 ; (adr r2, 8001c98 ) 8001c94: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001c98: 08001d13 .word 0x08001d13 8001c9c: 08001ced .word 0x08001ced 8001ca0: 08001cff .word 0x08001cff 8001ca4: 08001d41 .word 0x08001d41 8001ca8: 08001d47 .word 0x08001d47 8001cac: 08001d47 .word 0x08001d47 8001cb0: 08001d47 .word 0x08001d47 8001cb4: 08001d47 .word 0x08001d47 8001cb8: 08001d47 .word 0x08001d47 8001cbc: 08001d47 .word 0x08001d47 8001cc0: 08001d47 .word 0x08001d47 8001cc4: 08001d47 .word 0x08001d47 8001cc8: 08001d47 .word 0x08001d47 8001ccc: 08001d47 .word 0x08001d47 8001cd0: 08001d47 .word 0x08001d47 8001cd4: 08001d47 .word 0x08001d47 8001cd8: 08001d47 .word 0x08001d47 8001cdc: 08001cf5 .word 0x08001cf5 8001ce0: 08001d09 .word 0x08001d09 8001ce4: 4a7f ldr r2, [pc, #508] ; (8001ee4 ) 8001ce6: 4293 cmp r3, r2 8001ce8: d013 beq.n 8001d12 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001cea: e02c b.n 8001d46 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001cec: 683b ldr r3, [r7, #0] 8001cee: 68db ldr r3, [r3, #12] 8001cf0: 623b str r3, [r7, #32] break; 8001cf2: e029 b.n 8001d48 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8001cf4: 683b ldr r3, [r7, #0] 8001cf6: 68db ldr r3, [r3, #12] 8001cf8: 3304 adds r3, #4 8001cfa: 623b str r3, [r7, #32] break; 8001cfc: e024 b.n 8001d48 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001cfe: 683b ldr r3, [r7, #0] 8001d00: 68db ldr r3, [r3, #12] 8001d02: 3308 adds r3, #8 8001d04: 623b str r3, [r7, #32] break; 8001d06: e01f b.n 8001d48 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001d08: 683b ldr r3, [r7, #0] 8001d0a: 68db ldr r3, [r3, #12] 8001d0c: 330c adds r3, #12 8001d0e: 623b str r3, [r7, #32] break; 8001d10: e01a b.n 8001d48 if (GPIO_Init->Pull == GPIO_NOPULL) 8001d12: 683b ldr r3, [r7, #0] 8001d14: 689b ldr r3, [r3, #8] 8001d16: 2b00 cmp r3, #0 8001d18: d102 bne.n 8001d20 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001d1a: 2304 movs r3, #4 8001d1c: 623b str r3, [r7, #32] break; 8001d1e: e013 b.n 8001d48 else if (GPIO_Init->Pull == GPIO_PULLUP) 8001d20: 683b ldr r3, [r7, #0] 8001d22: 689b ldr r3, [r3, #8] 8001d24: 2b01 cmp r3, #1 8001d26: d105 bne.n 8001d34 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001d28: 2308 movs r3, #8 8001d2a: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001d2c: 687b ldr r3, [r7, #4] 8001d2e: 69fa ldr r2, [r7, #28] 8001d30: 611a str r2, [r3, #16] break; 8001d32: e009 b.n 8001d48 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001d34: 2308 movs r3, #8 8001d36: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001d38: 687b ldr r3, [r7, #4] 8001d3a: 69fa ldr r2, [r7, #28] 8001d3c: 615a str r2, [r3, #20] break; 8001d3e: e003 b.n 8001d48 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8001d40: 2300 movs r3, #0 8001d42: 623b str r3, [r7, #32] break; 8001d44: e000 b.n 8001d48 break; 8001d46: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001d48: 69bb ldr r3, [r7, #24] 8001d4a: 2bff cmp r3, #255 ; 0xff 8001d4c: d801 bhi.n 8001d52 8001d4e: 687b ldr r3, [r7, #4] 8001d50: e001 b.n 8001d56 8001d52: 687b ldr r3, [r7, #4] 8001d54: 3304 adds r3, #4 8001d56: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001d58: 69bb ldr r3, [r7, #24] 8001d5a: 2bff cmp r3, #255 ; 0xff 8001d5c: d802 bhi.n 8001d64 8001d5e: 6a7b ldr r3, [r7, #36] ; 0x24 8001d60: 009b lsls r3, r3, #2 8001d62: e002 b.n 8001d6a 8001d64: 6a7b ldr r3, [r7, #36] ; 0x24 8001d66: 3b08 subs r3, #8 8001d68: 009b lsls r3, r3, #2 8001d6a: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001d6c: 697b ldr r3, [r7, #20] 8001d6e: 681a ldr r2, [r3, #0] 8001d70: 210f movs r1, #15 8001d72: 693b ldr r3, [r7, #16] 8001d74: fa01 f303 lsl.w r3, r1, r3 8001d78: 43db mvns r3, r3 8001d7a: 401a ands r2, r3 8001d7c: 6a39 ldr r1, [r7, #32] 8001d7e: 693b ldr r3, [r7, #16] 8001d80: fa01 f303 lsl.w r3, r1, r3 8001d84: 431a orrs r2, r3 8001d86: 697b ldr r3, [r7, #20] 8001d88: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001d8a: 683b ldr r3, [r7, #0] 8001d8c: 685b ldr r3, [r3, #4] 8001d8e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001d92: 2b00 cmp r3, #0 8001d94: f000 80c1 beq.w 8001f1a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001d98: 4b53 ldr r3, [pc, #332] ; (8001ee8 ) 8001d9a: 699b ldr r3, [r3, #24] 8001d9c: 4a52 ldr r2, [pc, #328] ; (8001ee8 ) 8001d9e: f043 0301 orr.w r3, r3, #1 8001da2: 6193 str r3, [r2, #24] 8001da4: 4b50 ldr r3, [pc, #320] ; (8001ee8 ) 8001da6: 699b ldr r3, [r3, #24] 8001da8: f003 0301 and.w r3, r3, #1 8001dac: 60bb str r3, [r7, #8] 8001dae: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001db0: 4a4e ldr r2, [pc, #312] ; (8001eec ) 8001db2: 6a7b ldr r3, [r7, #36] ; 0x24 8001db4: 089b lsrs r3, r3, #2 8001db6: 3302 adds r3, #2 8001db8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001dbc: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001dbe: 6a7b ldr r3, [r7, #36] ; 0x24 8001dc0: f003 0303 and.w r3, r3, #3 8001dc4: 009b lsls r3, r3, #2 8001dc6: 220f movs r2, #15 8001dc8: fa02 f303 lsl.w r3, r2, r3 8001dcc: 43db mvns r3, r3 8001dce: 68fa ldr r2, [r7, #12] 8001dd0: 4013 ands r3, r2 8001dd2: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8001dd4: 687b ldr r3, [r7, #4] 8001dd6: 4a46 ldr r2, [pc, #280] ; (8001ef0 ) 8001dd8: 4293 cmp r3, r2 8001dda: d01f beq.n 8001e1c 8001ddc: 687b ldr r3, [r7, #4] 8001dde: 4a45 ldr r2, [pc, #276] ; (8001ef4 ) 8001de0: 4293 cmp r3, r2 8001de2: d019 beq.n 8001e18 8001de4: 687b ldr r3, [r7, #4] 8001de6: 4a44 ldr r2, [pc, #272] ; (8001ef8 ) 8001de8: 4293 cmp r3, r2 8001dea: d013 beq.n 8001e14 8001dec: 687b ldr r3, [r7, #4] 8001dee: 4a43 ldr r2, [pc, #268] ; (8001efc ) 8001df0: 4293 cmp r3, r2 8001df2: d00d beq.n 8001e10 8001df4: 687b ldr r3, [r7, #4] 8001df6: 4a42 ldr r2, [pc, #264] ; (8001f00 ) 8001df8: 4293 cmp r3, r2 8001dfa: d007 beq.n 8001e0c 8001dfc: 687b ldr r3, [r7, #4] 8001dfe: 4a41 ldr r2, [pc, #260] ; (8001f04 ) 8001e00: 4293 cmp r3, r2 8001e02: d101 bne.n 8001e08 8001e04: 2305 movs r3, #5 8001e06: e00a b.n 8001e1e 8001e08: 2306 movs r3, #6 8001e0a: e008 b.n 8001e1e 8001e0c: 2304 movs r3, #4 8001e0e: e006 b.n 8001e1e 8001e10: 2303 movs r3, #3 8001e12: e004 b.n 8001e1e 8001e14: 2302 movs r3, #2 8001e16: e002 b.n 8001e1e 8001e18: 2301 movs r3, #1 8001e1a: e000 b.n 8001e1e 8001e1c: 2300 movs r3, #0 8001e1e: 6a7a ldr r2, [r7, #36] ; 0x24 8001e20: f002 0203 and.w r2, r2, #3 8001e24: 0092 lsls r2, r2, #2 8001e26: 4093 lsls r3, r2 8001e28: 68fa ldr r2, [r7, #12] 8001e2a: 4313 orrs r3, r2 8001e2c: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001e2e: 492f ldr r1, [pc, #188] ; (8001eec ) 8001e30: 6a7b ldr r3, [r7, #36] ; 0x24 8001e32: 089b lsrs r3, r3, #2 8001e34: 3302 adds r3, #2 8001e36: 68fa ldr r2, [r7, #12] 8001e38: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8001e3c: 683b ldr r3, [r7, #0] 8001e3e: 685b ldr r3, [r3, #4] 8001e40: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001e44: 2b00 cmp r3, #0 8001e46: d006 beq.n 8001e56 { SET_BIT(EXTI->IMR, iocurrent); 8001e48: 4b2f ldr r3, [pc, #188] ; (8001f08 ) 8001e4a: 681a ldr r2, [r3, #0] 8001e4c: 492e ldr r1, [pc, #184] ; (8001f08 ) 8001e4e: 69bb ldr r3, [r7, #24] 8001e50: 4313 orrs r3, r2 8001e52: 600b str r3, [r1, #0] 8001e54: e006 b.n 8001e64 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8001e56: 4b2c ldr r3, [pc, #176] ; (8001f08 ) 8001e58: 681a ldr r2, [r3, #0] 8001e5a: 69bb ldr r3, [r7, #24] 8001e5c: 43db mvns r3, r3 8001e5e: 492a ldr r1, [pc, #168] ; (8001f08 ) 8001e60: 4013 ands r3, r2 8001e62: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8001e64: 683b ldr r3, [r7, #0] 8001e66: 685b ldr r3, [r3, #4] 8001e68: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001e6c: 2b00 cmp r3, #0 8001e6e: d006 beq.n 8001e7e { SET_BIT(EXTI->EMR, iocurrent); 8001e70: 4b25 ldr r3, [pc, #148] ; (8001f08 ) 8001e72: 685a ldr r2, [r3, #4] 8001e74: 4924 ldr r1, [pc, #144] ; (8001f08 ) 8001e76: 69bb ldr r3, [r7, #24] 8001e78: 4313 orrs r3, r2 8001e7a: 604b str r3, [r1, #4] 8001e7c: e006 b.n 8001e8c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8001e7e: 4b22 ldr r3, [pc, #136] ; (8001f08 ) 8001e80: 685a ldr r2, [r3, #4] 8001e82: 69bb ldr r3, [r7, #24] 8001e84: 43db mvns r3, r3 8001e86: 4920 ldr r1, [pc, #128] ; (8001f08 ) 8001e88: 4013 ands r3, r2 8001e8a: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001e8c: 683b ldr r3, [r7, #0] 8001e8e: 685b ldr r3, [r3, #4] 8001e90: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001e94: 2b00 cmp r3, #0 8001e96: d006 beq.n 8001ea6 { SET_BIT(EXTI->RTSR, iocurrent); 8001e98: 4b1b ldr r3, [pc, #108] ; (8001f08 ) 8001e9a: 689a ldr r2, [r3, #8] 8001e9c: 491a ldr r1, [pc, #104] ; (8001f08 ) 8001e9e: 69bb ldr r3, [r7, #24] 8001ea0: 4313 orrs r3, r2 8001ea2: 608b str r3, [r1, #8] 8001ea4: e006 b.n 8001eb4 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8001ea6: 4b18 ldr r3, [pc, #96] ; (8001f08 ) 8001ea8: 689a ldr r2, [r3, #8] 8001eaa: 69bb ldr r3, [r7, #24] 8001eac: 43db mvns r3, r3 8001eae: 4916 ldr r1, [pc, #88] ; (8001f08 ) 8001eb0: 4013 ands r3, r2 8001eb2: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8001eb4: 683b ldr r3, [r7, #0] 8001eb6: 685b ldr r3, [r3, #4] 8001eb8: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001ebc: 2b00 cmp r3, #0 8001ebe: d025 beq.n 8001f0c { SET_BIT(EXTI->FTSR, iocurrent); 8001ec0: 4b11 ldr r3, [pc, #68] ; (8001f08 ) 8001ec2: 68da ldr r2, [r3, #12] 8001ec4: 4910 ldr r1, [pc, #64] ; (8001f08 ) 8001ec6: 69bb ldr r3, [r7, #24] 8001ec8: 4313 orrs r3, r2 8001eca: 60cb str r3, [r1, #12] 8001ecc: e025 b.n 8001f1a 8001ece: bf00 nop 8001ed0: 10320000 .word 0x10320000 8001ed4: 10310000 .word 0x10310000 8001ed8: 10220000 .word 0x10220000 8001edc: 10210000 .word 0x10210000 8001ee0: 10120000 .word 0x10120000 8001ee4: 10110000 .word 0x10110000 8001ee8: 40021000 .word 0x40021000 8001eec: 40010000 .word 0x40010000 8001ef0: 40010800 .word 0x40010800 8001ef4: 40010c00 .word 0x40010c00 8001ef8: 40011000 .word 0x40011000 8001efc: 40011400 .word 0x40011400 8001f00: 40011800 .word 0x40011800 8001f04: 40011c00 .word 0x40011c00 8001f08: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001f0c: 4b0b ldr r3, [pc, #44] ; (8001f3c ) 8001f0e: 68da ldr r2, [r3, #12] 8001f10: 69bb ldr r3, [r7, #24] 8001f12: 43db mvns r3, r3 8001f14: 4909 ldr r1, [pc, #36] ; (8001f3c ) 8001f16: 4013 ands r3, r2 8001f18: 60cb str r3, [r1, #12] } } } position++; 8001f1a: 6a7b ldr r3, [r7, #36] ; 0x24 8001f1c: 3301 adds r3, #1 8001f1e: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8001f20: 683b ldr r3, [r7, #0] 8001f22: 681a ldr r2, [r3, #0] 8001f24: 6a7b ldr r3, [r7, #36] ; 0x24 8001f26: fa22 f303 lsr.w r3, r2, r3 8001f2a: 2b00 cmp r3, #0 8001f2c: f47f ae7e bne.w 8001c2c } } 8001f30: bf00 nop 8001f32: bf00 nop 8001f34: 372c adds r7, #44 ; 0x2c 8001f36: 46bd mov sp, r7 8001f38: bc80 pop {r7} 8001f3a: 4770 bx lr 8001f3c: 40010400 .word 0x40010400 08001f40 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001f40: b480 push {r7} 8001f42: b085 sub sp, #20 8001f44: af00 add r7, sp, #0 8001f46: 6078 str r0, [r7, #4] 8001f48: 460b mov r3, r1 8001f4a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001f4c: 687b ldr r3, [r7, #4] 8001f4e: 689a ldr r2, [r3, #8] 8001f50: 887b ldrh r3, [r7, #2] 8001f52: 4013 ands r3, r2 8001f54: 2b00 cmp r3, #0 8001f56: d002 beq.n 8001f5e { bitstatus = GPIO_PIN_SET; 8001f58: 2301 movs r3, #1 8001f5a: 73fb strb r3, [r7, #15] 8001f5c: e001 b.n 8001f62 } else { bitstatus = GPIO_PIN_RESET; 8001f5e: 2300 movs r3, #0 8001f60: 73fb strb r3, [r7, #15] } return bitstatus; 8001f62: 7bfb ldrb r3, [r7, #15] } 8001f64: 4618 mov r0, r3 8001f66: 3714 adds r7, #20 8001f68: 46bd mov sp, r7 8001f6a: bc80 pop {r7} 8001f6c: 4770 bx lr 08001f6e : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001f6e: b480 push {r7} 8001f70: b083 sub sp, #12 8001f72: af00 add r7, sp, #0 8001f74: 6078 str r0, [r7, #4] 8001f76: 460b mov r3, r1 8001f78: 807b strh r3, [r7, #2] 8001f7a: 4613 mov r3, r2 8001f7c: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001f7e: 787b ldrb r3, [r7, #1] 8001f80: 2b00 cmp r3, #0 8001f82: d003 beq.n 8001f8c { GPIOx->BSRR = GPIO_Pin; 8001f84: 887a ldrh r2, [r7, #2] 8001f86: 687b ldr r3, [r7, #4] 8001f88: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8001f8a: e003 b.n 8001f94 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8001f8c: 887b ldrh r3, [r7, #2] 8001f8e: 041a lsls r2, r3, #16 8001f90: 687b ldr r3, [r7, #4] 8001f92: 611a str r2, [r3, #16] } 8001f94: bf00 nop 8001f96: 370c adds r7, #12 8001f98: 46bd mov sp, r7 8001f9a: bc80 pop {r7} 8001f9c: 4770 bx lr ... 08001fa0 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8001fa0: b580 push {r7, lr} 8001fa2: b084 sub sp, #16 8001fa4: af00 add r7, sp, #0 8001fa6: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8001fa8: 687b ldr r3, [r7, #4] 8001faa: 2b00 cmp r3, #0 8001fac: d101 bne.n 8001fb2 { return HAL_ERROR; 8001fae: 2301 movs r3, #1 8001fb0: e12b b.n 800220a assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8001fb2: 687b ldr r3, [r7, #4] 8001fb4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001fb8: b2db uxtb r3, r3 8001fba: 2b00 cmp r3, #0 8001fbc: d106 bne.n 8001fcc { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8001fbe: 687b ldr r3, [r7, #4] 8001fc0: 2200 movs r2, #0 8001fc2: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8001fc6: 6878 ldr r0, [r7, #4] 8001fc8: f7ff fb0a bl 80015e0 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8001fcc: 687b ldr r3, [r7, #4] 8001fce: 2224 movs r2, #36 ; 0x24 8001fd0: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001fd4: 687b ldr r3, [r7, #4] 8001fd6: 681b ldr r3, [r3, #0] 8001fd8: 681a ldr r2, [r3, #0] 8001fda: 687b ldr r3, [r7, #4] 8001fdc: 681b ldr r3, [r3, #0] 8001fde: f022 0201 bic.w r2, r2, #1 8001fe2: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8001fe4: 687b ldr r3, [r7, #4] 8001fe6: 681b ldr r3, [r3, #0] 8001fe8: 681a ldr r2, [r3, #0] 8001fea: 687b ldr r3, [r7, #4] 8001fec: 681b ldr r3, [r3, #0] 8001fee: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8001ff2: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8001ff4: 687b ldr r3, [r7, #4] 8001ff6: 681b ldr r3, [r3, #0] 8001ff8: 681a ldr r2, [r3, #0] 8001ffa: 687b ldr r3, [r7, #4] 8001ffc: 681b ldr r3, [r3, #0] 8001ffe: f422 4200 bic.w r2, r2, #32768 ; 0x8000 8002002: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8002004: f001 fba0 bl 8003748 8002008: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 800200a: 687b ldr r3, [r7, #4] 800200c: 685b ldr r3, [r3, #4] 800200e: 4a81 ldr r2, [pc, #516] ; (8002214 ) 8002010: 4293 cmp r3, r2 8002012: d807 bhi.n 8002024 8002014: 68fb ldr r3, [r7, #12] 8002016: 4a80 ldr r2, [pc, #512] ; (8002218 ) 8002018: 4293 cmp r3, r2 800201a: bf94 ite ls 800201c: 2301 movls r3, #1 800201e: 2300 movhi r3, #0 8002020: b2db uxtb r3, r3 8002022: e006 b.n 8002032 8002024: 68fb ldr r3, [r7, #12] 8002026: 4a7d ldr r2, [pc, #500] ; (800221c ) 8002028: 4293 cmp r3, r2 800202a: bf94 ite ls 800202c: 2301 movls r3, #1 800202e: 2300 movhi r3, #0 8002030: b2db uxtb r3, r3 8002032: 2b00 cmp r3, #0 8002034: d001 beq.n 800203a { return HAL_ERROR; 8002036: 2301 movs r3, #1 8002038: e0e7 b.n 800220a } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 800203a: 68fb ldr r3, [r7, #12] 800203c: 4a78 ldr r2, [pc, #480] ; (8002220 ) 800203e: fba2 2303 umull r2, r3, r2, r3 8002042: 0c9b lsrs r3, r3, #18 8002044: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002046: 687b ldr r3, [r7, #4] 8002048: 681b ldr r3, [r3, #0] 800204a: 685b ldr r3, [r3, #4] 800204c: f023 013f bic.w r1, r3, #63 ; 0x3f 8002050: 687b ldr r3, [r7, #4] 8002052: 681b ldr r3, [r3, #0] 8002054: 68ba ldr r2, [r7, #8] 8002056: 430a orrs r2, r1 8002058: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 800205a: 687b ldr r3, [r7, #4] 800205c: 681b ldr r3, [r3, #0] 800205e: 6a1b ldr r3, [r3, #32] 8002060: f023 013f bic.w r1, r3, #63 ; 0x3f 8002064: 687b ldr r3, [r7, #4] 8002066: 685b ldr r3, [r3, #4] 8002068: 4a6a ldr r2, [pc, #424] ; (8002214 ) 800206a: 4293 cmp r3, r2 800206c: d802 bhi.n 8002074 800206e: 68bb ldr r3, [r7, #8] 8002070: 3301 adds r3, #1 8002072: e009 b.n 8002088 8002074: 68bb ldr r3, [r7, #8] 8002076: f44f 7296 mov.w r2, #300 ; 0x12c 800207a: fb02 f303 mul.w r3, r2, r3 800207e: 4a69 ldr r2, [pc, #420] ; (8002224 ) 8002080: fba2 2303 umull r2, r3, r2, r3 8002084: 099b lsrs r3, r3, #6 8002086: 3301 adds r3, #1 8002088: 687a ldr r2, [r7, #4] 800208a: 6812 ldr r2, [r2, #0] 800208c: 430b orrs r3, r1 800208e: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8002090: 687b ldr r3, [r7, #4] 8002092: 681b ldr r3, [r3, #0] 8002094: 69db ldr r3, [r3, #28] 8002096: f423 424f bic.w r2, r3, #52992 ; 0xcf00 800209a: f022 02ff bic.w r2, r2, #255 ; 0xff 800209e: 687b ldr r3, [r7, #4] 80020a0: 685b ldr r3, [r3, #4] 80020a2: 495c ldr r1, [pc, #368] ; (8002214 ) 80020a4: 428b cmp r3, r1 80020a6: d819 bhi.n 80020dc 80020a8: 68fb ldr r3, [r7, #12] 80020aa: 1e59 subs r1, r3, #1 80020ac: 687b ldr r3, [r7, #4] 80020ae: 685b ldr r3, [r3, #4] 80020b0: 005b lsls r3, r3, #1 80020b2: fbb1 f3f3 udiv r3, r1, r3 80020b6: 1c59 adds r1, r3, #1 80020b8: f640 73fc movw r3, #4092 ; 0xffc 80020bc: 400b ands r3, r1 80020be: 2b00 cmp r3, #0 80020c0: d00a beq.n 80020d8 80020c2: 68fb ldr r3, [r7, #12] 80020c4: 1e59 subs r1, r3, #1 80020c6: 687b ldr r3, [r7, #4] 80020c8: 685b ldr r3, [r3, #4] 80020ca: 005b lsls r3, r3, #1 80020cc: fbb1 f3f3 udiv r3, r1, r3 80020d0: 3301 adds r3, #1 80020d2: f3c3 030b ubfx r3, r3, #0, #12 80020d6: e051 b.n 800217c 80020d8: 2304 movs r3, #4 80020da: e04f b.n 800217c 80020dc: 687b ldr r3, [r7, #4] 80020de: 689b ldr r3, [r3, #8] 80020e0: 2b00 cmp r3, #0 80020e2: d111 bne.n 8002108 80020e4: 68fb ldr r3, [r7, #12] 80020e6: 1e58 subs r0, r3, #1 80020e8: 687b ldr r3, [r7, #4] 80020ea: 6859 ldr r1, [r3, #4] 80020ec: 460b mov r3, r1 80020ee: 005b lsls r3, r3, #1 80020f0: 440b add r3, r1 80020f2: fbb0 f3f3 udiv r3, r0, r3 80020f6: 3301 adds r3, #1 80020f8: f3c3 030b ubfx r3, r3, #0, #12 80020fc: 2b00 cmp r3, #0 80020fe: bf0c ite eq 8002100: 2301 moveq r3, #1 8002102: 2300 movne r3, #0 8002104: b2db uxtb r3, r3 8002106: e012 b.n 800212e 8002108: 68fb ldr r3, [r7, #12] 800210a: 1e58 subs r0, r3, #1 800210c: 687b ldr r3, [r7, #4] 800210e: 6859 ldr r1, [r3, #4] 8002110: 460b mov r3, r1 8002112: 009b lsls r3, r3, #2 8002114: 440b add r3, r1 8002116: 0099 lsls r1, r3, #2 8002118: 440b add r3, r1 800211a: fbb0 f3f3 udiv r3, r0, r3 800211e: 3301 adds r3, #1 8002120: f3c3 030b ubfx r3, r3, #0, #12 8002124: 2b00 cmp r3, #0 8002126: bf0c ite eq 8002128: 2301 moveq r3, #1 800212a: 2300 movne r3, #0 800212c: b2db uxtb r3, r3 800212e: 2b00 cmp r3, #0 8002130: d001 beq.n 8002136 8002132: 2301 movs r3, #1 8002134: e022 b.n 800217c 8002136: 687b ldr r3, [r7, #4] 8002138: 689b ldr r3, [r3, #8] 800213a: 2b00 cmp r3, #0 800213c: d10e bne.n 800215c 800213e: 68fb ldr r3, [r7, #12] 8002140: 1e58 subs r0, r3, #1 8002142: 687b ldr r3, [r7, #4] 8002144: 6859 ldr r1, [r3, #4] 8002146: 460b mov r3, r1 8002148: 005b lsls r3, r3, #1 800214a: 440b add r3, r1 800214c: fbb0 f3f3 udiv r3, r0, r3 8002150: 3301 adds r3, #1 8002152: f3c3 030b ubfx r3, r3, #0, #12 8002156: f443 4300 orr.w r3, r3, #32768 ; 0x8000 800215a: e00f b.n 800217c 800215c: 68fb ldr r3, [r7, #12] 800215e: 1e58 subs r0, r3, #1 8002160: 687b ldr r3, [r7, #4] 8002162: 6859 ldr r1, [r3, #4] 8002164: 460b mov r3, r1 8002166: 009b lsls r3, r3, #2 8002168: 440b add r3, r1 800216a: 0099 lsls r1, r3, #2 800216c: 440b add r3, r1 800216e: fbb0 f3f3 udiv r3, r0, r3 8002172: 3301 adds r3, #1 8002174: f3c3 030b ubfx r3, r3, #0, #12 8002178: f443 4340 orr.w r3, r3, #49152 ; 0xc000 800217c: 6879 ldr r1, [r7, #4] 800217e: 6809 ldr r1, [r1, #0] 8002180: 4313 orrs r3, r2 8002182: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002184: 687b ldr r3, [r7, #4] 8002186: 681b ldr r3, [r3, #0] 8002188: 681b ldr r3, [r3, #0] 800218a: f023 01c0 bic.w r1, r3, #192 ; 0xc0 800218e: 687b ldr r3, [r7, #4] 8002190: 69da ldr r2, [r3, #28] 8002192: 687b ldr r3, [r7, #4] 8002194: 6a1b ldr r3, [r3, #32] 8002196: 431a orrs r2, r3 8002198: 687b ldr r3, [r7, #4] 800219a: 681b ldr r3, [r3, #0] 800219c: 430a orrs r2, r1 800219e: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 80021a0: 687b ldr r3, [r7, #4] 80021a2: 681b ldr r3, [r3, #0] 80021a4: 689b ldr r3, [r3, #8] 80021a6: f423 4303 bic.w r3, r3, #33536 ; 0x8300 80021aa: f023 03ff bic.w r3, r3, #255 ; 0xff 80021ae: 687a ldr r2, [r7, #4] 80021b0: 6911 ldr r1, [r2, #16] 80021b2: 687a ldr r2, [r7, #4] 80021b4: 68d2 ldr r2, [r2, #12] 80021b6: 4311 orrs r1, r2 80021b8: 687a ldr r2, [r7, #4] 80021ba: 6812 ldr r2, [r2, #0] 80021bc: 430b orrs r3, r1 80021be: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 80021c0: 687b ldr r3, [r7, #4] 80021c2: 681b ldr r3, [r3, #0] 80021c4: 68db ldr r3, [r3, #12] 80021c6: f023 01ff bic.w r1, r3, #255 ; 0xff 80021ca: 687b ldr r3, [r7, #4] 80021cc: 695a ldr r2, [r3, #20] 80021ce: 687b ldr r3, [r7, #4] 80021d0: 699b ldr r3, [r3, #24] 80021d2: 431a orrs r2, r3 80021d4: 687b ldr r3, [r7, #4] 80021d6: 681b ldr r3, [r3, #0] 80021d8: 430a orrs r2, r1 80021da: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 80021dc: 687b ldr r3, [r7, #4] 80021de: 681b ldr r3, [r3, #0] 80021e0: 681a ldr r2, [r3, #0] 80021e2: 687b ldr r3, [r7, #4] 80021e4: 681b ldr r3, [r3, #0] 80021e6: f042 0201 orr.w r2, r2, #1 80021ea: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80021ec: 687b ldr r3, [r7, #4] 80021ee: 2200 movs r2, #0 80021f0: 641a str r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_READY; 80021f2: 687b ldr r3, [r7, #4] 80021f4: 2220 movs r2, #32 80021f6: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->PreviousState = I2C_STATE_NONE; 80021fa: 687b ldr r3, [r7, #4] 80021fc: 2200 movs r2, #0 80021fe: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002200: 687b ldr r3, [r7, #4] 8002202: 2200 movs r2, #0 8002204: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 8002208: 2300 movs r3, #0 } 800220a: 4618 mov r0, r3 800220c: 3710 adds r7, #16 800220e: 46bd mov sp, r7 8002210: bd80 pop {r7, pc} 8002212: bf00 nop 8002214: 000186a0 .word 0x000186a0 8002218: 001e847f .word 0x001e847f 800221c: 003d08ff .word 0x003d08ff 8002220: 431bde83 .word 0x431bde83 8002224: 10624dd3 .word 0x10624dd3 08002228 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8002228: b580 push {r7, lr} 800222a: b088 sub sp, #32 800222c: af02 add r7, sp, #8 800222e: 60f8 str r0, [r7, #12] 8002230: 4608 mov r0, r1 8002232: 4611 mov r1, r2 8002234: 461a mov r2, r3 8002236: 4603 mov r3, r0 8002238: 817b strh r3, [r7, #10] 800223a: 460b mov r3, r1 800223c: 813b strh r3, [r7, #8] 800223e: 4613 mov r3, r2 8002240: 80fb strh r3, [r7, #6] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 8002242: f7ff fbd7 bl 80019f4 8002246: 6178 str r0, [r7, #20] /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8002248: 68fb ldr r3, [r7, #12] 800224a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 800224e: b2db uxtb r3, r3 8002250: 2b20 cmp r3, #32 8002252: f040 80d9 bne.w 8002408 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 8002256: 697b ldr r3, [r7, #20] 8002258: 9300 str r3, [sp, #0] 800225a: 2319 movs r3, #25 800225c: 2201 movs r2, #1 800225e: 496d ldr r1, [pc, #436] ; (8002414 ) 8002260: 68f8 ldr r0, [r7, #12] 8002262: f000 fcc1 bl 8002be8 8002266: 4603 mov r3, r0 8002268: 2b00 cmp r3, #0 800226a: d001 beq.n 8002270 { return HAL_BUSY; 800226c: 2302 movs r3, #2 800226e: e0cc b.n 800240a } /* Process Locked */ __HAL_LOCK(hi2c); 8002270: 68fb ldr r3, [r7, #12] 8002272: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002276: 2b01 cmp r3, #1 8002278: d101 bne.n 800227e 800227a: 2302 movs r3, #2 800227c: e0c5 b.n 800240a 800227e: 68fb ldr r3, [r7, #12] 8002280: 2201 movs r2, #1 8002282: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 8002286: 68fb ldr r3, [r7, #12] 8002288: 681b ldr r3, [r3, #0] 800228a: 681b ldr r3, [r3, #0] 800228c: f003 0301 and.w r3, r3, #1 8002290: 2b01 cmp r3, #1 8002292: d007 beq.n 80022a4 { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002294: 68fb ldr r3, [r7, #12] 8002296: 681b ldr r3, [r3, #0] 8002298: 681a ldr r2, [r3, #0] 800229a: 68fb ldr r3, [r7, #12] 800229c: 681b ldr r3, [r3, #0] 800229e: f042 0201 orr.w r2, r2, #1 80022a2: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 80022a4: 68fb ldr r3, [r7, #12] 80022a6: 681b ldr r3, [r3, #0] 80022a8: 681a ldr r2, [r3, #0] 80022aa: 68fb ldr r3, [r7, #12] 80022ac: 681b ldr r3, [r3, #0] 80022ae: f422 6200 bic.w r2, r2, #2048 ; 0x800 80022b2: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_TX; 80022b4: 68fb ldr r3, [r7, #12] 80022b6: 2221 movs r2, #33 ; 0x21 80022b8: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 80022bc: 68fb ldr r3, [r7, #12] 80022be: 2240 movs r2, #64 ; 0x40 80022c0: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80022c4: 68fb ldr r3, [r7, #12] 80022c6: 2200 movs r2, #0 80022c8: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 80022ca: 68fb ldr r3, [r7, #12] 80022cc: 6a3a ldr r2, [r7, #32] 80022ce: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 80022d0: 68fb ldr r3, [r7, #12] 80022d2: 8cba ldrh r2, [r7, #36] ; 0x24 80022d4: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 80022d6: 68fb ldr r3, [r7, #12] 80022d8: 8d5b ldrh r3, [r3, #42] ; 0x2a 80022da: b29a uxth r2, r3 80022dc: 68fb ldr r3, [r7, #12] 80022de: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80022e0: 68fb ldr r3, [r7, #12] 80022e2: 4a4d ldr r2, [pc, #308] ; (8002418 ) 80022e4: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 80022e6: 88f8 ldrh r0, [r7, #6] 80022e8: 893a ldrh r2, [r7, #8] 80022ea: 8979 ldrh r1, [r7, #10] 80022ec: 697b ldr r3, [r7, #20] 80022ee: 9301 str r3, [sp, #4] 80022f0: 6abb ldr r3, [r7, #40] ; 0x28 80022f2: 9300 str r3, [sp, #0] 80022f4: 4603 mov r3, r0 80022f6: 68f8 ldr r0, [r7, #12] 80022f8: f000 faf8 bl 80028ec 80022fc: 4603 mov r3, r0 80022fe: 2b00 cmp r3, #0 8002300: d052 beq.n 80023a8 { return HAL_ERROR; 8002302: 2301 movs r3, #1 8002304: e081 b.n 800240a } while (hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8002306: 697a ldr r2, [r7, #20] 8002308: 6ab9 ldr r1, [r7, #40] ; 0x28 800230a: 68f8 ldr r0, [r7, #12] 800230c: f000 fd42 bl 8002d94 8002310: 4603 mov r3, r0 8002312: 2b00 cmp r3, #0 8002314: d00d beq.n 8002332 { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 8002316: 68fb ldr r3, [r7, #12] 8002318: 6c1b ldr r3, [r3, #64] ; 0x40 800231a: 2b04 cmp r3, #4 800231c: d107 bne.n 800232e { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 800231e: 68fb ldr r3, [r7, #12] 8002320: 681b ldr r3, [r3, #0] 8002322: 681a ldr r2, [r3, #0] 8002324: 68fb ldr r3, [r7, #12] 8002326: 681b ldr r3, [r3, #0] 8002328: f442 7200 orr.w r2, r2, #512 ; 0x200 800232c: 601a str r2, [r3, #0] } return HAL_ERROR; 800232e: 2301 movs r3, #1 8002330: e06b b.n 800240a } /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 8002332: 68fb ldr r3, [r7, #12] 8002334: 6a5b ldr r3, [r3, #36] ; 0x24 8002336: 781a ldrb r2, [r3, #0] 8002338: 68fb ldr r3, [r7, #12] 800233a: 681b ldr r3, [r3, #0] 800233c: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800233e: 68fb ldr r3, [r7, #12] 8002340: 6a5b ldr r3, [r3, #36] ; 0x24 8002342: 1c5a adds r2, r3, #1 8002344: 68fb ldr r3, [r7, #12] 8002346: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002348: 68fb ldr r3, [r7, #12] 800234a: 8d1b ldrh r3, [r3, #40] ; 0x28 800234c: 3b01 subs r3, #1 800234e: b29a uxth r2, r3 8002350: 68fb ldr r3, [r7, #12] 8002352: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002354: 68fb ldr r3, [r7, #12] 8002356: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002358: b29b uxth r3, r3 800235a: 3b01 subs r3, #1 800235c: b29a uxth r2, r3 800235e: 68fb ldr r3, [r7, #12] 8002360: 855a strh r2, [r3, #42] ; 0x2a if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 8002362: 68fb ldr r3, [r7, #12] 8002364: 681b ldr r3, [r3, #0] 8002366: 695b ldr r3, [r3, #20] 8002368: f003 0304 and.w r3, r3, #4 800236c: 2b04 cmp r3, #4 800236e: d11b bne.n 80023a8 8002370: 68fb ldr r3, [r7, #12] 8002372: 8d1b ldrh r3, [r3, #40] ; 0x28 8002374: 2b00 cmp r3, #0 8002376: d017 beq.n 80023a8 { /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 8002378: 68fb ldr r3, [r7, #12] 800237a: 6a5b ldr r3, [r3, #36] ; 0x24 800237c: 781a ldrb r2, [r3, #0] 800237e: 68fb ldr r3, [r7, #12] 8002380: 681b ldr r3, [r3, #0] 8002382: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002384: 68fb ldr r3, [r7, #12] 8002386: 6a5b ldr r3, [r3, #36] ; 0x24 8002388: 1c5a adds r2, r3, #1 800238a: 68fb ldr r3, [r7, #12] 800238c: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800238e: 68fb ldr r3, [r7, #12] 8002390: 8d1b ldrh r3, [r3, #40] ; 0x28 8002392: 3b01 subs r3, #1 8002394: b29a uxth r2, r3 8002396: 68fb ldr r3, [r7, #12] 8002398: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800239a: 68fb ldr r3, [r7, #12] 800239c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800239e: b29b uxth r3, r3 80023a0: 3b01 subs r3, #1 80023a2: b29a uxth r2, r3 80023a4: 68fb ldr r3, [r7, #12] 80023a6: 855a strh r2, [r3, #42] ; 0x2a while (hi2c->XferSize > 0U) 80023a8: 68fb ldr r3, [r7, #12] 80023aa: 8d1b ldrh r3, [r3, #40] ; 0x28 80023ac: 2b00 cmp r3, #0 80023ae: d1aa bne.n 8002306 } } /* Wait until BTF flag is set */ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80023b0: 697a ldr r2, [r7, #20] 80023b2: 6ab9 ldr r1, [r7, #40] ; 0x28 80023b4: 68f8 ldr r0, [r7, #12] 80023b6: f000 fd2e bl 8002e16 80023ba: 4603 mov r3, r0 80023bc: 2b00 cmp r3, #0 80023be: d00d beq.n 80023dc { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 80023c0: 68fb ldr r3, [r7, #12] 80023c2: 6c1b ldr r3, [r3, #64] ; 0x40 80023c4: 2b04 cmp r3, #4 80023c6: d107 bne.n 80023d8 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80023c8: 68fb ldr r3, [r7, #12] 80023ca: 681b ldr r3, [r3, #0] 80023cc: 681a ldr r2, [r3, #0] 80023ce: 68fb ldr r3, [r7, #12] 80023d0: 681b ldr r3, [r3, #0] 80023d2: f442 7200 orr.w r2, r2, #512 ; 0x200 80023d6: 601a str r2, [r3, #0] } return HAL_ERROR; 80023d8: 2301 movs r3, #1 80023da: e016 b.n 800240a } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80023dc: 68fb ldr r3, [r7, #12] 80023de: 681b ldr r3, [r3, #0] 80023e0: 681a ldr r2, [r3, #0] 80023e2: 68fb ldr r3, [r7, #12] 80023e4: 681b ldr r3, [r3, #0] 80023e6: f442 7200 orr.w r2, r2, #512 ; 0x200 80023ea: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80023ec: 68fb ldr r3, [r7, #12] 80023ee: 2220 movs r2, #32 80023f0: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 80023f4: 68fb ldr r3, [r7, #12] 80023f6: 2200 movs r2, #0 80023f8: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80023fc: 68fb ldr r3, [r7, #12] 80023fe: 2200 movs r2, #0 8002400: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8002404: 2300 movs r3, #0 8002406: e000 b.n 800240a } else { return HAL_BUSY; 8002408: 2302 movs r3, #2 } } 800240a: 4618 mov r0, r3 800240c: 3718 adds r7, #24 800240e: 46bd mov sp, r7 8002410: bd80 pop {r7, pc} 8002412: bf00 nop 8002414: 00100002 .word 0x00100002 8002418: ffff0000 .word 0xffff0000 0800241c : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800241c: b580 push {r7, lr} 800241e: b08c sub sp, #48 ; 0x30 8002420: af02 add r7, sp, #8 8002422: 60f8 str r0, [r7, #12] 8002424: 4608 mov r0, r1 8002426: 4611 mov r1, r2 8002428: 461a mov r2, r3 800242a: 4603 mov r3, r0 800242c: 817b strh r3, [r7, #10] 800242e: 460b mov r3, r1 8002430: 813b strh r3, [r7, #8] 8002432: 4613 mov r3, r2 8002434: 80fb strh r3, [r7, #6] __IO uint32_t count = 0U; 8002436: 2300 movs r3, #0 8002438: 623b str r3, [r7, #32] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 800243a: f7ff fadb bl 80019f4 800243e: 6278 str r0, [r7, #36] ; 0x24 /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8002440: 68fb ldr r3, [r7, #12] 8002442: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8002446: b2db uxtb r3, r3 8002448: 2b20 cmp r3, #32 800244a: f040 8244 bne.w 80028d6 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 800244e: 6a7b ldr r3, [r7, #36] ; 0x24 8002450: 9300 str r3, [sp, #0] 8002452: 2319 movs r3, #25 8002454: 2201 movs r2, #1 8002456: 4982 ldr r1, [pc, #520] ; (8002660 ) 8002458: 68f8 ldr r0, [r7, #12] 800245a: f000 fbc5 bl 8002be8 800245e: 4603 mov r3, r0 8002460: 2b00 cmp r3, #0 8002462: d001 beq.n 8002468 { return HAL_BUSY; 8002464: 2302 movs r3, #2 8002466: e237 b.n 80028d8 } /* Process Locked */ __HAL_LOCK(hi2c); 8002468: 68fb ldr r3, [r7, #12] 800246a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800246e: 2b01 cmp r3, #1 8002470: d101 bne.n 8002476 8002472: 2302 movs r3, #2 8002474: e230 b.n 80028d8 8002476: 68fb ldr r3, [r7, #12] 8002478: 2201 movs r2, #1 800247a: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 800247e: 68fb ldr r3, [r7, #12] 8002480: 681b ldr r3, [r3, #0] 8002482: 681b ldr r3, [r3, #0] 8002484: f003 0301 and.w r3, r3, #1 8002488: 2b01 cmp r3, #1 800248a: d007 beq.n 800249c { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800248c: 68fb ldr r3, [r7, #12] 800248e: 681b ldr r3, [r3, #0] 8002490: 681a ldr r2, [r3, #0] 8002492: 68fb ldr r3, [r7, #12] 8002494: 681b ldr r3, [r3, #0] 8002496: f042 0201 orr.w r2, r2, #1 800249a: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 800249c: 68fb ldr r3, [r7, #12] 800249e: 681b ldr r3, [r3, #0] 80024a0: 681a ldr r2, [r3, #0] 80024a2: 68fb ldr r3, [r7, #12] 80024a4: 681b ldr r3, [r3, #0] 80024a6: f422 6200 bic.w r2, r2, #2048 ; 0x800 80024aa: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_RX; 80024ac: 68fb ldr r3, [r7, #12] 80024ae: 2222 movs r2, #34 ; 0x22 80024b0: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 80024b4: 68fb ldr r3, [r7, #12] 80024b6: 2240 movs r2, #64 ; 0x40 80024b8: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80024bc: 68fb ldr r3, [r7, #12] 80024be: 2200 movs r2, #0 80024c0: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 80024c2: 68fb ldr r3, [r7, #12] 80024c4: 6b3a ldr r2, [r7, #48] ; 0x30 80024c6: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 80024c8: 68fb ldr r3, [r7, #12] 80024ca: 8eba ldrh r2, [r7, #52] ; 0x34 80024cc: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 80024ce: 68fb ldr r3, [r7, #12] 80024d0: 8d5b ldrh r3, [r3, #42] ; 0x2a 80024d2: b29a uxth r2, r3 80024d4: 68fb ldr r3, [r7, #12] 80024d6: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80024d8: 68fb ldr r3, [r7, #12] 80024da: 4a62 ldr r2, [pc, #392] ; (8002664 ) 80024dc: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 80024de: 88f8 ldrh r0, [r7, #6] 80024e0: 893a ldrh r2, [r7, #8] 80024e2: 8979 ldrh r1, [r7, #10] 80024e4: 6a7b ldr r3, [r7, #36] ; 0x24 80024e6: 9301 str r3, [sp, #4] 80024e8: 6bbb ldr r3, [r7, #56] ; 0x38 80024ea: 9300 str r3, [sp, #0] 80024ec: 4603 mov r3, r0 80024ee: 68f8 ldr r0, [r7, #12] 80024f0: f000 fa92 bl 8002a18 80024f4: 4603 mov r3, r0 80024f6: 2b00 cmp r3, #0 80024f8: d001 beq.n 80024fe { return HAL_ERROR; 80024fa: 2301 movs r3, #1 80024fc: e1ec b.n 80028d8 } if (hi2c->XferSize == 0U) 80024fe: 68fb ldr r3, [r7, #12] 8002500: 8d1b ldrh r3, [r3, #40] ; 0x28 8002502: 2b00 cmp r3, #0 8002504: d113 bne.n 800252e { /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8002506: 2300 movs r3, #0 8002508: 61fb str r3, [r7, #28] 800250a: 68fb ldr r3, [r7, #12] 800250c: 681b ldr r3, [r3, #0] 800250e: 695b ldr r3, [r3, #20] 8002510: 61fb str r3, [r7, #28] 8002512: 68fb ldr r3, [r7, #12] 8002514: 681b ldr r3, [r3, #0] 8002516: 699b ldr r3, [r3, #24] 8002518: 61fb str r3, [r7, #28] 800251a: 69fb ldr r3, [r7, #28] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 800251c: 68fb ldr r3, [r7, #12] 800251e: 681b ldr r3, [r3, #0] 8002520: 681a ldr r2, [r3, #0] 8002522: 68fb ldr r3, [r7, #12] 8002524: 681b ldr r3, [r3, #0] 8002526: f442 7200 orr.w r2, r2, #512 ; 0x200 800252a: 601a str r2, [r3, #0] 800252c: e1c0 b.n 80028b0 } else if (hi2c->XferSize == 1U) 800252e: 68fb ldr r3, [r7, #12] 8002530: 8d1b ldrh r3, [r3, #40] ; 0x28 8002532: 2b01 cmp r3, #1 8002534: d11e bne.n 8002574 { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8002536: 68fb ldr r3, [r7, #12] 8002538: 681b ldr r3, [r3, #0] 800253a: 681a ldr r2, [r3, #0] 800253c: 68fb ldr r3, [r7, #12] 800253e: 681b ldr r3, [r3, #0] 8002540: f422 6280 bic.w r2, r2, #1024 ; 0x400 8002544: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8002546: b672 cpsid i } 8002548: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 800254a: 2300 movs r3, #0 800254c: 61bb str r3, [r7, #24] 800254e: 68fb ldr r3, [r7, #12] 8002550: 681b ldr r3, [r3, #0] 8002552: 695b ldr r3, [r3, #20] 8002554: 61bb str r3, [r7, #24] 8002556: 68fb ldr r3, [r7, #12] 8002558: 681b ldr r3, [r3, #0] 800255a: 699b ldr r3, [r3, #24] 800255c: 61bb str r3, [r7, #24] 800255e: 69bb ldr r3, [r7, #24] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002560: 68fb ldr r3, [r7, #12] 8002562: 681b ldr r3, [r3, #0] 8002564: 681a ldr r2, [r3, #0] 8002566: 68fb ldr r3, [r7, #12] 8002568: 681b ldr r3, [r3, #0] 800256a: f442 7200 orr.w r2, r2, #512 ; 0x200 800256e: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8002570: b662 cpsie i } 8002572: e035 b.n 80025e0 /* Re-enable IRQs */ __enable_irq(); } else if (hi2c->XferSize == 2U) 8002574: 68fb ldr r3, [r7, #12] 8002576: 8d1b ldrh r3, [r3, #40] ; 0x28 8002578: 2b02 cmp r3, #2 800257a: d11e bne.n 80025ba { /* Enable Pos */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 800257c: 68fb ldr r3, [r7, #12] 800257e: 681b ldr r3, [r3, #0] 8002580: 681a ldr r2, [r3, #0] 8002582: 68fb ldr r3, [r7, #12] 8002584: 681b ldr r3, [r3, #0] 8002586: f442 6200 orr.w r2, r2, #2048 ; 0x800 800258a: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 800258c: b672 cpsid i } 800258e: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8002590: 2300 movs r3, #0 8002592: 617b str r3, [r7, #20] 8002594: 68fb ldr r3, [r7, #12] 8002596: 681b ldr r3, [r3, #0] 8002598: 695b ldr r3, [r3, #20] 800259a: 617b str r3, [r7, #20] 800259c: 68fb ldr r3, [r7, #12] 800259e: 681b ldr r3, [r3, #0] 80025a0: 699b ldr r3, [r3, #24] 80025a2: 617b str r3, [r7, #20] 80025a4: 697b ldr r3, [r7, #20] /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80025a6: 68fb ldr r3, [r7, #12] 80025a8: 681b ldr r3, [r3, #0] 80025aa: 681a ldr r2, [r3, #0] 80025ac: 68fb ldr r3, [r7, #12] 80025ae: 681b ldr r3, [r3, #0] 80025b0: f422 6280 bic.w r2, r2, #1024 ; 0x400 80025b4: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 80025b6: b662 cpsie i } 80025b8: e012 b.n 80025e0 __enable_irq(); } else { /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80025ba: 68fb ldr r3, [r7, #12] 80025bc: 681b ldr r3, [r3, #0] 80025be: 681a ldr r2, [r3, #0] 80025c0: 68fb ldr r3, [r7, #12] 80025c2: 681b ldr r3, [r3, #0] 80025c4: f442 6280 orr.w r2, r2, #1024 ; 0x400 80025c8: 601a str r2, [r3, #0] /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 80025ca: 2300 movs r3, #0 80025cc: 613b str r3, [r7, #16] 80025ce: 68fb ldr r3, [r7, #12] 80025d0: 681b ldr r3, [r3, #0] 80025d2: 695b ldr r3, [r3, #20] 80025d4: 613b str r3, [r7, #16] 80025d6: 68fb ldr r3, [r7, #12] 80025d8: 681b ldr r3, [r3, #0] 80025da: 699b ldr r3, [r3, #24] 80025dc: 613b str r3, [r7, #16] 80025de: 693b ldr r3, [r7, #16] } while (hi2c->XferSize > 0U) 80025e0: e166 b.n 80028b0 { if (hi2c->XferSize <= 3U) 80025e2: 68fb ldr r3, [r7, #12] 80025e4: 8d1b ldrh r3, [r3, #40] ; 0x28 80025e6: 2b03 cmp r3, #3 80025e8: f200 811f bhi.w 800282a { /* One byte */ if (hi2c->XferSize == 1U) 80025ec: 68fb ldr r3, [r7, #12] 80025ee: 8d1b ldrh r3, [r3, #40] ; 0x28 80025f0: 2b01 cmp r3, #1 80025f2: d123 bne.n 800263c { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80025f4: 6a7a ldr r2, [r7, #36] ; 0x24 80025f6: 6bb9 ldr r1, [r7, #56] ; 0x38 80025f8: 68f8 ldr r0, [r7, #12] 80025fa: f000 fc4d bl 8002e98 80025fe: 4603 mov r3, r0 8002600: 2b00 cmp r3, #0 8002602: d001 beq.n 8002608 { return HAL_ERROR; 8002604: 2301 movs r3, #1 8002606: e167 b.n 80028d8 } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002608: 68fb ldr r3, [r7, #12] 800260a: 681b ldr r3, [r3, #0] 800260c: 691a ldr r2, [r3, #16] 800260e: 68fb ldr r3, [r7, #12] 8002610: 6a5b ldr r3, [r3, #36] ; 0x24 8002612: b2d2 uxtb r2, r2 8002614: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002616: 68fb ldr r3, [r7, #12] 8002618: 6a5b ldr r3, [r3, #36] ; 0x24 800261a: 1c5a adds r2, r3, #1 800261c: 68fb ldr r3, [r7, #12] 800261e: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002620: 68fb ldr r3, [r7, #12] 8002622: 8d1b ldrh r3, [r3, #40] ; 0x28 8002624: 3b01 subs r3, #1 8002626: b29a uxth r2, r3 8002628: 68fb ldr r3, [r7, #12] 800262a: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800262c: 68fb ldr r3, [r7, #12] 800262e: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002630: b29b uxth r3, r3 8002632: 3b01 subs r3, #1 8002634: b29a uxth r2, r3 8002636: 68fb ldr r3, [r7, #12] 8002638: 855a strh r2, [r3, #42] ; 0x2a 800263a: e139 b.n 80028b0 } /* Two bytes */ else if (hi2c->XferSize == 2U) 800263c: 68fb ldr r3, [r7, #12] 800263e: 8d1b ldrh r3, [r3, #40] ; 0x28 8002640: 2b02 cmp r3, #2 8002642: d152 bne.n 80026ea { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 8002644: 6a7b ldr r3, [r7, #36] ; 0x24 8002646: 9300 str r3, [sp, #0] 8002648: 6bbb ldr r3, [r7, #56] ; 0x38 800264a: 2200 movs r2, #0 800264c: 4906 ldr r1, [pc, #24] ; (8002668 ) 800264e: 68f8 ldr r0, [r7, #12] 8002650: f000 faca bl 8002be8 8002654: 4603 mov r3, r0 8002656: 2b00 cmp r3, #0 8002658: d008 beq.n 800266c { return HAL_ERROR; 800265a: 2301 movs r3, #1 800265c: e13c b.n 80028d8 800265e: bf00 nop 8002660: 00100002 .word 0x00100002 8002664: ffff0000 .word 0xffff0000 8002668: 00010004 .word 0x00010004 __ASM volatile ("cpsid i" : : : "memory"); 800266c: b672 cpsid i } 800266e: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002670: 68fb ldr r3, [r7, #12] 8002672: 681b ldr r3, [r3, #0] 8002674: 681a ldr r2, [r3, #0] 8002676: 68fb ldr r3, [r7, #12] 8002678: 681b ldr r3, [r3, #0] 800267a: f442 7200 orr.w r2, r2, #512 ; 0x200 800267e: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002680: 68fb ldr r3, [r7, #12] 8002682: 681b ldr r3, [r3, #0] 8002684: 691a ldr r2, [r3, #16] 8002686: 68fb ldr r3, [r7, #12] 8002688: 6a5b ldr r3, [r3, #36] ; 0x24 800268a: b2d2 uxtb r2, r2 800268c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800268e: 68fb ldr r3, [r7, #12] 8002690: 6a5b ldr r3, [r3, #36] ; 0x24 8002692: 1c5a adds r2, r3, #1 8002694: 68fb ldr r3, [r7, #12] 8002696: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002698: 68fb ldr r3, [r7, #12] 800269a: 8d1b ldrh r3, [r3, #40] ; 0x28 800269c: 3b01 subs r3, #1 800269e: b29a uxth r2, r3 80026a0: 68fb ldr r3, [r7, #12] 80026a2: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80026a4: 68fb ldr r3, [r7, #12] 80026a6: 8d5b ldrh r3, [r3, #42] ; 0x2a 80026a8: b29b uxth r3, r3 80026aa: 3b01 subs r3, #1 80026ac: b29a uxth r2, r3 80026ae: 68fb ldr r3, [r7, #12] 80026b0: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 80026b2: b662 cpsie i } 80026b4: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80026b6: 68fb ldr r3, [r7, #12] 80026b8: 681b ldr r3, [r3, #0] 80026ba: 691a ldr r2, [r3, #16] 80026bc: 68fb ldr r3, [r7, #12] 80026be: 6a5b ldr r3, [r3, #36] ; 0x24 80026c0: b2d2 uxtb r2, r2 80026c2: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80026c4: 68fb ldr r3, [r7, #12] 80026c6: 6a5b ldr r3, [r3, #36] ; 0x24 80026c8: 1c5a adds r2, r3, #1 80026ca: 68fb ldr r3, [r7, #12] 80026cc: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80026ce: 68fb ldr r3, [r7, #12] 80026d0: 8d1b ldrh r3, [r3, #40] ; 0x28 80026d2: 3b01 subs r3, #1 80026d4: b29a uxth r2, r3 80026d6: 68fb ldr r3, [r7, #12] 80026d8: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80026da: 68fb ldr r3, [r7, #12] 80026dc: 8d5b ldrh r3, [r3, #42] ; 0x2a 80026de: b29b uxth r3, r3 80026e0: 3b01 subs r3, #1 80026e2: b29a uxth r2, r3 80026e4: 68fb ldr r3, [r7, #12] 80026e6: 855a strh r2, [r3, #42] ; 0x2a 80026e8: e0e2 b.n 80028b0 } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 80026ea: 6a7b ldr r3, [r7, #36] ; 0x24 80026ec: 9300 str r3, [sp, #0] 80026ee: 6bbb ldr r3, [r7, #56] ; 0x38 80026f0: 2200 movs r2, #0 80026f2: 497b ldr r1, [pc, #492] ; (80028e0 ) 80026f4: 68f8 ldr r0, [r7, #12] 80026f6: f000 fa77 bl 8002be8 80026fa: 4603 mov r3, r0 80026fc: 2b00 cmp r3, #0 80026fe: d001 beq.n 8002704 { return HAL_ERROR; 8002700: 2301 movs r3, #1 8002702: e0e9 b.n 80028d8 } /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8002704: 68fb ldr r3, [r7, #12] 8002706: 681b ldr r3, [r3, #0] 8002708: 681a ldr r2, [r3, #0] 800270a: 68fb ldr r3, [r7, #12] 800270c: 681b ldr r3, [r3, #0] 800270e: f422 6280 bic.w r2, r2, #1024 ; 0x400 8002712: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8002714: b672 cpsid i } 8002716: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002718: 68fb ldr r3, [r7, #12] 800271a: 681b ldr r3, [r3, #0] 800271c: 691a ldr r2, [r3, #16] 800271e: 68fb ldr r3, [r7, #12] 8002720: 6a5b ldr r3, [r3, #36] ; 0x24 8002722: b2d2 uxtb r2, r2 8002724: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002726: 68fb ldr r3, [r7, #12] 8002728: 6a5b ldr r3, [r3, #36] ; 0x24 800272a: 1c5a adds r2, r3, #1 800272c: 68fb ldr r3, [r7, #12] 800272e: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002730: 68fb ldr r3, [r7, #12] 8002732: 8d1b ldrh r3, [r3, #40] ; 0x28 8002734: 3b01 subs r3, #1 8002736: b29a uxth r2, r3 8002738: 68fb ldr r3, [r7, #12] 800273a: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800273c: 68fb ldr r3, [r7, #12] 800273e: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002740: b29b uxth r3, r3 8002742: 3b01 subs r3, #1 8002744: b29a uxth r2, r3 8002746: 68fb ldr r3, [r7, #12] 8002748: 855a strh r2, [r3, #42] ; 0x2a /* Wait until BTF flag is set */ count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 800274a: 4b66 ldr r3, [pc, #408] ; (80028e4 ) 800274c: 681b ldr r3, [r3, #0] 800274e: 08db lsrs r3, r3, #3 8002750: 4a65 ldr r2, [pc, #404] ; (80028e8 ) 8002752: fba2 2303 umull r2, r3, r2, r3 8002756: 0a1a lsrs r2, r3, #8 8002758: 4613 mov r3, r2 800275a: 009b lsls r3, r3, #2 800275c: 4413 add r3, r2 800275e: 00da lsls r2, r3, #3 8002760: 1ad3 subs r3, r2, r3 8002762: 623b str r3, [r7, #32] do { count--; 8002764: 6a3b ldr r3, [r7, #32] 8002766: 3b01 subs r3, #1 8002768: 623b str r3, [r7, #32] if (count == 0U) 800276a: 6a3b ldr r3, [r7, #32] 800276c: 2b00 cmp r3, #0 800276e: d118 bne.n 80027a2 { hi2c->PreviousState = I2C_STATE_NONE; 8002770: 68fb ldr r3, [r7, #12] 8002772: 2200 movs r2, #0 8002774: 631a str r2, [r3, #48] ; 0x30 hi2c->State = HAL_I2C_STATE_READY; 8002776: 68fb ldr r3, [r7, #12] 8002778: 2220 movs r2, #32 800277a: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 800277e: 68fb ldr r3, [r7, #12] 8002780: 2200 movs r2, #0 8002782: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8002786: 68fb ldr r3, [r7, #12] 8002788: 6c1b ldr r3, [r3, #64] ; 0x40 800278a: f043 0220 orr.w r2, r3, #32 800278e: 68fb ldr r3, [r7, #12] 8002790: 641a str r2, [r3, #64] ; 0x40 __ASM volatile ("cpsie i" : : : "memory"); 8002792: b662 cpsie i } 8002794: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002796: 68fb ldr r3, [r7, #12] 8002798: 2200 movs r2, #0 800279a: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_ERROR; 800279e: 2301 movs r3, #1 80027a0: e09a b.n 80028d8 } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 80027a2: 68fb ldr r3, [r7, #12] 80027a4: 681b ldr r3, [r3, #0] 80027a6: 695b ldr r3, [r3, #20] 80027a8: f003 0304 and.w r3, r3, #4 80027ac: 2b04 cmp r3, #4 80027ae: d1d9 bne.n 8002764 /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80027b0: 68fb ldr r3, [r7, #12] 80027b2: 681b ldr r3, [r3, #0] 80027b4: 681a ldr r2, [r3, #0] 80027b6: 68fb ldr r3, [r7, #12] 80027b8: 681b ldr r3, [r3, #0] 80027ba: f442 7200 orr.w r2, r2, #512 ; 0x200 80027be: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80027c0: 68fb ldr r3, [r7, #12] 80027c2: 681b ldr r3, [r3, #0] 80027c4: 691a ldr r2, [r3, #16] 80027c6: 68fb ldr r3, [r7, #12] 80027c8: 6a5b ldr r3, [r3, #36] ; 0x24 80027ca: b2d2 uxtb r2, r2 80027cc: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80027ce: 68fb ldr r3, [r7, #12] 80027d0: 6a5b ldr r3, [r3, #36] ; 0x24 80027d2: 1c5a adds r2, r3, #1 80027d4: 68fb ldr r3, [r7, #12] 80027d6: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80027d8: 68fb ldr r3, [r7, #12] 80027da: 8d1b ldrh r3, [r3, #40] ; 0x28 80027dc: 3b01 subs r3, #1 80027de: b29a uxth r2, r3 80027e0: 68fb ldr r3, [r7, #12] 80027e2: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80027e4: 68fb ldr r3, [r7, #12] 80027e6: 8d5b ldrh r3, [r3, #42] ; 0x2a 80027e8: b29b uxth r3, r3 80027ea: 3b01 subs r3, #1 80027ec: b29a uxth r2, r3 80027ee: 68fb ldr r3, [r7, #12] 80027f0: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 80027f2: b662 cpsie i } 80027f4: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80027f6: 68fb ldr r3, [r7, #12] 80027f8: 681b ldr r3, [r3, #0] 80027fa: 691a ldr r2, [r3, #16] 80027fc: 68fb ldr r3, [r7, #12] 80027fe: 6a5b ldr r3, [r3, #36] ; 0x24 8002800: b2d2 uxtb r2, r2 8002802: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002804: 68fb ldr r3, [r7, #12] 8002806: 6a5b ldr r3, [r3, #36] ; 0x24 8002808: 1c5a adds r2, r3, #1 800280a: 68fb ldr r3, [r7, #12] 800280c: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800280e: 68fb ldr r3, [r7, #12] 8002810: 8d1b ldrh r3, [r3, #40] ; 0x28 8002812: 3b01 subs r3, #1 8002814: b29a uxth r2, r3 8002816: 68fb ldr r3, [r7, #12] 8002818: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800281a: 68fb ldr r3, [r7, #12] 800281c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800281e: b29b uxth r3, r3 8002820: 3b01 subs r3, #1 8002822: b29a uxth r2, r3 8002824: 68fb ldr r3, [r7, #12] 8002826: 855a strh r2, [r3, #42] ; 0x2a 8002828: e042 b.n 80028b0 } } else { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 800282a: 6a7a ldr r2, [r7, #36] ; 0x24 800282c: 6bb9 ldr r1, [r7, #56] ; 0x38 800282e: 68f8 ldr r0, [r7, #12] 8002830: f000 fb32 bl 8002e98