: /** * @brief The application entry point. * @retval int */ int main(void) { 8001108: b580 push {r7, lr} 800110a: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800110c: f000 faf4 bl 80016f8 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001110: f000 f807 bl 8001122 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001114: f000 f84a bl 80011ac MX_FSMC_Init(); 8001118: f000 f8e0 bl 80012dc /* USER CODE BEGIN 2 */ main_app(); 800111c: f002 fe82 bl 8003e24 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8001120: e7fe b.n 8001120 08001122 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001122: b580 push {r7, lr} 8001124: b090 sub sp, #64 ; 0x40 8001126: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001128: f107 0318 add.w r3, r7, #24 800112c: 2228 movs r2, #40 ; 0x28 800112e: 2100 movs r1, #0 8001130: 4618 mov r0, r3 8001132: f003 f87d bl 8004230 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001136: 1d3b adds r3, r7, #4 8001138: 2200 movs r2, #0 800113a: 601a str r2, [r3, #0] 800113c: 605a str r2, [r3, #4] 800113e: 609a str r2, [r3, #8] 8001140: 60da str r2, [r3, #12] 8001142: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001144: 2301 movs r3, #1 8001146: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001148: f44f 3380 mov.w r3, #65536 ; 0x10000 800114c: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 800114e: 2300 movs r3, #0 8001150: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001152: 2301 movs r3, #1 8001154: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8001156: 2302 movs r3, #2 8001158: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800115a: f44f 3380 mov.w r3, #65536 ; 0x10000 800115e: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8001160: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8001164: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001166: f107 0318 add.w r3, r7, #24 800116a: 4618 mov r0, r3 800116c: f000 fdf2 bl 8001d54 8001170: 4603 mov r3, r0 8001172: 2b00 cmp r3, #0 8001174: d001 beq.n 800117a { Error_Handler(); 8001176: f000 f915 bl 80013a4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800117a: 230f movs r3, #15 800117c: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800117e: 2302 movs r3, #2 8001180: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001182: 2300 movs r3, #0 8001184: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8001186: f44f 6380 mov.w r3, #1024 ; 0x400 800118a: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800118c: 2300 movs r3, #0 800118e: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001190: 1d3b adds r3, r7, #4 8001192: 2102 movs r1, #2 8001194: 4618 mov r0, r3 8001196: f001 f85d bl 8002254 800119a: 4603 mov r3, r0 800119c: 2b00 cmp r3, #0 800119e: d001 beq.n 80011a4 { Error_Handler(); 80011a0: f000 f900 bl 80013a4 } } 80011a4: bf00 nop 80011a6: 3740 adds r7, #64 ; 0x40 80011a8: 46bd mov sp, r7 80011aa: bd80 pop {r7, pc} 080011ac : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80011ac: b580 push {r7, lr} 80011ae: b08a sub sp, #40 ; 0x28 80011b0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80011b2: f107 0318 add.w r3, r7, #24 80011b6: 2200 movs r2, #0 80011b8: 601a str r2, [r3, #0] 80011ba: 605a str r2, [r3, #4] 80011bc: 609a str r2, [r3, #8] 80011be: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80011c0: 4b43 ldr r3, [pc, #268] ; (80012d0 ) 80011c2: 699b ldr r3, [r3, #24] 80011c4: 4a42 ldr r2, [pc, #264] ; (80012d0 ) 80011c6: f043 0380 orr.w r3, r3, #128 ; 0x80 80011ca: 6193 str r3, [r2, #24] 80011cc: 4b40 ldr r3, [pc, #256] ; (80012d0 ) 80011ce: 699b ldr r3, [r3, #24] 80011d0: f003 0380 and.w r3, r3, #128 ; 0x80 80011d4: 617b str r3, [r7, #20] 80011d6: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 80011d8: 4b3d ldr r3, [pc, #244] ; (80012d0 ) 80011da: 699b ldr r3, [r3, #24] 80011dc: 4a3c ldr r2, [pc, #240] ; (80012d0 ) 80011de: f043 0308 orr.w r3, r3, #8 80011e2: 6193 str r3, [r2, #24] 80011e4: 4b3a ldr r3, [pc, #232] ; (80012d0 ) 80011e6: 699b ldr r3, [r3, #24] 80011e8: f003 0308 and.w r3, r3, #8 80011ec: 613b str r3, [r7, #16] 80011ee: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 80011f0: 4b37 ldr r3, [pc, #220] ; (80012d0 ) 80011f2: 699b ldr r3, [r3, #24] 80011f4: 4a36 ldr r2, [pc, #216] ; (80012d0 ) 80011f6: f443 7380 orr.w r3, r3, #256 ; 0x100 80011fa: 6193 str r3, [r2, #24] 80011fc: 4b34 ldr r3, [pc, #208] ; (80012d0 ) 80011fe: 699b ldr r3, [r3, #24] 8001200: f403 7380 and.w r3, r3, #256 ; 0x100 8001204: 60fb str r3, [r7, #12] 8001206: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001208: 4b31 ldr r3, [pc, #196] ; (80012d0 ) 800120a: 699b ldr r3, [r3, #24] 800120c: 4a30 ldr r2, [pc, #192] ; (80012d0 ) 800120e: f043 0340 orr.w r3, r3, #64 ; 0x40 8001212: 6193 str r3, [r2, #24] 8001214: 4b2e ldr r3, [pc, #184] ; (80012d0 ) 8001216: 699b ldr r3, [r3, #24] 8001218: f003 0340 and.w r3, r3, #64 ; 0x40 800121c: 60bb str r3, [r7, #8] 800121e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001220: 4b2b ldr r3, [pc, #172] ; (80012d0 ) 8001222: 699b ldr r3, [r3, #24] 8001224: 4a2a ldr r2, [pc, #168] ; (80012d0 ) 8001226: f043 0320 orr.w r3, r3, #32 800122a: 6193 str r3, [r2, #24] 800122c: 4b28 ldr r3, [pc, #160] ; (80012d0 ) 800122e: 699b ldr r3, [r3, #24] 8001230: f003 0320 and.w r3, r3, #32 8001234: 607b str r3, [r7, #4] 8001236: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TDIN_GPIO_Port, TDIN_Pin, GPIO_PIN_SET); 8001238: 2201 movs r2, #1 800123a: f44f 7100 mov.w r1, #512 ; 0x200 800123e: 4825 ldr r0, [pc, #148] ; (80012d4 ) 8001240: f000 fd6f bl 8001d22 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); 8001244: 2200 movs r2, #0 8001246: 2101 movs r1, #1 8001248: 4823 ldr r0, [pc, #140] ; (80012d8 ) 800124a: f000 fd6a bl 8001d22 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, TCLK_Pin|TCS_Pin, GPIO_PIN_SET); 800124e: 2201 movs r2, #1 8001250: 2106 movs r1, #6 8001252: 4821 ldr r0, [pc, #132] ; (80012d8 ) 8001254: f000 fd65 bl 8001d22 /*Configure GPIO pins : TDOUT_Pin TPEN_Pin */ GPIO_InitStruct.Pin = TDOUT_Pin|TPEN_Pin; 8001258: f44f 63a0 mov.w r3, #1280 ; 0x500 800125c: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800125e: 2300 movs r3, #0 8001260: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001262: 2300 movs r3, #0 8001264: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8001266: f107 0318 add.w r3, r7, #24 800126a: 4619 mov r1, r3 800126c: 4819 ldr r0, [pc, #100] ; (80012d4 ) 800126e: f000 fbad bl 80019cc /*Configure GPIO pin : TDIN_Pin */ GPIO_InitStruct.Pin = TDIN_Pin; 8001272: f44f 7300 mov.w r3, #512 ; 0x200 8001276: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001278: 2301 movs r3, #1 800127a: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800127c: 2300 movs r3, #0 800127e: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001280: 2303 movs r3, #3 8001282: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(TDIN_GPIO_Port, &GPIO_InitStruct); 8001284: f107 0318 add.w r3, r7, #24 8001288: 4619 mov r1, r3 800128a: 4812 ldr r0, [pc, #72] ; (80012d4 ) 800128c: f000 fb9e bl 80019cc /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 8001290: 2301 movs r3, #1 8001292: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001294: 2301 movs r3, #1 8001296: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001298: 2300 movs r3, #0 800129a: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800129c: 2302 movs r3, #2 800129e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 80012a0: f107 0318 add.w r3, r7, #24 80012a4: 4619 mov r1, r3 80012a6: 480c ldr r0, [pc, #48] ; (80012d8 ) 80012a8: f000 fb90 bl 80019cc /*Configure GPIO pins : TCLK_Pin TCS_Pin */ GPIO_InitStruct.Pin = TCLK_Pin|TCS_Pin; 80012ac: 2306 movs r3, #6 80012ae: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80012b0: 2301 movs r3, #1 80012b2: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012b4: 2300 movs r3, #0 80012b6: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80012b8: 2303 movs r3, #3 80012ba: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80012bc: f107 0318 add.w r3, r7, #24 80012c0: 4619 mov r1, r3 80012c2: 4805 ldr r0, [pc, #20] ; (80012d8 ) 80012c4: f000 fb82 bl 80019cc } 80012c8: bf00 nop 80012ca: 3728 adds r7, #40 ; 0x28 80012cc: 46bd mov sp, r7 80012ce: bd80 pop {r7, pc} 80012d0: 40021000 .word 0x40021000 80012d4: 40011c00 .word 0x40011c00 80012d8: 40010c00 .word 0x40010c00 080012dc : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 80012dc: b580 push {r7, lr} 80012de: b088 sub sp, #32 80012e0: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 80012e2: 1d3b adds r3, r7, #4 80012e4: 2200 movs r2, #0 80012e6: 601a str r2, [r3, #0] 80012e8: 605a str r2, [r3, #4] 80012ea: 609a str r2, [r3, #8] 80012ec: 60da str r2, [r3, #12] 80012ee: 611a str r2, [r3, #16] 80012f0: 615a str r2, [r3, #20] 80012f2: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 80012f4: 4b28 ldr r3, [pc, #160] ; (8001398 ) 80012f6: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 80012fa: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 80012fc: 4b26 ldr r3, [pc, #152] ; (8001398 ) 80012fe: 4a27 ldr r2, [pc, #156] ; (800139c ) 8001300: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 8001302: 4b25 ldr r3, [pc, #148] ; (8001398 ) 8001304: 2206 movs r2, #6 8001306: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 8001308: 4b23 ldr r3, [pc, #140] ; (8001398 ) 800130a: 2200 movs r2, #0 800130c: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 800130e: 4b22 ldr r3, [pc, #136] ; (8001398 ) 8001310: 2200 movs r2, #0 8001312: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 8001314: 4b20 ldr r3, [pc, #128] ; (8001398 ) 8001316: 2210 movs r2, #16 8001318: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 800131a: 4b1f ldr r3, [pc, #124] ; (8001398 ) 800131c: 2200 movs r2, #0 800131e: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 8001320: 4b1d ldr r3, [pc, #116] ; (8001398 ) 8001322: 2200 movs r2, #0 8001324: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 8001326: 4b1c ldr r3, [pc, #112] ; (8001398 ) 8001328: 2200 movs r2, #0 800132a: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 800132c: 4b1a ldr r3, [pc, #104] ; (8001398 ) 800132e: 2200 movs r2, #0 8001330: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 8001332: 4b19 ldr r3, [pc, #100] ; (8001398 ) 8001334: f44f 5280 mov.w r2, #4096 ; 0x1000 8001338: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 800133a: 4b17 ldr r3, [pc, #92] ; (8001398 ) 800133c: 2200 movs r2, #0 800133e: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 8001340: 4b15 ldr r3, [pc, #84] ; (8001398 ) 8001342: 2200 movs r2, #0 8001344: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 8001346: 4b14 ldr r3, [pc, #80] ; (8001398 ) 8001348: 2200 movs r2, #0 800134a: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 800134c: 4b12 ldr r3, [pc, #72] ; (8001398 ) 800134e: 2200 movs r2, #0 8001350: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 8001352: 2300 movs r3, #0 8001354: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 8001356: 230f movs r3, #15 8001358: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 800135a: 2301 movs r3, #1 800135c: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 0; 800135e: 2300 movs r3, #0 8001360: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 8001362: 2310 movs r3, #16 8001364: 617b str r3, [r7, #20] Timing.DataLatency = 17; 8001366: 2311 movs r3, #17 8001368: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 800136a: 2300 movs r3, #0 800136c: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 800136e: 1d3b adds r3, r7, #4 8001370: 2200 movs r2, #0 8001372: 4619 mov r1, r3 8001374: 4808 ldr r0, [pc, #32] ; (8001398 ) 8001376: f001 f8d5 bl 8002524 800137a: 4603 mov r3, r0 800137c: 2b00 cmp r3, #0 800137e: d001 beq.n 8001384 { Error_Handler( ); 8001380: f000 f810 bl 80013a4 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 8001384: 4b06 ldr r3, [pc, #24] ; (80013a0 ) 8001386: 69db ldr r3, [r3, #28] 8001388: 4a05 ldr r2, [pc, #20] ; (80013a0 ) 800138a: f443 6380 orr.w r3, r3, #1024 ; 0x400 800138e: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 8001390: bf00 nop 8001392: 3720 adds r7, #32 8001394: 46bd mov sp, r7 8001396: bd80 pop {r7, pc} 8001398: 20000208 .word 0x20000208 800139c: a0000104 .word 0xa0000104 80013a0: 40010000 .word 0x40010000 080013a4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80013a4: b480 push {r7} 80013a6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80013a8: b672 cpsid i } 80013aa: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80013ac: e7fe b.n 80013ac ... 080013b0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80013b0: b480 push {r7} 80013b2: b085 sub sp, #20 80013b4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80013b6: 4b15 ldr r3, [pc, #84] ; (800140c ) 80013b8: 699b ldr r3, [r3, #24] 80013ba: 4a14 ldr r2, [pc, #80] ; (800140c ) 80013bc: f043 0301 orr.w r3, r3, #1 80013c0: 6193 str r3, [r2, #24] 80013c2: 4b12 ldr r3, [pc, #72] ; (800140c ) 80013c4: 699b ldr r3, [r3, #24] 80013c6: f003 0301 and.w r3, r3, #1 80013ca: 60bb str r3, [r7, #8] 80013cc: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80013ce: 4b0f ldr r3, [pc, #60] ; (800140c ) 80013d0: 69db ldr r3, [r3, #28] 80013d2: 4a0e ldr r2, [pc, #56] ; (800140c ) 80013d4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80013d8: 61d3 str r3, [r2, #28] 80013da: 4b0c ldr r3, [pc, #48] ; (800140c ) 80013dc: 69db ldr r3, [r3, #28] 80013de: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80013e2: 607b str r3, [r7, #4] 80013e4: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 80013e6: 4b0a ldr r3, [pc, #40] ; (8001410 ) 80013e8: 685b ldr r3, [r3, #4] 80013ea: 60fb str r3, [r7, #12] 80013ec: 68fb ldr r3, [r7, #12] 80013ee: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80013f2: 60fb str r3, [r7, #12] 80013f4: 68fb ldr r3, [r7, #12] 80013f6: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 80013fa: 60fb str r3, [r7, #12] 80013fc: 4a04 ldr r2, [pc, #16] ; (8001410 ) 80013fe: 68fb ldr r3, [r7, #12] 8001400: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001402: bf00 nop 8001404: 3714 adds r7, #20 8001406: 46bd mov sp, r7 8001408: bc80 pop {r7} 800140a: 4770 bx lr 800140c: 40021000 .word 0x40021000 8001410: 40010000 .word 0x40010000 08001414 : static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 8001414: b580 push {r7, lr} 8001416: b086 sub sp, #24 8001418: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 800141a: f107 0308 add.w r3, r7, #8 800141e: 2200 movs r2, #0 8001420: 601a str r2, [r3, #0] 8001422: 605a str r2, [r3, #4] 8001424: 609a str r2, [r3, #8] 8001426: 60da str r2, [r3, #12] if (FSMC_Initialized) { 8001428: 4b1f ldr r3, [pc, #124] ; (80014a8 ) 800142a: 681b ldr r3, [r3, #0] 800142c: 2b00 cmp r3, #0 800142e: d136 bne.n 800149e return; } FSMC_Initialized = 1; 8001430: 4b1d ldr r3, [pc, #116] ; (80014a8 ) 8001432: 2201 movs r2, #1 8001434: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 8001436: 4b1d ldr r3, [pc, #116] ; (80014ac ) 8001438: 695b ldr r3, [r3, #20] 800143a: 4a1c ldr r2, [pc, #112] ; (80014ac ) 800143c: f443 7380 orr.w r3, r3, #256 ; 0x100 8001440: 6153 str r3, [r2, #20] 8001442: 4b1a ldr r3, [pc, #104] ; (80014ac ) 8001444: 695b ldr r3, [r3, #20] 8001446: f403 7380 and.w r3, r3, #256 ; 0x100 800144a: 607b str r3, [r7, #4] 800144c: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 800144e: f241 0301 movw r3, #4097 ; 0x1001 8001452: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001454: 2302 movs r3, #2 8001456: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001458: 2303 movs r3, #3 800145a: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800145c: f107 0308 add.w r3, r7, #8 8001460: 4619 mov r1, r3 8001462: 4813 ldr r0, [pc, #76] ; (80014b0 ) 8001464: f000 fab2 bl 80019cc GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001468: f64f 7380 movw r3, #65408 ; 0xff80 800146c: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800146e: 2302 movs r3, #2 8001470: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001472: 2303 movs r3, #3 8001474: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001476: f107 0308 add.w r3, r7, #8 800147a: 4619 mov r1, r3 800147c: 480d ldr r0, [pc, #52] ; (80014b4 ) 800147e: f000 faa5 bl 80019cc GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 8001482: f24c 7333 movw r3, #50995 ; 0xc733 8001486: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001488: 2302 movs r3, #2 800148a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800148c: 2303 movs r3, #3 800148e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001490: f107 0308 add.w r3, r7, #8 8001494: 4619 mov r1, r3 8001496: 4808 ldr r0, [pc, #32] ; (80014b8 ) 8001498: f000 fa98 bl 80019cc 800149c: e000 b.n 80014a0 return; 800149e: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 80014a0: 3718 adds r7, #24 80014a2: 46bd mov sp, r7 80014a4: bd80 pop {r7, pc} 80014a6: bf00 nop 80014a8: 200001f8 .word 0x200001f8 80014ac: 40021000 .word 0x40021000 80014b0: 40012000 .word 0x40012000 80014b4: 40011800 .word 0x40011800 80014b8: 40011400 .word 0x40011400 080014bc : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 80014bc: b580 push {r7, lr} 80014be: b082 sub sp, #8 80014c0: af00 add r7, sp, #0 80014c2: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 80014c4: f7ff ffa6 bl 8001414 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 80014c8: bf00 nop 80014ca: 3708 adds r7, #8 80014cc: 46bd mov sp, r7 80014ce: bd80 pop {r7, pc} 080014d0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80014d0: b480 push {r7} 80014d2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80014d4: e7fe b.n 80014d4 080014d6 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80014d6: b480 push {r7} 80014d8: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80014da: e7fe b.n 80014da 080014dc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80014dc: b480 push {r7} 80014de: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80014e0: e7fe b.n 80014e0 080014e2 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80014e2: b480 push {r7} 80014e4: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80014e6: e7fe b.n 80014e6 080014e8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80014e8: b480 push {r7} 80014ea: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80014ec: e7fe b.n 80014ec 080014ee : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80014ee: b480 push {r7} 80014f0: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80014f2: bf00 nop 80014f4: 46bd mov sp, r7 80014f6: bc80 pop {r7} 80014f8: 4770 bx lr 080014fa : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80014fa: b480 push {r7} 80014fc: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80014fe: bf00 nop 8001500: 46bd mov sp, r7 8001502: bc80 pop {r7} 8001504: 4770 bx lr 08001506 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001506: b480 push {r7} 8001508: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800150a: bf00 nop 800150c: 46bd mov sp, r7 800150e: bc80 pop {r7} 8001510: 4770 bx lr 08001512 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001512: b580 push {r7, lr} 8001514: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001516: f000 f935 bl 8001784 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800151a: bf00 nop 800151c: bd80 pop {r7, pc} 0800151e <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800151e: b480 push {r7} 8001520: af00 add r7, sp, #0 return 1; 8001522: 2301 movs r3, #1 } 8001524: 4618 mov r0, r3 8001526: 46bd mov sp, r7 8001528: bc80 pop {r7} 800152a: 4770 bx lr 0800152c <_kill>: int _kill(int pid, int sig) { 800152c: b580 push {r7, lr} 800152e: b082 sub sp, #8 8001530: af00 add r7, sp, #0 8001532: 6078 str r0, [r7, #4] 8001534: 6039 str r1, [r7, #0] errno = EINVAL; 8001536: f002 fe49 bl 80041cc <__errno> 800153a: 4603 mov r3, r0 800153c: 2216 movs r2, #22 800153e: 601a str r2, [r3, #0] return -1; 8001540: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001544: 4618 mov r0, r3 8001546: 3708 adds r7, #8 8001548: 46bd mov sp, r7 800154a: bd80 pop {r7, pc} 0800154c <_exit>: void _exit (int status) { 800154c: b580 push {r7, lr} 800154e: b082 sub sp, #8 8001550: af00 add r7, sp, #0 8001552: 6078 str r0, [r7, #4] _kill(status, -1); 8001554: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001558: 6878 ldr r0, [r7, #4] 800155a: f7ff ffe7 bl 800152c <_kill> while (1) {} /* Make sure we hang here */ 800155e: e7fe b.n 800155e <_exit+0x12> 08001560 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001560: b580 push {r7, lr} 8001562: b086 sub sp, #24 8001564: af00 add r7, sp, #0 8001566: 60f8 str r0, [r7, #12] 8001568: 60b9 str r1, [r7, #8] 800156a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800156c: 2300 movs r3, #0 800156e: 617b str r3, [r7, #20] 8001570: e00a b.n 8001588 <_read+0x28> { *ptr++ = __io_getchar(); 8001572: f3af 8000 nop.w 8001576: 4601 mov r1, r0 8001578: 68bb ldr r3, [r7, #8] 800157a: 1c5a adds r2, r3, #1 800157c: 60ba str r2, [r7, #8] 800157e: b2ca uxtb r2, r1 8001580: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8001582: 697b ldr r3, [r7, #20] 8001584: 3301 adds r3, #1 8001586: 617b str r3, [r7, #20] 8001588: 697a ldr r2, [r7, #20] 800158a: 687b ldr r3, [r7, #4] 800158c: 429a cmp r2, r3 800158e: dbf0 blt.n 8001572 <_read+0x12> } return len; 8001590: 687b ldr r3, [r7, #4] } 8001592: 4618 mov r0, r3 8001594: 3718 adds r7, #24 8001596: 46bd mov sp, r7 8001598: bd80 pop {r7, pc} 0800159a <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 800159a: b580 push {r7, lr} 800159c: b086 sub sp, #24 800159e: af00 add r7, sp, #0 80015a0: 60f8 str r0, [r7, #12] 80015a2: 60b9 str r1, [r7, #8] 80015a4: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80015a6: 2300 movs r3, #0 80015a8: 617b str r3, [r7, #20] 80015aa: e009 b.n 80015c0 <_write+0x26> { __io_putchar(*ptr++); 80015ac: 68bb ldr r3, [r7, #8] 80015ae: 1c5a adds r2, r3, #1 80015b0: 60ba str r2, [r7, #8] 80015b2: 781b ldrb r3, [r3, #0] 80015b4: 4618 mov r0, r3 80015b6: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 80015ba: 697b ldr r3, [r7, #20] 80015bc: 3301 adds r3, #1 80015be: 617b str r3, [r7, #20] 80015c0: 697a ldr r2, [r7, #20] 80015c2: 687b ldr r3, [r7, #4] 80015c4: 429a cmp r2, r3 80015c6: dbf1 blt.n 80015ac <_write+0x12> } return len; 80015c8: 687b ldr r3, [r7, #4] } 80015ca: 4618 mov r0, r3 80015cc: 3718 adds r7, #24 80015ce: 46bd mov sp, r7 80015d0: bd80 pop {r7, pc} 080015d2 <_close>: int _close(int file) { 80015d2: b480 push {r7} 80015d4: b083 sub sp, #12 80015d6: af00 add r7, sp, #0 80015d8: 6078 str r0, [r7, #4] return -1; 80015da: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 80015de: 4618 mov r0, r3 80015e0: 370c adds r7, #12 80015e2: 46bd mov sp, r7 80015e4: bc80 pop {r7} 80015e6: 4770 bx lr 080015e8 <_fstat>: int _fstat(int file, struct stat *st) { 80015e8: b480 push {r7} 80015ea: b083 sub sp, #12 80015ec: af00 add r7, sp, #0 80015ee: 6078 str r0, [r7, #4] 80015f0: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 80015f2: 683b ldr r3, [r7, #0] 80015f4: f44f 5200 mov.w r2, #8192 ; 0x2000 80015f8: 605a str r2, [r3, #4] return 0; 80015fa: 2300 movs r3, #0 } 80015fc: 4618 mov r0, r3 80015fe: 370c adds r7, #12 8001600: 46bd mov sp, r7 8001602: bc80 pop {r7} 8001604: 4770 bx lr 08001606 <_isatty>: int _isatty(int file) { 8001606: b480 push {r7} 8001608: b083 sub sp, #12 800160a: af00 add r7, sp, #0 800160c: 6078 str r0, [r7, #4] return 1; 800160e: 2301 movs r3, #1 } 8001610: 4618 mov r0, r3 8001612: 370c adds r7, #12 8001614: 46bd mov sp, r7 8001616: bc80 pop {r7} 8001618: 4770 bx lr 0800161a <_lseek>: int _lseek(int file, int ptr, int dir) { 800161a: b480 push {r7} 800161c: b085 sub sp, #20 800161e: af00 add r7, sp, #0 8001620: 60f8 str r0, [r7, #12] 8001622: 60b9 str r1, [r7, #8] 8001624: 607a str r2, [r7, #4] return 0; 8001626: 2300 movs r3, #0 } 8001628: 4618 mov r0, r3 800162a: 3714 adds r7, #20 800162c: 46bd mov sp, r7 800162e: bc80 pop {r7} 8001630: 4770 bx lr ... 08001634 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001634: b580 push {r7, lr} 8001636: b086 sub sp, #24 8001638: af00 add r7, sp, #0 800163a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800163c: 4a14 ldr r2, [pc, #80] ; (8001690 <_sbrk+0x5c>) 800163e: 4b15 ldr r3, [pc, #84] ; (8001694 <_sbrk+0x60>) 8001640: 1ad3 subs r3, r2, r3 8001642: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001644: 697b ldr r3, [r7, #20] 8001646: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001648: 4b13 ldr r3, [pc, #76] ; (8001698 <_sbrk+0x64>) 800164a: 681b ldr r3, [r3, #0] 800164c: 2b00 cmp r3, #0 800164e: d102 bne.n 8001656 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001650: 4b11 ldr r3, [pc, #68] ; (8001698 <_sbrk+0x64>) 8001652: 4a12 ldr r2, [pc, #72] ; (800169c <_sbrk+0x68>) 8001654: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001656: 4b10 ldr r3, [pc, #64] ; (8001698 <_sbrk+0x64>) 8001658: 681a ldr r2, [r3, #0] 800165a: 687b ldr r3, [r7, #4] 800165c: 4413 add r3, r2 800165e: 693a ldr r2, [r7, #16] 8001660: 429a cmp r2, r3 8001662: d207 bcs.n 8001674 <_sbrk+0x40> { errno = ENOMEM; 8001664: f002 fdb2 bl 80041cc <__errno> 8001668: 4603 mov r3, r0 800166a: 220c movs r2, #12 800166c: 601a str r2, [r3, #0] return (void *)-1; 800166e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8001672: e009 b.n 8001688 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8001674: 4b08 ldr r3, [pc, #32] ; (8001698 <_sbrk+0x64>) 8001676: 681b ldr r3, [r3, #0] 8001678: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800167a: 4b07 ldr r3, [pc, #28] ; (8001698 <_sbrk+0x64>) 800167c: 681a ldr r2, [r3, #0] 800167e: 687b ldr r3, [r7, #4] 8001680: 4413 add r3, r2 8001682: 4a05 ldr r2, [pc, #20] ; (8001698 <_sbrk+0x64>) 8001684: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8001686: 68fb ldr r3, [r7, #12] } 8001688: 4618 mov r0, r3 800168a: 3718 adds r7, #24 800168c: 46bd mov sp, r7 800168e: bd80 pop {r7, pc} 8001690: 20010000 .word 0x20010000 8001694: 00000400 .word 0x00000400 8001698: 200001fc .word 0x200001fc 800169c: 20000298 .word 0x20000298 080016a0 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80016a0: b480 push {r7} 80016a2: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80016a4: bf00 nop 80016a6: 46bd mov sp, r7 80016a8: bc80 pop {r7} 80016aa: 4770 bx lr 080016ac : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80016ac: 480c ldr r0, [pc, #48] ; (80016e0 ) ldr r1, =_edata 80016ae: 490d ldr r1, [pc, #52] ; (80016e4 ) ldr r2, =_sidata 80016b0: 4a0d ldr r2, [pc, #52] ; (80016e8 ) movs r3, #0 80016b2: 2300 movs r3, #0 b LoopCopyDataInit 80016b4: e002 b.n 80016bc 080016b6 : CopyDataInit: ldr r4, [r2, r3] 80016b6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80016b8: 50c4 str r4, [r0, r3] adds r3, r3, #4 80016ba: 3304 adds r3, #4 080016bc : LoopCopyDataInit: adds r4, r0, r3 80016bc: 18c4 adds r4, r0, r3 cmp r4, r1 80016be: 428c cmp r4, r1 bcc CopyDataInit 80016c0: d3f9 bcc.n 80016b6 /* Zero fill the bss segment. */ ldr r2, =_sbss 80016c2: 4a0a ldr r2, [pc, #40] ; (80016ec ) ldr r4, =_ebss 80016c4: 4c0a ldr r4, [pc, #40] ; (80016f0 ) movs r3, #0 80016c6: 2300 movs r3, #0 b LoopFillZerobss 80016c8: e001 b.n 80016ce 080016ca : FillZerobss: str r3, [r2] 80016ca: 6013 str r3, [r2, #0] adds r2, r2, #4 80016cc: 3204 adds r2, #4 080016ce : LoopFillZerobss: cmp r2, r4 80016ce: 42a2 cmp r2, r4 bcc FillZerobss 80016d0: d3fb bcc.n 80016ca /* Call the clock system intitialization function.*/ bl SystemInit 80016d2: f7ff ffe5 bl 80016a0 /* Call static constructors */ bl __libc_init_array 80016d6: f002 fd7f bl 80041d8 <__libc_init_array> /* Call the application's entry point.*/ bl main 80016da: f7ff fd15 bl 8001108

bx lr 80016de: 4770 bx lr ldr r0, =_sdata 80016e0: 20000000 .word 0x20000000 ldr r1, =_edata 80016e4: 200001dc .word 0x200001dc ldr r2, =_sidata 80016e8: 08007ebc .word 0x08007ebc ldr r2, =_sbss 80016ec: 200001dc .word 0x200001dc ldr r4, =_ebss 80016f0: 20000298 .word 0x20000298 080016f4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80016f4: e7fe b.n 80016f4 ... 080016f8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80016f8: b580 push {r7, lr} 80016fa: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80016fc: 4b08 ldr r3, [pc, #32] ; (8001720 ) 80016fe: 681b ldr r3, [r3, #0] 8001700: 4a07 ldr r2, [pc, #28] ; (8001720 ) 8001702: f043 0310 orr.w r3, r3, #16 8001706: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001708: 2003 movs r0, #3 800170a: f000 f92b bl 8001964 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800170e: 200f movs r0, #15 8001710: f000 f808 bl 8001724 /* Init the low level hardware */ HAL_MspInit(); 8001714: f7ff fe4c bl 80013b0 /* Return function status */ return HAL_OK; 8001718: 2300 movs r3, #0 } 800171a: 4618 mov r0, r3 800171c: bd80 pop {r7, pc} 800171e: bf00 nop 8001720: 40022000 .word 0x40022000 08001724 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001724: b580 push {r7, lr} 8001726: b082 sub sp, #8 8001728: af00 add r7, sp, #0 800172a: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800172c: 4b12 ldr r3, [pc, #72] ; (8001778 ) 800172e: 681a ldr r2, [r3, #0] 8001730: 4b12 ldr r3, [pc, #72] ; (800177c ) 8001732: 781b ldrb r3, [r3, #0] 8001734: 4619 mov r1, r3 8001736: f44f 737a mov.w r3, #1000 ; 0x3e8 800173a: fbb3 f3f1 udiv r3, r3, r1 800173e: fbb2 f3f3 udiv r3, r2, r3 8001742: 4618 mov r0, r3 8001744: f000 f935 bl 80019b2 8001748: 4603 mov r3, r0 800174a: 2b00 cmp r3, #0 800174c: d001 beq.n 8001752 { return HAL_ERROR; 800174e: 2301 movs r3, #1 8001750: e00e b.n 8001770 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001752: 687b ldr r3, [r7, #4] 8001754: 2b0f cmp r3, #15 8001756: d80a bhi.n 800176e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001758: 2200 movs r2, #0 800175a: 6879 ldr r1, [r7, #4] 800175c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001760: f000 f90b bl 800197a uwTickPrio = TickPriority; 8001764: 4a06 ldr r2, [pc, #24] ; (8001780 ) 8001766: 687b ldr r3, [r7, #4] 8001768: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800176a: 2300 movs r3, #0 800176c: e000 b.n 8001770 return HAL_ERROR; 800176e: 2301 movs r3, #1 } 8001770: 4618 mov r0, r3 8001772: 3708 adds r7, #8 8001774: 46bd mov sp, r7 8001776: bd80 pop {r7, pc} 8001778: 20000000 .word 0x20000000 800177c: 20000008 .word 0x20000008 8001780: 20000004 .word 0x20000004 08001784 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001784: b480 push {r7} 8001786: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001788: 4b05 ldr r3, [pc, #20] ; (80017a0 ) 800178a: 781b ldrb r3, [r3, #0] 800178c: 461a mov r2, r3 800178e: 4b05 ldr r3, [pc, #20] ; (80017a4 ) 8001790: 681b ldr r3, [r3, #0] 8001792: 4413 add r3, r2 8001794: 4a03 ldr r2, [pc, #12] ; (80017a4 ) 8001796: 6013 str r3, [r2, #0] } 8001798: bf00 nop 800179a: 46bd mov sp, r7 800179c: bc80 pop {r7} 800179e: 4770 bx lr 80017a0: 20000008 .word 0x20000008 80017a4: 20000250 .word 0x20000250 080017a8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80017a8: b480 push {r7} 80017aa: af00 add r7, sp, #0 return uwTick; 80017ac: 4b02 ldr r3, [pc, #8] ; (80017b8 ) 80017ae: 681b ldr r3, [r3, #0] } 80017b0: 4618 mov r0, r3 80017b2: 46bd mov sp, r7 80017b4: bc80 pop {r7} 80017b6: 4770 bx lr 80017b8: 20000250 .word 0x20000250 080017bc : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80017bc: b580 push {r7, lr} 80017be: b084 sub sp, #16 80017c0: af00 add r7, sp, #0 80017c2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80017c4: f7ff fff0 bl 80017a8 80017c8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80017ca: 687b ldr r3, [r7, #4] 80017cc: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80017ce: 68fb ldr r3, [r7, #12] 80017d0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80017d4: d005 beq.n 80017e2 { wait += (uint32_t)(uwTickFreq); 80017d6: 4b0a ldr r3, [pc, #40] ; (8001800 ) 80017d8: 781b ldrb r3, [r3, #0] 80017da: 461a mov r2, r3 80017dc: 68fb ldr r3, [r7, #12] 80017de: 4413 add r3, r2 80017e0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80017e2: bf00 nop 80017e4: f7ff ffe0 bl 80017a8 80017e8: 4602 mov r2, r0 80017ea: 68bb ldr r3, [r7, #8] 80017ec: 1ad3 subs r3, r2, r3 80017ee: 68fa ldr r2, [r7, #12] 80017f0: 429a cmp r2, r3 80017f2: d8f7 bhi.n 80017e4 { } } 80017f4: bf00 nop 80017f6: bf00 nop 80017f8: 3710 adds r7, #16 80017fa: 46bd mov sp, r7 80017fc: bd80 pop {r7, pc} 80017fe: bf00 nop 8001800: 20000008 .word 0x20000008 08001804 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001804: b480 push {r7} 8001806: b085 sub sp, #20 8001808: af00 add r7, sp, #0 800180a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800180c: 687b ldr r3, [r7, #4] 800180e: f003 0307 and.w r3, r3, #7 8001812: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001814: 4b0c ldr r3, [pc, #48] ; (8001848 <__NVIC_SetPriorityGrouping+0x44>) 8001816: 68db ldr r3, [r3, #12] 8001818: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800181a: 68ba ldr r2, [r7, #8] 800181c: f64f 03ff movw r3, #63743 ; 0xf8ff 8001820: 4013 ands r3, r2 8001822: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001824: 68fb ldr r3, [r7, #12] 8001826: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001828: 68bb ldr r3, [r7, #8] 800182a: 4313 orrs r3, r2 reg_value = (reg_value | 800182c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001830: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001834: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001836: 4a04 ldr r2, [pc, #16] ; (8001848 <__NVIC_SetPriorityGrouping+0x44>) 8001838: 68bb ldr r3, [r7, #8] 800183a: 60d3 str r3, [r2, #12] } 800183c: bf00 nop 800183e: 3714 adds r7, #20 8001840: 46bd mov sp, r7 8001842: bc80 pop {r7} 8001844: 4770 bx lr 8001846: bf00 nop 8001848: e000ed00 .word 0xe000ed00 0800184c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800184c: b480 push {r7} 800184e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001850: 4b04 ldr r3, [pc, #16] ; (8001864 <__NVIC_GetPriorityGrouping+0x18>) 8001852: 68db ldr r3, [r3, #12] 8001854: 0a1b lsrs r3, r3, #8 8001856: f003 0307 and.w r3, r3, #7 } 800185a: 4618 mov r0, r3 800185c: 46bd mov sp, r7 800185e: bc80 pop {r7} 8001860: 4770 bx lr 8001862: bf00 nop 8001864: e000ed00 .word 0xe000ed00 08001868 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001868: b480 push {r7} 800186a: b083 sub sp, #12 800186c: af00 add r7, sp, #0 800186e: 4603 mov r3, r0 8001870: 6039 str r1, [r7, #0] 8001872: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001874: f997 3007 ldrsb.w r3, [r7, #7] 8001878: 2b00 cmp r3, #0 800187a: db0a blt.n 8001892 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800187c: 683b ldr r3, [r7, #0] 800187e: b2da uxtb r2, r3 8001880: 490c ldr r1, [pc, #48] ; (80018b4 <__NVIC_SetPriority+0x4c>) 8001882: f997 3007 ldrsb.w r3, [r7, #7] 8001886: 0112 lsls r2, r2, #4 8001888: b2d2 uxtb r2, r2 800188a: 440b add r3, r1 800188c: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001890: e00a b.n 80018a8 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001892: 683b ldr r3, [r7, #0] 8001894: b2da uxtb r2, r3 8001896: 4908 ldr r1, [pc, #32] ; (80018b8 <__NVIC_SetPriority+0x50>) 8001898: 79fb ldrb r3, [r7, #7] 800189a: f003 030f and.w r3, r3, #15 800189e: 3b04 subs r3, #4 80018a0: 0112 lsls r2, r2, #4 80018a2: b2d2 uxtb r2, r2 80018a4: 440b add r3, r1 80018a6: 761a strb r2, [r3, #24] } 80018a8: bf00 nop 80018aa: 370c adds r7, #12 80018ac: 46bd mov sp, r7 80018ae: bc80 pop {r7} 80018b0: 4770 bx lr 80018b2: bf00 nop 80018b4: e000e100 .word 0xe000e100 80018b8: e000ed00 .word 0xe000ed00 080018bc : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80018bc: b480 push {r7} 80018be: b089 sub sp, #36 ; 0x24 80018c0: af00 add r7, sp, #0 80018c2: 60f8 str r0, [r7, #12] 80018c4: 60b9 str r1, [r7, #8] 80018c6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80018c8: 68fb ldr r3, [r7, #12] 80018ca: f003 0307 and.w r3, r3, #7 80018ce: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80018d0: 69fb ldr r3, [r7, #28] 80018d2: f1c3 0307 rsb r3, r3, #7 80018d6: 2b04 cmp r3, #4 80018d8: bf28 it cs 80018da: 2304 movcs r3, #4 80018dc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80018de: 69fb ldr r3, [r7, #28] 80018e0: 3304 adds r3, #4 80018e2: 2b06 cmp r3, #6 80018e4: d902 bls.n 80018ec 80018e6: 69fb ldr r3, [r7, #28] 80018e8: 3b03 subs r3, #3 80018ea: e000 b.n 80018ee 80018ec: 2300 movs r3, #0 80018ee: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80018f0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80018f4: 69bb ldr r3, [r7, #24] 80018f6: fa02 f303 lsl.w r3, r2, r3 80018fa: 43da mvns r2, r3 80018fc: 68bb ldr r3, [r7, #8] 80018fe: 401a ands r2, r3 8001900: 697b ldr r3, [r7, #20] 8001902: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001904: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001908: 697b ldr r3, [r7, #20] 800190a: fa01 f303 lsl.w r3, r1, r3 800190e: 43d9 mvns r1, r3 8001910: 687b ldr r3, [r7, #4] 8001912: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001914: 4313 orrs r3, r2 ); } 8001916: 4618 mov r0, r3 8001918: 3724 adds r7, #36 ; 0x24 800191a: 46bd mov sp, r7 800191c: bc80 pop {r7} 800191e: 4770 bx lr 08001920 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001920: b580 push {r7, lr} 8001922: b082 sub sp, #8 8001924: af00 add r7, sp, #0 8001926: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001928: 687b ldr r3, [r7, #4] 800192a: 3b01 subs r3, #1 800192c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001930: d301 bcc.n 8001936 { return (1UL); /* Reload value impossible */ 8001932: 2301 movs r3, #1 8001934: e00f b.n 8001956 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001936: 4a0a ldr r2, [pc, #40] ; (8001960 ) 8001938: 687b ldr r3, [r7, #4] 800193a: 3b01 subs r3, #1 800193c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800193e: 210f movs r1, #15 8001940: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001944: f7ff ff90 bl 8001868 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001948: 4b05 ldr r3, [pc, #20] ; (8001960 ) 800194a: 2200 movs r2, #0 800194c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800194e: 4b04 ldr r3, [pc, #16] ; (8001960 ) 8001950: 2207 movs r2, #7 8001952: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001954: 2300 movs r3, #0 } 8001956: 4618 mov r0, r3 8001958: 3708 adds r7, #8 800195a: 46bd mov sp, r7 800195c: bd80 pop {r7, pc} 800195e: bf00 nop 8001960: e000e010 .word 0xe000e010 08001964 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001964: b580 push {r7, lr} 8001966: b082 sub sp, #8 8001968: af00 add r7, sp, #0 800196a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800196c: 6878 ldr r0, [r7, #4] 800196e: f7ff ff49 bl 8001804 <__NVIC_SetPriorityGrouping> } 8001972: bf00 nop 8001974: 3708 adds r7, #8 8001976: 46bd mov sp, r7 8001978: bd80 pop {r7, pc} 0800197a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800197a: b580 push {r7, lr} 800197c: b086 sub sp, #24 800197e: af00 add r7, sp, #0 8001980: 4603 mov r3, r0 8001982: 60b9 str r1, [r7, #8] 8001984: 607a str r2, [r7, #4] 8001986: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001988: 2300 movs r3, #0 800198a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800198c: f7ff ff5e bl 800184c <__NVIC_GetPriorityGrouping> 8001990: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001992: 687a ldr r2, [r7, #4] 8001994: 68b9 ldr r1, [r7, #8] 8001996: 6978 ldr r0, [r7, #20] 8001998: f7ff ff90 bl 80018bc 800199c: 4602 mov r2, r0 800199e: f997 300f ldrsb.w r3, [r7, #15] 80019a2: 4611 mov r1, r2 80019a4: 4618 mov r0, r3 80019a6: f7ff ff5f bl 8001868 <__NVIC_SetPriority> } 80019aa: bf00 nop 80019ac: 3718 adds r7, #24 80019ae: 46bd mov sp, r7 80019b0: bd80 pop {r7, pc} 080019b2 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80019b2: b580 push {r7, lr} 80019b4: b082 sub sp, #8 80019b6: af00 add r7, sp, #0 80019b8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80019ba: 6878 ldr r0, [r7, #4] 80019bc: f7ff ffb0 bl 8001920 80019c0: 4603 mov r3, r0 } 80019c2: 4618 mov r0, r3 80019c4: 3708 adds r7, #8 80019c6: 46bd mov sp, r7 80019c8: bd80 pop {r7, pc} ... 080019cc : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80019cc: b480 push {r7} 80019ce: b08b sub sp, #44 ; 0x2c 80019d0: af00 add r7, sp, #0 80019d2: 6078 str r0, [r7, #4] 80019d4: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80019d6: 2300 movs r3, #0 80019d8: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80019da: 2300 movs r3, #0 80019dc: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80019de: e179 b.n 8001cd4 { /* Get the IO position */ ioposition = (0x01uL << position); 80019e0: 2201 movs r2, #1 80019e2: 6a7b ldr r3, [r7, #36] ; 0x24 80019e4: fa02 f303 lsl.w r3, r2, r3 80019e8: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80019ea: 683b ldr r3, [r7, #0] 80019ec: 681b ldr r3, [r3, #0] 80019ee: 69fa ldr r2, [r7, #28] 80019f0: 4013 ands r3, r2 80019f2: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80019f4: 69ba ldr r2, [r7, #24] 80019f6: 69fb ldr r3, [r7, #28] 80019f8: 429a cmp r2, r3 80019fa: f040 8168 bne.w 8001cce { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80019fe: 683b ldr r3, [r7, #0] 8001a00: 685b ldr r3, [r3, #4] 8001a02: 4aa0 ldr r2, [pc, #640] ; (8001c84 ) 8001a04: 4293 cmp r3, r2 8001a06: d05e beq.n 8001ac6 8001a08: 4a9e ldr r2, [pc, #632] ; (8001c84 ) 8001a0a: 4293 cmp r3, r2 8001a0c: d875 bhi.n 8001afa 8001a0e: 4a9e ldr r2, [pc, #632] ; (8001c88 ) 8001a10: 4293 cmp r3, r2 8001a12: d058 beq.n 8001ac6 8001a14: 4a9c ldr r2, [pc, #624] ; (8001c88 ) 8001a16: 4293 cmp r3, r2 8001a18: d86f bhi.n 8001afa 8001a1a: 4a9c ldr r2, [pc, #624] ; (8001c8c ) 8001a1c: 4293 cmp r3, r2 8001a1e: d052 beq.n 8001ac6 8001a20: 4a9a ldr r2, [pc, #616] ; (8001c8c ) 8001a22: 4293 cmp r3, r2 8001a24: d869 bhi.n 8001afa 8001a26: 4a9a ldr r2, [pc, #616] ; (8001c90 ) 8001a28: 4293 cmp r3, r2 8001a2a: d04c beq.n 8001ac6 8001a2c: 4a98 ldr r2, [pc, #608] ; (8001c90 ) 8001a2e: 4293 cmp r3, r2 8001a30: d863 bhi.n 8001afa 8001a32: 4a98 ldr r2, [pc, #608] ; (8001c94 ) 8001a34: 4293 cmp r3, r2 8001a36: d046 beq.n 8001ac6 8001a38: 4a96 ldr r2, [pc, #600] ; (8001c94 ) 8001a3a: 4293 cmp r3, r2 8001a3c: d85d bhi.n 8001afa 8001a3e: 2b12 cmp r3, #18 8001a40: d82a bhi.n 8001a98 8001a42: 2b12 cmp r3, #18 8001a44: d859 bhi.n 8001afa 8001a46: a201 add r2, pc, #4 ; (adr r2, 8001a4c ) 8001a48: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001a4c: 08001ac7 .word 0x08001ac7 8001a50: 08001aa1 .word 0x08001aa1 8001a54: 08001ab3 .word 0x08001ab3 8001a58: 08001af5 .word 0x08001af5 8001a5c: 08001afb .word 0x08001afb 8001a60: 08001afb .word 0x08001afb 8001a64: 08001afb .word 0x08001afb 8001a68: 08001afb .word 0x08001afb 8001a6c: 08001afb .word 0x08001afb 8001a70: 08001afb .word 0x08001afb 8001a74: 08001afb .word 0x08001afb 8001a78: 08001afb .word 0x08001afb 8001a7c: 08001afb .word 0x08001afb 8001a80: 08001afb .word 0x08001afb 8001a84: 08001afb .word 0x08001afb 8001a88: 08001afb .word 0x08001afb 8001a8c: 08001afb .word 0x08001afb 8001a90: 08001aa9 .word 0x08001aa9 8001a94: 08001abd .word 0x08001abd 8001a98: 4a7f ldr r2, [pc, #508] ; (8001c98 ) 8001a9a: 4293 cmp r3, r2 8001a9c: d013 beq.n 8001ac6 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001a9e: e02c b.n 8001afa config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001aa0: 683b ldr r3, [r7, #0] 8001aa2: 68db ldr r3, [r3, #12] 8001aa4: 623b str r3, [r7, #32] break; 8001aa6: e029 b.n 8001afc config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8001aa8: 683b ldr r3, [r7, #0] 8001aaa: 68db ldr r3, [r3, #12] 8001aac: 3304 adds r3, #4 8001aae: 623b str r3, [r7, #32] break; 8001ab0: e024 b.n 8001afc config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001ab2: 683b ldr r3, [r7, #0] 8001ab4: 68db ldr r3, [r3, #12] 8001ab6: 3308 adds r3, #8 8001ab8: 623b str r3, [r7, #32] break; 8001aba: e01f b.n 8001afc config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001abc: 683b ldr r3, [r7, #0] 8001abe: 68db ldr r3, [r3, #12] 8001ac0: 330c adds r3, #12 8001ac2: 623b str r3, [r7, #32] break; 8001ac4: e01a b.n 8001afc if (GPIO_Init->Pull == GPIO_NOPULL) 8001ac6: 683b ldr r3, [r7, #0] 8001ac8: 689b ldr r3, [r3, #8] 8001aca: 2b00 cmp r3, #0 8001acc: d102 bne.n 8001ad4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001ace: 2304 movs r3, #4 8001ad0: 623b str r3, [r7, #32] break; 8001ad2: e013 b.n 8001afc else if (GPIO_Init->Pull == GPIO_PULLUP) 8001ad4: 683b ldr r3, [r7, #0] 8001ad6: 689b ldr r3, [r3, #8] 8001ad8: 2b01 cmp r3, #1 8001ada: d105 bne.n 8001ae8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001adc: 2308 movs r3, #8 8001ade: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001ae0: 687b ldr r3, [r7, #4] 8001ae2: 69fa ldr r2, [r7, #28] 8001ae4: 611a str r2, [r3, #16] break; 8001ae6: e009 b.n 8001afc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001ae8: 2308 movs r3, #8 8001aea: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001aec: 687b ldr r3, [r7, #4] 8001aee: 69fa ldr r2, [r7, #28] 8001af0: 615a str r2, [r3, #20] break; 8001af2: e003 b.n 8001afc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8001af4: 2300 movs r3, #0 8001af6: 623b str r3, [r7, #32] break; 8001af8: e000 b.n 8001afc break; 8001afa: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001afc: 69bb ldr r3, [r7, #24] 8001afe: 2bff cmp r3, #255 ; 0xff 8001b00: d801 bhi.n 8001b06 8001b02: 687b ldr r3, [r7, #4] 8001b04: e001 b.n 8001b0a 8001b06: 687b ldr r3, [r7, #4] 8001b08: 3304 adds r3, #4 8001b0a: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001b0c: 69bb ldr r3, [r7, #24] 8001b0e: 2bff cmp r3, #255 ; 0xff 8001b10: d802 bhi.n 8001b18 8001b12: 6a7b ldr r3, [r7, #36] ; 0x24 8001b14: 009b lsls r3, r3, #2 8001b16: e002 b.n 8001b1e 8001b18: 6a7b ldr r3, [r7, #36] ; 0x24 8001b1a: 3b08 subs r3, #8 8001b1c: 009b lsls r3, r3, #2 8001b1e: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001b20: 697b ldr r3, [r7, #20] 8001b22: 681a ldr r2, [r3, #0] 8001b24: 210f movs r1, #15 8001b26: 693b ldr r3, [r7, #16] 8001b28: fa01 f303 lsl.w r3, r1, r3 8001b2c: 43db mvns r3, r3 8001b2e: 401a ands r2, r3 8001b30: 6a39 ldr r1, [r7, #32] 8001b32: 693b ldr r3, [r7, #16] 8001b34: fa01 f303 lsl.w r3, r1, r3 8001b38: 431a orrs r2, r3 8001b3a: 697b ldr r3, [r7, #20] 8001b3c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001b3e: 683b ldr r3, [r7, #0] 8001b40: 685b ldr r3, [r3, #4] 8001b42: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001b46: 2b00 cmp r3, #0 8001b48: f000 80c1 beq.w 8001cce { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001b4c: 4b53 ldr r3, [pc, #332] ; (8001c9c ) 8001b4e: 699b ldr r3, [r3, #24] 8001b50: 4a52 ldr r2, [pc, #328] ; (8001c9c ) 8001b52: f043 0301 orr.w r3, r3, #1 8001b56: 6193 str r3, [r2, #24] 8001b58: 4b50 ldr r3, [pc, #320] ; (8001c9c ) 8001b5a: 699b ldr r3, [r3, #24] 8001b5c: f003 0301 and.w r3, r3, #1 8001b60: 60bb str r3, [r7, #8] 8001b62: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001b64: 4a4e ldr r2, [pc, #312] ; (8001ca0 ) 8001b66: 6a7b ldr r3, [r7, #36] ; 0x24 8001b68: 089b lsrs r3, r3, #2 8001b6a: 3302 adds r3, #2 8001b6c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001b70: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001b72: 6a7b ldr r3, [r7, #36] ; 0x24 8001b74: f003 0303 and.w r3, r3, #3 8001b78: 009b lsls r3, r3, #2 8001b7a: 220f movs r2, #15 8001b7c: fa02 f303 lsl.w r3, r2, r3 8001b80: 43db mvns r3, r3 8001b82: 68fa ldr r2, [r7, #12] 8001b84: 4013 ands r3, r2 8001b86: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8001b88: 687b ldr r3, [r7, #4] 8001b8a: 4a46 ldr r2, [pc, #280] ; (8001ca4 ) 8001b8c: 4293 cmp r3, r2 8001b8e: d01f beq.n 8001bd0 8001b90: 687b ldr r3, [r7, #4] 8001b92: 4a45 ldr r2, [pc, #276] ; (8001ca8 ) 8001b94: 4293 cmp r3, r2 8001b96: d019 beq.n 8001bcc 8001b98: 687b ldr r3, [r7, #4] 8001b9a: 4a44 ldr r2, [pc, #272] ; (8001cac ) 8001b9c: 4293 cmp r3, r2 8001b9e: d013 beq.n 8001bc8 8001ba0: 687b ldr r3, [r7, #4] 8001ba2: 4a43 ldr r2, [pc, #268] ; (8001cb0 ) 8001ba4: 4293 cmp r3, r2 8001ba6: d00d beq.n 8001bc4 8001ba8: 687b ldr r3, [r7, #4] 8001baa: 4a42 ldr r2, [pc, #264] ; (8001cb4 ) 8001bac: 4293 cmp r3, r2 8001bae: d007 beq.n 8001bc0 8001bb0: 687b ldr r3, [r7, #4] 8001bb2: 4a41 ldr r2, [pc, #260] ; (8001cb8 ) 8001bb4: 4293 cmp r3, r2 8001bb6: d101 bne.n 8001bbc 8001bb8: 2305 movs r3, #5 8001bba: e00a b.n 8001bd2 8001bbc: 2306 movs r3, #6 8001bbe: e008 b.n 8001bd2 8001bc0: 2304 movs r3, #4 8001bc2: e006 b.n 8001bd2 8001bc4: 2303 movs r3, #3 8001bc6: e004 b.n 8001bd2 8001bc8: 2302 movs r3, #2 8001bca: e002 b.n 8001bd2 8001bcc: 2301 movs r3, #1 8001bce: e000 b.n 8001bd2 8001bd0: 2300 movs r3, #0 8001bd2: 6a7a ldr r2, [r7, #36] ; 0x24 8001bd4: f002 0203 and.w r2, r2, #3 8001bd8: 0092 lsls r2, r2, #2 8001bda: 4093 lsls r3, r2 8001bdc: 68fa ldr r2, [r7, #12] 8001bde: 4313 orrs r3, r2 8001be0: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001be2: 492f ldr r1, [pc, #188] ; (8001ca0 ) 8001be4: 6a7b ldr r3, [r7, #36] ; 0x24 8001be6: 089b lsrs r3, r3, #2 8001be8: 3302 adds r3, #2 8001bea: 68fa ldr r2, [r7, #12] 8001bec: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8001bf0: 683b ldr r3, [r7, #0] 8001bf2: 685b ldr r3, [r3, #4] 8001bf4: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001bf8: 2b00 cmp r3, #0 8001bfa: d006 beq.n 8001c0a { SET_BIT(EXTI->IMR, iocurrent); 8001bfc: 4b2f ldr r3, [pc, #188] ; (8001cbc ) 8001bfe: 681a ldr r2, [r3, #0] 8001c00: 492e ldr r1, [pc, #184] ; (8001cbc ) 8001c02: 69bb ldr r3, [r7, #24] 8001c04: 4313 orrs r3, r2 8001c06: 600b str r3, [r1, #0] 8001c08: e006 b.n 8001c18 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8001c0a: 4b2c ldr r3, [pc, #176] ; (8001cbc ) 8001c0c: 681a ldr r2, [r3, #0] 8001c0e: 69bb ldr r3, [r7, #24] 8001c10: 43db mvns r3, r3 8001c12: 492a ldr r1, [pc, #168] ; (8001cbc ) 8001c14: 4013 ands r3, r2 8001c16: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8001c18: 683b ldr r3, [r7, #0] 8001c1a: 685b ldr r3, [r3, #4] 8001c1c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001c20: 2b00 cmp r3, #0 8001c22: d006 beq.n 8001c32 { SET_BIT(EXTI->EMR, iocurrent); 8001c24: 4b25 ldr r3, [pc, #148] ; (8001cbc ) 8001c26: 685a ldr r2, [r3, #4] 8001c28: 4924 ldr r1, [pc, #144] ; (8001cbc ) 8001c2a: 69bb ldr r3, [r7, #24] 8001c2c: 4313 orrs r3, r2 8001c2e: 604b str r3, [r1, #4] 8001c30: e006 b.n 8001c40 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8001c32: 4b22 ldr r3, [pc, #136] ; (8001cbc ) 8001c34: 685a ldr r2, [r3, #4] 8001c36: 69bb ldr r3, [r7, #24] 8001c38: 43db mvns r3, r3 8001c3a: 4920 ldr r1, [pc, #128] ; (8001cbc ) 8001c3c: 4013 ands r3, r2 8001c3e: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001c40: 683b ldr r3, [r7, #0] 8001c42: 685b ldr r3, [r3, #4] 8001c44: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001c48: 2b00 cmp r3, #0 8001c4a: d006 beq.n 8001c5a { SET_BIT(EXTI->RTSR, iocurrent); 8001c4c: 4b1b ldr r3, [pc, #108] ; (8001cbc ) 8001c4e: 689a ldr r2, [r3, #8] 8001c50: 491a ldr r1, [pc, #104] ; (8001cbc ) 8001c52: 69bb ldr r3, [r7, #24] 8001c54: 4313 orrs r3, r2 8001c56: 608b str r3, [r1, #8] 8001c58: e006 b.n 8001c68 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8001c5a: 4b18 ldr r3, [pc, #96] ; (8001cbc ) 8001c5c: 689a ldr r2, [r3, #8] 8001c5e: 69bb ldr r3, [r7, #24] 8001c60: 43db mvns r3, r3 8001c62: 4916 ldr r1, [pc, #88] ; (8001cbc ) 8001c64: 4013 ands r3, r2 8001c66: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8001c68: 683b ldr r3, [r7, #0] 8001c6a: 685b ldr r3, [r3, #4] 8001c6c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001c70: 2b00 cmp r3, #0 8001c72: d025 beq.n 8001cc0 { SET_BIT(EXTI->FTSR, iocurrent); 8001c74: 4b11 ldr r3, [pc, #68] ; (8001cbc ) 8001c76: 68da ldr r2, [r3, #12] 8001c78: 4910 ldr r1, [pc, #64] ; (8001cbc ) 8001c7a: 69bb ldr r3, [r7, #24] 8001c7c: 4313 orrs r3, r2 8001c7e: 60cb str r3, [r1, #12] 8001c80: e025 b.n 8001cce 8001c82: bf00 nop 8001c84: 10320000 .word 0x10320000 8001c88: 10310000 .word 0x10310000 8001c8c: 10220000 .word 0x10220000 8001c90: 10210000 .word 0x10210000 8001c94: 10120000 .word 0x10120000 8001c98: 10110000 .word 0x10110000 8001c9c: 40021000 .word 0x40021000 8001ca0: 40010000 .word 0x40010000 8001ca4: 40010800 .word 0x40010800 8001ca8: 40010c00 .word 0x40010c00 8001cac: 40011000 .word 0x40011000 8001cb0: 40011400 .word 0x40011400 8001cb4: 40011800 .word 0x40011800 8001cb8: 40011c00 .word 0x40011c00 8001cbc: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001cc0: 4b0b ldr r3, [pc, #44] ; (8001cf0 ) 8001cc2: 68da ldr r2, [r3, #12] 8001cc4: 69bb ldr r3, [r7, #24] 8001cc6: 43db mvns r3, r3 8001cc8: 4909 ldr r1, [pc, #36] ; (8001cf0 ) 8001cca: 4013 ands r3, r2 8001ccc: 60cb str r3, [r1, #12] } } } position++; 8001cce: 6a7b ldr r3, [r7, #36] ; 0x24 8001cd0: 3301 adds r3, #1 8001cd2: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8001cd4: 683b ldr r3, [r7, #0] 8001cd6: 681a ldr r2, [r3, #0] 8001cd8: 6a7b ldr r3, [r7, #36] ; 0x24 8001cda: fa22 f303 lsr.w r3, r2, r3 8001cde: 2b00 cmp r3, #0 8001ce0: f47f ae7e bne.w 80019e0 } } 8001ce4: bf00 nop 8001ce6: bf00 nop 8001ce8: 372c adds r7, #44 ; 0x2c 8001cea: 46bd mov sp, r7 8001cec: bc80 pop {r7} 8001cee: 4770 bx lr 8001cf0: 40010400 .word 0x40010400 08001cf4 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001cf4: b480 push {r7} 8001cf6: b085 sub sp, #20 8001cf8: af00 add r7, sp, #0 8001cfa: 6078 str r0, [r7, #4] 8001cfc: 460b mov r3, r1 8001cfe: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001d00: 687b ldr r3, [r7, #4] 8001d02: 689a ldr r2, [r3, #8] 8001d04: 887b ldrh r3, [r7, #2] 8001d06: 4013 ands r3, r2 8001d08: 2b00 cmp r3, #0 8001d0a: d002 beq.n 8001d12 { bitstatus = GPIO_PIN_SET; 8001d0c: 2301 movs r3, #1 8001d0e: 73fb strb r3, [r7, #15] 8001d10: e001 b.n 8001d16 } else { bitstatus = GPIO_PIN_RESET; 8001d12: 2300 movs r3, #0 8001d14: 73fb strb r3, [r7, #15] } return bitstatus; 8001d16: 7bfb ldrb r3, [r7, #15] } 8001d18: 4618 mov r0, r3 8001d1a: 3714 adds r7, #20 8001d1c: 46bd mov sp, r7 8001d1e: bc80 pop {r7} 8001d20: 4770 bx lr 08001d22 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001d22: b480 push {r7} 8001d24: b083 sub sp, #12 8001d26: af00 add r7, sp, #0 8001d28: 6078 str r0, [r7, #4] 8001d2a: 460b mov r3, r1 8001d2c: 807b strh r3, [r7, #2] 8001d2e: 4613 mov r3, r2 8001d30: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001d32: 787b ldrb r3, [r7, #1] 8001d34: 2b00 cmp r3, #0 8001d36: d003 beq.n 8001d40 { GPIOx->BSRR = GPIO_Pin; 8001d38: 887a ldrh r2, [r7, #2] 8001d3a: 687b ldr r3, [r7, #4] 8001d3c: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8001d3e: e003 b.n 8001d48 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8001d40: 887b ldrh r3, [r7, #2] 8001d42: 041a lsls r2, r3, #16 8001d44: 687b ldr r3, [r7, #4] 8001d46: 611a str r2, [r3, #16] } 8001d48: bf00 nop 8001d4a: 370c adds r7, #12 8001d4c: 46bd mov sp, r7 8001d4e: bc80 pop {r7} 8001d50: 4770 bx lr ... 08001d54 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001d54: b580 push {r7, lr} 8001d56: b086 sub sp, #24 8001d58: af00 add r7, sp, #0 8001d5a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: 2b00 cmp r3, #0 8001d60: d101 bne.n 8001d66 { return HAL_ERROR; 8001d62: 2301 movs r3, #1 8001d64: e26c b.n 8002240 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8001d66: 687b ldr r3, [r7, #4] 8001d68: 681b ldr r3, [r3, #0] 8001d6a: f003 0301 and.w r3, r3, #1 8001d6e: 2b00 cmp r3, #0 8001d70: f000 8087 beq.w 8001e82 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8001d74: 4b92 ldr r3, [pc, #584] ; (8001fc0 ) 8001d76: 685b ldr r3, [r3, #4] 8001d78: f003 030c and.w r3, r3, #12 8001d7c: 2b04 cmp r3, #4 8001d7e: d00c beq.n 8001d9a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001d80: 4b8f ldr r3, [pc, #572] ; (8001fc0 ) 8001d82: 685b ldr r3, [r3, #4] 8001d84: f003 030c and.w r3, r3, #12 8001d88: 2b08 cmp r3, #8 8001d8a: d112 bne.n 8001db2 8001d8c: 4b8c ldr r3, [pc, #560] ; (8001fc0 ) 8001d8e: 685b ldr r3, [r3, #4] 8001d90: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001d94: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8001d98: d10b bne.n 8001db2 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001d9a: 4b89 ldr r3, [pc, #548] ; (8001fc0 ) 8001d9c: 681b ldr r3, [r3, #0] 8001d9e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001da2: 2b00 cmp r3, #0 8001da4: d06c beq.n 8001e80 8001da6: 687b ldr r3, [r7, #4] 8001da8: 685b ldr r3, [r3, #4] 8001daa: 2b00 cmp r3, #0 8001dac: d168 bne.n 8001e80 { return HAL_ERROR; 8001dae: 2301 movs r3, #1 8001db0: e246 b.n 8002240 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001db2: 687b ldr r3, [r7, #4] 8001db4: 685b ldr r3, [r3, #4] 8001db6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8001dba: d106 bne.n 8001dca 8001dbc: 4b80 ldr r3, [pc, #512] ; (8001fc0 ) 8001dbe: 681b ldr r3, [r3, #0] 8001dc0: 4a7f ldr r2, [pc, #508] ; (8001fc0 ) 8001dc2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8001dc6: 6013 str r3, [r2, #0] 8001dc8: e02e b.n 8001e28 8001dca: 687b ldr r3, [r7, #4] 8001dcc: 685b ldr r3, [r3, #4] 8001dce: 2b00 cmp r3, #0 8001dd0: d10c bne.n 8001dec 8001dd2: 4b7b ldr r3, [pc, #492] ; (8001fc0 ) 8001dd4: 681b ldr r3, [r3, #0] 8001dd6: 4a7a ldr r2, [pc, #488] ; (8001fc0 ) 8001dd8: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001ddc: 6013 str r3, [r2, #0] 8001dde: 4b78 ldr r3, [pc, #480] ; (8001fc0 ) 8001de0: 681b ldr r3, [r3, #0] 8001de2: 4a77 ldr r2, [pc, #476] ; (8001fc0 ) 8001de4: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8001de8: 6013 str r3, [r2, #0] 8001dea: e01d b.n 8001e28 8001dec: 687b ldr r3, [r7, #4] 8001dee: 685b ldr r3, [r3, #4] 8001df0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8001df4: d10c bne.n 8001e10 8001df6: 4b72 ldr r3, [pc, #456] ; (8001fc0 ) 8001df8: 681b ldr r3, [r3, #0] 8001dfa: 4a71 ldr r2, [pc, #452] ; (8001fc0 ) 8001dfc: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8001e00: 6013 str r3, [r2, #0] 8001e02: 4b6f ldr r3, [pc, #444] ; (8001fc0 ) 8001e04: 681b ldr r3, [r3, #0] 8001e06: 4a6e ldr r2, [pc, #440] ; (8001fc0 ) 8001e08: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8001e0c: 6013 str r3, [r2, #0] 8001e0e: e00b b.n 8001e28 8001e10: 4b6b ldr r3, [pc, #428] ; (8001fc0 ) 8001e12: 681b ldr r3, [r3, #0] 8001e14: 4a6a ldr r2, [pc, #424] ; (8001fc0 ) 8001e16: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001e1a: 6013 str r3, [r2, #0] 8001e1c: 4b68 ldr r3, [pc, #416] ; (8001fc0 ) 8001e1e: 681b ldr r3, [r3, #0] 8001e20: 4a67 ldr r2, [pc, #412] ; (8001fc0 ) 8001e22: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8001e26: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001e28: 687b ldr r3, [r7, #4] 8001e2a: 685b ldr r3, [r3, #4] 8001e2c: 2b00 cmp r3, #0 8001e2e: d013 beq.n 8001e58 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e30: f7ff fcba bl 80017a8 8001e34: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001e36: e008 b.n 8001e4a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001e38: f7ff fcb6 bl 80017a8 8001e3c: 4602 mov r2, r0 8001e3e: 693b ldr r3, [r7, #16] 8001e40: 1ad3 subs r3, r2, r3 8001e42: 2b64 cmp r3, #100 ; 0x64 8001e44: d901 bls.n 8001e4a { return HAL_TIMEOUT; 8001e46: 2303 movs r3, #3 8001e48: e1fa b.n 8002240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001e4a: 4b5d ldr r3, [pc, #372] ; (8001fc0 ) 8001e4c: 681b ldr r3, [r3, #0] 8001e4e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001e52: 2b00 cmp r3, #0 8001e54: d0f0 beq.n 8001e38 8001e56: e014 b.n 8001e82 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e58: f7ff fca6 bl 80017a8 8001e5c: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001e5e: e008 b.n 8001e72 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001e60: f7ff fca2 bl 80017a8 8001e64: 4602 mov r2, r0 8001e66: 693b ldr r3, [r7, #16] 8001e68: 1ad3 subs r3, r2, r3 8001e6a: 2b64 cmp r3, #100 ; 0x64 8001e6c: d901 bls.n 8001e72 { return HAL_TIMEOUT; 8001e6e: 2303 movs r3, #3 8001e70: e1e6 b.n 8002240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001e72: 4b53 ldr r3, [pc, #332] ; (8001fc0 ) 8001e74: 681b ldr r3, [r3, #0] 8001e76: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001e7a: 2b00 cmp r3, #0 8001e7c: d1f0 bne.n 8001e60 8001e7e: e000 b.n 8001e82 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001e80: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001e82: 687b ldr r3, [r7, #4] 8001e84: 681b ldr r3, [r3, #0] 8001e86: f003 0302 and.w r3, r3, #2 8001e8a: 2b00 cmp r3, #0 8001e8c: d063 beq.n 8001f56 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001e8e: 4b4c ldr r3, [pc, #304] ; (8001fc0 ) 8001e90: 685b ldr r3, [r3, #4] 8001e92: f003 030c and.w r3, r3, #12 8001e96: 2b00 cmp r3, #0 8001e98: d00b beq.n 8001eb2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8001e9a: 4b49 ldr r3, [pc, #292] ; (8001fc0 ) 8001e9c: 685b ldr r3, [r3, #4] 8001e9e: f003 030c and.w r3, r3, #12 8001ea2: 2b08 cmp r3, #8 8001ea4: d11c bne.n 8001ee0 8001ea6: 4b46 ldr r3, [pc, #280] ; (8001fc0 ) 8001ea8: 685b ldr r3, [r3, #4] 8001eaa: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001eae: 2b00 cmp r3, #0 8001eb0: d116 bne.n 8001ee0 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001eb2: 4b43 ldr r3, [pc, #268] ; (8001fc0 ) 8001eb4: 681b ldr r3, [r3, #0] 8001eb6: f003 0302 and.w r3, r3, #2 8001eba: 2b00 cmp r3, #0 8001ebc: d005 beq.n 8001eca 8001ebe: 687b ldr r3, [r7, #4] 8001ec0: 691b ldr r3, [r3, #16] 8001ec2: 2b01 cmp r3, #1 8001ec4: d001 beq.n 8001eca { return HAL_ERROR; 8001ec6: 2301 movs r3, #1 8001ec8: e1ba b.n 8002240 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001eca: 4b3d ldr r3, [pc, #244] ; (8001fc0 ) 8001ecc: 681b ldr r3, [r3, #0] 8001ece: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8001ed2: 687b ldr r3, [r7, #4] 8001ed4: 695b ldr r3, [r3, #20] 8001ed6: 00db lsls r3, r3, #3 8001ed8: 4939 ldr r1, [pc, #228] ; (8001fc0 ) 8001eda: 4313 orrs r3, r2 8001edc: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001ede: e03a b.n 8001f56 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001ee0: 687b ldr r3, [r7, #4] 8001ee2: 691b ldr r3, [r3, #16] 8001ee4: 2b00 cmp r3, #0 8001ee6: d020 beq.n 8001f2a { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001ee8: 4b36 ldr r3, [pc, #216] ; (8001fc4 ) 8001eea: 2201 movs r2, #1 8001eec: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001eee: f7ff fc5b bl 80017a8 8001ef2: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001ef4: e008 b.n 8001f08 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8001ef6: f7ff fc57 bl 80017a8 8001efa: 4602 mov r2, r0 8001efc: 693b ldr r3, [r7, #16] 8001efe: 1ad3 subs r3, r2, r3 8001f00: 2b02 cmp r3, #2 8001f02: d901 bls.n 8001f08 { return HAL_TIMEOUT; 8001f04: 2303 movs r3, #3 8001f06: e19b b.n 8002240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001f08: 4b2d ldr r3, [pc, #180] ; (8001fc0 ) 8001f0a: 681b ldr r3, [r3, #0] 8001f0c: f003 0302 and.w r3, r3, #2 8001f10: 2b00 cmp r3, #0 8001f12: d0f0 beq.n 8001ef6 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001f14: 4b2a ldr r3, [pc, #168] ; (8001fc0 ) 8001f16: 681b ldr r3, [r3, #0] 8001f18: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8001f1c: 687b ldr r3, [r7, #4] 8001f1e: 695b ldr r3, [r3, #20] 8001f20: 00db lsls r3, r3, #3 8001f22: 4927 ldr r1, [pc, #156] ; (8001fc0 ) 8001f24: 4313 orrs r3, r2 8001f26: 600b str r3, [r1, #0] 8001f28: e015 b.n 8001f56 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001f2a: 4b26 ldr r3, [pc, #152] ; (8001fc4 ) 8001f2c: 2200 movs r2, #0 8001f2e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001f30: f7ff fc3a bl 80017a8 8001f34: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001f36: e008 b.n 8001f4a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8001f38: f7ff fc36 bl 80017a8 8001f3c: 4602 mov r2, r0 8001f3e: 693b ldr r3, [r7, #16] 8001f40: 1ad3 subs r3, r2, r3 8001f42: 2b02 cmp r3, #2 8001f44: d901 bls.n 8001f4a { return HAL_TIMEOUT; 8001f46: 2303 movs r3, #3 8001f48: e17a b.n 8002240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001f4a: 4b1d ldr r3, [pc, #116] ; (8001fc0 ) 8001f4c: 681b ldr r3, [r3, #0] 8001f4e: f003 0302 and.w r3, r3, #2 8001f52: 2b00 cmp r3, #0 8001f54: d1f0 bne.n 8001f38 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001f56: 687b ldr r3, [r7, #4] 8001f58: 681b ldr r3, [r3, #0] 8001f5a: f003 0308 and.w r3, r3, #8 8001f5e: 2b00 cmp r3, #0 8001f60: d03a beq.n 8001fd8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001f62: 687b ldr r3, [r7, #4] 8001f64: 699b ldr r3, [r3, #24] 8001f66: 2b00 cmp r3, #0 8001f68: d019 beq.n 8001f9e { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001f6a: 4b17 ldr r3, [pc, #92] ; (8001fc8 ) 8001f6c: 2201 movs r2, #1 8001f6e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001f70: f7ff fc1a bl 80017a8 8001f74: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001f76: e008 b.n 8001f8a { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001f78: f7ff fc16 bl 80017a8 8001f7c: 4602 mov r2, r0 8001f7e: 693b ldr r3, [r7, #16] 8001f80: 1ad3 subs r3, r2, r3 8001f82: 2b02 cmp r3, #2 8001f84: d901 bls.n 8001f8a { return HAL_TIMEOUT; 8001f86: 2303 movs r3, #3 8001f88: e15a b.n 8002240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001f8a: 4b0d ldr r3, [pc, #52] ; (8001fc0 ) 8001f8c: 6a5b ldr r3, [r3, #36] ; 0x24 8001f8e: f003 0302 and.w r3, r3, #2 8001f92: 2b00 cmp r3, #0 8001f94: d0f0 beq.n 8001f78 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8001f96: 2001 movs r0, #1 8001f98: f000 faa6 bl 80024e8 8001f9c: e01c b.n 8001fd8 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001f9e: 4b0a ldr r3, [pc, #40] ; (8001fc8 ) 8001fa0: 2200 movs r2, #0 8001fa2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001fa4: f7ff fc00 bl 80017a8 8001fa8: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001faa: e00f b.n 8001fcc { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001fac: f7ff fbfc bl 80017a8 8001fb0: 4602 mov r2, r0 8001fb2: 693b ldr r3, [r7, #16] 8001fb4: 1ad3 subs r3, r2, r3 8001fb6: 2b02 cmp r3, #2 8001fb8: d908 bls.n 8001fcc { return HAL_TIMEOUT; 8001fba: 2303 movs r3, #3 8001fbc: e140 b.n 8002240 8001fbe: bf00 nop 8001fc0: 40021000 .word 0x40021000 8001fc4: 42420000 .word 0x42420000 8001fc8: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001fcc: 4b9e ldr r3, [pc, #632] ; (8002248 ) 8001fce: 6a5b ldr r3, [r3, #36] ; 0x24 8001fd0: f003 0302 and.w r3, r3, #2 8001fd4: 2b00 cmp r3, #0 8001fd6: d1e9 bne.n 8001fac } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001fd8: 687b ldr r3, [r7, #4] 8001fda: 681b ldr r3, [r3, #0] 8001fdc: f003 0304 and.w r3, r3, #4 8001fe0: 2b00 cmp r3, #0 8001fe2: f000 80a6 beq.w 8002132 { FlagStatus pwrclkchanged = RESET; 8001fe6: 2300 movs r3, #0 8001fe8: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001fea: 4b97 ldr r3, [pc, #604] ; (8002248 ) 8001fec: 69db ldr r3, [r3, #28] 8001fee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001ff2: 2b00 cmp r3, #0 8001ff4: d10d bne.n 8002012 { __HAL_RCC_PWR_CLK_ENABLE(); 8001ff6: 4b94 ldr r3, [pc, #592] ; (8002248 ) 8001ff8: 69db ldr r3, [r3, #28] 8001ffa: 4a93 ldr r2, [pc, #588] ; (8002248 ) 8001ffc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8002000: 61d3 str r3, [r2, #28] 8002002: 4b91 ldr r3, [pc, #580] ; (8002248 ) 8002004: 69db ldr r3, [r3, #28] 8002006: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800200a: 60bb str r3, [r7, #8] 800200c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800200e: 2301 movs r3, #1 8002010: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002012: 4b8e ldr r3, [pc, #568] ; (800224c ) 8002014: 681b ldr r3, [r3, #0] 8002016: f403 7380 and.w r3, r3, #256 ; 0x100 800201a: 2b00 cmp r3, #0 800201c: d118 bne.n 8002050 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800201e: 4b8b ldr r3, [pc, #556] ; (800224c ) 8002020: 681b ldr r3, [r3, #0] 8002022: 4a8a ldr r2, [pc, #552] ; (800224c ) 8002024: f443 7380 orr.w r3, r3, #256 ; 0x100 8002028: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800202a: f7ff fbbd bl 80017a8 800202e: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002030: e008 b.n 8002044 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8002032: f7ff fbb9 bl 80017a8 8002036: 4602 mov r2, r0 8002038: 693b ldr r3, [r7, #16] 800203a: 1ad3 subs r3, r2, r3 800203c: 2b64 cmp r3, #100 ; 0x64 800203e: d901 bls.n 8002044 { return HAL_TIMEOUT; 8002040: 2303 movs r3, #3 8002042: e0fd b.n 8002240 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002044: 4b81 ldr r3, [pc, #516] ; (800224c ) 8002046: 681b ldr r3, [r3, #0] 8002048: f403 7380 and.w r3, r3, #256 ; 0x100 800204c: 2b00 cmp r3, #0 800204e: d0f0 beq.n 8002032 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002050: 687b ldr r3, [r7, #4] 8002052: 68db ldr r3, [r3, #12] 8002054: 2b01 cmp r3, #1 8002056: d106 bne.n 8002066 8002058: 4b7b ldr r3, [pc, #492] ; (8002248 ) 800205a: 6a1b ldr r3, [r3, #32] 800205c: 4a7a ldr r2, [pc, #488] ; (8002248 ) 800205e: f043 0301 orr.w r3, r3, #1 8002062: 6213 str r3, [r2, #32] 8002064: e02d b.n 80020c2 8002066: 687b ldr r3, [r7, #4] 8002068: 68db ldr r3, [r3, #12] 800206a: 2b00 cmp r3, #0 800206c: d10c bne.n 8002088 800206e: 4b76 ldr r3, [pc, #472] ; (8002248 ) 8002070: 6a1b ldr r3, [r3, #32] 8002072: 4a75 ldr r2, [pc, #468] ; (8002248 ) 8002074: f023 0301 bic.w r3, r3, #1 8002078: 6213 str r3, [r2, #32] 800207a: 4b73 ldr r3, [pc, #460] ; (8002248 ) 800207c: 6a1b ldr r3, [r3, #32] 800207e: 4a72 ldr r2, [pc, #456] ; (8002248 ) 8002080: f023 0304 bic.w r3, r3, #4 8002084: 6213 str r3, [r2, #32] 8002086: e01c b.n 80020c2 8002088: 687b ldr r3, [r7, #4] 800208a: 68db ldr r3, [r3, #12] 800208c: 2b05 cmp r3, #5 800208e: d10c bne.n 80020aa