: /** * @brief The application entry point. * @retval int */ int main(void) { 8000b60: b580 push {r7, lr} 8000b62: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000b64: f000 fab2 bl 80010cc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000b68: f000 f807 bl 8000b7a /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000b6c: f000 f84a bl 8000c04 MX_FSMC_Init(); 8000b70: f000 f89e bl 8000cb0 /* USER CODE BEGIN 2 */ main_app(); 8000b74: f001 fe3e bl 80027f4 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000b78: e7fe b.n 8000b78 08000b7a : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000b7a: b580 push {r7, lr} 8000b7c: b090 sub sp, #64 ; 0x40 8000b7e: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000b80: f107 0318 add.w r3, r7, #24 8000b84: 2228 movs r2, #40 ; 0x28 8000b86: 2100 movs r1, #0 8000b88: 4618 mov r0, r3 8000b8a: f001 fe63 bl 8002854 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000b8e: 1d3b adds r3, r7, #4 8000b90: 2200 movs r2, #0 8000b92: 601a str r2, [r3, #0] 8000b94: 605a str r2, [r3, #4] 8000b96: 609a str r2, [r3, #8] 8000b98: 60da str r2, [r3, #12] 8000b9a: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000b9c: 2301 movs r3, #1 8000b9e: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000ba0: f44f 3380 mov.w r3, #65536 ; 0x10000 8000ba4: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8000ba6: 2300 movs r3, #0 8000ba8: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000baa: 2301 movs r3, #1 8000bac: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000bae: 2302 movs r3, #2 8000bb0: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000bb2: f44f 3380 mov.w r3, #65536 ; 0x10000 8000bb6: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8000bb8: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8000bbc: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000bbe: f107 0318 add.w r3, r7, #24 8000bc2: 4618 mov r0, r3 8000bc4: f000 fd98 bl 80016f8 8000bc8: 4603 mov r3, r0 8000bca: 2b00 cmp r3, #0 8000bcc: d001 beq.n 8000bd2 { Error_Handler(); 8000bce: f000 f8d3 bl 8000d78 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000bd2: 230f movs r3, #15 8000bd4: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000bd6: 2302 movs r3, #2 8000bd8: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000bda: 2300 movs r3, #0 8000bdc: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000bde: f44f 6380 mov.w r3, #1024 ; 0x400 8000be2: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000be4: 2300 movs r3, #0 8000be6: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000be8: 1d3b adds r3, r7, #4 8000bea: 2102 movs r1, #2 8000bec: 4618 mov r0, r3 8000bee: f001 f803 bl 8001bf8 8000bf2: 4603 mov r3, r0 8000bf4: 2b00 cmp r3, #0 8000bf6: d001 beq.n 8000bfc { Error_Handler(); 8000bf8: f000 f8be bl 8000d78 } } 8000bfc: bf00 nop 8000bfe: 3740 adds r7, #64 ; 0x40 8000c00: 46bd mov sp, r7 8000c02: bd80 pop {r7, pc} 08000c04 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000c04: b580 push {r7, lr} 8000c06: b088 sub sp, #32 8000c08: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000c0a: f107 0310 add.w r3, r7, #16 8000c0e: 2200 movs r2, #0 8000c10: 601a str r2, [r3, #0] 8000c12: 605a str r2, [r3, #4] 8000c14: 609a str r2, [r3, #8] 8000c16: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8000c18: 4b23 ldr r3, [pc, #140] ; (8000ca8 ) 8000c1a: 699b ldr r3, [r3, #24] 8000c1c: 4a22 ldr r2, [pc, #136] ; (8000ca8 ) 8000c1e: f043 0308 orr.w r3, r3, #8 8000c22: 6193 str r3, [r2, #24] 8000c24: 4b20 ldr r3, [pc, #128] ; (8000ca8 ) 8000c26: 699b ldr r3, [r3, #24] 8000c28: f003 0308 and.w r3, r3, #8 8000c2c: 60fb str r3, [r7, #12] 8000c2e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000c30: 4b1d ldr r3, [pc, #116] ; (8000ca8 ) 8000c32: 699b ldr r3, [r3, #24] 8000c34: 4a1c ldr r2, [pc, #112] ; (8000ca8 ) 8000c36: f443 7380 orr.w r3, r3, #256 ; 0x100 8000c3a: 6193 str r3, [r2, #24] 8000c3c: 4b1a ldr r3, [pc, #104] ; (8000ca8 ) 8000c3e: 699b ldr r3, [r3, #24] 8000c40: f403 7380 and.w r3, r3, #256 ; 0x100 8000c44: 60bb str r3, [r7, #8] 8000c46: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000c48: 4b17 ldr r3, [pc, #92] ; (8000ca8 ) 8000c4a: 699b ldr r3, [r3, #24] 8000c4c: 4a16 ldr r2, [pc, #88] ; (8000ca8 ) 8000c4e: f043 0340 orr.w r3, r3, #64 ; 0x40 8000c52: 6193 str r3, [r2, #24] 8000c54: 4b14 ldr r3, [pc, #80] ; (8000ca8 ) 8000c56: 699b ldr r3, [r3, #24] 8000c58: f003 0340 and.w r3, r3, #64 ; 0x40 8000c5c: 607b str r3, [r7, #4] 8000c5e: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000c60: 4b11 ldr r3, [pc, #68] ; (8000ca8 ) 8000c62: 699b ldr r3, [r3, #24] 8000c64: 4a10 ldr r2, [pc, #64] ; (8000ca8 ) 8000c66: f043 0320 orr.w r3, r3, #32 8000c6a: 6193 str r3, [r2, #24] 8000c6c: 4b0e ldr r3, [pc, #56] ; (8000ca8 ) 8000c6e: 699b ldr r3, [r3, #24] 8000c70: f003 0320 and.w r3, r3, #32 8000c74: 603b str r3, [r7, #0] 8000c76: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); 8000c78: 2200 movs r2, #0 8000c7a: 2101 movs r1, #1 8000c7c: 480b ldr r0, [pc, #44] ; (8000cac ) 8000c7e: f000 fd23 bl 80016c8 /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 8000c82: 2301 movs r3, #1 8000c84: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c86: 2301 movs r3, #1 8000c88: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c8a: 2300 movs r3, #0 8000c8c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c8e: 2302 movs r3, #2 8000c90: 61fb str r3, [r7, #28] HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 8000c92: f107 0310 add.w r3, r7, #16 8000c96: 4619 mov r1, r3 8000c98: 4804 ldr r0, [pc, #16] ; (8000cac ) 8000c9a: f000 fb81 bl 80013a0 } 8000c9e: bf00 nop 8000ca0: 3720 adds r7, #32 8000ca2: 46bd mov sp, r7 8000ca4: bd80 pop {r7, pc} 8000ca6: bf00 nop 8000ca8: 40021000 .word 0x40021000 8000cac: 40010c00 .word 0x40010c00 08000cb0 : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 8000cb0: b580 push {r7, lr} 8000cb2: b088 sub sp, #32 8000cb4: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 8000cb6: 1d3b adds r3, r7, #4 8000cb8: 2200 movs r2, #0 8000cba: 601a str r2, [r3, #0] 8000cbc: 605a str r2, [r3, #4] 8000cbe: 609a str r2, [r3, #8] 8000cc0: 60da str r2, [r3, #12] 8000cc2: 611a str r2, [r3, #16] 8000cc4: 615a str r2, [r3, #20] 8000cc6: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 8000cc8: 4b28 ldr r3, [pc, #160] ; (8000d6c ) 8000cca: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 8000cce: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 8000cd0: 4b26 ldr r3, [pc, #152] ; (8000d6c ) 8000cd2: 4a27 ldr r2, [pc, #156] ; (8000d70 ) 8000cd4: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 8000cd6: 4b25 ldr r3, [pc, #148] ; (8000d6c ) 8000cd8: 2206 movs r2, #6 8000cda: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 8000cdc: 4b23 ldr r3, [pc, #140] ; (8000d6c ) 8000cde: 2200 movs r2, #0 8000ce0: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 8000ce2: 4b22 ldr r3, [pc, #136] ; (8000d6c ) 8000ce4: 2200 movs r2, #0 8000ce6: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 8000ce8: 4b20 ldr r3, [pc, #128] ; (8000d6c ) 8000cea: 2210 movs r2, #16 8000cec: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 8000cee: 4b1f ldr r3, [pc, #124] ; (8000d6c ) 8000cf0: 2200 movs r2, #0 8000cf2: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 8000cf4: 4b1d ldr r3, [pc, #116] ; (8000d6c ) 8000cf6: 2200 movs r2, #0 8000cf8: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 8000cfa: 4b1c ldr r3, [pc, #112] ; (8000d6c ) 8000cfc: 2200 movs r2, #0 8000cfe: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 8000d00: 4b1a ldr r3, [pc, #104] ; (8000d6c ) 8000d02: 2200 movs r2, #0 8000d04: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 8000d06: 4b19 ldr r3, [pc, #100] ; (8000d6c ) 8000d08: f44f 5280 mov.w r2, #4096 ; 0x1000 8000d0c: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 8000d0e: 4b17 ldr r3, [pc, #92] ; (8000d6c ) 8000d10: 2200 movs r2, #0 8000d12: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 8000d14: 4b15 ldr r3, [pc, #84] ; (8000d6c ) 8000d16: 2200 movs r2, #0 8000d18: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 8000d1a: 4b14 ldr r3, [pc, #80] ; (8000d6c ) 8000d1c: 2200 movs r2, #0 8000d1e: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 8000d20: 4b12 ldr r3, [pc, #72] ; (8000d6c ) 8000d22: 2200 movs r2, #0 8000d24: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 8000d26: 2300 movs r3, #0 8000d28: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 8000d2a: 230f movs r3, #15 8000d2c: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 8000d2e: 2301 movs r3, #1 8000d30: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 0; 8000d32: 2300 movs r3, #0 8000d34: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 8000d36: 2310 movs r3, #16 8000d38: 617b str r3, [r7, #20] Timing.DataLatency = 17; 8000d3a: 2311 movs r3, #17 8000d3c: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 8000d3e: 2300 movs r3, #0 8000d40: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 8000d42: 1d3b adds r3, r7, #4 8000d44: 2200 movs r2, #0 8000d46: 4619 mov r1, r3 8000d48: 4808 ldr r0, [pc, #32] ; (8000d6c ) 8000d4a: f001 f8bd bl 8001ec8 8000d4e: 4603 mov r3, r0 8000d50: 2b00 cmp r3, #0 8000d52: d001 beq.n 8000d58 { Error_Handler( ); 8000d54: f000 f810 bl 8000d78 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 8000d58: 4b06 ldr r3, [pc, #24] ; (8000d74 ) 8000d5a: 69db ldr r3, [r3, #28] 8000d5c: 4a05 ldr r2, [pc, #20] ; (8000d74 ) 8000d5e: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000d62: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 8000d64: bf00 nop 8000d66: 3720 adds r7, #32 8000d68: 46bd mov sp, r7 8000d6a: bd80 pop {r7, pc} 8000d6c: 20000208 .word 0x20000208 8000d70: a0000104 .word 0xa0000104 8000d74: 40010000 .word 0x40010000 08000d78 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000d78: b480 push {r7} 8000d7a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000d7c: b672 cpsid i } 8000d7e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000d80: e7fe b.n 8000d80 ... 08000d84 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000d84: b480 push {r7} 8000d86: b085 sub sp, #20 8000d88: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000d8a: 4b15 ldr r3, [pc, #84] ; (8000de0 ) 8000d8c: 699b ldr r3, [r3, #24] 8000d8e: 4a14 ldr r2, [pc, #80] ; (8000de0 ) 8000d90: f043 0301 orr.w r3, r3, #1 8000d94: 6193 str r3, [r2, #24] 8000d96: 4b12 ldr r3, [pc, #72] ; (8000de0 ) 8000d98: 699b ldr r3, [r3, #24] 8000d9a: f003 0301 and.w r3, r3, #1 8000d9e: 60bb str r3, [r7, #8] 8000da0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8000da2: 4b0f ldr r3, [pc, #60] ; (8000de0 ) 8000da4: 69db ldr r3, [r3, #28] 8000da6: 4a0e ldr r2, [pc, #56] ; (8000de0 ) 8000da8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000dac: 61d3 str r3, [r2, #28] 8000dae: 4b0c ldr r3, [pc, #48] ; (8000de0 ) 8000db0: 69db ldr r3, [r3, #28] 8000db2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000db6: 607b str r3, [r7, #4] 8000db8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 8000dba: 4b0a ldr r3, [pc, #40] ; (8000de4 ) 8000dbc: 685b ldr r3, [r3, #4] 8000dbe: 60fb str r3, [r7, #12] 8000dc0: 68fb ldr r3, [r7, #12] 8000dc2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8000dc6: 60fb str r3, [r7, #12] 8000dc8: 68fb ldr r3, [r7, #12] 8000dca: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8000dce: 60fb str r3, [r7, #12] 8000dd0: 4a04 ldr r2, [pc, #16] ; (8000de4 ) 8000dd2: 68fb ldr r3, [r7, #12] 8000dd4: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000dd6: bf00 nop 8000dd8: 3714 adds r7, #20 8000dda: 46bd mov sp, r7 8000ddc: bc80 pop {r7} 8000dde: 4770 bx lr 8000de0: 40021000 .word 0x40021000 8000de4: 40010000 .word 0x40010000 08000de8 : static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 8000de8: b580 push {r7, lr} 8000dea: b086 sub sp, #24 8000dec: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 8000dee: f107 0308 add.w r3, r7, #8 8000df2: 2200 movs r2, #0 8000df4: 601a str r2, [r3, #0] 8000df6: 605a str r2, [r3, #4] 8000df8: 609a str r2, [r3, #8] 8000dfa: 60da str r2, [r3, #12] if (FSMC_Initialized) { 8000dfc: 4b1f ldr r3, [pc, #124] ; (8000e7c ) 8000dfe: 681b ldr r3, [r3, #0] 8000e00: 2b00 cmp r3, #0 8000e02: d136 bne.n 8000e72 return; } FSMC_Initialized = 1; 8000e04: 4b1d ldr r3, [pc, #116] ; (8000e7c ) 8000e06: 2201 movs r2, #1 8000e08: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 8000e0a: 4b1d ldr r3, [pc, #116] ; (8000e80 ) 8000e0c: 695b ldr r3, [r3, #20] 8000e0e: 4a1c ldr r2, [pc, #112] ; (8000e80 ) 8000e10: f443 7380 orr.w r3, r3, #256 ; 0x100 8000e14: 6153 str r3, [r2, #20] 8000e16: 4b1a ldr r3, [pc, #104] ; (8000e80 ) 8000e18: 695b ldr r3, [r3, #20] 8000e1a: f403 7380 and.w r3, r3, #256 ; 0x100 8000e1e: 607b str r3, [r7, #4] 8000e20: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 8000e22: f241 0301 movw r3, #4097 ; 0x1001 8000e26: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000e28: 2302 movs r3, #2 8000e2a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000e2c: 2303 movs r3, #3 8000e2e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000e30: f107 0308 add.w r3, r7, #8 8000e34: 4619 mov r1, r3 8000e36: 4813 ldr r0, [pc, #76] ; (8000e84 ) 8000e38: f000 fab2 bl 80013a0 GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8000e3c: f64f 7380 movw r3, #65408 ; 0xff80 8000e40: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000e42: 2302 movs r3, #2 8000e44: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000e46: 2303 movs r3, #3 8000e48: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000e4a: f107 0308 add.w r3, r7, #8 8000e4e: 4619 mov r1, r3 8000e50: 480d ldr r0, [pc, #52] ; (8000e88 ) 8000e52: f000 faa5 bl 80013a0 GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 8000e56: f24c 7333 movw r3, #50995 ; 0xc733 8000e5a: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000e5c: 2302 movs r3, #2 8000e5e: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000e60: 2303 movs r3, #3 8000e62: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000e64: f107 0308 add.w r3, r7, #8 8000e68: 4619 mov r1, r3 8000e6a: 4808 ldr r0, [pc, #32] ; (8000e8c ) 8000e6c: f000 fa98 bl 80013a0 8000e70: e000 b.n 8000e74 return; 8000e72: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 8000e74: 3718 adds r7, #24 8000e76: 46bd mov sp, r7 8000e78: bd80 pop {r7, pc} 8000e7a: bf00 nop 8000e7c: 200001f8 .word 0x200001f8 8000e80: 40021000 .word 0x40021000 8000e84: 40012000 .word 0x40012000 8000e88: 40011800 .word 0x40011800 8000e8c: 40011400 .word 0x40011400 08000e90 : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 8000e90: b580 push {r7, lr} 8000e92: b082 sub sp, #8 8000e94: af00 add r7, sp, #0 8000e96: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 8000e98: f7ff ffa6 bl 8000de8 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 8000e9c: bf00 nop 8000e9e: 3708 adds r7, #8 8000ea0: 46bd mov sp, r7 8000ea2: bd80 pop {r7, pc} 08000ea4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000ea4: b480 push {r7} 8000ea6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000ea8: e7fe b.n 8000ea8 08000eaa : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000eaa: b480 push {r7} 8000eac: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000eae: e7fe b.n 8000eae 08000eb0 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000eb0: b480 push {r7} 8000eb2: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000eb4: e7fe b.n 8000eb4 08000eb6 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8000eb6: b480 push {r7} 8000eb8: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000eba: e7fe b.n 8000eba 08000ebc : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000ebc: b480 push {r7} 8000ebe: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000ec0: e7fe b.n 8000ec0 08000ec2 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000ec2: b480 push {r7} 8000ec4: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000ec6: bf00 nop 8000ec8: 46bd mov sp, r7 8000eca: bc80 pop {r7} 8000ecc: 4770 bx lr 08000ece : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000ece: b480 push {r7} 8000ed0: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000ed2: bf00 nop 8000ed4: 46bd mov sp, r7 8000ed6: bc80 pop {r7} 8000ed8: 4770 bx lr 08000eda : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000eda: b480 push {r7} 8000edc: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000ede: bf00 nop 8000ee0: 46bd mov sp, r7 8000ee2: bc80 pop {r7} 8000ee4: 4770 bx lr 08000ee6 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000ee6: b580 push {r7, lr} 8000ee8: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000eea: f000 f935 bl 8001158 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000eee: bf00 nop 8000ef0: bd80 pop {r7, pc} 08000ef2 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 8000ef2: b480 push {r7} 8000ef4: af00 add r7, sp, #0 return 1; 8000ef6: 2301 movs r3, #1 } 8000ef8: 4618 mov r0, r3 8000efa: 46bd mov sp, r7 8000efc: bc80 pop {r7} 8000efe: 4770 bx lr 08000f00 <_kill>: int _kill(int pid, int sig) { 8000f00: b580 push {r7, lr} 8000f02: b082 sub sp, #8 8000f04: af00 add r7, sp, #0 8000f06: 6078 str r0, [r7, #4] 8000f08: 6039 str r1, [r7, #0] errno = EINVAL; 8000f0a: f001 fc79 bl 8002800 <__errno> 8000f0e: 4603 mov r3, r0 8000f10: 2216 movs r2, #22 8000f12: 601a str r2, [r3, #0] return -1; 8000f14: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8000f18: 4618 mov r0, r3 8000f1a: 3708 adds r7, #8 8000f1c: 46bd mov sp, r7 8000f1e: bd80 pop {r7, pc} 08000f20 <_exit>: void _exit (int status) { 8000f20: b580 push {r7, lr} 8000f22: b082 sub sp, #8 8000f24: af00 add r7, sp, #0 8000f26: 6078 str r0, [r7, #4] _kill(status, -1); 8000f28: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8000f2c: 6878 ldr r0, [r7, #4] 8000f2e: f7ff ffe7 bl 8000f00 <_kill> while (1) {} /* Make sure we hang here */ 8000f32: e7fe b.n 8000f32 <_exit+0x12> 08000f34 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8000f34: b580 push {r7, lr} 8000f36: b086 sub sp, #24 8000f38: af00 add r7, sp, #0 8000f3a: 60f8 str r0, [r7, #12] 8000f3c: 60b9 str r1, [r7, #8] 8000f3e: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8000f40: 2300 movs r3, #0 8000f42: 617b str r3, [r7, #20] 8000f44: e00a b.n 8000f5c <_read+0x28> { *ptr++ = __io_getchar(); 8000f46: f3af 8000 nop.w 8000f4a: 4601 mov r1, r0 8000f4c: 68bb ldr r3, [r7, #8] 8000f4e: 1c5a adds r2, r3, #1 8000f50: 60ba str r2, [r7, #8] 8000f52: b2ca uxtb r2, r1 8000f54: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8000f56: 697b ldr r3, [r7, #20] 8000f58: 3301 adds r3, #1 8000f5a: 617b str r3, [r7, #20] 8000f5c: 697a ldr r2, [r7, #20] 8000f5e: 687b ldr r3, [r7, #4] 8000f60: 429a cmp r2, r3 8000f62: dbf0 blt.n 8000f46 <_read+0x12> } return len; 8000f64: 687b ldr r3, [r7, #4] } 8000f66: 4618 mov r0, r3 8000f68: 3718 adds r7, #24 8000f6a: 46bd mov sp, r7 8000f6c: bd80 pop {r7, pc} 08000f6e <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8000f6e: b580 push {r7, lr} 8000f70: b086 sub sp, #24 8000f72: af00 add r7, sp, #0 8000f74: 60f8 str r0, [r7, #12] 8000f76: 60b9 str r1, [r7, #8] 8000f78: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8000f7a: 2300 movs r3, #0 8000f7c: 617b str r3, [r7, #20] 8000f7e: e009 b.n 8000f94 <_write+0x26> { __io_putchar(*ptr++); 8000f80: 68bb ldr r3, [r7, #8] 8000f82: 1c5a adds r2, r3, #1 8000f84: 60ba str r2, [r7, #8] 8000f86: 781b ldrb r3, [r3, #0] 8000f88: 4618 mov r0, r3 8000f8a: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 8000f8e: 697b ldr r3, [r7, #20] 8000f90: 3301 adds r3, #1 8000f92: 617b str r3, [r7, #20] 8000f94: 697a ldr r2, [r7, #20] 8000f96: 687b ldr r3, [r7, #4] 8000f98: 429a cmp r2, r3 8000f9a: dbf1 blt.n 8000f80 <_write+0x12> } return len; 8000f9c: 687b ldr r3, [r7, #4] } 8000f9e: 4618 mov r0, r3 8000fa0: 3718 adds r7, #24 8000fa2: 46bd mov sp, r7 8000fa4: bd80 pop {r7, pc} 08000fa6 <_close>: int _close(int file) { 8000fa6: b480 push {r7} 8000fa8: b083 sub sp, #12 8000faa: af00 add r7, sp, #0 8000fac: 6078 str r0, [r7, #4] return -1; 8000fae: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8000fb2: 4618 mov r0, r3 8000fb4: 370c adds r7, #12 8000fb6: 46bd mov sp, r7 8000fb8: bc80 pop {r7} 8000fba: 4770 bx lr 08000fbc <_fstat>: int _fstat(int file, struct stat *st) { 8000fbc: b480 push {r7} 8000fbe: b083 sub sp, #12 8000fc0: af00 add r7, sp, #0 8000fc2: 6078 str r0, [r7, #4] 8000fc4: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8000fc6: 683b ldr r3, [r7, #0] 8000fc8: f44f 5200 mov.w r2, #8192 ; 0x2000 8000fcc: 605a str r2, [r3, #4] return 0; 8000fce: 2300 movs r3, #0 } 8000fd0: 4618 mov r0, r3 8000fd2: 370c adds r7, #12 8000fd4: 46bd mov sp, r7 8000fd6: bc80 pop {r7} 8000fd8: 4770 bx lr 08000fda <_isatty>: int _isatty(int file) { 8000fda: b480 push {r7} 8000fdc: b083 sub sp, #12 8000fde: af00 add r7, sp, #0 8000fe0: 6078 str r0, [r7, #4] return 1; 8000fe2: 2301 movs r3, #1 } 8000fe4: 4618 mov r0, r3 8000fe6: 370c adds r7, #12 8000fe8: 46bd mov sp, r7 8000fea: bc80 pop {r7} 8000fec: 4770 bx lr 08000fee <_lseek>: int _lseek(int file, int ptr, int dir) { 8000fee: b480 push {r7} 8000ff0: b085 sub sp, #20 8000ff2: af00 add r7, sp, #0 8000ff4: 60f8 str r0, [r7, #12] 8000ff6: 60b9 str r1, [r7, #8] 8000ff8: 607a str r2, [r7, #4] return 0; 8000ffa: 2300 movs r3, #0 } 8000ffc: 4618 mov r0, r3 8000ffe: 3714 adds r7, #20 8001000: 46bd mov sp, r7 8001002: bc80 pop {r7} 8001004: 4770 bx lr ... 08001008 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001008: b580 push {r7, lr} 800100a: b086 sub sp, #24 800100c: af00 add r7, sp, #0 800100e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8001010: 4a14 ldr r2, [pc, #80] ; (8001064 <_sbrk+0x5c>) 8001012: 4b15 ldr r3, [pc, #84] ; (8001068 <_sbrk+0x60>) 8001014: 1ad3 subs r3, r2, r3 8001016: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001018: 697b ldr r3, [r7, #20] 800101a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800101c: 4b13 ldr r3, [pc, #76] ; (800106c <_sbrk+0x64>) 800101e: 681b ldr r3, [r3, #0] 8001020: 2b00 cmp r3, #0 8001022: d102 bne.n 800102a <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001024: 4b11 ldr r3, [pc, #68] ; (800106c <_sbrk+0x64>) 8001026: 4a12 ldr r2, [pc, #72] ; (8001070 <_sbrk+0x68>) 8001028: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800102a: 4b10 ldr r3, [pc, #64] ; (800106c <_sbrk+0x64>) 800102c: 681a ldr r2, [r3, #0] 800102e: 687b ldr r3, [r7, #4] 8001030: 4413 add r3, r2 8001032: 693a ldr r2, [r7, #16] 8001034: 429a cmp r2, r3 8001036: d207 bcs.n 8001048 <_sbrk+0x40> { errno = ENOMEM; 8001038: f001 fbe2 bl 8002800 <__errno> 800103c: 4603 mov r3, r0 800103e: 220c movs r2, #12 8001040: 601a str r2, [r3, #0] return (void *)-1; 8001042: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8001046: e009 b.n 800105c <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8001048: 4b08 ldr r3, [pc, #32] ; (800106c <_sbrk+0x64>) 800104a: 681b ldr r3, [r3, #0] 800104c: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800104e: 4b07 ldr r3, [pc, #28] ; (800106c <_sbrk+0x64>) 8001050: 681a ldr r2, [r3, #0] 8001052: 687b ldr r3, [r7, #4] 8001054: 4413 add r3, r2 8001056: 4a05 ldr r2, [pc, #20] ; (800106c <_sbrk+0x64>) 8001058: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800105a: 68fb ldr r3, [r7, #12] } 800105c: 4618 mov r0, r3 800105e: 3718 adds r7, #24 8001060: 46bd mov sp, r7 8001062: bd80 pop {r7, pc} 8001064: 20010000 .word 0x20010000 8001068: 00000400 .word 0x00000400 800106c: 200001fc .word 0x200001fc 8001070: 20000270 .word 0x20000270 08001074 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8001074: b480 push {r7} 8001076: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001078: bf00 nop 800107a: 46bd mov sp, r7 800107c: bc80 pop {r7} 800107e: 4770 bx lr 08001080 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001080: 480c ldr r0, [pc, #48] ; (80010b4 ) ldr r1, =_edata 8001082: 490d ldr r1, [pc, #52] ; (80010b8 ) ldr r2, =_sidata 8001084: 4a0d ldr r2, [pc, #52] ; (80010bc ) movs r3, #0 8001086: 2300 movs r3, #0 b LoopCopyDataInit 8001088: e002 b.n 8001090 0800108a : CopyDataInit: ldr r4, [r2, r3] 800108a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800108c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800108e: 3304 adds r3, #4 08001090 : LoopCopyDataInit: adds r4, r0, r3 8001090: 18c4 adds r4, r0, r3 cmp r4, r1 8001092: 428c cmp r4, r1 bcc CopyDataInit 8001094: d3f9 bcc.n 800108a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001096: 4a0a ldr r2, [pc, #40] ; (80010c0 ) ldr r4, =_ebss 8001098: 4c0a ldr r4, [pc, #40] ; (80010c4 ) movs r3, #0 800109a: 2300 movs r3, #0 b LoopFillZerobss 800109c: e001 b.n 80010a2 0800109e : FillZerobss: str r3, [r2] 800109e: 6013 str r3, [r2, #0] adds r2, r2, #4 80010a0: 3204 adds r2, #4 080010a2 : LoopFillZerobss: cmp r2, r4 80010a2: 42a2 cmp r2, r4 bcc FillZerobss 80010a4: d3fb bcc.n 800109e /* Call the clock system intitialization function.*/ bl SystemInit 80010a6: f7ff ffe5 bl 8001074 /* Call static constructors */ bl __libc_init_array 80010aa: f001 fbaf bl 800280c <__libc_init_array> /* Call the application's entry point.*/ bl main 80010ae: f7ff fd57 bl 8000b60

bx lr 80010b2: 4770 bx lr ldr r0, =_sdata 80010b4: 20000000 .word 0x20000000 ldr r1, =_edata 80010b8: 200001dc .word 0x200001dc ldr r2, =_sidata 80010bc: 08005634 .word 0x08005634 ldr r2, =_sbss 80010c0: 200001dc .word 0x200001dc ldr r4, =_ebss 80010c4: 20000270 .word 0x20000270 080010c8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80010c8: e7fe b.n 80010c8 ... 080010cc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80010cc: b580 push {r7, lr} 80010ce: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80010d0: 4b08 ldr r3, [pc, #32] ; (80010f4 ) 80010d2: 681b ldr r3, [r3, #0] 80010d4: 4a07 ldr r2, [pc, #28] ; (80010f4 ) 80010d6: f043 0310 orr.w r3, r3, #16 80010da: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80010dc: 2003 movs r0, #3 80010de: f000 f92b bl 8001338 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80010e2: 200f movs r0, #15 80010e4: f000 f808 bl 80010f8 /* Init the low level hardware */ HAL_MspInit(); 80010e8: f7ff fe4c bl 8000d84 /* Return function status */ return HAL_OK; 80010ec: 2300 movs r3, #0 } 80010ee: 4618 mov r0, r3 80010f0: bd80 pop {r7, pc} 80010f2: bf00 nop 80010f4: 40022000 .word 0x40022000 080010f8 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80010f8: b580 push {r7, lr} 80010fa: b082 sub sp, #8 80010fc: af00 add r7, sp, #0 80010fe: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001100: 4b12 ldr r3, [pc, #72] ; (800114c ) 8001102: 681a ldr r2, [r3, #0] 8001104: 4b12 ldr r3, [pc, #72] ; (8001150 ) 8001106: 781b ldrb r3, [r3, #0] 8001108: 4619 mov r1, r3 800110a: f44f 737a mov.w r3, #1000 ; 0x3e8 800110e: fbb3 f3f1 udiv r3, r3, r1 8001112: fbb2 f3f3 udiv r3, r2, r3 8001116: 4618 mov r0, r3 8001118: f000 f935 bl 8001386 800111c: 4603 mov r3, r0 800111e: 2b00 cmp r3, #0 8001120: d001 beq.n 8001126 { return HAL_ERROR; 8001122: 2301 movs r3, #1 8001124: e00e b.n 8001144 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001126: 687b ldr r3, [r7, #4] 8001128: 2b0f cmp r3, #15 800112a: d80a bhi.n 8001142 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800112c: 2200 movs r2, #0 800112e: 6879 ldr r1, [r7, #4] 8001130: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001134: f000 f90b bl 800134e uwTickPrio = TickPriority; 8001138: 4a06 ldr r2, [pc, #24] ; (8001154 ) 800113a: 687b ldr r3, [r7, #4] 800113c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800113e: 2300 movs r3, #0 8001140: e000 b.n 8001144 return HAL_ERROR; 8001142: 2301 movs r3, #1 } 8001144: 4618 mov r0, r3 8001146: 3708 adds r7, #8 8001148: 46bd mov sp, r7 800114a: bd80 pop {r7, pc} 800114c: 20000000 .word 0x20000000 8001150: 20000008 .word 0x20000008 8001154: 20000004 .word 0x20000004 08001158 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001158: b480 push {r7} 800115a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800115c: 4b05 ldr r3, [pc, #20] ; (8001174 ) 800115e: 781b ldrb r3, [r3, #0] 8001160: 461a mov r2, r3 8001162: 4b05 ldr r3, [pc, #20] ; (8001178 ) 8001164: 681b ldr r3, [r3, #0] 8001166: 4413 add r3, r2 8001168: 4a03 ldr r2, [pc, #12] ; (8001178 ) 800116a: 6013 str r3, [r2, #0] } 800116c: bf00 nop 800116e: 46bd mov sp, r7 8001170: bc80 pop {r7} 8001172: 4770 bx lr 8001174: 20000008 .word 0x20000008 8001178: 20000250 .word 0x20000250 0800117c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800117c: b480 push {r7} 800117e: af00 add r7, sp, #0 return uwTick; 8001180: 4b02 ldr r3, [pc, #8] ; (800118c ) 8001182: 681b ldr r3, [r3, #0] } 8001184: 4618 mov r0, r3 8001186: 46bd mov sp, r7 8001188: bc80 pop {r7} 800118a: 4770 bx lr 800118c: 20000250 .word 0x20000250 08001190 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001190: b580 push {r7, lr} 8001192: b084 sub sp, #16 8001194: af00 add r7, sp, #0 8001196: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001198: f7ff fff0 bl 800117c 800119c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800119e: 687b ldr r3, [r7, #4] 80011a0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80011a2: 68fb ldr r3, [r7, #12] 80011a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80011a8: d005 beq.n 80011b6 { wait += (uint32_t)(uwTickFreq); 80011aa: 4b0a ldr r3, [pc, #40] ; (80011d4 ) 80011ac: 781b ldrb r3, [r3, #0] 80011ae: 461a mov r2, r3 80011b0: 68fb ldr r3, [r7, #12] 80011b2: 4413 add r3, r2 80011b4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80011b6: bf00 nop 80011b8: f7ff ffe0 bl 800117c 80011bc: 4602 mov r2, r0 80011be: 68bb ldr r3, [r7, #8] 80011c0: 1ad3 subs r3, r2, r3 80011c2: 68fa ldr r2, [r7, #12] 80011c4: 429a cmp r2, r3 80011c6: d8f7 bhi.n 80011b8 { } } 80011c8: bf00 nop 80011ca: bf00 nop 80011cc: 3710 adds r7, #16 80011ce: 46bd mov sp, r7 80011d0: bd80 pop {r7, pc} 80011d2: bf00 nop 80011d4: 20000008 .word 0x20000008 080011d8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80011d8: b480 push {r7} 80011da: b085 sub sp, #20 80011dc: af00 add r7, sp, #0 80011de: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80011e0: 687b ldr r3, [r7, #4] 80011e2: f003 0307 and.w r3, r3, #7 80011e6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80011e8: 4b0c ldr r3, [pc, #48] ; (800121c <__NVIC_SetPriorityGrouping+0x44>) 80011ea: 68db ldr r3, [r3, #12] 80011ec: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80011ee: 68ba ldr r2, [r7, #8] 80011f0: f64f 03ff movw r3, #63743 ; 0xf8ff 80011f4: 4013 ands r3, r2 80011f6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80011f8: 68fb ldr r3, [r7, #12] 80011fa: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80011fc: 68bb ldr r3, [r7, #8] 80011fe: 4313 orrs r3, r2 reg_value = (reg_value | 8001200: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001204: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001208: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800120a: 4a04 ldr r2, [pc, #16] ; (800121c <__NVIC_SetPriorityGrouping+0x44>) 800120c: 68bb ldr r3, [r7, #8] 800120e: 60d3 str r3, [r2, #12] } 8001210: bf00 nop 8001212: 3714 adds r7, #20 8001214: 46bd mov sp, r7 8001216: bc80 pop {r7} 8001218: 4770 bx lr 800121a: bf00 nop 800121c: e000ed00 .word 0xe000ed00 08001220 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001220: b480 push {r7} 8001222: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001224: 4b04 ldr r3, [pc, #16] ; (8001238 <__NVIC_GetPriorityGrouping+0x18>) 8001226: 68db ldr r3, [r3, #12] 8001228: 0a1b lsrs r3, r3, #8 800122a: f003 0307 and.w r3, r3, #7 } 800122e: 4618 mov r0, r3 8001230: 46bd mov sp, r7 8001232: bc80 pop {r7} 8001234: 4770 bx lr 8001236: bf00 nop 8001238: e000ed00 .word 0xe000ed00 0800123c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800123c: b480 push {r7} 800123e: b083 sub sp, #12 8001240: af00 add r7, sp, #0 8001242: 4603 mov r3, r0 8001244: 6039 str r1, [r7, #0] 8001246: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001248: f997 3007 ldrsb.w r3, [r7, #7] 800124c: 2b00 cmp r3, #0 800124e: db0a blt.n 8001266 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001250: 683b ldr r3, [r7, #0] 8001252: b2da uxtb r2, r3 8001254: 490c ldr r1, [pc, #48] ; (8001288 <__NVIC_SetPriority+0x4c>) 8001256: f997 3007 ldrsb.w r3, [r7, #7] 800125a: 0112 lsls r2, r2, #4 800125c: b2d2 uxtb r2, r2 800125e: 440b add r3, r1 8001260: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001264: e00a b.n 800127c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001266: 683b ldr r3, [r7, #0] 8001268: b2da uxtb r2, r3 800126a: 4908 ldr r1, [pc, #32] ; (800128c <__NVIC_SetPriority+0x50>) 800126c: 79fb ldrb r3, [r7, #7] 800126e: f003 030f and.w r3, r3, #15 8001272: 3b04 subs r3, #4 8001274: 0112 lsls r2, r2, #4 8001276: b2d2 uxtb r2, r2 8001278: 440b add r3, r1 800127a: 761a strb r2, [r3, #24] } 800127c: bf00 nop 800127e: 370c adds r7, #12 8001280: 46bd mov sp, r7 8001282: bc80 pop {r7} 8001284: 4770 bx lr 8001286: bf00 nop 8001288: e000e100 .word 0xe000e100 800128c: e000ed00 .word 0xe000ed00 08001290 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001290: b480 push {r7} 8001292: b089 sub sp, #36 ; 0x24 8001294: af00 add r7, sp, #0 8001296: 60f8 str r0, [r7, #12] 8001298: 60b9 str r1, [r7, #8] 800129a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800129c: 68fb ldr r3, [r7, #12] 800129e: f003 0307 and.w r3, r3, #7 80012a2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80012a4: 69fb ldr r3, [r7, #28] 80012a6: f1c3 0307 rsb r3, r3, #7 80012aa: 2b04 cmp r3, #4 80012ac: bf28 it cs 80012ae: 2304 movcs r3, #4 80012b0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80012b2: 69fb ldr r3, [r7, #28] 80012b4: 3304 adds r3, #4 80012b6: 2b06 cmp r3, #6 80012b8: d902 bls.n 80012c0 80012ba: 69fb ldr r3, [r7, #28] 80012bc: 3b03 subs r3, #3 80012be: e000 b.n 80012c2 80012c0: 2300 movs r3, #0 80012c2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80012c4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80012c8: 69bb ldr r3, [r7, #24] 80012ca: fa02 f303 lsl.w r3, r2, r3 80012ce: 43da mvns r2, r3 80012d0: 68bb ldr r3, [r7, #8] 80012d2: 401a ands r2, r3 80012d4: 697b ldr r3, [r7, #20] 80012d6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80012d8: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80012dc: 697b ldr r3, [r7, #20] 80012de: fa01 f303 lsl.w r3, r1, r3 80012e2: 43d9 mvns r1, r3 80012e4: 687b ldr r3, [r7, #4] 80012e6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80012e8: 4313 orrs r3, r2 ); } 80012ea: 4618 mov r0, r3 80012ec: 3724 adds r7, #36 ; 0x24 80012ee: 46bd mov sp, r7 80012f0: bc80 pop {r7} 80012f2: 4770 bx lr 080012f4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80012f4: b580 push {r7, lr} 80012f6: b082 sub sp, #8 80012f8: af00 add r7, sp, #0 80012fa: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80012fc: 687b ldr r3, [r7, #4] 80012fe: 3b01 subs r3, #1 8001300: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001304: d301 bcc.n 800130a { return (1UL); /* Reload value impossible */ 8001306: 2301 movs r3, #1 8001308: e00f b.n 800132a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800130a: 4a0a ldr r2, [pc, #40] ; (8001334 ) 800130c: 687b ldr r3, [r7, #4] 800130e: 3b01 subs r3, #1 8001310: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001312: 210f movs r1, #15 8001314: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001318: f7ff ff90 bl 800123c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800131c: 4b05 ldr r3, [pc, #20] ; (8001334 ) 800131e: 2200 movs r2, #0 8001320: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001322: 4b04 ldr r3, [pc, #16] ; (8001334 ) 8001324: 2207 movs r2, #7 8001326: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001328: 2300 movs r3, #0 } 800132a: 4618 mov r0, r3 800132c: 3708 adds r7, #8 800132e: 46bd mov sp, r7 8001330: bd80 pop {r7, pc} 8001332: bf00 nop 8001334: e000e010 .word 0xe000e010 08001338 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001338: b580 push {r7, lr} 800133a: b082 sub sp, #8 800133c: af00 add r7, sp, #0 800133e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001340: 6878 ldr r0, [r7, #4] 8001342: f7ff ff49 bl 80011d8 <__NVIC_SetPriorityGrouping> } 8001346: bf00 nop 8001348: 3708 adds r7, #8 800134a: 46bd mov sp, r7 800134c: bd80 pop {r7, pc} 0800134e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800134e: b580 push {r7, lr} 8001350: b086 sub sp, #24 8001352: af00 add r7, sp, #0 8001354: 4603 mov r3, r0 8001356: 60b9 str r1, [r7, #8] 8001358: 607a str r2, [r7, #4] 800135a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800135c: 2300 movs r3, #0 800135e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001360: f7ff ff5e bl 8001220 <__NVIC_GetPriorityGrouping> 8001364: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001366: 687a ldr r2, [r7, #4] 8001368: 68b9 ldr r1, [r7, #8] 800136a: 6978 ldr r0, [r7, #20] 800136c: f7ff ff90 bl 8001290 8001370: 4602 mov r2, r0 8001372: f997 300f ldrsb.w r3, [r7, #15] 8001376: 4611 mov r1, r2 8001378: 4618 mov r0, r3 800137a: f7ff ff5f bl 800123c <__NVIC_SetPriority> } 800137e: bf00 nop 8001380: 3718 adds r7, #24 8001382: 46bd mov sp, r7 8001384: bd80 pop {r7, pc} 08001386 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001386: b580 push {r7, lr} 8001388: b082 sub sp, #8 800138a: af00 add r7, sp, #0 800138c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800138e: 6878 ldr r0, [r7, #4] 8001390: f7ff ffb0 bl 80012f4 8001394: 4603 mov r3, r0 } 8001396: 4618 mov r0, r3 8001398: 3708 adds r7, #8 800139a: 46bd mov sp, r7 800139c: bd80 pop {r7, pc} ... 080013a0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80013a0: b480 push {r7} 80013a2: b08b sub sp, #44 ; 0x2c 80013a4: af00 add r7, sp, #0 80013a6: 6078 str r0, [r7, #4] 80013a8: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80013aa: 2300 movs r3, #0 80013ac: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80013ae: 2300 movs r3, #0 80013b0: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80013b2: e179 b.n 80016a8 { /* Get the IO position */ ioposition = (0x01uL << position); 80013b4: 2201 movs r2, #1 80013b6: 6a7b ldr r3, [r7, #36] ; 0x24 80013b8: fa02 f303 lsl.w r3, r2, r3 80013bc: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80013be: 683b ldr r3, [r7, #0] 80013c0: 681b ldr r3, [r3, #0] 80013c2: 69fa ldr r2, [r7, #28] 80013c4: 4013 ands r3, r2 80013c6: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80013c8: 69ba ldr r2, [r7, #24] 80013ca: 69fb ldr r3, [r7, #28] 80013cc: 429a cmp r2, r3 80013ce: f040 8168 bne.w 80016a2 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80013d2: 683b ldr r3, [r7, #0] 80013d4: 685b ldr r3, [r3, #4] 80013d6: 4aa0 ldr r2, [pc, #640] ; (8001658 ) 80013d8: 4293 cmp r3, r2 80013da: d05e beq.n 800149a 80013dc: 4a9e ldr r2, [pc, #632] ; (8001658 ) 80013de: 4293 cmp r3, r2 80013e0: d875 bhi.n 80014ce 80013e2: 4a9e ldr r2, [pc, #632] ; (800165c ) 80013e4: 4293 cmp r3, r2 80013e6: d058 beq.n 800149a 80013e8: 4a9c ldr r2, [pc, #624] ; (800165c ) 80013ea: 4293 cmp r3, r2 80013ec: d86f bhi.n 80014ce 80013ee: 4a9c ldr r2, [pc, #624] ; (8001660 ) 80013f0: 4293 cmp r3, r2 80013f2: d052 beq.n 800149a 80013f4: 4a9a ldr r2, [pc, #616] ; (8001660 ) 80013f6: 4293 cmp r3, r2 80013f8: d869 bhi.n 80014ce 80013fa: 4a9a ldr r2, [pc, #616] ; (8001664 ) 80013fc: 4293 cmp r3, r2 80013fe: d04c beq.n 800149a 8001400: 4a98 ldr r2, [pc, #608] ; (8001664 ) 8001402: 4293 cmp r3, r2 8001404: d863 bhi.n 80014ce 8001406: 4a98 ldr r2, [pc, #608] ; (8001668 ) 8001408: 4293 cmp r3, r2 800140a: d046 beq.n 800149a 800140c: 4a96 ldr r2, [pc, #600] ; (8001668 ) 800140e: 4293 cmp r3, r2 8001410: d85d bhi.n 80014ce 8001412: 2b12 cmp r3, #18 8001414: d82a bhi.n 800146c 8001416: 2b12 cmp r3, #18 8001418: d859 bhi.n 80014ce 800141a: a201 add r2, pc, #4 ; (adr r2, 8001420 ) 800141c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001420: 0800149b .word 0x0800149b 8001424: 08001475 .word 0x08001475 8001428: 08001487 .word 0x08001487 800142c: 080014c9 .word 0x080014c9 8001430: 080014cf .word 0x080014cf 8001434: 080014cf .word 0x080014cf 8001438: 080014cf .word 0x080014cf 800143c: 080014cf .word 0x080014cf 8001440: 080014cf .word 0x080014cf 8001444: 080014cf .word 0x080014cf 8001448: 080014cf .word 0x080014cf 800144c: 080014cf .word 0x080014cf 8001450: 080014cf .word 0x080014cf 8001454: 080014cf .word 0x080014cf 8001458: 080014cf .word 0x080014cf 800145c: 080014cf .word 0x080014cf 8001460: 080014cf .word 0x080014cf 8001464: 0800147d .word 0x0800147d 8001468: 08001491 .word 0x08001491 800146c: 4a7f ldr r2, [pc, #508] ; (800166c ) 800146e: 4293 cmp r3, r2 8001470: d013 beq.n 800149a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001472: e02c b.n 80014ce config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001474: 683b ldr r3, [r7, #0] 8001476: 68db ldr r3, [r3, #12] 8001478: 623b str r3, [r7, #32] break; 800147a: e029 b.n 80014d0 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800147c: 683b ldr r3, [r7, #0] 800147e: 68db ldr r3, [r3, #12] 8001480: 3304 adds r3, #4 8001482: 623b str r3, [r7, #32] break; 8001484: e024 b.n 80014d0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001486: 683b ldr r3, [r7, #0] 8001488: 68db ldr r3, [r3, #12] 800148a: 3308 adds r3, #8 800148c: 623b str r3, [r7, #32] break; 800148e: e01f b.n 80014d0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001490: 683b ldr r3, [r7, #0] 8001492: 68db ldr r3, [r3, #12] 8001494: 330c adds r3, #12 8001496: 623b str r3, [r7, #32] break; 8001498: e01a b.n 80014d0 if (GPIO_Init->Pull == GPIO_NOPULL) 800149a: 683b ldr r3, [r7, #0] 800149c: 689b ldr r3, [r3, #8] 800149e: 2b00 cmp r3, #0 80014a0: d102 bne.n 80014a8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80014a2: 2304 movs r3, #4 80014a4: 623b str r3, [r7, #32] break; 80014a6: e013 b.n 80014d0 else if (GPIO_Init->Pull == GPIO_PULLUP) 80014a8: 683b ldr r3, [r7, #0] 80014aa: 689b ldr r3, [r3, #8] 80014ac: 2b01 cmp r3, #1 80014ae: d105 bne.n 80014bc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80014b0: 2308 movs r3, #8 80014b2: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80014b4: 687b ldr r3, [r7, #4] 80014b6: 69fa ldr r2, [r7, #28] 80014b8: 611a str r2, [r3, #16] break; 80014ba: e009 b.n 80014d0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80014bc: 2308 movs r3, #8 80014be: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80014c0: 687b ldr r3, [r7, #4] 80014c2: 69fa ldr r2, [r7, #28] 80014c4: 615a str r2, [r3, #20] break; 80014c6: e003 b.n 80014d0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80014c8: 2300 movs r3, #0 80014ca: 623b str r3, [r7, #32] break; 80014cc: e000 b.n 80014d0 break; 80014ce: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80014d0: 69bb ldr r3, [r7, #24] 80014d2: 2bff cmp r3, #255 ; 0xff 80014d4: d801 bhi.n 80014da 80014d6: 687b ldr r3, [r7, #4] 80014d8: e001 b.n 80014de 80014da: 687b ldr r3, [r7, #4] 80014dc: 3304 adds r3, #4 80014de: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80014e0: 69bb ldr r3, [r7, #24] 80014e2: 2bff cmp r3, #255 ; 0xff 80014e4: d802 bhi.n 80014ec 80014e6: 6a7b ldr r3, [r7, #36] ; 0x24 80014e8: 009b lsls r3, r3, #2 80014ea: e002 b.n 80014f2 80014ec: 6a7b ldr r3, [r7, #36] ; 0x24 80014ee: 3b08 subs r3, #8 80014f0: 009b lsls r3, r3, #2 80014f2: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80014f4: 697b ldr r3, [r7, #20] 80014f6: 681a ldr r2, [r3, #0] 80014f8: 210f movs r1, #15 80014fa: 693b ldr r3, [r7, #16] 80014fc: fa01 f303 lsl.w r3, r1, r3 8001500: 43db mvns r3, r3 8001502: 401a ands r2, r3 8001504: 6a39 ldr r1, [r7, #32] 8001506: 693b ldr r3, [r7, #16] 8001508: fa01 f303 lsl.w r3, r1, r3 800150c: 431a orrs r2, r3 800150e: 697b ldr r3, [r7, #20] 8001510: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001512: 683b ldr r3, [r7, #0] 8001514: 685b ldr r3, [r3, #4] 8001516: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800151a: 2b00 cmp r3, #0 800151c: f000 80c1 beq.w 80016a2 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001520: 4b53 ldr r3, [pc, #332] ; (8001670 ) 8001522: 699b ldr r3, [r3, #24] 8001524: 4a52 ldr r2, [pc, #328] ; (8001670 ) 8001526: f043 0301 orr.w r3, r3, #1 800152a: 6193 str r3, [r2, #24] 800152c: 4b50 ldr r3, [pc, #320] ; (8001670 ) 800152e: 699b ldr r3, [r3, #24] 8001530: f003 0301 and.w r3, r3, #1 8001534: 60bb str r3, [r7, #8] 8001536: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001538: 4a4e ldr r2, [pc, #312] ; (8001674 ) 800153a: 6a7b ldr r3, [r7, #36] ; 0x24 800153c: 089b lsrs r3, r3, #2 800153e: 3302 adds r3, #2 8001540: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001544: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001546: 6a7b ldr r3, [r7, #36] ; 0x24 8001548: f003 0303 and.w r3, r3, #3 800154c: 009b lsls r3, r3, #2 800154e: 220f movs r2, #15 8001550: fa02 f303 lsl.w r3, r2, r3 8001554: 43db mvns r3, r3 8001556: 68fa ldr r2, [r7, #12] 8001558: 4013 ands r3, r2 800155a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800155c: 687b ldr r3, [r7, #4] 800155e: 4a46 ldr r2, [pc, #280] ; (8001678 ) 8001560: 4293 cmp r3, r2 8001562: d01f beq.n 80015a4 8001564: 687b ldr r3, [r7, #4] 8001566: 4a45 ldr r2, [pc, #276] ; (800167c ) 8001568: 4293 cmp r3, r2 800156a: d019 beq.n 80015a0 800156c: 687b ldr r3, [r7, #4] 800156e: 4a44 ldr r2, [pc, #272] ; (8001680 ) 8001570: 4293 cmp r3, r2 8001572: d013 beq.n 800159c 8001574: 687b ldr r3, [r7, #4] 8001576: 4a43 ldr r2, [pc, #268] ; (8001684 ) 8001578: 4293 cmp r3, r2 800157a: d00d beq.n 8001598 800157c: 687b ldr r3, [r7, #4] 800157e: 4a42 ldr r2, [pc, #264] ; (8001688 ) 8001580: 4293 cmp r3, r2 8001582: d007 beq.n 8001594 8001584: 687b ldr r3, [r7, #4] 8001586: 4a41 ldr r2, [pc, #260] ; (800168c ) 8001588: 4293 cmp r3, r2 800158a: d101 bne.n 8001590 800158c: 2305 movs r3, #5 800158e: e00a b.n 80015a6 8001590: 2306 movs r3, #6 8001592: e008 b.n 80015a6 8001594: 2304 movs r3, #4 8001596: e006 b.n 80015a6 8001598: 2303 movs r3, #3 800159a: e004 b.n 80015a6 800159c: 2302 movs r3, #2 800159e: e002 b.n 80015a6 80015a0: 2301 movs r3, #1 80015a2: e000 b.n 80015a6 80015a4: 2300 movs r3, #0 80015a6: 6a7a ldr r2, [r7, #36] ; 0x24 80015a8: f002 0203 and.w r2, r2, #3 80015ac: 0092 lsls r2, r2, #2 80015ae: 4093 lsls r3, r2 80015b0: 68fa ldr r2, [r7, #12] 80015b2: 4313 orrs r3, r2 80015b4: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80015b6: 492f ldr r1, [pc, #188] ; (8001674 ) 80015b8: 6a7b ldr r3, [r7, #36] ; 0x24 80015ba: 089b lsrs r3, r3, #2 80015bc: 3302 adds r3, #2 80015be: 68fa ldr r2, [r7, #12] 80015c0: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80015c4: 683b ldr r3, [r7, #0] 80015c6: 685b ldr r3, [r3, #4] 80015c8: f403 3380 and.w r3, r3, #65536 ; 0x10000 80015cc: 2b00 cmp r3, #0 80015ce: d006 beq.n 80015de { SET_BIT(EXTI->IMR, iocurrent); 80015d0: 4b2f ldr r3, [pc, #188] ; (8001690 ) 80015d2: 681a ldr r2, [r3, #0] 80015d4: 492e ldr r1, [pc, #184] ; (8001690 ) 80015d6: 69bb ldr r3, [r7, #24] 80015d8: 4313 orrs r3, r2 80015da: 600b str r3, [r1, #0] 80015dc: e006 b.n 80015ec } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80015de: 4b2c ldr r3, [pc, #176] ; (8001690 ) 80015e0: 681a ldr r2, [r3, #0] 80015e2: 69bb ldr r3, [r7, #24] 80015e4: 43db mvns r3, r3 80015e6: 492a ldr r1, [pc, #168] ; (8001690 ) 80015e8: 4013 ands r3, r2 80015ea: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80015ec: 683b ldr r3, [r7, #0] 80015ee: 685b ldr r3, [r3, #4] 80015f0: f403 3300 and.w r3, r3, #131072 ; 0x20000 80015f4: 2b00 cmp r3, #0 80015f6: d006 beq.n 8001606 { SET_BIT(EXTI->EMR, iocurrent); 80015f8: 4b25 ldr r3, [pc, #148] ; (8001690 ) 80015fa: 685a ldr r2, [r3, #4] 80015fc: 4924 ldr r1, [pc, #144] ; (8001690 ) 80015fe: 69bb ldr r3, [r7, #24] 8001600: 4313 orrs r3, r2 8001602: 604b str r3, [r1, #4] 8001604: e006 b.n 8001614 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8001606: 4b22 ldr r3, [pc, #136] ; (8001690 ) 8001608: 685a ldr r2, [r3, #4] 800160a: 69bb ldr r3, [r7, #24] 800160c: 43db mvns r3, r3 800160e: 4920 ldr r1, [pc, #128] ; (8001690 ) 8001610: 4013 ands r3, r2 8001612: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001614: 683b ldr r3, [r7, #0] 8001616: 685b ldr r3, [r3, #4] 8001618: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800161c: 2b00 cmp r3, #0 800161e: d006 beq.n 800162e { SET_BIT(EXTI->RTSR, iocurrent); 8001620: 4b1b ldr r3, [pc, #108] ; (8001690 ) 8001622: 689a ldr r2, [r3, #8] 8001624: 491a ldr r1, [pc, #104] ; (8001690 ) 8001626: 69bb ldr r3, [r7, #24] 8001628: 4313 orrs r3, r2 800162a: 608b str r3, [r1, #8] 800162c: e006 b.n 800163c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800162e: 4b18 ldr r3, [pc, #96] ; (8001690 ) 8001630: 689a ldr r2, [r3, #8] 8001632: 69bb ldr r3, [r7, #24] 8001634: 43db mvns r3, r3 8001636: 4916 ldr r1, [pc, #88] ; (8001690 ) 8001638: 4013 ands r3, r2 800163a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800163c: 683b ldr r3, [r7, #0] 800163e: 685b ldr r3, [r3, #4] 8001640: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001644: 2b00 cmp r3, #0 8001646: d025 beq.n 8001694 { SET_BIT(EXTI->FTSR, iocurrent); 8001648: 4b11 ldr r3, [pc, #68] ; (8001690 ) 800164a: 68da ldr r2, [r3, #12] 800164c: 4910 ldr r1, [pc, #64] ; (8001690 ) 800164e: 69bb ldr r3, [r7, #24] 8001650: 4313 orrs r3, r2 8001652: 60cb str r3, [r1, #12] 8001654: e025 b.n 80016a2 8001656: bf00 nop 8001658: 10320000 .word 0x10320000 800165c: 10310000 .word 0x10310000 8001660: 10220000 .word 0x10220000 8001664: 10210000 .word 0x10210000 8001668: 10120000 .word 0x10120000 800166c: 10110000 .word 0x10110000 8001670: 40021000 .word 0x40021000 8001674: 40010000 .word 0x40010000 8001678: 40010800 .word 0x40010800 800167c: 40010c00 .word 0x40010c00 8001680: 40011000 .word 0x40011000 8001684: 40011400 .word 0x40011400 8001688: 40011800 .word 0x40011800 800168c: 40011c00 .word 0x40011c00 8001690: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001694: 4b0b ldr r3, [pc, #44] ; (80016c4 ) 8001696: 68da ldr r2, [r3, #12] 8001698: 69bb ldr r3, [r7, #24] 800169a: 43db mvns r3, r3 800169c: 4909 ldr r1, [pc, #36] ; (80016c4 ) 800169e: 4013 ands r3, r2 80016a0: 60cb str r3, [r1, #12] } } } position++; 80016a2: 6a7b ldr r3, [r7, #36] ; 0x24 80016a4: 3301 adds r3, #1 80016a6: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80016a8: 683b ldr r3, [r7, #0] 80016aa: 681a ldr r2, [r3, #0] 80016ac: 6a7b ldr r3, [r7, #36] ; 0x24 80016ae: fa22 f303 lsr.w r3, r2, r3 80016b2: 2b00 cmp r3, #0 80016b4: f47f ae7e bne.w 80013b4 } } 80016b8: bf00 nop 80016ba: bf00 nop 80016bc: 372c adds r7, #44 ; 0x2c 80016be: 46bd mov sp, r7 80016c0: bc80 pop {r7} 80016c2: 4770 bx lr 80016c4: 40010400 .word 0x40010400 080016c8 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80016c8: b480 push {r7} 80016ca: b083 sub sp, #12 80016cc: af00 add r7, sp, #0 80016ce: 6078 str r0, [r7, #4] 80016d0: 460b mov r3, r1 80016d2: 807b strh r3, [r7, #2] 80016d4: 4613 mov r3, r2 80016d6: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80016d8: 787b ldrb r3, [r7, #1] 80016da: 2b00 cmp r3, #0 80016dc: d003 beq.n 80016e6 { GPIOx->BSRR = GPIO_Pin; 80016de: 887a ldrh r2, [r7, #2] 80016e0: 687b ldr r3, [r7, #4] 80016e2: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 80016e4: e003 b.n 80016ee GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 80016e6: 887b ldrh r3, [r7, #2] 80016e8: 041a lsls r2, r3, #16 80016ea: 687b ldr r3, [r7, #4] 80016ec: 611a str r2, [r3, #16] } 80016ee: bf00 nop 80016f0: 370c adds r7, #12 80016f2: 46bd mov sp, r7 80016f4: bc80 pop {r7} 80016f6: 4770 bx lr 080016f8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80016f8: b580 push {r7, lr} 80016fa: b086 sub sp, #24 80016fc: af00 add r7, sp, #0 80016fe: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001700: 687b ldr r3, [r7, #4] 8001702: 2b00 cmp r3, #0 8001704: d101 bne.n 800170a { return HAL_ERROR; 8001706: 2301 movs r3, #1 8001708: e26c b.n 8001be4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800170a: 687b ldr r3, [r7, #4] 800170c: 681b ldr r3, [r3, #0] 800170e: f003 0301 and.w r3, r3, #1 8001712: 2b00 cmp r3, #0 8001714: f000 8087 beq.w 8001826 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8001718: 4b92 ldr r3, [pc, #584] ; (8001964 ) 800171a: 685b ldr r3, [r3, #4] 800171c: f003 030c and.w r3, r3, #12 8001720: 2b04 cmp r3, #4 8001722: d00c beq.n 800173e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001724: 4b8f ldr r3, [pc, #572] ; (8001964 ) 8001726: 685b ldr r3, [r3, #4] 8001728: f003 030c and.w r3, r3, #12 800172c: 2b08 cmp r3, #8 800172e: d112 bne.n 8001756 8001730: 4b8c ldr r3, [pc, #560] ; (8001964 ) 8001732: 685b ldr r3, [r3, #4] 8001734: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001738: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800173c: d10b bne.n 8001756 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800173e: 4b89 ldr r3, [pc, #548] ; (8001964 ) 8001740: 681b ldr r3, [r3, #0] 8001742: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001746: 2b00 cmp r3, #0 8001748: d06c beq.n 8001824 800174a: 687b ldr r3, [r7, #4] 800174c: 685b ldr r3, [r3, #4] 800174e: 2b00 cmp r3, #0 8001750: d168 bne.n 8001824 { return HAL_ERROR; 8001752: 2301 movs r3, #1 8001754: e246 b.n 8001be4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001756: 687b ldr r3, [r7, #4] 8001758: 685b ldr r3, [r3, #4] 800175a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800175e: d106 bne.n 800176e 8001760: 4b80 ldr r3, [pc, #512] ; (8001964 ) 8001762: 681b ldr r3, [r3, #0] 8001764: 4a7f ldr r2, [pc, #508] ; (8001964 ) 8001766: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800176a: 6013 str r3, [r2, #0] 800176c: e02e b.n 80017cc 800176e: 687b ldr r3, [r7, #4] 8001770: 685b ldr r3, [r3, #4] 8001772: 2b00 cmp r3, #0 8001774: d10c bne.n 8001790 8001776: 4b7b ldr r3, [pc, #492] ; (8001964 ) 8001778: 681b ldr r3, [r3, #0] 800177a: 4a7a ldr r2, [pc, #488] ; (8001964 ) 800177c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001780: 6013 str r3, [r2, #0] 8001782: 4b78 ldr r3, [pc, #480] ; (8001964 ) 8001784: 681b ldr r3, [r3, #0] 8001786: 4a77 ldr r2, [pc, #476] ; (8001964 ) 8001788: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800178c: 6013 str r3, [r2, #0] 800178e: e01d b.n 80017cc 8001790: 687b ldr r3, [r7, #4] 8001792: 685b ldr r3, [r3, #4] 8001794: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8001798: d10c bne.n 80017b4 800179a: 4b72 ldr r3, [pc, #456] ; (8001964 ) 800179c: 681b ldr r3, [r3, #0] 800179e: 4a71 ldr r2, [pc, #452] ; (8001964 ) 80017a0: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80017a4: 6013 str r3, [r2, #0] 80017a6: 4b6f ldr r3, [pc, #444] ; (8001964 ) 80017a8: 681b ldr r3, [r3, #0] 80017aa: 4a6e ldr r2, [pc, #440] ; (8001964 ) 80017ac: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80017b0: 6013 str r3, [r2, #0] 80017b2: e00b b.n 80017cc 80017b4: 4b6b ldr r3, [pc, #428] ; (8001964 ) 80017b6: 681b ldr r3, [r3, #0] 80017b8: 4a6a ldr r2, [pc, #424] ; (8001964 ) 80017ba: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80017be: 6013 str r3, [r2, #0] 80017c0: 4b68 ldr r3, [pc, #416] ; (8001964 ) 80017c2: 681b ldr r3, [r3, #0] 80017c4: 4a67 ldr r2, [pc, #412] ; (8001964 ) 80017c6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80017ca: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80017cc: 687b ldr r3, [r7, #4] 80017ce: 685b ldr r3, [r3, #4] 80017d0: 2b00 cmp r3, #0 80017d2: d013 beq.n 80017fc { /* Get Start Tick */ tickstart = HAL_GetTick(); 80017d4: f7ff fcd2 bl 800117c 80017d8: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80017da: e008 b.n 80017ee { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80017dc: f7ff fcce bl 800117c 80017e0: 4602 mov r2, r0 80017e2: 693b ldr r3, [r7, #16] 80017e4: 1ad3 subs r3, r2, r3 80017e6: 2b64 cmp r3, #100 ; 0x64 80017e8: d901 bls.n 80017ee { return HAL_TIMEOUT; 80017ea: 2303 movs r3, #3 80017ec: e1fa b.n 8001be4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80017ee: 4b5d ldr r3, [pc, #372] ; (8001964 ) 80017f0: 681b ldr r3, [r3, #0] 80017f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80017f6: 2b00 cmp r3, #0 80017f8: d0f0 beq.n 80017dc 80017fa: e014 b.n 8001826 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80017fc: f7ff fcbe bl 800117c 8001800: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001802: e008 b.n 8001816 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001804: f7ff fcba bl 800117c 8001808: 4602 mov r2, r0 800180a: 693b ldr r3, [r7, #16] 800180c: 1ad3 subs r3, r2, r3 800180e: 2b64 cmp r3, #100 ; 0x64 8001810: d901 bls.n 8001816 { return HAL_TIMEOUT; 8001812: 2303 movs r3, #3 8001814: e1e6 b.n 8001be4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001816: 4b53 ldr r3, [pc, #332] ; (8001964 ) 8001818: 681b ldr r3, [r3, #0] 800181a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800181e: 2b00 cmp r3, #0 8001820: d1f0 bne.n 8001804 8001822: e000 b.n 8001826 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001824: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001826: 687b ldr r3, [r7, #4] 8001828: 681b ldr r3, [r3, #0] 800182a: f003 0302 and.w r3, r3, #2 800182e: 2b00 cmp r3, #0 8001830: d063 beq.n 80018fa /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001832: 4b4c ldr r3, [pc, #304] ; (8001964 ) 8001834: 685b ldr r3, [r3, #4] 8001836: f003 030c and.w r3, r3, #12 800183a: 2b00 cmp r3, #0 800183c: d00b beq.n 8001856 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800183e: 4b49 ldr r3, [pc, #292] ; (8001964 ) 8001840: 685b ldr r3, [r3, #4] 8001842: f003 030c and.w r3, r3, #12 8001846: 2b08 cmp r3, #8 8001848: d11c bne.n 8001884 800184a: 4b46 ldr r3, [pc, #280] ; (8001964 ) 800184c: 685b ldr r3, [r3, #4] 800184e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001852: 2b00 cmp r3, #0 8001854: d116 bne.n 8001884 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001856: 4b43 ldr r3, [pc, #268] ; (8001964 ) 8001858: 681b ldr r3, [r3, #0] 800185a: f003 0302 and.w r3, r3, #2 800185e: 2b00 cmp r3, #0 8001860: d005 beq.n 800186e 8001862: 687b ldr r3, [r7, #4] 8001864: 691b ldr r3, [r3, #16] 8001866: 2b01 cmp r3, #1 8001868: d001 beq.n 800186e { return HAL_ERROR; 800186a: 2301 movs r3, #1 800186c: e1ba b.n 8001be4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800186e: 4b3d ldr r3, [pc, #244] ; (8001964 ) 8001870: 681b ldr r3, [r3, #0] 8001872: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8001876: 687b ldr r3, [r7, #4] 8001878: 695b ldr r3, [r3, #20] 800187a: 00db lsls r3, r3, #3 800187c: 4939 ldr r1, [pc, #228] ; (8001964 ) 800187e: 4313 orrs r3, r2 8001880: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001882: e03a b.n 80018fa } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001884: 687b ldr r3, [r7, #4] 8001886: 691b ldr r3, [r3, #16] 8001888: 2b00 cmp r3, #0 800188a: d020 beq.n 80018ce { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800188c: 4b36 ldr r3, [pc, #216] ; (8001968 ) 800188e: 2201 movs r2, #1 8001890: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001892: f7ff fc73 bl 800117c 8001896: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001898: e008 b.n 80018ac { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800189a: f7ff fc6f bl 800117c 800189e: 4602 mov r2, r0 80018a0: 693b ldr r3, [r7, #16] 80018a2: 1ad3 subs r3, r2, r3 80018a4: 2b02 cmp r3, #2 80018a6: d901 bls.n 80018ac { return HAL_TIMEOUT; 80018a8: 2303 movs r3, #3 80018aa: e19b b.n 8001be4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80018ac: 4b2d ldr r3, [pc, #180] ; (8001964 ) 80018ae: 681b ldr r3, [r3, #0] 80018b0: f003 0302 and.w r3, r3, #2 80018b4: 2b00 cmp r3, #0 80018b6: d0f0 beq.n 800189a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80018b8: 4b2a ldr r3, [pc, #168] ; (8001964 ) 80018ba: 681b ldr r3, [r3, #0] 80018bc: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80018c0: 687b ldr r3, [r7, #4] 80018c2: 695b ldr r3, [r3, #20] 80018c4: 00db lsls r3, r3, #3 80018c6: 4927 ldr r1, [pc, #156] ; (8001964 ) 80018c8: 4313 orrs r3, r2 80018ca: 600b str r3, [r1, #0] 80018cc: e015 b.n 80018fa } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80018ce: 4b26 ldr r3, [pc, #152] ; (8001968 ) 80018d0: 2200 movs r2, #0 80018d2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80018d4: f7ff fc52 bl 800117c 80018d8: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80018da: e008 b.n 80018ee { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80018dc: f7ff fc4e bl 800117c 80018e0: 4602 mov r2, r0 80018e2: 693b ldr r3, [r7, #16] 80018e4: 1ad3 subs r3, r2, r3 80018e6: 2b02 cmp r3, #2 80018e8: d901 bls.n 80018ee { return HAL_TIMEOUT; 80018ea: 2303 movs r3, #3 80018ec: e17a b.n 8001be4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80018ee: 4b1d ldr r3, [pc, #116] ; (8001964 ) 80018f0: 681b ldr r3, [r3, #0] 80018f2: f003 0302 and.w r3, r3, #2 80018f6: 2b00 cmp r3, #0 80018f8: d1f0 bne.n 80018dc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80018fa: 687b ldr r3, [r7, #4] 80018fc: 681b ldr r3, [r3, #0] 80018fe: f003 0308 and.w r3, r3, #8 8001902: 2b00 cmp r3, #0 8001904: d03a beq.n 800197c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001906: 687b ldr r3, [r7, #4] 8001908: 699b ldr r3, [r3, #24] 800190a: 2b00 cmp r3, #0 800190c: d019 beq.n 8001942 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800190e: 4b17 ldr r3, [pc, #92] ; (800196c ) 8001910: 2201 movs r2, #1 8001912: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001914: f7ff fc32 bl 800117c 8001918: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800191a: e008 b.n 800192e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800191c: f7ff fc2e bl 800117c 8001920: 4602 mov r2, r0 8001922: 693b ldr r3, [r7, #16] 8001924: 1ad3 subs r3, r2, r3 8001926: 2b02 cmp r3, #2 8001928: d901 bls.n 800192e { return HAL_TIMEOUT; 800192a: 2303 movs r3, #3 800192c: e15a b.n 8001be4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800192e: 4b0d ldr r3, [pc, #52] ; (8001964 ) 8001930: 6a5b ldr r3, [r3, #36] ; 0x24 8001932: f003 0302 and.w r3, r3, #2 8001936: 2b00 cmp r3, #0 8001938: d0f0 beq.n 800191c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800193a: 2001 movs r0, #1 800193c: f000 faa6 bl 8001e8c 8001940: e01c b.n 800197c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001942: 4b0a ldr r3, [pc, #40] ; (800196c ) 8001944: 2200 movs r2, #0 8001946: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001948: f7ff fc18 bl 800117c 800194c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800194e: e00f b.n 8001970 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001950: f7ff fc14 bl 800117c 8001954: 4602 mov r2, r0 8001956: 693b ldr r3, [r7, #16] 8001958: 1ad3 subs r3, r2, r3 800195a: 2b02 cmp r3, #2 800195c: d908 bls.n 8001970 { return HAL_TIMEOUT; 800195e: 2303 movs r3, #3 8001960: e140 b.n 8001be4 8001962: bf00 nop 8001964: 40021000 .word 0x40021000 8001968: 42420000 .word 0x42420000 800196c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001970: 4b9e ldr r3, [pc, #632] ; (8001bec ) 8001972: 6a5b ldr r3, [r3, #36] ; 0x24 8001974: f003 0302 and.w r3, r3, #2 8001978: 2b00 cmp r3, #0 800197a: d1e9 bne.n 8001950 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800197c: 687b ldr r3, [r7, #4] 800197e: 681b ldr r3, [r3, #0] 8001980: f003 0304 and.w r3, r3, #4 8001984: 2b00 cmp r3, #0 8001986: f000 80a6 beq.w 8001ad6 { FlagStatus pwrclkchanged = RESET; 800198a: 2300 movs r3, #0 800198c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800198e: 4b97 ldr r3, [pc, #604] ; (8001bec ) 8001990: 69db ldr r3, [r3, #28] 8001992: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001996: 2b00 cmp r3, #0 8001998: d10d bne.n 80019b6 { __HAL_RCC_PWR_CLK_ENABLE(); 800199a: 4b94 ldr r3, [pc, #592] ; (8001bec ) 800199c: 69db ldr r3, [r3, #28] 800199e: 4a93 ldr r2, [pc, #588] ; (8001bec ) 80019a0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80019a4: 61d3 str r3, [r2, #28] 80019a6: 4b91 ldr r3, [pc, #580] ; (8001bec ) 80019a8: 69db ldr r3, [r3, #28] 80019aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80019ae: 60bb str r3, [r7, #8] 80019b0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80019b2: 2301 movs r3, #1 80019b4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80019b6: 4b8e ldr r3, [pc, #568] ; (8001bf0 ) 80019b8: 681b ldr r3, [r3, #0] 80019ba: f403 7380 and.w r3, r3, #256 ; 0x100 80019be: 2b00 cmp r3, #0 80019c0: d118 bne.n 80019f4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80019c2: 4b8b ldr r3, [pc, #556] ; (8001bf0 ) 80019c4: 681b ldr r3, [r3, #0] 80019c6: 4a8a ldr r2, [pc, #552] ; (8001bf0 ) 80019c8: f443 7380 orr.w r3, r3, #256 ; 0x100 80019cc: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80019ce: f7ff fbd5 bl 800117c 80019d2: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80019d4: e008 b.n 80019e8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80019d6: f7ff fbd1 bl 800117c 80019da: 4602 mov r2, r0 80019dc: 693b ldr r3, [r7, #16] 80019de: 1ad3 subs r3, r2, r3 80019e0: 2b64 cmp r3, #100 ; 0x64 80019e2: d901 bls.n 80019e8 { return HAL_TIMEOUT; 80019e4: 2303 movs r3, #3 80019e6: e0fd b.n 8001be4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80019e8: 4b81 ldr r3, [pc, #516] ; (8001bf0 ) 80019ea: 681b ldr r3, [r3, #0] 80019ec: f403 7380 and.w r3, r3, #256 ; 0x100 80019f0: 2b00 cmp r3, #0 80019f2: d0f0 beq.n 80019d6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80019f4: 687b ldr r3, [r7, #4] 80019f6: 68db ldr r3, [r3, #12] 80019f8: 2b01 cmp r3, #1 80019fa: d106 bne.n 8001a0a 80019fc: 4b7b ldr r3, [pc, #492] ; (8001bec ) 80019fe: 6a1b ldr r3, [r3, #32] 8001a00: 4a7a ldr r2, [pc, #488] ; (8001bec ) 8001a02: f043 0301 orr.w r3, r3, #1 8001a06: 6213 str r3, [r2, #32] 8001a08: e02d b.n 8001a66 8001a0a: 687b ldr r3, [r7, #4] 8001a0c: 68db ldr r3, [r3, #12] 8001a0e: 2b00 cmp r3, #0 8001a10: d10c bne.n 8001a2c 8001a12: 4b76 ldr r3, [pc, #472] ; (8001bec ) 8001a14: 6a1b ldr r3, [r3, #32] 8001a16: 4a75 ldr r2, [pc, #468] ; (8001bec ) 8001a18: f023 0301 bic.w r3, r3, #1 8001a1c: 6213 str r3, [r2, #32] 8001a1e: 4b73 ldr r3, [pc, #460] ; (8001bec ) 8001a20: 6a1b ldr r3, [r3, #32] 8001a22: 4a72 ldr r2, [pc, #456] ; (8001bec ) 8001a24: f023 0304 bic.w r3, r3, #4 8001a28: 6213 str r3, [r2, #32] 8001a2a: e01c b.n 8001a66 8001a2c: 687b ldr r3, [r7, #4] 8001a2e: 68db ldr r3, [r3, #12] 8001a30: 2b05 cmp r3, #5 8001a32: d10c bne.n 8001a4e 8001a34: 4b6d ldr r3, [pc, #436] ; (8001bec ) 8001a36: 6a1b ldr r3, [r3, #32] 8001a38: 4a6c ldr r2, [pc, #432] ; (8001bec ) 8001a3a: f043 0304 orr.w r3, r3, #4 8001a3e: 6213 str r3, [r2, #32] 8001a40: 4b6a ldr r3, [pc, #424] ; (8001bec ) 8001a42: 6a1b ldr r3, [r3, #32] 8001a44: 4a69 ldr r2, [pc, #420] ; (8001bec ) 8001a46: f043 0301 orr.w r3, r3, #1 8001a4a: 6213 str r3, [r2, #32] 8001a4c: e00b b.n 8001a66 8001a4e: 4b67 ldr r3, [pc, #412] ; (8001bec ) 8001a50: 6a1b ldr r3, [r3, #32] 8001a52: 4a66 ldr r2, [pc, #408] ; (8001bec ) 8001a54: f023 0301 bic.w r3, r3, #1 8001a58: 6213 str r3, [r2, #32] 8001a5a: 4b64 ldr r3, [pc, #400] ; (8001bec ) 8001a5c: 6a1b ldr r3, [r3, #32] 8001a5e: 4a63 ldr r2, [pc, #396] ; (8001bec ) 8001a60: f023 0304 bic.w r3, r3, #4 8001a64: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001a66: 687b ldr r3, [r7, #4] 8001a68: 68db ldr r3, [r3, #12] 8001a6a: 2b00 cmp r3, #0 8001a6c: d015 beq.n 8001a9a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a6e: f7ff fb85 bl 800117c 8001a72: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001a74: e00a b.n 8001a8c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001a76: f7ff fb81 bl 800117c 8001a7a: 4602 mov r2, r0 8001a7c: 693b ldr r3, [r7, #16] 8001a7e: 1ad3 subs r3, r2, r3 8001a80: f241 3288 movw r2, #5000 ; 0x1388 8001a84: 4293 cmp r3, r2 8001a86: d901 bls.n 8001a8c { return HAL_TIMEOUT; 8001a88: 2303 movs r3, #3 8001a8a: e0ab b.n 8001be4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001a8c: 4b57 ldr r3, [pc, #348] ; (8001bec