: /** * @brief The application entry point. * @retval int */ int main(void) { 8001108: b580 push {r7, lr} 800110a: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800110c: f000 fb72 bl 80017f4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001110: f000 f809 bl 8001126 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001114: f000 f87a bl 800120c MX_FSMC_Init(); 8001118: f000 f91e bl 8001358 MX_I2C2_Init(); 800111c: f000 f848 bl 80011b0 /* USER CODE BEGIN 2 */ main_app(); 8001120: f004 f862 bl 80051e8 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8001124: e7fe b.n 8001124 08001126 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001126: b580 push {r7, lr} 8001128: b090 sub sp, #64 ; 0x40 800112a: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800112c: f107 0318 add.w r3, r7, #24 8001130: 2228 movs r2, #40 ; 0x28 8001132: 2100 movs r1, #0 8001134: 4618 mov r0, r3 8001136: f004 fbc1 bl 80058bc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800113a: 1d3b adds r3, r7, #4 800113c: 2200 movs r2, #0 800113e: 601a str r2, [r3, #0] 8001140: 605a str r2, [r3, #4] 8001142: 609a str r2, [r3, #8] 8001144: 60da str r2, [r3, #12] 8001146: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001148: 2301 movs r3, #1 800114a: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800114c: f44f 3380 mov.w r3, #65536 ; 0x10000 8001150: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8001152: 2300 movs r3, #0 8001154: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001156: 2301 movs r3, #1 8001158: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800115a: 2302 movs r3, #2 800115c: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800115e: f44f 3380 mov.w r3, #65536 ; 0x10000 8001162: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8001164: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8001168: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800116a: f107 0318 add.w r3, r7, #24 800116e: 4618 mov r0, r3 8001170: f001 fe6e bl 8002e50 8001174: 4603 mov r3, r0 8001176: 2b00 cmp r3, #0 8001178: d001 beq.n 800117e { Error_Handler(); 800117a: f000 f951 bl 8001420 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800117e: 230f movs r3, #15 8001180: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8001182: 2302 movs r3, #2 8001184: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001186: 2300 movs r3, #0 8001188: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800118a: f44f 6380 mov.w r3, #1024 ; 0x400 800118e: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001190: 2300 movs r3, #0 8001192: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001194: 1d3b adds r3, r7, #4 8001196: 2102 movs r1, #2 8001198: 4618 mov r0, r3 800119a: f002 f8d9 bl 8003350 800119e: 4603 mov r3, r0 80011a0: 2b00 cmp r3, #0 80011a2: d001 beq.n 80011a8 { Error_Handler(); 80011a4: f000 f93c bl 8001420 } } 80011a8: bf00 nop 80011aa: 3740 adds r7, #64 ; 0x40 80011ac: 46bd mov sp, r7 80011ae: bd80 pop {r7, pc} 080011b0 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 80011b0: b580 push {r7, lr} 80011b2: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 80011b4: 4b12 ldr r3, [pc, #72] ; (8001200 ) 80011b6: 4a13 ldr r2, [pc, #76] ; (8001204 ) 80011b8: 601a str r2, [r3, #0] hi2c2.Init.ClockSpeed = 100000; 80011ba: 4b11 ldr r3, [pc, #68] ; (8001200 ) 80011bc: 4a12 ldr r2, [pc, #72] ; (8001208 ) 80011be: 605a str r2, [r3, #4] hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2; 80011c0: 4b0f ldr r3, [pc, #60] ; (8001200 ) 80011c2: 2200 movs r2, #0 80011c4: 609a str r2, [r3, #8] hi2c2.Init.OwnAddress1 = 0; 80011c6: 4b0e ldr r3, [pc, #56] ; (8001200 ) 80011c8: 2200 movs r2, #0 80011ca: 60da str r2, [r3, #12] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80011cc: 4b0c ldr r3, [pc, #48] ; (8001200 ) 80011ce: f44f 4280 mov.w r2, #16384 ; 0x4000 80011d2: 611a str r2, [r3, #16] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80011d4: 4b0a ldr r3, [pc, #40] ; (8001200 ) 80011d6: 2200 movs r2, #0 80011d8: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2 = 0; 80011da: 4b09 ldr r3, [pc, #36] ; (8001200 ) 80011dc: 2200 movs r2, #0 80011de: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80011e0: 4b07 ldr r3, [pc, #28] ; (8001200 ) 80011e2: 2200 movs r2, #0 80011e4: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80011e6: 4b06 ldr r3, [pc, #24] ; (8001200 ) 80011e8: 2200 movs r2, #0 80011ea: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 80011ec: 4804 ldr r0, [pc, #16] ; (8001200 ) 80011ee: f000 fe2f bl 8001e50 80011f2: 4603 mov r3, r0 80011f4: 2b00 cmp r3, #0 80011f6: d001 beq.n 80011fc { Error_Handler(); 80011f8: f000 f912 bl 8001420 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 80011fc: bf00 nop 80011fe: bd80 pop {r7, pc} 8001200: 20000208 .word 0x20000208 8001204: 40005800 .word 0x40005800 8001208: 000186a0 .word 0x000186a0 0800120c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800120c: b580 push {r7, lr} 800120e: b08a sub sp, #40 ; 0x28 8001210: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001212: f107 0318 add.w r3, r7, #24 8001216: 2200 movs r2, #0 8001218: 601a str r2, [r3, #0] 800121a: 605a str r2, [r3, #4] 800121c: 609a str r2, [r3, #8] 800121e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8001220: 4b4a ldr r3, [pc, #296] ; (800134c ) 8001222: 699b ldr r3, [r3, #24] 8001224: 4a49 ldr r2, [pc, #292] ; (800134c ) 8001226: f043 0380 orr.w r3, r3, #128 ; 0x80 800122a: 6193 str r3, [r2, #24] 800122c: 4b47 ldr r3, [pc, #284] ; (800134c ) 800122e: 699b ldr r3, [r3, #24] 8001230: f003 0380 and.w r3, r3, #128 ; 0x80 8001234: 617b str r3, [r7, #20] 8001236: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001238: 4b44 ldr r3, [pc, #272] ; (800134c ) 800123a: 699b ldr r3, [r3, #24] 800123c: 4a43 ldr r2, [pc, #268] ; (800134c ) 800123e: f043 0308 orr.w r3, r3, #8 8001242: 6193 str r3, [r2, #24] 8001244: 4b41 ldr r3, [pc, #260] ; (800134c ) 8001246: 699b ldr r3, [r3, #24] 8001248: f003 0308 and.w r3, r3, #8 800124c: 613b str r3, [r7, #16] 800124e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 8001250: 4b3e ldr r3, [pc, #248] ; (800134c ) 8001252: 699b ldr r3, [r3, #24] 8001254: 4a3d ldr r2, [pc, #244] ; (800134c ) 8001256: f443 7380 orr.w r3, r3, #256 ; 0x100 800125a: 6193 str r3, [r2, #24] 800125c: 4b3b ldr r3, [pc, #236] ; (800134c ) 800125e: 699b ldr r3, [r3, #24] 8001260: f403 7380 and.w r3, r3, #256 ; 0x100 8001264: 60fb str r3, [r7, #12] 8001266: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001268: 4b38 ldr r3, [pc, #224] ; (800134c ) 800126a: 699b ldr r3, [r3, #24] 800126c: 4a37 ldr r2, [pc, #220] ; (800134c ) 800126e: f043 0340 orr.w r3, r3, #64 ; 0x40 8001272: 6193 str r3, [r2, #24] 8001274: 4b35 ldr r3, [pc, #212] ; (800134c ) 8001276: 699b ldr r3, [r3, #24] 8001278: f003 0340 and.w r3, r3, #64 ; 0x40 800127c: 60bb str r3, [r7, #8] 800127e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001280: 4b32 ldr r3, [pc, #200] ; (800134c ) 8001282: 699b ldr r3, [r3, #24] 8001284: 4a31 ldr r2, [pc, #196] ; (800134c ) 8001286: f043 0320 orr.w r3, r3, #32 800128a: 6193 str r3, [r2, #24] 800128c: 4b2f ldr r3, [pc, #188] ; (800134c ) 800128e: 699b ldr r3, [r3, #24] 8001290: f003 0320 and.w r3, r3, #32 8001294: 607b str r3, [r7, #4] 8001296: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TDIN_GPIO_Port, TDIN_Pin, GPIO_PIN_SET); 8001298: 2201 movs r2, #1 800129a: f44f 7100 mov.w r1, #512 ; 0x200 800129e: 482c ldr r0, [pc, #176] ; (8001350 ) 80012a0: f000 fdbd bl 8001e1e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); 80012a4: 2200 movs r2, #0 80012a6: 2101 movs r1, #1 80012a8: 482a ldr r0, [pc, #168] ; (8001354 ) 80012aa: f000 fdb8 bl 8001e1e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, TCLK_Pin|TCS_Pin, GPIO_PIN_SET); 80012ae: 2201 movs r2, #1 80012b0: 2106 movs r1, #6 80012b2: 4828 ldr r0, [pc, #160] ; (8001354 ) 80012b4: f000 fdb3 bl 8001e1e /*Configure GPIO pin : TDOUT_Pin */ GPIO_InitStruct.Pin = TDOUT_Pin; 80012b8: f44f 7380 mov.w r3, #256 ; 0x100 80012bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80012be: 2300 movs r3, #0 80012c0: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012c2: 2300 movs r3, #0 80012c4: 623b str r3, [r7, #32] HAL_GPIO_Init(TDOUT_GPIO_Port, &GPIO_InitStruct); 80012c6: f107 0318 add.w r3, r7, #24 80012ca: 4619 mov r1, r3 80012cc: 4820 ldr r0, [pc, #128] ; (8001350 ) 80012ce: f000 fbfb bl 8001ac8 /*Configure GPIO pin : TDIN_Pin */ GPIO_InitStruct.Pin = TDIN_Pin; 80012d2: f44f 7300 mov.w r3, #512 ; 0x200 80012d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80012d8: 2301 movs r3, #1 80012da: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012dc: 2300 movs r3, #0 80012de: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80012e0: 2303 movs r3, #3 80012e2: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(TDIN_GPIO_Port, &GPIO_InitStruct); 80012e4: f107 0318 add.w r3, r7, #24 80012e8: 4619 mov r1, r3 80012ea: 4819 ldr r0, [pc, #100] ; (8001350 ) 80012ec: f000 fbec bl 8001ac8 /*Configure GPIO pin : TPEN_Pin */ GPIO_InitStruct.Pin = TPEN_Pin; 80012f0: f44f 6380 mov.w r3, #1024 ; 0x400 80012f4: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80012f6: 2300 movs r3, #0 80012f8: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 80012fa: 2301 movs r3, #1 80012fc: 623b str r3, [r7, #32] HAL_GPIO_Init(TPEN_GPIO_Port, &GPIO_InitStruct); 80012fe: f107 0318 add.w r3, r7, #24 8001302: 4619 mov r1, r3 8001304: 4812 ldr r0, [pc, #72] ; (8001350 ) 8001306: f000 fbdf bl 8001ac8 /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 800130a: 2301 movs r3, #1 800130c: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800130e: 2301 movs r3, #1 8001310: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001312: 2300 movs r3, #0 8001314: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001316: 2302 movs r3, #2 8001318: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 800131a: f107 0318 add.w r3, r7, #24 800131e: 4619 mov r1, r3 8001320: 480c ldr r0, [pc, #48] ; (8001354 ) 8001322: f000 fbd1 bl 8001ac8 /*Configure GPIO pins : TCLK_Pin TCS_Pin */ GPIO_InitStruct.Pin = TCLK_Pin|TCS_Pin; 8001326: 2306 movs r3, #6 8001328: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800132a: 2301 movs r3, #1 800132c: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800132e: 2300 movs r3, #0 8001330: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001332: 2303 movs r3, #3 8001334: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001336: f107 0318 add.w r3, r7, #24 800133a: 4619 mov r1, r3 800133c: 4805 ldr r0, [pc, #20] ; (8001354 ) 800133e: f000 fbc3 bl 8001ac8 } 8001342: bf00 nop 8001344: 3728 adds r7, #40 ; 0x28 8001346: 46bd mov sp, r7 8001348: bd80 pop {r7, pc} 800134a: bf00 nop 800134c: 40021000 .word 0x40021000 8001350: 40011c00 .word 0x40011c00 8001354: 40010c00 .word 0x40010c00 08001358 : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 8001358: b580 push {r7, lr} 800135a: b088 sub sp, #32 800135c: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 800135e: 1d3b adds r3, r7, #4 8001360: 2200 movs r2, #0 8001362: 601a str r2, [r3, #0] 8001364: 605a str r2, [r3, #4] 8001366: 609a str r2, [r3, #8] 8001368: 60da str r2, [r3, #12] 800136a: 611a str r2, [r3, #16] 800136c: 615a str r2, [r3, #20] 800136e: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 8001370: 4b28 ldr r3, [pc, #160] ; (8001414 ) 8001372: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 8001376: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 8001378: 4b26 ldr r3, [pc, #152] ; (8001414 ) 800137a: 4a27 ldr r2, [pc, #156] ; (8001418 ) 800137c: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 800137e: 4b25 ldr r3, [pc, #148] ; (8001414 ) 8001380: 2206 movs r2, #6 8001382: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 8001384: 4b23 ldr r3, [pc, #140] ; (8001414 ) 8001386: 2200 movs r2, #0 8001388: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 800138a: 4b22 ldr r3, [pc, #136] ; (8001414 ) 800138c: 2200 movs r2, #0 800138e: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 8001390: 4b20 ldr r3, [pc, #128] ; (8001414 ) 8001392: 2210 movs r2, #16 8001394: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 8001396: 4b1f ldr r3, [pc, #124] ; (8001414 ) 8001398: 2200 movs r2, #0 800139a: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 800139c: 4b1d ldr r3, [pc, #116] ; (8001414 ) 800139e: 2200 movs r2, #0 80013a0: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 80013a2: 4b1c ldr r3, [pc, #112] ; (8001414 ) 80013a4: 2200 movs r2, #0 80013a6: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 80013a8: 4b1a ldr r3, [pc, #104] ; (8001414 ) 80013aa: 2200 movs r2, #0 80013ac: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 80013ae: 4b19 ldr r3, [pc, #100] ; (8001414 ) 80013b0: f44f 5280 mov.w r2, #4096 ; 0x1000 80013b4: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 80013b6: 4b17 ldr r3, [pc, #92] ; (8001414 ) 80013b8: 2200 movs r2, #0 80013ba: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 80013bc: 4b15 ldr r3, [pc, #84] ; (8001414 ) 80013be: 2200 movs r2, #0 80013c0: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 80013c2: 4b14 ldr r3, [pc, #80] ; (8001414 ) 80013c4: 2200 movs r2, #0 80013c6: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 80013c8: 4b12 ldr r3, [pc, #72] ; (8001414 ) 80013ca: 2200 movs r2, #0 80013cc: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 80013ce: 2300 movs r3, #0 80013d0: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 80013d2: 230f movs r3, #15 80013d4: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 80013d6: 2301 movs r3, #1 80013d8: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 0; 80013da: 2300 movs r3, #0 80013dc: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 80013de: 2310 movs r3, #16 80013e0: 617b str r3, [r7, #20] Timing.DataLatency = 17; 80013e2: 2311 movs r3, #17 80013e4: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 80013e6: 2300 movs r3, #0 80013e8: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 80013ea: 1d3b adds r3, r7, #4 80013ec: 2200 movs r2, #0 80013ee: 4619 mov r1, r3 80013f0: 4808 ldr r0, [pc, #32] ; (8001414 ) 80013f2: f002 f933 bl 800365c 80013f6: 4603 mov r3, r0 80013f8: 2b00 cmp r3, #0 80013fa: d001 beq.n 8001400 { Error_Handler( ); 80013fc: f000 f810 bl 8001420 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 8001400: 4b06 ldr r3, [pc, #24] ; (800141c ) 8001402: 69db ldr r3, [r3, #28] 8001404: 4a05 ldr r2, [pc, #20] ; (800141c ) 8001406: f443 6380 orr.w r3, r3, #1024 ; 0x400 800140a: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 800140c: bf00 nop 800140e: 3720 adds r7, #32 8001410: 46bd mov sp, r7 8001412: bd80 pop {r7, pc} 8001414: 2000025c .word 0x2000025c 8001418: a0000104 .word 0xa0000104 800141c: 40010000 .word 0x40010000 08001420 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001420: b480 push {r7} 8001422: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001424: b672 cpsid i } 8001426: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001428: e7fe b.n 8001428 ... 0800142c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800142c: b480 push {r7} 800142e: b085 sub sp, #20 8001430: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001432: 4b15 ldr r3, [pc, #84] ; (8001488 ) 8001434: 699b ldr r3, [r3, #24] 8001436: 4a14 ldr r2, [pc, #80] ; (8001488 ) 8001438: f043 0301 orr.w r3, r3, #1 800143c: 6193 str r3, [r2, #24] 800143e: 4b12 ldr r3, [pc, #72] ; (8001488 ) 8001440: 699b ldr r3, [r3, #24] 8001442: f003 0301 and.w r3, r3, #1 8001446: 60bb str r3, [r7, #8] 8001448: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800144a: 4b0f ldr r3, [pc, #60] ; (8001488 ) 800144c: 69db ldr r3, [r3, #28] 800144e: 4a0e ldr r2, [pc, #56] ; (8001488 ) 8001450: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001454: 61d3 str r3, [r2, #28] 8001456: 4b0c ldr r3, [pc, #48] ; (8001488 ) 8001458: 69db ldr r3, [r3, #28] 800145a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800145e: 607b str r3, [r7, #4] 8001460: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 8001462: 4b0a ldr r3, [pc, #40] ; (800148c ) 8001464: 685b ldr r3, [r3, #4] 8001466: 60fb str r3, [r7, #12] 8001468: 68fb ldr r3, [r7, #12] 800146a: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 800146e: 60fb str r3, [r7, #12] 8001470: 68fb ldr r3, [r7, #12] 8001472: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8001476: 60fb str r3, [r7, #12] 8001478: 4a04 ldr r2, [pc, #16] ; (800148c ) 800147a: 68fb ldr r3, [r7, #12] 800147c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800147e: bf00 nop 8001480: 3714 adds r7, #20 8001482: 46bd mov sp, r7 8001484: bc80 pop {r7} 8001486: 4770 bx lr 8001488: 40021000 .word 0x40021000 800148c: 40010000 .word 0x40010000 08001490 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8001490: b580 push {r7, lr} 8001492: b088 sub sp, #32 8001494: af00 add r7, sp, #0 8001496: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001498: f107 0310 add.w r3, r7, #16 800149c: 2200 movs r2, #0 800149e: 601a str r2, [r3, #0] 80014a0: 605a str r2, [r3, #4] 80014a2: 609a str r2, [r3, #8] 80014a4: 60da str r2, [r3, #12] if(hi2c->Instance==I2C2) 80014a6: 687b ldr r3, [r7, #4] 80014a8: 681b ldr r3, [r3, #0] 80014aa: 4a16 ldr r2, [pc, #88] ; (8001504 ) 80014ac: 4293 cmp r3, r2 80014ae: d124 bne.n 80014fa { /* USER CODE BEGIN I2C2_MspInit 0 */ /* USER CODE END I2C2_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80014b0: 4b15 ldr r3, [pc, #84] ; (8001508 ) 80014b2: 699b ldr r3, [r3, #24] 80014b4: 4a14 ldr r2, [pc, #80] ; (8001508 ) 80014b6: f043 0308 orr.w r3, r3, #8 80014ba: 6193 str r3, [r2, #24] 80014bc: 4b12 ldr r3, [pc, #72] ; (8001508 ) 80014be: 699b ldr r3, [r3, #24] 80014c0: f003 0308 and.w r3, r3, #8 80014c4: 60fb str r3, [r7, #12] 80014c6: 68fb ldr r3, [r7, #12] /**I2C2 GPIO Configuration PB10 ------> I2C2_SCL PB11 ------> I2C2_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 80014c8: f44f 6340 mov.w r3, #3072 ; 0xc00 80014cc: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80014ce: 2312 movs r3, #18 80014d0: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80014d2: 2303 movs r3, #3 80014d4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80014d6: f107 0310 add.w r3, r7, #16 80014da: 4619 mov r1, r3 80014dc: 480b ldr r0, [pc, #44] ; (800150c ) 80014de: f000 faf3 bl 8001ac8 /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); 80014e2: 4b09 ldr r3, [pc, #36] ; (8001508 ) 80014e4: 69db ldr r3, [r3, #28] 80014e6: 4a08 ldr r2, [pc, #32] ; (8001508 ) 80014e8: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 80014ec: 61d3 str r3, [r2, #28] 80014ee: 4b06 ldr r3, [pc, #24] ; (8001508 ) 80014f0: 69db ldr r3, [r3, #28] 80014f2: f403 0380 and.w r3, r3, #4194304 ; 0x400000 80014f6: 60bb str r3, [r7, #8] 80014f8: 68bb ldr r3, [r7, #8] /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ } } 80014fa: bf00 nop 80014fc: 3720 adds r7, #32 80014fe: 46bd mov sp, r7 8001500: bd80 pop {r7, pc} 8001502: bf00 nop 8001504: 40005800 .word 0x40005800 8001508: 40021000 .word 0x40021000 800150c: 40010c00 .word 0x40010c00 08001510 : } static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 8001510: b580 push {r7, lr} 8001512: b086 sub sp, #24 8001514: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 8001516: f107 0308 add.w r3, r7, #8 800151a: 2200 movs r2, #0 800151c: 601a str r2, [r3, #0] 800151e: 605a str r2, [r3, #4] 8001520: 609a str r2, [r3, #8] 8001522: 60da str r2, [r3, #12] if (FSMC_Initialized) { 8001524: 4b1f ldr r3, [pc, #124] ; (80015a4 ) 8001526: 681b ldr r3, [r3, #0] 8001528: 2b00 cmp r3, #0 800152a: d136 bne.n 800159a return; } FSMC_Initialized = 1; 800152c: 4b1d ldr r3, [pc, #116] ; (80015a4 ) 800152e: 2201 movs r2, #1 8001530: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 8001532: 4b1d ldr r3, [pc, #116] ; (80015a8 ) 8001534: 695b ldr r3, [r3, #20] 8001536: 4a1c ldr r2, [pc, #112] ; (80015a8 ) 8001538: f443 7380 orr.w r3, r3, #256 ; 0x100 800153c: 6153 str r3, [r2, #20] 800153e: 4b1a ldr r3, [pc, #104] ; (80015a8 ) 8001540: 695b ldr r3, [r3, #20] 8001542: f403 7380 and.w r3, r3, #256 ; 0x100 8001546: 607b str r3, [r7, #4] 8001548: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 800154a: f241 0301 movw r3, #4097 ; 0x1001 800154e: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001550: 2302 movs r3, #2 8001552: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001554: 2303 movs r3, #3 8001556: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8001558: f107 0308 add.w r3, r7, #8 800155c: 4619 mov r1, r3 800155e: 4813 ldr r0, [pc, #76] ; (80015ac ) 8001560: f000 fab2 bl 8001ac8 GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001564: f64f 7380 movw r3, #65408 ; 0xff80 8001568: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800156a: 2302 movs r3, #2 800156c: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800156e: 2303 movs r3, #3 8001570: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001572: f107 0308 add.w r3, r7, #8 8001576: 4619 mov r1, r3 8001578: 480d ldr r0, [pc, #52] ; (80015b0 ) 800157a: f000 faa5 bl 8001ac8 GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 800157e: f24c 7333 movw r3, #50995 ; 0xc733 8001582: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001584: 2302 movs r3, #2 8001586: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001588: 2303 movs r3, #3 800158a: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800158c: f107 0308 add.w r3, r7, #8 8001590: 4619 mov r1, r3 8001592: 4808 ldr r0, [pc, #32] ; (80015b4 ) 8001594: f000 fa98 bl 8001ac8 8001598: e000 b.n 800159c return; 800159a: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 800159c: 3718 adds r7, #24 800159e: 46bd mov sp, r7 80015a0: bd80 pop {r7, pc} 80015a2: bf00 nop 80015a4: 200001f8 .word 0x200001f8 80015a8: 40021000 .word 0x40021000 80015ac: 40012000 .word 0x40012000 80015b0: 40011800 .word 0x40011800 80015b4: 40011400 .word 0x40011400 080015b8 : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 80015b8: b580 push {r7, lr} 80015ba: b082 sub sp, #8 80015bc: af00 add r7, sp, #0 80015be: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 80015c0: f7ff ffa6 bl 8001510 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 80015c4: bf00 nop 80015c6: 3708 adds r7, #8 80015c8: 46bd mov sp, r7 80015ca: bd80 pop {r7, pc} 080015cc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80015cc: b480 push {r7} 80015ce: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80015d0: e7fe b.n 80015d0 080015d2 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80015d2: b480 push {r7} 80015d4: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80015d6: e7fe b.n 80015d6 080015d8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80015d8: b480 push {r7} 80015da: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80015dc: e7fe b.n 80015dc 080015de : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80015de: b480 push {r7} 80015e0: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80015e2: e7fe b.n 80015e2 080015e4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80015e4: b480 push {r7} 80015e6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80015e8: e7fe b.n 80015e8 080015ea : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80015ea: b480 push {r7} 80015ec: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80015ee: bf00 nop 80015f0: 46bd mov sp, r7 80015f2: bc80 pop {r7} 80015f4: 4770 bx lr 080015f6 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80015f6: b480 push {r7} 80015f8: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80015fa: bf00 nop 80015fc: 46bd mov sp, r7 80015fe: bc80 pop {r7} 8001600: 4770 bx lr 08001602 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001602: b480 push {r7} 8001604: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001606: bf00 nop 8001608: 46bd mov sp, r7 800160a: bc80 pop {r7} 800160c: 4770 bx lr 0800160e : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800160e: b580 push {r7, lr} 8001610: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001612: f000 f935 bl 8001880 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001616: bf00 nop 8001618: bd80 pop {r7, pc} 0800161a <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800161a: b480 push {r7} 800161c: af00 add r7, sp, #0 return 1; 800161e: 2301 movs r3, #1 } 8001620: 4618 mov r0, r3 8001622: 46bd mov sp, r7 8001624: bc80 pop {r7} 8001626: 4770 bx lr 08001628 <_kill>: int _kill(int pid, int sig) { 8001628: b580 push {r7, lr} 800162a: b082 sub sp, #8 800162c: af00 add r7, sp, #0 800162e: 6078 str r0, [r7, #4] 8001630: 6039 str r1, [r7, #0] errno = EINVAL; 8001632: f004 f909 bl 8005848 <__errno> 8001636: 4603 mov r3, r0 8001638: 2216 movs r2, #22 800163a: 601a str r2, [r3, #0] return -1; 800163c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001640: 4618 mov r0, r3 8001642: 3708 adds r7, #8 8001644: 46bd mov sp, r7 8001646: bd80 pop {r7, pc} 08001648 <_exit>: void _exit (int status) { 8001648: b580 push {r7, lr} 800164a: b082 sub sp, #8 800164c: af00 add r7, sp, #0 800164e: 6078 str r0, [r7, #4] _kill(status, -1); 8001650: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001654: 6878 ldr r0, [r7, #4] 8001656: f7ff ffe7 bl 8001628 <_kill> while (1) {} /* Make sure we hang here */ 800165a: e7fe b.n 800165a <_exit+0x12> 0800165c <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800165c: b580 push {r7, lr} 800165e: b086 sub sp, #24 8001660: af00 add r7, sp, #0 8001662: 60f8 str r0, [r7, #12] 8001664: 60b9 str r1, [r7, #8] 8001666: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001668: 2300 movs r3, #0 800166a: 617b str r3, [r7, #20] 800166c: e00a b.n 8001684 <_read+0x28> { *ptr++ = __io_getchar(); 800166e: f3af 8000 nop.w 8001672: 4601 mov r1, r0 8001674: 68bb ldr r3, [r7, #8] 8001676: 1c5a adds r2, r3, #1 8001678: 60ba str r2, [r7, #8] 800167a: b2ca uxtb r2, r1 800167c: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800167e: 697b ldr r3, [r7, #20] 8001680: 3301 adds r3, #1 8001682: 617b str r3, [r7, #20] 8001684: 697a ldr r2, [r7, #20] 8001686: 687b ldr r3, [r7, #4] 8001688: 429a cmp r2, r3 800168a: dbf0 blt.n 800166e <_read+0x12> } return len; 800168c: 687b ldr r3, [r7, #4] } 800168e: 4618 mov r0, r3 8001690: 3718 adds r7, #24 8001692: 46bd mov sp, r7 8001694: bd80 pop {r7, pc} 08001696 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8001696: b580 push {r7, lr} 8001698: b086 sub sp, #24 800169a: af00 add r7, sp, #0 800169c: 60f8 str r0, [r7, #12] 800169e: 60b9 str r1, [r7, #8] 80016a0: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80016a2: 2300 movs r3, #0 80016a4: 617b str r3, [r7, #20] 80016a6: e009 b.n 80016bc <_write+0x26> { __io_putchar(*ptr++); 80016a8: 68bb ldr r3, [r7, #8] 80016aa: 1c5a adds r2, r3, #1 80016ac: 60ba str r2, [r7, #8] 80016ae: 781b ldrb r3, [r3, #0] 80016b0: 4618 mov r0, r3 80016b2: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 80016b6: 697b ldr r3, [r7, #20] 80016b8: 3301 adds r3, #1 80016ba: 617b str r3, [r7, #20] 80016bc: 697a ldr r2, [r7, #20] 80016be: 687b ldr r3, [r7, #4] 80016c0: 429a cmp r2, r3 80016c2: dbf1 blt.n 80016a8 <_write+0x12> } return len; 80016c4: 687b ldr r3, [r7, #4] } 80016c6: 4618 mov r0, r3 80016c8: 3718 adds r7, #24 80016ca: 46bd mov sp, r7 80016cc: bd80 pop {r7, pc} 080016ce <_close>: int _close(int file) { 80016ce: b480 push {r7} 80016d0: b083 sub sp, #12 80016d2: af00 add r7, sp, #0 80016d4: 6078 str r0, [r7, #4] return -1; 80016d6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 80016da: 4618 mov r0, r3 80016dc: 370c adds r7, #12 80016de: 46bd mov sp, r7 80016e0: bc80 pop {r7} 80016e2: 4770 bx lr 080016e4 <_fstat>: int _fstat(int file, struct stat *st) { 80016e4: b480 push {r7} 80016e6: b083 sub sp, #12 80016e8: af00 add r7, sp, #0 80016ea: 6078 str r0, [r7, #4] 80016ec: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 80016ee: 683b ldr r3, [r7, #0] 80016f0: f44f 5200 mov.w r2, #8192 ; 0x2000 80016f4: 605a str r2, [r3, #4] return 0; 80016f6: 2300 movs r3, #0 } 80016f8: 4618 mov r0, r3 80016fa: 370c adds r7, #12 80016fc: 46bd mov sp, r7 80016fe: bc80 pop {r7} 8001700: 4770 bx lr 08001702 <_isatty>: int _isatty(int file) { 8001702: b480 push {r7} 8001704: b083 sub sp, #12 8001706: af00 add r7, sp, #0 8001708: 6078 str r0, [r7, #4] return 1; 800170a: 2301 movs r3, #1 } 800170c: 4618 mov r0, r3 800170e: 370c adds r7, #12 8001710: 46bd mov sp, r7 8001712: bc80 pop {r7} 8001714: 4770 bx lr 08001716 <_lseek>: int _lseek(int file, int ptr, int dir) { 8001716: b480 push {r7} 8001718: b085 sub sp, #20 800171a: af00 add r7, sp, #0 800171c: 60f8 str r0, [r7, #12] 800171e: 60b9 str r1, [r7, #8] 8001720: 607a str r2, [r7, #4] return 0; 8001722: 2300 movs r3, #0 } 8001724: 4618 mov r0, r3 8001726: 3714 adds r7, #20 8001728: 46bd mov sp, r7 800172a: bc80 pop {r7} 800172c: 4770 bx lr ... 08001730 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001730: b580 push {r7, lr} 8001732: b086 sub sp, #24 8001734: af00 add r7, sp, #0 8001736: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8001738: 4a14 ldr r2, [pc, #80] ; (800178c <_sbrk+0x5c>) 800173a: 4b15 ldr r3, [pc, #84] ; (8001790 <_sbrk+0x60>) 800173c: 1ad3 subs r3, r2, r3 800173e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001740: 697b ldr r3, [r7, #20] 8001742: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001744: 4b13 ldr r3, [pc, #76] ; (8001794 <_sbrk+0x64>) 8001746: 681b ldr r3, [r3, #0] 8001748: 2b00 cmp r3, #0 800174a: d102 bne.n 8001752 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800174c: 4b11 ldr r3, [pc, #68] ; (8001794 <_sbrk+0x64>) 800174e: 4a12 ldr r2, [pc, #72] ; (8001798 <_sbrk+0x68>) 8001750: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001752: 4b10 ldr r3, [pc, #64] ; (8001794 <_sbrk+0x64>) 8001754: 681a ldr r2, [r3, #0] 8001756: 687b ldr r3, [r7, #4] 8001758: 4413 add r3, r2 800175a: 693a ldr r2, [r7, #16] 800175c: 429a cmp r2, r3 800175e: d207 bcs.n 8001770 <_sbrk+0x40> { errno = ENOMEM; 8001760: f004 f872 bl 8005848 <__errno> 8001764: 4603 mov r3, r0 8001766: 220c movs r2, #12 8001768: 601a str r2, [r3, #0] return (void *)-1; 800176a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 800176e: e009 b.n 8001784 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8001770: 4b08 ldr r3, [pc, #32] ; (8001794 <_sbrk+0x64>) 8001772: 681b ldr r3, [r3, #0] 8001774: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8001776: 4b07 ldr r3, [pc, #28] ; (8001794 <_sbrk+0x64>) 8001778: 681a ldr r2, [r3, #0] 800177a: 687b ldr r3, [r7, #4] 800177c: 4413 add r3, r2 800177e: 4a05 ldr r2, [pc, #20] ; (8001794 <_sbrk+0x64>) 8001780: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8001782: 68fb ldr r3, [r7, #12] } 8001784: 4618 mov r0, r3 8001786: 3718 adds r7, #24 8001788: 46bd mov sp, r7 800178a: bd80 pop {r7, pc} 800178c: 20010000 .word 0x20010000 8001790: 00000800 .word 0x00000800 8001794: 200001fc .word 0x200001fc 8001798: 20000308 .word 0x20000308 0800179c : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800179c: b480 push {r7} 800179e: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80017a0: bf00 nop 80017a2: 46bd mov sp, r7 80017a4: bc80 pop {r7} 80017a6: 4770 bx lr 080017a8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80017a8: 480c ldr r0, [pc, #48] ; (80017dc ) ldr r1, =_edata 80017aa: 490d ldr r1, [pc, #52] ; (80017e0 ) ldr r2, =_sidata 80017ac: 4a0d ldr r2, [pc, #52] ; (80017e4 ) movs r3, #0 80017ae: 2300 movs r3, #0 b LoopCopyDataInit 80017b0: e002 b.n 80017b8 080017b2 : CopyDataInit: ldr r4, [r2, r3] 80017b2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80017b4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80017b6: 3304 adds r3, #4 080017b8 : LoopCopyDataInit: adds r4, r0, r3 80017b8: 18c4 adds r4, r0, r3 cmp r4, r1 80017ba: 428c cmp r4, r1 bcc CopyDataInit 80017bc: d3f9 bcc.n 80017b2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80017be: 4a0a ldr r2, [pc, #40] ; (80017e8 ) ldr r4, =_ebss 80017c0: 4c0a ldr r4, [pc, #40] ; (80017ec ) movs r3, #0 80017c2: 2300 movs r3, #0 b LoopFillZerobss 80017c4: e001 b.n 80017ca 080017c6 : FillZerobss: str r3, [r2] 80017c6: 6013 str r3, [r2, #0] adds r2, r2, #4 80017c8: 3204 adds r2, #4 080017ca : LoopFillZerobss: cmp r2, r4 80017ca: 42a2 cmp r2, r4 bcc FillZerobss 80017cc: d3fb bcc.n 80017c6 /* Call the clock system intitialization function.*/ bl SystemInit 80017ce: f7ff ffe5 bl 800179c /* Call static constructors */ bl __libc_init_array 80017d2: f004 f83f bl 8005854 <__libc_init_array> /* Call the application's entry point.*/ bl main 80017d6: f7ff fc97 bl 8001108

bx lr 80017da: 4770 bx lr ldr r0, =_sdata 80017dc: 20000000 .word 0x20000000 ldr r1, =_edata 80017e0: 200001dc .word 0x200001dc ldr r2, =_sidata 80017e4: 08009544 .word 0x08009544 ldr r2, =_sbss 80017e8: 200001dc .word 0x200001dc ldr r4, =_ebss 80017ec: 20000304 .word 0x20000304 080017f0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80017f0: e7fe b.n 80017f0 ... 080017f4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80017f4: b580 push {r7, lr} 80017f6: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80017f8: 4b08 ldr r3, [pc, #32] ; (800181c ) 80017fa: 681b ldr r3, [r3, #0] 80017fc: 4a07 ldr r2, [pc, #28] ; (800181c ) 80017fe: f043 0310 orr.w r3, r3, #16 8001802: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001804: 2003 movs r0, #3 8001806: f000 f92b bl 8001a60 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800180a: 200f movs r0, #15 800180c: f000 f808 bl 8001820 /* Init the low level hardware */ HAL_MspInit(); 8001810: f7ff fe0c bl 800142c /* Return function status */ return HAL_OK; 8001814: 2300 movs r3, #0 } 8001816: 4618 mov r0, r3 8001818: bd80 pop {r7, pc} 800181a: bf00 nop 800181c: 40022000 .word 0x40022000 08001820 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001820: b580 push {r7, lr} 8001822: b082 sub sp, #8 8001824: af00 add r7, sp, #0 8001826: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001828: 4b12 ldr r3, [pc, #72] ; (8001874 ) 800182a: 681a ldr r2, [r3, #0] 800182c: 4b12 ldr r3, [pc, #72] ; (8001878 ) 800182e: 781b ldrb r3, [r3, #0] 8001830: 4619 mov r1, r3 8001832: f44f 737a mov.w r3, #1000 ; 0x3e8 8001836: fbb3 f3f1 udiv r3, r3, r1 800183a: fbb2 f3f3 udiv r3, r2, r3 800183e: 4618 mov r0, r3 8001840: f000 f935 bl 8001aae 8001844: 4603 mov r3, r0 8001846: 2b00 cmp r3, #0 8001848: d001 beq.n 800184e { return HAL_ERROR; 800184a: 2301 movs r3, #1 800184c: e00e b.n 800186c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800184e: 687b ldr r3, [r7, #4] 8001850: 2b0f cmp r3, #15 8001852: d80a bhi.n 800186a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001854: 2200 movs r2, #0 8001856: 6879 ldr r1, [r7, #4] 8001858: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800185c: f000 f90b bl 8001a76 uwTickPrio = TickPriority; 8001860: 4a06 ldr r2, [pc, #24] ; (800187c ) 8001862: 687b ldr r3, [r7, #4] 8001864: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001866: 2300 movs r3, #0 8001868: e000 b.n 800186c return HAL_ERROR; 800186a: 2301 movs r3, #1 } 800186c: 4618 mov r0, r3 800186e: 3708 adds r7, #8 8001870: 46bd mov sp, r7 8001872: bd80 pop {r7, pc} 8001874: 20000000 .word 0x20000000 8001878: 20000008 .word 0x20000008 800187c: 20000004 .word 0x20000004 08001880 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001880: b480 push {r7} 8001882: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001884: 4b05 ldr r3, [pc, #20] ; (800189c ) 8001886: 781b ldrb r3, [r3, #0] 8001888: 461a mov r2, r3 800188a: 4b05 ldr r3, [pc, #20] ; (80018a0 ) 800188c: 681b ldr r3, [r3, #0] 800188e: 4413 add r3, r2 8001890: 4a03 ldr r2, [pc, #12] ; (80018a0 ) 8001892: 6013 str r3, [r2, #0] } 8001894: bf00 nop 8001896: 46bd mov sp, r7 8001898: bc80 pop {r7} 800189a: 4770 bx lr 800189c: 20000008 .word 0x20000008 80018a0: 200002a4 .word 0x200002a4 080018a4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80018a4: b480 push {r7} 80018a6: af00 add r7, sp, #0 return uwTick; 80018a8: 4b02 ldr r3, [pc, #8] ; (80018b4 ) 80018aa: 681b ldr r3, [r3, #0] } 80018ac: 4618 mov r0, r3 80018ae: 46bd mov sp, r7 80018b0: bc80 pop {r7} 80018b2: 4770 bx lr 80018b4: 200002a4 .word 0x200002a4 080018b8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80018b8: b580 push {r7, lr} 80018ba: b084 sub sp, #16 80018bc: af00 add r7, sp, #0 80018be: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80018c0: f7ff fff0 bl 80018a4 80018c4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80018c6: 687b ldr r3, [r7, #4] 80018c8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80018ca: 68fb ldr r3, [r7, #12] 80018cc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80018d0: d005 beq.n 80018de { wait += (uint32_t)(uwTickFreq); 80018d2: 4b0a ldr r3, [pc, #40] ; (80018fc ) 80018d4: 781b ldrb r3, [r3, #0] 80018d6: 461a mov r2, r3 80018d8: 68fb ldr r3, [r7, #12] 80018da: 4413 add r3, r2 80018dc: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80018de: bf00 nop 80018e0: f7ff ffe0 bl 80018a4 80018e4: 4602 mov r2, r0 80018e6: 68bb ldr r3, [r7, #8] 80018e8: 1ad3 subs r3, r2, r3 80018ea: 68fa ldr r2, [r7, #12] 80018ec: 429a cmp r2, r3 80018ee: d8f7 bhi.n 80018e0 { } } 80018f0: bf00 nop 80018f2: bf00 nop 80018f4: 3710 adds r7, #16 80018f6: 46bd mov sp, r7 80018f8: bd80 pop {r7, pc} 80018fa: bf00 nop 80018fc: 20000008 .word 0x20000008 08001900 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001900: b480 push {r7} 8001902: b085 sub sp, #20 8001904: af00 add r7, sp, #0 8001906: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001908: 687b ldr r3, [r7, #4] 800190a: f003 0307 and.w r3, r3, #7 800190e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001910: 4b0c ldr r3, [pc, #48] ; (8001944 <__NVIC_SetPriorityGrouping+0x44>) 8001912: 68db ldr r3, [r3, #12] 8001914: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001916: 68ba ldr r2, [r7, #8] 8001918: f64f 03ff movw r3, #63743 ; 0xf8ff 800191c: 4013 ands r3, r2 800191e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001920: 68fb ldr r3, [r7, #12] 8001922: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001924: 68bb ldr r3, [r7, #8] 8001926: 4313 orrs r3, r2 reg_value = (reg_value | 8001928: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800192c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001930: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001932: 4a04 ldr r2, [pc, #16] ; (8001944 <__NVIC_SetPriorityGrouping+0x44>) 8001934: 68bb ldr r3, [r7, #8] 8001936: 60d3 str r3, [r2, #12] } 8001938: bf00 nop 800193a: 3714 adds r7, #20 800193c: 46bd mov sp, r7 800193e: bc80 pop {r7} 8001940: 4770 bx lr 8001942: bf00 nop 8001944: e000ed00 .word 0xe000ed00 08001948 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001948: b480 push {r7} 800194a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800194c: 4b04 ldr r3, [pc, #16] ; (8001960 <__NVIC_GetPriorityGrouping+0x18>) 800194e: 68db ldr r3, [r3, #12] 8001950: 0a1b lsrs r3, r3, #8 8001952: f003 0307 and.w r3, r3, #7 } 8001956: 4618 mov r0, r3 8001958: 46bd mov sp, r7 800195a: bc80 pop {r7} 800195c: 4770 bx lr 800195e: bf00 nop 8001960: e000ed00 .word 0xe000ed00 08001964 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001964: b480 push {r7} 8001966: b083 sub sp, #12 8001968: af00 add r7, sp, #0 800196a: 4603 mov r3, r0 800196c: 6039 str r1, [r7, #0] 800196e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001970: f997 3007 ldrsb.w r3, [r7, #7] 8001974: 2b00 cmp r3, #0 8001976: db0a blt.n 800198e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001978: 683b ldr r3, [r7, #0] 800197a: b2da uxtb r2, r3 800197c: 490c ldr r1, [pc, #48] ; (80019b0 <__NVIC_SetPriority+0x4c>) 800197e: f997 3007 ldrsb.w r3, [r7, #7] 8001982: 0112 lsls r2, r2, #4 8001984: b2d2 uxtb r2, r2 8001986: 440b add r3, r1 8001988: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800198c: e00a b.n 80019a4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800198e: 683b ldr r3, [r7, #0] 8001990: b2da uxtb r2, r3 8001992: 4908 ldr r1, [pc, #32] ; (80019b4 <__NVIC_SetPriority+0x50>) 8001994: 79fb ldrb r3, [r7, #7] 8001996: f003 030f and.w r3, r3, #15 800199a: 3b04 subs r3, #4 800199c: 0112 lsls r2, r2, #4 800199e: b2d2 uxtb r2, r2 80019a0: 440b add r3, r1 80019a2: 761a strb r2, [r3, #24] } 80019a4: bf00 nop 80019a6: 370c adds r7, #12 80019a8: 46bd mov sp, r7 80019aa: bc80 pop {r7} 80019ac: 4770 bx lr 80019ae: bf00 nop 80019b0: e000e100 .word 0xe000e100 80019b4: e000ed00 .word 0xe000ed00 080019b8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80019b8: b480 push {r7} 80019ba: b089 sub sp, #36 ; 0x24 80019bc: af00 add r7, sp, #0 80019be: 60f8 str r0, [r7, #12] 80019c0: 60b9 str r1, [r7, #8] 80019c2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80019c4: 68fb ldr r3, [r7, #12] 80019c6: f003 0307 and.w r3, r3, #7 80019ca: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80019cc: 69fb ldr r3, [r7, #28] 80019ce: f1c3 0307 rsb r3, r3, #7 80019d2: 2b04 cmp r3, #4 80019d4: bf28 it cs 80019d6: 2304 movcs r3, #4 80019d8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80019da: 69fb ldr r3, [r7, #28] 80019dc: 3304 adds r3, #4 80019de: 2b06 cmp r3, #6 80019e0: d902 bls.n 80019e8 80019e2: 69fb ldr r3, [r7, #28] 80019e4: 3b03 subs r3, #3 80019e6: e000 b.n 80019ea 80019e8: 2300 movs r3, #0 80019ea: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80019ec: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80019f0: 69bb ldr r3, [r7, #24] 80019f2: fa02 f303 lsl.w r3, r2, r3 80019f6: 43da mvns r2, r3 80019f8: 68bb ldr r3, [r7, #8] 80019fa: 401a ands r2, r3 80019fc: 697b ldr r3, [r7, #20] 80019fe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001a00: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001a04: 697b ldr r3, [r7, #20] 8001a06: fa01 f303 lsl.w r3, r1, r3 8001a0a: 43d9 mvns r1, r3 8001a0c: 687b ldr r3, [r7, #4] 8001a0e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001a10: 4313 orrs r3, r2 ); } 8001a12: 4618 mov r0, r3 8001a14: 3724 adds r7, #36 ; 0x24 8001a16: 46bd mov sp, r7 8001a18: bc80 pop {r7} 8001a1a: 4770 bx lr 08001a1c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001a1c: b580 push {r7, lr} 8001a1e: b082 sub sp, #8 8001a20: af00 add r7, sp, #0 8001a22: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001a24: 687b ldr r3, [r7, #4] 8001a26: 3b01 subs r3, #1 8001a28: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001a2c: d301 bcc.n 8001a32 { return (1UL); /* Reload value impossible */ 8001a2e: 2301 movs r3, #1 8001a30: e00f b.n 8001a52 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001a32: 4a0a ldr r2, [pc, #40] ; (8001a5c ) 8001a34: 687b ldr r3, [r7, #4] 8001a36: 3b01 subs r3, #1 8001a38: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001a3a: 210f movs r1, #15 8001a3c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001a40: f7ff ff90 bl 8001964 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001a44: 4b05 ldr r3, [pc, #20] ; (8001a5c ) 8001a46: 2200 movs r2, #0 8001a48: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001a4a: 4b04 ldr r3, [pc, #16] ; (8001a5c ) 8001a4c: 2207 movs r2, #7 8001a4e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001a50: 2300 movs r3, #0 } 8001a52: 4618 mov r0, r3 8001a54: 3708 adds r7, #8 8001a56: 46bd mov sp, r7 8001a58: bd80 pop {r7, pc} 8001a5a: bf00 nop 8001a5c: e000e010 .word 0xe000e010 08001a60 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a60: b580 push {r7, lr} 8001a62: b082 sub sp, #8 8001a64: af00 add r7, sp, #0 8001a66: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001a68: 6878 ldr r0, [r7, #4] 8001a6a: f7ff ff49 bl 8001900 <__NVIC_SetPriorityGrouping> } 8001a6e: bf00 nop 8001a70: 3708 adds r7, #8 8001a72: 46bd mov sp, r7 8001a74: bd80 pop {r7, pc} 08001a76 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001a76: b580 push {r7, lr} 8001a78: b086 sub sp, #24 8001a7a: af00 add r7, sp, #0 8001a7c: 4603 mov r3, r0 8001a7e: 60b9 str r1, [r7, #8] 8001a80: 607a str r2, [r7, #4] 8001a82: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001a84: 2300 movs r3, #0 8001a86: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001a88: f7ff ff5e bl 8001948 <__NVIC_GetPriorityGrouping> 8001a8c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001a8e: 687a ldr r2, [r7, #4] 8001a90: 68b9 ldr r1, [r7, #8] 8001a92: 6978 ldr r0, [r7, #20] 8001a94: f7ff ff90 bl 80019b8 8001a98: 4602 mov r2, r0 8001a9a: f997 300f ldrsb.w r3, [r7, #15] 8001a9e: 4611 mov r1, r2 8001aa0: 4618 mov r0, r3 8001aa2: f7ff ff5f bl 8001964 <__NVIC_SetPriority> } 8001aa6: bf00 nop 8001aa8: 3718 adds r7, #24 8001aaa: 46bd mov sp, r7 8001aac: bd80 pop {r7, pc} 08001aae : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001aae: b580 push {r7, lr} 8001ab0: b082 sub sp, #8 8001ab2: af00 add r7, sp, #0 8001ab4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001ab6: 6878 ldr r0, [r7, #4] 8001ab8: f7ff ffb0 bl 8001a1c 8001abc: 4603 mov r3, r0 } 8001abe: 4618 mov r0, r3 8001ac0: 3708 adds r7, #8 8001ac2: 46bd mov sp, r7 8001ac4: bd80 pop {r7, pc} ... 08001ac8 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001ac8: b480 push {r7} 8001aca: b08b sub sp, #44 ; 0x2c 8001acc: af00 add r7, sp, #0 8001ace: 6078 str r0, [r7, #4] 8001ad0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8001ad2: 2300 movs r3, #0 8001ad4: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8001ad6: 2300 movs r3, #0 8001ad8: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8001ada: e179 b.n 8001dd0 { /* Get the IO position */ ioposition = (0x01uL << position); 8001adc: 2201 movs r2, #1 8001ade: 6a7b ldr r3, [r7, #36] ; 0x24 8001ae0: fa02 f303 lsl.w r3, r2, r3 8001ae4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001ae6: 683b ldr r3, [r7, #0] 8001ae8: 681b ldr r3, [r3, #0] 8001aea: 69fa ldr r2, [r7, #28] 8001aec: 4013 ands r3, r2 8001aee: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8001af0: 69ba ldr r2, [r7, #24] 8001af2: 69fb ldr r3, [r7, #28] 8001af4: 429a cmp r2, r3 8001af6: f040 8168 bne.w 8001dca { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8001afa: 683b ldr r3, [r7, #0] 8001afc: 685b ldr r3, [r3, #4] 8001afe: 4aa0 ldr r2, [pc, #640] ; (8001d80 ) 8001b00: 4293 cmp r3, r2 8001b02: d05e beq.n 8001bc2 8001b04: 4a9e ldr r2, [pc, #632] ; (8001d80 ) 8001b06: 4293 cmp r3, r2 8001b08: d875 bhi.n 8001bf6 8001b0a: 4a9e ldr r2, [pc, #632] ; (8001d84 ) 8001b0c: 4293 cmp r3, r2 8001b0e: d058 beq.n 8001bc2 8001b10: 4a9c ldr r2, [pc, #624] ; (8001d84 ) 8001b12: 4293 cmp r3, r2 8001b14: d86f bhi.n 8001bf6 8001b16: 4a9c ldr r2, [pc, #624] ; (8001d88 ) 8001b18: 4293 cmp r3, r2 8001b1a: d052 beq.n 8001bc2 8001b1c: 4a9a ldr r2, [pc, #616] ; (8001d88 ) 8001b1e: 4293 cmp r3, r2 8001b20: d869 bhi.n 8001bf6 8001b22: 4a9a ldr r2, [pc, #616] ; (8001d8c ) 8001b24: 4293 cmp r3, r2 8001b26: d04c beq.n 8001bc2 8001b28: 4a98 ldr r2, [pc, #608] ; (8001d8c ) 8001b2a: 4293 cmp r3, r2 8001b2c: d863 bhi.n 8001bf6 8001b2e: 4a98 ldr r2, [pc, #608] ; (8001d90 ) 8001b30: 4293 cmp r3, r2 8001b32: d046 beq.n 8001bc2 8001b34: 4a96 ldr r2, [pc, #600] ; (8001d90 ) 8001b36: 4293 cmp r3, r2 8001b38: d85d bhi.n 8001bf6 8001b3a: 2b12 cmp r3, #18 8001b3c: d82a bhi.n 8001b94 8001b3e: 2b12 cmp r3, #18 8001b40: d859 bhi.n 8001bf6 8001b42: a201 add r2, pc, #4 ; (adr r2, 8001b48 ) 8001b44: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001b48: 08001bc3 .word 0x08001bc3 8001b4c: 08001b9d .word 0x08001b9d 8001b50: 08001baf .word 0x08001baf 8001b54: 08001bf1 .word 0x08001bf1 8001b58: 08001bf7 .word 0x08001bf7 8001b5c: 08001bf7 .word 0x08001bf7 8001b60: 08001bf7 .word 0x08001bf7 8001b64: 08001bf7 .word 0x08001bf7 8001b68: 08001bf7 .word 0x08001bf7 8001b6c: 08001bf7 .word 0x08001bf7 8001b70: 08001bf7 .word 0x08001bf7 8001b74: 08001bf7 .word 0x08001bf7 8001b78: 08001bf7 .word 0x08001bf7 8001b7c: 08001bf7 .word 0x08001bf7 8001b80: 08001bf7 .word 0x08001bf7 8001b84: 08001bf7 .word 0x08001bf7 8001b88: 08001bf7 .word 0x08001bf7 8001b8c: 08001ba5 .word 0x08001ba5 8001b90: 08001bb9 .word 0x08001bb9 8001b94: 4a7f ldr r2, [pc, #508] ; (8001d94 ) 8001b96: 4293 cmp r3, r2 8001b98: d013 beq.n 8001bc2 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001b9a: e02c b.n 8001bf6 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001b9c: 683b ldr r3, [r7, #0] 8001b9e: 68db ldr r3, [r3, #12] 8001ba0: 623b str r3, [r7, #32] break; 8001ba2: e029 b.n 8001bf8 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8001ba4: 683b ldr r3, [r7, #0] 8001ba6: 68db ldr r3, [r3, #12] 8001ba8: 3304 adds r3, #4 8001baa: 623b str r3, [r7, #32] break; 8001bac: e024 b.n 8001bf8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001bae: 683b ldr r3, [r7, #0] 8001bb0: 68db ldr r3, [r3, #12] 8001bb2: 3308 adds r3, #8 8001bb4: 623b str r3, [r7, #32] break; 8001bb6: e01f b.n 8001bf8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001bb8: 683b ldr r3, [r7, #0] 8001bba: 68db ldr r3, [r3, #12] 8001bbc: 330c adds r3, #12 8001bbe: 623b str r3, [r7, #32] break; 8001bc0: e01a b.n 8001bf8 if (GPIO_Init->Pull == GPIO_NOPULL) 8001bc2: 683b ldr r3, [r7, #0] 8001bc4: 689b ldr r3, [r3, #8] 8001bc6: 2b00 cmp r3, #0 8001bc8: d102 bne.n 8001bd0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001bca: 2304 movs r3, #4 8001bcc: 623b str r3, [r7, #32] break; 8001bce: e013 b.n 8001bf8 else if (GPIO_Init->Pull == GPIO_PULLUP) 8001bd0: 683b ldr r3, [r7, #0] 8001bd2: 689b ldr r3, [r3, #8] 8001bd4: 2b01 cmp r3, #1 8001bd6: d105 bne.n 8001be4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001bd8: 2308 movs r3, #8 8001bda: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001bdc: 687b ldr r3, [r7, #4] 8001bde: 69fa ldr r2, [r7, #28] 8001be0: 611a str r2, [r3, #16] break; 8001be2: e009 b.n 8001bf8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001be4: 2308 movs r3, #8 8001be6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001be8: 687b ldr r3, [r7, #4] 8001bea: 69fa ldr r2, [r7, #28] 8001bec: 615a str r2, [r3, #20] break; 8001bee: e003 b.n 8001bf8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8001bf0: 2300 movs r3, #0 8001bf2: 623b str r3, [r7, #32] break; 8001bf4: e000 b.n 8001bf8 break; 8001bf6: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001bf8: 69bb ldr r3, [r7, #24] 8001bfa: 2bff cmp r3, #255 ; 0xff 8001bfc: d801 bhi.n 8001c02 8001bfe: 687b ldr r3, [r7, #4] 8001c00: e001 b.n 8001c06 8001c02: 687b ldr r3, [r7, #4] 8001c04: 3304 adds r3, #4 8001c06: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001c08: 69bb ldr r3, [r7, #24] 8001c0a: 2bff cmp r3, #255 ; 0xff 8001c0c: d802 bhi.n 8001c14 8001c0e: 6a7b ldr r3, [r7, #36] ; 0x24 8001c10: 009b lsls r3, r3, #2 8001c12: e002 b.n 8001c1a 8001c14: 6a7b ldr r3, [r7, #36] ; 0x24 8001c16: 3b08 subs r3, #8 8001c18: 009b lsls r3, r3, #2 8001c1a: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001c1c: 697b ldr r3, [r7, #20] 8001c1e: 681a ldr r2, [r3, #0] 8001c20: 210f movs r1, #15 8001c22: 693b ldr r3, [r7, #16] 8001c24: fa01 f303 lsl.w r3, r1, r3 8001c28: 43db mvns r3, r3 8001c2a: 401a ands r2, r3 8001c2c: 6a39 ldr r1, [r7, #32] 8001c2e: 693b ldr r3, [r7, #16] 8001c30: fa01 f303 lsl.w r3, r1, r3 8001c34: 431a orrs r2, r3 8001c36: 697b ldr r3, [r7, #20] 8001c38: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001c3a: 683b ldr r3, [r7, #0] 8001c3c: 685b ldr r3, [r3, #4] 8001c3e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001c42: 2b00 cmp r3, #0 8001c44: f000 80c1 beq.w 8001dca { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001c48: 4b53 ldr r3, [pc, #332] ; (8001d98 ) 8001c4a: 699b ldr r3, [r3, #24] 8001c4c: 4a52 ldr r2, [pc, #328] ; (8001d98 ) 8001c4e: f043 0301 orr.w r3, r3, #1 8001c52: 6193 str r3, [r2, #24] 8001c54: 4b50 ldr r3, [pc, #320] ; (8001d98 ) 8001c56: 699b ldr r3, [r3, #24] 8001c58: f003 0301 and.w r3, r3, #1 8001c5c: 60bb str r3, [r7, #8] 8001c5e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001c60: 4a4e ldr r2, [pc, #312] ; (8001d9c ) 8001c62: 6a7b ldr r3, [r7, #36] ; 0x24 8001c64: 089b lsrs r3, r3, #2 8001c66: 3302 adds r3, #2 8001c68: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001c6c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001c6e: 6a7b ldr r3, [r7, #36] ; 0x24 8001c70: f003 0303 and.w r3, r3, #3 8001c74: 009b lsls r3, r3, #2 8001c76: 220f movs r2, #15 8001c78: fa02 f303 lsl.w r3, r2, r3 8001c7c: 43db mvns r3, r3 8001c7e: 68fa ldr r2, [r7, #12] 8001c80: 4013 ands r3, r2 8001c82: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8001c84: 687b ldr r3, [r7, #4] 8001c86: 4a46 ldr r2, [pc, #280] ; (8001da0 ) 8001c88: 4293 cmp r3, r2 8001c8a: d01f beq.n 8001ccc 8001c8c: 687b ldr r3, [r7, #4] 8001c8e: 4a45 ldr r2, [pc, #276] ; (8001da4 ) 8001c90: 4293 cmp r3, r2 8001c92: d019 beq.n 8001cc8 8001c94: 687b ldr r3, [r7, #4] 8001c96: 4a44 ldr r2, [pc, #272] ; (8001da8 ) 8001c98: 4293 cmp r3, r2 8001c9a: d013 beq.n 8001cc4 8001c9c: 687b ldr r3, [r7, #4] 8001c9e: 4a43 ldr r2, [pc, #268] ; (8001dac ) 8001ca0: 4293 cmp r3, r2 8001ca2: d00d beq.n 8001cc0 8001ca4: 687b ldr r3, [r7, #4] 8001ca6: 4a42 ldr r2, [pc, #264] ; (8001db0 ) 8001ca8: 4293 cmp r3, r2 8001caa: d007 beq.n 8001cbc 8001cac: 687b ldr r3, [r7, #4] 8001cae: 4a41 ldr r2, [pc, #260] ; (8001db4 ) 8001cb0: 4293 cmp r3, r2 8001cb2: d101 bne.n 8001cb8 8001cb4: 2305 movs r3, #5 8001cb6: e00a b.n 8001cce 8001cb8: 2306 movs r3, #6 8001cba: e008 b.n 8001cce 8001cbc: 2304 movs r3, #4 8001cbe: e006 b.n 8001cce 8001cc0: 2303 movs r3, #3 8001cc2: e004 b.n 8001cce 8001cc4: 2302 movs r3, #2 8001cc6: e002 b.n 8001cce 8001cc8: 2301 movs r3, #1 8001cca: e000 b.n 8001cce 8001ccc: 2300 movs r3, #0 8001cce: 6a7a ldr r2, [r7, #36] ; 0x24 8001cd0: f002 0203 and.w r2, r2, #3 8001cd4: 0092 lsls r2, r2, #2 8001cd6: 4093 lsls r3, r2 8001cd8: 68fa ldr r2, [r7, #12] 8001cda: 4313 orrs r3, r2 8001cdc: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001cde: 492f ldr r1, [pc, #188] ; (8001d9c ) 8001ce0: 6a7b ldr r3, [r7, #36] ; 0x24 8001ce2: 089b lsrs r3, r3, #2 8001ce4: 3302 adds r3, #2 8001ce6: 68fa ldr r2, [r7, #12] 8001ce8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8001cec: 683b ldr r3, [r7, #0] 8001cee: 685b ldr r3, [r3, #4] 8001cf0: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001cf4: 2b00 cmp r3, #0 8001cf6: d006 beq.n 8001d06 { SET_BIT(EXTI->IMR, iocurrent); 8001cf8: 4b2f ldr r3, [pc, #188] ; (8001db8 ) 8001cfa: 681a ldr r2, [r3, #0] 8001cfc: 492e ldr r1, [pc, #184] ; (8001db8 ) 8001cfe: 69bb ldr r3, [r7, #24] 8001d00: 4313 orrs r3, r2 8001d02: 600b str r3, [r1, #0] 8001d04: e006 b.n 8001d14 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8001d06: 4b2c ldr r3, [pc, #176] ; (8001db8 ) 8001d08: 681a ldr r2, [r3, #0] 8001d0a: 69bb ldr r3, [r7, #24] 8001d0c: 43db mvns r3, r3 8001d0e: 492a ldr r1, [pc, #168] ; (8001db8 ) 8001d10: 4013 ands r3, r2 8001d12: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8001d14: 683b ldr r3, [r7, #0] 8001d16: 685b ldr r3, [r3, #4] 8001d18: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001d1c: 2b00 cmp r3, #0 8001d1e: d006 beq.n 8001d2e { SET_BIT(EXTI->EMR, iocurrent); 8001d20: 4b25 ldr r3, [pc, #148] ; (8001db8 ) 8001d22: 685a ldr r2, [r3, #4] 8001d24: 4924 ldr r1, [pc, #144] ; (8001db8 ) 8001d26: 69bb ldr r3, [r7, #24] 8001d28: 4313 orrs r3, r2 8001d2a: 604b str r3, [r1, #4] 8001d2c: e006 b.n 8001d3c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8001d2e: 4b22 ldr r3, [pc, #136] ; (8001db8 ) 8001d30: 685a ldr r2, [r3, #4] 8001d32: 69bb ldr r3, [r7, #24] 8001d34: 43db mvns r3, r3 8001d36: 4920 ldr r1, [pc, #128] ; (8001db8 ) 8001d38: 4013 ands r3, r2 8001d3a: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001d3c: 683b ldr r3, [r7, #0] 8001d3e: 685b ldr r3, [r3, #4] 8001d40: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001d44: 2b00 cmp r3, #0 8001d46: d006 beq.n 8001d56 { SET_BIT(EXTI->RTSR, iocurrent); 8001d48: 4b1b ldr r3, [pc, #108] ; (8001db8 ) 8001d4a: 689a ldr r2, [r3, #8] 8001d4c: 491a ldr r1, [pc, #104] ; (8001db8 ) 8001d4e: 69bb ldr r3, [r7, #24] 8001d50: 4313 orrs r3, r2 8001d52: 608b str r3, [r1, #8] 8001d54: e006 b.n 8001d64 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8001d56: 4b18 ldr r3, [pc, #96] ; (8001db8 ) 8001d58: 689a ldr r2, [r3, #8] 8001d5a: 69bb ldr r3, [r7, #24] 8001d5c: 43db mvns r3, r3 8001d5e: 4916 ldr r1, [pc, #88] ; (8001db8 ) 8001d60: 4013 ands r3, r2 8001d62: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8001d64: 683b ldr r3, [r7, #0] 8001d66: 685b ldr r3, [r3, #4] 8001d68: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001d6c: 2b00 cmp r3, #0 8001d6e: d025 beq.n 8001dbc { SET_BIT(EXTI->FTSR, iocurrent); 8001d70: 4b11 ldr r3, [pc, #68] ; (8001db8 ) 8001d72: 68da ldr r2, [r3, #12] 8001d74: 4910 ldr r1, [pc, #64] ; (8001db8 ) 8001d76: 69bb ldr r3, [r7, #24] 8001d78: 4313 orrs r3, r2 8001d7a: 60cb str r3, [r1, #12] 8001d7c: e025 b.n 8001dca 8001d7e: bf00 nop 8001d80: 10320000 .word 0x10320000 8001d84: 10310000 .word 0x10310000 8001d88: 10220000 .word 0x10220000 8001d8c: 10210000 .word 0x10210000 8001d90: 10120000 .word 0x10120000 8001d94: 10110000 .word 0x10110000 8001d98: 40021000 .word 0x40021000 8001d9c: 40010000 .word 0x40010000 8001da0: 40010800 .word 0x40010800 8001da4: 40010c00 .word 0x40010c00 8001da8: 40011000 .word 0x40011000 8001dac: 40011400 .word 0x40011400 8001db0: 40011800 .word 0x40011800 8001db4: 40011c00 .word 0x40011c00 8001db8: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001dbc: 4b0b ldr r3, [pc, #44] ; (8001dec ) 8001dbe: 68da ldr r2, [r3, #12] 8001dc0: 69bb ldr r3, [r7, #24] 8001dc2: 43db mvns r3, r3 8001dc4: 4909 ldr r1, [pc, #36] ; (8001dec ) 8001dc6: 4013 ands r3, r2 8001dc8: 60cb str r3, [r1, #12] } } } position++; 8001dca: 6a7b ldr r3, [r7, #36] ; 0x24 8001dcc: 3301 adds r3, #1 8001dce: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8001dd0: 683b ldr r3, [r7, #0] 8001dd2: 681a ldr r2, [r3, #0] 8001dd4: 6a7b ldr r3, [r7, #36] ; 0x24 8001dd6: fa22 f303 lsr.w r3, r2, r3 8001dda: 2b00 cmp r3, #0 8001ddc: f47f ae7e bne.w 8001adc } } 8001de0: bf00 nop 8001de2: bf00 nop 8001de4: 372c adds r7, #44 ; 0x2c 8001de6: 46bd mov sp, r7 8001de8: bc80 pop {r7} 8001dea: 4770 bx lr 8001dec: 40010400 .word 0x40010400 08001df0 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001df0: b480 push {r7} 8001df2: b085 sub sp, #20 8001df4: af00 add r7, sp, #0 8001df6: 6078 str r0, [r7, #4] 8001df8: 460b mov r3, r1 8001dfa: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001dfc: 687b ldr r3, [r7, #4] 8001dfe: 689a ldr r2, [r3, #8] 8001e00: 887b ldrh r3, [r7, #2] 8001e02: 4013 ands r3, r2 8001e04: 2b00 cmp r3, #0 8001e06: d002 beq.n 8001e0e { bitstatus = GPIO_PIN_SET; 8001e08: 2301 movs r3, #1 8001e0a: 73fb strb r3, [r7, #15] 8001e0c: e001 b.n 8001e12 } else { bitstatus = GPIO_PIN_RESET; 8001e0e: 2300 movs r3, #0 8001e10: 73fb strb r3, [r7, #15] } return bitstatus; 8001e12: 7bfb ldrb r3, [r7, #15] } 8001e14: 4618 mov r0, r3 8001e16: 3714 adds r7, #20 8001e18: 46bd mov sp, r7 8001e1a: bc80 pop {r7} 8001e1c: 4770 bx lr 08001e1e : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001e1e: b480 push {r7} 8001e20: b083 sub sp, #12 8001e22: af00 add r7, sp, #0 8001e24: 6078 str r0, [r7, #4] 8001e26: 460b mov r3, r1 8001e28: 807b strh r3, [r7, #2] 8001e2a: 4613 mov r3, r2 8001e2c: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001e2e: 787b ldrb r3, [r7, #1] 8001e30: 2b00 cmp r3, #0 8001e32: d003 beq.n 8001e3c { GPIOx->BSRR = GPIO_Pin; 8001e34: 887a ldrh r2, [r7, #2] 8001e36: 687b ldr r3, [r7, #4] 8001e38: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8001e3a: e003 b.n 8001e44 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8001e3c: 887b ldrh r3, [r7, #2] 8001e3e: 041a lsls r2, r3, #16 8001e40: 687b ldr r3, [r7, #4] 8001e42: 611a str r2, [r3, #16] } 8001e44: bf00 nop 8001e46: 370c adds r7, #12 8001e48: 46bd mov sp, r7 8001e4a: bc80 pop {r7} 8001e4c: 4770 bx lr ... 08001e50 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8001e50: b580 push {r7, lr} 8001e52: b084 sub sp, #16 8001e54: af00 add r7, sp, #0 8001e56: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8001e58: 687b ldr r3, [r7, #4] 8001e5a: 2b00 cmp r3, #0 8001e5c: d101 bne.n 8001e62 { return HAL_ERROR; 8001e5e: 2301 movs r3, #1 8001e60: e12b b.n 80020ba assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8001e62: 687b ldr r3, [r7, #4] 8001e64: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001e68: b2db uxtb r3, r3 8001e6a: 2b00 cmp r3, #0 8001e6c: d106 bne.n 8001e7c { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8001e6e: 687b ldr r3, [r7, #4] 8001e70: 2200 movs r2, #0 8001e72: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8001e76: 6878 ldr r0, [r7, #4] 8001e78: f7ff fb0a bl 8001490 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 2224 movs r2, #36 ; 0x24 8001e80: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001e84: 687b ldr r3, [r7, #4] 8001e86: 681b ldr r3, [r3, #0] 8001e88: 681a ldr r2, [r3, #0] 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 681b ldr r3, [r3, #0] 8001e8e: f022 0201 bic.w r2, r2, #1 8001e92: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8001e94: 687b ldr r3, [r7, #4] 8001e96: 681b ldr r3, [r3, #0] 8001e98: 681a ldr r2, [r3, #0] 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 681b ldr r3, [r3, #0] 8001e9e: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8001ea2: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 681b ldr r3, [r3, #0] 8001ea8: 681a ldr r2, [r3, #0] 8001eaa: 687b ldr r3, [r7, #4] 8001eac: 681b ldr r3, [r3, #0] 8001eae: f422 4200 bic.w r2, r2, #32768 ; 0x8000 8001eb2: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8001eb4: f001 fba0 bl 80035f8 8001eb8: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8001eba: 687b ldr r3, [r7, #4] 8001ebc: 685b ldr r3, [r3, #4] 8001ebe: 4a81 ldr r2, [pc, #516] ; (80020c4 ) 8001ec0: 4293 cmp r3, r2 8001ec2: d807 bhi.n 8001ed4 8001ec4: 68fb ldr r3, [r7, #12] 8001ec6: 4a80 ldr r2, [pc, #512] ; (80020c8 ) 8001ec8: 4293 cmp r3, r2 8001eca: bf94 ite ls 8001ecc: 2301 movls r3, #1 8001ece: 2300 movhi r3, #0 8001ed0: b2db uxtb r3, r3 8001ed2: e006 b.n 8001ee2 8001ed4: 68fb ldr r3, [r7, #12] 8001ed6: 4a7d ldr r2, [pc, #500] ; (80020cc ) 8001ed8: 4293 cmp r3, r2 8001eda: bf94 ite ls 8001edc: 2301 movls r3, #1 8001ede: 2300 movhi r3, #0 8001ee0: b2db uxtb r3, r3 8001ee2: 2b00 cmp r3, #0 8001ee4: d001 beq.n 8001eea { return HAL_ERROR; 8001ee6: 2301 movs r3, #1 8001ee8: e0e7 b.n 80020ba } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8001eea: 68fb ldr r3, [r7, #12] 8001eec: 4a78 ldr r2, [pc, #480] ; (80020d0 ) 8001eee: fba2 2303 umull r2, r3, r2, r3 8001ef2: 0c9b lsrs r3, r3, #18 8001ef4: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8001ef6: 687b ldr r3, [r7, #4] 8001ef8: 681b ldr r3, [r3, #0] 8001efa: 685b ldr r3, [r3, #4] 8001efc: f023 013f bic.w r1, r3, #63 ; 0x3f 8001f00: 687b ldr r3, [r7, #4] 8001f02: 681b ldr r3, [r3, #0] 8001f04: 68ba ldr r2, [r7, #8] 8001f06: 430a orrs r2, r1 8001f08: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8001f0a: 687b ldr r3, [r7, #4] 8001f0c: 681b ldr r3, [r3, #0] 8001f0e: 6a1b ldr r3, [r3, #32] 8001f10: f023 013f bic.w r1, r3, #63 ; 0x3f 8001f14: 687b ldr r3, [r7, #4] 8001f16: 685b ldr r3, [r3, #4] 8001f18: 4a6a ldr r2, [pc, #424] ; (80020c4 ) 8001f1a: 4293 cmp r3, r2 8001f1c: d802 bhi.n 8001f24 8001f1e: 68bb ldr r3, [r7, #8] 8001f20: 3301 adds r3, #1 8001f22: e009 b.n 8001f38 8001f24: 68bb ldr r3, [r7, #8] 8001f26: f44f 7296 mov.w r2, #300 ; 0x12c 8001f2a: fb02 f303 mul.w r3, r2, r3 8001f2e: 4a69 ldr r2, [pc, #420] ; (80020d4 ) 8001f30: fba2 2303 umull r2, r3, r2, r3 8001f34: 099b lsrs r3, r3, #6 8001f36: 3301 adds r3, #1 8001f38: 687a ldr r2, [r7, #4] 8001f3a: 6812 ldr r2, [r2, #0] 8001f3c: 430b orrs r3, r1 8001f3e: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8001f40: 687b ldr r3, [r7, #4] 8001f42: 681b ldr r3, [r3, #0] 8001f44: 69db ldr r3, [r3, #28] 8001f46: f423 424f bic.w r2, r3, #52992 ; 0xcf00 8001f4a: f022 02ff bic.w r2, r2, #255 ; 0xff 8001f4e: 687b ldr r3, [r7, #4] 8001f50: 685b ldr r3, [r3, #4] 8001f52: 495c ldr r1, [pc, #368] ; (80020c4 ) 8001f54: 428b cmp r3, r1 8001f56: d819 bhi.n 8001f8c 8001f58: 68fb ldr r3, [r7, #12] 8001f5a: 1e59 subs r1, r3, #1 8001f5c: 687b ldr r3, [r7, #4] 8001f5e: 685b ldr r3, [r3, #4] 8001f60: 005b lsls r3, r3, #1 8001f62: fbb1 f3f3 udiv r3, r1, r3 8001f66: 1c59 adds r1, r3, #1 8001f68: f640 73fc movw r3, #4092 ; 0xffc 8001f6c: 400b ands r3, r1 8001f6e: 2b00 cmp r3, #0 8001f70: d00a beq.n 8001f88 8001f72: 68fb ldr r3, [r7, #12] 8001f74: 1e59 subs r1, r3, #1 8001f76: 687b ldr r3, [r7, #4] 8001f78: 685b ldr r3, [r3, #4] 8001f7a: 005b lsls r3, r3, #1 8001f7c: fbb1 f3f3 udiv r3, r1, r3 8001f80: 3301 adds r3, #1 8001f82: f3c3 030b ubfx r3, r3, #0, #12 8001f86: e051 b.n 800202c 8001f88: 2304 movs r3, #4 8001f8a: e04f b.n 800202c 8001f8c: 687b ldr r3, [r7, #4] 8001f8e: 689b ldr r3, [r3, #8] 8001f90: 2b00 cmp r3, #0 8001f92: d111 bne.n 8001fb8 8001f94: 68fb ldr r3, [r7, #12] 8001f96: 1e58 subs r0, r3, #1 8001f98: 687b ldr r3, [r7, #4] 8001f9a: 6859 ldr r1, [r3, #4] 8001f9c: 460b mov r3, r1 8001f9e: 005b lsls r3, r3, #1 8001fa0: 440b add r3, r1 8001fa2: fbb0 f3f3 udiv r3, r0, r3 8001fa6: 3301 adds r3, #1 8001fa8: f3c3 030b ubfx r3, r3, #0, #12 8001fac: 2b00 cmp r3, #0 8001fae: bf0c ite eq 8001fb0: 2301 moveq r3, #1 8001fb2: 2300 movne r3, #0 8001fb4: b2db uxtb r3, r3 8001fb6: e012 b.n 8001fde 8001fb8: 68fb ldr r3, [r7, #12] 8001fba: 1e58 subs r0, r3, #1 8001fbc: 687b ldr r3, [r7, #4] 8001fbe: 6859 ldr r1, [r3, #4] 8001fc0: 460b mov r3, r1 8001fc2: 009b lsls r3, r3, #2 8001fc4: 440b add r3, r1 8001fc6: 0099 lsls r1, r3, #2 8001fc8: 440b add r3, r1 8001fca: fbb0 f3f3 udiv r3, r0, r3 8001fce: 3301 adds r3, #1 8001fd0: f3c3 030b ubfx r3, r3, #0, #12 8001fd4: 2b00 cmp r3, #0 8001fd6: bf0c ite eq 8001fd8: 2301 moveq r3, #1 8001fda: 2300 movne r3, #0 8001fdc: b2db uxtb r3, r3 8001fde: 2b00 cmp r3, #0 8001fe0: d001 beq.n 8001fe6 8001fe2: 2301 movs r3, #1 8001fe4: e022 b.n 800202c 8001fe6: 687b ldr r3, [r7, #4] 8001fe8: 689b ldr r3, [r3, #8] 8001fea: 2b00 cmp r3, #0 8001fec: d10e bne.n 800200c 8001fee: 68fb ldr r3, [r7, #12] 8001ff0: 1e58 subs r0, r3, #1 8001ff2: 687b ldr r3, [r7, #4] 8001ff4: 6859 ldr r1, [r3, #4] 8001ff6: 460b mov r3, r1 8001ff8: 005b lsls r3, r3, #1 8001ffa: 440b add r3, r1 8001ffc: fbb0 f3f3 udiv r3, r0, r3 8002000: 3301 adds r3, #1 8002002: f3c3 030b ubfx r3, r3, #0, #12 8002006: f443 4300 orr.w r3, r3, #32768 ; 0x8000 800200a: e00f b.n 800202c 800200c: 68fb ldr r3, [r7, #12] 800200e: 1e58 subs r0, r3, #1 8002010: 687b ldr r3, [r7, #4] 8002012: 6859 ldr r1, [r3, #4] 8002014: 460b mov r3, r1 8002016: 009b lsls r3, r3, #2 8002018: 440b add r3, r1 800201a: 0099 lsls r1, r3, #2 800201c: 440b add r3, r1 800201e: fbb0 f3f3 udiv r3, r0, r3 8002022: 3301 adds r3, #1 8002024: f3c3 030b ubfx r3, r3, #0, #12 8002028: f443 4340 orr.w r3, r3, #49152 ; 0xc000 800202c: 6879 ldr r1, [r7, #4] 800202e: 6809 ldr r1, [r1, #0] 8002030: 4313 orrs r3, r2 8002032: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: 681b ldr r3, [r3, #0] 800203a: f023 01c0 bic.w r1, r3, #192 ; 0xc0 800203e: 687b ldr r3, [r7, #4] 8002040: 69da ldr r2, [r3, #28] 8002042: 687b ldr r3, [r7, #4] 8002044: 6a1b ldr r3, [r3, #32] 8002046: 431a orrs r2, r3 8002048: 687b ldr r3, [r7, #4] 800204a: 681b ldr r3, [r3, #0] 800204c: 430a orrs r2, r1 800204e: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002050: 687b ldr r3, [r7, #4] 8002052: 681b ldr r3, [r3, #0] 8002054: 689b ldr r3, [r3, #8] 8002056: f423 4303 bic.w r3, r3, #33536 ; 0x8300 800205a: f023 03ff bic.w r3, r3, #255 ; 0xff 800205e: 687a ldr r2, [r7, #4] 8002060: 6911 ldr r1, [r2, #16] 8002062: 687a ldr r2, [r7, #4] 8002064: 68d2 ldr r2, [r2, #12] 8002066: 4311 orrs r1, r2 8002068: 687a ldr r2, [r7, #4] 800206a: 6812 ldr r2, [r2, #0] 800206c: 430b orrs r3, r1 800206e: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002070: 687b ldr r3, [r7, #4] 8002072: 681b ldr r3, [r3, #0] 8002074: 68db ldr r3, [r3, #12] 8002076: f023 01ff bic.w r1, r3, #255 ; 0xff 800207a: 687b ldr r3, [r7, #4] 800207c: 695a ldr r2, [r3, #20] 800207e: 687b ldr r3, [r7, #4] 8002080: 699b ldr r3, [r3, #24] 8002082: 431a orrs r2, r3 8002084: 687b ldr r3, [r7, #4] 8002086: 681b ldr r3, [r3, #0] 8002088: 430a orrs r2, r1 800208a: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800208c: 687b ldr r3, [r7, #4] 800208e: 681b ldr r3, [r3, #0] 8002090: 681a ldr r2, [r3, #0] 8002092: 687b ldr r3, [r7, #4] 8002094: 681b ldr r3, [r3, #0] 8002096: f042 0201 orr.w r2, r2, #1 800209a: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800209c: 687b ldr r3, [r7, #4] 800209e: 2200 movs r2, #0 80020a0: 641a str r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_READY; 80020a2: 687b ldr r3, [r7, #4] 80020a4: 2220 movs r2, #32 80020a6: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->PreviousState = I2C_STATE_NONE; 80020aa: 687b ldr r3, [r7, #4] 80020ac: 2200 movs r2, #0 80020ae: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 80020b0: 687b ldr r3, [r7, #4] 80020b2: 2200 movs r2, #0 80020b4: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 80020b8: 2300 movs r3, #0 } 80020ba: 4618 mov r0, r3 80020bc: 3710 adds r7, #16 80020be: 46bd mov sp, r7 80020c0: bd80 pop {r7, pc} 80020c2: bf00 nop 80020c4: 000186a0 .word 0x000186a0 80020c8: 001e847f .word 0x001e847f 80020cc: 003d08ff .word 0x003d08ff 80020d0: 431bde83 .word 0x431bde83 80020d4: 10624dd3 .word 0x10624dd3 080020d8 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80020d8: b580 push {r7, lr} 80020da: b088 sub sp, #32 80020dc: af02 add r7, sp, #8 80020de: 60f8 str r0, [r7, #12] 80020e0: 4608 mov r0, r1 80020e2: 4611 mov r1, r2 80020e4: 461a mov r2, r3 80020e6: 4603 mov r3, r0 80020e8: 817b strh r3, [r7, #10] 80020ea: 460b mov r3, r1 80020ec: 813b strh r3, [r7, #8] 80020ee: 4613 mov r3, r2 80020f0: 80fb strh r3, [r7, #6] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 80020f2: f7ff fbd7 bl 80018a4 80020f6: 6178 str r0, [r7, #20] /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80020f8: 68fb ldr r3, [r7, #12] 80020fa: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80020fe: b2db uxtb r3, r3 8002100: 2b20 cmp r3, #32 8002102: f040 80d9 bne.w 80022b8 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 8002106: 697b ldr r3, [r7, #20] 8002108: 9300 str r3, [sp, #0] 800210a: 2319 movs r3, #25 800210c: 2201 movs r2, #1 800210e: 496d ldr r1, [pc, #436] ; (80022c4 ) 8002110: 68f8 ldr r0, [r7, #12] 8002112: f000 fcc1 bl 8002a98 8002116: 4603 mov r3, r0 8002118: 2b00 cmp r3, #0 800211a: d001 beq.n 8002120 { return HAL_BUSY; 800211c: 2302 movs r3, #2 800211e: e0cc b.n 80022ba } /* Process Locked */ __HAL_LOCK(hi2c); 8002120: 68fb ldr r3, [r7, #12] 8002122: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002126: 2b01 cmp r3, #1 8002128: d101 bne.n 800212e 800212a: 2302 movs r3, #2 800212c: e0c5 b.n 80022ba 800212e: 68fb ldr r3, [r7, #12] 8002130: 2201 movs r2, #1 8002132: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 8002136: 68fb ldr r3, [r7, #12] 8002138: 681b ldr r3, [r3, #0] 800213a: 681b ldr r3, [r3, #0] 800213c: f003 0301 and.w r3, r3, #1 8002140: 2b01 cmp r3, #1 8002142: d007 beq.n 8002154 { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002144: 68fb ldr r3, [r7, #12] 8002146: 681b ldr r3, [r3, #0] 8002148: 681a ldr r2, [r3, #0] 800214a: 68fb ldr r3, [r7, #12] 800214c: 681b ldr r3, [r3, #0] 800214e: f042 0201 orr.w r2, r2, #1 8002152: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8002154: 68fb ldr r3, [r7, #12] 8002156: 681b ldr r3, [r3, #0] 8002158: 681a ldr r2, [r3, #0] 800215a: 68fb ldr r3, [r7, #12] 800215c: 681b ldr r3, [r3, #0] 800215e: f422 6200 bic.w r2, r2, #2048 ; 0x800 8002162: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_TX; 8002164: 68fb ldr r3, [r7, #12] 8002166: 2221 movs r2, #33 ; 0x21 8002168: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 800216c: 68fb ldr r3, [r7, #12] 800216e: 2240 movs r2, #64 ; 0x40 8002170: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002174: 68fb ldr r3, [r7, #12] 8002176: 2200 movs r2, #0 8002178: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 800217a: 68fb ldr r3, [r7, #12] 800217c: 6a3a ldr r2, [r7, #32] 800217e: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8002180: 68fb ldr r3, [r7, #12] 8002182: 8cba ldrh r2, [r7, #36] ; 0x24 8002184: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 8002186: 68fb ldr r3, [r7, #12] 8002188: 8d5b ldrh r3, [r3, #42] ; 0x2a 800218a: b29a uxth r2, r3 800218c: 68fb ldr r3, [r7, #12] 800218e: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002190: 68fb ldr r3, [r7, #12] 8002192: 4a4d ldr r2, [pc, #308] ; (80022c8 ) 8002194: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 8002196: 88f8 ldrh r0, [r7, #6] 8002198: 893a ldrh r2, [r7, #8] 800219a: 8979 ldrh r1, [r7, #10] 800219c: 697b ldr r3, [r7, #20] 800219e: 9301 str r3, [sp, #4] 80021a0: 6abb ldr r3, [r7, #40] ; 0x28 80021a2: 9300 str r3, [sp, #0] 80021a4: 4603 mov r3, r0 80021a6: 68f8 ldr r0, [r7, #12] 80021a8: f000 faf8 bl 800279c 80021ac: 4603 mov r3, r0 80021ae: 2b00 cmp r3, #0 80021b0: d052 beq.n 8002258 { return HAL_ERROR; 80021b2: 2301 movs r3, #1 80021b4: e081 b.n 80022ba } while (hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80021b6: 697a ldr r2, [r7, #20] 80021b8: 6ab9 ldr r1, [r7, #40] ; 0x28 80021ba: 68f8 ldr r0, [r7, #12] 80021bc: f000 fd42 bl 8002c44 80021c0: 4603 mov r3, r0 80021c2: 2b00 cmp r3, #0 80021c4: d00d beq.n 80021e2 { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 80021c6: 68fb ldr r3, [r7, #12] 80021c8: 6c1b ldr r3, [r3, #64] ; 0x40 80021ca: 2b04 cmp r3, #4 80021cc: d107 bne.n 80021de { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80021ce: 68fb ldr r3, [r7, #12] 80021d0: 681b ldr r3, [r3, #0] 80021d2: 681a ldr r2, [r3, #0] 80021d4: 68fb ldr r3, [r7, #12] 80021d6: 681b ldr r3, [r3, #0] 80021d8: f442 7200 orr.w r2, r2, #512 ; 0x200 80021dc: 601a str r2, [r3, #0] } return HAL_ERROR; 80021de: 2301 movs r3, #1 80021e0: e06b b.n 80022ba } /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 80021e2: 68fb ldr r3, [r7, #12] 80021e4: 6a5b ldr r3, [r3, #36] ; 0x24 80021e6: 781a ldrb r2, [r3, #0] 80021e8: 68fb ldr r3, [r7, #12] 80021ea: 681b ldr r3, [r3, #0] 80021ec: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80021ee: 68fb ldr r3, [r7, #12] 80021f0: 6a5b ldr r3, [r3, #36] ; 0x24 80021f2: 1c5a adds r2, r3, #1 80021f4: 68fb ldr r3, [r7, #12] 80021f6: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80021f8: 68fb ldr r3, [r7, #12] 80021fa: 8d1b ldrh r3, [r3, #40] ; 0x28 80021fc: 3b01 subs r3, #1 80021fe: b29a uxth r2, r3 8002200: 68fb ldr r3, [r7, #12] 8002202: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002204: 68fb ldr r3, [r7, #12] 8002206: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002208: b29b uxth r3, r3 800220a: 3b01 subs r3, #1 800220c: b29a uxth r2, r3 800220e: 68fb ldr r3, [r7, #12] 8002210: 855a strh r2, [r3, #42] ; 0x2a if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 8002212: 68fb ldr r3, [r7, #12] 8002214: 681b ldr r3, [r3, #0] 8002216: 695b ldr r3, [r3, #20] 8002218: f003 0304 and.w r3, r3, #4 800221c: 2b04 cmp r3, #4 800221e: d11b bne.n 8002258 8002220: 68fb ldr r3, [r7, #12] 8002222: 8d1b ldrh r3, [r3, #40] ; 0x28 8002224: 2b00 cmp r3, #0 8002226: d017 beq.n 8002258 { /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 8002228: 68fb ldr r3, [r7, #12] 800222a: 6a5b ldr r3, [r3, #36] ; 0x24 800222c: 781a ldrb r2, [r3, #0] 800222e: 68fb ldr r3, [r7, #12] 8002230: 681b ldr r3, [r3, #0] 8002232: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002234: 68fb ldr r3, [r7, #12] 8002236: 6a5b ldr r3, [r3, #36] ; 0x24 8002238: 1c5a adds r2, r3, #1 800223a: 68fb ldr r3, [r7, #12] 800223c: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800223e: 68fb ldr r3, [r7, #12] 8002240: 8d1b ldrh r3, [r3, #40] ; 0x28 8002242: 3b01 subs r3, #1 8002244: b29a uxth r2, r3 8002246: 68fb ldr r3, [r7, #12] 8002248: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800224a: 68fb ldr r3, [r7, #12] 800224c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800224e: b29b uxth r3, r3 8002250: 3b01 subs r3, #1 8002252: b29a uxth r2, r3 8002254: 68fb ldr r3, [r7, #12] 8002256: 855a strh r2, [r3, #42] ; 0x2a while (hi2c->XferSize > 0U) 8002258: 68fb ldr r3, [r7, #12] 800225a: 8d1b ldrh r3, [r3, #40] ; 0x28 800225c: 2b00 cmp r3, #0 800225e: d1aa bne.n 80021b6 } } /* Wait until BTF flag is set */ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8002260: 697a ldr r2, [r7, #20] 8002262: 6ab9 ldr r1, [r7, #40] ; 0x28 8002264: 68f8 ldr r0, [r7, #12] 8002266: f000 fd2e bl 8002cc6 800226a: 4603 mov r3, r0 800226c: 2b00 cmp r3, #0 800226e: d00d beq.n 800228c { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 8002270: 68fb ldr r3, [r7, #12] 8002272: 6c1b ldr r3, [r3, #64] ; 0x40 8002274: 2b04 cmp r3, #4 8002276: d107 bne.n 8002288 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002278: 68fb ldr r3, [r7, #12] 800227a: 681b ldr r3, [r3, #0] 800227c: 681a ldr r2, [r3, #0] 800227e: 68fb ldr r3, [r7, #12] 8002280: 681b ldr r3, [r3, #0] 8002282: f442 7200 orr.w r2, r2, #512 ; 0x200 8002286: 601a str r2, [r3, #0] } return HAL_ERROR; 8002288: 2301 movs r3, #1 800228a: e016 b.n 80022ba } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 800228c: 68fb ldr r3, [r7, #12] 800228e: 681b ldr r3, [r3, #0] 8002290: 681a ldr r2, [r3, #0] 8002292: 68fb ldr r3, [r7, #12] 8002294: 681b ldr r3, [r3, #0] 8002296: f442 7200 orr.w r2, r2, #512 ; 0x200 800229a: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 800229c: 68fb ldr r3, [r7, #12] 800229e: 2220 movs r2, #32 80022a0: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 80022a4: 68fb ldr r3, [r7, #12] 80022a6: 2200 movs r2, #0 80022a8: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80022ac: 68fb ldr r3, [r7, #12] 80022ae: 2200 movs r2, #0 80022b0: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80022b4: 2300 movs r3, #0 80022b6: e000 b.n 80022ba } else { return HAL_BUSY; 80022b8: 2302 movs r3, #2 } } 80022ba: 4618 mov r0, r3 80022bc: 3718 adds r7, #24 80022be: 46bd mov sp, r7 80022c0: bd80 pop {r7, pc} 80022c2: bf00 nop 80022c4: 00100002 .word 0x00100002 80022c8: ffff0000 .word 0xffff0000 080022cc : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80022cc: b580 push {r7, lr} 80022ce: b08c sub sp, #48 ; 0x30 80022d0: af02 add r7, sp, #8 80022d2: 60f8 str r0, [r7, #12] 80022d4: 4608 mov r0, r1 80022d6: 4611 mov r1, r2 80022d8: 461a mov r2, r3 80022da: 4603 mov r3, r0 80022dc: 817b strh r3, [r7, #10] 80022de: 460b mov r3, r1 80022e0: 813b strh r3, [r7, #8] 80022e2: 4613 mov r3, r2 80022e4: 80fb strh r3, [r7, #6] __IO uint32_t count = 0U; 80022e6: 2300 movs r3, #0 80022e8: 623b str r3, [r7, #32] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 80022ea: f7ff fadb bl 80018a4 80022ee: 6278 str r0, [r7, #36] ; 0x24 /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80022f0: 68fb ldr r3, [r7, #12] 80022f2: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80022f6: b2db uxtb r3, r3 80022f8: 2b20 cmp r3, #32 80022fa: f040 8244 bne.w 8002786 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 80022fe: 6a7b ldr r3, [r7, #36] ; 0x24 8002300: 9300 str r3, [sp, #0] 8002302: 2319 movs r3, #25 8002304: 2201 movs r2, #1 8002306: 4982 ldr r1, [pc, #520] ; (8002510 ) 8002308: 68f8 ldr r0, [r7, #12] 800230a: f000 fbc5 bl 8002a98 800230e: 4603 mov r3, r0 8002310: 2b00 cmp r3, #0 8002312: d001 beq.n 8002318 { return HAL_BUSY; 8002314: 2302 movs r3, #2 8002316: e237 b.n 8002788 } /* Process Locked */ __HAL_LOCK(hi2c); 8002318: 68fb ldr r3, [r7, #12] 800231a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800231e: 2b01 cmp r3, #1 8002320: d101 bne.n 8002326 8002322: 2302 movs r3, #2 8002324: e230 b.n 8002788 8002326: 68fb ldr r3, [r7, #12] 8002328: 2201 movs r2, #1 800232a: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 800232e: 68fb ldr r3, [r7, #12] 8002330: 681b ldr r3, [r3, #0] 8002332: 681b ldr r3, [r3, #0] 8002334: f003 0301 and.w r3, r3, #1 8002338: 2b01 cmp r3, #1 800233a: d007 beq.n 800234c { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800233c: 68fb ldr r3, [r7, #12] 800233e: 681b ldr r3, [r3, #0] 8002340: 681a ldr r2, [r3, #0] 8002342: 68fb ldr r3, [r7, #12] 8002344: 681b ldr r3, [r3, #0] 8002346: f042 0201 orr.w r2, r2, #1 800234a: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 800234c: 68fb ldr r3, [r7, #12] 800234e: 681b ldr r3, [r3, #0] 8002350: 681a ldr r2, [r3, #0] 8002352: 68fb ldr r3, [r7, #12] 8002354: 681b ldr r3, [r3, #0] 8002356: f422 6200 bic.w r2, r2, #2048 ; 0x800 800235a: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_RX; 800235c: 68fb ldr r3, [r7, #12] 800235e: 2222 movs r2, #34 ; 0x22 8002360: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 8002364: 68fb ldr r3, [r7, #12] 8002366: 2240 movs r2, #64 ; 0x40 8002368: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800236c: 68fb ldr r3, [r7, #12] 800236e: 2200 movs r2, #0 8002370: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8002372: 68fb ldr r3, [r7, #12] 8002374: 6b3a ldr r2, [r7, #48] ; 0x30 8002376: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8002378: 68fb ldr r3, [r7, #12] 800237a: 8eba ldrh r2, [r7, #52] ; 0x34 800237c: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 800237e: 68fb ldr r3, [r7, #12] 8002380: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002382: b29a uxth r2, r3 8002384: 68fb ldr r3, [r7, #12] 8002386: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002388: 68fb ldr r3, [r7, #12] 800238a: 4a62 ldr r2, [pc, #392] ; (8002514 ) 800238c: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 800238e: 88f8 ldrh r0, [r7, #6] 8002390: 893a ldrh r2, [r7, #8] 8002392: 8979 ldrh r1, [r7, #10] 8002394: 6a7b ldr r3, [r7, #36] ; 0x24 8002396: 9301 str r3, [sp, #4] 8002398: 6bbb ldr r3, [r7, #56] ; 0x38 800239a: 9300 str r3, [sp, #0] 800239c: 4603 mov r3, r0 800239e: 68f8 ldr r0, [r7, #12] 80023a0: f000 fa92 bl 80028c8 80023a4: 4603 mov r3, r0 80023a6: 2b00 cmp r3, #0 80023a8: d001 beq.n 80023ae { return HAL_ERROR; 80023aa: 2301 movs r3, #1 80023ac: e1ec b.n 8002788 } if (hi2c->XferSize == 0U) 80023ae: 68fb ldr r3, [r7, #12] 80023b0: 8d1b ldrh r3, [r3, #40] ; 0x28 80023b2: 2b00 cmp r3, #0 80023b4: d113 bne.n 80023de { /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 80023b6: 2300 movs r3, #0 80023b8: 61fb str r3, [r7, #28] 80023ba: 68fb ldr r3, [r7, #12] 80023bc: 681b ldr r3, [r3, #0] 80023be: 695b ldr r3, [r3, #20] 80023c0: 61fb str r3, [r7, #28] 80023c2: 68fb ldr r3, [r7, #12] 80023c4: 681b ldr r3, [r3, #0] 80023c6: 699b ldr r3, [r3, #24] 80023c8: 61fb str r3, [r7, #28] 80023ca: 69fb ldr r3, [r7, #28] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80023cc: 68fb ldr r3, [r7, #12] 80023ce: 681b ldr r3, [r3, #0] 80023d0: 681a ldr r2, [r3, #0] 80023d2: 68fb ldr r3, [r7, #12] 80023d4: 681b ldr r3, [r3, #0] 80023d6: f442 7200 orr.w r2, r2, #512 ; 0x200 80023da: 601a str r2, [r3, #0] 80023dc: e1c0 b.n 8002760 } else if (hi2c->XferSize == 1U) 80023de: 68fb ldr r3, [r7, #12] 80023e0: 8d1b ldrh r3, [r3, #40] ; 0x28 80023e2: 2b01 cmp r3, #1 80023e4: d11e bne.n 8002424 { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80023e6: 68fb ldr r3, [r7, #12] 80023e8: 681b ldr r3, [r3, #0] 80023ea: 681a ldr r2, [r3, #0] 80023ec: 68fb ldr r3, [r7, #12] 80023ee: 681b ldr r3, [r3, #0] 80023f0: f422 6280 bic.w r2, r2, #1024 ; 0x400 80023f4: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 80023f6: b672 cpsid i } 80023f8: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 80023fa: 2300 movs r3, #0 80023fc: 61bb str r3, [r7, #24] 80023fe: 68fb ldr r3, [r7, #12] 8002400: 681b ldr r3, [r3, #0] 8002402: 695b ldr r3, [r3, #20] 8002404: 61bb str r3, [r7, #24] 8002406: 68fb ldr r3, [r7, #12] 8002408: 681b ldr r3, [r3, #0] 800240a: 699b ldr r3, [r3, #24] 800240c: 61bb str r3, [r7, #24] 800240e: 69bb ldr r3, [r7, #24] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002410: 68fb ldr r3, [r7, #12] 8002412: 681b ldr r3, [r3, #0] 8002414: 681a ldr r2, [r3, #0] 8002416: 68fb ldr r3, [r7, #12] 8002418: 681b ldr r3, [r3, #0] 800241a: f442 7200 orr.w r2, r2, #512 ; 0x200 800241e: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8002420: b662 cpsie i } 8002422: e035 b.n 8002490 /* Re-enable IRQs */ __enable_irq(); } else if (hi2c->XferSize == 2U) 8002424: 68fb ldr r3, [r7, #12] 8002426: 8d1b ldrh r3, [r3, #40] ; 0x28 8002428: 2b02 cmp r3, #2 800242a: d11e bne.n 800246a { /* Enable Pos */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 800242c: 68fb ldr r3, [r7, #12] 800242e: 681b ldr r3, [r3, #0] 8002430: 681a ldr r2, [r3, #0] 8002432: 68fb ldr r3, [r7, #12] 8002434: 681b ldr r3, [r3, #0] 8002436: f442 6200 orr.w r2, r2, #2048 ; 0x800 800243a: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 800243c: b672 cpsid i } 800243e: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8002440: 2300 movs r3, #0 8002442: 617b str r3, [r7, #20] 8002444: 68fb ldr r3, [r7, #12] 8002446: 681b ldr r3, [r3, #0] 8002448: 695b ldr r3, [r3, #20] 800244a: 617b str r3, [r7, #20] 800244c: 68fb ldr r3, [r7, #12] 800244e: 681b ldr r3, [r3, #0] 8002450: 699b ldr r3, [r3, #24] 8002452: 617b str r3, [r7, #20] 8002454: 697b ldr r3, [r7, #20] /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 8002456: 68fb ldr r3, [r7, #12] 8002458: 681b ldr r3, [r3, #0] 800245a: 681a ldr r2, [r3, #0] 800245c: 68fb ldr r3, [r7, #12] 800245e: 681b ldr r3, [r3, #0] 8002460: f422 6280 bic.w r2, r2, #1024 ; 0x400 8002464: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8002466: b662 cpsie i } 8002468: e012 b.n 8002490 __enable_irq(); } else { /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 800246a: 68fb ldr r3, [r7, #12] 800246c: 681b ldr r3, [r3, #0] 800246e: 681a ldr r2, [r3, #0] 8002470: 68fb ldr r3, [r7, #12] 8002472: 681b ldr r3, [r3, #0] 8002474: f442 6280 orr.w r2, r2, #1024 ; 0x400 8002478: 601a str r2, [r3, #0] /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 800247a: 2300 movs r3, #0 800247c: 613b str r3, [r7, #16] 800247e: 68fb ldr r3, [r7, #12] 8002480: 681b ldr r3, [r3, #0] 8002482: 695b ldr r3, [r3, #20] 8002484: 613b str r3, [r7, #16] 8002486: 68fb ldr r3, [r7, #12] 8002488: 681b ldr r3, [r3, #0] 800248a: 699b ldr r3, [r3, #24] 800248c: 613b str r3, [r7, #16] 800248e: 693b ldr r3, [r7, #16] } while (hi2c->XferSize > 0U) 8002490: e166 b.n 8002760 { if (hi2c->XferSize <= 3U) 8002492: 68fb ldr r3, [r7, #12] 8002494: 8d1b ldrh r3, [r3, #40] ; 0x28 8002496: 2b03 cmp r3, #3 8002498: f200 811f bhi.w 80026da { /* One byte */ if (hi2c->XferSize == 1U) 800249c: 68fb ldr r3, [r7, #12] 800249e: 8d1b ldrh r3, [r3, #40] ; 0x28 80024a0: 2b01 cmp r3, #1 80024a2: d123 bne.n 80024ec { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80024a4: 6a7a ldr r2, [r7, #36] ; 0x24 80024a6: 6bb9 ldr r1, [r7, #56] ; 0x38 80024a8: 68f8 ldr r0, [r7, #12] 80024aa: f000 fc4d bl 8002d48 80024ae: 4603 mov r3, r0 80024b0: 2b00 cmp r3, #0 80024b2: d001 beq.n 80024b8 { return HAL_ERROR; 80024b4: 2301 movs r3, #1 80024b6: e167 b.n 8002788 } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80024b8: 68fb ldr r3, [r7, #12] 80024ba: 681b ldr r3, [r3, #0] 80024bc: 691a ldr r2, [r3, #16] 80024be: 68fb ldr r3, [r7, #12] 80024c0: 6a5b ldr r3, [r3, #36] ; 0x24 80024c2: b2d2 uxtb r2, r2 80024c4: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80024c6: 68fb ldr r3, [r7, #12] 80024c8: 6a5b ldr r3, [r3, #36] ; 0x24 80024ca: 1c5a adds r2, r3, #1 80024cc: 68fb ldr r3, [r7, #12] 80024ce: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80024d0: 68fb ldr r3, [r7, #12] 80024d2: 8d1b ldrh r3, [r3, #40] ; 0x28 80024d4: 3b01 subs r3, #1 80024d6: b29a uxth r2, r3 80024d8: 68fb ldr r3, [r7, #12] 80024da: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80024dc: 68fb ldr r3, [r7, #12] 80024de: 8d5b ldrh r3, [r3, #42] ; 0x2a 80024e0: b29b uxth r3, r3 80024e2: 3b01 subs r3, #1 80024e4: b29a uxth r2, r3 80024e6: 68fb ldr r3, [r7, #12] 80024e8: 855a strh r2, [r3, #42] ; 0x2a 80024ea: e139 b.n 8002760 } /* Two bytes */ else if (hi2c->XferSize == 2U) 80024ec: 68fb ldr r3, [r7, #12] 80024ee: 8d1b ldrh r3, [r3, #40] ; 0x28 80024f0: 2b02 cmp r3, #2 80024f2: d152 bne.n 800259a { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 80024f4: 6a7b ldr r3, [r7, #36] ; 0x24 80024f6: 9300 str r3, [sp, #0] 80024f8: 6bbb ldr r3, [r7, #56] ; 0x38 80024fa: 2200 movs r2, #0 80024fc: 4906 ldr r1, [pc, #24] ; (8002518 ) 80024fe: 68f8 ldr r0, [r7, #12] 8002500: f000 faca bl 8002a98 8002504: 4603 mov r3, r0 8002506: 2b00 cmp r3, #0 8002508: d008 beq.n 800251c { return HAL_ERROR; 800250a: 2301 movs r3, #1 800250c: e13c b.n 8002788 800250e: bf00 nop 8002510: 00100002 .word 0x00100002 8002514: ffff0000 .word 0xffff0000 8002518: 00010004 .word 0x00010004 __ASM volatile ("cpsid i" : : : "memory"); 800251c: b672 cpsid i } 800251e: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002520: 68fb ldr r3, [r7, #12] 8002522: 681b ldr r3, [r3, #0] 8002524: 681a ldr r2, [r3, #0] 8002526: 68fb ldr r3, [r7, #12] 8002528: 681b ldr r3, [r3, #0] 800252a: f442 7200 orr.w r2, r2, #512 ; 0x200 800252e: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002530: 68fb ldr r3, [r7, #12] 8002532: 681b ldr r3, [r3, #0] 8002534: 691a ldr r2, [r3, #16] 8002536: 68fb ldr r3, [r7, #12] 8002538: 6a5b ldr r3, [r3, #36] ; 0x24 800253a: b2d2 uxtb r2, r2 800253c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800253e: 68fb ldr r3, [r7, #12] 8002540: 6a5b ldr r3, [r3, #36] ; 0x24 8002542: 1c5a adds r2, r3, #1 8002544: 68fb ldr r3, [r7, #12] 8002546: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002548: 68fb ldr r3, [r7, #12] 800254a: 8d1b ldrh r3, [r3, #40] ; 0x28 800254c: 3b01 subs r3, #1 800254e: b29a uxth r2, r3 8002550: 68fb ldr r3, [r7, #12] 8002552: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002554: 68fb ldr r3, [r7, #12] 8002556: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002558: b29b uxth r3, r3 800255a: 3b01 subs r3, #1 800255c: b29a uxth r2, r3 800255e: 68fb ldr r3, [r7, #12] 8002560: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 8002562: b662 cpsie i } 8002564: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002566: 68fb ldr r3, [r7, #12] 8002568: 681b ldr r3, [r3, #0] 800256a: 691a ldr r2, [r3, #16] 800256c: 68fb ldr r3, [r7, #12] 800256e: 6a5b ldr r3, [r3, #36] ; 0x24 8002570: b2d2 uxtb r2, r2 8002572: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002574: 68fb ldr r3, [r7, #12] 8002576: 6a5b ldr r3, [r3, #36] ; 0x24 8002578: 1c5a adds r2, r3, #1 800257a: 68fb ldr r3, [r7, #12] 800257c: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 800257e: 68fb ldr r3, [r7, #12] 8002580: 8d1b ldrh r3, [r3, #40] ; 0x28 8002582: 3b01 subs r3, #1 8002584: b29a uxth r2, r3 8002586: 68fb ldr r3, [r7, #12] 8002588: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800258a: 68fb ldr r3, [r7, #12] 800258c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800258e: b29b uxth r3, r3 8002590: 3b01 subs r3, #1 8002592: b29a uxth r2, r3 8002594: 68fb ldr r3, [r7, #12] 8002596: 855a strh r2, [r3, #42] ; 0x2a 8002598: e0e2 b.n 8002760 } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 800259a: 6a7b ldr r3, [r7, #36] ; 0x24 800259c: 9300 str r3, [sp, #0] 800259e: 6bbb ldr r3, [r7, #56] ; 0x38 80025a0: 2200 movs r2, #0 80025a2: 497b ldr r1, [pc, #492] ; (8002790 ) 80025a4: 68f8 ldr r0, [r7, #12] 80025a6: f000 fa77 bl 8002a98 80025aa: 4603 mov r3, r0 80025ac: 2b00 cmp r3, #0 80025ae: d001 beq.n 80025b4 { return HAL_ERROR; 80025b0: 2301 movs r3, #1 80025b2: e0e9 b.n 8002788 } /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80025b4: 68fb ldr r3, [r7, #12] 80025b6: 681b ldr r3, [r3, #0] 80025b8: 681a ldr r2, [r3, #0] 80025ba: 68fb ldr r3, [r7, #12] 80025bc: 681b ldr r3, [r3, #0] 80025be: f422 6280 bic.w r2, r2, #1024 ; 0x400 80025c2: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 80025c4: b672 cpsid i } 80025c6: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80025c8: 68fb ldr r3, [r7, #12] 80025ca: 681b ldr r3, [r3, #0] 80025cc: 691a ldr r2, [r3, #16] 80025ce: 68fb ldr r3, [r7, #12] 80025d0: 6a5b ldr r3, [r3, #36] ; 0x24 80025d2: b2d2 uxtb r2, r2 80025d4: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80025d6: 68fb ldr r3, [r7, #12] 80025d8: 6a5b ldr r3, [r3, #36] ; 0x24 80025da: 1c5a adds r2, r3, #1 80025dc: 68fb ldr r3, [r7, #12] 80025de: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80025e0: 68fb ldr r3, [r7, #12] 80025e2: 8d1b ldrh r3, [r3, #40] ; 0x28 80025e4: 3b01 subs r3, #1 80025e6: b29a uxth r2, r3 80025e8: 68fb ldr r3, [r7, #12] 80025ea: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80025ec: 68fb ldr r3, [r7, #12] 80025ee: 8d5b ldrh r3, [r3, #42] ; 0x2a 80025f0: b29b uxth r3, r3 80025f2: 3b01 subs r3, #1 80025f4: b29a uxth r2, r3 80025f6: 68fb ldr r3, [r7, #12] 80025f8: 855a strh r2, [r3, #42] ; 0x2a /* Wait until BTF flag is set */ count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 80025fa: 4b66 ldr r3, [pc, #408] ; (8002794 ) 80025fc: 681b ldr r3, [r3, #0] 80025fe: 08db lsrs r3, r3, #3 8002600: 4a65 ldr r2, [pc, #404] ; (8002798 ) 8002602: fba2 2303 umull r2, r3, r2, r3 8002606: 0a1a lsrs r2, r3, #8 8002608: 4613 mov r3, r2 800260a: 009b lsls r3, r3, #2 800260c: 4413 add r3, r2 800260e: 00da lsls r2, r3, #3 8002610: 1ad3 subs r3, r2, r3 8002612: 623b str r3, [r7, #32] do { count--; 8002614: 6a3b ldr r3, [r7, #32] 8002616: 3b01 subs r3, #1 8002618: 623b str r3, [r7, #32] if (count == 0U) 800261a: 6a3b ldr r3, [r7, #32] 800261c: 2b00 cmp r3, #0 800261e: d118 bne.n 8002652 { hi2c->PreviousState = I2C_STATE_NONE; 8002620: 68fb ldr r3, [r7, #12] 8002622: 2200 movs r2, #0 8002624: 631a str r2, [r3, #48] ; 0x30 hi2c->State = HAL_I2C_STATE_READY; 8002626: 68fb ldr r3, [r7, #12] 8002628: 2220 movs r2, #32 800262a: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 800262e: 68fb ldr r3, [r7, #12] 8002630: 2200 movs r2, #0 8002632: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8002636: 68fb ldr r3, [r7, #12] 8002638: 6c1b ldr r3, [r3, #64] ; 0x40 800263a: f043 0220 orr.w r2, r3, #32 800263e: 68fb ldr r3, [r7, #12] 8002640: 641a str r2, [r3, #64] ; 0x40 __ASM volatile ("cpsie i" : : : "memory"); 8002642: b662 cpsie i } 8002644: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002646: 68fb ldr r3, [r7, #12] 8002648: 2200 movs r2, #0 800264a: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_ERROR; 800264e: 2301 movs r3, #1 8002650: e09a b.n 8002788 } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 8002652: 68fb ldr r3, [r7, #12] 8002654: 681b ldr r3, [r3, #0] 8002656: 695b ldr r3, [r3, #20] 8002658: f003 0304 and.w r3, r3, #4 800265c: 2b04 cmp r3, #4 800265e: d1d9 bne.n 8002614 /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002660: 68fb ldr r3, [r7, #12] 8002662: 681b ldr r3, [r3, #0] 8002664: 681a ldr r2, [r3, #0] 8002666: 68fb ldr r3, [r7, #12] 8002668: 681b ldr r3, [r3, #0] 800266a: f442 7200 orr.w r2, r2, #512 ; 0x200 800266e: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002670: 68fb ldr r3, [r7, #12] 8002672: 681b ldr r3, [r3, #0] 8002674: 691a ldr r2, [r3, #16] 8002676: 68fb ldr r3, [r7, #12] 8002678: 6a5b ldr r3, [r3, #36] ; 0x24 800267a: b2d2 uxtb r2, r2 800267c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800267e: 68fb ldr r3, [r7, #12] 8002680: 6a5b ldr r3, [r3, #36] ; 0x24 8002682: 1c5a adds r2, r3, #1 8002684: 68fb ldr r3, [r7, #12] 8002686: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002688: 68fb ldr r3, [r7, #12] 800268a: 8d1b ldrh r3, [r3, #40] ; 0x28 800268c: 3b01 subs r3, #1 800268e: b29a uxth r2, r3 8002690: 68fb ldr r3, [r7, #12] 8002692: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002694: 68fb ldr r3, [r7, #12] 8002696: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002698: b29b uxth r3, r3 800269a: 3b01 subs r3, #1 800269c: b29a uxth r2, r3 800269e: 68fb ldr r3, [r7, #12] 80026a0: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 80026a2: b662 cpsie i } 80026a4: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80026a6: 68fb ldr r3, [r7, #12] 80026a8: 681b ldr r3, [r3, #0] 80026aa: 691a ldr r2, [r3, #16] 80026ac: 68fb ldr r3, [r7, #12] 80026ae: 6a5b ldr r3, [r3, #36] ; 0x24 80026b0: b2d2 uxtb r2, r2 80026b2: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80026b4: 68fb ldr r3, [r7, #12] 80026b6: 6a5b ldr r3, [r3, #36] ; 0x24 80026b8: 1c5a adds r2, r3, #1 80026ba: 68fb ldr r3, [r7, #12] 80026bc: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80026be: 68fb ldr r3, [r7, #12] 80026c0: 8d1b ldrh r3, [r3, #40] ; 0x28 80026c2: 3b01 subs r3, #1 80026c4: b29a uxth r2, r3 80026c6: 68fb ldr r3, [r7, #12] 80026c8: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80026ca: 68fb ldr r3, [r7, #12] 80026cc: 8d5b ldrh r3, [r3, #42] ; 0x2a 80026ce: b29b uxth r3, r3 80026d0: 3b01 subs r3, #1 80026d2: b29a uxth r2, r3 80026d4: 68fb ldr r3, [r7, #12] 80026d6: 855a strh r2, [r3, #42] ; 0x2a 80026d8: e042 b.n 8002760 } } else { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80026da: 6a7a ldr r2, [r7, #36] ; 0x24 80026dc: 6bb9 ldr r1, [r7, #56] ; 0x38 80026de: 68f8 ldr r0, [r7, #12] 80026e0: f000 fb32 bl 8002d48 80026e4: 4603 mov r3, r0 80026e6: 2b00 cmp r3, #0 80026e8: d001 beq.n 80026ee { return HAL_ERROR; 80026ea: 2301 movs r3, #1 80026ec: e04c b.n 8002788 } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80026ee: 68fb ldr r3, [r7, #12] 80026f0: 681b ldr r3, [r3, #0] 80026f2: 691a ldr r2, [r3, #16] 80026f4: 68fb ldr r3, [r7, #12] 80026f6: 6a5b ldr r3, [r3, #36] ; 0x24 80026f8: b2d2 uxtb r2, r2 80026fa: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80026fc: 68fb ldr r3, [r7, #12] 80026fe: 6a5b ldr r3, [r3, #36] ; 0x24 8002700: 1c5a adds r2, r3, #1 8002702: 68fb ldr r3, [r7, #12] 8002704: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002706: 68fb ldr r3, [r7, #12] 8002708: 8d1b ldrh r3, [r3, #40] ; 0x28 800270a: 3b01 subs r3, #1 800270c: b29a uxth r2, r3 800270e: 68fb ldr r3, [r7, #12] 8002710: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002712: 68fb ldr r3, [r7, #12] 8002714: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002716: b29b uxth r3, r3 8002718: 3b01 subs r3, #1 800271a: b29a uxth r2, r3 800271c: 68fb ldr r3, [r7, #12] 800271e: 855a strh r2, [r3, #42] ; 0x2a if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 8002720: 68fb ldr r3, [r7, #12] 8002722: 681b ldr r3, [r3, #0] 8002724: 695b ldr r3, [r3, #20] 8002726: f003 0304 and.w r3, r3, #4 800272a: 2b04 cmp r3, #4 800272c: d118 bne.n 8002760 { /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 800272e: 68fb ldr r3, [r7, #12] 8002730: 681b ldr r3, [r3, #0] 8002732: 691a ldr r2, [r3, #16] 8002734: 68fb ldr r3, [r7, #12] 8002736: 6a5b ldr r3, [r3, #36] ; 0x24 8002738: b2d2 uxtb r2, r2 800273a: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800273c: 68fb ldr r3, [r7, #12] 800273e: 6a5b ldr r3, [r3, #36] ; 0x24 8002740: 1c5a adds r2, r3, #1 8002742: 68fb ldr r3, [r7, #12] 8002744: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002746: 68fb ldr r3, [r7, #12] 8002748: 8d1b ldrh r3, [r3, #40] ; 0x28 800274a: 3b01 subs r3, #1 800274c: b29a uxth r2, r3 800274e: 68fb ldr r3, [r7, #12] 8002750: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002752: 68fb ldr r3, [r7, #12] 8002754: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002756: b29b uxth r3, r3 8002758: 3b01 subs r3, #1 800275a: b29a uxth r2, r3 800275c: 68fb ldr r3, [r7, #12] 800275e: 855a strh r2, [r3, #42] ; 0x2a while (hi2c->XferSize > 0U) 8002760: 68fb ldr r3, [r7, #12] 8002762: 8d1b ldrh r3, [r3, #40] ; 0x28 8002764: 2b00 cmp r3, #0 8002766: f47f ae94 bne.w 8002492