: /** * @brief The application entry point. * @retval int */ int main(void) { 8001108: b580 push {r7, lr} 800110a: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800110c: f000 fb8e bl 800182c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001110: f000 f809 bl 8001126 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001114: f000 f87a bl 800120c MX_FSMC_Init(); 8001118: f000 f93a bl 8001390 MX_I2C2_Init(); 800111c: f000 f848 bl 80011b0 /* USER CODE BEGIN 2 */ main_app(); 8001120: f004 f9cc bl 80054bc /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8001124: e7fe b.n 8001124 08001126 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001126: b580 push {r7, lr} 8001128: b090 sub sp, #64 ; 0x40 800112a: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800112c: f107 0318 add.w r3, r7, #24 8001130: 2228 movs r2, #40 ; 0x28 8001132: 2100 movs r1, #0 8001134: 4618 mov r0, r3 8001136: f004 fd2b bl 8005b90 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800113a: 1d3b adds r3, r7, #4 800113c: 2200 movs r2, #0 800113e: 601a str r2, [r3, #0] 8001140: 605a str r2, [r3, #4] 8001142: 609a str r2, [r3, #8] 8001144: 60da str r2, [r3, #12] 8001146: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001148: 2301 movs r3, #1 800114a: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800114c: f44f 3380 mov.w r3, #65536 ; 0x10000 8001150: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8001152: 2300 movs r3, #0 8001154: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001156: 2301 movs r3, #1 8001158: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800115a: 2302 movs r3, #2 800115c: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800115e: f44f 3380 mov.w r3, #65536 ; 0x10000 8001162: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8001164: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8001168: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800116a: f107 0318 add.w r3, r7, #24 800116e: 4618 mov r0, r3 8001170: f001 fe8a bl 8002e88 8001174: 4603 mov r3, r0 8001176: 2b00 cmp r3, #0 8001178: d001 beq.n 800117e { Error_Handler(); 800117a: f000 f96d bl 8001458 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800117e: 230f movs r3, #15 8001180: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8001182: 2302 movs r3, #2 8001184: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001186: 2300 movs r3, #0 8001188: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800118a: f44f 6380 mov.w r3, #1024 ; 0x400 800118e: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001190: 2300 movs r3, #0 8001192: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001194: 1d3b adds r3, r7, #4 8001196: 2102 movs r1, #2 8001198: 4618 mov r0, r3 800119a: f002 f8f5 bl 8003388 800119e: 4603 mov r3, r0 80011a0: 2b00 cmp r3, #0 80011a2: d001 beq.n 80011a8 { Error_Handler(); 80011a4: f000 f958 bl 8001458 } } 80011a8: bf00 nop 80011aa: 3740 adds r7, #64 ; 0x40 80011ac: 46bd mov sp, r7 80011ae: bd80 pop {r7, pc} 080011b0 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 80011b0: b580 push {r7, lr} 80011b2: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 80011b4: 4b12 ldr r3, [pc, #72] ; (8001200 ) 80011b6: 4a13 ldr r2, [pc, #76] ; (8001204 ) 80011b8: 601a str r2, [r3, #0] hi2c2.Init.ClockSpeed = 100000; 80011ba: 4b11 ldr r3, [pc, #68] ; (8001200 ) 80011bc: 4a12 ldr r2, [pc, #72] ; (8001208 ) 80011be: 605a str r2, [r3, #4] hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2; 80011c0: 4b0f ldr r3, [pc, #60] ; (8001200 ) 80011c2: 2200 movs r2, #0 80011c4: 609a str r2, [r3, #8] hi2c2.Init.OwnAddress1 = 0; 80011c6: 4b0e ldr r3, [pc, #56] ; (8001200 ) 80011c8: 2200 movs r2, #0 80011ca: 60da str r2, [r3, #12] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80011cc: 4b0c ldr r3, [pc, #48] ; (8001200 ) 80011ce: f44f 4280 mov.w r2, #16384 ; 0x4000 80011d2: 611a str r2, [r3, #16] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80011d4: 4b0a ldr r3, [pc, #40] ; (8001200 ) 80011d6: 2200 movs r2, #0 80011d8: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2 = 0; 80011da: 4b09 ldr r3, [pc, #36] ; (8001200 ) 80011dc: 2200 movs r2, #0 80011de: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80011e0: 4b07 ldr r3, [pc, #28] ; (8001200 ) 80011e2: 2200 movs r2, #0 80011e4: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80011e6: 4b06 ldr r3, [pc, #24] ; (8001200 ) 80011e8: 2200 movs r2, #0 80011ea: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 80011ec: 4804 ldr r0, [pc, #16] ; (8001200 ) 80011ee: f000 fe4b bl 8001e88 80011f2: 4603 mov r3, r0 80011f4: 2b00 cmp r3, #0 80011f6: d001 beq.n 80011fc { Error_Handler(); 80011f8: f000 f92e bl 8001458 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 80011fc: bf00 nop 80011fe: bd80 pop {r7, pc} 8001200: 20000208 .word 0x20000208 8001204: 40005800 .word 0x40005800 8001208: 000186a0 .word 0x000186a0 0800120c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800120c: b580 push {r7, lr} 800120e: b08a sub sp, #40 ; 0x28 8001210: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001212: f107 0318 add.w r3, r7, #24 8001216: 2200 movs r2, #0 8001218: 601a str r2, [r3, #0] 800121a: 605a str r2, [r3, #4] 800121c: 609a str r2, [r3, #8] 800121e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8001220: 4b58 ldr r3, [pc, #352] ; (8001384 ) 8001222: 699b ldr r3, [r3, #24] 8001224: 4a57 ldr r2, [pc, #348] ; (8001384 ) 8001226: f043 0380 orr.w r3, r3, #128 ; 0x80 800122a: 6193 str r3, [r2, #24] 800122c: 4b55 ldr r3, [pc, #340] ; (8001384 ) 800122e: 699b ldr r3, [r3, #24] 8001230: f003 0380 and.w r3, r3, #128 ; 0x80 8001234: 617b str r3, [r7, #20] 8001236: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001238: 4b52 ldr r3, [pc, #328] ; (8001384 ) 800123a: 699b ldr r3, [r3, #24] 800123c: 4a51 ldr r2, [pc, #324] ; (8001384 ) 800123e: f043 0308 orr.w r3, r3, #8 8001242: 6193 str r3, [r2, #24] 8001244: 4b4f ldr r3, [pc, #316] ; (8001384 ) 8001246: 699b ldr r3, [r3, #24] 8001248: f003 0308 and.w r3, r3, #8 800124c: 613b str r3, [r7, #16] 800124e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 8001250: 4b4c ldr r3, [pc, #304] ; (8001384 ) 8001252: 699b ldr r3, [r3, #24] 8001254: 4a4b ldr r2, [pc, #300] ; (8001384 ) 8001256: f443 7380 orr.w r3, r3, #256 ; 0x100 800125a: 6193 str r3, [r2, #24] 800125c: 4b49 ldr r3, [pc, #292] ; (8001384 ) 800125e: 699b ldr r3, [r3, #24] 8001260: f403 7380 and.w r3, r3, #256 ; 0x100 8001264: 60fb str r3, [r7, #12] 8001266: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001268: 4b46 ldr r3, [pc, #280] ; (8001384 ) 800126a: 699b ldr r3, [r3, #24] 800126c: 4a45 ldr r2, [pc, #276] ; (8001384 ) 800126e: f043 0340 orr.w r3, r3, #64 ; 0x40 8001272: 6193 str r3, [r2, #24] 8001274: 4b43 ldr r3, [pc, #268] ; (8001384 ) 8001276: 699b ldr r3, [r3, #24] 8001278: f003 0340 and.w r3, r3, #64 ; 0x40 800127c: 60bb str r3, [r7, #8] 800127e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001280: 4b40 ldr r3, [pc, #256] ; (8001384 ) 8001282: 699b ldr r3, [r3, #24] 8001284: 4a3f ldr r2, [pc, #252] ; (8001384 ) 8001286: f043 0320 orr.w r3, r3, #32 800128a: 6193 str r3, [r2, #24] 800128c: 4b3d ldr r3, [pc, #244] ; (8001384 ) 800128e: 699b ldr r3, [r3, #24] 8001290: f003 0320 and.w r3, r3, #32 8001294: 607b str r3, [r7, #4] 8001296: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TDIN_GPIO_Port, TDIN_Pin, GPIO_PIN_SET); 8001298: 2201 movs r2, #1 800129a: f44f 7100 mov.w r1, #512 ; 0x200 800129e: 483a ldr r0, [pc, #232] ; (8001388 ) 80012a0: f000 fdd9 bl 8001e56 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LCD_BL_GPIO_Port, LCD_BL_Pin, GPIO_PIN_RESET); 80012a4: 2200 movs r2, #0 80012a6: 2101 movs r1, #1 80012a8: 4838 ldr r0, [pc, #224] ; (800138c ) 80012aa: f000 fdd4 bl 8001e56 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, TCLK_Pin|TCS_Pin|MAX_IRD_Pin|MAX_RD_Pin, GPIO_PIN_SET); 80012ae: 2201 movs r2, #1 80012b0: f245 0106 movw r1, #20486 ; 0x5006 80012b4: 4835 ldr r0, [pc, #212] ; (800138c ) 80012b6: f000 fdce bl 8001e56 /*Configure GPIO pin : TDOUT_Pin */ GPIO_InitStruct.Pin = TDOUT_Pin; 80012ba: f44f 7380 mov.w r3, #256 ; 0x100 80012be: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80012c0: 2300 movs r3, #0 80012c2: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012c4: 2300 movs r3, #0 80012c6: 623b str r3, [r7, #32] HAL_GPIO_Init(TDOUT_GPIO_Port, &GPIO_InitStruct); 80012c8: f107 0318 add.w r3, r7, #24 80012cc: 4619 mov r1, r3 80012ce: 482e ldr r0, [pc, #184] ; (8001388 ) 80012d0: f000 fc16 bl 8001b00 /*Configure GPIO pin : TDIN_Pin */ GPIO_InitStruct.Pin = TDIN_Pin; 80012d4: f44f 7300 mov.w r3, #512 ; 0x200 80012d8: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80012da: 2301 movs r3, #1 80012dc: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012de: 2300 movs r3, #0 80012e0: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80012e2: 2303 movs r3, #3 80012e4: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(TDIN_GPIO_Port, &GPIO_InitStruct); 80012e6: f107 0318 add.w r3, r7, #24 80012ea: 4619 mov r1, r3 80012ec: 4826 ldr r0, [pc, #152] ; (8001388 ) 80012ee: f000 fc07 bl 8001b00 /*Configure GPIO pin : TPEN_Pin */ GPIO_InitStruct.Pin = TPEN_Pin; 80012f2: f44f 6380 mov.w r3, #1024 ; 0x400 80012f6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80012f8: 2300 movs r3, #0 80012fa: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 80012fc: 2301 movs r3, #1 80012fe: 623b str r3, [r7, #32] HAL_GPIO_Init(TPEN_GPIO_Port, &GPIO_InitStruct); 8001300: f107 0318 add.w r3, r7, #24 8001304: 4619 mov r1, r3 8001306: 4820 ldr r0, [pc, #128] ; (8001388 ) 8001308: f000 fbfa bl 8001b00 /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 800130c: 2301 movs r3, #1 800130e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001310: 2301 movs r3, #1 8001312: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001314: 2300 movs r3, #0 8001316: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001318: 2302 movs r3, #2 800131a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 800131c: f107 0318 add.w r3, r7, #24 8001320: 4619 mov r1, r3 8001322: 481a ldr r0, [pc, #104] ; (800138c ) 8001324: f000 fbec bl 8001b00 /*Configure GPIO pins : TCLK_Pin TCS_Pin */ GPIO_InitStruct.Pin = TCLK_Pin|TCS_Pin; 8001328: 2306 movs r3, #6 800132a: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800132c: 2301 movs r3, #1 800132e: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001330: 2300 movs r3, #0 8001332: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001334: 2303 movs r3, #3 8001336: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001338: f107 0318 add.w r3, r7, #24 800133c: 4619 mov r1, r3 800133e: 4813 ldr r0, [pc, #76] ; (800138c ) 8001340: f000 fbde bl 8001b00 /*Configure GPIO pins : MAX_IRD_Pin MAX_RD_Pin */ GPIO_InitStruct.Pin = MAX_IRD_Pin|MAX_RD_Pin; 8001344: f44f 43a0 mov.w r3, #20480 ; 0x5000 8001348: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800134a: 2301 movs r3, #1 800134c: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 800134e: 2301 movs r3, #1 8001350: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001352: 2303 movs r3, #3 8001354: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001356: f107 0318 add.w r3, r7, #24 800135a: 4619 mov r1, r3 800135c: 480b ldr r0, [pc, #44] ; (800138c ) 800135e: f000 fbcf bl 8001b00 /*Configure GPIO pin : MAX_INT_Pin */ GPIO_InitStruct.Pin = MAX_INT_Pin; 8001362: f44f 5300 mov.w r3, #8192 ; 0x2000 8001366: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001368: 2300 movs r3, #0 800136a: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800136c: 2300 movs r3, #0 800136e: 623b str r3, [r7, #32] HAL_GPIO_Init(MAX_INT_GPIO_Port, &GPIO_InitStruct); 8001370: f107 0318 add.w r3, r7, #24 8001374: 4619 mov r1, r3 8001376: 4805 ldr r0, [pc, #20] ; (800138c ) 8001378: f000 fbc2 bl 8001b00 } 800137c: bf00 nop 800137e: 3728 adds r7, #40 ; 0x28 8001380: 46bd mov sp, r7 8001382: bd80 pop {r7, pc} 8001384: 40021000 .word 0x40021000 8001388: 40011c00 .word 0x40011c00 800138c: 40010c00 .word 0x40010c00 08001390 : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 8001390: b580 push {r7, lr} 8001392: b088 sub sp, #32 8001394: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 8001396: 1d3b adds r3, r7, #4 8001398: 2200 movs r2, #0 800139a: 601a str r2, [r3, #0] 800139c: 605a str r2, [r3, #4] 800139e: 609a str r2, [r3, #8] 80013a0: 60da str r2, [r3, #12] 80013a2: 611a str r2, [r3, #16] 80013a4: 615a str r2, [r3, #20] 80013a6: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 80013a8: 4b28 ldr r3, [pc, #160] ; (800144c ) 80013aa: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 80013ae: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 80013b0: 4b26 ldr r3, [pc, #152] ; (800144c ) 80013b2: 4a27 ldr r2, [pc, #156] ; (8001450 ) 80013b4: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 80013b6: 4b25 ldr r3, [pc, #148] ; (800144c ) 80013b8: 2206 movs r2, #6 80013ba: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 80013bc: 4b23 ldr r3, [pc, #140] ; (800144c ) 80013be: 2200 movs r2, #0 80013c0: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 80013c2: 4b22 ldr r3, [pc, #136] ; (800144c ) 80013c4: 2200 movs r2, #0 80013c6: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 80013c8: 4b20 ldr r3, [pc, #128] ; (800144c ) 80013ca: 2210 movs r2, #16 80013cc: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 80013ce: 4b1f ldr r3, [pc, #124] ; (800144c ) 80013d0: 2200 movs r2, #0 80013d2: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 80013d4: 4b1d ldr r3, [pc, #116] ; (800144c ) 80013d6: 2200 movs r2, #0 80013d8: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 80013da: 4b1c ldr r3, [pc, #112] ; (800144c ) 80013dc: 2200 movs r2, #0 80013de: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 80013e0: 4b1a ldr r3, [pc, #104] ; (800144c ) 80013e2: 2200 movs r2, #0 80013e4: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 80013e6: 4b19 ldr r3, [pc, #100] ; (800144c ) 80013e8: f44f 5280 mov.w r2, #4096 ; 0x1000 80013ec: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 80013ee: 4b17 ldr r3, [pc, #92] ; (800144c ) 80013f0: 2200 movs r2, #0 80013f2: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 80013f4: 4b15 ldr r3, [pc, #84] ; (800144c ) 80013f6: 2200 movs r2, #0 80013f8: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 80013fa: 4b14 ldr r3, [pc, #80] ; (800144c ) 80013fc: 2200 movs r2, #0 80013fe: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 8001400: 4b12 ldr r3, [pc, #72] ; (800144c ) 8001402: 2200 movs r2, #0 8001404: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 8001406: 2300 movs r3, #0 8001408: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 800140a: 230f movs r3, #15 800140c: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 800140e: 2301 movs r3, #1 8001410: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 0; 8001412: 2300 movs r3, #0 8001414: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 8001416: 2310 movs r3, #16 8001418: 617b str r3, [r7, #20] Timing.DataLatency = 17; 800141a: 2311 movs r3, #17 800141c: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 800141e: 2300 movs r3, #0 8001420: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 8001422: 1d3b adds r3, r7, #4 8001424: 2200 movs r2, #0 8001426: 4619 mov r1, r3 8001428: 4808 ldr r0, [pc, #32] ; (800144c ) 800142a: f002 f933 bl 8003694 800142e: 4603 mov r3, r0 8001430: 2b00 cmp r3, #0 8001432: d001 beq.n 8001438 { Error_Handler( ); 8001434: f000 f810 bl 8001458 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 8001438: 4b06 ldr r3, [pc, #24] ; (8001454 ) 800143a: 69db ldr r3, [r3, #28] 800143c: 4a05 ldr r2, [pc, #20] ; (8001454 ) 800143e: f443 6380 orr.w r3, r3, #1024 ; 0x400 8001442: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 8001444: bf00 nop 8001446: 3720 adds r7, #32 8001448: 46bd mov sp, r7 800144a: bd80 pop {r7, pc} 800144c: 2000025c .word 0x2000025c 8001450: a0000104 .word 0xa0000104 8001454: 40010000 .word 0x40010000 08001458 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001458: b480 push {r7} 800145a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800145c: b672 cpsid i } 800145e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001460: e7fe b.n 8001460 ... 08001464 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001464: b480 push {r7} 8001466: b085 sub sp, #20 8001468: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800146a: 4b15 ldr r3, [pc, #84] ; (80014c0 ) 800146c: 699b ldr r3, [r3, #24] 800146e: 4a14 ldr r2, [pc, #80] ; (80014c0 ) 8001470: f043 0301 orr.w r3, r3, #1 8001474: 6193 str r3, [r2, #24] 8001476: 4b12 ldr r3, [pc, #72] ; (80014c0 ) 8001478: 699b ldr r3, [r3, #24] 800147a: f003 0301 and.w r3, r3, #1 800147e: 60bb str r3, [r7, #8] 8001480: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8001482: 4b0f ldr r3, [pc, #60] ; (80014c0 ) 8001484: 69db ldr r3, [r3, #28] 8001486: 4a0e ldr r2, [pc, #56] ; (80014c0 ) 8001488: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800148c: 61d3 str r3, [r2, #28] 800148e: 4b0c ldr r3, [pc, #48] ; (80014c0 ) 8001490: 69db ldr r3, [r3, #28] 8001492: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001496: 607b str r3, [r7, #4] 8001498: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 800149a: 4b0a ldr r3, [pc, #40] ; (80014c4 ) 800149c: 685b ldr r3, [r3, #4] 800149e: 60fb str r3, [r7, #12] 80014a0: 68fb ldr r3, [r7, #12] 80014a2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80014a6: 60fb str r3, [r7, #12] 80014a8: 68fb ldr r3, [r7, #12] 80014aa: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 80014ae: 60fb str r3, [r7, #12] 80014b0: 4a04 ldr r2, [pc, #16] ; (80014c4 ) 80014b2: 68fb ldr r3, [r7, #12] 80014b4: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80014b6: bf00 nop 80014b8: 3714 adds r7, #20 80014ba: 46bd mov sp, r7 80014bc: bc80 pop {r7} 80014be: 4770 bx lr 80014c0: 40021000 .word 0x40021000 80014c4: 40010000 .word 0x40010000 080014c8 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 80014c8: b580 push {r7, lr} 80014ca: b088 sub sp, #32 80014cc: af00 add r7, sp, #0 80014ce: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80014d0: f107 0310 add.w r3, r7, #16 80014d4: 2200 movs r2, #0 80014d6: 601a str r2, [r3, #0] 80014d8: 605a str r2, [r3, #4] 80014da: 609a str r2, [r3, #8] 80014dc: 60da str r2, [r3, #12] if(hi2c->Instance==I2C2) 80014de: 687b ldr r3, [r7, #4] 80014e0: 681b ldr r3, [r3, #0] 80014e2: 4a16 ldr r2, [pc, #88] ; (800153c ) 80014e4: 4293 cmp r3, r2 80014e6: d124 bne.n 8001532 { /* USER CODE BEGIN I2C2_MspInit 0 */ /* USER CODE END I2C2_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80014e8: 4b15 ldr r3, [pc, #84] ; (8001540 ) 80014ea: 699b ldr r3, [r3, #24] 80014ec: 4a14 ldr r2, [pc, #80] ; (8001540 ) 80014ee: f043 0308 orr.w r3, r3, #8 80014f2: 6193 str r3, [r2, #24] 80014f4: 4b12 ldr r3, [pc, #72] ; (8001540 ) 80014f6: 699b ldr r3, [r3, #24] 80014f8: f003 0308 and.w r3, r3, #8 80014fc: 60fb str r3, [r7, #12] 80014fe: 68fb ldr r3, [r7, #12] /**I2C2 GPIO Configuration PB10 ------> I2C2_SCL PB11 ------> I2C2_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8001500: f44f 6340 mov.w r3, #3072 ; 0xc00 8001504: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001506: 2312 movs r3, #18 8001508: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800150a: 2303 movs r3, #3 800150c: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800150e: f107 0310 add.w r3, r7, #16 8001512: 4619 mov r1, r3 8001514: 480b ldr r0, [pc, #44] ; (8001544 ) 8001516: f000 faf3 bl 8001b00 /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); 800151a: 4b09 ldr r3, [pc, #36] ; (8001540 ) 800151c: 69db ldr r3, [r3, #28] 800151e: 4a08 ldr r2, [pc, #32] ; (8001540 ) 8001520: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8001524: 61d3 str r3, [r2, #28] 8001526: 4b06 ldr r3, [pc, #24] ; (8001540 ) 8001528: 69db ldr r3, [r3, #28] 800152a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800152e: 60bb str r3, [r7, #8] 8001530: 68bb ldr r3, [r7, #8] /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ } } 8001532: bf00 nop 8001534: 3720 adds r7, #32 8001536: 46bd mov sp, r7 8001538: bd80 pop {r7, pc} 800153a: bf00 nop 800153c: 40005800 .word 0x40005800 8001540: 40021000 .word 0x40021000 8001544: 40010c00 .word 0x40010c00 08001548 : } static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 8001548: b580 push {r7, lr} 800154a: b086 sub sp, #24 800154c: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 800154e: f107 0308 add.w r3, r7, #8 8001552: 2200 movs r2, #0 8001554: 601a str r2, [r3, #0] 8001556: 605a str r2, [r3, #4] 8001558: 609a str r2, [r3, #8] 800155a: 60da str r2, [r3, #12] if (FSMC_Initialized) { 800155c: 4b1f ldr r3, [pc, #124] ; (80015dc ) 800155e: 681b ldr r3, [r3, #0] 8001560: 2b00 cmp r3, #0 8001562: d136 bne.n 80015d2 return; } FSMC_Initialized = 1; 8001564: 4b1d ldr r3, [pc, #116] ; (80015dc ) 8001566: 2201 movs r2, #1 8001568: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 800156a: 4b1d ldr r3, [pc, #116] ; (80015e0 ) 800156c: 695b ldr r3, [r3, #20] 800156e: 4a1c ldr r2, [pc, #112] ; (80015e0 ) 8001570: f443 7380 orr.w r3, r3, #256 ; 0x100 8001574: 6153 str r3, [r2, #20] 8001576: 4b1a ldr r3, [pc, #104] ; (80015e0 ) 8001578: 695b ldr r3, [r3, #20] 800157a: f403 7380 and.w r3, r3, #256 ; 0x100 800157e: 607b str r3, [r7, #4] 8001580: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 8001582: f241 0301 movw r3, #4097 ; 0x1001 8001586: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001588: 2302 movs r3, #2 800158a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800158c: 2303 movs r3, #3 800158e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8001590: f107 0308 add.w r3, r7, #8 8001594: 4619 mov r1, r3 8001596: 4813 ldr r0, [pc, #76] ; (80015e4 ) 8001598: f000 fab2 bl 8001b00 GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800159c: f64f 7380 movw r3, #65408 ; 0xff80 80015a0: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80015a2: 2302 movs r3, #2 80015a4: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80015a6: 2303 movs r3, #3 80015a8: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80015aa: f107 0308 add.w r3, r7, #8 80015ae: 4619 mov r1, r3 80015b0: 480d ldr r0, [pc, #52] ; (80015e8 ) 80015b2: f000 faa5 bl 8001b00 GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 80015b6: f24c 7333 movw r3, #50995 ; 0xc733 80015ba: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80015bc: 2302 movs r3, #2 80015be: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80015c0: 2303 movs r3, #3 80015c2: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80015c4: f107 0308 add.w r3, r7, #8 80015c8: 4619 mov r1, r3 80015ca: 4808 ldr r0, [pc, #32] ; (80015ec ) 80015cc: f000 fa98 bl 8001b00 80015d0: e000 b.n 80015d4 return; 80015d2: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 80015d4: 3718 adds r7, #24 80015d6: 46bd mov sp, r7 80015d8: bd80 pop {r7, pc} 80015da: bf00 nop 80015dc: 200001f8 .word 0x200001f8 80015e0: 40021000 .word 0x40021000 80015e4: 40012000 .word 0x40012000 80015e8: 40011800 .word 0x40011800 80015ec: 40011400 .word 0x40011400 080015f0 : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 80015f0: b580 push {r7, lr} 80015f2: b082 sub sp, #8 80015f4: af00 add r7, sp, #0 80015f6: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 80015f8: f7ff ffa6 bl 8001548 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 80015fc: bf00 nop 80015fe: 3708 adds r7, #8 8001600: 46bd mov sp, r7 8001602: bd80 pop {r7, pc} 08001604 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001604: b480 push {r7} 8001606: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001608: e7fe b.n 8001608 0800160a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800160a: b480 push {r7} 800160c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800160e: e7fe b.n 800160e 08001610 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001610: b480 push {r7} 8001612: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001614: e7fe b.n 8001614 08001616 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8001616: b480 push {r7} 8001618: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800161a: e7fe b.n 800161a 0800161c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800161c: b480 push {r7} 800161e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001620: e7fe b.n 8001620 08001622 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001622: b480 push {r7} 8001624: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001626: bf00 nop 8001628: 46bd mov sp, r7 800162a: bc80 pop {r7} 800162c: 4770 bx lr 0800162e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800162e: b480 push {r7} 8001630: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001632: bf00 nop 8001634: 46bd mov sp, r7 8001636: bc80 pop {r7} 8001638: 4770 bx lr 0800163a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800163a: b480 push {r7} 800163c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800163e: bf00 nop 8001640: 46bd mov sp, r7 8001642: bc80 pop {r7} 8001644: 4770 bx lr 08001646 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001646: b580 push {r7, lr} 8001648: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800164a: f000 f935 bl 80018b8 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800164e: bf00 nop 8001650: bd80 pop {r7, pc} 08001652 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 8001652: b480 push {r7} 8001654: af00 add r7, sp, #0 return 1; 8001656: 2301 movs r3, #1 } 8001658: 4618 mov r0, r3 800165a: 46bd mov sp, r7 800165c: bc80 pop {r7} 800165e: 4770 bx lr 08001660 <_kill>: int _kill(int pid, int sig) { 8001660: b580 push {r7, lr} 8001662: b082 sub sp, #8 8001664: af00 add r7, sp, #0 8001666: 6078 str r0, [r7, #4] 8001668: 6039 str r1, [r7, #0] errno = EINVAL; 800166a: f004 fa57 bl 8005b1c <__errno> 800166e: 4603 mov r3, r0 8001670: 2216 movs r2, #22 8001672: 601a str r2, [r3, #0] return -1; 8001674: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001678: 4618 mov r0, r3 800167a: 3708 adds r7, #8 800167c: 46bd mov sp, r7 800167e: bd80 pop {r7, pc} 08001680 <_exit>: void _exit (int status) { 8001680: b580 push {r7, lr} 8001682: b082 sub sp, #8 8001684: af00 add r7, sp, #0 8001686: 6078 str r0, [r7, #4] _kill(status, -1); 8001688: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 800168c: 6878 ldr r0, [r7, #4] 800168e: f7ff ffe7 bl 8001660 <_kill> while (1) {} /* Make sure we hang here */ 8001692: e7fe b.n 8001692 <_exit+0x12> 08001694 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001694: b580 push {r7, lr} 8001696: b086 sub sp, #24 8001698: af00 add r7, sp, #0 800169a: 60f8 str r0, [r7, #12] 800169c: 60b9 str r1, [r7, #8] 800169e: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80016a0: 2300 movs r3, #0 80016a2: 617b str r3, [r7, #20] 80016a4: e00a b.n 80016bc <_read+0x28> { *ptr++ = __io_getchar(); 80016a6: f3af 8000 nop.w 80016aa: 4601 mov r1, r0 80016ac: 68bb ldr r3, [r7, #8] 80016ae: 1c5a adds r2, r3, #1 80016b0: 60ba str r2, [r7, #8] 80016b2: b2ca uxtb r2, r1 80016b4: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80016b6: 697b ldr r3, [r7, #20] 80016b8: 3301 adds r3, #1 80016ba: 617b str r3, [r7, #20] 80016bc: 697a ldr r2, [r7, #20] 80016be: 687b ldr r3, [r7, #4] 80016c0: 429a cmp r2, r3 80016c2: dbf0 blt.n 80016a6 <_read+0x12> } return len; 80016c4: 687b ldr r3, [r7, #4] } 80016c6: 4618 mov r0, r3 80016c8: 3718 adds r7, #24 80016ca: 46bd mov sp, r7 80016cc: bd80 pop {r7, pc} 080016ce <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 80016ce: b580 push {r7, lr} 80016d0: b086 sub sp, #24 80016d2: af00 add r7, sp, #0 80016d4: 60f8 str r0, [r7, #12] 80016d6: 60b9 str r1, [r7, #8] 80016d8: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80016da: 2300 movs r3, #0 80016dc: 617b str r3, [r7, #20] 80016de: e009 b.n 80016f4 <_write+0x26> { __io_putchar(*ptr++); 80016e0: 68bb ldr r3, [r7, #8] 80016e2: 1c5a adds r2, r3, #1 80016e4: 60ba str r2, [r7, #8] 80016e6: 781b ldrb r3, [r3, #0] 80016e8: 4618 mov r0, r3 80016ea: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 80016ee: 697b ldr r3, [r7, #20] 80016f0: 3301 adds r3, #1 80016f2: 617b str r3, [r7, #20] 80016f4: 697a ldr r2, [r7, #20] 80016f6: 687b ldr r3, [r7, #4] 80016f8: 429a cmp r2, r3 80016fa: dbf1 blt.n 80016e0 <_write+0x12> } return len; 80016fc: 687b ldr r3, [r7, #4] } 80016fe: 4618 mov r0, r3 8001700: 3718 adds r7, #24 8001702: 46bd mov sp, r7 8001704: bd80 pop {r7, pc} 08001706 <_close>: int _close(int file) { 8001706: b480 push {r7} 8001708: b083 sub sp, #12 800170a: af00 add r7, sp, #0 800170c: 6078 str r0, [r7, #4] return -1; 800170e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8001712: 4618 mov r0, r3 8001714: 370c adds r7, #12 8001716: 46bd mov sp, r7 8001718: bc80 pop {r7} 800171a: 4770 bx lr 0800171c <_fstat>: int _fstat(int file, struct stat *st) { 800171c: b480 push {r7} 800171e: b083 sub sp, #12 8001720: af00 add r7, sp, #0 8001722: 6078 str r0, [r7, #4] 8001724: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8001726: 683b ldr r3, [r7, #0] 8001728: f44f 5200 mov.w r2, #8192 ; 0x2000 800172c: 605a str r2, [r3, #4] return 0; 800172e: 2300 movs r3, #0 } 8001730: 4618 mov r0, r3 8001732: 370c adds r7, #12 8001734: 46bd mov sp, r7 8001736: bc80 pop {r7} 8001738: 4770 bx lr 0800173a <_isatty>: int _isatty(int file) { 800173a: b480 push {r7} 800173c: b083 sub sp, #12 800173e: af00 add r7, sp, #0 8001740: 6078 str r0, [r7, #4] return 1; 8001742: 2301 movs r3, #1 } 8001744: 4618 mov r0, r3 8001746: 370c adds r7, #12 8001748: 46bd mov sp, r7 800174a: bc80 pop {r7} 800174c: 4770 bx lr 0800174e <_lseek>: int _lseek(int file, int ptr, int dir) { 800174e: b480 push {r7} 8001750: b085 sub sp, #20 8001752: af00 add r7, sp, #0 8001754: 60f8 str r0, [r7, #12] 8001756: 60b9 str r1, [r7, #8] 8001758: 607a str r2, [r7, #4] return 0; 800175a: 2300 movs r3, #0 } 800175c: 4618 mov r0, r3 800175e: 3714 adds r7, #20 8001760: 46bd mov sp, r7 8001762: bc80 pop {r7} 8001764: 4770 bx lr ... 08001768 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001768: b580 push {r7, lr} 800176a: b086 sub sp, #24 800176c: af00 add r7, sp, #0 800176e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8001770: 4a14 ldr r2, [pc, #80] ; (80017c4 <_sbrk+0x5c>) 8001772: 4b15 ldr r3, [pc, #84] ; (80017c8 <_sbrk+0x60>) 8001774: 1ad3 subs r3, r2, r3 8001776: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001778: 697b ldr r3, [r7, #20] 800177a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800177c: 4b13 ldr r3, [pc, #76] ; (80017cc <_sbrk+0x64>) 800177e: 681b ldr r3, [r3, #0] 8001780: 2b00 cmp r3, #0 8001782: d102 bne.n 800178a <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001784: 4b11 ldr r3, [pc, #68] ; (80017cc <_sbrk+0x64>) 8001786: 4a12 ldr r2, [pc, #72] ; (80017d0 <_sbrk+0x68>) 8001788: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800178a: 4b10 ldr r3, [pc, #64] ; (80017cc <_sbrk+0x64>) 800178c: 681a ldr r2, [r3, #0] 800178e: 687b ldr r3, [r7, #4] 8001790: 4413 add r3, r2 8001792: 693a ldr r2, [r7, #16] 8001794: 429a cmp r2, r3 8001796: d207 bcs.n 80017a8 <_sbrk+0x40> { errno = ENOMEM; 8001798: f004 f9c0 bl 8005b1c <__errno> 800179c: 4603 mov r3, r0 800179e: 220c movs r2, #12 80017a0: 601a str r2, [r3, #0] return (void *)-1; 80017a2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 80017a6: e009 b.n 80017bc <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80017a8: 4b08 ldr r3, [pc, #32] ; (80017cc <_sbrk+0x64>) 80017aa: 681b ldr r3, [r3, #0] 80017ac: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80017ae: 4b07 ldr r3, [pc, #28] ; (80017cc <_sbrk+0x64>) 80017b0: 681a ldr r2, [r3, #0] 80017b2: 687b ldr r3, [r7, #4] 80017b4: 4413 add r3, r2 80017b6: 4a05 ldr r2, [pc, #20] ; (80017cc <_sbrk+0x64>) 80017b8: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80017ba: 68fb ldr r3, [r7, #12] } 80017bc: 4618 mov r0, r3 80017be: 3718 adds r7, #24 80017c0: 46bd mov sp, r7 80017c2: bd80 pop {r7, pc} 80017c4: 20010000 .word 0x20010000 80017c8: 00000800 .word 0x00000800 80017cc: 200001fc .word 0x200001fc 80017d0: 20000350 .word 0x20000350 080017d4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80017d4: b480 push {r7} 80017d6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80017d8: bf00 nop 80017da: 46bd mov sp, r7 80017dc: bc80 pop {r7} 80017de: 4770 bx lr 080017e0 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80017e0: 480c ldr r0, [pc, #48] ; (8001814 ) ldr r1, =_edata 80017e2: 490d ldr r1, [pc, #52] ; (8001818 ) ldr r2, =_sidata 80017e4: 4a0d ldr r2, [pc, #52] ; (800181c ) movs r3, #0 80017e6: 2300 movs r3, #0 b LoopCopyDataInit 80017e8: e002 b.n 80017f0 080017ea : CopyDataInit: ldr r4, [r2, r3] 80017ea: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80017ec: 50c4 str r4, [r0, r3] adds r3, r3, #4 80017ee: 3304 adds r3, #4 080017f0 : LoopCopyDataInit: adds r4, r0, r3 80017f0: 18c4 adds r4, r0, r3 cmp r4, r1 80017f2: 428c cmp r4, r1 bcc CopyDataInit 80017f4: d3f9 bcc.n 80017ea /* Zero fill the bss segment. */ ldr r2, =_sbss 80017f6: 4a0a ldr r2, [pc, #40] ; (8001820 ) ldr r4, =_ebss 80017f8: 4c0a ldr r4, [pc, #40] ; (8001824 ) movs r3, #0 80017fa: 2300 movs r3, #0 b LoopFillZerobss 80017fc: e001 b.n 8001802 080017fe : FillZerobss: str r3, [r2] 80017fe: 6013 str r3, [r2, #0] adds r2, r2, #4 8001800: 3204 adds r2, #4 08001802 : LoopFillZerobss: cmp r2, r4 8001802: 42a2 cmp r2, r4 bcc FillZerobss 8001804: d3fb bcc.n 80017fe /* Call the clock system intitialization function.*/ bl SystemInit 8001806: f7ff ffe5 bl 80017d4 /* Call static constructors */ bl __libc_init_array 800180a: f004 f98d bl 8005b28 <__libc_init_array> /* Call the application's entry point.*/ bl main 800180e: f7ff fc7b bl 8001108

bx lr 8001812: 4770 bx lr ldr r0, =_sdata 8001814: 20000000 .word 0x20000000 ldr r1, =_edata 8001818: 200001dc .word 0x200001dc ldr r2, =_sidata 800181c: 08009834 .word 0x08009834 ldr r2, =_sbss 8001820: 200001dc .word 0x200001dc ldr r4, =_ebss 8001824: 2000034c .word 0x2000034c 08001828 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001828: e7fe b.n 8001828 ... 0800182c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800182c: b580 push {r7, lr} 800182e: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001830: 4b08 ldr r3, [pc, #32] ; (8001854 ) 8001832: 681b ldr r3, [r3, #0] 8001834: 4a07 ldr r2, [pc, #28] ; (8001854 ) 8001836: f043 0310 orr.w r3, r3, #16 800183a: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800183c: 2003 movs r0, #3 800183e: f000 f92b bl 8001a98 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001842: 200f movs r0, #15 8001844: f000 f808 bl 8001858 /* Init the low level hardware */ HAL_MspInit(); 8001848: f7ff fe0c bl 8001464 /* Return function status */ return HAL_OK; 800184c: 2300 movs r3, #0 } 800184e: 4618 mov r0, r3 8001850: bd80 pop {r7, pc} 8001852: bf00 nop 8001854: 40022000 .word 0x40022000 08001858 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001858: b580 push {r7, lr} 800185a: b082 sub sp, #8 800185c: af00 add r7, sp, #0 800185e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001860: 4b12 ldr r3, [pc, #72] ; (80018ac ) 8001862: 681a ldr r2, [r3, #0] 8001864: 4b12 ldr r3, [pc, #72] ; (80018b0 ) 8001866: 781b ldrb r3, [r3, #0] 8001868: 4619 mov r1, r3 800186a: f44f 737a mov.w r3, #1000 ; 0x3e8 800186e: fbb3 f3f1 udiv r3, r3, r1 8001872: fbb2 f3f3 udiv r3, r2, r3 8001876: 4618 mov r0, r3 8001878: f000 f935 bl 8001ae6 800187c: 4603 mov r3, r0 800187e: 2b00 cmp r3, #0 8001880: d001 beq.n 8001886 { return HAL_ERROR; 8001882: 2301 movs r3, #1 8001884: e00e b.n 80018a4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001886: 687b ldr r3, [r7, #4] 8001888: 2b0f cmp r3, #15 800188a: d80a bhi.n 80018a2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800188c: 2200 movs r2, #0 800188e: 6879 ldr r1, [r7, #4] 8001890: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001894: f000 f90b bl 8001aae uwTickPrio = TickPriority; 8001898: 4a06 ldr r2, [pc, #24] ; (80018b4 ) 800189a: 687b ldr r3, [r7, #4] 800189c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800189e: 2300 movs r3, #0 80018a0: e000 b.n 80018a4 return HAL_ERROR; 80018a2: 2301 movs r3, #1 } 80018a4: 4618 mov r0, r3 80018a6: 3708 adds r7, #8 80018a8: 46bd mov sp, r7 80018aa: bd80 pop {r7, pc} 80018ac: 20000000 .word 0x20000000 80018b0: 20000008 .word 0x20000008 80018b4: 20000004 .word 0x20000004 080018b8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80018b8: b480 push {r7} 80018ba: af00 add r7, sp, #0 uwTick += uwTickFreq; 80018bc: 4b05 ldr r3, [pc, #20] ; (80018d4 ) 80018be: 781b ldrb r3, [r3, #0] 80018c0: 461a mov r2, r3 80018c2: 4b05 ldr r3, [pc, #20] ; (80018d8 ) 80018c4: 681b ldr r3, [r3, #0] 80018c6: 4413 add r3, r2 80018c8: 4a03 ldr r2, [pc, #12] ; (80018d8 ) 80018ca: 6013 str r3, [r2, #0] } 80018cc: bf00 nop 80018ce: 46bd mov sp, r7 80018d0: bc80 pop {r7} 80018d2: 4770 bx lr 80018d4: 20000008 .word 0x20000008 80018d8: 200002a4 .word 0x200002a4 080018dc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80018dc: b480 push {r7} 80018de: af00 add r7, sp, #0 return uwTick; 80018e0: 4b02 ldr r3, [pc, #8] ; (80018ec ) 80018e2: 681b ldr r3, [r3, #0] } 80018e4: 4618 mov r0, r3 80018e6: 46bd mov sp, r7 80018e8: bc80 pop {r7} 80018ea: 4770 bx lr 80018ec: 200002a4 .word 0x200002a4 080018f0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80018f0: b580 push {r7, lr} 80018f2: b084 sub sp, #16 80018f4: af00 add r7, sp, #0 80018f6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80018f8: f7ff fff0 bl 80018dc 80018fc: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80018fe: 687b ldr r3, [r7, #4] 8001900: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001902: 68fb ldr r3, [r7, #12] 8001904: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8001908: d005 beq.n 8001916 { wait += (uint32_t)(uwTickFreq); 800190a: 4b0a ldr r3, [pc, #40] ; (8001934 ) 800190c: 781b ldrb r3, [r3, #0] 800190e: 461a mov r2, r3 8001910: 68fb ldr r3, [r7, #12] 8001912: 4413 add r3, r2 8001914: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001916: bf00 nop 8001918: f7ff ffe0 bl 80018dc 800191c: 4602 mov r2, r0 800191e: 68bb ldr r3, [r7, #8] 8001920: 1ad3 subs r3, r2, r3 8001922: 68fa ldr r2, [r7, #12] 8001924: 429a cmp r2, r3 8001926: d8f7 bhi.n 8001918 { } } 8001928: bf00 nop 800192a: bf00 nop 800192c: 3710 adds r7, #16 800192e: 46bd mov sp, r7 8001930: bd80 pop {r7, pc} 8001932: bf00 nop 8001934: 20000008 .word 0x20000008 08001938 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001938: b480 push {r7} 800193a: b085 sub sp, #20 800193c: af00 add r7, sp, #0 800193e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001940: 687b ldr r3, [r7, #4] 8001942: f003 0307 and.w r3, r3, #7 8001946: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001948: 4b0c ldr r3, [pc, #48] ; (800197c <__NVIC_SetPriorityGrouping+0x44>) 800194a: 68db ldr r3, [r3, #12] 800194c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800194e: 68ba ldr r2, [r7, #8] 8001950: f64f 03ff movw r3, #63743 ; 0xf8ff 8001954: 4013 ands r3, r2 8001956: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001958: 68fb ldr r3, [r7, #12] 800195a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800195c: 68bb ldr r3, [r7, #8] 800195e: 4313 orrs r3, r2 reg_value = (reg_value | 8001960: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001964: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001968: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800196a: 4a04 ldr r2, [pc, #16] ; (800197c <__NVIC_SetPriorityGrouping+0x44>) 800196c: 68bb ldr r3, [r7, #8] 800196e: 60d3 str r3, [r2, #12] } 8001970: bf00 nop 8001972: 3714 adds r7, #20 8001974: 46bd mov sp, r7 8001976: bc80 pop {r7} 8001978: 4770 bx lr 800197a: bf00 nop 800197c: e000ed00 .word 0xe000ed00 08001980 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001980: b480 push {r7} 8001982: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001984: 4b04 ldr r3, [pc, #16] ; (8001998 <__NVIC_GetPriorityGrouping+0x18>) 8001986: 68db ldr r3, [r3, #12] 8001988: 0a1b lsrs r3, r3, #8 800198a: f003 0307 and.w r3, r3, #7 } 800198e: 4618 mov r0, r3 8001990: 46bd mov sp, r7 8001992: bc80 pop {r7} 8001994: 4770 bx lr 8001996: bf00 nop 8001998: e000ed00 .word 0xe000ed00 0800199c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800199c: b480 push {r7} 800199e: b083 sub sp, #12 80019a0: af00 add r7, sp, #0 80019a2: 4603 mov r3, r0 80019a4: 6039 str r1, [r7, #0] 80019a6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80019a8: f997 3007 ldrsb.w r3, [r7, #7] 80019ac: 2b00 cmp r3, #0 80019ae: db0a blt.n 80019c6 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80019b0: 683b ldr r3, [r7, #0] 80019b2: b2da uxtb r2, r3 80019b4: 490c ldr r1, [pc, #48] ; (80019e8 <__NVIC_SetPriority+0x4c>) 80019b6: f997 3007 ldrsb.w r3, [r7, #7] 80019ba: 0112 lsls r2, r2, #4 80019bc: b2d2 uxtb r2, r2 80019be: 440b add r3, r1 80019c0: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80019c4: e00a b.n 80019dc <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80019c6: 683b ldr r3, [r7, #0] 80019c8: b2da uxtb r2, r3 80019ca: 4908 ldr r1, [pc, #32] ; (80019ec <__NVIC_SetPriority+0x50>) 80019cc: 79fb ldrb r3, [r7, #7] 80019ce: f003 030f and.w r3, r3, #15 80019d2: 3b04 subs r3, #4 80019d4: 0112 lsls r2, r2, #4 80019d6: b2d2 uxtb r2, r2 80019d8: 440b add r3, r1 80019da: 761a strb r2, [r3, #24] } 80019dc: bf00 nop 80019de: 370c adds r7, #12 80019e0: 46bd mov sp, r7 80019e2: bc80 pop {r7} 80019e4: 4770 bx lr 80019e6: bf00 nop 80019e8: e000e100 .word 0xe000e100 80019ec: e000ed00 .word 0xe000ed00 080019f0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80019f0: b480 push {r7} 80019f2: b089 sub sp, #36 ; 0x24 80019f4: af00 add r7, sp, #0 80019f6: 60f8 str r0, [r7, #12] 80019f8: 60b9 str r1, [r7, #8] 80019fa: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80019fc: 68fb ldr r3, [r7, #12] 80019fe: f003 0307 and.w r3, r3, #7 8001a02: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001a04: 69fb ldr r3, [r7, #28] 8001a06: f1c3 0307 rsb r3, r3, #7 8001a0a: 2b04 cmp r3, #4 8001a0c: bf28 it cs 8001a0e: 2304 movcs r3, #4 8001a10: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001a12: 69fb ldr r3, [r7, #28] 8001a14: 3304 adds r3, #4 8001a16: 2b06 cmp r3, #6 8001a18: d902 bls.n 8001a20 8001a1a: 69fb ldr r3, [r7, #28] 8001a1c: 3b03 subs r3, #3 8001a1e: e000 b.n 8001a22 8001a20: 2300 movs r3, #0 8001a22: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001a24: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8001a28: 69bb ldr r3, [r7, #24] 8001a2a: fa02 f303 lsl.w r3, r2, r3 8001a2e: 43da mvns r2, r3 8001a30: 68bb ldr r3, [r7, #8] 8001a32: 401a ands r2, r3 8001a34: 697b ldr r3, [r7, #20] 8001a36: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001a38: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001a3c: 697b ldr r3, [r7, #20] 8001a3e: fa01 f303 lsl.w r3, r1, r3 8001a42: 43d9 mvns r1, r3 8001a44: 687b ldr r3, [r7, #4] 8001a46: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001a48: 4313 orrs r3, r2 ); } 8001a4a: 4618 mov r0, r3 8001a4c: 3724 adds r7, #36 ; 0x24 8001a4e: 46bd mov sp, r7 8001a50: bc80 pop {r7} 8001a52: 4770 bx lr 08001a54 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001a54: b580 push {r7, lr} 8001a56: b082 sub sp, #8 8001a58: af00 add r7, sp, #0 8001a5a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001a5c: 687b ldr r3, [r7, #4] 8001a5e: 3b01 subs r3, #1 8001a60: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001a64: d301 bcc.n 8001a6a { return (1UL); /* Reload value impossible */ 8001a66: 2301 movs r3, #1 8001a68: e00f b.n 8001a8a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001a6a: 4a0a ldr r2, [pc, #40] ; (8001a94 ) 8001a6c: 687b ldr r3, [r7, #4] 8001a6e: 3b01 subs r3, #1 8001a70: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001a72: 210f movs r1, #15 8001a74: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001a78: f7ff ff90 bl 800199c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001a7c: 4b05 ldr r3, [pc, #20] ; (8001a94 ) 8001a7e: 2200 movs r2, #0 8001a80: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001a82: 4b04 ldr r3, [pc, #16] ; (8001a94 ) 8001a84: 2207 movs r2, #7 8001a86: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001a88: 2300 movs r3, #0 } 8001a8a: 4618 mov r0, r3 8001a8c: 3708 adds r7, #8 8001a8e: 46bd mov sp, r7 8001a90: bd80 pop {r7, pc} 8001a92: bf00 nop 8001a94: e000e010 .word 0xe000e010 08001a98 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a98: b580 push {r7, lr} 8001a9a: b082 sub sp, #8 8001a9c: af00 add r7, sp, #0 8001a9e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001aa0: 6878 ldr r0, [r7, #4] 8001aa2: f7ff ff49 bl 8001938 <__NVIC_SetPriorityGrouping> } 8001aa6: bf00 nop 8001aa8: 3708 adds r7, #8 8001aaa: 46bd mov sp, r7 8001aac: bd80 pop {r7, pc} 08001aae : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001aae: b580 push {r7, lr} 8001ab0: b086 sub sp, #24 8001ab2: af00 add r7, sp, #0 8001ab4: 4603 mov r3, r0 8001ab6: 60b9 str r1, [r7, #8] 8001ab8: 607a str r2, [r7, #4] 8001aba: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001abc: 2300 movs r3, #0 8001abe: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001ac0: f7ff ff5e bl 8001980 <__NVIC_GetPriorityGrouping> 8001ac4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001ac6: 687a ldr r2, [r7, #4] 8001ac8: 68b9 ldr r1, [r7, #8] 8001aca: 6978 ldr r0, [r7, #20] 8001acc: f7ff ff90 bl 80019f0 8001ad0: 4602 mov r2, r0 8001ad2: f997 300f ldrsb.w r3, [r7, #15] 8001ad6: 4611 mov r1, r2 8001ad8: 4618 mov r0, r3 8001ada: f7ff ff5f bl 800199c <__NVIC_SetPriority> } 8001ade: bf00 nop 8001ae0: 3718 adds r7, #24 8001ae2: 46bd mov sp, r7 8001ae4: bd80 pop {r7, pc} 08001ae6 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001ae6: b580 push {r7, lr} 8001ae8: b082 sub sp, #8 8001aea: af00 add r7, sp, #0 8001aec: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001aee: 6878 ldr r0, [r7, #4] 8001af0: f7ff ffb0 bl 8001a54 8001af4: 4603 mov r3, r0 } 8001af6: 4618 mov r0, r3 8001af8: 3708 adds r7, #8 8001afa: 46bd mov sp, r7 8001afc: bd80 pop {r7, pc} ... 08001b00 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001b00: b480 push {r7} 8001b02: b08b sub sp, #44 ; 0x2c 8001b04: af00 add r7, sp, #0 8001b06: 6078 str r0, [r7, #4] 8001b08: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8001b0a: 2300 movs r3, #0 8001b0c: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8001b0e: 2300 movs r3, #0 8001b10: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8001b12: e179 b.n 8001e08 { /* Get the IO position */ ioposition = (0x01uL << position); 8001b14: 2201 movs r2, #1 8001b16: 6a7b ldr r3, [r7, #36] ; 0x24 8001b18: fa02 f303 lsl.w r3, r2, r3 8001b1c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001b1e: 683b ldr r3, [r7, #0] 8001b20: 681b ldr r3, [r3, #0] 8001b22: 69fa ldr r2, [r7, #28] 8001b24: 4013 ands r3, r2 8001b26: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8001b28: 69ba ldr r2, [r7, #24] 8001b2a: 69fb ldr r3, [r7, #28] 8001b2c: 429a cmp r2, r3 8001b2e: f040 8168 bne.w 8001e02 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8001b32: 683b ldr r3, [r7, #0] 8001b34: 685b ldr r3, [r3, #4] 8001b36: 4aa0 ldr r2, [pc, #640] ; (8001db8 ) 8001b38: 4293 cmp r3, r2 8001b3a: d05e beq.n 8001bfa 8001b3c: 4a9e ldr r2, [pc, #632] ; (8001db8 ) 8001b3e: 4293 cmp r3, r2 8001b40: d875 bhi.n 8001c2e 8001b42: 4a9e ldr r2, [pc, #632] ; (8001dbc ) 8001b44: 4293 cmp r3, r2 8001b46: d058 beq.n 8001bfa 8001b48: 4a9c ldr r2, [pc, #624] ; (8001dbc ) 8001b4a: 4293 cmp r3, r2 8001b4c: d86f bhi.n 8001c2e 8001b4e: 4a9c ldr r2, [pc, #624] ; (8001dc0 ) 8001b50: 4293 cmp r3, r2 8001b52: d052 beq.n 8001bfa 8001b54: 4a9a ldr r2, [pc, #616] ; (8001dc0 ) 8001b56: 4293 cmp r3, r2 8001b58: d869 bhi.n 8001c2e 8001b5a: 4a9a ldr r2, [pc, #616] ; (8001dc4 ) 8001b5c: 4293 cmp r3, r2 8001b5e: d04c beq.n 8001bfa 8001b60: 4a98 ldr r2, [pc, #608] ; (8001dc4 ) 8001b62: 4293 cmp r3, r2 8001b64: d863 bhi.n 8001c2e 8001b66: 4a98 ldr r2, [pc, #608] ; (8001dc8 ) 8001b68: 4293 cmp r3, r2 8001b6a: d046 beq.n 8001bfa 8001b6c: 4a96 ldr r2, [pc, #600] ; (8001dc8 ) 8001b6e: 4293 cmp r3, r2 8001b70: d85d bhi.n 8001c2e 8001b72: 2b12 cmp r3, #18 8001b74: d82a bhi.n 8001bcc 8001b76: 2b12 cmp r3, #18 8001b78: d859 bhi.n 8001c2e 8001b7a: a201 add r2, pc, #4 ; (adr r2, 8001b80 ) 8001b7c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001b80: 08001bfb .word 0x08001bfb 8001b84: 08001bd5 .word 0x08001bd5 8001b88: 08001be7 .word 0x08001be7 8001b8c: 08001c29 .word 0x08001c29 8001b90: 08001c2f .word 0x08001c2f 8001b94: 08001c2f .word 0x08001c2f 8001b98: 08001c2f .word 0x08001c2f 8001b9c: 08001c2f .word 0x08001c2f 8001ba0: 08001c2f .word 0x08001c2f 8001ba4: 08001c2f .word 0x08001c2f 8001ba8: 08001c2f .word 0x08001c2f 8001bac: 08001c2f .word 0x08001c2f 8001bb0: 08001c2f .word 0x08001c2f 8001bb4: 08001c2f .word 0x08001c2f 8001bb8: 08001c2f .word 0x08001c2f 8001bbc: 08001c2f .word 0x08001c2f 8001bc0: 08001c2f .word 0x08001c2f 8001bc4: 08001bdd .word 0x08001bdd 8001bc8: 08001bf1 .word 0x08001bf1 8001bcc: 4a7f ldr r2, [pc, #508] ; (8001dcc ) 8001bce: 4293 cmp r3, r2 8001bd0: d013 beq.n 8001bfa config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001bd2: e02c b.n 8001c2e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001bd4: 683b ldr r3, [r7, #0] 8001bd6: 68db ldr r3, [r3, #12] 8001bd8: 623b str r3, [r7, #32] break; 8001bda: e029 b.n 8001c30 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8001bdc: 683b ldr r3, [r7, #0] 8001bde: 68db ldr r3, [r3, #12] 8001be0: 3304 adds r3, #4 8001be2: 623b str r3, [r7, #32] break; 8001be4: e024 b.n 8001c30 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001be6: 683b ldr r3, [r7, #0] 8001be8: 68db ldr r3, [r3, #12] 8001bea: 3308 adds r3, #8 8001bec: 623b str r3, [r7, #32] break; 8001bee: e01f b.n 8001c30 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001bf0: 683b ldr r3, [r7, #0] 8001bf2: 68db ldr r3, [r3, #12] 8001bf4: 330c adds r3, #12 8001bf6: 623b str r3, [r7, #32] break; 8001bf8: e01a b.n 8001c30 if (GPIO_Init->Pull == GPIO_NOPULL) 8001bfa: 683b ldr r3, [r7, #0] 8001bfc: 689b ldr r3, [r3, #8] 8001bfe: 2b00 cmp r3, #0 8001c00: d102 bne.n 8001c08 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001c02: 2304 movs r3, #4 8001c04: 623b str r3, [r7, #32] break; 8001c06: e013 b.n 8001c30 else if (GPIO_Init->Pull == GPIO_PULLUP) 8001c08: 683b ldr r3, [r7, #0] 8001c0a: 689b ldr r3, [r3, #8] 8001c0c: 2b01 cmp r3, #1 8001c0e: d105 bne.n 8001c1c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001c10: 2308 movs r3, #8 8001c12: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001c14: 687b ldr r3, [r7, #4] 8001c16: 69fa ldr r2, [r7, #28] 8001c18: 611a str r2, [r3, #16] break; 8001c1a: e009 b.n 8001c30 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001c1c: 2308 movs r3, #8 8001c1e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001c20: 687b ldr r3, [r7, #4] 8001c22: 69fa ldr r2, [r7, #28] 8001c24: 615a str r2, [r3, #20] break; 8001c26: e003 b.n 8001c30 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8001c28: 2300 movs r3, #0 8001c2a: 623b str r3, [r7, #32] break; 8001c2c: e000 b.n 8001c30 break; 8001c2e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001c30: 69bb ldr r3, [r7, #24] 8001c32: 2bff cmp r3, #255 ; 0xff 8001c34: d801 bhi.n 8001c3a 8001c36: 687b ldr r3, [r7, #4] 8001c38: e001 b.n 8001c3e 8001c3a: 687b ldr r3, [r7, #4] 8001c3c: 3304 adds r3, #4 8001c3e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001c40: 69bb ldr r3, [r7, #24] 8001c42: 2bff cmp r3, #255 ; 0xff 8001c44: d802 bhi.n 8001c4c 8001c46: 6a7b ldr r3, [r7, #36] ; 0x24 8001c48: 009b lsls r3, r3, #2 8001c4a: e002 b.n 8001c52 8001c4c: 6a7b ldr r3, [r7, #36] ; 0x24 8001c4e: 3b08 subs r3, #8 8001c50: 009b lsls r3, r3, #2 8001c52: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001c54: 697b ldr r3, [r7, #20] 8001c56: 681a ldr r2, [r3, #0] 8001c58: 210f movs r1, #15 8001c5a: 693b ldr r3, [r7, #16] 8001c5c: fa01 f303 lsl.w r3, r1, r3 8001c60: 43db mvns r3, r3 8001c62: 401a ands r2, r3 8001c64: 6a39 ldr r1, [r7, #32] 8001c66: 693b ldr r3, [r7, #16] 8001c68: fa01 f303 lsl.w r3, r1, r3 8001c6c: 431a orrs r2, r3 8001c6e: 697b ldr r3, [r7, #20] 8001c70: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001c72: 683b ldr r3, [r7, #0] 8001c74: 685b ldr r3, [r3, #4] 8001c76: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001c7a: 2b00 cmp r3, #0 8001c7c: f000 80c1 beq.w 8001e02 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001c80: 4b53 ldr r3, [pc, #332] ; (8001dd0 ) 8001c82: 699b ldr r3, [r3, #24] 8001c84: 4a52 ldr r2, [pc, #328] ; (8001dd0 ) 8001c86: f043 0301 orr.w r3, r3, #1 8001c8a: 6193 str r3, [r2, #24] 8001c8c: 4b50 ldr r3, [pc, #320] ; (8001dd0 ) 8001c8e: 699b ldr r3, [r3, #24] 8001c90: f003 0301 and.w r3, r3, #1 8001c94: 60bb str r3, [r7, #8] 8001c96: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001c98: 4a4e ldr r2, [pc, #312] ; (8001dd4 ) 8001c9a: 6a7b ldr r3, [r7, #36] ; 0x24 8001c9c: 089b lsrs r3, r3, #2 8001c9e: 3302 adds r3, #2 8001ca0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001ca4: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001ca6: 6a7b ldr r3, [r7, #36] ; 0x24 8001ca8: f003 0303 and.w r3, r3, #3 8001cac: 009b lsls r3, r3, #2 8001cae: 220f movs r2, #15 8001cb0: fa02 f303 lsl.w r3, r2, r3 8001cb4: 43db mvns r3, r3 8001cb6: 68fa ldr r2, [r7, #12] 8001cb8: 4013 ands r3, r2 8001cba: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8001cbc: 687b ldr r3, [r7, #4] 8001cbe: 4a46 ldr r2, [pc, #280] ; (8001dd8 ) 8001cc0: 4293 cmp r3, r2 8001cc2: d01f beq.n 8001d04 8001cc4: 687b ldr r3, [r7, #4] 8001cc6: 4a45 ldr r2, [pc, #276] ; (8001ddc ) 8001cc8: 4293 cmp r3, r2 8001cca: d019 beq.n 8001d00 8001ccc: 687b ldr r3, [r7, #4] 8001cce: 4a44 ldr r2, [pc, #272] ; (8001de0 ) 8001cd0: 4293 cmp r3, r2 8001cd2: d013 beq.n 8001cfc 8001cd4: 687b ldr r3, [r7, #4] 8001cd6: 4a43 ldr r2, [pc, #268] ; (8001de4 ) 8001cd8: 4293 cmp r3, r2 8001cda: d00d beq.n 8001cf8 8001cdc: 687b ldr r3, [r7, #4] 8001cde: 4a42 ldr r2, [pc, #264] ; (8001de8 ) 8001ce0: 4293 cmp r3, r2 8001ce2: d007 beq.n 8001cf4 8001ce4: 687b ldr r3, [r7, #4] 8001ce6: 4a41 ldr r2, [pc, #260] ; (8001dec ) 8001ce8: 4293 cmp r3, r2 8001cea: d101 bne.n 8001cf0 8001cec: 2305 movs r3, #5 8001cee: e00a b.n 8001d06 8001cf0: 2306 movs r3, #6 8001cf2: e008 b.n 8001d06 8001cf4: 2304 movs r3, #4 8001cf6: e006 b.n 8001d06 8001cf8: 2303 movs r3, #3 8001cfa: e004 b.n 8001d06 8001cfc: 2302 movs r3, #2 8001cfe: e002 b.n 8001d06 8001d00: 2301 movs r3, #1 8001d02: e000 b.n 8001d06 8001d04: 2300 movs r3, #0 8001d06: 6a7a ldr r2, [r7, #36] ; 0x24 8001d08: f002 0203 and.w r2, r2, #3 8001d0c: 0092 lsls r2, r2, #2 8001d0e: 4093 lsls r3, r2 8001d10: 68fa ldr r2, [r7, #12] 8001d12: 4313 orrs r3, r2 8001d14: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001d16: 492f ldr r1, [pc, #188] ; (8001dd4 ) 8001d18: 6a7b ldr r3, [r7, #36] ; 0x24 8001d1a: 089b lsrs r3, r3, #2 8001d1c: 3302 adds r3, #2 8001d1e: 68fa ldr r2, [r7, #12] 8001d20: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8001d24: 683b ldr r3, [r7, #0] 8001d26: 685b ldr r3, [r3, #4] 8001d28: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001d2c: 2b00 cmp r3, #0 8001d2e: d006 beq.n 8001d3e { SET_BIT(EXTI->IMR, iocurrent); 8001d30: 4b2f ldr r3, [pc, #188] ; (8001df0 ) 8001d32: 681a ldr r2, [r3, #0] 8001d34: 492e ldr r1, [pc, #184] ; (8001df0 ) 8001d36: 69bb ldr r3, [r7, #24] 8001d38: 4313 orrs r3, r2 8001d3a: 600b str r3, [r1, #0] 8001d3c: e006 b.n 8001d4c } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8001d3e: 4b2c ldr r3, [pc, #176] ; (8001df0 ) 8001d40: 681a ldr r2, [r3, #0] 8001d42: 69bb ldr r3, [r7, #24] 8001d44: 43db mvns r3, r3 8001d46: 492a ldr r1, [pc, #168] ; (8001df0 ) 8001d48: 4013 ands r3, r2 8001d4a: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8001d4c: 683b ldr r3, [r7, #0] 8001d4e: 685b ldr r3, [r3, #4] 8001d50: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001d54: 2b00 cmp r3, #0 8001d56: d006 beq.n 8001d66 { SET_BIT(EXTI->EMR, iocurrent); 8001d58: 4b25 ldr r3, [pc, #148] ; (8001df0 ) 8001d5a: 685a ldr r2, [r3, #4] 8001d5c: 4924 ldr r1, [pc, #144] ; (8001df0 ) 8001d5e: 69bb ldr r3, [r7, #24] 8001d60: 4313 orrs r3, r2 8001d62: 604b str r3, [r1, #4] 8001d64: e006 b.n 8001d74 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8001d66: 4b22 ldr r3, [pc, #136] ; (8001df0 ) 8001d68: 685a ldr r2, [r3, #4] 8001d6a: 69bb ldr r3, [r7, #24] 8001d6c: 43db mvns r3, r3 8001d6e: 4920 ldr r1, [pc, #128] ; (8001df0 ) 8001d70: 4013 ands r3, r2 8001d72: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001d74: 683b ldr r3, [r7, #0] 8001d76: 685b ldr r3, [r3, #4] 8001d78: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001d7c: 2b00 cmp r3, #0 8001d7e: d006 beq.n 8001d8e { SET_BIT(EXTI->RTSR, iocurrent); 8001d80: 4b1b ldr r3, [pc, #108] ; (8001df0 ) 8001d82: 689a ldr r2, [r3, #8] 8001d84: 491a ldr r1, [pc, #104] ; (8001df0 ) 8001d86: 69bb ldr r3, [r7, #24] 8001d88: 4313 orrs r3, r2 8001d8a: 608b str r3, [r1, #8] 8001d8c: e006 b.n 8001d9c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8001d8e: 4b18 ldr r3, [pc, #96] ; (8001df0 ) 8001d90: 689a ldr r2, [r3, #8] 8001d92: 69bb ldr r3, [r7, #24] 8001d94: 43db mvns r3, r3 8001d96: 4916 ldr r1, [pc, #88] ; (8001df0 ) 8001d98: 4013 ands r3, r2 8001d9a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8001d9c: 683b ldr r3, [r7, #0] 8001d9e: 685b ldr r3, [r3, #4] 8001da0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001da4: 2b00 cmp r3, #0 8001da6: d025 beq.n 8001df4 { SET_BIT(EXTI->FTSR, iocurrent); 8001da8: 4b11 ldr r3, [pc, #68] ; (8001df0 ) 8001daa: 68da ldr r2, [r3, #12] 8001dac: 4910 ldr r1, [pc, #64] ; (8001df0 ) 8001dae: 69bb ldr r3, [r7, #24] 8001db0: 4313 orrs r3, r2 8001db2: 60cb str r3, [r1, #12] 8001db4: e025 b.n 8001e02 8001db6: bf00 nop 8001db8: 10320000 .word 0x10320000 8001dbc: 10310000 .word 0x10310000 8001dc0: 10220000 .word 0x10220000 8001dc4: 10210000 .word 0x10210000 8001dc8: 10120000 .word 0x10120000 8001dcc: 10110000 .word 0x10110000 8001dd0: 40021000 .word 0x40021000 8001dd4: 40010000 .word 0x40010000 8001dd8: 40010800 .word 0x40010800 8001ddc: 40010c00 .word 0x40010c00 8001de0: 40011000 .word 0x40011000 8001de4: 40011400 .word 0x40011400 8001de8: 40011800 .word 0x40011800 8001dec: 40011c00 .word 0x40011c00 8001df0: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001df4: 4b0b ldr r3, [pc, #44] ; (8001e24 ) 8001df6: 68da ldr r2, [r3, #12] 8001df8: 69bb ldr r3, [r7, #24] 8001dfa: 43db mvns r3, r3 8001dfc: 4909 ldr r1, [pc, #36] ; (8001e24 ) 8001dfe: 4013 ands r3, r2 8001e00: 60cb str r3, [r1, #12] } } } position++; 8001e02: 6a7b ldr r3, [r7, #36] ; 0x24 8001e04: 3301 adds r3, #1 8001e06: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8001e08: 683b ldr r3, [r7, #0] 8001e0a: 681a ldr r2, [r3, #0] 8001e0c: 6a7b ldr r3, [r7, #36] ; 0x24 8001e0e: fa22 f303 lsr.w r3, r2, r3 8001e12: 2b00 cmp r3, #0 8001e14: f47f ae7e bne.w 8001b14 } } 8001e18: bf00 nop 8001e1a: bf00 nop 8001e1c: 372c adds r7, #44 ; 0x2c 8001e1e: 46bd mov sp, r7 8001e20: bc80 pop {r7} 8001e22: 4770 bx lr 8001e24: 40010400 .word 0x40010400 08001e28 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001e28: b480 push {r7} 8001e2a: b085 sub sp, #20 8001e2c: af00 add r7, sp, #0 8001e2e: 6078 str r0, [r7, #4] 8001e30: 460b mov r3, r1 8001e32: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001e34: 687b ldr r3, [r7, #4] 8001e36: 689a ldr r2, [r3, #8] 8001e38: 887b ldrh r3, [r7, #2] 8001e3a: 4013 ands r3, r2 8001e3c: 2b00 cmp r3, #0 8001e3e: d002 beq.n 8001e46 { bitstatus = GPIO_PIN_SET; 8001e40: 2301 movs r3, #1 8001e42: 73fb strb r3, [r7, #15] 8001e44: e001 b.n 8001e4a } else { bitstatus = GPIO_PIN_RESET; 8001e46: 2300 movs r3, #0 8001e48: 73fb strb r3, [r7, #15] } return bitstatus; 8001e4a: 7bfb ldrb r3, [r7, #15] } 8001e4c: 4618 mov r0, r3 8001e4e: 3714 adds r7, #20 8001e50: 46bd mov sp, r7 8001e52: bc80 pop {r7} 8001e54: 4770 bx lr 08001e56 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001e56: b480 push {r7} 8001e58: b083 sub sp, #12 8001e5a: af00 add r7, sp, #0 8001e5c: 6078 str r0, [r7, #4] 8001e5e: 460b mov r3, r1 8001e60: 807b strh r3, [r7, #2] 8001e62: 4613 mov r3, r2 8001e64: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001e66: 787b ldrb r3, [r7, #1] 8001e68: 2b00 cmp r3, #0 8001e6a: d003 beq.n 8001e74 { GPIOx->BSRR = GPIO_Pin; 8001e6c: 887a ldrh r2, [r7, #2] 8001e6e: 687b ldr r3, [r7, #4] 8001e70: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8001e72: e003 b.n 8001e7c GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8001e74: 887b ldrh r3, [r7, #2] 8001e76: 041a lsls r2, r3, #16 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 611a str r2, [r3, #16] } 8001e7c: bf00 nop 8001e7e: 370c adds r7, #12 8001e80: 46bd mov sp, r7 8001e82: bc80 pop {r7} 8001e84: 4770 bx lr ... 08001e88 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8001e88: b580 push {r7, lr} 8001e8a: b084 sub sp, #16 8001e8c: af00 add r7, sp, #0 8001e8e: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8001e90: 687b ldr r3, [r7, #4] 8001e92: 2b00 cmp r3, #0 8001e94: d101 bne.n 8001e9a { return HAL_ERROR; 8001e96: 2301 movs r3, #1 8001e98: e12b b.n 80020f2 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001ea0: b2db uxtb r3, r3 8001ea2: 2b00 cmp r3, #0 8001ea4: d106 bne.n 8001eb4 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8001ea6: 687b ldr r3, [r7, #4] 8001ea8: 2200 movs r2, #0 8001eaa: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8001eae: 6878 ldr r0, [r7, #4] 8001eb0: f7ff fb0a bl 80014c8 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8001eb4: 687b ldr r3, [r7, #4] 8001eb6: 2224 movs r2, #36 ; 0x24 8001eb8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001ebc: 687b ldr r3, [r7, #4] 8001ebe: 681b ldr r3, [r3, #0] 8001ec0: 681a ldr r2, [r3, #0] 8001ec2: 687b ldr r3, [r7, #4] 8001ec4: 681b ldr r3, [r3, #0] 8001ec6: f022 0201 bic.w r2, r2, #1 8001eca: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8001ecc: 687b ldr r3, [r7, #4] 8001ece: 681b ldr r3, [r3, #0] 8001ed0: 681a ldr r2, [r3, #0] 8001ed2: 687b ldr r3, [r7, #4] 8001ed4: 681b ldr r3, [r3, #0] 8001ed6: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8001eda: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8001edc: 687b ldr r3, [r7, #4] 8001ede: 681b ldr r3, [r3, #0] 8001ee0: 681a ldr r2, [r3, #0] 8001ee2: 687b ldr r3, [r7, #4] 8001ee4: 681b ldr r3, [r3, #0] 8001ee6: f422 4200 bic.w r2, r2, #32768 ; 0x8000 8001eea: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8001eec: f001 fba0 bl 8003630 8001ef0: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8001ef2: 687b ldr r3, [r7, #4] 8001ef4: 685b ldr r3, [r3, #4] 8001ef6: 4a81 ldr r2, [pc, #516] ; (80020fc ) 8001ef8: 4293 cmp r3, r2 8001efa: d807 bhi.n 8001f0c 8001efc: 68fb ldr r3, [r7, #12] 8001efe: 4a80 ldr r2, [pc, #512] ; (8002100 ) 8001f00: 4293 cmp r3, r2 8001f02: bf94 ite ls 8001f04: 2301 movls r3, #1 8001f06: 2300 movhi r3, #0 8001f08: b2db uxtb r3, r3 8001f0a: e006 b.n 8001f1a 8001f0c: 68fb ldr r3, [r7, #12] 8001f0e: 4a7d ldr r2, [pc, #500] ; (8002104 ) 8001f10: 4293 cmp r3, r2 8001f12: bf94 ite ls 8001f14: 2301 movls r3, #1 8001f16: 2300 movhi r3, #0 8001f18: b2db uxtb r3, r3 8001f1a: 2b00 cmp r3, #0 8001f1c: d001 beq.n 8001f22 { return HAL_ERROR; 8001f1e: 2301 movs r3, #1 8001f20: e0e7 b.n 80020f2 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8001f22: 68fb ldr r3, [r7, #12] 8001f24: 4a78 ldr r2, [pc, #480] ; (8002108 ) 8001f26: fba2 2303 umull r2, r3, r2, r3 8001f2a: 0c9b lsrs r3, r3, #18 8001f2c: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8001f2e: 687b ldr r3, [r7, #4] 8001f30: 681b ldr r3, [r3, #0] 8001f32: 685b ldr r3, [r3, #4] 8001f34: f023 013f bic.w r1, r3, #63 ; 0x3f 8001f38: 687b ldr r3, [r7, #4] 8001f3a: 681b ldr r3, [r3, #0] 8001f3c: 68ba ldr r2, [r7, #8] 8001f3e: 430a orrs r2, r1 8001f40: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8001f42: 687b ldr r3, [r7, #4] 8001f44: 681b ldr r3, [r3, #0] 8001f46: 6a1b ldr r3, [r3, #32] 8001f48: f023 013f bic.w r1, r3, #63 ; 0x3f 8001f4c: 687b ldr r3, [r7, #4] 8001f4e: 685b ldr r3, [r3, #4] 8001f50: 4a6a ldr r2, [pc, #424] ; (80020fc ) 8001f52: 4293 cmp r3, r2 8001f54: d802 bhi.n 8001f5c 8001f56: 68bb ldr r3, [r7, #8] 8001f58: 3301 adds r3, #1 8001f5a: e009 b.n 8001f70 8001f5c: 68bb ldr r3, [r7, #8] 8001f5e: f44f 7296 mov.w r2, #300 ; 0x12c 8001f62: fb02 f303 mul.w r3, r2, r3 8001f66: 4a69 ldr r2, [pc, #420] ; (800210c ) 8001f68: fba2 2303 umull r2, r3, r2, r3 8001f6c: 099b lsrs r3, r3, #6 8001f6e: 3301 adds r3, #1 8001f70: 687a ldr r2, [r7, #4] 8001f72: 6812 ldr r2, [r2, #0] 8001f74: 430b orrs r3, r1 8001f76: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8001f78: 687b ldr r3, [r7, #4] 8001f7a: 681b ldr r3, [r3, #0] 8001f7c: 69db ldr r3, [r3, #28] 8001f7e: f423 424f bic.w r2, r3, #52992 ; 0xcf00 8001f82: f022 02ff bic.w r2, r2, #255 ; 0xff 8001f86: 687b ldr r3, [r7, #4] 8001f88: 685b ldr r3, [r3, #4] 8001f8a: 495c ldr r1, [pc, #368] ; (80020fc ) 8001f8c: 428b cmp r3, r1 8001f8e: d819 bhi.n 8001fc4 8001f90: 68fb ldr r3, [r7, #12] 8001f92: 1e59 subs r1, r3, #1 8001f94: 687b ldr r3, [r7, #4] 8001f96: 685b ldr r3, [r3, #4] 8001f98: 005b lsls r3, r3, #1 8001f9a: fbb1 f3f3 udiv r3, r1, r3 8001f9e: 1c59 adds r1, r3, #1 8001fa0: f640 73fc movw r3, #4092 ; 0xffc 8001fa4: 400b ands r3, r1 8001fa6: 2b00 cmp r3, #0 8001fa8: d00a beq.n 8001fc0 8001faa: 68fb ldr r3, [r7, #12] 8001fac: 1e59 subs r1, r3, #1 8001fae: 687b ldr r3, [r7, #4] 8001fb0: 685b ldr r3, [r3, #4] 8001fb2: 005b lsls r3, r3, #1 8001fb4: fbb1 f3f3 udiv r3, r1, r3 8001fb8: 3301 adds r3, #1 8001fba: f3c3 030b ubfx r3, r3, #0, #12 8001fbe: e051 b.n 8002064 8001fc0: 2304 movs r3, #4 8001fc2: e04f b.n 8002064 8001fc4: 687b ldr r3, [r7, #4] 8001fc6: 689b ldr r3, [r3, #8] 8001fc8: 2b00 cmp r3, #0 8001fca: d111 bne.n 8001ff0 8001fcc: 68fb ldr r3, [r7, #12] 8001fce: 1e58 subs r0, r3, #1 8001fd0: 687b ldr r3, [r7, #4] 8001fd2: 6859 ldr r1, [r3, #4] 8001fd4: 460b mov r3, r1 8001fd6: 005b lsls r3, r3, #1 8001fd8: 440b add r3, r1 8001fda: fbb0 f3f3 udiv r3, r0, r3 8001fde: 3301 adds r3, #1 8001fe0: f3c3 030b ubfx r3, r3, #0, #12 8001fe4: 2b00 cmp r3, #0 8001fe6: bf0c ite eq 8001fe8: 2301 moveq r3, #1 8001fea: 2300 movne r3, #0 8001fec: b2db uxtb r3, r3 8001fee: e012 b.n 8002016 8001ff0: 68fb ldr r3, [r7, #12] 8001ff2: 1e58 subs r0, r3, #1 8001ff4: 687b ldr r3, [r7, #4] 8001ff6: 6859 ldr r1, [r3, #4] 8001ff8: 460b mov r3, r1 8001ffa: 009b lsls r3, r3, #2 8001ffc: 440b add r3, r1 8001ffe: 0099 lsls r1, r3, #2 8002000: 440b add r3, r1 8002002: fbb0 f3f3 udiv r3, r0, r3 8002006: 3301 adds r3, #1 8002008: f3c3 030b ubfx r3, r3, #0, #12 800200c: 2b00 cmp r3, #0 800200e: bf0c ite eq 8002010: 2301 moveq r3, #1 8002012: 2300 movne r3, #0 8002014: b2db uxtb r3, r3 8002016: 2b00 cmp r3, #0 8002018: d001 beq.n 800201e 800201a: 2301 movs r3, #1 800201c: e022 b.n 8002064 800201e: 687b ldr r3, [r7, #4] 8002020: 689b ldr r3, [r3, #8] 8002022: 2b00 cmp r3, #0 8002024: d10e bne.n 8002044 8002026: 68fb ldr r3, [r7, #12] 8002028: 1e58 subs r0, r3, #1 800202a: 687b ldr r3, [r7, #4] 800202c: 6859 ldr r1, [r3, #4] 800202e: 460b mov r3, r1 8002030: 005b lsls r3, r3, #1 8002032: 440b add r3, r1 8002034: fbb0 f3f3 udiv r3, r0, r3 8002038: 3301 adds r3, #1 800203a: f3c3 030b ubfx r3, r3, #0, #12 800203e: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8002042: e00f b.n 8002064 8002044: 68fb ldr r3, [r7, #12] 8002046: 1e58 subs r0, r3, #1 8002048: 687b ldr r3, [r7, #4] 800204a: 6859 ldr r1, [r3, #4] 800204c: 460b mov r3, r1 800204e: 009b lsls r3, r3, #2 8002050: 440b add r3, r1 8002052: 0099 lsls r1, r3, #2 8002054: 440b add r3, r1 8002056: fbb0 f3f3 udiv r3, r0, r3 800205a: 3301 adds r3, #1 800205c: f3c3 030b ubfx r3, r3, #0, #12 8002060: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8002064: 6879 ldr r1, [r7, #4] 8002066: 6809 ldr r1, [r1, #0] 8002068: 4313 orrs r3, r2 800206a: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 800206c: 687b ldr r3, [r7, #4] 800206e: 681b ldr r3, [r3, #0] 8002070: 681b ldr r3, [r3, #0] 8002072: f023 01c0 bic.w r1, r3, #192 ; 0xc0 8002076: 687b ldr r3, [r7, #4] 8002078: 69da ldr r2, [r3, #28] 800207a: 687b ldr r3, [r7, #4] 800207c: 6a1b ldr r3, [r3, #32] 800207e: 431a orrs r2, r3 8002080: 687b ldr r3, [r7, #4] 8002082: 681b ldr r3, [r3, #0] 8002084: 430a orrs r2, r1 8002086: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002088: 687b ldr r3, [r7, #4] 800208a: 681b ldr r3, [r3, #0] 800208c: 689b ldr r3, [r3, #8] 800208e: f423 4303 bic.w r3, r3, #33536 ; 0x8300 8002092: f023 03ff bic.w r3, r3, #255 ; 0xff 8002096: 687a ldr r2, [r7, #4] 8002098: 6911 ldr r1, [r2, #16] 800209a: 687a ldr r2, [r7, #4] 800209c: 68d2 ldr r2, [r2, #12] 800209e: 4311 orrs r1, r2 80020a0: 687a ldr r2, [r7, #4] 80020a2: 6812 ldr r2, [r2, #0] 80020a4: 430b orrs r3, r1 80020a6: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: 68db ldr r3, [r3, #12] 80020ae: f023 01ff bic.w r1, r3, #255 ; 0xff 80020b2: 687b ldr r3, [r7, #4] 80020b4: 695a ldr r2, [r3, #20] 80020b6: 687b ldr r3, [r7, #4] 80020b8: 699b ldr r3, [r3, #24] 80020ba: 431a orrs r2, r3 80020bc: 687b ldr r3, [r7, #4] 80020be: 681b ldr r3, [r3, #0] 80020c0: 430a orrs r2, r1 80020c2: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 80020c4: 687b ldr r3, [r7, #4] 80020c6: 681b ldr r3, [r3, #0] 80020c8: 681a ldr r2, [r3, #0] 80020ca: 687b ldr r3, [r7, #4] 80020cc: 681b ldr r3, [r3, #0] 80020ce: f042 0201 orr.w r2, r2, #1 80020d2: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80020d4: 687b ldr r3, [r7, #4] 80020d6: 2200 movs r2, #0 80020d8: 641a str r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_READY; 80020da: 687b ldr r3, [r7, #4] 80020dc: 2220 movs r2, #32 80020de: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->PreviousState = I2C_STATE_NONE; 80020e2: 687b ldr r3, [r7, #4] 80020e4: 2200 movs r2, #0 80020e6: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 80020e8: 687b ldr r3, [r7, #4] 80020ea: 2200 movs r2, #0 80020ec: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 80020f0: 2300 movs r3, #0 } 80020f2: 4618 mov r0, r3 80020f4: 3710 adds r7, #16 80020f6: 46bd mov sp, r7 80020f8: bd80 pop {r7, pc} 80020fa: bf00 nop 80020fc: 000186a0 .word 0x000186a0 8002100: 001e847f .word 0x001e847f 8002104: 003d08ff .word 0x003d08ff 8002108: 431bde83 .word 0x431bde83 800210c: 10624dd3 .word 0x10624dd3 08002110 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8002110: b580 push {r7, lr} 8002112: b088 sub sp, #32 8002114: af02 add r7, sp, #8 8002116: 60f8 str r0, [r7, #12] 8002118: 4608 mov r0, r1 800211a: 4611 mov r1, r2 800211c: 461a mov r2, r3 800211e: 4603 mov r3, r0 8002120: 817b strh r3, [r7, #10] 8002122: 460b mov r3, r1 8002124: 813b strh r3, [r7, #8] 8002126: 4613 mov r3, r2 8002128: 80fb strh r3, [r7, #6] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 800212a: f7ff fbd7 bl 80018dc 800212e: 6178 str r0, [r7, #20] /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8002130: 68fb ldr r3, [r7, #12] 8002132: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8002136: b2db uxtb r3, r3 8002138: 2b20 cmp r3, #32 800213a: f040 80d9 bne.w 80022f0 { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 800213e: 697b ldr r3, [r7, #20] 8002140: 9300 str r3, [sp, #0] 8002142: 2319 movs r3, #25 8002144: 2201 movs r2, #1 8002146: 496d ldr r1, [pc, #436] ; (80022fc ) 8002148: 68f8 ldr r0, [r7, #12] 800214a: f000 fcc1 bl 8002ad0 800214e: 4603 mov r3, r0 8002150: 2b00 cmp r3, #0 8002152: d001 beq.n 8002158 { return HAL_BUSY; 8002154: 2302 movs r3, #2 8002156: e0cc b.n 80022f2 } /* Process Locked */ __HAL_LOCK(hi2c); 8002158: 68fb ldr r3, [r7, #12] 800215a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800215e: 2b01 cmp r3, #1 8002160: d101 bne.n 8002166 8002162: 2302 movs r3, #2 8002164: e0c5 b.n 80022f2 8002166: 68fb ldr r3, [r7, #12] 8002168: 2201 movs r2, #1 800216a: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 800216e: 68fb ldr r3, [r7, #12] 8002170: 681b ldr r3, [r3, #0] 8002172: 681b ldr r3, [r3, #0] 8002174: f003 0301 and.w r3, r3, #1 8002178: 2b01 cmp r3, #1 800217a: d007 beq.n 800218c { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800217c: 68fb ldr r3, [r7, #12] 800217e: 681b ldr r3, [r3, #0] 8002180: 681a ldr r2, [r3, #0] 8002182: 68fb ldr r3, [r7, #12] 8002184: 681b ldr r3, [r3, #0] 8002186: f042 0201 orr.w r2, r2, #1 800218a: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 800218c: 68fb ldr r3, [r7, #12] 800218e: 681b ldr r3, [r3, #0] 8002190: 681a ldr r2, [r3, #0] 8002192: 68fb ldr r3, [r7, #12] 8002194: 681b ldr r3, [r3, #0] 8002196: f422 6200 bic.w r2, r2, #2048 ; 0x800 800219a: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_TX; 800219c: 68fb ldr r3, [r7, #12] 800219e: 2221 movs r2, #33 ; 0x21 80021a0: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 80021a4: 68fb ldr r3, [r7, #12] 80021a6: 2240 movs r2, #64 ; 0x40 80021a8: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80021ac: 68fb ldr r3, [r7, #12] 80021ae: 2200 movs r2, #0 80021b0: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 80021b2: 68fb ldr r3, [r7, #12] 80021b4: 6a3a ldr r2, [r7, #32] 80021b6: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 80021b8: 68fb ldr r3, [r7, #12] 80021ba: 8cba ldrh r2, [r7, #36] ; 0x24 80021bc: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 80021be: 68fb ldr r3, [r7, #12] 80021c0: 8d5b ldrh r3, [r3, #42] ; 0x2a 80021c2: b29a uxth r2, r3 80021c4: 68fb ldr r3, [r7, #12] 80021c6: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80021c8: 68fb ldr r3, [r7, #12] 80021ca: 4a4d ldr r2, [pc, #308] ; (8002300 ) 80021cc: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 80021ce: 88f8 ldrh r0, [r7, #6] 80021d0: 893a ldrh r2, [r7, #8] 80021d2: 8979 ldrh r1, [r7, #10] 80021d4: 697b ldr r3, [r7, #20] 80021d6: 9301 str r3, [sp, #4] 80021d8: 6abb ldr r3, [r7, #40] ; 0x28 80021da: 9300 str r3, [sp, #0] 80021dc: 4603 mov r3, r0 80021de: 68f8 ldr r0, [r7, #12] 80021e0: f000 faf8 bl 80027d4 80021e4: 4603 mov r3, r0 80021e6: 2b00 cmp r3, #0 80021e8: d052 beq.n 8002290 { return HAL_ERROR; 80021ea: 2301 movs r3, #1 80021ec: e081 b.n 80022f2 } while (hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80021ee: 697a ldr r2, [r7, #20] 80021f0: 6ab9 ldr r1, [r7, #40] ; 0x28 80021f2: 68f8 ldr r0, [r7, #12] 80021f4: f000 fd42 bl 8002c7c 80021f8: 4603 mov r3, r0 80021fa: 2b00 cmp r3, #0 80021fc: d00d beq.n 800221a { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 80021fe: 68fb ldr r3, [r7, #12] 8002200: 6c1b ldr r3, [r3, #64] ; 0x40 8002202: 2b04 cmp r3, #4 8002204: d107 bne.n 8002216 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002206: 68fb ldr r3, [r7, #12] 8002208: 681b ldr r3, [r3, #0] 800220a: 681a ldr r2, [r3, #0] 800220c: 68fb ldr r3, [r7, #12] 800220e: 681b ldr r3, [r3, #0] 8002210: f442 7200 orr.w r2, r2, #512 ; 0x200 8002214: 601a str r2, [r3, #0] } return HAL_ERROR; 8002216: 2301 movs r3, #1 8002218: e06b b.n 80022f2 } /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 800221a: 68fb ldr r3, [r7, #12] 800221c: 6a5b ldr r3, [r3, #36] ; 0x24 800221e: 781a ldrb r2, [r3, #0] 8002220: 68fb ldr r3, [r7, #12] 8002222: 681b ldr r3, [r3, #0] 8002224: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002226: 68fb ldr r3, [r7, #12] 8002228: 6a5b ldr r3, [r3, #36] ; 0x24 800222a: 1c5a adds r2, r3, #1 800222c: 68fb ldr r3, [r7, #12] 800222e: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002230: 68fb ldr r3, [r7, #12] 8002232: 8d1b ldrh r3, [r3, #40] ; 0x28 8002234: 3b01 subs r3, #1 8002236: b29a uxth r2, r3 8002238: 68fb ldr r3, [r7, #12] 800223a: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800223c: 68fb ldr r3, [r7, #12] 800223e: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002240: b29b uxth r3, r3 8002242: 3b01 subs r3, #1 8002244: b29a uxth r2, r3 8002246: 68fb ldr r3, [r7, #12] 8002248: 855a strh r2, [r3, #42] ; 0x2a if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 800224a: 68fb ldr r3, [r7, #12] 800224c: 681b ldr r3, [r3, #0] 800224e: 695b ldr r3, [r3, #20] 8002250: f003 0304 and.w r3, r3, #4 8002254: 2b04 cmp r3, #4 8002256: d11b bne.n 8002290 8002258: 68fb ldr r3, [r7, #12] 800225a: 8d1b ldrh r3, [r3, #40] ; 0x28 800225c: 2b00 cmp r3, #0 800225e: d017 beq.n 8002290 { /* Write data to DR */ hi2c->Instance->DR = *hi2c->pBuffPtr; 8002260: 68fb ldr r3, [r7, #12] 8002262: 6a5b ldr r3, [r3, #36] ; 0x24 8002264: 781a ldrb r2, [r3, #0] 8002266: 68fb ldr r3, [r7, #12] 8002268: 681b ldr r3, [r3, #0] 800226a: 611a str r2, [r3, #16] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800226c: 68fb ldr r3, [r7, #12] 800226e: 6a5b ldr r3, [r3, #36] ; 0x24 8002270: 1c5a adds r2, r3, #1 8002272: 68fb ldr r3, [r7, #12] 8002274: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002276: 68fb ldr r3, [r7, #12] 8002278: 8d1b ldrh r3, [r3, #40] ; 0x28 800227a: 3b01 subs r3, #1 800227c: b29a uxth r2, r3 800227e: 68fb ldr r3, [r7, #12] 8002280: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002282: 68fb ldr r3, [r7, #12] 8002284: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002286: b29b uxth r3, r3 8002288: 3b01 subs r3, #1 800228a: b29a uxth r2, r3 800228c: 68fb ldr r3, [r7, #12] 800228e: 855a strh r2, [r3, #42] ; 0x2a while (hi2c->XferSize > 0U) 8002290: 68fb ldr r3, [r7, #12] 8002292: 8d1b ldrh r3, [r3, #40] ; 0x28 8002294: 2b00 cmp r3, #0 8002296: d1aa bne.n 80021ee } } /* Wait until BTF flag is set */ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8002298: 697a ldr r2, [r7, #20] 800229a: 6ab9 ldr r1, [r7, #40] ; 0x28 800229c: 68f8 ldr r0, [r7, #12] 800229e: f000 fd2e bl 8002cfe 80022a2: 4603 mov r3, r0 80022a4: 2b00 cmp r3, #0 80022a6: d00d beq.n 80022c4 { if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 80022a8: 68fb ldr r3, [r7, #12] 80022aa: 6c1b ldr r3, [r3, #64] ; 0x40 80022ac: 2b04 cmp r3, #4 80022ae: d107 bne.n 80022c0 { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80022b0: 68fb ldr r3, [r7, #12] 80022b2: 681b ldr r3, [r3, #0] 80022b4: 681a ldr r2, [r3, #0] 80022b6: 68fb ldr r3, [r7, #12] 80022b8: 681b ldr r3, [r3, #0] 80022ba: f442 7200 orr.w r2, r2, #512 ; 0x200 80022be: 601a str r2, [r3, #0] } return HAL_ERROR; 80022c0: 2301 movs r3, #1 80022c2: e016 b.n 80022f2 } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 80022c4: 68fb ldr r3, [r7, #12] 80022c6: 681b ldr r3, [r3, #0] 80022c8: 681a ldr r2, [r3, #0] 80022ca: 68fb ldr r3, [r7, #12] 80022cc: 681b ldr r3, [r3, #0] 80022ce: f442 7200 orr.w r2, r2, #512 ; 0x200 80022d2: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80022d4: 68fb ldr r3, [r7, #12] 80022d6: 2220 movs r2, #32 80022d8: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 80022dc: 68fb ldr r3, [r7, #12] 80022de: 2200 movs r2, #0 80022e0: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80022e4: 68fb ldr r3, [r7, #12] 80022e6: 2200 movs r2, #0 80022e8: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80022ec: 2300 movs r3, #0 80022ee: e000 b.n 80022f2 } else { return HAL_BUSY; 80022f0: 2302 movs r3, #2 } } 80022f2: 4618 mov r0, r3 80022f4: 3718 adds r7, #24 80022f6: 46bd mov sp, r7 80022f8: bd80 pop {r7, pc} 80022fa: bf00 nop 80022fc: 00100002 .word 0x00100002 8002300: ffff0000 .word 0xffff0000 08002304 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8002304: b580 push {r7, lr} 8002306: b08c sub sp, #48 ; 0x30 8002308: af02 add r7, sp, #8 800230a: 60f8 str r0, [r7, #12] 800230c: 4608 mov r0, r1 800230e: 4611 mov r1, r2 8002310: 461a mov r2, r3 8002312: 4603 mov r3, r0 8002314: 817b strh r3, [r7, #10] 8002316: 460b mov r3, r1 8002318: 813b strh r3, [r7, #8] 800231a: 4613 mov r3, r2 800231c: 80fb strh r3, [r7, #6] __IO uint32_t count = 0U; 800231e: 2300 movs r3, #0 8002320: 623b str r3, [r7, #32] /* Init tickstart for timeout management*/ uint32_t tickstart = HAL_GetTick(); 8002322: f7ff fadb bl 80018dc 8002326: 6278 str r0, [r7, #36] ; 0x24 /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8002328: 68fb ldr r3, [r7, #12] 800232a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 800232e: b2db uxtb r3, r3 8002330: 2b20 cmp r3, #32 8002332: f040 8244 bne.w 80027be { /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 8002336: 6a7b ldr r3, [r7, #36] ; 0x24 8002338: 9300 str r3, [sp, #0] 800233a: 2319 movs r3, #25 800233c: 2201 movs r2, #1 800233e: 4982 ldr r1, [pc, #520] ; (8002548 ) 8002340: 68f8 ldr r0, [r7, #12] 8002342: f000 fbc5 bl 8002ad0 8002346: 4603 mov r3, r0 8002348: 2b00 cmp r3, #0 800234a: d001 beq.n 8002350 { return HAL_BUSY; 800234c: 2302 movs r3, #2 800234e: e237 b.n 80027c0 } /* Process Locked */ __HAL_LOCK(hi2c); 8002350: 68fb ldr r3, [r7, #12] 8002352: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002356: 2b01 cmp r3, #1 8002358: d101 bne.n 800235e 800235a: 2302 movs r3, #2 800235c: e230 b.n 80027c0 800235e: 68fb ldr r3, [r7, #12] 8002360: 2201 movs r2, #1 8002362: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check if the I2C is already enabled */ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 8002366: 68fb ldr r3, [r7, #12] 8002368: 681b ldr r3, [r3, #0] 800236a: 681b ldr r3, [r3, #0] 800236c: f003 0301 and.w r3, r3, #1 8002370: 2b01 cmp r3, #1 8002372: d007 beq.n 8002384 { /* Enable I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002374: 68fb ldr r3, [r7, #12] 8002376: 681b ldr r3, [r3, #0] 8002378: 681a ldr r2, [r3, #0] 800237a: 68fb ldr r3, [r7, #12] 800237c: 681b ldr r3, [r3, #0] 800237e: f042 0201 orr.w r2, r2, #1 8002382: 601a str r2, [r3, #0] } /* Disable Pos */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8002384: 68fb ldr r3, [r7, #12] 8002386: 681b ldr r3, [r3, #0] 8002388: 681a ldr r2, [r3, #0] 800238a: 68fb ldr r3, [r7, #12] 800238c: 681b ldr r3, [r3, #0] 800238e: f422 6200 bic.w r2, r2, #2048 ; 0x800 8002392: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_BUSY_RX; 8002394: 68fb ldr r3, [r7, #12] 8002396: 2222 movs r2, #34 ; 0x22 8002398: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_MEM; 800239c: 68fb ldr r3, [r7, #12] 800239e: 2240 movs r2, #64 ; 0x40 80023a0: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80023a4: 68fb ldr r3, [r7, #12] 80023a6: 2200 movs r2, #0 80023a8: 641a str r2, [r3, #64] ; 0x40 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 80023aa: 68fb ldr r3, [r7, #12] 80023ac: 6b3a ldr r2, [r7, #48] ; 0x30 80023ae: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 80023b0: 68fb ldr r3, [r7, #12] 80023b2: 8eba ldrh r2, [r7, #52] ; 0x34 80023b4: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize = hi2c->XferCount; 80023b6: 68fb ldr r3, [r7, #12] 80023b8: 8d5b ldrh r3, [r3, #42] ; 0x2a 80023ba: b29a uxth r2, r3 80023bc: 68fb ldr r3, [r7, #12] 80023be: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80023c0: 68fb ldr r3, [r7, #12] 80023c2: 4a62 ldr r2, [pc, #392] ; (800254c ) 80023c4: 62da str r2, [r3, #44] ; 0x2c /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 80023c6: 88f8 ldrh r0, [r7, #6] 80023c8: 893a ldrh r2, [r7, #8] 80023ca: 8979 ldrh r1, [r7, #10] 80023cc: 6a7b ldr r3, [r7, #36] ; 0x24 80023ce: 9301 str r3, [sp, #4] 80023d0: 6bbb ldr r3, [r7, #56] ; 0x38 80023d2: 9300 str r3, [sp, #0] 80023d4: 4603 mov r3, r0 80023d6: 68f8 ldr r0, [r7, #12] 80023d8: f000 fa92 bl 8002900 80023dc: 4603 mov r3, r0 80023de: 2b00 cmp r3, #0 80023e0: d001 beq.n 80023e6 { return HAL_ERROR; 80023e2: 2301 movs r3, #1 80023e4: e1ec b.n 80027c0 } if (hi2c->XferSize == 0U) 80023e6: 68fb ldr r3, [r7, #12] 80023e8: 8d1b ldrh r3, [r3, #40] ; 0x28 80023ea: 2b00 cmp r3, #0 80023ec: d113 bne.n 8002416 { /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 80023ee: 2300 movs r3, #0 80023f0: 61fb str r3, [r7, #28] 80023f2: 68fb ldr r3, [r7, #12] 80023f4: 681b ldr r3, [r3, #0] 80023f6: 695b ldr r3, [r3, #20] 80023f8: 61fb str r3, [r7, #28] 80023fa: 68fb ldr r3, [r7, #12] 80023fc: 681b ldr r3, [r3, #0] 80023fe: 699b ldr r3, [r3, #24] 8002400: 61fb str r3, [r7, #28] 8002402: 69fb ldr r3, [r7, #28] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002404: 68fb ldr r3, [r7, #12] 8002406: 681b ldr r3, [r3, #0] 8002408: 681a ldr r2, [r3, #0] 800240a: 68fb ldr r3, [r7, #12] 800240c: 681b ldr r3, [r3, #0] 800240e: f442 7200 orr.w r2, r2, #512 ; 0x200 8002412: 601a str r2, [r3, #0] 8002414: e1c0 b.n 8002798 } else if (hi2c->XferSize == 1U) 8002416: 68fb ldr r3, [r7, #12] 8002418: 8d1b ldrh r3, [r3, #40] ; 0x28 800241a: 2b01 cmp r3, #1 800241c: d11e bne.n 800245c { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 800241e: 68fb ldr r3, [r7, #12] 8002420: 681b ldr r3, [r3, #0] 8002422: 681a ldr r2, [r3, #0] 8002424: 68fb ldr r3, [r7, #12] 8002426: 681b ldr r3, [r3, #0] 8002428: f422 6280 bic.w r2, r2, #1024 ; 0x400 800242c: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 800242e: b672 cpsid i } 8002430: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8002432: 2300 movs r3, #0 8002434: 61bb str r3, [r7, #24] 8002436: 68fb ldr r3, [r7, #12] 8002438: 681b ldr r3, [r3, #0] 800243a: 695b ldr r3, [r3, #20] 800243c: 61bb str r3, [r7, #24] 800243e: 68fb ldr r3, [r7, #12] 8002440: 681b ldr r3, [r3, #0] 8002442: 699b ldr r3, [r3, #24] 8002444: 61bb str r3, [r7, #24] 8002446: 69bb ldr r3, [r7, #24] /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002448: 68fb ldr r3, [r7, #12] 800244a: 681b ldr r3, [r3, #0] 800244c: 681a ldr r2, [r3, #0] 800244e: 68fb ldr r3, [r7, #12] 8002450: 681b ldr r3, [r3, #0] 8002452: f442 7200 orr.w r2, r2, #512 ; 0x200 8002456: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8002458: b662 cpsie i } 800245a: e035 b.n 80024c8 /* Re-enable IRQs */ __enable_irq(); } else if (hi2c->XferSize == 2U) 800245c: 68fb ldr r3, [r7, #12] 800245e: 8d1b ldrh r3, [r3, #40] ; 0x28 8002460: 2b02 cmp r3, #2 8002462: d11e bne.n 80024a2 { /* Enable Pos */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 8002464: 68fb ldr r3, [r7, #12] 8002466: 681b ldr r3, [r3, #0] 8002468: 681a ldr r2, [r3, #0] 800246a: 68fb ldr r3, [r7, #12] 800246c: 681b ldr r3, [r3, #0] 800246e: f442 6200 orr.w r2, r2, #2048 ; 0x800 8002472: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 8002474: b672 cpsid i } 8002476: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 8002478: 2300 movs r3, #0 800247a: 617b str r3, [r7, #20] 800247c: 68fb ldr r3, [r7, #12] 800247e: 681b ldr r3, [r3, #0] 8002480: 695b ldr r3, [r3, #20] 8002482: 617b str r3, [r7, #20] 8002484: 68fb ldr r3, [r7, #12] 8002486: 681b ldr r3, [r3, #0] 8002488: 699b ldr r3, [r3, #24] 800248a: 617b str r3, [r7, #20] 800248c: 697b ldr r3, [r7, #20] /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 800248e: 68fb ldr r3, [r7, #12] 8002490: 681b ldr r3, [r3, #0] 8002492: 681a ldr r2, [r3, #0] 8002494: 68fb ldr r3, [r7, #12] 8002496: 681b ldr r3, [r3, #0] 8002498: f422 6280 bic.w r2, r2, #1024 ; 0x400 800249c: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 800249e: b662 cpsie i } 80024a0: e012 b.n 80024c8 __enable_irq(); } else { /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80024a2: 68fb ldr r3, [r7, #12] 80024a4: 681b ldr r3, [r3, #0] 80024a6: 681a ldr r2, [r3, #0] 80024a8: 68fb ldr r3, [r7, #12] 80024aa: 681b ldr r3, [r3, #0] 80024ac: f442 6280 orr.w r2, r2, #1024 ; 0x400 80024b0: 601a str r2, [r3, #0] /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 80024b2: 2300 movs r3, #0 80024b4: 613b str r3, [r7, #16] 80024b6: 68fb ldr r3, [r7, #12] 80024b8: 681b ldr r3, [r3, #0] 80024ba: 695b ldr r3, [r3, #20] 80024bc: 613b str r3, [r7, #16] 80024be: 68fb ldr r3, [r7, #12] 80024c0: 681b ldr r3, [r3, #0] 80024c2: 699b ldr r3, [r3, #24] 80024c4: 613b str r3, [r7, #16] 80024c6: 693b ldr r3, [r7, #16] } while (hi2c->XferSize > 0U) 80024c8: e166 b.n 8002798 { if (hi2c->XferSize <= 3U) 80024ca: 68fb ldr r3, [r7, #12] 80024cc: 8d1b ldrh r3, [r3, #40] ; 0x28 80024ce: 2b03 cmp r3, #3 80024d0: f200 811f bhi.w 8002712 { /* One byte */ if (hi2c->XferSize == 1U) 80024d4: 68fb ldr r3, [r7, #12] 80024d6: 8d1b ldrh r3, [r3, #40] ; 0x28 80024d8: 2b01 cmp r3, #1 80024da: d123 bne.n 8002524 { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80024dc: 6a7a ldr r2, [r7, #36] ; 0x24 80024de: 6bb9 ldr r1, [r7, #56] ; 0x38 80024e0: 68f8 ldr r0, [r7, #12] 80024e2: f000 fc4d bl 8002d80 80024e6: 4603 mov r3, r0 80024e8: 2b00 cmp r3, #0 80024ea: d001 beq.n 80024f0 { return HAL_ERROR; 80024ec: 2301 movs r3, #1 80024ee: e167 b.n 80027c0 } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80024f0: 68fb ldr r3, [r7, #12] 80024f2: 681b ldr r3, [r3, #0] 80024f4: 691a ldr r2, [r3, #16] 80024f6: 68fb ldr r3, [r7, #12] 80024f8: 6a5b ldr r3, [r3, #36] ; 0x24 80024fa: b2d2 uxtb r2, r2 80024fc: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80024fe: 68fb ldr r3, [r7, #12] 8002500: 6a5b ldr r3, [r3, #36] ; 0x24 8002502: 1c5a adds r2, r3, #1 8002504: 68fb ldr r3, [r7, #12] 8002506: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002508: 68fb ldr r3, [r7, #12] 800250a: 8d1b ldrh r3, [r3, #40] ; 0x28 800250c: 3b01 subs r3, #1 800250e: b29a uxth r2, r3 8002510: 68fb ldr r3, [r7, #12] 8002512: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002514: 68fb ldr r3, [r7, #12] 8002516: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002518: b29b uxth r3, r3 800251a: 3b01 subs r3, #1 800251c: b29a uxth r2, r3 800251e: 68fb ldr r3, [r7, #12] 8002520: 855a strh r2, [r3, #42] ; 0x2a 8002522: e139 b.n 8002798 } /* Two bytes */ else if (hi2c->XferSize == 2U) 8002524: 68fb ldr r3, [r7, #12] 8002526: 8d1b ldrh r3, [r3, #40] ; 0x28 8002528: 2b02 cmp r3, #2 800252a: d152 bne.n 80025d2 { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 800252c: 6a7b ldr r3, [r7, #36] ; 0x24 800252e: 9300 str r3, [sp, #0] 8002530: 6bbb ldr r3, [r7, #56] ; 0x38 8002532: 2200 movs r2, #0 8002534: 4906 ldr r1, [pc, #24] ; (8002550 ) 8002536: 68f8 ldr r0, [r7, #12] 8002538: f000 faca bl 8002ad0 800253c: 4603 mov r3, r0 800253e: 2b00 cmp r3, #0 8002540: d008 beq.n 8002554 { return HAL_ERROR; 8002542: 2301 movs r3, #1 8002544: e13c b.n 80027c0 8002546: bf00 nop 8002548: 00100002 .word 0x00100002 800254c: ffff0000 .word 0xffff0000 8002550: 00010004 .word 0x00010004 __ASM volatile ("cpsid i" : : : "memory"); 8002554: b672 cpsid i } 8002556: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002558: 68fb ldr r3, [r7, #12] 800255a: 681b ldr r3, [r3, #0] 800255c: 681a ldr r2, [r3, #0] 800255e: 68fb ldr r3, [r7, #12] 8002560: 681b ldr r3, [r3, #0] 8002562: f442 7200 orr.w r2, r2, #512 ; 0x200 8002566: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002568: 68fb ldr r3, [r7, #12] 800256a: 681b ldr r3, [r3, #0] 800256c: 691a ldr r2, [r3, #16] 800256e: 68fb ldr r3, [r7, #12] 8002570: 6a5b ldr r3, [r3, #36] ; 0x24 8002572: b2d2 uxtb r2, r2 8002574: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002576: 68fb ldr r3, [r7, #12] 8002578: 6a5b ldr r3, [r3, #36] ; 0x24 800257a: 1c5a adds r2, r3, #1 800257c: 68fb ldr r3, [r7, #12] 800257e: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002580: 68fb ldr r3, [r7, #12] 8002582: 8d1b ldrh r3, [r3, #40] ; 0x28 8002584: 3b01 subs r3, #1 8002586: b29a uxth r2, r3 8002588: 68fb ldr r3, [r7, #12] 800258a: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 800258c: 68fb ldr r3, [r7, #12] 800258e: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002590: b29b uxth r3, r3 8002592: 3b01 subs r3, #1 8002594: b29a uxth r2, r3 8002596: 68fb ldr r3, [r7, #12] 8002598: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 800259a: b662 cpsie i } 800259c: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 800259e: 68fb ldr r3, [r7, #12] 80025a0: 681b ldr r3, [r3, #0] 80025a2: 691a ldr r2, [r3, #16] 80025a4: 68fb ldr r3, [r7, #12] 80025a6: 6a5b ldr r3, [r3, #36] ; 0x24 80025a8: b2d2 uxtb r2, r2 80025aa: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80025ac: 68fb ldr r3, [r7, #12] 80025ae: 6a5b ldr r3, [r3, #36] ; 0x24 80025b0: 1c5a adds r2, r3, #1 80025b2: 68fb ldr r3, [r7, #12] 80025b4: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80025b6: 68fb ldr r3, [r7, #12] 80025b8: 8d1b ldrh r3, [r3, #40] ; 0x28 80025ba: 3b01 subs r3, #1 80025bc: b29a uxth r2, r3 80025be: 68fb ldr r3, [r7, #12] 80025c0: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80025c2: 68fb ldr r3, [r7, #12] 80025c4: 8d5b ldrh r3, [r3, #42] ; 0x2a 80025c6: b29b uxth r3, r3 80025c8: 3b01 subs r3, #1 80025ca: b29a uxth r2, r3 80025cc: 68fb ldr r3, [r7, #12] 80025ce: 855a strh r2, [r3, #42] ; 0x2a 80025d0: e0e2 b.n 8002798 } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 80025d2: 6a7b ldr r3, [r7, #36] ; 0x24 80025d4: 9300 str r3, [sp, #0] 80025d6: 6bbb ldr r3, [r7, #56] ; 0x38 80025d8: 2200 movs r2, #0 80025da: 497b ldr r1, [pc, #492] ; (80027c8 ) 80025dc: 68f8 ldr r0, [r7, #12] 80025de: f000 fa77 bl 8002ad0 80025e2: 4603 mov r3, r0 80025e4: 2b00 cmp r3, #0 80025e6: d001 beq.n 80025ec { return HAL_ERROR; 80025e8: 2301 movs r3, #1 80025ea: e0e9 b.n 80027c0 } /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 80025ec: 68fb ldr r3, [r7, #12] 80025ee: 681b ldr r3, [r3, #0] 80025f0: 681a ldr r2, [r3, #0] 80025f2: 68fb ldr r3, [r7, #12] 80025f4: 681b ldr r3, [r3, #0] 80025f6: f422 6280 bic.w r2, r2, #1024 ; 0x400 80025fa: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 80025fc: b672 cpsid i } 80025fe: bf00 nop /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 8002600: 68fb ldr r3, [r7, #12] 8002602: 681b ldr r3, [r3, #0] 8002604: 691a ldr r2, [r3, #16] 8002606: 68fb ldr r3, [r7, #12] 8002608: 6a5b ldr r3, [r3, #36] ; 0x24 800260a: b2d2 uxtb r2, r2 800260c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800260e: 68fb ldr r3, [r7, #12] 8002610: 6a5b ldr r3, [r3, #36] ; 0x24 8002612: 1c5a adds r2, r3, #1 8002614: 68fb ldr r3, [r7, #12] 8002616: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 8002618: 68fb ldr r3, [r7, #12] 800261a: 8d1b ldrh r3, [r3, #40] ; 0x28 800261c: 3b01 subs r3, #1 800261e: b29a uxth r2, r3 8002620: 68fb ldr r3, [r7, #12] 8002622: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002624: 68fb ldr r3, [r7, #12] 8002626: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002628: b29b uxth r3, r3 800262a: 3b01 subs r3, #1 800262c: b29a uxth r2, r3 800262e: 68fb ldr r3, [r7, #12] 8002630: 855a strh r2, [r3, #42] ; 0x2a /* Wait until BTF flag is set */ count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 8002632: 4b66 ldr r3, [pc, #408] ; (80027cc ) 8002634: 681b ldr r3, [r3, #0] 8002636: 08db lsrs r3, r3, #3 8002638: 4a65 ldr r2, [pc, #404] ; (80027d0 ) 800263a: fba2 2303 umull r2, r3, r2, r3 800263e: 0a1a lsrs r2, r3, #8 8002640: 4613 mov r3, r2 8002642: 009b lsls r3, r3, #2 8002644: 4413 add r3, r2 8002646: 00da lsls r2, r3, #3 8002648: 1ad3 subs r3, r2, r3 800264a: 623b str r3, [r7, #32] do { count--; 800264c: 6a3b ldr r3, [r7, #32] 800264e: 3b01 subs r3, #1 8002650: 623b str r3, [r7, #32] if (count == 0U) 8002652: 6a3b ldr r3, [r7, #32] 8002654: 2b00 cmp r3, #0 8002656: d118 bne.n 800268a { hi2c->PreviousState = I2C_STATE_NONE; 8002658: 68fb ldr r3, [r7, #12] 800265a: 2200 movs r2, #0 800265c: 631a str r2, [r3, #48] ; 0x30 hi2c->State = HAL_I2C_STATE_READY; 800265e: 68fb ldr r3, [r7, #12] 8002660: 2220 movs r2, #32 8002662: f883 203d strb.w r2, [r3, #61] ; 0x3d hi2c->Mode = HAL_I2C_MODE_NONE; 8002666: 68fb ldr r3, [r7, #12] 8002668: 2200 movs r2, #0 800266a: f883 203e strb.w r2, [r3, #62] ; 0x3e hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 800266e: 68fb ldr r3, [r7, #12] 8002670: 6c1b ldr r3, [r3, #64] ; 0x40 8002672: f043 0220 orr.w r2, r3, #32 8002676: 68fb ldr r3, [r7, #12] 8002678: 641a str r2, [r3, #64] ; 0x40 __ASM volatile ("cpsie i" : : : "memory"); 800267a: b662 cpsie i } 800267c: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800267e: 68fb ldr r3, [r7, #12] 8002680: 2200 movs r2, #0 8002682: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_ERROR; 8002686: 2301 movs r3, #1 8002688: e09a b.n 80027c0 } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 800268a: 68fb ldr r3, [r7, #12] 800268c: 681b ldr r3, [r3, #0] 800268e: 695b ldr r3, [r3, #20] 8002690: f003 0304 and.w r3, r3, #4 8002694: 2b04 cmp r3, #4 8002696: d1d9 bne.n 800264c /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 8002698: 68fb ldr r3, [r7, #12] 800269a: 681b ldr r3, [r3, #0] 800269c: 681a ldr r2, [r3, #0] 800269e: 68fb ldr r3, [r7, #12] 80026a0: 681b ldr r3, [r3, #0] 80026a2: f442 7200 orr.w r2, r2, #512 ; 0x200 80026a6: 601a str r2, [r3, #0] /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80026a8: 68fb ldr r3, [r7, #12] 80026aa: 681b ldr r3, [r3, #0] 80026ac: 691a ldr r2, [r3, #16] 80026ae: 68fb ldr r3, [r7, #12] 80026b0: 6a5b ldr r3, [r3, #36] ; 0x24 80026b2: b2d2 uxtb r2, r2 80026b4: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80026b6: 68fb ldr r3, [r7, #12] 80026b8: 6a5b ldr r3, [r3, #36] ; 0x24 80026ba: 1c5a adds r2, r3, #1 80026bc: 68fb ldr r3, [r7, #12] 80026be: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80026c0: 68fb ldr r3, [r7, #12] 80026c2: 8d1b ldrh r3, [r3, #40] ; 0x28 80026c4: 3b01 subs r3, #1 80026c6: b29a uxth r2, r3 80026c8: 68fb ldr r3, [r7, #12] 80026ca: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 80026cc: 68fb ldr r3, [r7, #12] 80026ce: 8d5b ldrh r3, [r3, #42] ; 0x2a 80026d0: b29b uxth r3, r3 80026d2: 3b01 subs r3, #1 80026d4: b29a uxth r2, r3 80026d6: 68fb ldr r3, [r7, #12] 80026d8: 855a strh r2, [r3, #42] ; 0x2a __ASM volatile ("cpsie i" : : : "memory"); 80026da: b662 cpsie i } 80026dc: bf00 nop /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 80026de: 68fb ldr r3, [r7, #12] 80026e0: 681b ldr r3, [r3, #0] 80026e2: 691a ldr r2, [r3, #16] 80026e4: 68fb ldr r3, [r7, #12] 80026e6: 6a5b ldr r3, [r3, #36] ; 0x24 80026e8: b2d2 uxtb r2, r2 80026ea: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80026ec: 68fb ldr r3, [r7, #12] 80026ee: 6a5b ldr r3, [r3, #36] ; 0x24 80026f0: 1c5a adds r2, r3, #1 80026f2: 68fb ldr r3, [r7, #12] 80026f4: 625a str r2, [r3, #36] ; 0x24 /* Update counter */ hi2c->XferSize--; 80026f6: 68fb ldr r3, [r7, #12] 80026f8: 8d1b ldrh r3, [r3, #40] ; 0x28 80026fa: 3b01 subs r3, #1 80026fc: b29a uxth r2, r3 80026fe: 68fb ldr r3, [r7, #12] 8002700: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8002702: 68fb ldr r3, [r7, #12] 8002704: 8d5b ldrh r3, [r3, #42] ; 0x2a 8002706: b29b uxth r3, r3 8002708: 3b01 subs r3, #1 800270a: b29a uxth r2, r3 800270c: 68fb ldr r3, [r7, #12] 800270e: 855a strh r2, [r3, #42] ; 0x2a 8002710: e042 b.n 8002798 } } else { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8002712: 6a7a ldr r2, [r7, #36] ; 0x24 8002714: 6bb9 ldr r1, [r7, #56] ; 0x38 8002716: 68f8 ldr r0, [r7, #12] 8002718: f000 fb32 bl 8002d80