cleanup rootdir by moving things into docs/bin

bin/build-all.sh

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+set -e
+
+VERSION=0.0.2
+
+rm .pio/build/esp32/firmware.bin
+export PLATFORMIO_BUILD_FLAGS="-DT_BEAM_V10 -DAPP_VERSION=$VERSION"
+pio run # -v
+cp .pio/build/esp32/firmware.bin release/firmware-TBEAM-US.bin
+
+rm .pio/build/esp32/firmware.bin
+export PLATFORMIO_BUILD_FLAGS="-DHELTEC_LORA32 -DAPP_VERSION=$VERSION"
+pio run # -v
+cp .pio/build/esp32/firmware.bin release/firmware-HELTEC-US.bin

bin/genpartitions.py

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+#!/usr/bin/python2
+
+# This is a layout for 4MB of flash
+# Name,   Type, SubType, Offset,  Size, Flags
+# nvs,      data, nvs,     0x9000,  0x6000,
+# otadata,  data, ota,     , 0x2000,
+# app0,     app,  ota_0,   , 0x1c0000,
+# app1,     app,  ota_1,   , 0x1c0000,
+# spiffs,   data, spiffs,  , 0x06f000,
+
+start = 0x9000
+nvssys = 0x3000
+nvsuser = 0x2000 # NOTE: ti seems total size of nvssys MUST be 0x5000 or device will bootloop
+nvs = nvssys + nvsuser
+ota = 0x2000
+# app = 0x1c0000
+spi = 128 * 1024
+
+# treat sys part sizes + spiffs size as reserved, then calculate what appsize can be
+reserved = start + nvs + ota + spi
+maxsize = 0x400000 # 4MB
+
+app = (maxsize - reserved) / 2
+
+# total = start + nvs + ota + 2 * app + spi
+
+nvskb = nvsuser / 1024
+spikb = spi / 1024
+appkb = app / 1024
+
+table = """
+# This is autogenerated by genpartions.py - change that tool instead!
+# appsize={appkb} KB, spiffs={spikb} KB, usernvs={nvskb} KB
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x{start:x},  0x{nvs:x},
+otadata,  data, ota,     , 0x{ota:x},
+app0,     app,  ota_0,   , 0x{app:x},
+app1,     app,  ota_1,   , 0x{app:x},
+spiffs,   data, spiffs,  , 0x{spi:x} """.format(**locals())
+
+print(table)

bin/lora32-openocd.cfg

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+# Example OpenOCD configuration file for ESP-WROOM-32 module.
+# By default, the following configuration is used:
+# - dual core debugging
+# - support for listing FreeRTOS tasks is enabled
+# - OpenOCD is configured to set SPI flash voltage at 3.3V
+#   by keeping MTDI bootstrapping pin low
+#
+# Use variables listed below to customize this.
+# Variables can be modified in this file or set on the command line.
+#
+# For example, OpenOCD can be started for single core ESP32 debugging on
+# ESP-WROVER-KIT with ESP-WROOM-32 module as follows:
+#
+#   openocd -f interface/ftdi/esp32_devkitj_v1.cfg -c 'set ESP32_ONLYCPU 1' -f board/esp-wroom-32.cfg
+#
+# If a different JTAG interface is used, change the first -f option.
+#
+# If OpenOCD is built from source, pass an additional -s option to specify
+# the location of 'tcl' directory:
+#
+#    src/openocd -s tcl <rest of the command line>
+#
+# Note:
+#   For ESP32-WROVER module use 'esp32-wrover.cfg' configuration file
+#   ESP-WROOM-32 and ESP32-WROVER have different flash voltage setting
+
+
+# The ESP32 only supports JTAG.
+transport select jtag
+
+# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they
+# do not relate to OpenOCD trying to read from a memory range without physical
+# memory being present there), you can try lowering this.
+#
+# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
+# if CPU frequency is 160MHz or 240MHz.
+adapter_khz 20000
+
+# If single core debugging is required, uncomment the following line
+# set ESP32_ONLYCPU 1
+
+# To disable RTOS support, uncomment the following line
+# set ESP32_RTOS none
+
+# Tell OpenOCD which SPI flash voltage is used by the board (3.3 or 1.8)
+# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash
+# chip runs at. When a hard reset happens (e.g. because someone switches the board off
+# and on) the ESP32 will use the current TDI value as the bootstrap value because the
+# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the
+# bootstrapping. These lines basically set the idle value of the TDI line to a
+# specified value, therefore reducing the chance of a bad bootup due to a bad flash
+# voltage greatly.
+# This option defaults to 3.3, if not set. To override the default, uncomment
+# the following line:
+# set ESP32_FLASH_VOLTAGE 1.8
+
+# Set semihosting I/O base dir
+# set ESP_SEMIHOST_BASEDIR ""
+
+# Source the ESP32 configuration file
+source [find target/esp32.cfg]

bin/regen-protos.sh

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+/home/kevinh/packages/nanopb-0.4.1-linux-x86/generator-bin/protoc --nanopb_out=-v:src -I=../MeshUtil/app/src/main/proto mesh.proto

bin/run-0-monitor.sh

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+pio run --upload-port /dev/ttyUSB0 -t upload -t monitor

bin/run-both-monitor.sh

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+set -e 
+
+echo uploading to usb1
+pio run --upload-port /dev/ttyUSB1 -t upload
+
+echo uploading to usb0
+pio run --upload-port /dev/ttyUSB0 -t upload -t monitor

bin/run-openocd.sh

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+
+
+# /home/kevinh/.platformio/packages/tool-openocd-esp32/bin/openocd -s /home/kevinh/.platformio/packages/tool-openocd-esp32 -c gdb_port pipe; tcl_port disabled; telnet_port disabled -s /home/kevinh/.platformio/packages/tool-openocd-esp32/share/openocd/scripts -f interface/jlink.cfg -f board/esp-wroom-32.cfg
+/home/kevinh/.platformio/packages/tool-openocd-esp32/bin/openocd -s /home/kevinh/.platformio/packages/tool-openocd-esp32 -s /home/kevinh/.platformio/packages/tool-openocd-esp32/share/openocd/scripts -f interface/jlink.cfg -f ./lora32-openocd.cfg
+

bin/start-terminal.sh

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+pio device monitor -b 115200

bin/upload-usb1.sh

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+pio run --upload-port /dev/ttyUSB1 -t upload