Merge remote-tracking branch 'origin/develop'

src/mesh/LR11x0Interface.cpp

@@ -263,6 +263,7 @@ template <typename T> void LR11x0Interface<T>::startReceive()
 
     // Must be done AFTER, starting transmit, because startTransmit clears (possibly stale) interrupt pending register bits
     enableInterrupt(isrRxLevel0);
+    checkRxDoneIrqFlag();
 #endif
 }
 

src/mesh/RF95Interface.cpp

@@ -301,6 +301,7 @@ void RF95Interface::startReceive()
 
     // Must be done AFTER, starting receive, because startReceive clears (possibly stale) interrupt pending register bits
     enableInterrupt(isrRxLevel0);
+    checkRxDoneIrqFlag();
 }
 
 bool RF95Interface::isChannelActive()

src/mesh/RadioLibInterface.cpp

@@ -517,12 +517,26 @@ void RadioLibInterface::handleReceiveInterrupt()
 
 void RadioLibInterface::startReceive()
 {
-    // Note the updated timestamp, to avoid unneeded AGC resets
-    last_listen = millis();
     isReceiving = true;
     powerMon->setState(meshtastic_PowerMon_State_Lora_RXOn);
 }
 
+void RadioLibInterface::pollMissedIrqs()
+{
+    // RadioLibInterface::enableInterrupt uses EDGE-TRIGGERED interrupts. Poll as a backup to catch missed edges.
+    if (isReceiving) {
+        checkRxDoneIrqFlag();
+    }
+}
+
+void RadioLibInterface::checkRxDoneIrqFlag()
+{
+    if (iface->checkIrq(RADIOLIB_IRQ_RX_DONE)) {
+        LOG_WARN("caught missed RX_DONE");
+        notify(ISR_RX, true);
+    }
+}
+
 void RadioLibInterface::configHardwareForSend()
 {
     powerMon->setState(meshtastic_PowerMon_State_Lora_TXOn);

src/mesh/RadioLibInterface.h

@@ -112,6 +112,11 @@ class RadioLibInterface : public RadioInterface, protected concurrency::Notified
      */
     virtual void enableInterrupt(void (*)()) = 0;
 
+    /**
+     * Poll as a backup to catch missed edge-triggered interrupts.
+     */
+    void pollMissedIrqs();
+
     /**
      * Debugging counts
      */
@@ -264,4 +269,6 @@ class RadioLibInterface : public RadioInterface, protected concurrency::Notified
      */
 
     bool removePendingTXPacket(NodeNum from, PacketId id, uint32_t hop_limit_lt) override;
+
+    void checkRxDoneIrqFlag();
 };

src/mesh/SX126xInterface.cpp

@@ -6,6 +6,10 @@
 #ifdef ARCH_PORTDUINO
 #include "PortduinoGlue.h"
 #endif
+#if defined(USE_GC1109_PA) && defined(ARCH_ESP32)
+#include <driver/rtc_io.h>
+#include <esp_sleep.h>
+#endif
 
 #include "Throttle.h"
 
@@ -55,14 +59,33 @@ template <typename T> bool SX126xInterface<T>::init()
 #if defined(USE_GC1109_PA)
     // GC1109 FEM chip initialization
     // See variant.h for full pin mapping and control logic documentation
+    //
+    // On deep sleep wake, PA_POWER and PA_EN are held HIGH by RTC latch (set in
+    // enableLoraInterrupt). We configure GPIO registers before releasing the hold
+    // so the pad transitions atomically from held-HIGH to register-HIGH with no
+    // power glitch. On cold boot the hold_dis is a harmless no-op.
 
     // VFEM_Ctrl (LORA_PA_POWER): Power enable for GC1109 LDO (always on)
     pinMode(LORA_PA_POWER, OUTPUT);
     digitalWrite(LORA_PA_POWER, HIGH);
+    rtc_gpio_hold_dis((gpio_num_t)LORA_PA_POWER);
+
+    // TLV75733P LDO has ~550us startup time (datasheet tSTR). On cold boot, wait
+    // for VBAT to stabilise before driving CSD/CPS, per GC1109 requirement:
+    // "VBAT must be prior to CSD/CPS/CTX for the power on sequence"
+    // On deep sleep wake the LDO was held on via RTC latch, so no delay needed.
+#if defined(ARCH_ESP32)
+    if (esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_UNDEFINED) {
+        delayMicroseconds(1000);
+    }
+#else
+    delayMicroseconds(1000);
+#endif
 
     // CSD (LORA_PA_EN): Chip enable - must be HIGH to enable GC1109 for both RX and TX
     pinMode(LORA_PA_EN, OUTPUT);
     digitalWrite(LORA_PA_EN, HIGH);
+    rtc_gpio_hold_dis((gpio_num_t)LORA_PA_EN);
 
     // CPS (LORA_PA_TX_EN): PA mode select - HIGH enables full PA during TX, LOW for RX (don't care)
     // Note: TX/RX path switching (CTX) is handled by DIO2 via SX126X_DIO2_AS_RF_SWITCH
@@ -171,6 +194,17 @@ template <typename T> bool SX126xInterface<T>::init()
         LOG_INFO("Set RX gain to power saving mode (boosted mode off); result: %d", result);
     }
 
+#ifdef USE_GC1109_PA
+    // Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity
+    // on boards with the GC1109 FEM. Sets bit 0 of register 0x8B5.
+    // Reference: https://github.com/meshcore-dev/MeshCore/pull/1398
+    if (module.SPIsetRegValue(0x8B5, 0x01, 0, 0) == RADIOLIB_ERR_NONE) {
+        LOG_INFO("Applied SX1262 register 0x8B5 patch for GC1109 RX improvement");
+    } else {
+        LOG_WARN("Failed to apply SX1262 register 0x8B5 patch for GC1109");
+    }
+#endif
+
 #if 0
     // Read/write a register we are not using (only used for FSK mode) to test SPI comms
     uint8_t crcLSB = 0;
@@ -328,6 +362,7 @@ template <typename T> void SX126xInterface<T>::startReceive()
 
     // Must be done AFTER, starting transmit, because startTransmit clears (possibly stale) interrupt pending register bits
     enableInterrupt(isrRxLevel0);
+    checkRxDoneIrqFlag();
 #endif
 }
 

src/mesh/SX128xInterface.cpp

@@ -271,6 +271,7 @@ template <typename T> void SX128xInterface<T>::startReceive()
 
     // Must be done AFTER, starting transmit, because startTransmit clears (possibly stale) interrupt pending register bits
     enableInterrupt(isrRxLevel0);
+    checkRxDoneIrqFlag();
 #endif
 }