5ced739a57
* Add heltec-v4.3 board * Modify LNA control display content * Fix Heltec Tracker v2 FEM control * Use trunk to fix formatting issues. * Optimize the fem initialization control logic. * Update src/mesh/RadioInterface.h change #ifdef to #if Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Change LORA_PA_EN to LORA_GC1109_PA_EN. Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Remove the NodeDB.h include. Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Change tx_gain to a const variable. Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Fixed the issue where ARCH_PORTDUINO lacked the NUM_PA_POINTS macro. * Remove the comment. Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Move #pragma once to the first line. * Remove the FEM LNA control menu. * Add description for KCT8103L. --------- Co-authored-by: Thomas Göttgens <tgoettgens@gmail.com> Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Ben Meadors <benmmeadors@gmail.com>
92 lines
4.1 KiB
C
92 lines
4.1 KiB
C
#define VEXT_ENABLE 36 // active low, powers the oled display and the lora antenna boost
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#define BUTTON_PIN 0
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#define ADC_CTRL 37
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#define ADC_CTRL_ENABLED HIGH
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#define BATTERY_PIN 1 // A battery voltage measurement pin, voltage divider connected here to measure battery voltage
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#define ADC_CHANNEL ADC1_GPIO1_CHANNEL
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#define ADC_ATTENUATION ADC_ATTEN_DB_2_5 // lower dB for high resistance voltage divider
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#define ADC_MULTIPLIER 4.9 * 1.045
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#define USE_SX1262
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#define LORA_DIO0 -1 // a No connect on the SX1262 module
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#define LORA_RESET 12
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#define LORA_DIO1 14 // SX1262 IRQ
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#define LORA_DIO2 13 // SX1262 BUSY
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#define LORA_DIO3 // Not connected on PCB, but internally on the TTGO SX1262, if DIO3 is high the TCXO is enabled
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#define LORA_SCK 9
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#define LORA_MISO 11
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#define LORA_MOSI 10
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#define LORA_CS 8
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#define SX126X_CS LORA_CS
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#define SX126X_DIO1 LORA_DIO1
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#define SX126X_BUSY LORA_DIO2
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#define SX126X_RESET LORA_RESET
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#define SX126X_DIO2_AS_RF_SWITCH
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#define SX126X_DIO3_TCXO_VOLTAGE 1.8
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// ---- GC1109 RF FRONT END CONFIGURATION ----
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// The Heltec V4.2 uses a GC1109 FEM chip with integrated PA and LNA
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// RF path: SX1262 -> Pi attenuator -> GC1109 PA -> Antenna
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// Measured net TX gain (non-linear due to PA compression):
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// +11dB at 0-15dBm input (e.g., 10dBm in -> 21dBm out)
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// +10dB at 16-17dBm input
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// +9dB at 18-19dBm input
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// +7dB at 21dBm input (e.g., 21dBm in -> 28dBm out max)
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// Control logic (from GC1109 datasheet):
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// Shutdown: CSD=0, CTX=X, CPS=X
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// Receive LNA: CSD=1, CTX=0, CPS=X (17dB gain, 2dB NF)
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// Transmit bypass: CSD=1, CTX=1, CPS=0 (~1dB loss, no PA)
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// Transmit PA: CSD=1, CTX=1, CPS=1 (full PA enabled)
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// Pin mapping:
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// CTX (pin 6) -> SX1262 DIO2: TX/RX path select (automatic via SX126X_DIO2_AS_RF_SWITCH)
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// CSD (pin 4) -> GPIO2: Chip enable (HIGH=on, LOW=shutdown)
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// CPS (pin 5) -> GPIO46: PA mode select (HIGH=full PA, LOW=bypass)
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// VCC0/VCC1 -> Vfem via U3 LDO, controlled by GPIO7
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// GC1109 FEM: TX/RX path switching is handled by DIO2 -> CTX pin (via SX126X_DIO2_AS_RF_SWITCH)
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// Do NOT use SX126X_TXEN/RXEN as that would cause double-control of GPIO46
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#define LORA_PA_POWER 7 // VFEM_Ctrl - GC1109 and KCT8103L LDO power enable
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#define LORA_GC1109_PA_EN 2 // CSD - GC1109 chip enable (HIGH=on)
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#define LORA_GC1109_PA_TX_EN 46 // CPS - GC1109 PA mode (HIGH=full PA, LOW=bypass)
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// ---- KCT8103L RF FRONT END CONFIGURATION ----
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// The Heltec V4.3 uses a KCT8103L FEM chip with integrated PA and LNA
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// RF path: SX1262 -> Pi attenuator -> KCT8103L PA -> Antenna
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// Control logic (from KCT8103L datasheet):
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// Transmit PA: CSD=1, CTX=1, CPS=1
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// Receive LNA: CSD=1, CTX=0, CPS=X (21dB gain, 1.9dB NF)
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// Receive bypass: CSD=1, CTX=1, CPS=0
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// Shutdown: CSD=0, CTX=X, CPS=X
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// Pin mapping:
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// CPS (pin 5) -> SX1262 DIO2: TX/RX path select (automatic via SX126X_DIO2_AS_RF_SWITCH)
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// CSD (pin 4) -> GPIO2: Chip enable (HIGH=on, LOW=shutdown)
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// CTX (pin 6) -> GPIO5: Switch between Receive LNA Mode and Receive Bypass Mode. (HIGH=bypass PA, LOW=LNA)
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// VCC0/VCC1 -> Vfem via U3 LDO, controlled by GPIO7
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// KCT8103L FEM: TX/RX path switching is handled by DIO2 -> CPS pin (via SX126X_DIO2_AS_RF_SWITCH)
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#define LORA_KCT8103L_PA_CSD 2 // CSD - KCT8103L chip enable (HIGH=on)
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#define LORA_KCT8103L_PA_CTX 5 // CTX - Switch between Receive LNA Mode and Receive Bypass Mode. (HIGH=bypass PA, LOW=LNA)
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#if HAS_TFT
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#define USE_TFTDISPLAY 1
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#endif
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/*
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* GPS pins
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*/
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#define GPS_L76K
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#define PIN_GPS_RESET (42) // An output to reset L76K GPS. As per datasheet, low for > 100ms will reset the L76K
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#define GPS_RESET_MODE LOW
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#define PIN_GPS_EN (34)
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#define GPS_EN_ACTIVE LOW
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#define PERIPHERAL_WARMUP_MS 1000 // Make sure I2C QuickLink has stable power before continuing
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#define PIN_GPS_STANDBY (40) // An output to wake GPS, low means allow sleep, high means force wake
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#define PIN_GPS_PPS (41)
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// Seems to be missing on this new board
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#define GPS_TX_PIN (38) // This is for bits going TOWARDS the CPU
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#define GPS_RX_PIN (39) // This is for bits going TOWARDS the GPS
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#define GPS_THREAD_INTERVAL 50 |