diff --git a/Morse_code_PCB/Morse_code_PCB.kicad_prl b/Morse_code_PCB/Morse_code_PCB.kicad_prl
index 9a8a4b4..41ade6d 100644
--- a/Morse_code_PCB/Morse_code_PCB.kicad_prl
+++ b/Morse_code_PCB/Morse_code_PCB.kicad_prl
@@ -61,7 +61,7 @@
35,
36
],
- "visible_layers": "fffffff_ffffffff",
+ "visible_layers": "ffebfaa_7fffffff",
"zone_display_mode": 0
},
"meta": {
diff --git a/f103c8t6_HAL/.cproject b/f103c8t6_HAL/.cproject
new file mode 100644
index 0000000..a2b2e16
--- /dev/null
+++ b/f103c8t6_HAL/.cproject
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/f103c8t6_HAL/.mxproject b/f103c8t6_HAL/.mxproject
new file mode 100644
index 0000000..2bfefcc
--- /dev/null
+++ b/f103c8t6_HAL/.mxproject
@@ -0,0 +1,25 @@
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Inc/stm32f1xx_it.h
+HeaderFiles#1=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Inc/stm32f1xx_hal_conf.h
+HeaderFiles#2=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Src/stm32f1xx_it.c
+SourceFiles#1=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Src/stm32f1xx_hal_msp.c
+SourceFiles#2=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=C:/Users/wuwen/Desktop/morse_code_trainer/f103c8t6_HAL/Core/Src
+SourceFiles=;
+
+[PreviousLibFiles]
+LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core\Src\main.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;;;
+HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
diff --git a/stm32f103/.project b/f103c8t6_HAL/.project
similarity index 97%
rename from stm32f103/.project
rename to f103c8t6_HAL/.project
index e07da81..02bfb32 100644
--- a/stm32f103/.project
+++ b/f103c8t6_HAL/.project
@@ -1,6 +1,6 @@
- stm32f103
+ f103c8t6_HAL
@@ -20,9 +20,9 @@
com.st.stm32cube.ide.mcu.MCUProjectNature
- com.st.stm32cube.ide.mcu.MCUCubeProjectNature
org.eclipse.cdt.core.cnature
com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature
+ com.st.stm32cube.ide.mcu.MCUCubeProjectNature
com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
com.st.stm32cube.ide.mcu.MCURootProjectNature
diff --git a/stm32f103/.settings/language.settings.xml b/f103c8t6_HAL/.settings/language.settings.xml
similarity index 85%
rename from stm32f103/.settings/language.settings.xml
rename to f103c8t6_HAL/.settings/language.settings.xml
index a26121f..d3b4fb6 100644
--- a/stm32f103/.settings/language.settings.xml
+++ b/f103c8t6_HAL/.settings/language.settings.xml
@@ -1,24 +1,24 @@
-
+
+
-
+
+
diff --git a/f103c8t6_HAL/.settings/stm32cubeide.project.prefs b/f103c8t6_HAL/.settings/stm32cubeide.project.prefs
new file mode 100644
index 0000000..d990a46
--- /dev/null
+++ b/f103c8t6_HAL/.settings/stm32cubeide.project.prefs
@@ -0,0 +1,3 @@
+8DF89ED150041C4CBC7CB9A9CAA90856=E08A4A42B43BAA3E4C79F58D26E83ECC
+DC22A860405A8BF2F2C095E5B6529F12=3B1C4025B9BFE66495091C321A27C880
+eclipse.preferences.version=1
diff --git a/stm32f103/Core/Inc/main.h b/f103c8t6_HAL/Core/Inc/main.h
similarity index 76%
rename from stm32f103/Core/Inc/main.h
rename to f103c8t6_HAL/Core/Inc/main.h
index f79fdef..4d79c08 100644
--- a/stm32f103/Core/Inc/main.h
+++ b/f103c8t6_HAL/Core/Inc/main.h
@@ -1,71 +1,68 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file : main.h
- * @brief : Header for main.c file.
- * This file contains the common defines of the application.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2022 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2022 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2022 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2022 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved. :
+ 8000130: b508 push {r3, lr}
+ 8000132: 4b03 ldr r3, [pc, #12] ; (8000140 )
+ 8000134: b11b cbz r3, 800013e
+ 8000136: 4903 ldr r1, [pc, #12] ; (8000144 )
+ 8000138: 4803 ldr r0, [pc, #12] ; (8000148 )
+ 800013a: f3af 8000 nop.w
+ 800013e: bd08 pop {r3, pc}
+ 8000140: 00000000 .word 0x00000000
+ 8000144: 20000010 .word 0x20000010
+ 8000148: 08000df8 .word 0x08000df8
+
+0800014c :
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ 800014c: b580 push {r7, lr}
+ 800014e: af00 add r7, sp, #0
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ 8000150: f000 f8f8 bl 8000344
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+ 8000154: f000 f803 bl 800015e
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ 8000158: f000 f846 bl 80001e8
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ 800015c: e7fe b.n 800015c
+
+0800015e :
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 800015e: b580 push {r7, lr}
+ 8000160: b090 sub sp, #64 ; 0x40
+ 8000162: af00 add r7, sp, #0
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 8000164: f107 0318 add.w r3, r7, #24
+ 8000168: 2228 movs r2, #40 ; 0x28
+ 800016a: 2100 movs r1, #0
+ 800016c: 4618 mov r0, r3
+ 800016e: f000 fe3b bl 8000de8
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 8000172: 1d3b adds r3, r7, #4
+ 8000174: 2200 movs r2, #0
+ 8000176: 601a str r2, [r3, #0]
+ 8000178: 605a str r2, [r3, #4]
+ 800017a: 609a str r2, [r3, #8]
+ 800017c: 60da str r2, [r3, #12]
+ 800017e: 611a str r2, [r3, #16]
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ 8000180: 2301 movs r3, #1
+ 8000182: 61bb str r3, [r7, #24]
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 8000184: f44f 3380 mov.w r3, #65536 ; 0x10000
+ 8000188: 61fb str r3, [r7, #28]
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ 800018a: 2300 movs r3, #0
+ 800018c: 623b str r3, [r7, #32]
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ 800018e: 2301 movs r3, #1
+ 8000190: 62bb str r3, [r7, #40] ; 0x28
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 8000192: 2302 movs r3, #2
+ 8000194: 637b str r3, [r7, #52] ; 0x34
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 8000196: f44f 3380 mov.w r3, #65536 ; 0x10000
+ 800019a: 63bb str r3, [r7, #56] ; 0x38
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+ 800019c: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
+ 80001a0: 63fb str r3, [r7, #60] ; 0x3c
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 80001a2: f107 0318 add.w r3, r7, #24
+ 80001a6: 4618 mov r0, r3
+ 80001a8: f000 fa12 bl 80005d0
+ 80001ac: 4603 mov r3, r0
+ 80001ae: 2b00 cmp r3, #0
+ 80001b0: d001 beq.n 80001b6
+ {
+ Error_Handler();
+ 80001b2: f000 f83b bl 800022c
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 80001b6: 230f movs r3, #15
+ 80001b8: 607b str r3, [r7, #4]
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 80001ba: 2302 movs r3, #2
+ 80001bc: 60bb str r3, [r7, #8]
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 80001be: 2300 movs r3, #0
+ 80001c0: 60fb str r3, [r7, #12]
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ 80001c2: f44f 6380 mov.w r3, #1024 ; 0x400
+ 80001c6: 613b str r3, [r7, #16]
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 80001c8: 2300 movs r3, #0
+ 80001ca: 617b str r3, [r7, #20]
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ 80001cc: 1d3b adds r3, r7, #4
+ 80001ce: 2102 movs r1, #2
+ 80001d0: 4618 mov r0, r3
+ 80001d2: f000 fc7d bl 8000ad0
+ 80001d6: 4603 mov r3, r0
+ 80001d8: 2b00 cmp r3, #0
+ 80001da: d001 beq.n 80001e0
+ {
+ Error_Handler();
+ 80001dc: f000 f826 bl 800022c
+ }
+}
+ 80001e0: bf00 nop
+ 80001e2: 3740 adds r7, #64 ; 0x40
+ 80001e4: 46bd mov sp, r7
+ 80001e6: bd80 pop {r7, pc}
+
+080001e8 :
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ 80001e8: b480 push {r7}
+ 80001ea: b083 sub sp, #12
+ 80001ec: af00 add r7, sp, #0
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ 80001ee: 4b0e ldr r3, [pc, #56] ; (8000228 )
+ 80001f0: 699b ldr r3, [r3, #24]
+ 80001f2: 4a0d ldr r2, [pc, #52] ; (8000228 )
+ 80001f4: f043 0320 orr.w r3, r3, #32
+ 80001f8: 6193 str r3, [r2, #24]
+ 80001fa: 4b0b ldr r3, [pc, #44] ; (8000228 )
+ 80001fc: 699b ldr r3, [r3, #24]
+ 80001fe: f003 0320 and.w r3, r3, #32
+ 8000202: 607b str r3, [r7, #4]
+ 8000204: 687b ldr r3, [r7, #4]
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8000206: 4b08 ldr r3, [pc, #32] ; (8000228 )
+ 8000208: 699b ldr r3, [r3, #24]
+ 800020a: 4a07 ldr r2, [pc, #28] ; (8000228 )
+ 800020c: f043 0304 orr.w r3, r3, #4
+ 8000210: 6193 str r3, [r2, #24]
+ 8000212: 4b05 ldr r3, [pc, #20] ; (8000228 )
+ 8000214: 699b ldr r3, [r3, #24]
+ 8000216: f003 0304 and.w r3, r3, #4
+ 800021a: 603b str r3, [r7, #0]
+ 800021c: 683b ldr r3, [r7, #0]
+
+}
+ 800021e: bf00 nop
+ 8000220: 370c adds r7, #12
+ 8000222: 46bd mov sp, r7
+ 8000224: bc80 pop {r7}
+ 8000226: 4770 bx lr
+ 8000228: 40021000 .word 0x40021000
+
+0800022c :
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ 800022c: b480 push {r7}
+ 800022e: af00 add r7, sp, #0
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+ 8000230: b672 cpsid i
+}
+ 8000232: bf00 nop
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ 8000234: e7fe b.n 8000234
+ ...
+
+08000238 :
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ 8000238: b480 push {r7}
+ 800023a: b085 sub sp, #20
+ 800023c: af00 add r7, sp, #0
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_AFIO_CLK_ENABLE();
+ 800023e: 4b15 ldr r3, [pc, #84] ; (8000294 )
+ 8000240: 699b ldr r3, [r3, #24]
+ 8000242: 4a14 ldr r2, [pc, #80] ; (8000294 )
+ 8000244: f043 0301 orr.w r3, r3, #1
+ 8000248: 6193 str r3, [r2, #24]
+ 800024a: 4b12 ldr r3, [pc, #72] ; (8000294 )
+ 800024c: 699b ldr r3, [r3, #24]
+ 800024e: f003 0301 and.w r3, r3, #1
+ 8000252: 60bb str r3, [r7, #8]
+ 8000254: 68bb ldr r3, [r7, #8]
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8000256: 4b0f ldr r3, [pc, #60] ; (8000294 )
+ 8000258: 69db ldr r3, [r3, #28]
+ 800025a: 4a0e ldr r2, [pc, #56] ; (8000294 )
+ 800025c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000260: 61d3 str r3, [r2, #28]
+ 8000262: 4b0c ldr r3, [pc, #48] ; (8000294 )
+ 8000264: 69db ldr r3, [r3, #28]
+ 8000266: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 800026a: 607b str r3, [r7, #4]
+ 800026c: 687b ldr r3, [r7, #4]
+
+ /* System interrupt init*/
+
+ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ */
+ __HAL_AFIO_REMAP_SWJ_NOJTAG();
+ 800026e: 4b0a ldr r3, [pc, #40] ; (8000298 )
+ 8000270: 685b ldr r3, [r3, #4]
+ 8000272: 60fb str r3, [r7, #12]
+ 8000274: 68fb ldr r3, [r7, #12]
+ 8000276: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
+ 800027a: 60fb str r3, [r7, #12]
+ 800027c: 68fb ldr r3, [r7, #12]
+ 800027e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
+ 8000282: 60fb str r3, [r7, #12]
+ 8000284: 4a04 ldr r2, [pc, #16] ; (8000298 )
+ 8000286: 68fb ldr r3, [r7, #12]
+ 8000288: 6053 str r3, [r2, #4]
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+ 800028a: bf00 nop
+ 800028c: 3714 adds r7, #20
+ 800028e: 46bd mov sp, r7
+ 8000290: bc80 pop {r7}
+ 8000292: 4770 bx lr
+ 8000294: 40021000 .word 0x40021000
+ 8000298: 40010000 .word 0x40010000
+
+0800029c :
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ 800029c: b480 push {r7}
+ 800029e: af00 add r7, sp, #0
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ 80002a0: e7fe b.n 80002a0
+
+080002a2 :
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ 80002a2: b480 push {r7}
+ 80002a4: af00 add r7, sp, #0
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 80002a6: e7fe b.n 80002a6
+
+080002a8 :
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ 80002a8: b480 push {r7}
+ 80002aa: af00 add r7, sp, #0
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ 80002ac: e7fe b.n 80002ac
+
+080002ae :
+
+/**
+ * @brief This function handles Prefetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ 80002ae: b480 push {r7}
+ 80002b0: af00 add r7, sp, #0
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ 80002b2: e7fe b.n 80002b2
+
+080002b4 :
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ 80002b4: b480 push {r7}
+ 80002b6: af00 add r7, sp, #0
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ 80002b8: e7fe b.n 80002b8
+
+080002ba :
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ 80002ba: b480 push {r7}
+ 80002bc: af00 add r7, sp, #0
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+ 80002be: bf00 nop
+ 80002c0: 46bd mov sp, r7
+ 80002c2: bc80 pop {r7}
+ 80002c4: 4770 bx lr
+
+080002c6 :
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ 80002c6: b480 push {r7}
+ 80002c8: af00 add r7, sp, #0
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+ 80002ca: bf00 nop
+ 80002cc: 46bd mov sp, r7
+ 80002ce: bc80 pop {r7}
+ 80002d0: 4770 bx lr
+
+080002d2 :
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ 80002d2: b480 push {r7}
+ 80002d4: af00 add r7, sp, #0
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+ 80002d6: bf00 nop
+ 80002d8: 46bd mov sp, r7
+ 80002da: bc80 pop {r7}
+ 80002dc: 4770 bx lr
+
+080002de :
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ 80002de: b580 push {r7, lr}
+ 80002e0: af00 add r7, sp, #0
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ 80002e2: f000 f875 bl 80003d0
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+ 80002e6: bf00 nop
+ 80002e8: bd80 pop {r7, pc}
+
+080002ea :
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ 80002ea: b480 push {r7}
+ 80002ec: af00 add r7, sp, #0
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+ 80002ee: bf00 nop
+ 80002f0: 46bd mov sp, r7
+ 80002f2: bc80 pop {r7}
+ 80002f4: 4770 bx lr
+ ...
+
+080002f8 :
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ 80002f8: 480c ldr r0, [pc, #48] ; (800032c )
+ ldr r1, =_edata
+ 80002fa: 490d ldr r1, [pc, #52] ; (8000330 )
+ ldr r2, =_sidata
+ 80002fc: 4a0d ldr r2, [pc, #52] ; (8000334 )
+ movs r3, #0
+ 80002fe: 2300 movs r3, #0
+ b LoopCopyDataInit
+ 8000300: e002 b.n 8000308
+
+08000302 :
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ 8000302: 58d4 ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ 8000304: 50c4 str r4, [r0, r3]
+ adds r3, r3, #4
+ 8000306: 3304 adds r3, #4
+
+08000308 :
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ 8000308: 18c4 adds r4, r0, r3
+ cmp r4, r1
+ 800030a: 428c cmp r4, r1
+ bcc CopyDataInit
+ 800030c: d3f9 bcc.n 8000302
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ 800030e: 4a0a ldr r2, [pc, #40] ; (8000338 )
+ ldr r4, =_ebss
+ 8000310: 4c0a ldr r4, [pc, #40] ; (800033c )
+ movs r3, #0
+ 8000312: 2300 movs r3, #0
+ b LoopFillZerobss
+ 8000314: e001 b.n 800031a
+
+08000316 :
+
+FillZerobss:
+ str r3, [r2]
+ 8000316: 6013 str r3, [r2, #0]
+ adds r2, r2, #4
+ 8000318: 3204 adds r2, #4
+
+0800031a :
+
+LoopFillZerobss:
+ cmp r2, r4
+ 800031a: 42a2 cmp r2, r4
+ bcc FillZerobss
+ 800031c: d3fb bcc.n 8000316
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+ 800031e: f7ff ffe4 bl 80002ea
+/* Call static constructors */
+ bl __libc_init_array
+ 8000322: f000 fd3d bl 8000da0 <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8000326: f7ff ff11 bl 800014c
+ bx lr
+ 800032a: 4770 bx lr
+ ldr r0, =_sdata
+ 800032c: 20000000 .word 0x20000000
+ ldr r1, =_edata
+ 8000330: 2000000c .word 0x2000000c
+ ldr r2, =_sidata
+ 8000334: 08000e38 .word 0x08000e38
+ ldr r2, =_sbss
+ 8000338: 2000000c .word 0x2000000c
+ ldr r4, =_ebss
+ 800033c: 2000002c .word 0x2000002c
+
+08000340 :
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8000340: e7fe b.n 8000340
+ ...
+
+08000344 :
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 8000344: b580 push {r7, lr}
+ 8000346: af00 add r7, sp, #0
+ defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+ /* Prefetch buffer is not available on value line devices */
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ 8000348: 4b08 ldr r3, [pc, #32] ; (800036c )
+ 800034a: 681b ldr r3, [r3, #0]
+ 800034c: 4a07 ldr r2, [pc, #28] ; (800036c )
+ 800034e: f043 0310 orr.w r3, r3, #16
+ 8000352: 6013 str r3, [r2, #0]
+#endif
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 8000354: 2003 movs r0, #3
+ 8000356: f000 f907 bl 8000568
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+ 800035a: 200f movs r0, #15
+ 800035c: f000 f808 bl 8000370
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+ 8000360: f7ff ff6a bl 8000238
+
+ /* Return function status */
+ return HAL_OK;
+ 8000364: 2300 movs r3, #0
+}
+ 8000366: 4618 mov r0, r3
+ 8000368: bd80 pop {r7, pc}
+ 800036a: bf00 nop
+ 800036c: 40022000 .word 0x40022000
+
+08000370 :
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 8000370: b580 push {r7, lr}
+ 8000372: b082 sub sp, #8
+ 8000374: af00 add r7, sp, #0
+ 8000376: 6078 str r0, [r7, #4]
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 8000378: 4b12 ldr r3, [pc, #72] ; (80003c4 )
+ 800037a: 681a ldr r2, [r3, #0]
+ 800037c: 4b12 ldr r3, [pc, #72] ; (80003c8 )
+ 800037e: 781b ldrb r3, [r3, #0]
+ 8000380: 4619 mov r1, r3
+ 8000382: f44f 737a mov.w r3, #1000 ; 0x3e8
+ 8000386: fbb3 f3f1 udiv r3, r3, r1
+ 800038a: fbb2 f3f3 udiv r3, r2, r3
+ 800038e: 4618 mov r0, r3
+ 8000390: f000 f911 bl 80005b6
+ 8000394: 4603 mov r3, r0
+ 8000396: 2b00 cmp r3, #0
+ 8000398: d001 beq.n 800039e
+ {
+ return HAL_ERROR;
+ 800039a: 2301 movs r3, #1
+ 800039c: e00e b.n 80003bc
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 800039e: 687b ldr r3, [r7, #4]
+ 80003a0: 2b0f cmp r3, #15
+ 80003a2: d80a bhi.n 80003ba
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 80003a4: 2200 movs r2, #0
+ 80003a6: 6879 ldr r1, [r7, #4]
+ 80003a8: f04f 30ff mov.w r0, #4294967295
+ 80003ac: f000 f8e7 bl 800057e
+ uwTickPrio = TickPriority;
+ 80003b0: 4a06 ldr r2, [pc, #24] ; (80003cc )
+ 80003b2: 687b ldr r3, [r7, #4]
+ 80003b4: 6013 str r3, [r2, #0]
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 80003b6: 2300 movs r3, #0
+ 80003b8: e000 b.n 80003bc
+ return HAL_ERROR;
+ 80003ba: 2301 movs r3, #1
+}
+ 80003bc: 4618 mov r0, r3
+ 80003be: 3708 adds r7, #8
+ 80003c0: 46bd mov sp, r7
+ 80003c2: bd80 pop {r7, pc}
+ 80003c4: 20000000 .word 0x20000000
+ 80003c8: 20000008 .word 0x20000008
+ 80003cc: 20000004 .word 0x20000004
+
+080003d0 :
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ 80003d0: b480 push {r7}
+ 80003d2: af00 add r7, sp, #0
+ uwTick += uwTickFreq;
+ 80003d4: 4b05 ldr r3, [pc, #20] ; (80003ec )
+ 80003d6: 781b ldrb r3, [r3, #0]
+ 80003d8: 461a mov r2, r3
+ 80003da: 4b05 ldr r3, [pc, #20] ; (80003f0 )
+ 80003dc: 681b ldr r3, [r3, #0]
+ 80003de: 4413 add r3, r2
+ 80003e0: 4a03 ldr r2, [pc, #12] ; (80003f0 )
+ 80003e2: 6013 str r3, [r2, #0]
+}
+ 80003e4: bf00 nop
+ 80003e6: 46bd mov sp, r7
+ 80003e8: bc80 pop {r7}
+ 80003ea: 4770 bx lr
+ 80003ec: 20000008 .word 0x20000008
+ 80003f0: 20000028 .word 0x20000028
+
+080003f4 :
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ 80003f4: b480 push {r7}
+ 80003f6: af00 add r7, sp, #0
+ return uwTick;
+ 80003f8: 4b02 ldr r3, [pc, #8] ; (8000404 )
+ 80003fa: 681b ldr r3, [r3, #0]
+}
+ 80003fc: 4618 mov r0, r3
+ 80003fe: 46bd mov sp, r7
+ 8000400: bc80 pop {r7}
+ 8000402: 4770 bx lr
+ 8000404: 20000028 .word 0x20000028
+
+08000408 <__NVIC_SetPriorityGrouping>:
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8000408: b480 push {r7}
+ 800040a: b085 sub sp, #20
+ 800040c: af00 add r7, sp, #0
+ 800040e: 6078 str r0, [r7, #4]
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 8000410: 687b ldr r3, [r7, #4]
+ 8000412: f003 0307 and.w r3, r3, #7
+ 8000416: 60fb str r3, [r7, #12]
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ 8000418: 4b0c ldr r3, [pc, #48] ; (800044c <__NVIC_SetPriorityGrouping+0x44>)
+ 800041a: 68db ldr r3, [r3, #12]
+ 800041c: 60bb str r3, [r7, #8]
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ 800041e: 68ba ldr r2, [r7, #8]
+ 8000420: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8000424: 4013 ands r3, r2
+ 8000426: 60bb str r3, [r7, #8]
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ 8000428: 68fb ldr r3, [r7, #12]
+ 800042a: 021a lsls r2, r3, #8
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 800042c: 68bb ldr r3, [r7, #8]
+ 800042e: 4313 orrs r3, r2
+ reg_value = (reg_value |
+ 8000430: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
+ 8000434: f443 3300 orr.w r3, r3, #131072 ; 0x20000
+ 8000438: 60bb str r3, [r7, #8]
+ SCB->AIRCR = reg_value;
+ 800043a: 4a04 ldr r2, [pc, #16] ; (800044c <__NVIC_SetPriorityGrouping+0x44>)
+ 800043c: 68bb ldr r3, [r7, #8]
+ 800043e: 60d3 str r3, [r2, #12]
+}
+ 8000440: bf00 nop
+ 8000442: 3714 adds r7, #20
+ 8000444: 46bd mov sp, r7
+ 8000446: bc80 pop {r7}
+ 8000448: 4770 bx lr
+ 800044a: bf00 nop
+ 800044c: e000ed00 .word 0xe000ed00
+
+08000450 <__NVIC_GetPriorityGrouping>:
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ 8000450: b480 push {r7}
+ 8000452: af00 add r7, sp, #0
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8000454: 4b04 ldr r3, [pc, #16] ; (8000468 <__NVIC_GetPriorityGrouping+0x18>)
+ 8000456: 68db ldr r3, [r3, #12]
+ 8000458: 0a1b lsrs r3, r3, #8
+ 800045a: f003 0307 and.w r3, r3, #7
+}
+ 800045e: 4618 mov r0, r3
+ 8000460: 46bd mov sp, r7
+ 8000462: bc80 pop {r7}
+ 8000464: 4770 bx lr
+ 8000466: bf00 nop
+ 8000468: e000ed00 .word 0xe000ed00
+
+0800046c <__NVIC_SetPriority>:
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 800046c: b480 push {r7}
+ 800046e: b083 sub sp, #12
+ 8000470: af00 add r7, sp, #0
+ 8000472: 4603 mov r3, r0
+ 8000474: 6039 str r1, [r7, #0]
+ 8000476: 71fb strb r3, [r7, #7]
+ if ((int32_t)(IRQn) >= 0)
+ 8000478: f997 3007 ldrsb.w r3, [r7, #7]
+ 800047c: 2b00 cmp r3, #0
+ 800047e: db0a blt.n 8000496 <__NVIC_SetPriority+0x2a>
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8000480: 683b ldr r3, [r7, #0]
+ 8000482: b2da uxtb r2, r3
+ 8000484: 490c ldr r1, [pc, #48] ; (80004b8 <__NVIC_SetPriority+0x4c>)
+ 8000486: f997 3007 ldrsb.w r3, [r7, #7]
+ 800048a: 0112 lsls r2, r2, #4
+ 800048c: b2d2 uxtb r2, r2
+ 800048e: 440b add r3, r1
+ 8000490: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+ 8000494: e00a b.n 80004ac <__NVIC_SetPriority+0x40>
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8000496: 683b ldr r3, [r7, #0]
+ 8000498: b2da uxtb r2, r3
+ 800049a: 4908 ldr r1, [pc, #32] ; (80004bc <__NVIC_SetPriority+0x50>)
+ 800049c: 79fb ldrb r3, [r7, #7]
+ 800049e: f003 030f and.w r3, r3, #15
+ 80004a2: 3b04 subs r3, #4
+ 80004a4: 0112 lsls r2, r2, #4
+ 80004a6: b2d2 uxtb r2, r2
+ 80004a8: 440b add r3, r1
+ 80004aa: 761a strb r2, [r3, #24]
+}
+ 80004ac: bf00 nop
+ 80004ae: 370c adds r7, #12
+ 80004b0: 46bd mov sp, r7
+ 80004b2: bc80 pop {r7}
+ 80004b4: 4770 bx lr
+ 80004b6: bf00 nop
+ 80004b8: e000e100 .word 0xe000e100
+ 80004bc: e000ed00 .word 0xe000ed00
+
+080004c0 :
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 80004c0: b480 push {r7}
+ 80004c2: b089 sub sp, #36 ; 0x24
+ 80004c4: af00 add r7, sp, #0
+ 80004c6: 60f8 str r0, [r7, #12]
+ 80004c8: 60b9 str r1, [r7, #8]
+ 80004ca: 607a str r2, [r7, #4]
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 80004cc: 68fb ldr r3, [r7, #12]
+ 80004ce: f003 0307 and.w r3, r3, #7
+ 80004d2: 61fb str r3, [r7, #28]
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 80004d4: 69fb ldr r3, [r7, #28]
+ 80004d6: f1c3 0307 rsb r3, r3, #7
+ 80004da: 2b04 cmp r3, #4
+ 80004dc: bf28 it cs
+ 80004de: 2304 movcs r3, #4
+ 80004e0: 61bb str r3, [r7, #24]
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 80004e2: 69fb ldr r3, [r7, #28]
+ 80004e4: 3304 adds r3, #4
+ 80004e6: 2b06 cmp r3, #6
+ 80004e8: d902 bls.n 80004f0
+ 80004ea: 69fb ldr r3, [r7, #28]
+ 80004ec: 3b03 subs r3, #3
+ 80004ee: e000 b.n 80004f2
+ 80004f0: 2300 movs r3, #0
+ 80004f2: 617b str r3, [r7, #20]
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 80004f4: f04f 32ff mov.w r2, #4294967295
+ 80004f8: 69bb ldr r3, [r7, #24]
+ 80004fa: fa02 f303 lsl.w r3, r2, r3
+ 80004fe: 43da mvns r2, r3
+ 8000500: 68bb ldr r3, [r7, #8]
+ 8000502: 401a ands r2, r3
+ 8000504: 697b ldr r3, [r7, #20]
+ 8000506: 409a lsls r2, r3
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ 8000508: f04f 31ff mov.w r1, #4294967295
+ 800050c: 697b ldr r3, [r7, #20]
+ 800050e: fa01 f303 lsl.w r3, r1, r3
+ 8000512: 43d9 mvns r1, r3
+ 8000514: 687b ldr r3, [r7, #4]
+ 8000516: 400b ands r3, r1
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8000518: 4313 orrs r3, r2
+ );
+}
+ 800051a: 4618 mov r0, r3
+ 800051c: 3724 adds r7, #36 ; 0x24
+ 800051e: 46bd mov sp, r7
+ 8000520: bc80 pop {r7}
+ 8000522: 4770 bx lr
+
+08000524 :
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+ {
+ return (1UL); /* Reload value impossible */
+ 8000536: 2301 movs r3, #1
+ 8000538: e00f b.n 800055a
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 800053a: 4a0a ldr r2, [pc, #40] ; (8000564 )
+ 800053c: 687b ldr r3, [r7, #4]
+ 800053e: 3b01 subs r3, #1
+ 8000540: 6053 str r3, [r2, #4]
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8000542: 210f movs r1, #15
+ 8000544: f04f 30ff mov.w r0, #4294967295
+ 8000548: f7ff ff90 bl 800046c <__NVIC_SetPriority>
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 800054c: 4b05 ldr r3, [pc, #20] ; (8000564 )
+ 800054e: 2200 movs r2, #0
+ 8000550: 609a str r2, [r3, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 8000552: 4b04 ldr r3, [pc, #16] ; (8000564 )
+ 8000554: 2207 movs r2, #7
+ 8000556: 601a str r2, [r3, #0]
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+ 8000558: 2300 movs r3, #0
+}
+ 800055a: 4618 mov r0, r3
+ 800055c: 3708 adds r7, #8
+ 800055e: 46bd mov sp, r7
+ 8000560: bd80 pop {r7, pc}
+ 8000562: bf00 nop
+ 8000564: e000e010 .word 0xe000e010
+
+08000568 :
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8000568: b580 push {r7, lr}
+ 800056a: b082 sub sp, #8
+ 800056c: af00 add r7, sp, #0
+ 800056e: 6078 str r0, [r7, #4]
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+ 8000570: 6878 ldr r0, [r7, #4]
+ 8000572: f7ff ff49 bl 8000408 <__NVIC_SetPriorityGrouping>
+}
+ 8000576: bf00 nop
+ 8000578: 3708 adds r7, #8
+ 800057a: 46bd mov sp, r7
+ 800057c: bd80 pop {r7, pc}
+
+0800057e :
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 800057e: b580 push {r7, lr}
+ 8000580: b086 sub sp, #24
+ 8000582: af00 add r7, sp, #0
+ 8000584: 4603 mov r3, r0
+ 8000586: 60b9 str r1, [r7, #8]
+ 8000588: 607a str r2, [r7, #4]
+ 800058a: 73fb strb r3, [r7, #15]
+ uint32_t prioritygroup = 0x00U;
+ 800058c: 2300 movs r3, #0
+ 800058e: 617b str r3, [r7, #20]
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+ 8000590: f7ff ff5e bl 8000450 <__NVIC_GetPriorityGrouping>
+ 8000594: 6178 str r0, [r7, #20]
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8000596: 687a ldr r2, [r7, #4]
+ 8000598: 68b9 ldr r1, [r7, #8]
+ 800059a: 6978 ldr r0, [r7, #20]
+ 800059c: f7ff ff90 bl 80004c0
+ 80005a0: 4602 mov r2, r0
+ 80005a2: f997 300f ldrsb.w r3, [r7, #15]
+ 80005a6: 4611 mov r1, r2
+ 80005a8: 4618 mov r0, r3
+ 80005aa: f7ff ff5f bl 800046c <__NVIC_SetPriority>
+}
+ 80005ae: bf00 nop
+ 80005b0: 3718 adds r7, #24
+ 80005b2: 46bd mov sp, r7
+ 80005b4: bd80 pop {r7, pc}
+
+080005b6 :
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 80005b6: b580 push {r7, lr}
+ 80005b8: b082 sub sp, #8
+ 80005ba: af00 add r7, sp, #0
+ 80005bc: 6078 str r0, [r7, #4]
+ return SysTick_Config(TicksNumb);
+ 80005be: 6878 ldr r0, [r7, #4]
+ 80005c0: f7ff ffb0 bl 8000524
+ 80005c4: 4603 mov r3, r0
+}
+ 80005c6: 4618 mov r0, r3
+ 80005c8: 3708 adds r7, #8
+ 80005ca: 46bd mov sp, r7
+ 80005cc: bd80 pop {r7, pc}
+ ...
+
+080005d0 :
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ 80005d0: b580 push {r7, lr}
+ 80005d2: b086 sub sp, #24
+ 80005d4: af00 add r7, sp, #0
+ 80005d6: 6078 str r0, [r7, #4]
+ uint32_t tickstart;
+ uint32_t pll_config;
+
+ /* Check Null pointer */
+ if (RCC_OscInitStruct == NULL)
+ 80005d8: 687b ldr r3, [r7, #4]
+ 80005da: 2b00 cmp r3, #0
+ 80005dc: d101 bne.n 80005e2
+ {
+ return HAL_ERROR;
+ 80005de: 2301 movs r3, #1
+ 80005e0: e26c b.n 8000abc
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 80005e2: 687b ldr r3, [r7, #4]
+ 80005e4: 681b ldr r3, [r3, #0]
+ 80005e6: f003 0301 and.w r3, r3, #1
+ 80005ea: 2b00 cmp r3, #0
+ 80005ec: f000 8087 beq.w 80006fe
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ 80005f0: 4b92 ldr r3, [pc, #584] ; (800083c )
+ 80005f2: 685b ldr r3, [r3, #4]
+ 80005f4: f003 030c and.w r3, r3, #12
+ 80005f8: 2b04 cmp r3, #4
+ 80005fa: d00c beq.n 8000616
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ 80005fc: 4b8f ldr r3, [pc, #572] ; (800083c )
+ 80005fe: 685b ldr r3, [r3, #4]
+ 8000600: f003 030c and.w r3, r3, #12
+ 8000604: 2b08 cmp r3, #8
+ 8000606: d112 bne.n 800062e
+ 8000608: 4b8c ldr r3, [pc, #560] ; (800083c )
+ 800060a: 685b ldr r3, [r3, #4]
+ 800060c: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8000610: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8000614: d10b bne.n 800062e
+ {
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8000616: 4b89 ldr r3, [pc, #548] ; (800083c )
+ 8000618: 681b ldr r3, [r3, #0]
+ 800061a: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 800061e: 2b00 cmp r3, #0
+ 8000620: d06c beq.n 80006fc
+ 8000622: 687b ldr r3, [r7, #4]
+ 8000624: 685b ldr r3, [r3, #4]
+ 8000626: 2b00 cmp r3, #0
+ 8000628: d168 bne.n 80006fc
+ {
+ return HAL_ERROR;
+ 800062a: 2301 movs r3, #1
+ 800062c: e246 b.n 8000abc
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 800062e: 687b ldr r3, [r7, #4]
+ 8000630: 685b ldr r3, [r3, #4]
+ 8000632: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8000636: d106 bne.n 8000646
+ 8000638: 4b80 ldr r3, [pc, #512] ; (800083c )
+ 800063a: 681b ldr r3, [r3, #0]
+ 800063c: 4a7f ldr r2, [pc, #508] ; (800083c )
+ 800063e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8000642: 6013 str r3, [r2, #0]
+ 8000644: e02e b.n 80006a4
+ 8000646: 687b ldr r3, [r7, #4]
+ 8000648: 685b ldr r3, [r3, #4]
+ 800064a: 2b00 cmp r3, #0
+ 800064c: d10c bne.n 8000668
+ 800064e: 4b7b ldr r3, [pc, #492] ; (800083c )
+ 8000650: 681b ldr r3, [r3, #0]
+ 8000652: 4a7a ldr r2, [pc, #488] ; (800083c )
+ 8000654: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8000658: 6013 str r3, [r2, #0]
+ 800065a: 4b78 ldr r3, [pc, #480] ; (800083c )
+ 800065c: 681b ldr r3, [r3, #0]
+ 800065e: 4a77 ldr r2, [pc, #476] ; (800083c )
+ 8000660: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000664: 6013 str r3, [r2, #0]
+ 8000666: e01d b.n 80006a4
+ 8000668: 687b ldr r3, [r7, #4]
+ 800066a: 685b ldr r3, [r3, #4]
+ 800066c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
+ 8000670: d10c bne.n 800068c
+ 8000672: 4b72 ldr r3, [pc, #456] ; (800083c )
+ 8000674: 681b ldr r3, [r3, #0]
+ 8000676: 4a71 ldr r2, [pc, #452] ; (800083c )
+ 8000678: f443 2380 orr.w r3, r3, #262144 ; 0x40000
+ 800067c: 6013 str r3, [r2, #0]
+ 800067e: 4b6f ldr r3, [pc, #444] ; (800083c )
+ 8000680: 681b ldr r3, [r3, #0]
+ 8000682: 4a6e ldr r2, [pc, #440] ; (800083c )
+ 8000684: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8000688: 6013 str r3, [r2, #0]
+ 800068a: e00b b.n 80006a4
+ 800068c: 4b6b ldr r3, [pc, #428] ; (800083c )
+ 800068e: 681b ldr r3, [r3, #0]
+ 8000690: 4a6a ldr r2, [pc, #424] ; (800083c )
+ 8000692: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8000696: 6013 str r3, [r2, #0]
+ 8000698: 4b68 ldr r3, [pc, #416] ; (800083c )
+ 800069a: 681b ldr r3, [r3, #0]
+ 800069c: 4a67 ldr r2, [pc, #412] ; (800083c )
+ 800069e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 80006a2: 6013 str r3, [r2, #0]
+
+
+ /* Check the HSE State */
+ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 80006a4: 687b ldr r3, [r7, #4]
+ 80006a6: 685b ldr r3, [r3, #4]
+ 80006a8: 2b00 cmp r3, #0
+ 80006aa: d013 beq.n 80006d4
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 80006ac: f7ff fea2 bl 80003f4
+ 80006b0: 6138 str r0, [r7, #16]
+
+ /* Wait till HSE is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 80006b2: e008 b.n 80006c6
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 80006b4: f7ff fe9e bl 80003f4
+ 80006b8: 4602 mov r2, r0
+ 80006ba: 693b ldr r3, [r7, #16]
+ 80006bc: 1ad3 subs r3, r2, r3
+ 80006be: 2b64 cmp r3, #100 ; 0x64
+ 80006c0: d901 bls.n 80006c6
+ {
+ return HAL_TIMEOUT;
+ 80006c2: 2303 movs r3, #3
+ 80006c4: e1fa b.n 8000abc
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 80006c6: 4b5d ldr r3, [pc, #372] ; (800083c )
+ 80006c8: 681b ldr r3, [r3, #0]
+ 80006ca: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80006ce: 2b00 cmp r3, #0
+ 80006d0: d0f0 beq.n 80006b4
+ 80006d2: e014 b.n 80006fe
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 80006d4: f7ff fe8e bl 80003f4
+ 80006d8: 6138 str r0, [r7, #16]
+
+ /* Wait till HSE is disabled */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 80006da: e008 b.n 80006ee
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 80006dc: f7ff fe8a bl 80003f4
+ 80006e0: 4602 mov r2, r0
+ 80006e2: 693b ldr r3, [r7, #16]
+ 80006e4: 1ad3 subs r3, r2, r3
+ 80006e6: 2b64 cmp r3, #100 ; 0x64
+ 80006e8: d901 bls.n 80006ee
+ {
+ return HAL_TIMEOUT;
+ 80006ea: 2303 movs r3, #3
+ 80006ec: e1e6 b.n 8000abc
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 80006ee: 4b53 ldr r3, [pc, #332] ; (800083c )
+ 80006f0: 681b ldr r3, [r3, #0]
+ 80006f2: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80006f6: 2b00 cmp r3, #0
+ 80006f8: d1f0 bne.n 80006dc
+ 80006fa: e000 b.n 80006fe
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 80006fc: bf00 nop
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 80006fe: 687b ldr r3, [r7, #4]
+ 8000700: 681b ldr r3, [r3, #0]
+ 8000702: f003 0302 and.w r3, r3, #2
+ 8000706: 2b00 cmp r3, #0
+ 8000708: d063 beq.n 80007d2
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ 800070a: 4b4c ldr r3, [pc, #304] ; (800083c )
+ 800070c: 685b ldr r3, [r3, #4]
+ 800070e: f003 030c and.w r3, r3, #12
+ 8000712: 2b00 cmp r3, #0
+ 8000714: d00b beq.n 800072e
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
+ 8000716: 4b49 ldr r3, [pc, #292] ; (800083c )
+ 8000718: 685b ldr r3, [r3, #4]
+ 800071a: f003 030c and.w r3, r3, #12
+ 800071e: 2b08 cmp r3, #8
+ 8000720: d11c bne.n 800075c
+ 8000722: 4b46 ldr r3, [pc, #280] ; (800083c )
+ 8000724: 685b ldr r3, [r3, #4]
+ 8000726: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 800072a: 2b00 cmp r3, #0
+ 800072c: d116 bne.n 800075c
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 800072e: 4b43 ldr r3, [pc, #268] ; (800083c )
+ 8000730: 681b ldr r3, [r3, #0]
+ 8000732: f003 0302 and.w r3, r3, #2
+ 8000736: 2b00 cmp r3, #0
+ 8000738: d005 beq.n 8000746
+ 800073a: 687b ldr r3, [r7, #4]
+ 800073c: 691b ldr r3, [r3, #16]
+ 800073e: 2b01 cmp r3, #1
+ 8000740: d001 beq.n 8000746
+ {
+ return HAL_ERROR;
+ 8000742: 2301 movs r3, #1
+ 8000744: e1ba b.n 8000abc
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8000746: 4b3d ldr r3, [pc, #244] ; (800083c )
+ 8000748: 681b ldr r3, [r3, #0]
+ 800074a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 800074e: 687b ldr r3, [r7, #4]
+ 8000750: 695b ldr r3, [r3, #20]
+ 8000752: 00db lsls r3, r3, #3
+ 8000754: 4939 ldr r1, [pc, #228] ; (800083c )
+ 8000756: 4313 orrs r3, r2
+ 8000758: 600b str r3, [r1, #0]
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 800075a: e03a b.n 80007d2
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ 800075c: 687b ldr r3, [r7, #4]
+ 800075e: 691b ldr r3, [r3, #16]
+ 8000760: 2b00 cmp r3, #0
+ 8000762: d020 beq.n 80007a6
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+ 8000764: 4b36 ldr r3, [pc, #216] ; (8000840 )
+ 8000766: 2201 movs r2, #1
+ 8000768: 601a str r2, [r3, #0]
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 800076a: f7ff fe43 bl 80003f4
+ 800076e: 6138 str r0, [r7, #16]
+
+ /* Wait till HSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000770: e008 b.n 8000784
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 8000772: f7ff fe3f bl 80003f4
+ 8000776: 4602 mov r2, r0
+ 8000778: 693b ldr r3, [r7, #16]
+ 800077a: 1ad3 subs r3, r2, r3
+ 800077c: 2b02 cmp r3, #2
+ 800077e: d901 bls.n 8000784
+ {
+ return HAL_TIMEOUT;
+ 8000780: 2303 movs r3, #3
+ 8000782: e19b b.n 8000abc
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000784: 4b2d ldr r3, [pc, #180] ; (800083c )
+ 8000786: 681b ldr r3, [r3, #0]
+ 8000788: f003 0302 and.w r3, r3, #2
+ 800078c: 2b00 cmp r3, #0
+ 800078e: d0f0 beq.n 8000772
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8000790: 4b2a ldr r3, [pc, #168] ; (800083c )
+ 8000792: 681b ldr r3, [r3, #0]
+ 8000794: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8000798: 687b ldr r3, [r7, #4]
+ 800079a: 695b ldr r3, [r3, #20]
+ 800079c: 00db lsls r3, r3, #3
+ 800079e: 4927 ldr r1, [pc, #156] ; (800083c )
+ 80007a0: 4313 orrs r3, r2
+ 80007a2: 600b str r3, [r1, #0]
+ 80007a4: e015 b.n 80007d2
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+ 80007a6: 4b26 ldr r3, [pc, #152] ; (8000840 )
+ 80007a8: 2200 movs r2, #0
+ 80007aa: 601a str r2, [r3, #0]
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 80007ac: f7ff fe22 bl 80003f4
+ 80007b0: 6138 str r0, [r7, #16]
+
+ /* Wait till HSI is disabled */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 80007b2: e008 b.n 80007c6
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 80007b4: f7ff fe1e bl 80003f4
+ 80007b8: 4602 mov r2, r0
+ 80007ba: 693b ldr r3, [r7, #16]
+ 80007bc: 1ad3 subs r3, r2, r3
+ 80007be: 2b02 cmp r3, #2
+ 80007c0: d901 bls.n 80007c6
+ {
+ return HAL_TIMEOUT;
+ 80007c2: 2303 movs r3, #3
+ 80007c4: e17a b.n 8000abc
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 80007c6: 4b1d ldr r3, [pc, #116] ; (800083c )
+ 80007c8: 681b ldr r3, [r3, #0]
+ 80007ca: f003 0302 and.w r3, r3, #2
+ 80007ce: 2b00 cmp r3, #0
+ 80007d0: d1f0 bne.n 80007b4
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 80007d2: 687b ldr r3, [r7, #4]
+ 80007d4: 681b ldr r3, [r3, #0]
+ 80007d6: f003 0308 and.w r3, r3, #8
+ 80007da: 2b00 cmp r3, #0
+ 80007dc: d03a beq.n 8000854
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 80007de: 687b ldr r3, [r7, #4]
+ 80007e0: 699b ldr r3, [r3, #24]
+ 80007e2: 2b00 cmp r3, #0
+ 80007e4: d019 beq.n 800081a
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+ 80007e6: 4b17 ldr r3, [pc, #92] ; (8000844 )
+ 80007e8: 2201 movs r2, #1
+ 80007ea: 601a str r2, [r3, #0]
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 80007ec: f7ff fe02 bl 80003f4
+ 80007f0: 6138 str r0, [r7, #16]
+
+ /* Wait till LSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 80007f2: e008 b.n 8000806
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 80007f4: f7ff fdfe bl 80003f4
+ 80007f8: 4602 mov r2, r0
+ 80007fa: 693b ldr r3, [r7, #16]
+ 80007fc: 1ad3 subs r3, r2, r3
+ 80007fe: 2b02 cmp r3, #2
+ 8000800: d901 bls.n 8000806
+ {
+ return HAL_TIMEOUT;
+ 8000802: 2303 movs r3, #3
+ 8000804: e15a b.n 8000abc
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 8000806: 4b0d ldr r3, [pc, #52] ; (800083c )
+ 8000808: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800080a: f003 0302 and.w r3, r3, #2
+ 800080e: 2b00 cmp r3, #0
+ 8000810: d0f0 beq.n 80007f4
+ }
+ }
+ /* To have a fully stabilized clock in the specified range, a software delay of 1ms
+ should be added.*/
+ RCC_Delay(1);
+ 8000812: 2001 movs r0, #1
+ 8000814: f000 faa6 bl 8000d64
+ 8000818: e01c b.n 8000854
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+ 800081a: 4b0a ldr r3, [pc, #40] ; (8000844 )
+ 800081c: 2200 movs r2, #0
+ 800081e: 601a str r2, [r3, #0]
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 8000820: f7ff fde8 bl 80003f4
+ 8000824: 6138 str r0, [r7, #16]
+
+ /* Wait till LSI is disabled */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 8000826: e00f b.n 8000848
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 8000828: f7ff fde4 bl 80003f4
+ 800082c: 4602 mov r2, r0
+ 800082e: 693b ldr r3, [r7, #16]
+ 8000830: 1ad3 subs r3, r2, r3
+ 8000832: 2b02 cmp r3, #2
+ 8000834: d908 bls.n 8000848
+ {
+ return HAL_TIMEOUT;
+ 8000836: 2303 movs r3, #3
+ 8000838: e140 b.n 8000abc
+ 800083a: bf00 nop
+ 800083c: 40021000 .word 0x40021000
+ 8000840: 42420000 .word 0x42420000
+ 8000844: 42420480 .word 0x42420480
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 8000848: 4b9e ldr r3, [pc, #632] ; (8000ac4 )
+ 800084a: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800084c: f003 0302 and.w r3, r3, #2
+ 8000850: 2b00 cmp r3, #0
+ 8000852: d1e9 bne.n 8000828
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 8000854: 687b ldr r3, [r7, #4]
+ 8000856: 681b ldr r3, [r3, #0]
+ 8000858: f003 0304 and.w r3, r3, #4
+ 800085c: 2b00 cmp r3, #0
+ 800085e: f000 80a6 beq.w 80009ae
+ {
+ FlagStatus pwrclkchanged = RESET;
+ 8000862: 2300 movs r3, #0
+ 8000864: 75fb strb r3, [r7, #23]
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 8000866: 4b97 ldr r3, [pc, #604] ; (8000ac4 )
+ 8000868: 69db ldr r3, [r3, #28]
+ 800086a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 800086e: 2b00 cmp r3, #0
+ 8000870: d10d bne.n 800088e
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8000872: 4b94 ldr r3, [pc, #592] ; (8000ac4 )
+ 8000874: 69db ldr r3, [r3, #28]
+ 8000876: 4a93 ldr r2, [pc, #588] ; (8000ac4 )
+ 8000878: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 800087c: 61d3 str r3, [r2, #28]
+ 800087e: 4b91 ldr r3, [pc, #580] ; (8000ac4 )
+ 8000880: 69db ldr r3, [r3, #28]
+ 8000882: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000886: 60bb str r3, [r7, #8]
+ 8000888: 68bb ldr r3, [r7, #8]
+ pwrclkchanged = SET;
+ 800088a: 2301 movs r3, #1
+ 800088c: 75fb strb r3, [r7, #23]
+ }
+
+ if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 800088e: 4b8e ldr r3, [pc, #568] ; (8000ac8 )
+ 8000890: 681b ldr r3, [r3, #0]
+ 8000892: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8000896: 2b00 cmp r3, #0
+ 8000898: d118 bne.n 80008cc
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+ 800089a: 4b8b ldr r3, [pc, #556] ; (8000ac8 )
+ 800089c: 681b ldr r3, [r3, #0]
+ 800089e: 4a8a ldr r2, [pc, #552] ; (8000ac8 )
+ 80008a0: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 80008a4: 6013 str r3, [r2, #0]
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+ 80008a6: f7ff fda5 bl 80003f4
+ 80008aa: 6138 str r0, [r7, #16]
+
+ while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 80008ac: e008 b.n 80008c0
+ {
+ if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 80008ae: f7ff fda1 bl 80003f4
+ 80008b2: 4602 mov r2, r0
+ 80008b4: 693b ldr r3, [r7, #16]
+ 80008b6: 1ad3 subs r3, r2, r3
+ 80008b8: 2b64 cmp r3, #100 ; 0x64
+ 80008ba: d901 bls.n 80008c0
+ {
+ return HAL_TIMEOUT;
+ 80008bc: 2303 movs r3, #3
+ 80008be: e0fd b.n 8000abc
+ while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 80008c0: 4b81 ldr r3, [pc, #516] ; (8000ac8 )
+ 80008c2: 681b ldr r3, [r3, #0]
+ 80008c4: f403 7380 and.w r3, r3, #256 ; 0x100
+ 80008c8: 2b00 cmp r3, #0
+ 80008ca: d0f0 beq.n 80008ae
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 80008cc: 687b ldr r3, [r7, #4]
+ 80008ce: 68db ldr r3, [r3, #12]
+ 80008d0: 2b01 cmp r3, #1
+ 80008d2: d106 bne.n 80008e2
+ 80008d4: 4b7b ldr r3, [pc, #492] ; (8000ac4 )
+ 80008d6: 6a1b ldr r3, [r3, #32]
+ 80008d8: 4a7a ldr r2, [pc, #488] ; (8000ac4 )
+ 80008da: f043 0301 orr.w r3, r3, #1
+ 80008de: 6213 str r3, [r2, #32]
+ 80008e0: e02d b.n 800093e
+ 80008e2: 687b ldr r3, [r7, #4]
+ 80008e4: 68db ldr r3, [r3, #12]
+ 80008e6: 2b00 cmp r3, #0
+ 80008e8: d10c bne.n 8000904
+ 80008ea: 4b76 ldr r3, [pc, #472] ; (8000ac4 )
+ 80008ec: 6a1b ldr r3, [r3, #32]
+ 80008ee: 4a75 ldr r2, [pc, #468] ; (8000ac4 )
+ 80008f0: f023 0301 bic.w r3, r3, #1
+ 80008f4: 6213 str r3, [r2, #32]
+ 80008f6: 4b73 ldr r3, [pc, #460] ; (8000ac4 )
+ 80008f8: 6a1b ldr r3, [r3, #32]
+ 80008fa: 4a72 ldr r2, [pc, #456] ; (8000ac4 )
+ 80008fc: f023 0304 bic.w r3, r3, #4
+ 8000900: 6213 str r3, [r2, #32]
+ 8000902: e01c b.n 800093e
+ 8000904: 687b ldr r3, [r7, #4]
+ 8000906: 68db ldr r3, [r3, #12]
+ 8000908: 2b05 cmp r3, #5
+ 800090a: d10c bne.n 8000926
+ 800090c: 4b6d ldr r3, [pc, #436] ; (8000ac4 )
+ 800090e: 6a1b ldr r3, [r3, #32]
+ 8000910: 4a6c ldr r2, [pc, #432] ; (8000ac4 )
+ 8000912: f043 0304 orr.w r3, r3, #4
+ 8000916: 6213 str r3, [r2, #32]
+ 8000918: 4b6a ldr r3, [pc, #424] ; (8000ac4 )
+ 800091a: 6a1b ldr r3, [r3, #32]
+ 800091c: 4a69 ldr r2, [pc, #420] ; (8000ac4 )
+ 800091e: f043 0301 orr.w r3, r3, #1
+ 8000922: 6213 str r3, [r2, #32]
+ 8000924: e00b b.n 800093e
+ 8000926: 4b67 ldr r3, [pc, #412] ; (8000ac4 )
+ 8000928: 6a1b ldr r3, [r3, #32]
+ 800092a: 4a66 ldr r2, [pc, #408] ; (8000ac4