kevin/morse_code_trainer
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
c2367adb65770f5ef7242af806e5cd49aadd1fac
morse_code_trainer/stm32f103/Debug/stm32f103.list
T
kevin c2367adb65 updata pcb
2022-04-05 18:14:42 +08:00

2607 lines
98 KiB
Plaintext
Raw Blame History

stm32f103.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00000d1c 0800010c 0800010c 0001010c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000020 08000e28 08000e28 00010e28 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08000e48 08000e48 0002000c 2**0
CONTENTS
4 .ARM 00000000 08000e48 08000e48 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08000e48 08000e48 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08000e48 08000e48 00010e48 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08000e4c 08000e4c 00010e4c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08000e50 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000020 2000000c 08000e5c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000002c 08000e5c 0002002c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00002816 00000000 00000000 00020035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00000c75 00000000 00000000 0002284b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000378 00000000 00000000 000234c0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000300 00000000 00000000 00023838 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000156ee 00000000 00000000 00023b38 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00003d01 00000000 00000000 00039226 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0007b704 00000000 00000000 0003cf27 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 000b862b 2**0
CONTENTS, READONLY
20 .debug_frame 00000be8 00000000 00000000 000b8680 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 2000000c .word 0x2000000c
8000128: 00000000 .word 0x00000000
800012c: 08000e10 .word 0x08000e10
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000010 .word 0x20000010
8000148: 08000e10 .word 0x08000e10
0800014c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800014c: b580 push {r7, lr}
800014e: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000150: f000 f904 bl 800035c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000154: f000 f803 bl 800015e <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000158: f000 f846 bl 80001e8 <MX_GPIO_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
800015c: e7fe b.n 800015c <main+0x10>
0800015e <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800015e: b580 push {r7, lr}
8000160: b090 sub sp, #64 ; 0x40
8000162: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000164: f107 0318 add.w r3, r7, #24
8000168: 2228 movs r2, #40 ; 0x28
800016a: 2100 movs r1, #0
800016c: 4618 mov r0, r3
800016e: f000 fe47 bl 8000e00 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000172: 1d3b adds r3, r7, #4
8000174: 2200 movs r2, #0
8000176: 601a str r2, [r3, #0]
8000178: 605a str r2, [r3, #4]
800017a: 609a str r2, [r3, #8]
800017c: 60da str r2, [r3, #12]
800017e: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000180: 2301 movs r3, #1
8000182: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000184: f44f 3380 mov.w r3, #65536 ; 0x10000
8000188: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
800018a: 2300 movs r3, #0
800018c: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800018e: 2301 movs r3, #1
8000190: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000192: 2302 movs r3, #2
8000194: 637b str r3, [r7, #52] ; 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000196: f44f 3380 mov.w r3, #65536 ; 0x10000
800019a: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
800019c: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
80001a0: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80001a2: f107 0318 add.w r3, r7, #24
80001a6: 4618 mov r0, r3
80001a8: f000 fa1e bl 80005e8 <HAL_RCC_OscConfig>
80001ac: 4603 mov r3, r0
80001ae: 2b00 cmp r3, #0
80001b0: d001 beq.n 80001b6 <SystemClock_Config+0x58>
{
Error_Handler();
80001b2: f000 f847 bl 8000244 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80001b6: 230f movs r3, #15
80001b8: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80001ba: 2302 movs r3, #2
80001bc: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80001be: 2300 movs r3, #0
80001c0: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80001c2: f44f 6380 mov.w r3, #1024 ; 0x400
80001c6: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80001c8: 2300 movs r3, #0
80001ca: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80001cc: 1d3b adds r3, r7, #4
80001ce: 2102 movs r1, #2
80001d0: 4618 mov r0, r3
80001d2: f000 fc89 bl 8000ae8 <HAL_RCC_ClockConfig>
80001d6: 4603 mov r3, r0
80001d8: 2b00 cmp r3, #0
80001da: d001 beq.n 80001e0 <SystemClock_Config+0x82>
{
Error_Handler();
80001dc: f000 f832 bl 8000244 <Error_Handler>
}
}
80001e0: bf00 nop
80001e2: 3740 adds r7, #64 ; 0x40
80001e4: 46bd mov sp, r7
80001e6: bd80 pop {r7, pc}
080001e8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80001e8: b480 push {r7}
80001ea: b085 sub sp, #20
80001ec: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80001ee: 4b14 ldr r3, [pc, #80] ; (8000240 <MX_GPIO_Init+0x58>)
80001f0: 699b ldr r3, [r3, #24]
80001f2: 4a13 ldr r2, [pc, #76] ; (8000240 <MX_GPIO_Init+0x58>)
80001f4: f043 0310 orr.w r3, r3, #16
80001f8: 6193 str r3, [r2, #24]
80001fa: 4b11 ldr r3, [pc, #68] ; (8000240 <MX_GPIO_Init+0x58>)
80001fc: 699b ldr r3, [r3, #24]
80001fe: f003 0310 and.w r3, r3, #16
8000202: 60fb str r3, [r7, #12]
8000204: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000206: 4b0e ldr r3, [pc, #56] ; (8000240 <MX_GPIO_Init+0x58>)
8000208: 699b ldr r3, [r3, #24]
800020a: 4a0d ldr r2, [pc, #52] ; (8000240 <MX_GPIO_Init+0x58>)
800020c: f043 0320 orr.w r3, r3, #32
8000210: 6193 str r3, [r2, #24]
8000212: 4b0b ldr r3, [pc, #44] ; (8000240 <MX_GPIO_Init+0x58>)
8000214: 699b ldr r3, [r3, #24]
8000216: f003 0320 and.w r3, r3, #32
800021a: 60bb str r3, [r7, #8]
800021c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800021e: 4b08 ldr r3, [pc, #32] ; (8000240 <MX_GPIO_Init+0x58>)
8000220: 699b ldr r3, [r3, #24]
8000222: 4a07 ldr r2, [pc, #28] ; (8000240 <MX_GPIO_Init+0x58>)
8000224: f043 0304 orr.w r3, r3, #4
8000228: 6193 str r3, [r2, #24]
800022a: 4b05 ldr r3, [pc, #20] ; (8000240 <MX_GPIO_Init+0x58>)
800022c: 699b ldr r3, [r3, #24]
800022e: f003 0304 and.w r3, r3, #4
8000232: 607b str r3, [r7, #4]
8000234: 687b ldr r3, [r7, #4]
}
8000236: bf00 nop
8000238: 3714 adds r7, #20
800023a: 46bd mov sp, r7
800023c: bc80 pop {r7}
800023e: 4770 bx lr
8000240: 40021000 .word 0x40021000
08000244 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000244: b480 push {r7}
8000246: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000248: b672 cpsid i
}
800024a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800024c: e7fe b.n 800024c <Error_Handler+0x8>
...
08000250 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000250: b480 push {r7}
8000252: b085 sub sp, #20
8000254: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8000256: 4b15 ldr r3, [pc, #84] ; (80002ac <HAL_MspInit+0x5c>)
8000258: 699b ldr r3, [r3, #24]
800025a: 4a14 ldr r2, [pc, #80] ; (80002ac <HAL_MspInit+0x5c>)
800025c: f043 0301 orr.w r3, r3, #1
8000260: 6193 str r3, [r2, #24]
8000262: 4b12 ldr r3, [pc, #72] ; (80002ac <HAL_MspInit+0x5c>)
8000264: 699b ldr r3, [r3, #24]
8000266: f003 0301 and.w r3, r3, #1
800026a: 60bb str r3, [r7, #8]
800026c: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800026e: 4b0f ldr r3, [pc, #60] ; (80002ac <HAL_MspInit+0x5c>)
8000270: 69db ldr r3, [r3, #28]
8000272: 4a0e ldr r2, [pc, #56] ; (80002ac <HAL_MspInit+0x5c>)
8000274: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000278: 61d3 str r3, [r2, #28]
800027a: 4b0c ldr r3, [pc, #48] ; (80002ac <HAL_MspInit+0x5c>)
800027c: 69db ldr r3, [r3, #28]
800027e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000282: 607b str r3, [r7, #4]
8000284: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8000286: 4b0a ldr r3, [pc, #40] ; (80002b0 <HAL_MspInit+0x60>)
8000288: 685b ldr r3, [r3, #4]
800028a: 60fb str r3, [r7, #12]
800028c: 68fb ldr r3, [r7, #12]
800028e: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
8000292: 60fb str r3, [r7, #12]
8000294: 68fb ldr r3, [r7, #12]
8000296: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800029a: 60fb str r3, [r7, #12]
800029c: 4a04 ldr r2, [pc, #16] ; (80002b0 <HAL_MspInit+0x60>)
800029e: 68fb ldr r3, [r7, #12]
80002a0: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80002a2: bf00 nop
80002a4: 3714 adds r7, #20
80002a6: 46bd mov sp, r7
80002a8: bc80 pop {r7}
80002aa: 4770 bx lr
80002ac: 40021000 .word 0x40021000
80002b0: 40010000 .word 0x40010000
080002b4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80002b4: b480 push {r7}
80002b6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80002b8: e7fe b.n 80002b8 <NMI_Handler+0x4>
080002ba <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80002ba: b480 push {r7}
80002bc: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80002be: e7fe b.n 80002be <HardFault_Handler+0x4>
080002c0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80002c0: b480 push {r7}
80002c2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80002c4: e7fe b.n 80002c4 <MemManage_Handler+0x4>
080002c6 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80002c6: b480 push {r7}
80002c8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80002ca: e7fe b.n 80002ca <BusFault_Handler+0x4>
080002cc <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80002cc: b480 push {r7}
80002ce: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80002d0: e7fe b.n 80002d0 <UsageFault_Handler+0x4>
080002d2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80002d2: b480 push {r7}
80002d4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80002d6: bf00 nop
80002d8: 46bd mov sp, r7
80002da: bc80 pop {r7}
80002dc: 4770 bx lr
080002de <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80002de: b480 push {r7}
80002e0: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80002e2: bf00 nop
80002e4: 46bd mov sp, r7
80002e6: bc80 pop {r7}
80002e8: 4770 bx lr
080002ea <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80002ea: b480 push {r7}
80002ec: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80002ee: bf00 nop
80002f0: 46bd mov sp, r7
80002f2: bc80 pop {r7}
80002f4: 4770 bx lr
080002f6 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80002f6: b580 push {r7, lr}
80002f8: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80002fa: f000 f875 bl 80003e8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80002fe: bf00 nop
8000300: bd80 pop {r7, pc}
08000302 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8000302: b480 push {r7}
8000304: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000306: bf00 nop
8000308: 46bd mov sp, r7
800030a: bc80 pop {r7}
800030c: 4770 bx lr
...
08000310 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000310: 480c ldr r0, [pc, #48] ; (8000344 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8000312: 490d ldr r1, [pc, #52] ; (8000348 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8000314: 4a0d ldr r2, [pc, #52] ; (800034c <LoopFillZerobss+0x1a>)
movs r3, #0
8000316: 2300 movs r3, #0
b LoopCopyDataInit
8000318: e002 b.n 8000320 <LoopCopyDataInit>
0800031a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800031a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800031c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800031e: 3304 adds r3, #4
08000320 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000320: 18c4 adds r4, r0, r3
cmp r4, r1
8000322: 428c cmp r4, r1
bcc CopyDataInit
8000324: d3f9 bcc.n 800031a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000326: 4a0a ldr r2, [pc, #40] ; (8000350 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8000328: 4c0a ldr r4, [pc, #40] ; (8000354 <LoopFillZerobss+0x22>)
movs r3, #0
800032a: 2300 movs r3, #0
b LoopFillZerobss
800032c: e001 b.n 8000332 <LoopFillZerobss>
0800032e <FillZerobss>:
FillZerobss:
str r3, [r2]
800032e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000330: 3204 adds r2, #4
08000332 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000332: 42a2 cmp r2, r4
bcc FillZerobss
8000334: d3fb bcc.n 800032e <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000336: f7ff ffe4 bl 8000302 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800033a: f000 fd3d bl 8000db8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800033e: f7ff ff05 bl 800014c <main>
bx lr
8000342: 4770 bx lr
ldr r0, =_sdata
8000344: 20000000 .word 0x20000000
ldr r1, =_edata
8000348: 2000000c .word 0x2000000c
ldr r2, =_sidata
800034c: 08000e50 .word 0x08000e50
ldr r2, =_sbss
8000350: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000354: 2000002c .word 0x2000002c
08000358 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000358: e7fe b.n 8000358 <ADC1_2_IRQHandler>
...
0800035c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800035c: b580 push {r7, lr}
800035e: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000360: 4b08 ldr r3, [pc, #32] ; (8000384 <HAL_Init+0x28>)
8000362: 681b ldr r3, [r3, #0]
8000364: 4a07 ldr r2, [pc, #28] ; (8000384 <HAL_Init+0x28>)
8000366: f043 0310 orr.w r3, r3, #16
800036a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800036c: 2003 movs r0, #3
800036e: f000 f907 bl 8000580 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000372: 200f movs r0, #15
8000374: f000 f808 bl 8000388 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000378: f7ff ff6a bl 8000250 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800037c: 2300 movs r3, #0
}
800037e: 4618 mov r0, r3
8000380: bd80 pop {r7, pc}
8000382: bf00 nop
8000384: 40022000 .word 0x40022000
08000388 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000388: b580 push {r7, lr}
800038a: b082 sub sp, #8
800038c: af00 add r7, sp, #0
800038e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000390: 4b12 ldr r3, [pc, #72] ; (80003dc <HAL_InitTick+0x54>)
8000392: 681a ldr r2, [r3, #0]
8000394: 4b12 ldr r3, [pc, #72] ; (80003e0 <HAL_InitTick+0x58>)
8000396: 781b ldrb r3, [r3, #0]
8000398: 4619 mov r1, r3
800039a: f44f 737a mov.w r3, #1000 ; 0x3e8
800039e: fbb3 f3f1 udiv r3, r3, r1
80003a2: fbb2 f3f3 udiv r3, r2, r3
80003a6: 4618 mov r0, r3
80003a8: f000 f911 bl 80005ce <HAL_SYSTICK_Config>
80003ac: 4603 mov r3, r0
80003ae: 2b00 cmp r3, #0
80003b0: d001 beq.n 80003b6 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
80003b2: 2301 movs r3, #1
80003b4: e00e b.n 80003d4 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80003b6: 687b ldr r3, [r7, #4]
80003b8: 2b0f cmp r3, #15
80003ba: d80a bhi.n 80003d2 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80003bc: 2200 movs r2, #0
80003be: 6879 ldr r1, [r7, #4]
80003c0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
80003c4: f000 f8e7 bl 8000596 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80003c8: 4a06 ldr r2, [pc, #24] ; (80003e4 <HAL_InitTick+0x5c>)
80003ca: 687b ldr r3, [r7, #4]
80003cc: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80003ce: 2300 movs r3, #0
80003d0: e000 b.n 80003d4 <HAL_InitTick+0x4c>
return HAL_ERROR;
80003d2: 2301 movs r3, #1
}
80003d4: 4618 mov r0, r3
80003d6: 3708 adds r7, #8
80003d8: 46bd mov sp, r7
80003da: bd80 pop {r7, pc}
80003dc: 20000000 .word 0x20000000
80003e0: 20000008 .word 0x20000008
80003e4: 20000004 .word 0x20000004
080003e8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80003e8: b480 push {r7}
80003ea: af00 add r7, sp, #0
uwTick += uwTickFreq;
80003ec: 4b05 ldr r3, [pc, #20] ; (8000404 <HAL_IncTick+0x1c>)
80003ee: 781b ldrb r3, [r3, #0]
80003f0: 461a mov r2, r3
80003f2: 4b05 ldr r3, [pc, #20] ; (8000408 <HAL_IncTick+0x20>)
80003f4: 681b ldr r3, [r3, #0]
80003f6: 4413 add r3, r2
80003f8: 4a03 ldr r2, [pc, #12] ; (8000408 <HAL_IncTick+0x20>)
80003fa: 6013 str r3, [r2, #0]
}
80003fc: bf00 nop
80003fe: 46bd mov sp, r7
8000400: bc80 pop {r7}
8000402: 4770 bx lr
8000404: 20000008 .word 0x20000008
8000408: 20000028 .word 0x20000028
0800040c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800040c: b480 push {r7}
800040e: af00 add r7, sp, #0
return uwTick;
8000410: 4b02 ldr r3, [pc, #8] ; (800041c <HAL_GetTick+0x10>)
8000412: 681b ldr r3, [r3, #0]
}
8000414: 4618 mov r0, r3
8000416: 46bd mov sp, r7
8000418: bc80 pop {r7}
800041a: 4770 bx lr
800041c: 20000028 .word 0x20000028
08000420 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000420: b480 push {r7}
8000422: b085 sub sp, #20
8000424: af00 add r7, sp, #0
8000426: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000428: 687b ldr r3, [r7, #4]
800042a: f003 0307 and.w r3, r3, #7
800042e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000430: 4b0c ldr r3, [pc, #48] ; (8000464 <__NVIC_SetPriorityGrouping+0x44>)
8000432: 68db ldr r3, [r3, #12]
8000434: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000436: 68ba ldr r2, [r7, #8]
8000438: f64f 03ff movw r3, #63743 ; 0xf8ff
800043c: 4013 ands r3, r2
800043e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000440: 68fb ldr r3, [r7, #12]
8000442: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000444: 68bb ldr r3, [r7, #8]
8000446: 4313 orrs r3, r2
reg_value = (reg_value |
8000448: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
800044c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000450: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000452: 4a04 ldr r2, [pc, #16] ; (8000464 <__NVIC_SetPriorityGrouping+0x44>)
8000454: 68bb ldr r3, [r7, #8]
8000456: 60d3 str r3, [r2, #12]
}
8000458: bf00 nop
800045a: 3714 adds r7, #20
800045c: 46bd mov sp, r7
800045e: bc80 pop {r7}
8000460: 4770 bx lr
8000462: bf00 nop
8000464: e000ed00 .word 0xe000ed00
08000468 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000468: b480 push {r7}
800046a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
800046c: 4b04 ldr r3, [pc, #16] ; (8000480 <__NVIC_GetPriorityGrouping+0x18>)
800046e: 68db ldr r3, [r3, #12]
8000470: 0a1b lsrs r3, r3, #8
8000472: f003 0307 and.w r3, r3, #7
}
8000476: 4618 mov r0, r3
8000478: 46bd mov sp, r7
800047a: bc80 pop {r7}
800047c: 4770 bx lr
800047e: bf00 nop
8000480: e000ed00 .word 0xe000ed00
08000484 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000484: b480 push {r7}
8000486: b083 sub sp, #12
8000488: af00 add r7, sp, #0
800048a: 4603 mov r3, r0
800048c: 6039 str r1, [r7, #0]
800048e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000490: f997 3007 ldrsb.w r3, [r7, #7]
8000494: 2b00 cmp r3, #0
8000496: db0a blt.n 80004ae <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000498: 683b ldr r3, [r7, #0]
800049a: b2da uxtb r2, r3
800049c: 490c ldr r1, [pc, #48] ; (80004d0 <__NVIC_SetPriority+0x4c>)
800049e: f997 3007 ldrsb.w r3, [r7, #7]
80004a2: 0112 lsls r2, r2, #4
80004a4: b2d2 uxtb r2, r2
80004a6: 440b add r3, r1
80004a8: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80004ac: e00a b.n 80004c4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80004ae: 683b ldr r3, [r7, #0]
80004b0: b2da uxtb r2, r3
80004b2: 4908 ldr r1, [pc, #32] ; (80004d4 <__NVIC_SetPriority+0x50>)
80004b4: 79fb ldrb r3, [r7, #7]
80004b6: f003 030f and.w r3, r3, #15
80004ba: 3b04 subs r3, #4
80004bc: 0112 lsls r2, r2, #4
80004be: b2d2 uxtb r2, r2
80004c0: 440b add r3, r1
80004c2: 761a strb r2, [r3, #24]
}
80004c4: bf00 nop
80004c6: 370c adds r7, #12
80004c8: 46bd mov sp, r7
80004ca: bc80 pop {r7}
80004cc: 4770 bx lr
80004ce: bf00 nop
80004d0: e000e100 .word 0xe000e100
80004d4: e000ed00 .word 0xe000ed00
080004d8 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80004d8: b480 push {r7}
80004da: b089 sub sp, #36 ; 0x24
80004dc: af00 add r7, sp, #0
80004de: 60f8 str r0, [r7, #12]
80004e0: 60b9 str r1, [r7, #8]
80004e2: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80004e4: 68fb ldr r3, [r7, #12]
80004e6: f003 0307 and.w r3, r3, #7
80004ea: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80004ec: 69fb ldr r3, [r7, #28]
80004ee: f1c3 0307 rsb r3, r3, #7
80004f2: 2b04 cmp r3, #4
80004f4: bf28 it cs
80004f6: 2304 movcs r3, #4
80004f8: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80004fa: 69fb ldr r3, [r7, #28]
80004fc: 3304 adds r3, #4
80004fe: 2b06 cmp r3, #6
8000500: d902 bls.n 8000508 <NVIC_EncodePriority+0x30>
8000502: 69fb ldr r3, [r7, #28]
8000504: 3b03 subs r3, #3
8000506: e000 b.n 800050a <NVIC_EncodePriority+0x32>
8000508: 2300 movs r3, #0
800050a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800050c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8000510: 69bb ldr r3, [r7, #24]
8000512: fa02 f303 lsl.w r3, r2, r3
8000516: 43da mvns r2, r3
8000518: 68bb ldr r3, [r7, #8]
800051a: 401a ands r2, r3
800051c: 697b ldr r3, [r7, #20]
800051e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000520: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
8000524: 697b ldr r3, [r7, #20]
8000526: fa01 f303 lsl.w r3, r1, r3
800052a: 43d9 mvns r1, r3
800052c: 687b ldr r3, [r7, #4]
800052e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000530: 4313 orrs r3, r2
);
}
8000532: 4618 mov r0, r3
8000534: 3724 adds r7, #36 ; 0x24
8000536: 46bd mov sp, r7
8000538: bc80 pop {r7}
800053a: 4770 bx lr
0800053c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800053c: b580 push {r7, lr}
800053e: b082 sub sp, #8
8000540: af00 add r7, sp, #0
8000542: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000544: 687b ldr r3, [r7, #4]
8000546: 3b01 subs r3, #1
8000548: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
800054c: d301 bcc.n 8000552 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800054e: 2301 movs r3, #1
8000550: e00f b.n 8000572 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000552: 4a0a ldr r2, [pc, #40] ; (800057c <SysTick_Config+0x40>)
8000554: 687b ldr r3, [r7, #4]
8000556: 3b01 subs r3, #1
8000558: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800055a: 210f movs r1, #15
800055c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8000560: f7ff ff90 bl 8000484 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000564: 4b05 ldr r3, [pc, #20] ; (800057c <SysTick_Config+0x40>)
8000566: 2200 movs r2, #0
8000568: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800056a: 4b04 ldr r3, [pc, #16] ; (800057c <SysTick_Config+0x40>)
800056c: 2207 movs r2, #7
800056e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000570: 2300 movs r3, #0
}
8000572: 4618 mov r0, r3
8000574: 3708 adds r7, #8
8000576: 46bd mov sp, r7
8000578: bd80 pop {r7, pc}
800057a: bf00 nop
800057c: e000e010 .word 0xe000e010
08000580 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000580: b580 push {r7, lr}
8000582: b082 sub sp, #8
8000584: af00 add r7, sp, #0
8000586: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000588: 6878 ldr r0, [r7, #4]
800058a: f7ff ff49 bl 8000420 <__NVIC_SetPriorityGrouping>
}
800058e: bf00 nop
8000590: 3708 adds r7, #8
8000592: 46bd mov sp, r7
8000594: bd80 pop {r7, pc}
08000596 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000596: b580 push {r7, lr}
8000598: b086 sub sp, #24
800059a: af00 add r7, sp, #0
800059c: 4603 mov r3, r0
800059e: 60b9 str r1, [r7, #8]
80005a0: 607a str r2, [r7, #4]
80005a2: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80005a4: 2300 movs r3, #0
80005a6: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80005a8: f7ff ff5e bl 8000468 <__NVIC_GetPriorityGrouping>
80005ac: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80005ae: 687a ldr r2, [r7, #4]
80005b0: 68b9 ldr r1, [r7, #8]
80005b2: 6978 ldr r0, [r7, #20]
80005b4: f7ff ff90 bl 80004d8 <NVIC_EncodePriority>
80005b8: 4602 mov r2, r0
80005ba: f997 300f ldrsb.w r3, [r7, #15]
80005be: 4611 mov r1, r2
80005c0: 4618 mov r0, r3
80005c2: f7ff ff5f bl 8000484 <__NVIC_SetPriority>
}
80005c6: bf00 nop
80005c8: 3718 adds r7, #24
80005ca: 46bd mov sp, r7
80005cc: bd80 pop {r7, pc}
080005ce <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80005ce: b580 push {r7, lr}
80005d0: b082 sub sp, #8
80005d2: af00 add r7, sp, #0
80005d4: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80005d6: 6878 ldr r0, [r7, #4]
80005d8: f7ff ffb0 bl 800053c <SysTick_Config>
80005dc: 4603 mov r3, r0
}
80005de: 4618 mov r0, r3
80005e0: 3708 adds r7, #8
80005e2: 46bd mov sp, r7
80005e4: bd80 pop {r7, pc}
...
080005e8 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80005e8: b580 push {r7, lr}
80005ea: b086 sub sp, #24
80005ec: af00 add r7, sp, #0
80005ee: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80005f0: 687b ldr r3, [r7, #4]
80005f2: 2b00 cmp r3, #0
80005f4: d101 bne.n 80005fa <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80005f6: 2301 movs r3, #1
80005f8: e26c b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80005fa: 687b ldr r3, [r7, #4]
80005fc: 681b ldr r3, [r3, #0]
80005fe: f003 0301 and.w r3, r3, #1
8000602: 2b00 cmp r3, #0
8000604: f000 8087 beq.w 8000716 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000608: 4b92 ldr r3, [pc, #584] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800060a: 685b ldr r3, [r3, #4]
800060c: f003 030c and.w r3, r3, #12
8000610: 2b04 cmp r3, #4
8000612: d00c beq.n 800062e <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000614: 4b8f ldr r3, [pc, #572] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000616: 685b ldr r3, [r3, #4]
8000618: f003 030c and.w r3, r3, #12
800061c: 2b08 cmp r3, #8
800061e: d112 bne.n 8000646 <HAL_RCC_OscConfig+0x5e>
8000620: 4b8c ldr r3, [pc, #560] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000622: 685b ldr r3, [r3, #4]
8000624: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000628: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800062c: d10b bne.n 8000646 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800062e: 4b89 ldr r3, [pc, #548] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000630: 681b ldr r3, [r3, #0]
8000632: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000636: 2b00 cmp r3, #0
8000638: d06c beq.n 8000714 <HAL_RCC_OscConfig+0x12c>
800063a: 687b ldr r3, [r7, #4]
800063c: 685b ldr r3, [r3, #4]
800063e: 2b00 cmp r3, #0
8000640: d168 bne.n 8000714 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000642: 2301 movs r3, #1
8000644: e246 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000646: 687b ldr r3, [r7, #4]
8000648: 685b ldr r3, [r3, #4]
800064a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800064e: d106 bne.n 800065e <HAL_RCC_OscConfig+0x76>
8000650: 4b80 ldr r3, [pc, #512] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000652: 681b ldr r3, [r3, #0]
8000654: 4a7f ldr r2, [pc, #508] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000656: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800065a: 6013 str r3, [r2, #0]
800065c: e02e b.n 80006bc <HAL_RCC_OscConfig+0xd4>
800065e: 687b ldr r3, [r7, #4]
8000660: 685b ldr r3, [r3, #4]
8000662: 2b00 cmp r3, #0
8000664: d10c bne.n 8000680 <HAL_RCC_OscConfig+0x98>
8000666: 4b7b ldr r3, [pc, #492] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000668: 681b ldr r3, [r3, #0]
800066a: 4a7a ldr r2, [pc, #488] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800066c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000670: 6013 str r3, [r2, #0]
8000672: 4b78 ldr r3, [pc, #480] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000674: 681b ldr r3, [r3, #0]
8000676: 4a77 ldr r2, [pc, #476] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000678: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800067c: 6013 str r3, [r2, #0]
800067e: e01d b.n 80006bc <HAL_RCC_OscConfig+0xd4>
8000680: 687b ldr r3, [r7, #4]
8000682: 685b ldr r3, [r3, #4]
8000684: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000688: d10c bne.n 80006a4 <HAL_RCC_OscConfig+0xbc>
800068a: 4b72 ldr r3, [pc, #456] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800068c: 681b ldr r3, [r3, #0]
800068e: 4a71 ldr r2, [pc, #452] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000690: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000694: 6013 str r3, [r2, #0]
8000696: 4b6f ldr r3, [pc, #444] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000698: 681b ldr r3, [r3, #0]
800069a: 4a6e ldr r2, [pc, #440] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800069c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80006a0: 6013 str r3, [r2, #0]
80006a2: e00b b.n 80006bc <HAL_RCC_OscConfig+0xd4>
80006a4: 4b6b ldr r3, [pc, #428] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80006a6: 681b ldr r3, [r3, #0]
80006a8: 4a6a ldr r2, [pc, #424] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80006aa: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80006ae: 6013 str r3, [r2, #0]
80006b0: 4b68 ldr r3, [pc, #416] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80006b2: 681b ldr r3, [r3, #0]
80006b4: 4a67 ldr r2, [pc, #412] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80006b6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
80006ba: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80006bc: 687b ldr r3, [r7, #4]
80006be: 685b ldr r3, [r3, #4]
80006c0: 2b00 cmp r3, #0
80006c2: d013 beq.n 80006ec <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80006c4: f7ff fea2 bl 800040c <HAL_GetTick>
80006c8: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80006ca: e008 b.n 80006de <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80006cc: f7ff fe9e bl 800040c <HAL_GetTick>
80006d0: 4602 mov r2, r0
80006d2: 693b ldr r3, [r7, #16]
80006d4: 1ad3 subs r3, r2, r3
80006d6: 2b64 cmp r3, #100 ; 0x64
80006d8: d901 bls.n 80006de <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
80006da: 2303 movs r3, #3
80006dc: e1fa b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80006de: 4b5d ldr r3, [pc, #372] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80006e0: 681b ldr r3, [r3, #0]
80006e2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80006e6: 2b00 cmp r3, #0
80006e8: d0f0 beq.n 80006cc <HAL_RCC_OscConfig+0xe4>
80006ea: e014 b.n 8000716 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80006ec: f7ff fe8e bl 800040c <HAL_GetTick>
80006f0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80006f2: e008 b.n 8000706 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80006f4: f7ff fe8a bl 800040c <HAL_GetTick>
80006f8: 4602 mov r2, r0
80006fa: 693b ldr r3, [r7, #16]
80006fc: 1ad3 subs r3, r2, r3
80006fe: 2b64 cmp r3, #100 ; 0x64
8000700: d901 bls.n 8000706 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000702: 2303 movs r3, #3
8000704: e1e6 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000706: 4b53 ldr r3, [pc, #332] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000708: 681b ldr r3, [r3, #0]
800070a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800070e: 2b00 cmp r3, #0
8000710: d1f0 bne.n 80006f4 <HAL_RCC_OscConfig+0x10c>
8000712: e000 b.n 8000716 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000714: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000716: 687b ldr r3, [r7, #4]
8000718: 681b ldr r3, [r3, #0]
800071a: f003 0302 and.w r3, r3, #2
800071e: 2b00 cmp r3, #0
8000720: d063 beq.n 80007ea <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000722: 4b4c ldr r3, [pc, #304] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000724: 685b ldr r3, [r3, #4]
8000726: f003 030c and.w r3, r3, #12
800072a: 2b00 cmp r3, #0
800072c: d00b beq.n 8000746 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
800072e: 4b49 ldr r3, [pc, #292] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000730: 685b ldr r3, [r3, #4]
8000732: f003 030c and.w r3, r3, #12
8000736: 2b08 cmp r3, #8
8000738: d11c bne.n 8000774 <HAL_RCC_OscConfig+0x18c>
800073a: 4b46 ldr r3, [pc, #280] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800073c: 685b ldr r3, [r3, #4]
800073e: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000742: 2b00 cmp r3, #0
8000744: d116 bne.n 8000774 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000746: 4b43 ldr r3, [pc, #268] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000748: 681b ldr r3, [r3, #0]
800074a: f003 0302 and.w r3, r3, #2
800074e: 2b00 cmp r3, #0
8000750: d005 beq.n 800075e <HAL_RCC_OscConfig+0x176>
8000752: 687b ldr r3, [r7, #4]
8000754: 691b ldr r3, [r3, #16]
8000756: 2b01 cmp r3, #1
8000758: d001 beq.n 800075e <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
800075a: 2301 movs r3, #1
800075c: e1ba b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800075e: 4b3d ldr r3, [pc, #244] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000760: 681b ldr r3, [r3, #0]
8000762: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000766: 687b ldr r3, [r7, #4]
8000768: 695b ldr r3, [r3, #20]
800076a: 00db lsls r3, r3, #3
800076c: 4939 ldr r1, [pc, #228] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800076e: 4313 orrs r3, r2
8000770: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000772: e03a b.n 80007ea <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000774: 687b ldr r3, [r7, #4]
8000776: 691b ldr r3, [r3, #16]
8000778: 2b00 cmp r3, #0
800077a: d020 beq.n 80007be <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800077c: 4b36 ldr r3, [pc, #216] ; (8000858 <HAL_RCC_OscConfig+0x270>)
800077e: 2201 movs r2, #1
8000780: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000782: f7ff fe43 bl 800040c <HAL_GetTick>
8000786: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000788: e008 b.n 800079c <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800078a: f7ff fe3f bl 800040c <HAL_GetTick>
800078e: 4602 mov r2, r0
8000790: 693b ldr r3, [r7, #16]
8000792: 1ad3 subs r3, r2, r3
8000794: 2b02 cmp r3, #2
8000796: d901 bls.n 800079c <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000798: 2303 movs r3, #3
800079a: e19b b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800079c: 4b2d ldr r3, [pc, #180] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
800079e: 681b ldr r3, [r3, #0]
80007a0: f003 0302 and.w r3, r3, #2
80007a4: 2b00 cmp r3, #0
80007a6: d0f0 beq.n 800078a <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80007a8: 4b2a ldr r3, [pc, #168] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80007aa: 681b ldr r3, [r3, #0]
80007ac: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80007b0: 687b ldr r3, [r7, #4]
80007b2: 695b ldr r3, [r3, #20]
80007b4: 00db lsls r3, r3, #3
80007b6: 4927 ldr r1, [pc, #156] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80007b8: 4313 orrs r3, r2
80007ba: 600b str r3, [r1, #0]
80007bc: e015 b.n 80007ea <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80007be: 4b26 ldr r3, [pc, #152] ; (8000858 <HAL_RCC_OscConfig+0x270>)
80007c0: 2200 movs r2, #0
80007c2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80007c4: f7ff fe22 bl 800040c <HAL_GetTick>
80007c8: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80007ca: e008 b.n 80007de <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80007cc: f7ff fe1e bl 800040c <HAL_GetTick>
80007d0: 4602 mov r2, r0
80007d2: 693b ldr r3, [r7, #16]
80007d4: 1ad3 subs r3, r2, r3
80007d6: 2b02 cmp r3, #2
80007d8: d901 bls.n 80007de <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
80007da: 2303 movs r3, #3
80007dc: e17a b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80007de: 4b1d ldr r3, [pc, #116] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
80007e0: 681b ldr r3, [r3, #0]
80007e2: f003 0302 and.w r3, r3, #2
80007e6: 2b00 cmp r3, #0
80007e8: d1f0 bne.n 80007cc <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80007ea: 687b ldr r3, [r7, #4]
80007ec: 681b ldr r3, [r3, #0]
80007ee: f003 0308 and.w r3, r3, #8
80007f2: 2b00 cmp r3, #0
80007f4: d03a beq.n 800086c <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80007f6: 687b ldr r3, [r7, #4]
80007f8: 699b ldr r3, [r3, #24]
80007fa: 2b00 cmp r3, #0
80007fc: d019 beq.n 8000832 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80007fe: 4b17 ldr r3, [pc, #92] ; (800085c <HAL_RCC_OscConfig+0x274>)
8000800: 2201 movs r2, #1
8000802: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000804: f7ff fe02 bl 800040c <HAL_GetTick>
8000808: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800080a: e008 b.n 800081e <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800080c: f7ff fdfe bl 800040c <HAL_GetTick>
8000810: 4602 mov r2, r0
8000812: 693b ldr r3, [r7, #16]
8000814: 1ad3 subs r3, r2, r3
8000816: 2b02 cmp r3, #2
8000818: d901 bls.n 800081e <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
800081a: 2303 movs r3, #3
800081c: e15a b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800081e: 4b0d ldr r3, [pc, #52] ; (8000854 <HAL_RCC_OscConfig+0x26c>)
8000820: 6a5b ldr r3, [r3, #36] ; 0x24
8000822: f003 0302 and.w r3, r3, #2
8000826: 2b00 cmp r3, #0
8000828: d0f0 beq.n 800080c <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
800082a: 2001 movs r0, #1
800082c: f000 faa6 bl 8000d7c <RCC_Delay>
8000830: e01c b.n 800086c <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000832: 4b0a ldr r3, [pc, #40] ; (800085c <HAL_RCC_OscConfig+0x274>)
8000834: 2200 movs r2, #0
8000836: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000838: f7ff fde8 bl 800040c <HAL_GetTick>
800083c: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800083e: e00f b.n 8000860 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000840: f7ff fde4 bl 800040c <HAL_GetTick>
8000844: 4602 mov r2, r0
8000846: 693b ldr r3, [r7, #16]
8000848: 1ad3 subs r3, r2, r3
800084a: 2b02 cmp r3, #2
800084c: d908 bls.n 8000860 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
800084e: 2303 movs r3, #3
8000850: e140 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
8000852: bf00 nop
8000854: 40021000 .word 0x40021000
8000858: 42420000 .word 0x42420000
800085c: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000860: 4b9e ldr r3, [pc, #632] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000862: 6a5b ldr r3, [r3, #36] ; 0x24
8000864: f003 0302 and.w r3, r3, #2
8000868: 2b00 cmp r3, #0
800086a: d1e9 bne.n 8000840 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800086c: 687b ldr r3, [r7, #4]
800086e: 681b ldr r3, [r3, #0]
8000870: f003 0304 and.w r3, r3, #4
8000874: 2b00 cmp r3, #0
8000876: f000 80a6 beq.w 80009c6 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
800087a: 2300 movs r3, #0
800087c: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800087e: 4b97 ldr r3, [pc, #604] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000880: 69db ldr r3, [r3, #28]
8000882: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000886: 2b00 cmp r3, #0
8000888: d10d bne.n 80008a6 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
800088a: 4b94 ldr r3, [pc, #592] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
800088c: 69db ldr r3, [r3, #28]
800088e: 4a93 ldr r2, [pc, #588] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000890: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000894: 61d3 str r3, [r2, #28]
8000896: 4b91 ldr r3, [pc, #580] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000898: 69db ldr r3, [r3, #28]
800089a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800089e: 60bb str r3, [r7, #8]
80008a0: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80008a2: 2301 movs r3, #1
80008a4: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80008a6: 4b8e ldr r3, [pc, #568] ; (8000ae0 <HAL_RCC_OscConfig+0x4f8>)
80008a8: 681b ldr r3, [r3, #0]
80008aa: f403 7380 and.w r3, r3, #256 ; 0x100
80008ae: 2b00 cmp r3, #0
80008b0: d118 bne.n 80008e4 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80008b2: 4b8b ldr r3, [pc, #556] ; (8000ae0 <HAL_RCC_OscConfig+0x4f8>)
80008b4: 681b ldr r3, [r3, #0]
80008b6: 4a8a ldr r2, [pc, #552] ; (8000ae0 <HAL_RCC_OscConfig+0x4f8>)
80008b8: f443 7380 orr.w r3, r3, #256 ; 0x100
80008bc: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80008be: f7ff fda5 bl 800040c <HAL_GetTick>
80008c2: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80008c4: e008 b.n 80008d8 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80008c6: f7ff fda1 bl 800040c <HAL_GetTick>
80008ca: 4602 mov r2, r0
80008cc: 693b ldr r3, [r7, #16]
80008ce: 1ad3 subs r3, r2, r3
80008d0: 2b64 cmp r3, #100 ; 0x64
80008d2: d901 bls.n 80008d8 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
80008d4: 2303 movs r3, #3
80008d6: e0fd b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80008d8: 4b81 ldr r3, [pc, #516] ; (8000ae0 <HAL_RCC_OscConfig+0x4f8>)
80008da: 681b ldr r3, [r3, #0]
80008dc: f403 7380 and.w r3, r3, #256 ; 0x100
80008e0: 2b00 cmp r3, #0
80008e2: d0f0 beq.n 80008c6 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80008e4: 687b ldr r3, [r7, #4]
80008e6: 68db ldr r3, [r3, #12]
80008e8: 2b01 cmp r3, #1
80008ea: d106 bne.n 80008fa <HAL_RCC_OscConfig+0x312>
80008ec: 4b7b ldr r3, [pc, #492] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
80008ee: 6a1b ldr r3, [r3, #32]
80008f0: 4a7a ldr r2, [pc, #488] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
80008f2: f043 0301 orr.w r3, r3, #1
80008f6: 6213 str r3, [r2, #32]
80008f8: e02d b.n 8000956 <HAL_RCC_OscConfig+0x36e>
80008fa: 687b ldr r3, [r7, #4]
80008fc: 68db ldr r3, [r3, #12]
80008fe: 2b00 cmp r3, #0
8000900: d10c bne.n 800091c <HAL_RCC_OscConfig+0x334>
8000902: 4b76 ldr r3, [pc, #472] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000904: 6a1b ldr r3, [r3, #32]
8000906: 4a75 ldr r2, [pc, #468] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000908: f023 0301 bic.w r3, r3, #1
800090c: 6213 str r3, [r2, #32]
800090e: 4b73 ldr r3, [pc, #460] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000910: 6a1b ldr r3, [r3, #32]
8000912: 4a72 ldr r2, [pc, #456] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000914: f023 0304 bic.w r3, r3, #4
8000918: 6213 str r3, [r2, #32]
800091a: e01c b.n 8000956 <HAL_RCC_OscConfig+0x36e>
800091c: 687b ldr r3, [r7, #4]
800091e: 68db ldr r3, [r3, #12]
8000920: 2b05 cmp r3, #5
8000922: d10c bne.n 800093e <HAL_RCC_OscConfig+0x356>
8000924: 4b6d ldr r3, [pc, #436] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000926: 6a1b ldr r3, [r3, #32]
8000928: 4a6c ldr r2, [pc, #432] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
800092a: f043 0304 orr.w r3, r3, #4
800092e: 6213 str r3, [r2, #32]
8000930: 4b6a ldr r3, [pc, #424] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000932: 6a1b ldr r3, [r3, #32]
8000934: 4a69 ldr r2, [pc, #420] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000936: f043 0301 orr.w r3, r3, #1
800093a: 6213 str r3, [r2, #32]
800093c: e00b b.n 8000956 <HAL_RCC_OscConfig+0x36e>
800093e: 4b67 ldr r3, [pc, #412] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000940: 6a1b ldr r3, [r3, #32]
8000942: 4a66 ldr r2, [pc, #408] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000944: f023 0301 bic.w r3, r3, #1
8000948: 6213 str r3, [r2, #32]
800094a: 4b64 ldr r3, [pc, #400] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
800094c: 6a1b ldr r3, [r3, #32]
800094e: 4a63 ldr r2, [pc, #396] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000950: f023 0304 bic.w r3, r3, #4
8000954: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000956: 687b ldr r3, [r7, #4]
8000958: 68db ldr r3, [r3, #12]
800095a: 2b00 cmp r3, #0
800095c: d015 beq.n 800098a <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800095e: f7ff fd55 bl 800040c <HAL_GetTick>
8000962: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000964: e00a b.n 800097c <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000966: f7ff fd51 bl 800040c <HAL_GetTick>
800096a: 4602 mov r2, r0
800096c: 693b ldr r3, [r7, #16]
800096e: 1ad3 subs r3, r2, r3
8000970: f241 3288 movw r2, #5000 ; 0x1388
8000974: 4293 cmp r3, r2
8000976: d901 bls.n 800097c <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8000978: 2303 movs r3, #3
800097a: e0ab b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800097c: 4b57 ldr r3, [pc, #348] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
800097e: 6a1b ldr r3, [r3, #32]
8000980: f003 0302 and.w r3, r3, #2
8000984: 2b00 cmp r3, #0
8000986: d0ee beq.n 8000966 <HAL_RCC_OscConfig+0x37e>
8000988: e014 b.n 80009b4 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800098a: f7ff fd3f bl 800040c <HAL_GetTick>
800098e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000990: e00a b.n 80009a8 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000992: f7ff fd3b bl 800040c <HAL_GetTick>
8000996: 4602 mov r2, r0
8000998: 693b ldr r3, [r7, #16]
800099a: 1ad3 subs r3, r2, r3
800099c: f241 3288 movw r2, #5000 ; 0x1388
80009a0: 4293 cmp r3, r2
80009a2: d901 bls.n 80009a8 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
80009a4: 2303 movs r3, #3
80009a6: e095 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80009a8: 4b4c ldr r3, [pc, #304] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
80009aa: 6a1b ldr r3, [r3, #32]
80009ac: f003 0302 and.w r3, r3, #2
80009b0: 2b00 cmp r3, #0
80009b2: d1ee bne.n 8000992 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
80009b4: 7dfb ldrb r3, [r7, #23]
80009b6: 2b01 cmp r3, #1
80009b8: d105 bne.n 80009c6 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
80009ba: 4b48 ldr r3, [pc, #288] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
80009bc: 69db ldr r3, [r3, #28]
80009be: 4a47 ldr r2, [pc, #284] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
80009c0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80009c4: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80009c6: 687b ldr r3, [r7, #4]
80009c8: 69db ldr r3, [r3, #28]
80009ca: 2b00 cmp r3, #0
80009cc: f000 8081 beq.w 8000ad2 <HAL_RCC_OscConfig+0x4ea>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80009d0: 4b42 ldr r3, [pc, #264] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
80009d2: 685b ldr r3, [r3, #4]
80009d4: f003 030c and.w r3, r3, #12
80009d8: 2b08 cmp r3, #8
80009da: d061 beq.n 8000aa0 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80009dc: 687b ldr r3, [r7, #4]
80009de: 69db ldr r3, [r3, #28]
80009e0: 2b02 cmp r3, #2
80009e2: d146 bne.n 8000a72 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80009e4: 4b3f ldr r3, [pc, #252] ; (8000ae4 <HAL_RCC_OscConfig+0x4fc>)
80009e6: 2200 movs r2, #0
80009e8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80009ea: f7ff fd0f bl 800040c <HAL_GetTick>
80009ee: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80009f0: e008 b.n 8000a04 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80009f2: f7ff fd0b bl 800040c <HAL_GetTick>
80009f6: 4602 mov r2, r0
80009f8: 693b ldr r3, [r7, #16]
80009fa: 1ad3 subs r3, r2, r3
80009fc: 2b02 cmp r3, #2
80009fe: d901 bls.n 8000a04 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8000a00: 2303 movs r3, #3
8000a02: e067 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000a04: 4b35 ldr r3, [pc, #212] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a06: 681b ldr r3, [r3, #0]
8000a08: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000a0c: 2b00 cmp r3, #0
8000a0e: d1f0 bne.n 80009f2 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8000a10: 687b ldr r3, [r7, #4]
8000a12: 6a1b ldr r3, [r3, #32]
8000a14: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000a18: d108 bne.n 8000a2c <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8000a1a: 4b30 ldr r3, [pc, #192] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a1c: 685b ldr r3, [r3, #4]
8000a1e: f423 3200 bic.w r2, r3, #131072 ; 0x20000
8000a22: 687b ldr r3, [r7, #4]
8000a24: 689b ldr r3, [r3, #8]
8000a26: 492d ldr r1, [pc, #180] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a28: 4313 orrs r3, r2
8000a2a: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000a2c: 4b2b ldr r3, [pc, #172] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a2e: 685b ldr r3, [r3, #4]
8000a30: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
8000a34: 687b ldr r3, [r7, #4]
8000a36: 6a19 ldr r1, [r3, #32]
8000a38: 687b ldr r3, [r7, #4]
8000a3a: 6a5b ldr r3, [r3, #36] ; 0x24
8000a3c: 430b orrs r3, r1
8000a3e: 4927 ldr r1, [pc, #156] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a40: 4313 orrs r3, r2
8000a42: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8000a44: 4b27 ldr r3, [pc, #156] ; (8000ae4 <HAL_RCC_OscConfig+0x4fc>)
8000a46: 2201 movs r2, #1
8000a48: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a4a: f7ff fcdf bl 800040c <HAL_GetTick>
8000a4e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000a50: e008 b.n 8000a64 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000a52: f7ff fcdb bl 800040c <HAL_GetTick>
8000a56: 4602 mov r2, r0
8000a58: 693b ldr r3, [r7, #16]
8000a5a: 1ad3 subs r3, r2, r3
8000a5c: 2b02 cmp r3, #2
8000a5e: d901 bls.n 8000a64 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8000a60: 2303 movs r3, #3
8000a62: e037 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000a64: 4b1d ldr r3, [pc, #116] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a66: 681b ldr r3, [r3, #0]
8000a68: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000a6c: 2b00 cmp r3, #0
8000a6e: d0f0 beq.n 8000a52 <HAL_RCC_OscConfig+0x46a>
8000a70: e02f b.n 8000ad2 <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000a72: 4b1c ldr r3, [pc, #112] ; (8000ae4 <HAL_RCC_OscConfig+0x4fc>)
8000a74: 2200 movs r2, #0
8000a76: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a78: f7ff fcc8 bl 800040c <HAL_GetTick>
8000a7c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000a7e: e008 b.n 8000a92 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000a80: f7ff fcc4 bl 800040c <HAL_GetTick>
8000a84: 4602 mov r2, r0
8000a86: 693b ldr r3, [r7, #16]
8000a88: 1ad3 subs r3, r2, r3
8000a8a: 2b02 cmp r3, #2
8000a8c: d901 bls.n 8000a92 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8000a8e: 2303 movs r3, #3
8000a90: e020 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000a92: 4b12 ldr r3, [pc, #72] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000a94: 681b ldr r3, [r3, #0]
8000a96: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000a9a: 2b00 cmp r3, #0
8000a9c: d1f0 bne.n 8000a80 <HAL_RCC_OscConfig+0x498>
8000a9e: e018 b.n 8000ad2 <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8000aa0: 687b ldr r3, [r7, #4]
8000aa2: 69db ldr r3, [r3, #28]
8000aa4: 2b01 cmp r3, #1
8000aa6: d101 bne.n 8000aac <HAL_RCC_OscConfig+0x4c4>
{
return HAL_ERROR;
8000aa8: 2301 movs r3, #1
8000aaa: e013 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8000aac: 4b0b ldr r3, [pc, #44] ; (8000adc <HAL_RCC_OscConfig+0x4f4>)
8000aae: 685b ldr r3, [r3, #4]
8000ab0: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000ab2: 68fb ldr r3, [r7, #12]
8000ab4: f403 3280 and.w r2, r3, #65536 ; 0x10000
8000ab8: 687b ldr r3, [r7, #4]
8000aba: 6a1b ldr r3, [r3, #32]
8000abc: 429a cmp r2, r3
8000abe: d106 bne.n 8000ace <HAL_RCC_OscConfig+0x4e6>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8000ac0: 68fb ldr r3, [r7, #12]
8000ac2: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8000ac6: 687b ldr r3, [r7, #4]
8000ac8: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000aca: 429a cmp r2, r3
8000acc: d001 beq.n 8000ad2 <HAL_RCC_OscConfig+0x4ea>
{
return HAL_ERROR;
8000ace: 2301 movs r3, #1
8000ad0: e000 b.n 8000ad4 <HAL_RCC_OscConfig+0x4ec>
}
}
}
}
return HAL_OK;
8000ad2: 2300 movs r3, #0
}
8000ad4: 4618 mov r0, r3
8000ad6: 3718 adds r7, #24
8000ad8: 46bd mov sp, r7
8000ada: bd80 pop {r7, pc}
8000adc: 40021000 .word 0x40021000
8000ae0: 40007000 .word 0x40007000
8000ae4: 42420060 .word 0x42420060
08000ae8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8000ae8: b580 push {r7, lr}
8000aea: b084 sub sp, #16
8000aec: af00 add r7, sp, #0
8000aee: 6078 str r0, [r7, #4]
8000af0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8000af2: 687b ldr r3, [r7, #4]
8000af4: 2b00 cmp r3, #0
8000af6: d101 bne.n 8000afc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8000af8: 2301 movs r3, #1
8000afa: e0d0 b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8000afc: 4b6a ldr r3, [pc, #424] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000afe: 681b ldr r3, [r3, #0]
8000b00: f003 0307 and.w r3, r3, #7
8000b04: 683a ldr r2, [r7, #0]
8000b06: 429a cmp r2, r3
8000b08: d910 bls.n 8000b2c <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000b0a: 4b67 ldr r3, [pc, #412] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000b0c: 681b ldr r3, [r3, #0]
8000b0e: f023 0207 bic.w r2, r3, #7
8000b12: 4965 ldr r1, [pc, #404] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000b14: 683b ldr r3, [r7, #0]
8000b16: 4313 orrs r3, r2
8000b18: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8000b1a: 4b63 ldr r3, [pc, #396] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000b1c: 681b ldr r3, [r3, #0]
8000b1e: f003 0307 and.w r3, r3, #7
8000b22: 683a ldr r2, [r7, #0]
8000b24: 429a cmp r2, r3
8000b26: d001 beq.n 8000b2c <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8000b28: 2301 movs r3, #1
8000b2a: e0b8 b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8000b2c: 687b ldr r3, [r7, #4]
8000b2e: 681b ldr r3, [r3, #0]
8000b30: f003 0302 and.w r3, r3, #2
8000b34: 2b00 cmp r3, #0
8000b36: d020 beq.n 8000b7a <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000b38: 687b ldr r3, [r7, #4]
8000b3a: 681b ldr r3, [r3, #0]
8000b3c: f003 0304 and.w r3, r3, #4
8000b40: 2b00 cmp r3, #0
8000b42: d005 beq.n 8000b50 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8000b44: 4b59 ldr r3, [pc, #356] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b46: 685b ldr r3, [r3, #4]
8000b48: 4a58 ldr r2, [pc, #352] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b4a: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8000b4e: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8000b50: 687b ldr r3, [r7, #4]
8000b52: 681b ldr r3, [r3, #0]
8000b54: f003 0308 and.w r3, r3, #8
8000b58: 2b00 cmp r3, #0
8000b5a: d005 beq.n 8000b68 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8000b5c: 4b53 ldr r3, [pc, #332] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b5e: 685b ldr r3, [r3, #4]
8000b60: 4a52 ldr r2, [pc, #328] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b62: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8000b66: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8000b68: 4b50 ldr r3, [pc, #320] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b6a: 685b ldr r3, [r3, #4]
8000b6c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8000b70: 687b ldr r3, [r7, #4]
8000b72: 689b ldr r3, [r3, #8]
8000b74: 494d ldr r1, [pc, #308] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b76: 4313 orrs r3, r2
8000b78: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8000b7a: 687b ldr r3, [r7, #4]
8000b7c: 681b ldr r3, [r3, #0]
8000b7e: f003 0301 and.w r3, r3, #1
8000b82: 2b00 cmp r3, #0
8000b84: d040 beq.n 8000c08 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8000b86: 687b ldr r3, [r7, #4]
8000b88: 685b ldr r3, [r3, #4]
8000b8a: 2b01 cmp r3, #1
8000b8c: d107 bne.n 8000b9e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000b8e: 4b47 ldr r3, [pc, #284] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000b90: 681b ldr r3, [r3, #0]
8000b92: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000b96: 2b00 cmp r3, #0
8000b98: d115 bne.n 8000bc6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8000b9a: 2301 movs r3, #1
8000b9c: e07f b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8000b9e: 687b ldr r3, [r7, #4]
8000ba0: 685b ldr r3, [r3, #4]
8000ba2: 2b02 cmp r3, #2
8000ba4: d107 bne.n 8000bb6 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000ba6: 4b41 ldr r3, [pc, #260] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000ba8: 681b ldr r3, [r3, #0]
8000baa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000bae: 2b00 cmp r3, #0
8000bb0: d109 bne.n 8000bc6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8000bb2: 2301 movs r3, #1
8000bb4: e073 b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000bb6: 4b3d ldr r3, [pc, #244] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000bb8: 681b ldr r3, [r3, #0]
8000bba: f003 0302 and.w r3, r3, #2
8000bbe: 2b00 cmp r3, #0
8000bc0: d101 bne.n 8000bc6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8000bc2: 2301 movs r3, #1
8000bc4: e06b b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8000bc6: 4b39 ldr r3, [pc, #228] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000bc8: 685b ldr r3, [r3, #4]
8000bca: f023 0203 bic.w r2, r3, #3
8000bce: 687b ldr r3, [r7, #4]
8000bd0: 685b ldr r3, [r3, #4]
8000bd2: 4936 ldr r1, [pc, #216] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000bd4: 4313 orrs r3, r2
8000bd6: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000bd8: f7ff fc18 bl 800040c <HAL_GetTick>
8000bdc: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8000bde: e00a b.n 8000bf6 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8000be0: f7ff fc14 bl 800040c <HAL_GetTick>
8000be4: 4602 mov r2, r0
8000be6: 68fb ldr r3, [r7, #12]
8000be8: 1ad3 subs r3, r2, r3
8000bea: f241 3288 movw r2, #5000 ; 0x1388
8000bee: 4293 cmp r3, r2
8000bf0: d901 bls.n 8000bf6 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8000bf2: 2303 movs r3, #3
8000bf4: e053 b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8000bf6: 4b2d ldr r3, [pc, #180] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000bf8: 685b ldr r3, [r3, #4]
8000bfa: f003 020c and.w r2, r3, #12
8000bfe: 687b ldr r3, [r7, #4]
8000c00: 685b ldr r3, [r3, #4]
8000c02: 009b lsls r3, r3, #2
8000c04: 429a cmp r2, r3
8000c06: d1eb bne.n 8000be0 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8000c08: 4b27 ldr r3, [pc, #156] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000c0a: 681b ldr r3, [r3, #0]
8000c0c: f003 0307 and.w r3, r3, #7
8000c10: 683a ldr r2, [r7, #0]
8000c12: 429a cmp r2, r3
8000c14: d210 bcs.n 8000c38 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000c16: 4b24 ldr r3, [pc, #144] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000c18: 681b ldr r3, [r3, #0]
8000c1a: f023 0207 bic.w r2, r3, #7
8000c1e: 4922 ldr r1, [pc, #136] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000c20: 683b ldr r3, [r7, #0]
8000c22: 4313 orrs r3, r2
8000c24: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8000c26: 4b20 ldr r3, [pc, #128] ; (8000ca8 <HAL_RCC_ClockConfig+0x1c0>)
8000c28: 681b ldr r3, [r3, #0]
8000c2a: f003 0307 and.w r3, r3, #7
8000c2e: 683a ldr r2, [r7, #0]
8000c30: 429a cmp r2, r3
8000c32: d001 beq.n 8000c38 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8000c34: 2301 movs r3, #1
8000c36: e032 b.n 8000c9e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000c38: 687b ldr r3, [r7, #4]
8000c3a: 681b ldr r3, [r3, #0]
8000c3c: f003 0304 and.w r3, r3, #4
8000c40: 2b00 cmp r3, #0
8000c42: d008 beq.n 8000c56 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8000c44: 4b19 ldr r3, [pc, #100] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000c46: 685b ldr r3, [r3, #4]
8000c48: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8000c4c: 687b ldr r3, [r7, #4]
8000c4e: 68db ldr r3, [r3, #12]
8000c50: 4916 ldr r1, [pc, #88] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000c52: 4313 orrs r3, r2
8000c54: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8000c56: 687b ldr r3, [r7, #4]
8000c58: 681b ldr r3, [r3, #0]
8000c5a: f003 0308 and.w r3, r3, #8
8000c5e: 2b00 cmp r3, #0
8000c60: d009 beq.n 8000c76 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8000c62: 4b12 ldr r3, [pc, #72] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000c64: 685b ldr r3, [r3, #4]
8000c66: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8000c6a: 687b ldr r3, [r7, #4]
8000c6c: 691b ldr r3, [r3, #16]
8000c6e: 00db lsls r3, r3, #3
8000c70: 490e ldr r1, [pc, #56] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000c72: 4313 orrs r3, r2
8000c74: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8000c76: f000 f821 bl 8000cbc <HAL_RCC_GetSysClockFreq>
8000c7a: 4602 mov r2, r0
8000c7c: 4b0b ldr r3, [pc, #44] ; (8000cac <HAL_RCC_ClockConfig+0x1c4>)
8000c7e: 685b ldr r3, [r3, #4]
8000c80: 091b lsrs r3, r3, #4
8000c82: f003 030f and.w r3, r3, #15
8000c86: 490a ldr r1, [pc, #40] ; (8000cb0 <HAL_RCC_ClockConfig+0x1c8>)
8000c88: 5ccb ldrb r3, [r1, r3]
8000c8a: fa22 f303 lsr.w r3, r2, r3
8000c8e: 4a09 ldr r2, [pc, #36] ; (8000cb4 <HAL_RCC_ClockConfig+0x1cc>)
8000c90: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8000c92: 4b09 ldr r3, [pc, #36] ; (8000cb8 <HAL_RCC_ClockConfig+0x1d0>)
8000c94: 681b ldr r3, [r3, #0]
8000c96: 4618 mov r0, r3
8000c98: f7ff fb76 bl 8000388 <HAL_InitTick>
return HAL_OK;
8000c9c: 2300 movs r3, #0
}
8000c9e: 4618 mov r0, r3
8000ca0: 3710 adds r7, #16
8000ca2: 46bd mov sp, r7
8000ca4: bd80 pop {r7, pc}
8000ca6: bf00 nop
8000ca8: 40022000 .word 0x40022000
8000cac: 40021000 .word 0x40021000
8000cb0: 08000e38 .word 0x08000e38
8000cb4: 20000000 .word 0x20000000
8000cb8: 20000004 .word 0x20000004
08000cbc <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8000cbc: b490 push {r4, r7}
8000cbe: b08a sub sp, #40 ; 0x28
8000cc0: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
8000cc2: 4b2a ldr r3, [pc, #168] ; (8000d6c <HAL_RCC_GetSysClockFreq+0xb0>)
8000cc4: 1d3c adds r4, r7, #4
8000cc6: cb0f ldmia r3, {r0, r1, r2, r3}
8000cc8: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
8000ccc: f240 2301 movw r3, #513 ; 0x201
8000cd0: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8000cd2: 2300 movs r3, #0
8000cd4: 61fb str r3, [r7, #28]
8000cd6: 2300 movs r3, #0
8000cd8: 61bb str r3, [r7, #24]
8000cda: 2300 movs r3, #0
8000cdc: 627b str r3, [r7, #36] ; 0x24
8000cde: 2300 movs r3, #0
8000ce0: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8000ce2: 2300 movs r3, #0
8000ce4: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8000ce6: 4b22 ldr r3, [pc, #136] ; (8000d70 <HAL_RCC_GetSysClockFreq+0xb4>)
8000ce8: 685b ldr r3, [r3, #4]
8000cea: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8000cec: 69fb ldr r3, [r7, #28]
8000cee: f003 030c and.w r3, r3, #12
8000cf2: 2b04 cmp r3, #4
8000cf4: d002 beq.n 8000cfc <HAL_RCC_GetSysClockFreq+0x40>
8000cf6: 2b08 cmp r3, #8
8000cf8: d003 beq.n 8000d02 <HAL_RCC_GetSysClockFreq+0x46>
8000cfa: e02d b.n 8000d58 <HAL_RCC_GetSysClockFreq+0x9c>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8000cfc: 4b1d ldr r3, [pc, #116] ; (8000d74 <HAL_RCC_GetSysClockFreq+0xb8>)
8000cfe: 623b str r3, [r7, #32]
break;
8000d00: e02d b.n 8000d5e <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8000d02: 69fb ldr r3, [r7, #28]
8000d04: 0c9b lsrs r3, r3, #18
8000d06: f003 030f and.w r3, r3, #15
8000d0a: f107 0228 add.w r2, r7, #40 ; 0x28
8000d0e: 4413 add r3, r2
8000d10: f813 3c24 ldrb.w r3, [r3, #-36]
8000d14: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8000d16: 69fb ldr r3, [r7, #28]
8000d18: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000d1c: 2b00 cmp r3, #0
8000d1e: d013 beq.n 8000d48 <HAL_RCC_GetSysClockFreq+0x8c>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8000d20: 4b13 ldr r3, [pc, #76] ; (8000d70 <HAL_RCC_GetSysClockFreq+0xb4>)
8000d22: 685b ldr r3, [r3, #4]
8000d24: 0c5b lsrs r3, r3, #17
8000d26: f003 0301 and.w r3, r3, #1
8000d2a: f107 0228 add.w r2, r7, #40 ; 0x28
8000d2e: 4413 add r3, r2
8000d30: f813 3c28 ldrb.w r3, [r3, #-40]
8000d34: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8000d36: 697b ldr r3, [r7, #20]
8000d38: 4a0e ldr r2, [pc, #56] ; (8000d74 <HAL_RCC_GetSysClockFreq+0xb8>)
8000d3a: fb02 f203 mul.w r2, r2, r3
8000d3e: 69bb ldr r3, [r7, #24]
8000d40: fbb2 f3f3 udiv r3, r2, r3
8000d44: 627b str r3, [r7, #36] ; 0x24
8000d46: e004 b.n 8000d52 <HAL_RCC_GetSysClockFreq+0x96>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8000d48: 697b ldr r3, [r7, #20]
8000d4a: 4a0b ldr r2, [pc, #44] ; (8000d78 <HAL_RCC_GetSysClockFreq+0xbc>)
8000d4c: fb02 f303 mul.w r3, r2, r3
8000d50: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
8000d52: 6a7b ldr r3, [r7, #36] ; 0x24
8000d54: 623b str r3, [r7, #32]
break;
8000d56: e002 b.n 8000d5e <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8000d58: 4b06 ldr r3, [pc, #24] ; (8000d74 <HAL_RCC_GetSysClockFreq+0xb8>)
8000d5a: 623b str r3, [r7, #32]
break;
8000d5c: bf00 nop
}
}
return sysclockfreq;
8000d5e: 6a3b ldr r3, [r7, #32]
}
8000d60: 4618 mov r0, r3
8000d62: 3728 adds r7, #40 ; 0x28
8000d64: 46bd mov sp, r7
8000d66: bc90 pop {r4, r7}
8000d68: 4770 bx lr
8000d6a: bf00 nop
8000d6c: 08000e28 .word 0x08000e28
8000d70: 40021000 .word 0x40021000
8000d74: 007a1200 .word 0x007a1200
8000d78: 003d0900 .word 0x003d0900
08000d7c <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8000d7c: b480 push {r7}
8000d7e: b085 sub sp, #20
8000d80: af00 add r7, sp, #0
8000d82: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8000d84: 4b0a ldr r3, [pc, #40] ; (8000db0 <RCC_Delay+0x34>)
8000d86: 681b ldr r3, [r3, #0]
8000d88: 4a0a ldr r2, [pc, #40] ; (8000db4 <RCC_Delay+0x38>)
8000d8a: fba2 2303 umull r2, r3, r2, r3
8000d8e: 0a5b lsrs r3, r3, #9
8000d90: 687a ldr r2, [r7, #4]
8000d92: fb02 f303 mul.w r3, r2, r3
8000d96: 60fb str r3, [r7, #12]
do
{
__NOP();
8000d98: bf00 nop
}
while (Delay --);
8000d9a: 68fb ldr r3, [r7, #12]
8000d9c: 1e5a subs r2, r3, #1
8000d9e: 60fa str r2, [r7, #12]
8000da0: 2b00 cmp r3, #0
8000da2: d1f9 bne.n 8000d98 <RCC_Delay+0x1c>
}
8000da4: bf00 nop
8000da6: bf00 nop
8000da8: 3714 adds r7, #20
8000daa: 46bd mov sp, r7
8000dac: bc80 pop {r7}
8000dae: 4770 bx lr
8000db0: 20000000 .word 0x20000000
8000db4: 10624dd3 .word 0x10624dd3
08000db8 <__libc_init_array>:
8000db8: b570 push {r4, r5, r6, lr}
8000dba: 2600 movs r6, #0
8000dbc: 4d0c ldr r5, [pc, #48] ; (8000df0 <__libc_init_array+0x38>)
8000dbe: 4c0d ldr r4, [pc, #52] ; (8000df4 <__libc_init_array+0x3c>)
8000dc0: 1b64 subs r4, r4, r5
8000dc2: 10a4 asrs r4, r4, #2
8000dc4: 42a6 cmp r6, r4
8000dc6: d109 bne.n 8000ddc <__libc_init_array+0x24>
8000dc8: f000 f822 bl 8000e10 <_init>
8000dcc: 2600 movs r6, #0
8000dce: 4d0a ldr r5, [pc, #40] ; (8000df8 <__libc_init_array+0x40>)
8000dd0: 4c0a ldr r4, [pc, #40] ; (8000dfc <__libc_init_array+0x44>)
8000dd2: 1b64 subs r4, r4, r5
8000dd4: 10a4 asrs r4, r4, #2
8000dd6: 42a6 cmp r6, r4
8000dd8: d105 bne.n 8000de6 <__libc_init_array+0x2e>
8000dda: bd70 pop {r4, r5, r6, pc}
8000ddc: f855 3b04 ldr.w r3, [r5], #4
8000de0: 4798 blx r3
8000de2: 3601 adds r6, #1
8000de4: e7ee b.n 8000dc4 <__libc_init_array+0xc>
8000de6: f855 3b04 ldr.w r3, [r5], #4
8000dea: 4798 blx r3
8000dec: 3601 adds r6, #1
8000dee: e7f2 b.n 8000dd6 <__libc_init_array+0x1e>
8000df0: 08000e48 .word 0x08000e48
8000df4: 08000e48 .word 0x08000e48
8000df8: 08000e48 .word 0x08000e48
8000dfc: 08000e4c .word 0x08000e4c
08000e00 <memset>:
8000e00: 4603 mov r3, r0
8000e02: 4402 add r2, r0
8000e04: 4293 cmp r3, r2
8000e06: d100 bne.n 8000e0a <memset+0xa>
8000e08: 4770 bx lr
8000e0a: f803 1b01 strb.w r1, [r3], #1
8000e0e: e7f9 b.n 8000e04 <memset+0x4>
08000e10 <_init>:
8000e10: b5f8 push {r3, r4, r5, r6, r7, lr}
8000e12: bf00 nop
8000e14: bcf8 pop {r3, r4, r5, r6, r7}
8000e16: bc08 pop {r3}
8000e18: 469e mov lr, r3
8000e1a: 4770 bx lr
08000e1c <_fini>:
8000e1c: b5f8 push {r3, r4, r5, r6, r7, lr}
8000e1e: bf00 nop
8000e20: bcf8 pop {r3, r4, r5, r6, r7}
8000e22: bc08 pop {r3}
8000e24: 469e mov lr, r3
8000e26: 4770 bx lr
Reference in New Issue View Git Blame Copy Permalink