From 0058af14cdc592ba177e38583aa56623468dab23 Mon Sep 17 00:00:00 2001
From: kevin <kevin@lmve.net>
Date: Fri, 17 Sep 2021 22:35:39 +0800
Subject: [PATCH] =?UTF-8?q?=E7=A1=AE=E5=AE=9A=E5=BC=95=E8=84=9A=E5=8A=9F?=
 =?UTF-8?q?=E8=83=BD?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 .cproject                                     |    8 +-
 .mxproject                                    |   16 +-
 .settings/stm32cubeide.project.prefs          |    4 +-
 Core/Inc/main.h                               |   18 +
 Core/Inc/stm32f0xx_hal_conf.h                 |    2 +-
 Core/Src/main.c                               |   87 +-
 Core/Src/stm32f0xx_hal_msp.c                  |   61 +
 Debug/Core/Src/main.d                         |    6 +
 Debug/Core/Src/main.su                        |    9 +-
 Debug/Core/Src/stm32f0xx_hal_msp.d            |    6 +
 Debug/Core/Src/stm32f0xx_hal_msp.su           |    2 +
 Debug/Core/Src/stm32f0xx_it.d                 |    6 +
 Debug/Core/Src/system_stm32f0xx.d             |    6 +
 .../STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d  |    6 +
 .../Src/stm32f0xx_hal_adc.d                   |   83 +
 .../Src/stm32f0xx_hal_adc.su                  |   28 +
 .../Src/stm32f0xx_hal_adc_ex.d                |   83 +
 .../Src/stm32f0xx_hal_adc_ex.su               |    1 +
 .../Src/stm32f0xx_hal_cortex.d                |    6 +
 .../Src/stm32f0xx_hal_dma.d                   |    6 +
 .../Src/stm32f0xx_hal_exti.d                  |    6 +
 .../Src/stm32f0xx_hal_flash.d                 |    6 +
 .../Src/stm32f0xx_hal_flash_ex.d              |    6 +
 .../Src/stm32f0xx_hal_gpio.d                  |    6 +
 .../Src/stm32f0xx_hal_i2c.d                   |    6 +
 .../Src/stm32f0xx_hal_i2c_ex.d                |    6 +
 .../Src/stm32f0xx_hal_pwr.d                   |    6 +
 .../Src/stm32f0xx_hal_pwr_ex.d                |    6 +
 .../Src/stm32f0xx_hal_rcc.d                   |    6 +
 .../Src/stm32f0xx_hal_rcc_ex.d                |    6 +
 .../Src/stm32f0xx_hal_tim.d                   |    6 +
 .../Src/stm32f0xx_hal_tim_ex.d                |    6 +
 .../STM32F0xx_HAL_Driver/Src/subdir.mk        |    6 +
 Debug/Motor_Controller.bin                    |  Bin 3936 -> 6388 bytes
 Debug/Motor_Controller.list                   | 4957 +++++++++++------
 Debug/Motor_Controller.map                    | 1031 ++--
 Debug/My_Soul/my_main.d                       |    6 +
 Debug/objects.list                            |    2 +
 .../Inc/stm32f0xx_hal_adc.h                   | 1019 ++++
 .../Inc/stm32f0xx_hal_adc_ex.h                |  299 +
 .../Src/stm32f0xx_hal_adc.c                   | 2497 +++++++++
 .../Src/stm32f0xx_hal_adc_ex.c                |  192 +
 Motor_Controller.ioc                          |   73 +-
 STM32F030F4PX_FLASH.ld                        |    4 +-
 44 files changed, 8616 insertions(+), 1986 deletions(-)
 create mode 100644 Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d
 create mode 100644 Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su
 create mode 100644 Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d
 create mode 100644 Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su
 create mode 100644 Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h
 create mode 100644 Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h
 create mode 100644 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
 create mode 100644 Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c

diff --git a/.cproject b/.cproject
index a1ee852..0bc7cf5 100644
--- a/.cproject
+++ b/.cproject
@@ -21,7 +21,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.503044650" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2082033962" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.641898970" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1183730318" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F030F4Px || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F030x6 ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1183730318" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F030F4Px || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/STM32F0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F0xx/Include ||  ||  || USE_HAL_DRIVER | STM32F030x6 ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.140773480" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Motor_Controller}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.922364228" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1853470241" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -73,8 +73,8 @@
 					</folderInfo>
 					<sourceEntries>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="My_Soul"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -100,7 +100,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1895286405" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1020982045" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1279839714" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1646973974" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F030F4Px || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F030x6 ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1646973974" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F030F4Px || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/STM32F0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F0xx/Include ||  ||  || USE_HAL_DRIVER | STM32F030x6 ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1870847758" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Motor_Controller}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.430936253" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.613593740" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -147,8 +147,8 @@
 					</folderInfo>
 					<sourceEntries>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="My_Soul"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
diff --git a/.mxproject b/.mxproject
index 5fe9988..deb844b 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,3 +1,11 @@
+[PreviousLibFiles]
+LibFiles=Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core/Src/main.c;Core/Src/stm32f0xx_it.c;Core/Src/stm32f0xx_hal_msp.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Core/Src/system_stm32f0xx.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Core/Src/system_stm32f0xx.c;;;
+HeaderPath=Drivers/STM32F0xx_HAL_Driver/Inc;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F0xx/Include;Drivers/CMSIS/Include;Core/Inc;
+CDefines=USE_HAL_DRIVER;STM32F030x6;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
 [PreviousGenFiles]
 AdvancedFolderStructure=true
 HeaderFileListSize=3
@@ -15,11 +23,3 @@ SourceFolderListSize=1
 SourcePath#0=/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller/Core/Src
 SourceFiles=;
 
-[PreviousLibFiles]
-LibFiles=Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;
-
-[PreviousUsedCubeIDEFiles]
-SourceFiles=Core/Src/main.c;Core/Src/stm32f0xx_it.c;Core/Src/stm32f0xx_hal_msp.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Core/Src/system_stm32f0xx.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Core/Src/system_stm32f0xx.c;;;
-HeaderPath=Drivers/STM32F0xx_HAL_Driver/Inc;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F0xx/Include;Drivers/CMSIS/Include;Core/Inc;
-CDefines=USE_HAL_DRIVER;STM32F030x6;USE_HAL_DRIVER;USE_HAL_DRIVER;
-
diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs
index 4a62201..89fb884 100644
--- a/.settings/stm32cubeide.project.prefs
+++ b/.settings/stm32cubeide.project.prefs
@@ -1,3 +1,3 @@
-8DF89ED150041C4CBC7CB9A9CAA90856=1C22DD7ADF2195BDF8650303BA7D1C7B
-DC22A860405A8BF2F2C095E5B6529F12=1C22DD7ADF2195BDF8650303BA7D1C7B
+8DF89ED150041C4CBC7CB9A9CAA90856=4CEDEAF73CDABB08FD3583A2D7D4A47A
+DC22A860405A8BF2F2C095E5B6529F12=4CEDEAF73CDABB08FD3583A2D7D4A47A
 eclipse.preferences.version=1
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 331c025..8018b3b 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -58,6 +58,24 @@ void Error_Handler(void);
 /* USER CODE END EFP */
 
 /* Private defines -----------------------------------------------------------*/
+#define MOTA_Pin GPIO_PIN_0
+#define MOTA_GPIO_Port GPIOF
+#define MOTB_Pin GPIO_PIN_1
+#define MOTB_GPIO_Port GPIOF
+#define HC595_DCK_Pin GPIO_PIN_3
+#define HC595_DCK_GPIO_Port GPIOA
+#define HC595_RCK_Pin GPIO_PIN_4
+#define HC595_RCK_GPIO_Port GPIOA
+#define HC595_SCK_Pin GPIO_PIN_5
+#define HC595_SCK_GPIO_Port GPIOA
+#define KEY1_Pin GPIO_PIN_6
+#define KEY1_GPIO_Port GPIOA
+#define KEY2_Pin GPIO_PIN_7
+#define KEY2_GPIO_Port GPIOA
+#define KEY3_Pin GPIO_PIN_9
+#define KEY3_GPIO_Port GPIOA
+#define KEY4_Pin GPIO_PIN_10
+#define KEY4_GPIO_Port GPIOA
 /* USER CODE BEGIN Private defines */
 
 /* USER CODE END Private defines */
diff --git a/Core/Inc/stm32f0xx_hal_conf.h b/Core/Inc/stm32f0xx_hal_conf.h
index 0606436..aee8d2d 100644
--- a/Core/Inc/stm32f0xx_hal_conf.h
+++ b/Core/Inc/stm32f0xx_hal_conf.h
@@ -32,7 +32,7 @@
   * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
-  /*#define HAL_ADC_MODULE_ENABLED   */
+  #define HAL_ADC_MODULE_ENABLED
 /*#define HAL_CRYP_MODULE_ENABLED   */
 /*#define HAL_CAN_MODULE_ENABLED   */
 /*#define HAL_CEC_MODULE_ENABLED   */
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 889d1dd..2562358 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -40,6 +40,7 @@
 /* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc;
 
 /* USER CODE BEGIN PV */
 
@@ -48,6 +49,7 @@
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
+static void MX_ADC_Init(void);
 /* USER CODE BEGIN PFP */
 
 /* USER CODE END PFP */
@@ -85,6 +87,7 @@ int main(void)
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
+  MX_ADC_Init();
   /* USER CODE BEGIN 2 */
   mymain();
   /* USER CODE END 2 */
@@ -112,9 +115,11 @@ void SystemClock_Config(void)
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14CalibrationValue = 16;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
@@ -137,6 +142,58 @@ void SystemClock_Config(void)
   }
 }
 
+/**
+  * @brief ADC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC_Init(void)
+{
+
+  /* USER CODE BEGIN ADC_Init 0 */
+
+  /* USER CODE END ADC_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC_Init 1 */
+
+  /* USER CODE END ADC_Init 1 */
+  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+  */
+  hadc.Instance = ADC1;
+  hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
+  hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc.Init.LowPowerAutoWait = DISABLE;
+  hadc.Init.LowPowerAutoPowerOff = DISABLE;
+  hadc.Init.ContinuousConvMode = DISABLE;
+  hadc.Init.DiscontinuousConvMode = DISABLE;
+  hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc.Init.DMAContinuousRequests = DISABLE;
+  hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  if (HAL_ADC_Init(&hadc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure for the selected ADC regular channel to be converted.
+  */
+  sConfig.Channel = ADC_CHANNEL_0;
+  sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC_Init 2 */
+
+  /* USER CODE END ADC_Init 2 */
+
+}
+
 /**
   * @brief GPIO Initialization Function
   * @param None
@@ -144,10 +201,38 @@ void SystemClock_Config(void)
   */
 static void MX_GPIO_Init(void)
 {
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
 
   /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : MOTA_Pin MOTB_Pin */
+  GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */
+  GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */
+  GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
 }
 
 /* USER CODE BEGIN 4 */
diff --git a/Core/Src/stm32f0xx_hal_msp.c b/Core/Src/stm32f0xx_hal_msp.c
index 2b1a5c9..cefb189 100644
--- a/Core/Src/stm32f0xx_hal_msp.c
+++ b/Core/Src/stm32f0xx_hal_msp.c
@@ -77,6 +77,67 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**ADC GPIO Configuration
+    PA0     ------> ADC_IN0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC1_CLK_DISABLE();
+
+    /**ADC GPIO Configuration
+    PA0     ------> ADC_IN0
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d
index 68a701a..31b2623 100644
--- a/Debug/Core/Src/main.d
+++ b/Debug/Core/Src/main.d
@@ -18,6 +18,8 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -66,6 +68,10 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su
index 6eee1a6..022fe05 100644
--- a/Debug/Core/Src/main.su
+++ b/Debug/Core/Src/main.su
@@ -1,4 +1,5 @@
-main.c:64:5:main	8	static
-main.c:107:6:SystemClock_Config	80	static
-main.c:145:13:MX_GPIO_Init	16	static
-main.c:161:6:Error_Handler	8	static,ignoring_inline_asm
+main.c:66:5:main	8	static
+main.c:110:6:SystemClock_Config	80	static
+main.c:150:13:MX_ADC_Init	24	static
+main.c:202:13:MX_GPIO_Init	48	static
+main.c:246:6:Error_Handler	8	static,ignoring_inline_asm
diff --git a/Debug/Core/Src/stm32f0xx_hal_msp.d b/Debug/Core/Src/stm32f0xx_hal_msp.d
index 62a4406..8389811 100644
--- a/Debug/Core/Src/stm32f0xx_hal_msp.d
+++ b/Debug/Core/Src/stm32f0xx_hal_msp.d
@@ -18,6 +18,8 @@ Core/Src/stm32f0xx_hal_msp.o: ../Core/Src/stm32f0xx_hal_msp.c \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -65,6 +67,10 @@ Core/Src/stm32f0xx_hal_msp.o: ../Core/Src/stm32f0xx_hal_msp.c \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Core/Src/stm32f0xx_hal_msp.su b/Debug/Core/Src/stm32f0xx_hal_msp.su
index 994fa07..5997029 100644
--- a/Debug/Core/Src/stm32f0xx_hal_msp.su
+++ b/Debug/Core/Src/stm32f0xx_hal_msp.su
@@ -1 +1,3 @@
 stm32f0xx_hal_msp.c:64:6:HAL_MspInit	16	static
+stm32f0xx_hal_msp.c:86:6:HAL_ADC_MspInit	56	static
+stm32f0xx_hal_msp.c:119:6:HAL_ADC_MspDeInit	16	static
diff --git a/Debug/Core/Src/stm32f0xx_it.d b/Debug/Core/Src/stm32f0xx_it.d
index d841325..fe06dea 100644
--- a/Debug/Core/Src/stm32f0xx_it.d
+++ b/Debug/Core/Src/stm32f0xx_it.d
@@ -18,6 +18,8 @@ Core/Src/stm32f0xx_it.o: ../Core/Src/stm32f0xx_it.c ../Core/Inc/main.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -66,6 +68,10 @@ Core/Src/stm32f0xx_it.o: ../Core/Src/stm32f0xx_it.c ../Core/Inc/main.h \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Core/Src/system_stm32f0xx.d b/Debug/Core/Src/system_stm32f0xx.d
index e20f9a2..a1c4da1 100644
--- a/Debug/Core/Src/system_stm32f0xx.d
+++ b/Debug/Core/Src/system_stm32f0xx.d
@@ -18,6 +18,8 @@ Core/Src/system_stm32f0xx.o: ../Core/Src/system_stm32f0xx.c \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -63,6 +65,10 @@ Core/Src/system_stm32f0xx.o: ../Core/Src/system_stm32f0xx.c \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d
index 9b32d12..b23db59 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d
new file mode 100644
index 0000000..c062fe6
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d
@@ -0,0 +1,83 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su
new file mode 100644
index 0000000..f828457
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su
@@ -0,0 +1,28 @@
+stm32f0xx_hal_adc.c:406:19:HAL_ADC_Init	24	static
+stm32f0xx_hal_adc.c:648:19:HAL_ADC_DeInit	32	static
+stm32f0xx_hal_adc.c:774:13:HAL_ADC_MspInit	16	static
+stm32f0xx_hal_adc.c:789:13:HAL_ADC_MspDeInit	16	static
+stm32f0xx_hal_adc.c:1027:19:HAL_ADC_Start	32	static
+stm32f0xx_hal_adc.c:1092:19:HAL_ADC_Stop	32	static
+stm32f0xx_hal_adc.c:1146:19:HAL_ADC_PollForConversion	24	static
+stm32f0xx_hal_adc.c:1270:19:HAL_ADC_PollForEvent	32	static
+stm32f0xx_hal_adc.c:1350:19:HAL_ADC_Start_IT	32	static
+stm32f0xx_hal_adc.c:1431:19:HAL_ADC_Stop_IT	32	static
+stm32f0xx_hal_adc.c:1484:19:HAL_ADC_Start_DMA	40	static
+stm32f0xx_hal_adc.c:1573:19:HAL_ADC_Stop_DMA	32	static
+stm32f0xx_hal_adc.c:1658:10:HAL_ADC_GetValue	16	static
+stm32f0xx_hal_adc.c:1675:6:HAL_ADC_IRQHandler	16	static
+stm32f0xx_hal_adc.c:1800:13:HAL_ADC_ConvCpltCallback	16	static
+stm32f0xx_hal_adc.c:1815:13:HAL_ADC_ConvHalfCpltCallback	16	static
+stm32f0xx_hal_adc.c:1830:13:HAL_ADC_LevelOutOfWindowCallback	16	static
+stm32f0xx_hal_adc.c:1846:13:HAL_ADC_ErrorCallback	16	static
+stm32f0xx_hal_adc.c:1900:19:HAL_ADC_ConfigChannel	24	static
+stm32f0xx_hal_adc.c:2033:19:HAL_ADC_AnalogWDGConfig	32	static
+stm32f0xx_hal_adc.c:2155:10:HAL_ADC_GetState	16	static
+stm32f0xx_hal_adc.c:2169:10:HAL_ADC_GetError	16	static
+stm32f0xx_hal_adc.c:2199:26:ADC_Enable	24	static
+stm32f0xx_hal_adc.c:2267:26:ADC_Disable	24	static
+stm32f0xx_hal_adc.c:2328:26:ADC_ConversionStop	24	static
+stm32f0xx_hal_adc.c:2382:13:ADC_DMAConvCplt	24	static
+stm32f0xx_hal_adc.c:2447:13:ADC_DMAHalfConvCplt	24	static
+stm32f0xx_hal_adc.c:2465:13:ADC_DMAError	24	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d
new file mode 100644
index 0000000..b9b3961
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d
@@ -0,0 +1,83 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su
new file mode 100644
index 0000000..fb018f0
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su
@@ -0,0 +1 @@
+stm32f0xx_hal_adc_ex.c:97:19:HAL_ADCEx_Calibration_Start	32	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d
index 750c6ff..73be8e1 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d
index 6158fa4..ded8165 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d
index 76b58f3..9d48420 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d
index 2eb18d4..d08deff 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d
index f2b6d4a..549efbf 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d
index 0cd7cbf..01b9ecb 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d
index 57698d8..976a54c 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d
index 9737ab8..9464de3 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d
index c8e0cad..a8fdcc1 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d
index 1f7f41d..1c9571c 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d
index a7478f5..7e0ea71 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d
index b2234db..1d4d538 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d
index 2949cd6..d7f6d4c 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d
index 2ccb2ad..b60b63e 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d
@@ -19,6 +19,8 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o: \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -64,6 +66,10 @@ Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o: \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
index 87ec920..26e37f6 100644
--- a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
@@ -6,6 +6,8 @@
 # Add inputs and outputs from these tool invocations to the build variables 
 C_SRCS += \
 ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c \
 ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c \
 ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c \
 ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c \
@@ -23,6 +25,8 @@ C_SRCS += \
 
 OBJS += \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o \
@@ -40,6 +44,8 @@ OBJS += \
 
 C_DEPS += \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d \
 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d \
diff --git a/Debug/Motor_Controller.bin b/Debug/Motor_Controller.bin
index ec30b6c93413148535e57e38a99e7c9f00ac8bc5..86c40ed831d96d0837b05aa2340e79036e06ddd0 100755
GIT binary patch
delta 3231
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R8?54EcYG2wKOOwR{{U$yLofgU

delta 789
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zTyy-H_(kis=4>^!xvQ|SweVYbdYRcbg;oz&qeANBsM4N?zW-)8Hx&HN6-e3u^9m-M
z*NJF=8w##D!(`Y1egzxOQPN`oi-JPm64{mY@jqq!*!PKK{sTLmmzFW+@{xxIn3nOC
zYnF@{B|#Z$t|ijw=soHkeBu^K)c{{RxZzHa_Xb$$An&<EG6qO@$}!JlrdMrlwoTAZ
zYLhE%+&o_}tIdmTjCloi%7KgCWtvYPqvQ=+2kD;}bKn*JcJCb;>bmE^75@1@F5niM

diff --git a/Debug/Motor_Controller.list b/Debug/Motor_Controller.list
index 8c7d681..ee43413 100644
--- a/Debug/Motor_Controller.list
+++ b/Debug/Motor_Controller.list
@@ -5,45 +5,45 @@ Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
   0 .isr_vector   000000c0  08000000  08000000  00010000  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         00000e5c  080000c0  080000c0  000100c0  2**2
+  1 .text         000017f0  080000c0  080000c0  000100c0  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       00000030  08000f1c  08000f1c  00010f1c  2**2
+  2 .rodata       00000030  080018b0  080018b0  000118b0  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .ARM.extab    00000000  08000f4c  08000f4c  0002000c  2**0
+  3 .ARM.extab    00000000  080018e0  080018e0  0002000c  2**0
                   CONTENTS
-  4 .ARM          00000000  08000f4c  08000f4c  0002000c  2**0
+  4 .ARM          00000000  080018e0  080018e0  0002000c  2**0
                   CONTENTS
-  5 .preinit_array 00000000  08000f4c  08000f4c  0002000c  2**0
+  5 .preinit_array 00000000  080018e0  080018e0  0002000c  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  6 .init_array   00000004  08000f4c  08000f4c  00010f4c  2**2
+  6 .init_array   00000004  080018e0  080018e0  000118e0  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  7 .fini_array   00000004  08000f50  08000f50  00010f50  2**2
+  7 .fini_array   00000004  080018e4  080018e4  000118e4  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  8 .data         0000000c  20000000  08000f54  00020000  2**2
+  8 .data         0000000c  20000000  080018e8  00020000  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  9 .bss          00000020  2000000c  08000f60  0002000c  2**2
+  9 .bss          00000060  2000000c  080018f4  0002000c  2**2
                   ALLOC
- 10 ._user_heap_stack 00000604  2000002c  08000f60  0002002c  2**0
+ 10 ._user_heap_stack 00000604  2000006c  080018f4  0002006c  2**0
                   ALLOC
  11 .ARM.attributes 00000028  00000000  00000000  0002000c  2**0
                   CONTENTS, READONLY
- 12 .debug_info   00002395  00000000  00000000  00020034  2**0
+ 12 .debug_info   00004405  00000000  00000000  00020034  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 13 .debug_abbrev 00000cb7  00000000  00000000  000223c9  2**0
+ 13 .debug_abbrev 0000116e  00000000  00000000  00024439  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 14 .debug_aranges 00000318  00000000  00000000  00023080  2**3
+ 14 .debug_aranges 00000480  00000000  00000000  000255a8  2**3
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_ranges 00000290  00000000  00000000  00023398  2**3
+ 15 .debug_ranges 000003d8  00000000  00000000  00025a28  2**3
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_macro  0000de81  00000000  00000000  00023628  2**0
+ 16 .debug_macro  0000e729  00000000  00000000  00025e00  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_line   000043b1  00000000  00000000  000314a9  2**0
+ 17 .debug_line   0000625a  00000000  00000000  00034529  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_str    0005322e  00000000  00000000  0003585a  2**0
+ 18 .debug_str    00056381  00000000  00000000  0003a783  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .comment      00000053  00000000  00000000  00088a88  2**0
+ 19 .comment      00000053  00000000  00000000  00090b04  2**0
                   CONTENTS, READONLY
- 20 .debug_frame  00000914  00000000  00000000  00088adc  2**2
+ 20 .debug_frame  00000e24  00000000  00000000  00090b58  2**2
                   CONTENTS, READONLY, DEBUGGING, OCTETS
 
 Disassembly of section .text:
@@ -65,7 +65,7 @@ Disassembly of section .text:
  80000da:	bd10      	pop	{r4, pc}
  80000dc:	2000000c 	.word	0x2000000c
  80000e0:	00000000 	.word	0x00000000
- 80000e4:	08000f04 	.word	0x08000f04
+ 80000e4:	08001898 	.word	0x08001898
 
 080000e8 <frame_dummy>:
  80000e8:	4b04      	ldr	r3, [pc, #16]	; (80000fc <frame_dummy+0x14>)
@@ -80,7 +80,7 @@ Disassembly of section .text:
  80000fa:	46c0      	nop			; (mov r8, r8)
  80000fc:	00000000 	.word	0x00000000
  8000100:	20000010 	.word	0x20000010
- 8000104:	08000f04 	.word	0x08000f04
+ 8000104:	08001898 	.word	0x08001898
 
 08000108 <__udivsi3>:
  8000108:	2200      	movs	r2, #0
@@ -242,2567 +242,4298 @@ int main(void)
 
   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
   HAL_Init();
- 8000224:	f000 f8da 	bl	80003dc <HAL_Init>
+ 8000224:	f000 f9e0 	bl	80005e8 <HAL_Init>
   /* USER CODE BEGIN Init */
 
   /* USER CODE END Init */
 
   /* Configure the system clock */
   SystemClock_Config();
- 8000228:	f000 f805 	bl	8000236 <SystemClock_Config>
+ 8000228:	f000 f807 	bl	800023a <SystemClock_Config>
   /* USER CODE BEGIN SysInit */
 
   /* USER CODE END SysInit */
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
- 800022c:	f000 f84e 	bl	80002cc <MX_GPIO_Init>
+ 800022c:	f000 f8b2 	bl	8000394 <MX_GPIO_Init>
+  MX_ADC_Init();
+ 8000230:	f000 f854 	bl	80002dc <MX_ADC_Init>
   /* USER CODE BEGIN 2 */
   mymain();
- 8000230:	f000 fe38 	bl	8000ea4 <mymain>
+ 8000234:	f001 fb00 	bl	8001838 <mymain>
   /* USER CODE END 2 */
 
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
   while (1)
- 8000234:	e7fe      	b.n	8000234 <main+0x14>
+ 8000238:	e7fe      	b.n	8000238 <main+0x18>
 
-08000236 <SystemClock_Config>:
+0800023a <SystemClock_Config>:
 /**
   * @brief System Clock Configuration
   * @retval None
   */
 void SystemClock_Config(void)
 {
- 8000236:	b590      	push	{r4, r7, lr}
- 8000238:	b091      	sub	sp, #68	; 0x44
- 800023a:	af00      	add	r7, sp, #0
+ 800023a:	b590      	push	{r4, r7, lr}
+ 800023c:	b091      	sub	sp, #68	; 0x44
+ 800023e:	af00      	add	r7, sp, #0
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 800023c:	2410      	movs	r4, #16
- 800023e:	193b      	adds	r3, r7, r4
- 8000240:	0018      	movs	r0, r3
- 8000242:	2330      	movs	r3, #48	; 0x30
- 8000244:	001a      	movs	r2, r3
- 8000246:	2100      	movs	r1, #0
- 8000248:	f000 fe54 	bl	8000ef4 <memset>
+ 8000240:	2410      	movs	r4, #16
+ 8000242:	193b      	adds	r3, r7, r4
+ 8000244:	0018      	movs	r0, r3
+ 8000246:	2330      	movs	r3, #48	; 0x30
+ 8000248:	001a      	movs	r2, r3
+ 800024a:	2100      	movs	r1, #0
+ 800024c:	f001 fb1c 	bl	8001888 <memset>
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 800024c:	003b      	movs	r3, r7
- 800024e:	0018      	movs	r0, r3
- 8000250:	2310      	movs	r3, #16
- 8000252:	001a      	movs	r2, r3
- 8000254:	2100      	movs	r1, #0
- 8000256:	f000 fe4d 	bl	8000ef4 <memset>
+ 8000250:	003b      	movs	r3, r7
+ 8000252:	0018      	movs	r0, r3
+ 8000254:	2310      	movs	r3, #16
+ 8000256:	001a      	movs	r2, r3
+ 8000258:	2100      	movs	r1, #0
+ 800025a:	f001 fb15 	bl	8001888 <memset>
 
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 800025a:	0021      	movs	r1, r4
- 800025c:	187b      	adds	r3, r7, r1
- 800025e:	2202      	movs	r2, #2
- 8000260:	601a      	str	r2, [r3, #0]
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14;
+ 800025e:	0021      	movs	r1, r4
+ 8000260:	187b      	adds	r3, r7, r1
+ 8000262:	2212      	movs	r2, #18
+ 8000264:	601a      	str	r2, [r3, #0]
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000262:	187b      	adds	r3, r7, r1
- 8000264:	2201      	movs	r2, #1
- 8000266:	60da      	str	r2, [r3, #12]
+ 8000266:	187b      	adds	r3, r7, r1
+ 8000268:	2201      	movs	r2, #1
+ 800026a:	60da      	str	r2, [r3, #12]
+  RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
+ 800026c:	187b      	adds	r3, r7, r1
+ 800026e:	2201      	movs	r2, #1
+ 8000270:	615a      	str	r2, [r3, #20]
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000268:	187b      	adds	r3, r7, r1
- 800026a:	2210      	movs	r2, #16
- 800026c:	611a      	str	r2, [r3, #16]
+ 8000272:	187b      	adds	r3, r7, r1
+ 8000274:	2210      	movs	r2, #16
+ 8000276:	611a      	str	r2, [r3, #16]
+  RCC_OscInitStruct.HSI14CalibrationValue = 16;
+ 8000278:	187b      	adds	r3, r7, r1
+ 800027a:	2210      	movs	r2, #16
+ 800027c:	619a      	str	r2, [r3, #24]
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- 800026e:	187b      	adds	r3, r7, r1
- 8000270:	2202      	movs	r2, #2
- 8000272:	621a      	str	r2, [r3, #32]
+ 800027e:	187b      	adds	r3, r7, r1
+ 8000280:	2202      	movs	r2, #2
+ 8000282:	621a      	str	r2, [r3, #32]
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- 8000274:	187b      	adds	r3, r7, r1
- 8000276:	2200      	movs	r2, #0
- 8000278:	625a      	str	r2, [r3, #36]	; 0x24
+ 8000284:	187b      	adds	r3, r7, r1
+ 8000286:	2200      	movs	r2, #0
+ 8000288:	625a      	str	r2, [r3, #36]	; 0x24
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
- 800027a:	187b      	adds	r3, r7, r1
- 800027c:	22a0      	movs	r2, #160	; 0xa0
- 800027e:	0392      	lsls	r2, r2, #14
- 8000280:	629a      	str	r2, [r3, #40]	; 0x28
+ 800028a:	187b      	adds	r3, r7, r1
+ 800028c:	22a0      	movs	r2, #160	; 0xa0
+ 800028e:	0392      	lsls	r2, r2, #14
+ 8000290:	629a      	str	r2, [r3, #40]	; 0x28
   RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
- 8000282:	187b      	adds	r3, r7, r1
- 8000284:	2200      	movs	r2, #0
- 8000286:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8000292:	187b      	adds	r3, r7, r1
+ 8000294:	2200      	movs	r2, #0
+ 8000296:	62da      	str	r2, [r3, #44]	; 0x2c
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8000288:	187b      	adds	r3, r7, r1
- 800028a:	0018      	movs	r0, r3
- 800028c:	f000 f9be 	bl	800060c <HAL_RCC_OscConfig>
- 8000290:	1e03      	subs	r3, r0, #0
- 8000292:	d001      	beq.n	8000298 <SystemClock_Config+0x62>
+ 8000298:	187b      	adds	r3, r7, r1
+ 800029a:	0018      	movs	r0, r3
+ 800029c:	f000 fe80 	bl	8000fa0 <HAL_RCC_OscConfig>
+ 80002a0:	1e03      	subs	r3, r0, #0
+ 80002a2:	d001      	beq.n	80002a8 <SystemClock_Config+0x6e>
   {
     Error_Handler();
- 8000294:	f000 f832 	bl	80002fc <Error_Handler>
+ 80002a4:	f000 f8ea 	bl	800047c <Error_Handler>
   }
   /** Initializes the CPU, AHB and APB buses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8000298:	003b      	movs	r3, r7
- 800029a:	2207      	movs	r2, #7
- 800029c:	601a      	str	r2, [r3, #0]
+ 80002a8:	003b      	movs	r3, r7
+ 80002aa:	2207      	movs	r2, #7
+ 80002ac:	601a      	str	r2, [r3, #0]
                               |RCC_CLOCKTYPE_PCLK1;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- 800029e:	003b      	movs	r3, r7
- 80002a0:	2202      	movs	r2, #2
- 80002a2:	605a      	str	r2, [r3, #4]
+ 80002ae:	003b      	movs	r3, r7
+ 80002b0:	2202      	movs	r2, #2
+ 80002b2:	605a      	str	r2, [r3, #4]
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 80002a4:	003b      	movs	r3, r7
- 80002a6:	2200      	movs	r2, #0
- 80002a8:	609a      	str	r2, [r3, #8]
+ 80002b4:	003b      	movs	r3, r7
+ 80002b6:	2200      	movs	r2, #0
+ 80002b8:	609a      	str	r2, [r3, #8]
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 80002aa:	003b      	movs	r3, r7
- 80002ac:	2200      	movs	r2, #0
- 80002ae:	60da      	str	r2, [r3, #12]
+ 80002ba:	003b      	movs	r3, r7
+ 80002bc:	2200      	movs	r2, #0
+ 80002be:	60da      	str	r2, [r3, #12]
 
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
- 80002b0:	003b      	movs	r3, r7
- 80002b2:	2101      	movs	r1, #1
- 80002b4:	0018      	movs	r0, r3
- 80002b6:	f000 fcc3 	bl	8000c40 <HAL_RCC_ClockConfig>
- 80002ba:	1e03      	subs	r3, r0, #0
- 80002bc:	d001      	beq.n	80002c2 <SystemClock_Config+0x8c>
+ 80002c0:	003b      	movs	r3, r7
+ 80002c2:	2101      	movs	r1, #1
+ 80002c4:	0018      	movs	r0, r3
+ 80002c6:	f001 f985 	bl	80015d4 <HAL_RCC_ClockConfig>
+ 80002ca:	1e03      	subs	r3, r0, #0
+ 80002cc:	d001      	beq.n	80002d2 <SystemClock_Config+0x98>
   {
     Error_Handler();
- 80002be:	f000 f81d 	bl	80002fc <Error_Handler>
+ 80002ce:	f000 f8d5 	bl	800047c <Error_Handler>
   }
 }
- 80002c2:	46c0      	nop			; (mov r8, r8)
- 80002c4:	46bd      	mov	sp, r7
- 80002c6:	b011      	add	sp, #68	; 0x44
- 80002c8:	bd90      	pop	{r4, r7, pc}
+ 80002d2:	46c0      	nop			; (mov r8, r8)
+ 80002d4:	46bd      	mov	sp, r7
+ 80002d6:	b011      	add	sp, #68	; 0x44
+ 80002d8:	bd90      	pop	{r4, r7, pc}
 	...
 
-080002cc <MX_GPIO_Init>:
+080002dc <MX_ADC_Init>:
+  * @brief ADC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC_Init(void)
+{
+ 80002dc:	b580      	push	{r7, lr}
+ 80002de:	b084      	sub	sp, #16
+ 80002e0:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN ADC_Init 0 */
+
+  /* USER CODE END ADC_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+ 80002e2:	1d3b      	adds	r3, r7, #4
+ 80002e4:	0018      	movs	r0, r3
+ 80002e6:	230c      	movs	r3, #12
+ 80002e8:	001a      	movs	r2, r3
+ 80002ea:	2100      	movs	r1, #0
+ 80002ec:	f001 facc 	bl	8001888 <memset>
+  /* USER CODE BEGIN ADC_Init 1 */
+
+  /* USER CODE END ADC_Init 1 */
+  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+  */
+  hadc.Instance = ADC1;
+ 80002f0:	4b26      	ldr	r3, [pc, #152]	; (800038c <MX_ADC_Init+0xb0>)
+ 80002f2:	4a27      	ldr	r2, [pc, #156]	; (8000390 <MX_ADC_Init+0xb4>)
+ 80002f4:	601a      	str	r2, [r3, #0]
+  hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+ 80002f6:	4b25      	ldr	r3, [pc, #148]	; (800038c <MX_ADC_Init+0xb0>)
+ 80002f8:	2200      	movs	r2, #0
+ 80002fa:	605a      	str	r2, [r3, #4]
+  hadc.Init.Resolution = ADC_RESOLUTION_12B;
+ 80002fc:	4b23      	ldr	r3, [pc, #140]	; (800038c <MX_ADC_Init+0xb0>)
+ 80002fe:	2200      	movs	r2, #0
+ 8000300:	609a      	str	r2, [r3, #8]
+  hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 8000302:	4b22      	ldr	r3, [pc, #136]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000304:	2200      	movs	r2, #0
+ 8000306:	60da      	str	r2, [r3, #12]
+  hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
+ 8000308:	4b20      	ldr	r3, [pc, #128]	; (800038c <MX_ADC_Init+0xb0>)
+ 800030a:	2201      	movs	r2, #1
+ 800030c:	611a      	str	r2, [r3, #16]
+  hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 800030e:	4b1f      	ldr	r3, [pc, #124]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000310:	2204      	movs	r2, #4
+ 8000312:	615a      	str	r2, [r3, #20]
+  hadc.Init.LowPowerAutoWait = DISABLE;
+ 8000314:	4b1d      	ldr	r3, [pc, #116]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000316:	2200      	movs	r2, #0
+ 8000318:	761a      	strb	r2, [r3, #24]
+  hadc.Init.LowPowerAutoPowerOff = DISABLE;
+ 800031a:	4b1c      	ldr	r3, [pc, #112]	; (800038c <MX_ADC_Init+0xb0>)
+ 800031c:	2200      	movs	r2, #0
+ 800031e:	765a      	strb	r2, [r3, #25]
+  hadc.Init.ContinuousConvMode = DISABLE;
+ 8000320:	4b1a      	ldr	r3, [pc, #104]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000322:	2200      	movs	r2, #0
+ 8000324:	769a      	strb	r2, [r3, #26]
+  hadc.Init.DiscontinuousConvMode = DISABLE;
+ 8000326:	4b19      	ldr	r3, [pc, #100]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000328:	2200      	movs	r2, #0
+ 800032a:	76da      	strb	r2, [r3, #27]
+  hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 800032c:	4b17      	ldr	r3, [pc, #92]	; (800038c <MX_ADC_Init+0xb0>)
+ 800032e:	22c2      	movs	r2, #194	; 0xc2
+ 8000330:	32ff      	adds	r2, #255	; 0xff
+ 8000332:	61da      	str	r2, [r3, #28]
+  hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 8000334:	4b15      	ldr	r3, [pc, #84]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000336:	2200      	movs	r2, #0
+ 8000338:	621a      	str	r2, [r3, #32]
+  hadc.Init.DMAContinuousRequests = DISABLE;
+ 800033a:	4b14      	ldr	r3, [pc, #80]	; (800038c <MX_ADC_Init+0xb0>)
+ 800033c:	2224      	movs	r2, #36	; 0x24
+ 800033e:	2100      	movs	r1, #0
+ 8000340:	5499      	strb	r1, [r3, r2]
+  hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 8000342:	4b12      	ldr	r3, [pc, #72]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000344:	2201      	movs	r2, #1
+ 8000346:	629a      	str	r2, [r3, #40]	; 0x28
+  if (HAL_ADC_Init(&hadc) != HAL_OK)
+ 8000348:	4b10      	ldr	r3, [pc, #64]	; (800038c <MX_ADC_Init+0xb0>)
+ 800034a:	0018      	movs	r0, r3
+ 800034c:	f000 f9b0 	bl	80006b0 <HAL_ADC_Init>
+ 8000350:	1e03      	subs	r3, r0, #0
+ 8000352:	d001      	beq.n	8000358 <MX_ADC_Init+0x7c>
+  {
+    Error_Handler();
+ 8000354:	f000 f892 	bl	800047c <Error_Handler>
+  }
+  /** Configure for the selected ADC regular channel to be converted.
+  */
+  sConfig.Channel = ADC_CHANNEL_0;
+ 8000358:	1d3b      	adds	r3, r7, #4
+ 800035a:	2200      	movs	r2, #0
+ 800035c:	601a      	str	r2, [r3, #0]
+  sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+ 800035e:	1d3b      	adds	r3, r7, #4
+ 8000360:	2280      	movs	r2, #128	; 0x80
+ 8000362:	0152      	lsls	r2, r2, #5
+ 8000364:	605a      	str	r2, [r3, #4]
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+ 8000366:	1d3b      	adds	r3, r7, #4
+ 8000368:	2280      	movs	r2, #128	; 0x80
+ 800036a:	0552      	lsls	r2, r2, #21
+ 800036c:	609a      	str	r2, [r3, #8]
+  if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
+ 800036e:	1d3a      	adds	r2, r7, #4
+ 8000370:	4b06      	ldr	r3, [pc, #24]	; (800038c <MX_ADC_Init+0xb0>)
+ 8000372:	0011      	movs	r1, r2
+ 8000374:	0018      	movs	r0, r3
+ 8000376:	f000 fadb 	bl	8000930 <HAL_ADC_ConfigChannel>
+ 800037a:	1e03      	subs	r3, r0, #0
+ 800037c:	d001      	beq.n	8000382 <MX_ADC_Init+0xa6>
+  {
+    Error_Handler();
+ 800037e:	f000 f87d 	bl	800047c <Error_Handler>
+  }
+  /* USER CODE BEGIN ADC_Init 2 */
+
+  /* USER CODE END ADC_Init 2 */
+
+}
+ 8000382:	46c0      	nop			; (mov r8, r8)
+ 8000384:	46bd      	mov	sp, r7
+ 8000386:	b004      	add	sp, #16
+ 8000388:	bd80      	pop	{r7, pc}
+ 800038a:	46c0      	nop			; (mov r8, r8)
+ 800038c:	20000028 	.word	0x20000028
+ 8000390:	40012400 	.word	0x40012400
+
+08000394 <MX_GPIO_Init>:
   * @brief GPIO Initialization Function
   * @param None
   * @retval None
   */
 static void MX_GPIO_Init(void)
 {
- 80002cc:	b580      	push	{r7, lr}
- 80002ce:	b082      	sub	sp, #8
- 80002d0:	af00      	add	r7, sp, #0
+ 8000394:	b590      	push	{r4, r7, lr}
+ 8000396:	b089      	sub	sp, #36	; 0x24
+ 8000398:	af00      	add	r7, sp, #0
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 800039a:	240c      	movs	r4, #12
+ 800039c:	193b      	adds	r3, r7, r4
+ 800039e:	0018      	movs	r0, r3
+ 80003a0:	2314      	movs	r3, #20
+ 80003a2:	001a      	movs	r2, r3
+ 80003a4:	2100      	movs	r1, #0
+ 80003a6:	f001 fa6f 	bl	8001888 <memset>
 
   /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 80003aa:	4b32      	ldr	r3, [pc, #200]	; (8000474 <MX_GPIO_Init+0xe0>)
+ 80003ac:	695a      	ldr	r2, [r3, #20]
+ 80003ae:	4b31      	ldr	r3, [pc, #196]	; (8000474 <MX_GPIO_Init+0xe0>)
+ 80003b0:	2180      	movs	r1, #128	; 0x80
+ 80003b2:	03c9      	lsls	r1, r1, #15
+ 80003b4:	430a      	orrs	r2, r1
+ 80003b6:	615a      	str	r2, [r3, #20]
+ 80003b8:	4b2e      	ldr	r3, [pc, #184]	; (8000474 <MX_GPIO_Init+0xe0>)
+ 80003ba:	695a      	ldr	r2, [r3, #20]
+ 80003bc:	2380      	movs	r3, #128	; 0x80
+ 80003be:	03db      	lsls	r3, r3, #15
+ 80003c0:	4013      	ands	r3, r2
+ 80003c2:	60bb      	str	r3, [r7, #8]
+ 80003c4:	68bb      	ldr	r3, [r7, #8]
   __HAL_RCC_GPIOA_CLK_ENABLE();
- 80002d2:	4b09      	ldr	r3, [pc, #36]	; (80002f8 <MX_GPIO_Init+0x2c>)
- 80002d4:	695a      	ldr	r2, [r3, #20]
- 80002d6:	4b08      	ldr	r3, [pc, #32]	; (80002f8 <MX_GPIO_Init+0x2c>)
- 80002d8:	2180      	movs	r1, #128	; 0x80
- 80002da:	0289      	lsls	r1, r1, #10
- 80002dc:	430a      	orrs	r2, r1
- 80002de:	615a      	str	r2, [r3, #20]
- 80002e0:	4b05      	ldr	r3, [pc, #20]	; (80002f8 <MX_GPIO_Init+0x2c>)
- 80002e2:	695a      	ldr	r2, [r3, #20]
- 80002e4:	2380      	movs	r3, #128	; 0x80
- 80002e6:	029b      	lsls	r3, r3, #10
- 80002e8:	4013      	ands	r3, r2
- 80002ea:	607b      	str	r3, [r7, #4]
- 80002ec:	687b      	ldr	r3, [r7, #4]
+ 80003c6:	4b2b      	ldr	r3, [pc, #172]	; (8000474 <MX_GPIO_Init+0xe0>)
+ 80003c8:	695a      	ldr	r2, [r3, #20]
+ 80003ca:	4b2a      	ldr	r3, [pc, #168]	; (8000474 <MX_GPIO_Init+0xe0>)
+ 80003cc:	2180      	movs	r1, #128	; 0x80
+ 80003ce:	0289      	lsls	r1, r1, #10
+ 80003d0:	430a      	orrs	r2, r1
+ 80003d2:	615a      	str	r2, [r3, #20]
+ 80003d4:	4b27      	ldr	r3, [pc, #156]	; (8000474 <MX_GPIO_Init+0xe0>)
+ 80003d6:	695a      	ldr	r2, [r3, #20]
+ 80003d8:	2380      	movs	r3, #128	; 0x80
+ 80003da:	029b      	lsls	r3, r3, #10
+ 80003dc:	4013      	ands	r3, r2
+ 80003de:	607b      	str	r3, [r7, #4]
+ 80003e0:	687b      	ldr	r3, [r7, #4]
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET);
+ 80003e2:	4b25      	ldr	r3, [pc, #148]	; (8000478 <MX_GPIO_Init+0xe4>)
+ 80003e4:	2200      	movs	r2, #0
+ 80003e6:	2103      	movs	r1, #3
+ 80003e8:	0018      	movs	r0, r3
+ 80003ea:	f000 fdbb 	bl	8000f64 <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET);
+ 80003ee:	2390      	movs	r3, #144	; 0x90
+ 80003f0:	05db      	lsls	r3, r3, #23
+ 80003f2:	2200      	movs	r2, #0
+ 80003f4:	2138      	movs	r1, #56	; 0x38
+ 80003f6:	0018      	movs	r0, r3
+ 80003f8:	f000 fdb4 	bl	8000f64 <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pins : MOTA_Pin MOTB_Pin */
+  GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin;
+ 80003fc:	193b      	adds	r3, r7, r4
+ 80003fe:	2203      	movs	r2, #3
+ 8000400:	601a      	str	r2, [r3, #0]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8000402:	193b      	adds	r3, r7, r4
+ 8000404:	2201      	movs	r2, #1
+ 8000406:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000408:	193b      	adds	r3, r7, r4
+ 800040a:	2200      	movs	r2, #0
+ 800040c:	609a      	str	r2, [r3, #8]
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ 800040e:	193b      	adds	r3, r7, r4
+ 8000410:	2203      	movs	r2, #3
+ 8000412:	60da      	str	r2, [r3, #12]
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 8000414:	193b      	adds	r3, r7, r4
+ 8000416:	4a18      	ldr	r2, [pc, #96]	; (8000478 <MX_GPIO_Init+0xe4>)
+ 8000418:	0019      	movs	r1, r3
+ 800041a:	0010      	movs	r0, r2
+ 800041c:	f000 fc32 	bl	8000c84 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */
+  GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin;
+ 8000420:	193b      	adds	r3, r7, r4
+ 8000422:	2238      	movs	r2, #56	; 0x38
+ 8000424:	601a      	str	r2, [r3, #0]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8000426:	193b      	adds	r3, r7, r4
+ 8000428:	2201      	movs	r2, #1
+ 800042a:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800042c:	193b      	adds	r3, r7, r4
+ 800042e:	2200      	movs	r2, #0
+ 8000430:	609a      	str	r2, [r3, #8]
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ 8000432:	193b      	adds	r3, r7, r4
+ 8000434:	2203      	movs	r2, #3
+ 8000436:	60da      	str	r2, [r3, #12]
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000438:	193a      	adds	r2, r7, r4
+ 800043a:	2390      	movs	r3, #144	; 0x90
+ 800043c:	05db      	lsls	r3, r3, #23
+ 800043e:	0011      	movs	r1, r2
+ 8000440:	0018      	movs	r0, r3
+ 8000442:	f000 fc1f 	bl	8000c84 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */
+  GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin;
+ 8000446:	0021      	movs	r1, r4
+ 8000448:	187b      	adds	r3, r7, r1
+ 800044a:	22d8      	movs	r2, #216	; 0xd8
+ 800044c:	00d2      	lsls	r2, r2, #3
+ 800044e:	601a      	str	r2, [r3, #0]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8000450:	187b      	adds	r3, r7, r1
+ 8000452:	2200      	movs	r2, #0
+ 8000454:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000456:	187b      	adds	r3, r7, r1
+ 8000458:	2200      	movs	r2, #0
+ 800045a:	609a      	str	r2, [r3, #8]
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800045c:	187a      	adds	r2, r7, r1
+ 800045e:	2390      	movs	r3, #144	; 0x90
+ 8000460:	05db      	lsls	r3, r3, #23
+ 8000462:	0011      	movs	r1, r2
+ 8000464:	0018      	movs	r0, r3
+ 8000466:	f000 fc0d 	bl	8000c84 <HAL_GPIO_Init>
 
 }
- 80002ee:	46c0      	nop			; (mov r8, r8)
- 80002f0:	46bd      	mov	sp, r7
- 80002f2:	b002      	add	sp, #8
- 80002f4:	bd80      	pop	{r7, pc}
- 80002f6:	46c0      	nop			; (mov r8, r8)
- 80002f8:	40021000 	.word	0x40021000
+ 800046a:	46c0      	nop			; (mov r8, r8)
+ 800046c:	46bd      	mov	sp, r7
+ 800046e:	b009      	add	sp, #36	; 0x24
+ 8000470:	bd90      	pop	{r4, r7, pc}
+ 8000472:	46c0      	nop			; (mov r8, r8)
+ 8000474:	40021000 	.word	0x40021000
+ 8000478:	48001400 	.word	0x48001400
 
-080002fc <Error_Handler>:
+0800047c <Error_Handler>:
 /**
   * @brief  This function is executed in case of error occurrence.
   * @retval None
   */
 void Error_Handler(void)
 {
- 80002fc:	b580      	push	{r7, lr}
- 80002fe:	af00      	add	r7, sp, #0
+ 800047c:	b580      	push	{r7, lr}
+ 800047e:	af00      	add	r7, sp, #0
   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __disable_irq(void)
 {
   __ASM volatile ("cpsid i" : : : "memory");
- 8000300:	b672      	cpsid	i
+ 8000480:	b672      	cpsid	i
 }
- 8000302:	46c0      	nop			; (mov r8, r8)
+ 8000482:	46c0      	nop			; (mov r8, r8)
   /* USER CODE BEGIN Error_Handler_Debug */
   /* User can add his own implementation to report the HAL error return state */
   __disable_irq();
   while (1)
- 8000304:	e7fe      	b.n	8000304 <Error_Handler+0x8>
+ 8000484:	e7fe      	b.n	8000484 <Error_Handler+0x8>
 	...
 
-08000308 <HAL_MspInit>:
+08000488 <HAL_MspInit>:
 /* USER CODE END 0 */
 /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
 {
- 8000308:	b580      	push	{r7, lr}
- 800030a:	b082      	sub	sp, #8
- 800030c:	af00      	add	r7, sp, #0
+ 8000488:	b580      	push	{r7, lr}
+ 800048a:	b082      	sub	sp, #8
+ 800048c:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN MspInit 0 */
 
   /* USER CODE END MspInit 0 */
 
   __HAL_RCC_SYSCFG_CLK_ENABLE();
- 800030e:	4b0f      	ldr	r3, [pc, #60]	; (800034c <HAL_MspInit+0x44>)
- 8000310:	699a      	ldr	r2, [r3, #24]
- 8000312:	4b0e      	ldr	r3, [pc, #56]	; (800034c <HAL_MspInit+0x44>)
- 8000314:	2101      	movs	r1, #1
- 8000316:	430a      	orrs	r2, r1
- 8000318:	619a      	str	r2, [r3, #24]
- 800031a:	4b0c      	ldr	r3, [pc, #48]	; (800034c <HAL_MspInit+0x44>)
- 800031c:	699b      	ldr	r3, [r3, #24]
- 800031e:	2201      	movs	r2, #1
- 8000320:	4013      	ands	r3, r2
- 8000322:	607b      	str	r3, [r7, #4]
- 8000324:	687b      	ldr	r3, [r7, #4]
+ 800048e:	4b0f      	ldr	r3, [pc, #60]	; (80004cc <HAL_MspInit+0x44>)
+ 8000490:	699a      	ldr	r2, [r3, #24]
+ 8000492:	4b0e      	ldr	r3, [pc, #56]	; (80004cc <HAL_MspInit+0x44>)
+ 8000494:	2101      	movs	r1, #1
+ 8000496:	430a      	orrs	r2, r1
+ 8000498:	619a      	str	r2, [r3, #24]
+ 800049a:	4b0c      	ldr	r3, [pc, #48]	; (80004cc <HAL_MspInit+0x44>)
+ 800049c:	699b      	ldr	r3, [r3, #24]
+ 800049e:	2201      	movs	r2, #1
+ 80004a0:	4013      	ands	r3, r2
+ 80004a2:	607b      	str	r3, [r7, #4]
+ 80004a4:	687b      	ldr	r3, [r7, #4]
   __HAL_RCC_PWR_CLK_ENABLE();
- 8000326:	4b09      	ldr	r3, [pc, #36]	; (800034c <HAL_MspInit+0x44>)
- 8000328:	69da      	ldr	r2, [r3, #28]
- 800032a:	4b08      	ldr	r3, [pc, #32]	; (800034c <HAL_MspInit+0x44>)
- 800032c:	2180      	movs	r1, #128	; 0x80
- 800032e:	0549      	lsls	r1, r1, #21
- 8000330:	430a      	orrs	r2, r1
- 8000332:	61da      	str	r2, [r3, #28]
- 8000334:	4b05      	ldr	r3, [pc, #20]	; (800034c <HAL_MspInit+0x44>)
- 8000336:	69da      	ldr	r2, [r3, #28]
- 8000338:	2380      	movs	r3, #128	; 0x80
- 800033a:	055b      	lsls	r3, r3, #21
- 800033c:	4013      	ands	r3, r2
- 800033e:	603b      	str	r3, [r7, #0]
- 8000340:	683b      	ldr	r3, [r7, #0]
+ 80004a6:	4b09      	ldr	r3, [pc, #36]	; (80004cc <HAL_MspInit+0x44>)
+ 80004a8:	69da      	ldr	r2, [r3, #28]
+ 80004aa:	4b08      	ldr	r3, [pc, #32]	; (80004cc <HAL_MspInit+0x44>)
+ 80004ac:	2180      	movs	r1, #128	; 0x80
+ 80004ae:	0549      	lsls	r1, r1, #21
+ 80004b0:	430a      	orrs	r2, r1
+ 80004b2:	61da      	str	r2, [r3, #28]
+ 80004b4:	4b05      	ldr	r3, [pc, #20]	; (80004cc <HAL_MspInit+0x44>)
+ 80004b6:	69da      	ldr	r2, [r3, #28]
+ 80004b8:	2380      	movs	r3, #128	; 0x80
+ 80004ba:	055b      	lsls	r3, r3, #21
+ 80004bc:	4013      	ands	r3, r2
+ 80004be:	603b      	str	r3, [r7, #0]
+ 80004c0:	683b      	ldr	r3, [r7, #0]
   /* System interrupt init*/
 
   /* USER CODE BEGIN MspInit 1 */
 
   /* USER CODE END MspInit 1 */
 }
- 8000342:	46c0      	nop			; (mov r8, r8)
- 8000344:	46bd      	mov	sp, r7
- 8000346:	b002      	add	sp, #8
- 8000348:	bd80      	pop	{r7, pc}
- 800034a:	46c0      	nop			; (mov r8, r8)
- 800034c:	40021000 	.word	0x40021000
+ 80004c2:	46c0      	nop			; (mov r8, r8)
+ 80004c4:	46bd      	mov	sp, r7
+ 80004c6:	b002      	add	sp, #8
+ 80004c8:	bd80      	pop	{r7, pc}
+ 80004ca:	46c0      	nop			; (mov r8, r8)
+ 80004cc:	40021000 	.word	0x40021000
 
-08000350 <NMI_Handler>:
+080004d0 <HAL_ADC_MspInit>:
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ 80004d0:	b590      	push	{r4, r7, lr}
+ 80004d2:	b08b      	sub	sp, #44	; 0x2c
+ 80004d4:	af00      	add	r7, sp, #0
+ 80004d6:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80004d8:	2414      	movs	r4, #20
+ 80004da:	193b      	adds	r3, r7, r4
+ 80004dc:	0018      	movs	r0, r3
+ 80004de:	2314      	movs	r3, #20
+ 80004e0:	001a      	movs	r2, r3
+ 80004e2:	2100      	movs	r1, #0
+ 80004e4:	f001 f9d0 	bl	8001888 <memset>
+  if(hadc->Instance==ADC1)
+ 80004e8:	687b      	ldr	r3, [r7, #4]
+ 80004ea:	681b      	ldr	r3, [r3, #0]
+ 80004ec:	4a19      	ldr	r2, [pc, #100]	; (8000554 <HAL_ADC_MspInit+0x84>)
+ 80004ee:	4293      	cmp	r3, r2
+ 80004f0:	d12b      	bne.n	800054a <HAL_ADC_MspInit+0x7a>
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+ 80004f2:	4b19      	ldr	r3, [pc, #100]	; (8000558 <HAL_ADC_MspInit+0x88>)
+ 80004f4:	699a      	ldr	r2, [r3, #24]
+ 80004f6:	4b18      	ldr	r3, [pc, #96]	; (8000558 <HAL_ADC_MspInit+0x88>)
+ 80004f8:	2180      	movs	r1, #128	; 0x80
+ 80004fa:	0089      	lsls	r1, r1, #2
+ 80004fc:	430a      	orrs	r2, r1
+ 80004fe:	619a      	str	r2, [r3, #24]
+ 8000500:	4b15      	ldr	r3, [pc, #84]	; (8000558 <HAL_ADC_MspInit+0x88>)
+ 8000502:	699a      	ldr	r2, [r3, #24]
+ 8000504:	2380      	movs	r3, #128	; 0x80
+ 8000506:	009b      	lsls	r3, r3, #2
+ 8000508:	4013      	ands	r3, r2
+ 800050a:	613b      	str	r3, [r7, #16]
+ 800050c:	693b      	ldr	r3, [r7, #16]
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800050e:	4b12      	ldr	r3, [pc, #72]	; (8000558 <HAL_ADC_MspInit+0x88>)
+ 8000510:	695a      	ldr	r2, [r3, #20]
+ 8000512:	4b11      	ldr	r3, [pc, #68]	; (8000558 <HAL_ADC_MspInit+0x88>)
+ 8000514:	2180      	movs	r1, #128	; 0x80
+ 8000516:	0289      	lsls	r1, r1, #10
+ 8000518:	430a      	orrs	r2, r1
+ 800051a:	615a      	str	r2, [r3, #20]
+ 800051c:	4b0e      	ldr	r3, [pc, #56]	; (8000558 <HAL_ADC_MspInit+0x88>)
+ 800051e:	695a      	ldr	r2, [r3, #20]
+ 8000520:	2380      	movs	r3, #128	; 0x80
+ 8000522:	029b      	lsls	r3, r3, #10
+ 8000524:	4013      	ands	r3, r2
+ 8000526:	60fb      	str	r3, [r7, #12]
+ 8000528:	68fb      	ldr	r3, [r7, #12]
+    /**ADC GPIO Configuration
+    PA0     ------> ADC_IN0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0;
+ 800052a:	193b      	adds	r3, r7, r4
+ 800052c:	2201      	movs	r2, #1
+ 800052e:	601a      	str	r2, [r3, #0]
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 8000530:	193b      	adds	r3, r7, r4
+ 8000532:	2203      	movs	r2, #3
+ 8000534:	605a      	str	r2, [r3, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000536:	193b      	adds	r3, r7, r4
+ 8000538:	2200      	movs	r2, #0
+ 800053a:	609a      	str	r2, [r3, #8]
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800053c:	193a      	adds	r2, r7, r4
+ 800053e:	2390      	movs	r3, #144	; 0x90
+ 8000540:	05db      	lsls	r3, r3, #23
+ 8000542:	0011      	movs	r1, r2
+ 8000544:	0018      	movs	r0, r3
+ 8000546:	f000 fb9d 	bl	8000c84 <HAL_GPIO_Init>
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+ 800054a:	46c0      	nop			; (mov r8, r8)
+ 800054c:	46bd      	mov	sp, r7
+ 800054e:	b00b      	add	sp, #44	; 0x2c
+ 8000550:	bd90      	pop	{r4, r7, pc}
+ 8000552:	46c0      	nop			; (mov r8, r8)
+ 8000554:	40012400 	.word	0x40012400
+ 8000558:	40021000 	.word	0x40021000
+
+0800055c <NMI_Handler>:
 /******************************************************************************/
 /**
   * @brief This function handles Non maskable interrupt.
   */
 void NMI_Handler(void)
 {
- 8000350:	b580      	push	{r7, lr}
- 8000352:	af00      	add	r7, sp, #0
+ 800055c:	b580      	push	{r7, lr}
+ 800055e:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
 
   /* USER CODE END NonMaskableInt_IRQn 0 */
   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
- 8000354:	e7fe      	b.n	8000354 <NMI_Handler+0x4>
+ 8000560:	e7fe      	b.n	8000560 <NMI_Handler+0x4>
 
-08000356 <HardFault_Handler>:
+08000562 <HardFault_Handler>:
 
 /**
   * @brief This function handles Hard fault interrupt.
   */
 void HardFault_Handler(void)
 {
- 8000356:	b580      	push	{r7, lr}
- 8000358:	af00      	add	r7, sp, #0
+ 8000562:	b580      	push	{r7, lr}
+ 8000564:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN HardFault_IRQn 0 */
 
   /* USER CODE END HardFault_IRQn 0 */
   while (1)
- 800035a:	e7fe      	b.n	800035a <HardFault_Handler+0x4>
+ 8000566:	e7fe      	b.n	8000566 <HardFault_Handler+0x4>
 
-0800035c <SVC_Handler>:
+08000568 <SVC_Handler>:
 
 /**
   * @brief This function handles System service call via SWI instruction.
   */
 void SVC_Handler(void)
 {
- 800035c:	b580      	push	{r7, lr}
- 800035e:	af00      	add	r7, sp, #0
+ 8000568:	b580      	push	{r7, lr}
+ 800056a:	af00      	add	r7, sp, #0
 
   /* USER CODE END SVC_IRQn 0 */
   /* USER CODE BEGIN SVC_IRQn 1 */
 
   /* USER CODE END SVC_IRQn 1 */
 }
- 8000360:	46c0      	nop			; (mov r8, r8)
- 8000362:	46bd      	mov	sp, r7
- 8000364:	bd80      	pop	{r7, pc}
+ 800056c:	46c0      	nop			; (mov r8, r8)
+ 800056e:	46bd      	mov	sp, r7
+ 8000570:	bd80      	pop	{r7, pc}
 
-08000366 <PendSV_Handler>:
+08000572 <PendSV_Handler>:
 
 /**
   * @brief This function handles Pendable request for system service.
   */
 void PendSV_Handler(void)
 {
- 8000366:	b580      	push	{r7, lr}
- 8000368:	af00      	add	r7, sp, #0
+ 8000572:	b580      	push	{r7, lr}
+ 8000574:	af00      	add	r7, sp, #0
 
   /* USER CODE END PendSV_IRQn 0 */
   /* USER CODE BEGIN PendSV_IRQn 1 */
 
   /* USER CODE END PendSV_IRQn 1 */
 }
- 800036a:	46c0      	nop			; (mov r8, r8)
- 800036c:	46bd      	mov	sp, r7
- 800036e:	bd80      	pop	{r7, pc}
+ 8000576:	46c0      	nop			; (mov r8, r8)
+ 8000578:	46bd      	mov	sp, r7
+ 800057a:	bd80      	pop	{r7, pc}
 
-08000370 <SysTick_Handler>:
+0800057c <SysTick_Handler>:
 
 /**
   * @brief This function handles System tick timer.
   */
 void SysTick_Handler(void)
 {
- 8000370:	b580      	push	{r7, lr}
- 8000372:	af00      	add	r7, sp, #0
+ 800057c:	b580      	push	{r7, lr}
+ 800057e:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN SysTick_IRQn 0 */
 
   /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
- 8000374:	f000 f87a 	bl	800046c <HAL_IncTick>
+ 8000580:	f000 f87a 	bl	8000678 <HAL_IncTick>
   /* USER CODE BEGIN SysTick_IRQn 1 */
 
   /* USER CODE END SysTick_IRQn 1 */
 }
- 8000378:	46c0      	nop			; (mov r8, r8)
- 800037a:	46bd      	mov	sp, r7
- 800037c:	bd80      	pop	{r7, pc}
+ 8000584:	46c0      	nop			; (mov r8, r8)
+ 8000586:	46bd      	mov	sp, r7
+ 8000588:	bd80      	pop	{r7, pc}
 
-0800037e <SystemInit>:
+0800058a <SystemInit>:
   * @brief  Setup the microcontroller system
   * @param  None
   * @retval None
   */
 void SystemInit(void)
 {
- 800037e:	b580      	push	{r7, lr}
- 8000380:	af00      	add	r7, sp, #0
+ 800058a:	b580      	push	{r7, lr}
+ 800058c:	af00      	add	r7, sp, #0
                          before branch to main program. This call is made inside
                          the "startup_stm32f0xx.s" file.
                          User can setups the default system clock (System clock source, PLL Multiplier
                          and Divider factors, AHB/APBx prescalers and Flash settings).
    */
 }
- 8000382:	46c0      	nop			; (mov r8, r8)
- 8000384:	46bd      	mov	sp, r7
- 8000386:	bd80      	pop	{r7, pc}
+ 800058e:	46c0      	nop			; (mov r8, r8)
+ 8000590:	46bd      	mov	sp, r7
+ 8000592:	bd80      	pop	{r7, pc}
 
-08000388 <Reset_Handler>:
+08000594 <Reset_Handler>:
 
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
- 8000388:	480d      	ldr	r0, [pc, #52]	; (80003c0 <LoopForever+0x2>)
+ 8000594:	480d      	ldr	r0, [pc, #52]	; (80005cc <LoopForever+0x2>)
   mov   sp, r0          /* set stack pointer */
- 800038a:	4685      	mov	sp, r0
+ 8000596:	4685      	mov	sp, r0
 
 /* Copy the data segment initializers from flash to SRAM */
   ldr r0, =_sdata
- 800038c:	480d      	ldr	r0, [pc, #52]	; (80003c4 <LoopForever+0x6>)
+ 8000598:	480d      	ldr	r0, [pc, #52]	; (80005d0 <LoopForever+0x6>)
   ldr r1, =_edata
- 800038e:	490e      	ldr	r1, [pc, #56]	; (80003c8 <LoopForever+0xa>)
+ 800059a:	490e      	ldr	r1, [pc, #56]	; (80005d4 <LoopForever+0xa>)
   ldr r2, =_sidata
- 8000390:	4a0e      	ldr	r2, [pc, #56]	; (80003cc <LoopForever+0xe>)
+ 800059c:	4a0e      	ldr	r2, [pc, #56]	; (80005d8 <LoopForever+0xe>)
   movs r3, #0
- 8000392:	2300      	movs	r3, #0
+ 800059e:	2300      	movs	r3, #0
   b LoopCopyDataInit
- 8000394:	e002      	b.n	800039c <LoopCopyDataInit>
+ 80005a0:	e002      	b.n	80005a8 <LoopCopyDataInit>
 
-08000396 <CopyDataInit>:
+080005a2 <CopyDataInit>:
 
 CopyDataInit:
   ldr r4, [r2, r3]
- 8000396:	58d4      	ldr	r4, [r2, r3]
+ 80005a2:	58d4      	ldr	r4, [r2, r3]
   str r4, [r0, r3]
- 8000398:	50c4      	str	r4, [r0, r3]
+ 80005a4:	50c4      	str	r4, [r0, r3]
   adds r3, r3, #4
- 800039a:	3304      	adds	r3, #4
+ 80005a6:	3304      	adds	r3, #4
 
-0800039c <LoopCopyDataInit>:
+080005a8 <LoopCopyDataInit>:
 
 LoopCopyDataInit:
   adds r4, r0, r3
- 800039c:	18c4      	adds	r4, r0, r3
+ 80005a8:	18c4      	adds	r4, r0, r3
   cmp r4, r1
- 800039e:	428c      	cmp	r4, r1
+ 80005aa:	428c      	cmp	r4, r1
   bcc CopyDataInit
- 80003a0:	d3f9      	bcc.n	8000396 <CopyDataInit>
+ 80005ac:	d3f9      	bcc.n	80005a2 <CopyDataInit>
   
 /* Zero fill the bss segment. */
   ldr r2, =_sbss
- 80003a2:	4a0b      	ldr	r2, [pc, #44]	; (80003d0 <LoopForever+0x12>)
+ 80005ae:	4a0b      	ldr	r2, [pc, #44]	; (80005dc <LoopForever+0x12>)
   ldr r4, =_ebss
- 80003a4:	4c0b      	ldr	r4, [pc, #44]	; (80003d4 <LoopForever+0x16>)
+ 80005b0:	4c0b      	ldr	r4, [pc, #44]	; (80005e0 <LoopForever+0x16>)
   movs r3, #0
- 80003a6:	2300      	movs	r3, #0
+ 80005b2:	2300      	movs	r3, #0
   b LoopFillZerobss
- 80003a8:	e001      	b.n	80003ae <LoopFillZerobss>
+ 80005b4:	e001      	b.n	80005ba <LoopFillZerobss>
 
-080003aa <FillZerobss>:
+080005b6 <FillZerobss>:
 
 FillZerobss:
   str  r3, [r2]
- 80003aa:	6013      	str	r3, [r2, #0]
+ 80005b6:	6013      	str	r3, [r2, #0]
   adds r2, r2, #4
- 80003ac:	3204      	adds	r2, #4
+ 80005b8:	3204      	adds	r2, #4
 
-080003ae <LoopFillZerobss>:
+080005ba <LoopFillZerobss>:
 
 LoopFillZerobss:
   cmp r2, r4
- 80003ae:	42a2      	cmp	r2, r4
+ 80005ba:	42a2      	cmp	r2, r4
   bcc FillZerobss
- 80003b0:	d3fb      	bcc.n	80003aa <FillZerobss>
+ 80005bc:	d3fb      	bcc.n	80005b6 <FillZerobss>
 
 /* Call the clock system intitialization function.*/
   bl  SystemInit
- 80003b2:	f7ff ffe4 	bl	800037e <SystemInit>
+ 80005be:	f7ff ffe4 	bl	800058a <SystemInit>
 /* Call static constructors */
   bl __libc_init_array
- 80003b6:	f000 fd79 	bl	8000eac <__libc_init_array>
+ 80005c2:	f001 f93d 	bl	8001840 <__libc_init_array>
 /* Call the application's entry point.*/
   bl main
- 80003ba:	f7ff ff31 	bl	8000220 <main>
+ 80005c6:	f7ff fe2b 	bl	8000220 <main>
 
-080003be <LoopForever>:
+080005ca <LoopForever>:
 
 LoopForever:
     b LoopForever
- 80003be:	e7fe      	b.n	80003be <LoopForever>
+ 80005ca:	e7fe      	b.n	80005ca <LoopForever>
   ldr   r0, =_estack
- 80003c0:	20001000 	.word	0x20001000
+ 80005cc:	20001000 	.word	0x20001000
   ldr r0, =_sdata
- 80003c4:	20000000 	.word	0x20000000
+ 80005d0:	20000000 	.word	0x20000000
   ldr r1, =_edata
- 80003c8:	2000000c 	.word	0x2000000c
+ 80005d4:	2000000c 	.word	0x2000000c
   ldr r2, =_sidata
- 80003cc:	08000f54 	.word	0x08000f54
+ 80005d8:	080018e8 	.word	0x080018e8
   ldr r2, =_sbss
- 80003d0:	2000000c 	.word	0x2000000c
+ 80005dc:	2000000c 	.word	0x2000000c
   ldr r4, =_ebss
- 80003d4:	2000002c 	.word	0x2000002c
+ 80005e0:	2000006c 	.word	0x2000006c
 
-080003d8 <ADC1_IRQHandler>:
+080005e4 <ADC1_IRQHandler>:
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
- 80003d8:	e7fe      	b.n	80003d8 <ADC1_IRQHandler>
+ 80005e4:	e7fe      	b.n	80005e4 <ADC1_IRQHandler>
 	...
 
-080003dc <HAL_Init>:
+080005e8 <HAL_Init>:
   *       In the default implementation,Systick is used as source of time base.
   *       The tick variable is incremented each 1ms in its ISR.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_Init(void)
 {
- 80003dc:	b580      	push	{r7, lr}
- 80003de:	af00      	add	r7, sp, #0
+ 80005e8:	b580      	push	{r7, lr}
+ 80005ea:	af00      	add	r7, sp, #0
   /* Configure Flash prefetch */ 
 #if (PREFETCH_ENABLE != 0)
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
- 80003e0:	4b07      	ldr	r3, [pc, #28]	; (8000400 <HAL_Init+0x24>)
- 80003e2:	681a      	ldr	r2, [r3, #0]
- 80003e4:	4b06      	ldr	r3, [pc, #24]	; (8000400 <HAL_Init+0x24>)
- 80003e6:	2110      	movs	r1, #16
- 80003e8:	430a      	orrs	r2, r1
- 80003ea:	601a      	str	r2, [r3, #0]
+ 80005ec:	4b07      	ldr	r3, [pc, #28]	; (800060c <HAL_Init+0x24>)
+ 80005ee:	681a      	ldr	r2, [r3, #0]
+ 80005f0:	4b06      	ldr	r3, [pc, #24]	; (800060c <HAL_Init+0x24>)
+ 80005f2:	2110      	movs	r1, #16
+ 80005f4:	430a      	orrs	r2, r1
+ 80005f6:	601a      	str	r2, [r3, #0]
 #endif /* PREFETCH_ENABLE */
 
   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
 
   HAL_InitTick(TICK_INT_PRIORITY);
- 80003ec:	2003      	movs	r0, #3
- 80003ee:	f000 f809 	bl	8000404 <HAL_InitTick>
+ 80005f8:	2003      	movs	r0, #3
+ 80005fa:	f000 f809 	bl	8000610 <HAL_InitTick>
 
   /* Init the low level hardware */
   HAL_MspInit();
- 80003f2:	f7ff ff89 	bl	8000308 <HAL_MspInit>
+ 80005fe:	f7ff ff43 	bl	8000488 <HAL_MspInit>
 
   /* Return function status */
   return HAL_OK;
- 80003f6:	2300      	movs	r3, #0
+ 8000602:	2300      	movs	r3, #0
 }
- 80003f8:	0018      	movs	r0, r3
- 80003fa:	46bd      	mov	sp, r7
- 80003fc:	bd80      	pop	{r7, pc}
- 80003fe:	46c0      	nop			; (mov r8, r8)
- 8000400:	40022000 	.word	0x40022000
+ 8000604:	0018      	movs	r0, r3
+ 8000606:	46bd      	mov	sp, r7
+ 8000608:	bd80      	pop	{r7, pc}
+ 800060a:	46c0      	nop			; (mov r8, r8)
+ 800060c:	40022000 	.word	0x40022000
 
-08000404 <HAL_InitTick>:
+08000610 <HAL_InitTick>:
   *       implementation  in user file.
   * @param TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
- 8000404:	b590      	push	{r4, r7, lr}
- 8000406:	b083      	sub	sp, #12
- 8000408:	af00      	add	r7, sp, #0
- 800040a:	6078      	str	r0, [r7, #4]
+ 8000610:	b590      	push	{r4, r7, lr}
+ 8000612:	b083      	sub	sp, #12
+ 8000614:	af00      	add	r7, sp, #0
+ 8000616:	6078      	str	r0, [r7, #4]
   /*Configure the SysTick to have interrupt in 1ms time basis*/
   if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 800040c:	4b14      	ldr	r3, [pc, #80]	; (8000460 <HAL_InitTick+0x5c>)
- 800040e:	681c      	ldr	r4, [r3, #0]
- 8000410:	4b14      	ldr	r3, [pc, #80]	; (8000464 <HAL_InitTick+0x60>)
- 8000412:	781b      	ldrb	r3, [r3, #0]
- 8000414:	0019      	movs	r1, r3
- 8000416:	23fa      	movs	r3, #250	; 0xfa
- 8000418:	0098      	lsls	r0, r3, #2
- 800041a:	f7ff fe75 	bl	8000108 <__udivsi3>
- 800041e:	0003      	movs	r3, r0
- 8000420:	0019      	movs	r1, r3
- 8000422:	0020      	movs	r0, r4
- 8000424:	f7ff fe70 	bl	8000108 <__udivsi3>
- 8000428:	0003      	movs	r3, r0
- 800042a:	0018      	movs	r0, r3
- 800042c:	f000 f8e1 	bl	80005f2 <HAL_SYSTICK_Config>
- 8000430:	1e03      	subs	r3, r0, #0
- 8000432:	d001      	beq.n	8000438 <HAL_InitTick+0x34>
+ 8000618:	4b14      	ldr	r3, [pc, #80]	; (800066c <HAL_InitTick+0x5c>)
+ 800061a:	681c      	ldr	r4, [r3, #0]
+ 800061c:	4b14      	ldr	r3, [pc, #80]	; (8000670 <HAL_InitTick+0x60>)
+ 800061e:	781b      	ldrb	r3, [r3, #0]
+ 8000620:	0019      	movs	r1, r3
+ 8000622:	23fa      	movs	r3, #250	; 0xfa
+ 8000624:	0098      	lsls	r0, r3, #2
+ 8000626:	f7ff fd6f 	bl	8000108 <__udivsi3>
+ 800062a:	0003      	movs	r3, r0
+ 800062c:	0019      	movs	r1, r3
+ 800062e:	0020      	movs	r0, r4
+ 8000630:	f7ff fd6a 	bl	8000108 <__udivsi3>
+ 8000634:	0003      	movs	r3, r0
+ 8000636:	0018      	movs	r0, r3
+ 8000638:	f000 fb17 	bl	8000c6a <HAL_SYSTICK_Config>
+ 800063c:	1e03      	subs	r3, r0, #0
+ 800063e:	d001      	beq.n	8000644 <HAL_InitTick+0x34>
   {
     return HAL_ERROR;
- 8000434:	2301      	movs	r3, #1
- 8000436:	e00f      	b.n	8000458 <HAL_InitTick+0x54>
+ 8000640:	2301      	movs	r3, #1
+ 8000642:	e00f      	b.n	8000664 <HAL_InitTick+0x54>
   }
 
   /* Configure the SysTick IRQ priority */
   if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8000438:	687b      	ldr	r3, [r7, #4]
- 800043a:	2b03      	cmp	r3, #3
- 800043c:	d80b      	bhi.n	8000456 <HAL_InitTick+0x52>
+ 8000644:	687b      	ldr	r3, [r7, #4]
+ 8000646:	2b03      	cmp	r3, #3
+ 8000648:	d80b      	bhi.n	8000662 <HAL_InitTick+0x52>
   {
     HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 800043e:	6879      	ldr	r1, [r7, #4]
- 8000440:	2301      	movs	r3, #1
- 8000442:	425b      	negs	r3, r3
- 8000444:	2200      	movs	r2, #0
- 8000446:	0018      	movs	r0, r3
- 8000448:	f000 f8be 	bl	80005c8 <HAL_NVIC_SetPriority>
+ 800064a:	6879      	ldr	r1, [r7, #4]
+ 800064c:	2301      	movs	r3, #1
+ 800064e:	425b      	negs	r3, r3
+ 8000650:	2200      	movs	r2, #0
+ 8000652:	0018      	movs	r0, r3
+ 8000654:	f000 faf4 	bl	8000c40 <HAL_NVIC_SetPriority>
     uwTickPrio = TickPriority;
- 800044c:	4b06      	ldr	r3, [pc, #24]	; (8000468 <HAL_InitTick+0x64>)
- 800044e:	687a      	ldr	r2, [r7, #4]
- 8000450:	601a      	str	r2, [r3, #0]
+ 8000658:	4b06      	ldr	r3, [pc, #24]	; (8000674 <HAL_InitTick+0x64>)
+ 800065a:	687a      	ldr	r2, [r7, #4]
+ 800065c:	601a      	str	r2, [r3, #0]
   {
     return HAL_ERROR;
   }
 
    /* Return function status */
   return HAL_OK;
- 8000452:	2300      	movs	r3, #0
- 8000454:	e000      	b.n	8000458 <HAL_InitTick+0x54>
+ 800065e:	2300      	movs	r3, #0
+ 8000660:	e000      	b.n	8000664 <HAL_InitTick+0x54>
     return HAL_ERROR;
- 8000456:	2301      	movs	r3, #1
+ 8000662:	2301      	movs	r3, #1
 }
- 8000458:	0018      	movs	r0, r3
- 800045a:	46bd      	mov	sp, r7
- 800045c:	b003      	add	sp, #12
- 800045e:	bd90      	pop	{r4, r7, pc}
- 8000460:	20000000 	.word	0x20000000
- 8000464:	20000008 	.word	0x20000008
- 8000468:	20000004 	.word	0x20000004
+ 8000664:	0018      	movs	r0, r3
+ 8000666:	46bd      	mov	sp, r7
+ 8000668:	b003      	add	sp, #12
+ 800066a:	bd90      	pop	{r4, r7, pc}
+ 800066c:	20000000 	.word	0x20000000
+ 8000670:	20000008 	.word	0x20000008
+ 8000674:	20000004 	.word	0x20000004
 
-0800046c <HAL_IncTick>:
+08000678 <HAL_IncTick>:
   * @note This function is declared as __weak to be overwritten in case of other 
   *       implementations in user file.
   * @retval None
   */
 __weak void HAL_IncTick(void)
 {
- 800046c:	b580      	push	{r7, lr}
- 800046e:	af00      	add	r7, sp, #0
+ 8000678:	b580      	push	{r7, lr}
+ 800067a:	af00      	add	r7, sp, #0
   uwTick += uwTickFreq;
- 8000470:	4b05      	ldr	r3, [pc, #20]	; (8000488 <HAL_IncTick+0x1c>)
- 8000472:	781b      	ldrb	r3, [r3, #0]
- 8000474:	001a      	movs	r2, r3
- 8000476:	4b05      	ldr	r3, [pc, #20]	; (800048c <HAL_IncTick+0x20>)
- 8000478:	681b      	ldr	r3, [r3, #0]
- 800047a:	18d2      	adds	r2, r2, r3
- 800047c:	4b03      	ldr	r3, [pc, #12]	; (800048c <HAL_IncTick+0x20>)
- 800047e:	601a      	str	r2, [r3, #0]
+ 800067c:	4b05      	ldr	r3, [pc, #20]	; (8000694 <HAL_IncTick+0x1c>)
+ 800067e:	781b      	ldrb	r3, [r3, #0]
+ 8000680:	001a      	movs	r2, r3
+ 8000682:	4b05      	ldr	r3, [pc, #20]	; (8000698 <HAL_IncTick+0x20>)
+ 8000684:	681b      	ldr	r3, [r3, #0]
+ 8000686:	18d2      	adds	r2, r2, r3
+ 8000688:	4b03      	ldr	r3, [pc, #12]	; (8000698 <HAL_IncTick+0x20>)
+ 800068a:	601a      	str	r2, [r3, #0]
 }
- 8000480:	46c0      	nop			; (mov r8, r8)
- 8000482:	46bd      	mov	sp, r7
- 8000484:	bd80      	pop	{r7, pc}
- 8000486:	46c0      	nop			; (mov r8, r8)
- 8000488:	20000008 	.word	0x20000008
- 800048c:	20000028 	.word	0x20000028
+ 800068c:	46c0      	nop			; (mov r8, r8)
+ 800068e:	46bd      	mov	sp, r7
+ 8000690:	bd80      	pop	{r7, pc}
+ 8000692:	46c0      	nop			; (mov r8, r8)
+ 8000694:	20000008 	.word	0x20000008
+ 8000698:	20000068 	.word	0x20000068
 
-08000490 <HAL_GetTick>:
+0800069c <HAL_GetTick>:
   * @note   This function is declared as __weak  to be overwritten  in case of other 
   *       implementations in user file.
   * @retval tick value
   */
 __weak uint32_t HAL_GetTick(void)
 {
- 8000490:	b580      	push	{r7, lr}
- 8000492:	af00      	add	r7, sp, #0
+ 800069c:	b580      	push	{r7, lr}
+ 800069e:	af00      	add	r7, sp, #0
   return uwTick;
- 8000494:	4b02      	ldr	r3, [pc, #8]	; (80004a0 <HAL_GetTick+0x10>)
- 8000496:	681b      	ldr	r3, [r3, #0]
+ 80006a0:	4b02      	ldr	r3, [pc, #8]	; (80006ac <HAL_GetTick+0x10>)
+ 80006a2:	681b      	ldr	r3, [r3, #0]
 }
- 8000498:	0018      	movs	r0, r3
- 800049a:	46bd      	mov	sp, r7
- 800049c:	bd80      	pop	{r7, pc}
- 800049e:	46c0      	nop			; (mov r8, r8)
- 80004a0:	20000028 	.word	0x20000028
+ 80006a4:	0018      	movs	r0, r3
+ 80006a6:	46bd      	mov	sp, r7
+ 80006a8:	bd80      	pop	{r7, pc}
+ 80006aa:	46c0      	nop			; (mov r8, r8)
+ 80006ac:	20000068 	.word	0x20000068
 
-080004a4 <__NVIC_SetPriority>:
+080006b0 <HAL_ADC_Init>:
+  *         of structure "ADC_InitTypeDef".
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ 80006b0:	b580      	push	{r7, lr}
+ 80006b2:	b084      	sub	sp, #16
+ 80006b4:	af00      	add	r7, sp, #0
+ 80006b6:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 80006b8:	230f      	movs	r3, #15
+ 80006ba:	18fb      	adds	r3, r7, r3
+ 80006bc:	2200      	movs	r2, #0
+ 80006be:	701a      	strb	r2, [r3, #0]
+  uint32_t tmpCFGR1 = 0U;
+ 80006c0:	2300      	movs	r3, #0
+ 80006c2:	60bb      	str	r3, [r7, #8]
+
+  /* Check ADC handle */
+  if(hadc == NULL)
+ 80006c4:	687b      	ldr	r3, [r7, #4]
+ 80006c6:	2b00      	cmp	r3, #0
+ 80006c8:	d101      	bne.n	80006ce <HAL_ADC_Init+0x1e>
+  {
+    return HAL_ERROR;
+ 80006ca:	2301      	movs	r3, #1
+ 80006cc:	e125      	b.n	800091a <HAL_ADC_Init+0x26a>
+  /* Refer to header of this file for more details on clock enabling procedure*/
+  
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  /* - ADC voltage regulator enable                                           */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+ 80006ce:	687b      	ldr	r3, [r7, #4]
+ 80006d0:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80006d2:	2b00      	cmp	r3, #0
+ 80006d4:	d10a      	bne.n	80006ec <HAL_ADC_Init+0x3c>
+  {
+    /* Initialize ADC error code */
+    ADC_CLEAR_ERRORCODE(hadc);
+ 80006d6:	687b      	ldr	r3, [r7, #4]
+ 80006d8:	2200      	movs	r2, #0
+ 80006da:	63da      	str	r2, [r3, #60]	; 0x3c
+    
+    /* Allocate lock resource and initialize it */
+    hadc->Lock = HAL_UNLOCKED;
+ 80006dc:	687b      	ldr	r3, [r7, #4]
+ 80006de:	2234      	movs	r2, #52	; 0x34
+ 80006e0:	2100      	movs	r1, #0
+ 80006e2:	5499      	strb	r1, [r3, r2]
+    
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+ 80006e4:	687b      	ldr	r3, [r7, #4]
+ 80006e6:	0018      	movs	r0, r3
+ 80006e8:	f7ff fef2 	bl	80004d0 <HAL_ADC_MspInit>
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  /* and if there is no conversion on going on regular group (ADC can be      */ 
+  /* enabled anyway, in case of call of this function to update a parameter   */
+  /* on the fly).                                                             */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ 80006ec:	687b      	ldr	r3, [r7, #4]
+ 80006ee:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80006f0:	2210      	movs	r2, #16
+ 80006f2:	4013      	ands	r3, r2
+ 80006f4:	d000      	beq.n	80006f8 <HAL_ADC_Init+0x48>
+ 80006f6:	e103      	b.n	8000900 <HAL_ADC_Init+0x250>
+ 80006f8:	230f      	movs	r3, #15
+ 80006fa:	18fb      	adds	r3, r7, r3
+ 80006fc:	781b      	ldrb	r3, [r3, #0]
+ 80006fe:	2b00      	cmp	r3, #0
+ 8000700:	d000      	beq.n	8000704 <HAL_ADC_Init+0x54>
+ 8000702:	e0fd      	b.n	8000900 <HAL_ADC_Init+0x250>
+      (tmp_hal_status == HAL_OK)                                &&
+      (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)          )
+ 8000704:	687b      	ldr	r3, [r7, #4]
+ 8000706:	681b      	ldr	r3, [r3, #0]
+ 8000708:	689b      	ldr	r3, [r3, #8]
+ 800070a:	2204      	movs	r2, #4
+ 800070c:	4013      	ands	r3, r2
+      (tmp_hal_status == HAL_OK)                                &&
+ 800070e:	d000      	beq.n	8000712 <HAL_ADC_Init+0x62>
+ 8000710:	e0f6      	b.n	8000900 <HAL_ADC_Init+0x250>
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+ 8000712:	687b      	ldr	r3, [r7, #4]
+ 8000714:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8000716:	4a83      	ldr	r2, [pc, #524]	; (8000924 <HAL_ADC_Init+0x274>)
+ 8000718:	4013      	ands	r3, r2
+ 800071a:	2202      	movs	r2, #2
+ 800071c:	431a      	orrs	r2, r3
+ 800071e:	687b      	ldr	r3, [r7, #4]
+ 8000720:	639a      	str	r2, [r3, #56]	; 0x38
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - ADC clock mode                                                      */
+    /*  - ADC clock prescaler                                                 */
+    /*  - ADC resolution                                                      */
+    if (ADC_IS_ENABLE(hadc) == RESET)
+ 8000722:	687b      	ldr	r3, [r7, #4]
+ 8000724:	681b      	ldr	r3, [r3, #0]
+ 8000726:	689b      	ldr	r3, [r3, #8]
+ 8000728:	2203      	movs	r2, #3
+ 800072a:	4013      	ands	r3, r2
+ 800072c:	2b01      	cmp	r3, #1
+ 800072e:	d112      	bne.n	8000756 <HAL_ADC_Init+0xa6>
+ 8000730:	687b      	ldr	r3, [r7, #4]
+ 8000732:	681b      	ldr	r3, [r3, #0]
+ 8000734:	681b      	ldr	r3, [r3, #0]
+ 8000736:	2201      	movs	r2, #1
+ 8000738:	4013      	ands	r3, r2
+ 800073a:	2b01      	cmp	r3, #1
+ 800073c:	d009      	beq.n	8000752 <HAL_ADC_Init+0xa2>
+ 800073e:	687b      	ldr	r3, [r7, #4]
+ 8000740:	681b      	ldr	r3, [r3, #0]
+ 8000742:	68da      	ldr	r2, [r3, #12]
+ 8000744:	2380      	movs	r3, #128	; 0x80
+ 8000746:	021b      	lsls	r3, r3, #8
+ 8000748:	401a      	ands	r2, r3
+ 800074a:	2380      	movs	r3, #128	; 0x80
+ 800074c:	021b      	lsls	r3, r3, #8
+ 800074e:	429a      	cmp	r2, r3
+ 8000750:	d101      	bne.n	8000756 <HAL_ADC_Init+0xa6>
+ 8000752:	2301      	movs	r3, #1
+ 8000754:	e000      	b.n	8000758 <HAL_ADC_Init+0xa8>
+ 8000756:	2300      	movs	r3, #0
+ 8000758:	2b00      	cmp	r3, #0
+ 800075a:	d116      	bne.n	800078a <HAL_ADC_Init+0xda>
+      /* parameters):                                                         */
+      /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+      /*     (set into HAL_ADC_ConfigChannel() )                              */
+     
+      /* Configuration of ADC resolution                                      */
+      MODIFY_REG(hadc->Instance->CFGR1,
+ 800075c:	687b      	ldr	r3, [r7, #4]
+ 800075e:	681b      	ldr	r3, [r3, #0]
+ 8000760:	68db      	ldr	r3, [r3, #12]
+ 8000762:	2218      	movs	r2, #24
+ 8000764:	4393      	bics	r3, r2
+ 8000766:	0019      	movs	r1, r3
+ 8000768:	687b      	ldr	r3, [r7, #4]
+ 800076a:	689a      	ldr	r2, [r3, #8]
+ 800076c:	687b      	ldr	r3, [r7, #4]
+ 800076e:	681b      	ldr	r3, [r3, #0]
+ 8000770:	430a      	orrs	r2, r1
+ 8000772:	60da      	str	r2, [r3, #12]
+                 ADC_CFGR1_RES        ,
+                 hadc->Init.Resolution );
+      
+      /* Configuration of ADC clock mode: clock source AHB or HSI with        */
+      /* selectable prescaler                                                 */
+      MODIFY_REG(hadc->Instance->CFGR2    ,
+ 8000774:	687b      	ldr	r3, [r7, #4]
+ 8000776:	681b      	ldr	r3, [r3, #0]
+ 8000778:	691b      	ldr	r3, [r3, #16]
+ 800077a:	009b      	lsls	r3, r3, #2
+ 800077c:	0899      	lsrs	r1, r3, #2
+ 800077e:	687b      	ldr	r3, [r7, #4]
+ 8000780:	685a      	ldr	r2, [r3, #4]
+ 8000782:	687b      	ldr	r3, [r7, #4]
+ 8000784:	681b      	ldr	r3, [r3, #0]
+ 8000786:	430a      	orrs	r2, r1
+ 8000788:	611a      	str	r2, [r3, #16]
+    /*  - external trigger polarity                                           */
+    /*  - data alignment                                                      */
+    /*  - resolution                                                          */
+    /*  - scan direction                                                      */
+    /*  - DMA continuous request                                              */
+    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN  |
+ 800078a:	687b      	ldr	r3, [r7, #4]
+ 800078c:	681b      	ldr	r3, [r3, #0]
+ 800078e:	68da      	ldr	r2, [r3, #12]
+ 8000790:	687b      	ldr	r3, [r7, #4]
+ 8000792:	681b      	ldr	r3, [r3, #0]
+ 8000794:	4964      	ldr	r1, [pc, #400]	; (8000928 <HAL_ADC_Init+0x278>)
+ 8000796:	400a      	ands	r2, r1
+ 8000798:	60da      	str	r2, [r3, #12]
+                                ADC_CFGR1_EXTEN   |
+                                ADC_CFGR1_ALIGN   |
+                                ADC_CFGR1_SCANDIR |
+                                ADC_CFGR1_DMACFG   );
+
+    tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 800079a:	687b      	ldr	r3, [r7, #4]
+ 800079c:	7e1b      	ldrb	r3, [r3, #24]
+ 800079e:	039a      	lsls	r2, r3, #14
+                 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)     |
+ 80007a0:	687b      	ldr	r3, [r7, #4]
+ 80007a2:	7e5b      	ldrb	r3, [r3, #25]
+ 80007a4:	03db      	lsls	r3, r3, #15
+    tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 80007a6:	431a      	orrs	r2, r3
+                 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)    |
+ 80007a8:	687b      	ldr	r3, [r7, #4]
+ 80007aa:	7e9b      	ldrb	r3, [r3, #26]
+ 80007ac:	035b      	lsls	r3, r3, #13
+                 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)     |
+ 80007ae:	431a      	orrs	r2, r3
+                 ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                            |
+ 80007b0:	687b      	ldr	r3, [r7, #4]
+ 80007b2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 80007b4:	2b01      	cmp	r3, #1
+ 80007b6:	d002      	beq.n	80007be <HAL_ADC_Init+0x10e>
+ 80007b8:	2380      	movs	r3, #128	; 0x80
+ 80007ba:	015b      	lsls	r3, r3, #5
+ 80007bc:	e000      	b.n	80007c0 <HAL_ADC_Init+0x110>
+ 80007be:	2300      	movs	r3, #0
+                 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)    |
+ 80007c0:	431a      	orrs	r2, r3
+                 hadc->Init.DataAlign                                             |
+ 80007c2:	687b      	ldr	r3, [r7, #4]
+ 80007c4:	68db      	ldr	r3, [r3, #12]
+                 ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                            |
+ 80007c6:	431a      	orrs	r2, r3
+                 ADC_SCANDIR(hadc->Init.ScanConvMode)                             |
+ 80007c8:	687b      	ldr	r3, [r7, #4]
+ 80007ca:	691b      	ldr	r3, [r3, #16]
+ 80007cc:	2b02      	cmp	r3, #2
+ 80007ce:	d101      	bne.n	80007d4 <HAL_ADC_Init+0x124>
+ 80007d0:	2304      	movs	r3, #4
+ 80007d2:	e000      	b.n	80007d6 <HAL_ADC_Init+0x126>
+ 80007d4:	2300      	movs	r3, #0
+                 hadc->Init.DataAlign                                             |
+ 80007d6:	431a      	orrs	r2, r3
+                 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)  );
+ 80007d8:	687b      	ldr	r3, [r7, #4]
+ 80007da:	2124      	movs	r1, #36	; 0x24
+ 80007dc:	5c5b      	ldrb	r3, [r3, r1]
+ 80007de:	005b      	lsls	r3, r3, #1
+                 ADC_SCANDIR(hadc->Init.ScanConvMode)                             |
+ 80007e0:	4313      	orrs	r3, r2
+    tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 80007e2:	68ba      	ldr	r2, [r7, #8]
+ 80007e4:	4313      	orrs	r3, r2
+ 80007e6:	60bb      	str	r3, [r7, #8]
+    
+    /* Enable discontinuous mode only if continuous mode is disabled */
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ 80007e8:	687b      	ldr	r3, [r7, #4]
+ 80007ea:	7edb      	ldrb	r3, [r3, #27]
+ 80007ec:	2b01      	cmp	r3, #1
+ 80007ee:	d115      	bne.n	800081c <HAL_ADC_Init+0x16c>
+    {
+      if (hadc->Init.ContinuousConvMode == DISABLE)
+ 80007f0:	687b      	ldr	r3, [r7, #4]
+ 80007f2:	7e9b      	ldrb	r3, [r3, #26]
+ 80007f4:	2b00      	cmp	r3, #0
+ 80007f6:	d105      	bne.n	8000804 <HAL_ADC_Init+0x154>
+      {
+        /* Enable the selected ADC group regular discontinuous mode */
+        tmpCFGR1 |= ADC_CFGR1_DISCEN;
+ 80007f8:	68bb      	ldr	r3, [r7, #8]
+ 80007fa:	2280      	movs	r2, #128	; 0x80
+ 80007fc:	0252      	lsls	r2, r2, #9
+ 80007fe:	4313      	orrs	r3, r2
+ 8000800:	60bb      	str	r3, [r7, #8]
+ 8000802:	e00b      	b.n	800081c <HAL_ADC_Init+0x16c>
+        /* ADC regular group discontinuous was intended to be enabled,        */
+        /* but ADC regular group modes continuous and sequencer discontinuous */
+        /* cannot be enabled simultaneously.                                  */
+        
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8000804:	687b      	ldr	r3, [r7, #4]
+ 8000806:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8000808:	2220      	movs	r2, #32
+ 800080a:	431a      	orrs	r2, r3
+ 800080c:	687b      	ldr	r3, [r7, #4]
+ 800080e:	639a      	str	r2, [r3, #56]	; 0x38
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8000810:	687b      	ldr	r3, [r7, #4]
+ 8000812:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8000814:	2201      	movs	r2, #1
+ 8000816:	431a      	orrs	r2, r3
+ 8000818:	687b      	ldr	r3, [r7, #4]
+ 800081a:	63da      	str	r2, [r3, #60]	; 0x3c
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /* Note: This configuration keeps the hardware feature of parameter       */
+    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+    /*       software start.                                                  */
+    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ 800081c:	687b      	ldr	r3, [r7, #4]
+ 800081e:	69da      	ldr	r2, [r3, #28]
+ 8000820:	23c2      	movs	r3, #194	; 0xc2
+ 8000822:	33ff      	adds	r3, #255	; 0xff
+ 8000824:	429a      	cmp	r2, r3
+ 8000826:	d007      	beq.n	8000838 <HAL_ADC_Init+0x188>
+    {
+      tmpCFGR1 |= ( hadc->Init.ExternalTrigConv    |
+ 8000828:	687b      	ldr	r3, [r7, #4]
+ 800082a:	69da      	ldr	r2, [r3, #28]
+                    hadc->Init.ExternalTrigConvEdge );
+ 800082c:	687b      	ldr	r3, [r7, #4]
+ 800082e:	6a1b      	ldr	r3, [r3, #32]
+      tmpCFGR1 |= ( hadc->Init.ExternalTrigConv    |
+ 8000830:	4313      	orrs	r3, r2
+ 8000832:	68ba      	ldr	r2, [r7, #8]
+ 8000834:	4313      	orrs	r3, r2
+ 8000836:	60bb      	str	r3, [r7, #8]
+    }
+    
+    /* Update ADC configuration register with previous settings */
+    hadc->Instance->CFGR1 |= tmpCFGR1;
+ 8000838:	687b      	ldr	r3, [r7, #4]
+ 800083a:	681b      	ldr	r3, [r3, #0]
+ 800083c:	68d9      	ldr	r1, [r3, #12]
+ 800083e:	687b      	ldr	r3, [r7, #4]
+ 8000840:	681b      	ldr	r3, [r3, #0]
+ 8000842:	68ba      	ldr	r2, [r7, #8]
+ 8000844:	430a      	orrs	r2, r1
+ 8000846:	60da      	str	r2, [r3, #12]
+    /* Management of parameters "SamplingTimeCommon" and "SamplingTime"       */
+    /* (obsolete): sampling time set in this function if parameter            */
+    /*  "SamplingTimeCommon" has been set to a valid sampling time.           */
+    /* Otherwise, sampling time is set into ADC channel initialization        */
+    /* structure with parameter "SamplingTime" (obsolete).                    */
+    if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+ 8000848:	687b      	ldr	r3, [r7, #4]
+ 800084a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800084c:	2380      	movs	r3, #128	; 0x80
+ 800084e:	055b      	lsls	r3, r3, #21
+ 8000850:	429a      	cmp	r2, r3
+ 8000852:	d01b      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 8000854:	687b      	ldr	r3, [r7, #4]
+ 8000856:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000858:	2b01      	cmp	r3, #1
+ 800085a:	d017      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 800085c:	687b      	ldr	r3, [r7, #4]
+ 800085e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000860:	2b02      	cmp	r3, #2
+ 8000862:	d013      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 8000864:	687b      	ldr	r3, [r7, #4]
+ 8000866:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000868:	2b03      	cmp	r3, #3
+ 800086a:	d00f      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 800086c:	687b      	ldr	r3, [r7, #4]
+ 800086e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000870:	2b04      	cmp	r3, #4
+ 8000872:	d00b      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 8000874:	687b      	ldr	r3, [r7, #4]
+ 8000876:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000878:	2b05      	cmp	r3, #5
+ 800087a:	d007      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 800087c:	687b      	ldr	r3, [r7, #4]
+ 800087e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000880:	2b06      	cmp	r3, #6
+ 8000882:	d003      	beq.n	800088c <HAL_ADC_Init+0x1dc>
+ 8000884:	687b      	ldr	r3, [r7, #4]
+ 8000886:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000888:	2b07      	cmp	r3, #7
+ 800088a:	d112      	bne.n	80008b2 <HAL_ADC_Init+0x202>
+    {
+      /* Channel sampling time configuration */
+      /* Clear the old sample time */
+      hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+ 800088c:	687b      	ldr	r3, [r7, #4]
+ 800088e:	681b      	ldr	r3, [r3, #0]
+ 8000890:	695a      	ldr	r2, [r3, #20]
+ 8000892:	687b      	ldr	r3, [r7, #4]
+ 8000894:	681b      	ldr	r3, [r3, #0]
+ 8000896:	2107      	movs	r1, #7
+ 8000898:	438a      	bics	r2, r1
+ 800089a:	615a      	str	r2, [r3, #20]
+      
+      /* Set the new sample time */
+      hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
+ 800089c:	687b      	ldr	r3, [r7, #4]
+ 800089e:	681b      	ldr	r3, [r3, #0]
+ 80008a0:	6959      	ldr	r1, [r3, #20]
+ 80008a2:	687b      	ldr	r3, [r7, #4]
+ 80008a4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80008a6:	2207      	movs	r2, #7
+ 80008a8:	401a      	ands	r2, r3
+ 80008aa:	687b      	ldr	r3, [r7, #4]
+ 80008ac:	681b      	ldr	r3, [r3, #0]
+ 80008ae:	430a      	orrs	r2, r1
+ 80008b0:	615a      	str	r2, [r3, #20]
+    /* Check back that ADC registers have effectively been configured to      */
+    /* ensure of no potential problem of ADC core IP clocking.                */
+    /* Check through register CFGR1 (excluding analog watchdog configuration: */
+    /* set into separate dedicated function, and bits of ADC resolution set   */
+    /* out of temporary variable 'tmpCFGR1').                                 */
+    if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
+ 80008b2:	687b      	ldr	r3, [r7, #4]
+ 80008b4:	681b      	ldr	r3, [r3, #0]
+ 80008b6:	68db      	ldr	r3, [r3, #12]
+ 80008b8:	4a1c      	ldr	r2, [pc, #112]	; (800092c <HAL_ADC_Init+0x27c>)
+ 80008ba:	4013      	ands	r3, r2
+ 80008bc:	68ba      	ldr	r2, [r7, #8]
+ 80008be:	429a      	cmp	r2, r3
+ 80008c0:	d10b      	bne.n	80008da <HAL_ADC_Init+0x22a>
+         == tmpCFGR1)
+    {
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+ 80008c2:	687b      	ldr	r3, [r7, #4]
+ 80008c4:	2200      	movs	r2, #0
+ 80008c6:	63da      	str	r2, [r3, #60]	; 0x3c
+      
+      /* Set the ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+ 80008c8:	687b      	ldr	r3, [r7, #4]
+ 80008ca:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80008cc:	2203      	movs	r2, #3
+ 80008ce:	4393      	bics	r3, r2
+ 80008d0:	2201      	movs	r2, #1
+ 80008d2:	431a      	orrs	r2, r3
+ 80008d4:	687b      	ldr	r3, [r7, #4]
+ 80008d6:	639a      	str	r2, [r3, #56]	; 0x38
+    if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
+ 80008d8:	e01c      	b.n	8000914 <HAL_ADC_Init+0x264>
+                        HAL_ADC_STATE_READY);
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      ADC_STATE_CLR_SET(hadc->State,
+ 80008da:	687b      	ldr	r3, [r7, #4]
+ 80008dc:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 80008de:	2212      	movs	r2, #18
+ 80008e0:	4393      	bics	r3, r2
+ 80008e2:	2210      	movs	r2, #16
+ 80008e4:	431a      	orrs	r2, r3
+ 80008e6:	687b      	ldr	r3, [r7, #4]
+ 80008e8:	639a      	str	r2, [r3, #56]	; 0x38
+                        HAL_ADC_STATE_BUSY_INTERNAL,
+                        HAL_ADC_STATE_ERROR_INTERNAL);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 80008ea:	687b      	ldr	r3, [r7, #4]
+ 80008ec:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 80008ee:	2201      	movs	r2, #1
+ 80008f0:	431a      	orrs	r2, r3
+ 80008f2:	687b      	ldr	r3, [r7, #4]
+ 80008f4:	63da      	str	r2, [r3, #60]	; 0x3c
+      
+      tmp_hal_status = HAL_ERROR;
+ 80008f6:	230f      	movs	r3, #15
+ 80008f8:	18fb      	adds	r3, r7, r3
+ 80008fa:	2201      	movs	r2, #1
+ 80008fc:	701a      	strb	r2, [r3, #0]
+    if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
+ 80008fe:	e009      	b.n	8000914 <HAL_ADC_Init+0x264>
+  
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 8000900:	687b      	ldr	r3, [r7, #4]
+ 8000902:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8000904:	2210      	movs	r2, #16
+ 8000906:	431a      	orrs	r2, r3
+ 8000908:	687b      	ldr	r3, [r7, #4]
+ 800090a:	639a      	str	r2, [r3, #56]	; 0x38
+        
+    tmp_hal_status = HAL_ERROR;
+ 800090c:	230f      	movs	r3, #15
+ 800090e:	18fb      	adds	r3, r7, r3
+ 8000910:	2201      	movs	r2, #1
+ 8000912:	701a      	strb	r2, [r3, #0]
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+ 8000914:	230f      	movs	r3, #15
+ 8000916:	18fb      	adds	r3, r7, r3
+ 8000918:	781b      	ldrb	r3, [r3, #0]
+}
+ 800091a:	0018      	movs	r0, r3
+ 800091c:	46bd      	mov	sp, r7
+ 800091e:	b004      	add	sp, #16
+ 8000920:	bd80      	pop	{r7, pc}
+ 8000922:	46c0      	nop			; (mov r8, r8)
+ 8000924:	fffffefd 	.word	0xfffffefd
+ 8000928:	fffe0219 	.word	0xfffe0219
+ 800092c:	833fffe7 	.word	0x833fffe7
+
+08000930 <HAL_ADC_ConfigChannel>:
+  * @param  hadc ADC handle
+  * @param  sConfig Structure of ADC channel for regular group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ 8000930:	b580      	push	{r7, lr}
+ 8000932:	b084      	sub	sp, #16
+ 8000934:	af00      	add	r7, sp, #0
+ 8000936:	6078      	str	r0, [r7, #4]
+ 8000938:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 800093a:	230f      	movs	r3, #15
+ 800093c:	18fb      	adds	r3, r7, r3
+ 800093e:	2200      	movs	r2, #0
+ 8000940:	701a      	strb	r2, [r3, #0]
+  __IO uint32_t wait_loop_index = 0U;
+ 8000942:	2300      	movs	r3, #0
+ 8000944:	60bb      	str	r3, [r7, #8]
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_RANK(sConfig->Rank));
+  
+  if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+ 8000946:	687b      	ldr	r3, [r7, #4]
+ 8000948:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 800094a:	2380      	movs	r3, #128	; 0x80
+ 800094c:	055b      	lsls	r3, r3, #21
+ 800094e:	429a      	cmp	r2, r3
+ 8000950:	d011      	beq.n	8000976 <HAL_ADC_ConfigChannel+0x46>
+ 8000952:	687b      	ldr	r3, [r7, #4]
+ 8000954:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000956:	2b01      	cmp	r3, #1
+ 8000958:	d00d      	beq.n	8000976 <HAL_ADC_ConfigChannel+0x46>
+ 800095a:	687b      	ldr	r3, [r7, #4]
+ 800095c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800095e:	2b02      	cmp	r3, #2
+ 8000960:	d009      	beq.n	8000976 <HAL_ADC_ConfigChannel+0x46>
+ 8000962:	687b      	ldr	r3, [r7, #4]
+ 8000964:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000966:	2b03      	cmp	r3, #3
+ 8000968:	d005      	beq.n	8000976 <HAL_ADC_ConfigChannel+0x46>
+ 800096a:	687b      	ldr	r3, [r7, #4]
+ 800096c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800096e:	2b04      	cmp	r3, #4
+ 8000970:	d001      	beq.n	8000976 <HAL_ADC_ConfigChannel+0x46>
+ 8000972:	687b      	ldr	r3, [r7, #4]
+ 8000974:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+  {
+    assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+ 8000976:	687b      	ldr	r3, [r7, #4]
+ 8000978:	2234      	movs	r2, #52	; 0x34
+ 800097a:	5c9b      	ldrb	r3, [r3, r2]
+ 800097c:	2b01      	cmp	r3, #1
+ 800097e:	d101      	bne.n	8000984 <HAL_ADC_ConfigChannel+0x54>
+ 8000980:	2302      	movs	r3, #2
+ 8000982:	e0bb      	b.n	8000afc <HAL_ADC_ConfigChannel+0x1cc>
+ 8000984:	687b      	ldr	r3, [r7, #4]
+ 8000986:	2234      	movs	r2, #52	; 0x34
+ 8000988:	2101      	movs	r1, #1
+ 800098a:	5499      	strb	r1, [r3, r2]
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel sampling time                                                 */
+  /*  - Management of internal measurement channels: VrefInt/TempSensor/Vbat  */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ 800098c:	687b      	ldr	r3, [r7, #4]
+ 800098e:	681b      	ldr	r3, [r3, #0]
+ 8000990:	689b      	ldr	r3, [r3, #8]
+ 8000992:	2204      	movs	r2, #4
+ 8000994:	4013      	ands	r3, r2
+ 8000996:	d000      	beq.n	800099a <HAL_ADC_ConfigChannel+0x6a>
+ 8000998:	e09f      	b.n	8000ada <HAL_ADC_ConfigChannel+0x1aa>
+  {
+    /* Configure channel: depending on rank setting, add it or remove it from */
+    /* ADC conversion sequencer.                                              */
+    if (sConfig->Rank != ADC_RANK_NONE)
+ 800099a:	683b      	ldr	r3, [r7, #0]
+ 800099c:	685b      	ldr	r3, [r3, #4]
+ 800099e:	4a59      	ldr	r2, [pc, #356]	; (8000b04 <HAL_ADC_ConfigChannel+0x1d4>)
+ 80009a0:	4293      	cmp	r3, r2
+ 80009a2:	d100      	bne.n	80009a6 <HAL_ADC_ConfigChannel+0x76>
+ 80009a4:	e077      	b.n	8000a96 <HAL_ADC_ConfigChannel+0x166>
+    {
+      /* Regular sequence configuration */
+      /* Set the channel selection register from the selected channel */
+      hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
+ 80009a6:	687b      	ldr	r3, [r7, #4]
+ 80009a8:	681b      	ldr	r3, [r3, #0]
+ 80009aa:	6a99      	ldr	r1, [r3, #40]	; 0x28
+ 80009ac:	683b      	ldr	r3, [r7, #0]
+ 80009ae:	681b      	ldr	r3, [r3, #0]
+ 80009b0:	2201      	movs	r2, #1
+ 80009b2:	409a      	lsls	r2, r3
+ 80009b4:	687b      	ldr	r3, [r7, #4]
+ 80009b6:	681b      	ldr	r3, [r3, #0]
+ 80009b8:	430a      	orrs	r2, r1
+ 80009ba:	629a      	str	r2, [r3, #40]	; 0x28
+      /* Channel sampling time configuration */
+      /* Management of parameters "SamplingTimeCommon" and "SamplingTime"     */
+      /* (obsolete): sampling time set in this function with                  */
+      /* parameter "SamplingTime" (obsolete) only if not already set into     */
+      /* ADC initialization structure with parameter "SamplingTimeCommon".    */
+      if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+ 80009bc:	687b      	ldr	r3, [r7, #4]
+ 80009be:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80009c0:	2380      	movs	r3, #128	; 0x80
+ 80009c2:	055b      	lsls	r3, r3, #21
+ 80009c4:	429a      	cmp	r2, r3
+ 80009c6:	d037      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009c8:	687b      	ldr	r3, [r7, #4]
+ 80009ca:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009cc:	2b01      	cmp	r3, #1
+ 80009ce:	d033      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009d0:	687b      	ldr	r3, [r7, #4]
+ 80009d2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009d4:	2b02      	cmp	r3, #2
+ 80009d6:	d02f      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009d8:	687b      	ldr	r3, [r7, #4]
+ 80009da:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009dc:	2b03      	cmp	r3, #3
+ 80009de:	d02b      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009e0:	687b      	ldr	r3, [r7, #4]
+ 80009e2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009e4:	2b04      	cmp	r3, #4
+ 80009e6:	d027      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009e8:	687b      	ldr	r3, [r7, #4]
+ 80009ea:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009ec:	2b05      	cmp	r3, #5
+ 80009ee:	d023      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009f0:	687b      	ldr	r3, [r7, #4]
+ 80009f2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009f4:	2b06      	cmp	r3, #6
+ 80009f6:	d01f      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+ 80009f8:	687b      	ldr	r3, [r7, #4]
+ 80009fa:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80009fc:	2b07      	cmp	r3, #7
+ 80009fe:	d01b      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+      {
+        /* Modify sampling time if needed (not needed in case of reoccurrence */
+        /* for several channels programmed consecutively into the sequencer)  */
+        if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
+ 8000a00:	683b      	ldr	r3, [r7, #0]
+ 8000a02:	689a      	ldr	r2, [r3, #8]
+ 8000a04:	687b      	ldr	r3, [r7, #4]
+ 8000a06:	681b      	ldr	r3, [r3, #0]
+ 8000a08:	695b      	ldr	r3, [r3, #20]
+ 8000a0a:	2107      	movs	r1, #7
+ 8000a0c:	400b      	ands	r3, r1
+ 8000a0e:	429a      	cmp	r2, r3
+ 8000a10:	d012      	beq.n	8000a38 <HAL_ADC_ConfigChannel+0x108>
+        {
+          /* Channel sampling time configuration */
+          /* Clear the old sample time */
+          hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+ 8000a12:	687b      	ldr	r3, [r7, #4]
+ 8000a14:	681b      	ldr	r3, [r3, #0]
+ 8000a16:	695a      	ldr	r2, [r3, #20]
+ 8000a18:	687b      	ldr	r3, [r7, #4]
+ 8000a1a:	681b      	ldr	r3, [r3, #0]
+ 8000a1c:	2107      	movs	r1, #7
+ 8000a1e:	438a      	bics	r2, r1
+ 8000a20:	615a      	str	r2, [r3, #20]
+          
+          /* Set the new sample time */
+          hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
+ 8000a22:	687b      	ldr	r3, [r7, #4]
+ 8000a24:	681b      	ldr	r3, [r3, #0]
+ 8000a26:	6959      	ldr	r1, [r3, #20]
+ 8000a28:	683b      	ldr	r3, [r7, #0]
+ 8000a2a:	689b      	ldr	r3, [r3, #8]
+ 8000a2c:	2207      	movs	r2, #7
+ 8000a2e:	401a      	ands	r2, r3
+ 8000a30:	687b      	ldr	r3, [r7, #4]
+ 8000a32:	681b      	ldr	r3, [r3, #0]
+ 8000a34:	430a      	orrs	r2, r1
+ 8000a36:	615a      	str	r2, [r3, #20]
+      /* internal measurement paths enable: If internal channel selected,     */
+      /* enable dedicated internal buffers and path.                          */
+      /* Note: these internal measurement paths can be disabled using         */
+      /*       HAL_ADC_DeInit() or removing the channel from sequencer with   */
+      /*       channel configuration parameter "Rank".                        */
+      if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ 8000a38:	683b      	ldr	r3, [r7, #0]
+ 8000a3a:	681b      	ldr	r3, [r3, #0]
+ 8000a3c:	2b10      	cmp	r3, #16
+ 8000a3e:	d003      	beq.n	8000a48 <HAL_ADC_ConfigChannel+0x118>
+ 8000a40:	683b      	ldr	r3, [r7, #0]
+ 8000a42:	681b      	ldr	r3, [r3, #0]
+ 8000a44:	2b11      	cmp	r3, #17
+ 8000a46:	d152      	bne.n	8000aee <HAL_ADC_ConfigChannel+0x1be>
+      {
+        /* If Channel_16 is selected, enable Temp. sensor measurement path. */
+        /* If Channel_17 is selected, enable VREFINT measurement path. */
+        /* If Channel_18 is selected, enable VBAT measurement path. */
+        ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
+ 8000a48:	4b2f      	ldr	r3, [pc, #188]	; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
+ 8000a4a:	6819      	ldr	r1, [r3, #0]
+ 8000a4c:	683b      	ldr	r3, [r7, #0]
+ 8000a4e:	681b      	ldr	r3, [r3, #0]
+ 8000a50:	2b10      	cmp	r3, #16
+ 8000a52:	d102      	bne.n	8000a5a <HAL_ADC_ConfigChannel+0x12a>
+ 8000a54:	2380      	movs	r3, #128	; 0x80
+ 8000a56:	041b      	lsls	r3, r3, #16
+ 8000a58:	e001      	b.n	8000a5e <HAL_ADC_ConfigChannel+0x12e>
+ 8000a5a:	2380      	movs	r3, #128	; 0x80
+ 8000a5c:	03db      	lsls	r3, r3, #15
+ 8000a5e:	4a2a      	ldr	r2, [pc, #168]	; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
+ 8000a60:	430b      	orrs	r3, r1
+ 8000a62:	6013      	str	r3, [r2, #0]
+        
+        /* If Temp. sensor is selected, wait for stabilization delay */
+        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ 8000a64:	683b      	ldr	r3, [r7, #0]
+ 8000a66:	681b      	ldr	r3, [r3, #0]
+ 8000a68:	2b10      	cmp	r3, #16
+ 8000a6a:	d140      	bne.n	8000aee <HAL_ADC_ConfigChannel+0x1be>
+        {
+          /* Delay for temperature sensor stabilization time */
+          /* Compute number of CPU cycles to wait for */
+          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ 8000a6c:	4b27      	ldr	r3, [pc, #156]	; (8000b0c <HAL_ADC_ConfigChannel+0x1dc>)
+ 8000a6e:	681b      	ldr	r3, [r3, #0]
+ 8000a70:	4927      	ldr	r1, [pc, #156]	; (8000b10 <HAL_ADC_ConfigChannel+0x1e0>)
+ 8000a72:	0018      	movs	r0, r3
+ 8000a74:	f7ff fb48 	bl	8000108 <__udivsi3>
+ 8000a78:	0003      	movs	r3, r0
+ 8000a7a:	001a      	movs	r2, r3
+ 8000a7c:	0013      	movs	r3, r2
+ 8000a7e:	009b      	lsls	r3, r3, #2
+ 8000a80:	189b      	adds	r3, r3, r2
+ 8000a82:	005b      	lsls	r3, r3, #1
+ 8000a84:	60bb      	str	r3, [r7, #8]
+          while(wait_loop_index != 0U)
+ 8000a86:	e002      	b.n	8000a8e <HAL_ADC_ConfigChannel+0x15e>
+          {
+            wait_loop_index--;
+ 8000a88:	68bb      	ldr	r3, [r7, #8]
+ 8000a8a:	3b01      	subs	r3, #1
+ 8000a8c:	60bb      	str	r3, [r7, #8]
+          while(wait_loop_index != 0U)
+ 8000a8e:	68bb      	ldr	r3, [r7, #8]
+ 8000a90:	2b00      	cmp	r3, #0
+ 8000a92:	d1f9      	bne.n	8000a88 <HAL_ADC_ConfigChannel+0x158>
+ 8000a94:	e02b      	b.n	8000aee <HAL_ADC_ConfigChannel+0x1be>
+    }
+    else
+    {
+      /* Regular sequence configuration */
+      /* Reset the channel selection register from the selected channel */
+      hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
+ 8000a96:	687b      	ldr	r3, [r7, #4]
+ 8000a98:	681b      	ldr	r3, [r3, #0]
+ 8000a9a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8000a9c:	683b      	ldr	r3, [r7, #0]
+ 8000a9e:	681b      	ldr	r3, [r3, #0]
+ 8000aa0:	2101      	movs	r1, #1
+ 8000aa2:	4099      	lsls	r1, r3
+ 8000aa4:	000b      	movs	r3, r1
+ 8000aa6:	43d9      	mvns	r1, r3
+ 8000aa8:	687b      	ldr	r3, [r7, #4]
+ 8000aaa:	681b      	ldr	r3, [r3, #0]
+ 8000aac:	400a      	ands	r2, r1
+ 8000aae:	629a      	str	r2, [r3, #40]	; 0x28
+      
+      /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+      /* internal measurement paths disable: If internal channel selected,    */
+      /* disable dedicated internal buffers and path.                         */
+      if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ 8000ab0:	683b      	ldr	r3, [r7, #0]
+ 8000ab2:	681b      	ldr	r3, [r3, #0]
+ 8000ab4:	2b10      	cmp	r3, #16
+ 8000ab6:	d003      	beq.n	8000ac0 <HAL_ADC_ConfigChannel+0x190>
+ 8000ab8:	683b      	ldr	r3, [r7, #0]
+ 8000aba:	681b      	ldr	r3, [r3, #0]
+ 8000abc:	2b11      	cmp	r3, #17
+ 8000abe:	d116      	bne.n	8000aee <HAL_ADC_ConfigChannel+0x1be>
+      {
+        /* If Channel_16 is selected, disable Temp. sensor measurement path. */
+        /* If Channel_17 is selected, disable VREFINT measurement path. */
+        /* If Channel_18 is selected, disable VBAT measurement path. */
+        ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
+ 8000ac0:	4b11      	ldr	r3, [pc, #68]	; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
+ 8000ac2:	6819      	ldr	r1, [r3, #0]
+ 8000ac4:	683b      	ldr	r3, [r7, #0]
+ 8000ac6:	681b      	ldr	r3, [r3, #0]
+ 8000ac8:	2b10      	cmp	r3, #16
+ 8000aca:	d101      	bne.n	8000ad0 <HAL_ADC_ConfigChannel+0x1a0>
+ 8000acc:	4a11      	ldr	r2, [pc, #68]	; (8000b14 <HAL_ADC_ConfigChannel+0x1e4>)
+ 8000ace:	e000      	b.n	8000ad2 <HAL_ADC_ConfigChannel+0x1a2>
+ 8000ad0:	4a11      	ldr	r2, [pc, #68]	; (8000b18 <HAL_ADC_ConfigChannel+0x1e8>)
+ 8000ad2:	4b0d      	ldr	r3, [pc, #52]	; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
+ 8000ad4:	400a      	ands	r2, r1
+ 8000ad6:	601a      	str	r2, [r3, #0]
+ 8000ad8:	e009      	b.n	8000aee <HAL_ADC_ConfigChannel+0x1be>
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8000ada:	687b      	ldr	r3, [r7, #4]
+ 8000adc:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8000ade:	2220      	movs	r2, #32
+ 8000ae0:	431a      	orrs	r2, r3
+ 8000ae2:	687b      	ldr	r3, [r7, #4]
+ 8000ae4:	639a      	str	r2, [r3, #56]	; 0x38
+    
+    tmp_hal_status = HAL_ERROR;
+ 8000ae6:	230f      	movs	r3, #15
+ 8000ae8:	18fb      	adds	r3, r7, r3
+ 8000aea:	2201      	movs	r2, #1
+ 8000aec:	701a      	strb	r2, [r3, #0]
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+ 8000aee:	687b      	ldr	r3, [r7, #4]
+ 8000af0:	2234      	movs	r2, #52	; 0x34
+ 8000af2:	2100      	movs	r1, #0
+ 8000af4:	5499      	strb	r1, [r3, r2]
+  
+  /* Return function status */
+  return tmp_hal_status;
+ 8000af6:	230f      	movs	r3, #15
+ 8000af8:	18fb      	adds	r3, r7, r3
+ 8000afa:	781b      	ldrb	r3, [r3, #0]
+}
+ 8000afc:	0018      	movs	r0, r3
+ 8000afe:	46bd      	mov	sp, r7
+ 8000b00:	b004      	add	sp, #16
+ 8000b02:	bd80      	pop	{r7, pc}
+ 8000b04:	00001001 	.word	0x00001001
+ 8000b08:	40012708 	.word	0x40012708
+ 8000b0c:	20000000 	.word	0x20000000
+ 8000b10:	000f4240 	.word	0x000f4240
+ 8000b14:	ff7fffff 	.word	0xff7fffff
+ 8000b18:	ffbfffff 	.word	0xffbfffff
+
+08000b1c <__NVIC_SetPriority>:
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
   \note    The priority cannot be set for every processor exception.
  */
 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
- 80004a4:	b590      	push	{r4, r7, lr}
- 80004a6:	b083      	sub	sp, #12
- 80004a8:	af00      	add	r7, sp, #0
- 80004aa:	0002      	movs	r2, r0
- 80004ac:	6039      	str	r1, [r7, #0]
- 80004ae:	1dfb      	adds	r3, r7, #7
- 80004b0:	701a      	strb	r2, [r3, #0]
+ 8000b1c:	b590      	push	{r4, r7, lr}
+ 8000b1e:	b083      	sub	sp, #12
+ 8000b20:	af00      	add	r7, sp, #0
+ 8000b22:	0002      	movs	r2, r0
+ 8000b24:	6039      	str	r1, [r7, #0]
+ 8000b26:	1dfb      	adds	r3, r7, #7
+ 8000b28:	701a      	strb	r2, [r3, #0]
   if ((int32_t)(IRQn) >= 0)
- 80004b2:	1dfb      	adds	r3, r7, #7
- 80004b4:	781b      	ldrb	r3, [r3, #0]
- 80004b6:	2b7f      	cmp	r3, #127	; 0x7f
- 80004b8:	d828      	bhi.n	800050c <__NVIC_SetPriority+0x68>
+ 8000b2a:	1dfb      	adds	r3, r7, #7
+ 8000b2c:	781b      	ldrb	r3, [r3, #0]
+ 8000b2e:	2b7f      	cmp	r3, #127	; 0x7f
+ 8000b30:	d828      	bhi.n	8000b84 <__NVIC_SetPriority+0x68>
   {
     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80004ba:	4a2f      	ldr	r2, [pc, #188]	; (8000578 <__NVIC_SetPriority+0xd4>)
- 80004bc:	1dfb      	adds	r3, r7, #7
- 80004be:	781b      	ldrb	r3, [r3, #0]
- 80004c0:	b25b      	sxtb	r3, r3
- 80004c2:	089b      	lsrs	r3, r3, #2
- 80004c4:	33c0      	adds	r3, #192	; 0xc0
- 80004c6:	009b      	lsls	r3, r3, #2
- 80004c8:	589b      	ldr	r3, [r3, r2]
- 80004ca:	1dfa      	adds	r2, r7, #7
- 80004cc:	7812      	ldrb	r2, [r2, #0]
- 80004ce:	0011      	movs	r1, r2
- 80004d0:	2203      	movs	r2, #3
- 80004d2:	400a      	ands	r2, r1
- 80004d4:	00d2      	lsls	r2, r2, #3
- 80004d6:	21ff      	movs	r1, #255	; 0xff
- 80004d8:	4091      	lsls	r1, r2
- 80004da:	000a      	movs	r2, r1
- 80004dc:	43d2      	mvns	r2, r2
- 80004de:	401a      	ands	r2, r3
- 80004e0:	0011      	movs	r1, r2
+ 8000b32:	4a2f      	ldr	r2, [pc, #188]	; (8000bf0 <__NVIC_SetPriority+0xd4>)
+ 8000b34:	1dfb      	adds	r3, r7, #7
+ 8000b36:	781b      	ldrb	r3, [r3, #0]
+ 8000b38:	b25b      	sxtb	r3, r3
+ 8000b3a:	089b      	lsrs	r3, r3, #2
+ 8000b3c:	33c0      	adds	r3, #192	; 0xc0
+ 8000b3e:	009b      	lsls	r3, r3, #2
+ 8000b40:	589b      	ldr	r3, [r3, r2]
+ 8000b42:	1dfa      	adds	r2, r7, #7
+ 8000b44:	7812      	ldrb	r2, [r2, #0]
+ 8000b46:	0011      	movs	r1, r2
+ 8000b48:	2203      	movs	r2, #3
+ 8000b4a:	400a      	ands	r2, r1
+ 8000b4c:	00d2      	lsls	r2, r2, #3
+ 8000b4e:	21ff      	movs	r1, #255	; 0xff
+ 8000b50:	4091      	lsls	r1, r2
+ 8000b52:	000a      	movs	r2, r1
+ 8000b54:	43d2      	mvns	r2, r2
+ 8000b56:	401a      	ands	r2, r3
+ 8000b58:	0011      	movs	r1, r2
        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 80004e2:	683b      	ldr	r3, [r7, #0]
- 80004e4:	019b      	lsls	r3, r3, #6
- 80004e6:	22ff      	movs	r2, #255	; 0xff
- 80004e8:	401a      	ands	r2, r3
- 80004ea:	1dfb      	adds	r3, r7, #7
- 80004ec:	781b      	ldrb	r3, [r3, #0]
- 80004ee:	0018      	movs	r0, r3
- 80004f0:	2303      	movs	r3, #3
- 80004f2:	4003      	ands	r3, r0
- 80004f4:	00db      	lsls	r3, r3, #3
- 80004f6:	409a      	lsls	r2, r3
+ 8000b5a:	683b      	ldr	r3, [r7, #0]
+ 8000b5c:	019b      	lsls	r3, r3, #6
+ 8000b5e:	22ff      	movs	r2, #255	; 0xff
+ 8000b60:	401a      	ands	r2, r3
+ 8000b62:	1dfb      	adds	r3, r7, #7
+ 8000b64:	781b      	ldrb	r3, [r3, #0]
+ 8000b66:	0018      	movs	r0, r3
+ 8000b68:	2303      	movs	r3, #3
+ 8000b6a:	4003      	ands	r3, r0
+ 8000b6c:	00db      	lsls	r3, r3, #3
+ 8000b6e:	409a      	lsls	r2, r3
     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80004f8:	481f      	ldr	r0, [pc, #124]	; (8000578 <__NVIC_SetPriority+0xd4>)
- 80004fa:	1dfb      	adds	r3, r7, #7
- 80004fc:	781b      	ldrb	r3, [r3, #0]
- 80004fe:	b25b      	sxtb	r3, r3
- 8000500:	089b      	lsrs	r3, r3, #2
- 8000502:	430a      	orrs	r2, r1
- 8000504:	33c0      	adds	r3, #192	; 0xc0
- 8000506:	009b      	lsls	r3, r3, #2
- 8000508:	501a      	str	r2, [r3, r0]
+ 8000b70:	481f      	ldr	r0, [pc, #124]	; (8000bf0 <__NVIC_SetPriority+0xd4>)
+ 8000b72:	1dfb      	adds	r3, r7, #7
+ 8000b74:	781b      	ldrb	r3, [r3, #0]
+ 8000b76:	b25b      	sxtb	r3, r3
+ 8000b78:	089b      	lsrs	r3, r3, #2
+ 8000b7a:	430a      	orrs	r2, r1
+ 8000b7c:	33c0      	adds	r3, #192	; 0xc0
+ 8000b7e:	009b      	lsls	r3, r3, #2
+ 8000b80:	501a      	str	r2, [r3, r0]
   else
   {
     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
 }
- 800050a:	e031      	b.n	8000570 <__NVIC_SetPriority+0xcc>
+ 8000b82:	e031      	b.n	8000be8 <__NVIC_SetPriority+0xcc>
     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 800050c:	4a1b      	ldr	r2, [pc, #108]	; (800057c <__NVIC_SetPriority+0xd8>)
- 800050e:	1dfb      	adds	r3, r7, #7
- 8000510:	781b      	ldrb	r3, [r3, #0]
- 8000512:	0019      	movs	r1, r3
- 8000514:	230f      	movs	r3, #15
- 8000516:	400b      	ands	r3, r1
- 8000518:	3b08      	subs	r3, #8
- 800051a:	089b      	lsrs	r3, r3, #2
- 800051c:	3306      	adds	r3, #6
- 800051e:	009b      	lsls	r3, r3, #2
- 8000520:	18d3      	adds	r3, r2, r3
- 8000522:	3304      	adds	r3, #4
- 8000524:	681b      	ldr	r3, [r3, #0]
- 8000526:	1dfa      	adds	r2, r7, #7
- 8000528:	7812      	ldrb	r2, [r2, #0]
- 800052a:	0011      	movs	r1, r2
- 800052c:	2203      	movs	r2, #3
- 800052e:	400a      	ands	r2, r1
- 8000530:	00d2      	lsls	r2, r2, #3
- 8000532:	21ff      	movs	r1, #255	; 0xff
- 8000534:	4091      	lsls	r1, r2
- 8000536:	000a      	movs	r2, r1
- 8000538:	43d2      	mvns	r2, r2
- 800053a:	401a      	ands	r2, r3
- 800053c:	0011      	movs	r1, r2
+ 8000b84:	4a1b      	ldr	r2, [pc, #108]	; (8000bf4 <__NVIC_SetPriority+0xd8>)
+ 8000b86:	1dfb      	adds	r3, r7, #7
+ 8000b88:	781b      	ldrb	r3, [r3, #0]
+ 8000b8a:	0019      	movs	r1, r3
+ 8000b8c:	230f      	movs	r3, #15
+ 8000b8e:	400b      	ands	r3, r1
+ 8000b90:	3b08      	subs	r3, #8
+ 8000b92:	089b      	lsrs	r3, r3, #2
+ 8000b94:	3306      	adds	r3, #6
+ 8000b96:	009b      	lsls	r3, r3, #2
+ 8000b98:	18d3      	adds	r3, r2, r3
+ 8000b9a:	3304      	adds	r3, #4
+ 8000b9c:	681b      	ldr	r3, [r3, #0]
+ 8000b9e:	1dfa      	adds	r2, r7, #7
+ 8000ba0:	7812      	ldrb	r2, [r2, #0]
+ 8000ba2:	0011      	movs	r1, r2
+ 8000ba4:	2203      	movs	r2, #3
+ 8000ba6:	400a      	ands	r2, r1
+ 8000ba8:	00d2      	lsls	r2, r2, #3
+ 8000baa:	21ff      	movs	r1, #255	; 0xff
+ 8000bac:	4091      	lsls	r1, r2
+ 8000bae:	000a      	movs	r2, r1
+ 8000bb0:	43d2      	mvns	r2, r2
+ 8000bb2:	401a      	ands	r2, r3
+ 8000bb4:	0011      	movs	r1, r2
        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 800053e:	683b      	ldr	r3, [r7, #0]
- 8000540:	019b      	lsls	r3, r3, #6
- 8000542:	22ff      	movs	r2, #255	; 0xff
- 8000544:	401a      	ands	r2, r3
- 8000546:	1dfb      	adds	r3, r7, #7
- 8000548:	781b      	ldrb	r3, [r3, #0]
- 800054a:	0018      	movs	r0, r3
- 800054c:	2303      	movs	r3, #3
- 800054e:	4003      	ands	r3, r0
- 8000550:	00db      	lsls	r3, r3, #3
- 8000552:	409a      	lsls	r2, r3
+ 8000bb6:	683b      	ldr	r3, [r7, #0]
+ 8000bb8:	019b      	lsls	r3, r3, #6
+ 8000bba:	22ff      	movs	r2, #255	; 0xff
+ 8000bbc:	401a      	ands	r2, r3
+ 8000bbe:	1dfb      	adds	r3, r7, #7
+ 8000bc0:	781b      	ldrb	r3, [r3, #0]
+ 8000bc2:	0018      	movs	r0, r3
+ 8000bc4:	2303      	movs	r3, #3
+ 8000bc6:	4003      	ands	r3, r0
+ 8000bc8:	00db      	lsls	r3, r3, #3
+ 8000bca:	409a      	lsls	r2, r3
     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8000554:	4809      	ldr	r0, [pc, #36]	; (800057c <__NVIC_SetPriority+0xd8>)
- 8000556:	1dfb      	adds	r3, r7, #7
- 8000558:	781b      	ldrb	r3, [r3, #0]
- 800055a:	001c      	movs	r4, r3
- 800055c:	230f      	movs	r3, #15
- 800055e:	4023      	ands	r3, r4
- 8000560:	3b08      	subs	r3, #8
- 8000562:	089b      	lsrs	r3, r3, #2
- 8000564:	430a      	orrs	r2, r1
- 8000566:	3306      	adds	r3, #6
- 8000568:	009b      	lsls	r3, r3, #2
- 800056a:	18c3      	adds	r3, r0, r3
- 800056c:	3304      	adds	r3, #4
- 800056e:	601a      	str	r2, [r3, #0]
+ 8000bcc:	4809      	ldr	r0, [pc, #36]	; (8000bf4 <__NVIC_SetPriority+0xd8>)
+ 8000bce:	1dfb      	adds	r3, r7, #7
+ 8000bd0:	781b      	ldrb	r3, [r3, #0]
+ 8000bd2:	001c      	movs	r4, r3
+ 8000bd4:	230f      	movs	r3, #15
+ 8000bd6:	4023      	ands	r3, r4
+ 8000bd8:	3b08      	subs	r3, #8
+ 8000bda:	089b      	lsrs	r3, r3, #2
+ 8000bdc:	430a      	orrs	r2, r1
+ 8000bde:	3306      	adds	r3, #6
+ 8000be0:	009b      	lsls	r3, r3, #2
+ 8000be2:	18c3      	adds	r3, r0, r3
+ 8000be4:	3304      	adds	r3, #4
+ 8000be6:	601a      	str	r2, [r3, #0]
 }
- 8000570:	46c0      	nop			; (mov r8, r8)
- 8000572:	46bd      	mov	sp, r7
- 8000574:	b003      	add	sp, #12
- 8000576:	bd90      	pop	{r4, r7, pc}
- 8000578:	e000e100 	.word	0xe000e100
- 800057c:	e000ed00 	.word	0xe000ed00
+ 8000be8:	46c0      	nop			; (mov r8, r8)
+ 8000bea:	46bd      	mov	sp, r7
+ 8000bec:	b003      	add	sp, #12
+ 8000bee:	bd90      	pop	{r4, r7, pc}
+ 8000bf0:	e000e100 	.word	0xe000e100
+ 8000bf4:	e000ed00 	.word	0xe000ed00
 
-08000580 <SysTick_Config>:
+08000bf8 <SysTick_Config>:
   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
- 8000580:	b580      	push	{r7, lr}
- 8000582:	b082      	sub	sp, #8
- 8000584:	af00      	add	r7, sp, #0
- 8000586:	6078      	str	r0, [r7, #4]
+ 8000bf8:	b580      	push	{r7, lr}
+ 8000bfa:	b082      	sub	sp, #8
+ 8000bfc:	af00      	add	r7, sp, #0
+ 8000bfe:	6078      	str	r0, [r7, #4]
   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8000588:	687b      	ldr	r3, [r7, #4]
- 800058a:	1e5a      	subs	r2, r3, #1
- 800058c:	2380      	movs	r3, #128	; 0x80
- 800058e:	045b      	lsls	r3, r3, #17
- 8000590:	429a      	cmp	r2, r3
- 8000592:	d301      	bcc.n	8000598 <SysTick_Config+0x18>
+ 8000c00:	687b      	ldr	r3, [r7, #4]
+ 8000c02:	1e5a      	subs	r2, r3, #1
+ 8000c04:	2380      	movs	r3, #128	; 0x80
+ 8000c06:	045b      	lsls	r3, r3, #17
+ 8000c08:	429a      	cmp	r2, r3
+ 8000c0a:	d301      	bcc.n	8000c10 <SysTick_Config+0x18>
   {
     return (1UL);                                                   /* Reload value impossible */
- 8000594:	2301      	movs	r3, #1
- 8000596:	e010      	b.n	80005ba <SysTick_Config+0x3a>
+ 8000c0c:	2301      	movs	r3, #1
+ 8000c0e:	e010      	b.n	8000c32 <SysTick_Config+0x3a>
   }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
- 8000598:	4b0a      	ldr	r3, [pc, #40]	; (80005c4 <SysTick_Config+0x44>)
- 800059a:	687a      	ldr	r2, [r7, #4]
- 800059c:	3a01      	subs	r2, #1
- 800059e:	605a      	str	r2, [r3, #4]
+ 8000c10:	4b0a      	ldr	r3, [pc, #40]	; (8000c3c <SysTick_Config+0x44>)
+ 8000c12:	687a      	ldr	r2, [r7, #4]
+ 8000c14:	3a01      	subs	r2, #1
+ 8000c16:	605a      	str	r2, [r3, #4]
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 80005a0:	2301      	movs	r3, #1
- 80005a2:	425b      	negs	r3, r3
- 80005a4:	2103      	movs	r1, #3
- 80005a6:	0018      	movs	r0, r3
- 80005a8:	f7ff ff7c 	bl	80004a4 <__NVIC_SetPriority>
+ 8000c18:	2301      	movs	r3, #1
+ 8000c1a:	425b      	negs	r3, r3
+ 8000c1c:	2103      	movs	r1, #3
+ 8000c1e:	0018      	movs	r0, r3
+ 8000c20:	f7ff ff7c 	bl	8000b1c <__NVIC_SetPriority>
   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
- 80005ac:	4b05      	ldr	r3, [pc, #20]	; (80005c4 <SysTick_Config+0x44>)
- 80005ae:	2200      	movs	r2, #0
- 80005b0:	609a      	str	r2, [r3, #8]
+ 8000c24:	4b05      	ldr	r3, [pc, #20]	; (8000c3c <SysTick_Config+0x44>)
+ 8000c26:	2200      	movs	r2, #0
+ 8000c28:	609a      	str	r2, [r3, #8]
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
- 80005b2:	4b04      	ldr	r3, [pc, #16]	; (80005c4 <SysTick_Config+0x44>)
- 80005b4:	2207      	movs	r2, #7
- 80005b6:	601a      	str	r2, [r3, #0]
+ 8000c2a:	4b04      	ldr	r3, [pc, #16]	; (8000c3c <SysTick_Config+0x44>)
+ 8000c2c:	2207      	movs	r2, #7
+ 8000c2e:	601a      	str	r2, [r3, #0]
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                     /* Function successful */
- 80005b8:	2300      	movs	r3, #0
+ 8000c30:	2300      	movs	r3, #0
 }
- 80005ba:	0018      	movs	r0, r3
- 80005bc:	46bd      	mov	sp, r7
- 80005be:	b002      	add	sp, #8
- 80005c0:	bd80      	pop	{r7, pc}
- 80005c2:	46c0      	nop			; (mov r8, r8)
- 80005c4:	e000e010 	.word	0xe000e010
+ 8000c32:	0018      	movs	r0, r3
+ 8000c34:	46bd      	mov	sp, r7
+ 8000c36:	b002      	add	sp, #8
+ 8000c38:	bd80      	pop	{r7, pc}
+ 8000c3a:	46c0      	nop			; (mov r8, r8)
+ 8000c3c:	e000e010 	.word	0xe000e010
 
-080005c8 <HAL_NVIC_SetPriority>:
+08000c40 <HAL_NVIC_SetPriority>:
   *         with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 
   *         no subpriority supported in Cortex M0 based products.   
   * @retval None
   */
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 { 
- 80005c8:	b580      	push	{r7, lr}
- 80005ca:	b084      	sub	sp, #16
- 80005cc:	af00      	add	r7, sp, #0
- 80005ce:	60b9      	str	r1, [r7, #8]
- 80005d0:	607a      	str	r2, [r7, #4]
- 80005d2:	210f      	movs	r1, #15
- 80005d4:	187b      	adds	r3, r7, r1
- 80005d6:	1c02      	adds	r2, r0, #0
- 80005d8:	701a      	strb	r2, [r3, #0]
+ 8000c40:	b580      	push	{r7, lr}
+ 8000c42:	b084      	sub	sp, #16
+ 8000c44:	af00      	add	r7, sp, #0
+ 8000c46:	60b9      	str	r1, [r7, #8]
+ 8000c48:	607a      	str	r2, [r7, #4]
+ 8000c4a:	210f      	movs	r1, #15
+ 8000c4c:	187b      	adds	r3, r7, r1
+ 8000c4e:	1c02      	adds	r2, r0, #0
+ 8000c50:	701a      	strb	r2, [r3, #0]
   /* Check the parameters */
   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
   NVIC_SetPriority(IRQn,PreemptPriority);
- 80005da:	68ba      	ldr	r2, [r7, #8]
- 80005dc:	187b      	adds	r3, r7, r1
- 80005de:	781b      	ldrb	r3, [r3, #0]
- 80005e0:	b25b      	sxtb	r3, r3
- 80005e2:	0011      	movs	r1, r2
- 80005e4:	0018      	movs	r0, r3
- 80005e6:	f7ff ff5d 	bl	80004a4 <__NVIC_SetPriority>
+ 8000c52:	68ba      	ldr	r2, [r7, #8]
+ 8000c54:	187b      	adds	r3, r7, r1
+ 8000c56:	781b      	ldrb	r3, [r3, #0]
+ 8000c58:	b25b      	sxtb	r3, r3
+ 8000c5a:	0011      	movs	r1, r2
+ 8000c5c:	0018      	movs	r0, r3
+ 8000c5e:	f7ff ff5d 	bl	8000b1c <__NVIC_SetPriority>
 }
- 80005ea:	46c0      	nop			; (mov r8, r8)
- 80005ec:	46bd      	mov	sp, r7
- 80005ee:	b004      	add	sp, #16
- 80005f0:	bd80      	pop	{r7, pc}
+ 8000c62:	46c0      	nop			; (mov r8, r8)
+ 8000c64:	46bd      	mov	sp, r7
+ 8000c66:	b004      	add	sp, #16
+ 8000c68:	bd80      	pop	{r7, pc}
 
-080005f2 <HAL_SYSTICK_Config>:
+08000c6a <HAL_SYSTICK_Config>:
   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
   * @retval status:  - 0  Function succeeded.
   *                  - 1  Function failed.
   */
 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
 {
- 80005f2:	b580      	push	{r7, lr}
- 80005f4:	b082      	sub	sp, #8
- 80005f6:	af00      	add	r7, sp, #0
- 80005f8:	6078      	str	r0, [r7, #4]
+ 8000c6a:	b580      	push	{r7, lr}
+ 8000c6c:	b082      	sub	sp, #8
+ 8000c6e:	af00      	add	r7, sp, #0
+ 8000c70:	6078      	str	r0, [r7, #4]
    return SysTick_Config(TicksNumb);
- 80005fa:	687b      	ldr	r3, [r7, #4]
- 80005fc:	0018      	movs	r0, r3
- 80005fe:	f7ff ffbf 	bl	8000580 <SysTick_Config>
- 8000602:	0003      	movs	r3, r0
+ 8000c72:	687b      	ldr	r3, [r7, #4]
+ 8000c74:	0018      	movs	r0, r3
+ 8000c76:	f7ff ffbf 	bl	8000bf8 <SysTick_Config>
+ 8000c7a:	0003      	movs	r3, r0
 }
- 8000604:	0018      	movs	r0, r3
- 8000606:	46bd      	mov	sp, r7
- 8000608:	b002      	add	sp, #8
- 800060a:	bd80      	pop	{r7, pc}
+ 8000c7c:	0018      	movs	r0, r3
+ 8000c7e:	46bd      	mov	sp, r7
+ 8000c80:	b002      	add	sp, #8
+ 8000c82:	bd80      	pop	{r7, pc}
 
-0800060c <HAL_RCC_OscConfig>:
+08000c84 <HAL_GPIO_Init>:
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 8000c84:	b580      	push	{r7, lr}
+ 8000c86:	b086      	sub	sp, #24
+ 8000c88:	af00      	add	r7, sp, #0
+ 8000c8a:	6078      	str	r0, [r7, #4]
+ 8000c8c:	6039      	str	r1, [r7, #0]
+  uint32_t position = 0x00u;
+ 8000c8e:	2300      	movs	r3, #0
+ 8000c90:	617b      	str	r3, [r7, #20]
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+ 8000c92:	e14f      	b.n	8000f34 <HAL_GPIO_Init+0x2b0>
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1uL << position);
+ 8000c94:	683b      	ldr	r3, [r7, #0]
+ 8000c96:	681b      	ldr	r3, [r3, #0]
+ 8000c98:	2101      	movs	r1, #1
+ 8000c9a:	697a      	ldr	r2, [r7, #20]
+ 8000c9c:	4091      	lsls	r1, r2
+ 8000c9e:	000a      	movs	r2, r1
+ 8000ca0:	4013      	ands	r3, r2
+ 8000ca2:	60fb      	str	r3, [r7, #12]
+
+    if (iocurrent != 0x00u)
+ 8000ca4:	68fb      	ldr	r3, [r7, #12]
+ 8000ca6:	2b00      	cmp	r3, #0
+ 8000ca8:	d100      	bne.n	8000cac <HAL_GPIO_Init+0x28>
+ 8000caa:	e140      	b.n	8000f2e <HAL_GPIO_Init+0x2aa>
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 8000cac:	683b      	ldr	r3, [r7, #0]
+ 8000cae:	685b      	ldr	r3, [r3, #4]
+ 8000cb0:	2203      	movs	r2, #3
+ 8000cb2:	4013      	ands	r3, r2
+ 8000cb4:	2b01      	cmp	r3, #1
+ 8000cb6:	d005      	beq.n	8000cc4 <HAL_GPIO_Init+0x40>
+         ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 8000cb8:	683b      	ldr	r3, [r7, #0]
+ 8000cba:	685b      	ldr	r3, [r3, #4]
+ 8000cbc:	2203      	movs	r2, #3
+ 8000cbe:	4013      	ands	r3, r2
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 8000cc0:	2b02      	cmp	r3, #2
+ 8000cc2:	d130      	bne.n	8000d26 <HAL_GPIO_Init+0xa2>
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+ 8000cc4:	687b      	ldr	r3, [r7, #4]
+ 8000cc6:	689b      	ldr	r3, [r3, #8]
+ 8000cc8:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
+ 8000cca:	697b      	ldr	r3, [r7, #20]
+ 8000ccc:	005b      	lsls	r3, r3, #1
+ 8000cce:	2203      	movs	r2, #3
+ 8000cd0:	409a      	lsls	r2, r3
+ 8000cd2:	0013      	movs	r3, r2
+ 8000cd4:	43da      	mvns	r2, r3
+ 8000cd6:	693b      	ldr	r3, [r7, #16]
+ 8000cd8:	4013      	ands	r3, r2
+ 8000cda:	613b      	str	r3, [r7, #16]
+        temp |= (GPIO_Init->Speed << (position * 2u));
+ 8000cdc:	683b      	ldr	r3, [r7, #0]
+ 8000cde:	68da      	ldr	r2, [r3, #12]
+ 8000ce0:	697b      	ldr	r3, [r7, #20]
+ 8000ce2:	005b      	lsls	r3, r3, #1
+ 8000ce4:	409a      	lsls	r2, r3
+ 8000ce6:	0013      	movs	r3, r2
+ 8000ce8:	693a      	ldr	r2, [r7, #16]
+ 8000cea:	4313      	orrs	r3, r2
+ 8000cec:	613b      	str	r3, [r7, #16]
+        GPIOx->OSPEEDR = temp;
+ 8000cee:	687b      	ldr	r3, [r7, #4]
+ 8000cf0:	693a      	ldr	r2, [r7, #16]
+ 8000cf2:	609a      	str	r2, [r3, #8]
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+ 8000cf4:	687b      	ldr	r3, [r7, #4]
+ 8000cf6:	685b      	ldr	r3, [r3, #4]
+ 8000cf8:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 8000cfa:	2201      	movs	r2, #1
+ 8000cfc:	697b      	ldr	r3, [r7, #20]
+ 8000cfe:	409a      	lsls	r2, r3
+ 8000d00:	0013      	movs	r3, r2
+ 8000d02:	43da      	mvns	r2, r3
+ 8000d04:	693b      	ldr	r3, [r7, #16]
+ 8000d06:	4013      	ands	r3, r2
+ 8000d08:	613b      	str	r3, [r7, #16]
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ 8000d0a:	683b      	ldr	r3, [r7, #0]
+ 8000d0c:	685b      	ldr	r3, [r3, #4]
+ 8000d0e:	091b      	lsrs	r3, r3, #4
+ 8000d10:	2201      	movs	r2, #1
+ 8000d12:	401a      	ands	r2, r3
+ 8000d14:	697b      	ldr	r3, [r7, #20]
+ 8000d16:	409a      	lsls	r2, r3
+ 8000d18:	0013      	movs	r3, r2
+ 8000d1a:	693a      	ldr	r2, [r7, #16]
+ 8000d1c:	4313      	orrs	r3, r2
+ 8000d1e:	613b      	str	r3, [r7, #16]
+        GPIOx->OTYPER = temp;
+ 8000d20:	687b      	ldr	r3, [r7, #4]
+ 8000d22:	693a      	ldr	r2, [r7, #16]
+ 8000d24:	605a      	str	r2, [r3, #4]
+      }
+      
+      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 8000d26:	683b      	ldr	r3, [r7, #0]
+ 8000d28:	685b      	ldr	r3, [r3, #4]
+ 8000d2a:	2203      	movs	r2, #3
+ 8000d2c:	4013      	ands	r3, r2
+ 8000d2e:	2b03      	cmp	r3, #3
+ 8000d30:	d017      	beq.n	8000d62 <HAL_GPIO_Init+0xde>
+      {
+        /* Check the Pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+ 8000d32:	687b      	ldr	r3, [r7, #4]
+ 8000d34:	68db      	ldr	r3, [r3, #12]
+ 8000d36:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
+ 8000d38:	697b      	ldr	r3, [r7, #20]
+ 8000d3a:	005b      	lsls	r3, r3, #1
+ 8000d3c:	2203      	movs	r2, #3
+ 8000d3e:	409a      	lsls	r2, r3
+ 8000d40:	0013      	movs	r3, r2
+ 8000d42:	43da      	mvns	r2, r3
+ 8000d44:	693b      	ldr	r3, [r7, #16]
+ 8000d46:	4013      	ands	r3, r2
+ 8000d48:	613b      	str	r3, [r7, #16]
+        temp |= ((GPIO_Init->Pull) << (position * 2u));
+ 8000d4a:	683b      	ldr	r3, [r7, #0]
+ 8000d4c:	689a      	ldr	r2, [r3, #8]
+ 8000d4e:	697b      	ldr	r3, [r7, #20]
+ 8000d50:	005b      	lsls	r3, r3, #1
+ 8000d52:	409a      	lsls	r2, r3
+ 8000d54:	0013      	movs	r3, r2
+ 8000d56:	693a      	ldr	r2, [r7, #16]
+ 8000d58:	4313      	orrs	r3, r2
+ 8000d5a:	613b      	str	r3, [r7, #16]
+        GPIOx->PUPDR = temp;
+ 8000d5c:	687b      	ldr	r3, [r7, #4]
+ 8000d5e:	693a      	ldr	r2, [r7, #16]
+ 8000d60:	60da      	str	r2, [r3, #12]
+      }
+
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 8000d62:	683b      	ldr	r3, [r7, #0]
+ 8000d64:	685b      	ldr	r3, [r3, #4]
+ 8000d66:	2203      	movs	r2, #3
+ 8000d68:	4013      	ands	r3, r2
+ 8000d6a:	2b02      	cmp	r3, #2
+ 8000d6c:	d123      	bne.n	8000db6 <HAL_GPIO_Init+0x132>
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3u];
+ 8000d6e:	697b      	ldr	r3, [r7, #20]
+ 8000d70:	08da      	lsrs	r2, r3, #3
+ 8000d72:	687b      	ldr	r3, [r7, #4]
+ 8000d74:	3208      	adds	r2, #8
+ 8000d76:	0092      	lsls	r2, r2, #2
+ 8000d78:	58d3      	ldr	r3, [r2, r3]
+ 8000d7a:	613b      	str	r3, [r7, #16]
+        temp &= ~(0xFu << ((position & 0x07u) * 4u));
+ 8000d7c:	697b      	ldr	r3, [r7, #20]
+ 8000d7e:	2207      	movs	r2, #7
+ 8000d80:	4013      	ands	r3, r2
+ 8000d82:	009b      	lsls	r3, r3, #2
+ 8000d84:	220f      	movs	r2, #15
+ 8000d86:	409a      	lsls	r2, r3
+ 8000d88:	0013      	movs	r3, r2
+ 8000d8a:	43da      	mvns	r2, r3
+ 8000d8c:	693b      	ldr	r3, [r7, #16]
+ 8000d8e:	4013      	ands	r3, r2
+ 8000d90:	613b      	str	r3, [r7, #16]
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+ 8000d92:	683b      	ldr	r3, [r7, #0]
+ 8000d94:	691a      	ldr	r2, [r3, #16]
+ 8000d96:	697b      	ldr	r3, [r7, #20]
+ 8000d98:	2107      	movs	r1, #7
+ 8000d9a:	400b      	ands	r3, r1
+ 8000d9c:	009b      	lsls	r3, r3, #2
+ 8000d9e:	409a      	lsls	r2, r3
+ 8000da0:	0013      	movs	r3, r2
+ 8000da2:	693a      	ldr	r2, [r7, #16]
+ 8000da4:	4313      	orrs	r3, r2
+ 8000da6:	613b      	str	r3, [r7, #16]
+        GPIOx->AFR[position >> 3u] = temp;
+ 8000da8:	697b      	ldr	r3, [r7, #20]
+ 8000daa:	08da      	lsrs	r2, r3, #3
+ 8000dac:	687b      	ldr	r3, [r7, #4]
+ 8000dae:	3208      	adds	r2, #8
+ 8000db0:	0092      	lsls	r2, r2, #2
+ 8000db2:	6939      	ldr	r1, [r7, #16]
+ 8000db4:	50d1      	str	r1, [r2, r3]
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+ 8000db6:	687b      	ldr	r3, [r7, #4]
+ 8000db8:	681b      	ldr	r3, [r3, #0]
+ 8000dba:	613b      	str	r3, [r7, #16]
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
+ 8000dbc:	697b      	ldr	r3, [r7, #20]
+ 8000dbe:	005b      	lsls	r3, r3, #1
+ 8000dc0:	2203      	movs	r2, #3
+ 8000dc2:	409a      	lsls	r2, r3
+ 8000dc4:	0013      	movs	r3, r2
+ 8000dc6:	43da      	mvns	r2, r3
+ 8000dc8:	693b      	ldr	r3, [r7, #16]
+ 8000dca:	4013      	ands	r3, r2
+ 8000dcc:	613b      	str	r3, [r7, #16]
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
+ 8000dce:	683b      	ldr	r3, [r7, #0]
+ 8000dd0:	685b      	ldr	r3, [r3, #4]
+ 8000dd2:	2203      	movs	r2, #3
+ 8000dd4:	401a      	ands	r2, r3
+ 8000dd6:	697b      	ldr	r3, [r7, #20]
+ 8000dd8:	005b      	lsls	r3, r3, #1
+ 8000dda:	409a      	lsls	r2, r3
+ 8000ddc:	0013      	movs	r3, r2
+ 8000dde:	693a      	ldr	r2, [r7, #16]
+ 8000de0:	4313      	orrs	r3, r2
+ 8000de2:	613b      	str	r3, [r7, #16]
+      GPIOx->MODER = temp;
+ 8000de4:	687b      	ldr	r3, [r7, #4]
+ 8000de6:	693a      	ldr	r2, [r7, #16]
+ 8000de8:	601a      	str	r2, [r3, #0]
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+ 8000dea:	683b      	ldr	r3, [r7, #0]
+ 8000dec:	685a      	ldr	r2, [r3, #4]
+ 8000dee:	23c0      	movs	r3, #192	; 0xc0
+ 8000df0:	029b      	lsls	r3, r3, #10
+ 8000df2:	4013      	ands	r3, r2
+ 8000df4:	d100      	bne.n	8000df8 <HAL_GPIO_Init+0x174>
+ 8000df6:	e09a      	b.n	8000f2e <HAL_GPIO_Init+0x2aa>
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8000df8:	4b54      	ldr	r3, [pc, #336]	; (8000f4c <HAL_GPIO_Init+0x2c8>)
+ 8000dfa:	699a      	ldr	r2, [r3, #24]
+ 8000dfc:	4b53      	ldr	r3, [pc, #332]	; (8000f4c <HAL_GPIO_Init+0x2c8>)
+ 8000dfe:	2101      	movs	r1, #1
+ 8000e00:	430a      	orrs	r2, r1
+ 8000e02:	619a      	str	r2, [r3, #24]
+ 8000e04:	4b51      	ldr	r3, [pc, #324]	; (8000f4c <HAL_GPIO_Init+0x2c8>)
+ 8000e06:	699b      	ldr	r3, [r3, #24]
+ 8000e08:	2201      	movs	r2, #1
+ 8000e0a:	4013      	ands	r3, r2
+ 8000e0c:	60bb      	str	r3, [r7, #8]
+ 8000e0e:	68bb      	ldr	r3, [r7, #8]
+
+        temp = SYSCFG->EXTICR[position >> 2u];
+ 8000e10:	4a4f      	ldr	r2, [pc, #316]	; (8000f50 <HAL_GPIO_Init+0x2cc>)
+ 8000e12:	697b      	ldr	r3, [r7, #20]
+ 8000e14:	089b      	lsrs	r3, r3, #2
+ 8000e16:	3302      	adds	r3, #2
+ 8000e18:	009b      	lsls	r3, r3, #2
+ 8000e1a:	589b      	ldr	r3, [r3, r2]
+ 8000e1c:	613b      	str	r3, [r7, #16]
+        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
+ 8000e1e:	697b      	ldr	r3, [r7, #20]
+ 8000e20:	2203      	movs	r2, #3
+ 8000e22:	4013      	ands	r3, r2
+ 8000e24:	009b      	lsls	r3, r3, #2
+ 8000e26:	220f      	movs	r2, #15
+ 8000e28:	409a      	lsls	r2, r3
+ 8000e2a:	0013      	movs	r3, r2
+ 8000e2c:	43da      	mvns	r2, r3
+ 8000e2e:	693b      	ldr	r3, [r7, #16]
+ 8000e30:	4013      	ands	r3, r2
+ 8000e32:	613b      	str	r3, [r7, #16]
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
+ 8000e34:	687a      	ldr	r2, [r7, #4]
+ 8000e36:	2390      	movs	r3, #144	; 0x90
+ 8000e38:	05db      	lsls	r3, r3, #23
+ 8000e3a:	429a      	cmp	r2, r3
+ 8000e3c:	d013      	beq.n	8000e66 <HAL_GPIO_Init+0x1e2>
+ 8000e3e:	687b      	ldr	r3, [r7, #4]
+ 8000e40:	4a44      	ldr	r2, [pc, #272]	; (8000f54 <HAL_GPIO_Init+0x2d0>)
+ 8000e42:	4293      	cmp	r3, r2
+ 8000e44:	d00d      	beq.n	8000e62 <HAL_GPIO_Init+0x1de>
+ 8000e46:	687b      	ldr	r3, [r7, #4]
+ 8000e48:	4a43      	ldr	r2, [pc, #268]	; (8000f58 <HAL_GPIO_Init+0x2d4>)
+ 8000e4a:	4293      	cmp	r3, r2
+ 8000e4c:	d007      	beq.n	8000e5e <HAL_GPIO_Init+0x1da>
+ 8000e4e:	687b      	ldr	r3, [r7, #4]
+ 8000e50:	4a42      	ldr	r2, [pc, #264]	; (8000f5c <HAL_GPIO_Init+0x2d8>)
+ 8000e52:	4293      	cmp	r3, r2
+ 8000e54:	d101      	bne.n	8000e5a <HAL_GPIO_Init+0x1d6>
+ 8000e56:	2303      	movs	r3, #3
+ 8000e58:	e006      	b.n	8000e68 <HAL_GPIO_Init+0x1e4>
+ 8000e5a:	2305      	movs	r3, #5
+ 8000e5c:	e004      	b.n	8000e68 <HAL_GPIO_Init+0x1e4>
+ 8000e5e:	2302      	movs	r3, #2
+ 8000e60:	e002      	b.n	8000e68 <HAL_GPIO_Init+0x1e4>
+ 8000e62:	2301      	movs	r3, #1
+ 8000e64:	e000      	b.n	8000e68 <HAL_GPIO_Init+0x1e4>
+ 8000e66:	2300      	movs	r3, #0
+ 8000e68:	697a      	ldr	r2, [r7, #20]
+ 8000e6a:	2103      	movs	r1, #3
+ 8000e6c:	400a      	ands	r2, r1
+ 8000e6e:	0092      	lsls	r2, r2, #2
+ 8000e70:	4093      	lsls	r3, r2
+ 8000e72:	693a      	ldr	r2, [r7, #16]
+ 8000e74:	4313      	orrs	r3, r2
+ 8000e76:	613b      	str	r3, [r7, #16]
+        SYSCFG->EXTICR[position >> 2u] = temp;
+ 8000e78:	4935      	ldr	r1, [pc, #212]	; (8000f50 <HAL_GPIO_Init+0x2cc>)
+ 8000e7a:	697b      	ldr	r3, [r7, #20]
+ 8000e7c:	089b      	lsrs	r3, r3, #2
+ 8000e7e:	3302      	adds	r3, #2
+ 8000e80:	009b      	lsls	r3, r3, #2
+ 8000e82:	693a      	ldr	r2, [r7, #16]
+ 8000e84:	505a      	str	r2, [r3, r1]
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+ 8000e86:	4b36      	ldr	r3, [pc, #216]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000e88:	681b      	ldr	r3, [r3, #0]
+ 8000e8a:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 8000e8c:	68fb      	ldr	r3, [r7, #12]
+ 8000e8e:	43da      	mvns	r2, r3
+ 8000e90:	693b      	ldr	r3, [r7, #16]
+ 8000e92:	4013      	ands	r3, r2
+ 8000e94:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+ 8000e96:	683b      	ldr	r3, [r7, #0]
+ 8000e98:	685a      	ldr	r2, [r3, #4]
+ 8000e9a:	2380      	movs	r3, #128	; 0x80
+ 8000e9c:	025b      	lsls	r3, r3, #9
+ 8000e9e:	4013      	ands	r3, r2
+ 8000ea0:	d003      	beq.n	8000eaa <HAL_GPIO_Init+0x226>
+        {
+          temp |= iocurrent;
+ 8000ea2:	693a      	ldr	r2, [r7, #16]
+ 8000ea4:	68fb      	ldr	r3, [r7, #12]
+ 8000ea6:	4313      	orrs	r3, r2
+ 8000ea8:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->IMR = temp;
+ 8000eaa:	4b2d      	ldr	r3, [pc, #180]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000eac:	693a      	ldr	r2, [r7, #16]
+ 8000eae:	601a      	str	r2, [r3, #0]
+
+        temp = EXTI->EMR;
+ 8000eb0:	4b2b      	ldr	r3, [pc, #172]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000eb2:	685b      	ldr	r3, [r3, #4]
+ 8000eb4:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 8000eb6:	68fb      	ldr	r3, [r7, #12]
+ 8000eb8:	43da      	mvns	r2, r3
+ 8000eba:	693b      	ldr	r3, [r7, #16]
+ 8000ebc:	4013      	ands	r3, r2
+ 8000ebe:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+ 8000ec0:	683b      	ldr	r3, [r7, #0]
+ 8000ec2:	685a      	ldr	r2, [r3, #4]
+ 8000ec4:	2380      	movs	r3, #128	; 0x80
+ 8000ec6:	029b      	lsls	r3, r3, #10
+ 8000ec8:	4013      	ands	r3, r2
+ 8000eca:	d003      	beq.n	8000ed4 <HAL_GPIO_Init+0x250>
+        {
+          temp |= iocurrent;
+ 8000ecc:	693a      	ldr	r2, [r7, #16]
+ 8000ece:	68fb      	ldr	r3, [r7, #12]
+ 8000ed0:	4313      	orrs	r3, r2
+ 8000ed2:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->EMR = temp;
+ 8000ed4:	4b22      	ldr	r3, [pc, #136]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000ed6:	693a      	ldr	r2, [r7, #16]
+ 8000ed8:	605a      	str	r2, [r3, #4]
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+ 8000eda:	4b21      	ldr	r3, [pc, #132]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000edc:	689b      	ldr	r3, [r3, #8]
+ 8000ede:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 8000ee0:	68fb      	ldr	r3, [r7, #12]
+ 8000ee2:	43da      	mvns	r2, r3
+ 8000ee4:	693b      	ldr	r3, [r7, #16]
+ 8000ee6:	4013      	ands	r3, r2
+ 8000ee8:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
+ 8000eea:	683b      	ldr	r3, [r7, #0]
+ 8000eec:	685a      	ldr	r2, [r3, #4]
+ 8000eee:	2380      	movs	r3, #128	; 0x80
+ 8000ef0:	035b      	lsls	r3, r3, #13
+ 8000ef2:	4013      	ands	r3, r2
+ 8000ef4:	d003      	beq.n	8000efe <HAL_GPIO_Init+0x27a>
+        {
+          temp |= iocurrent;
+ 8000ef6:	693a      	ldr	r2, [r7, #16]
+ 8000ef8:	68fb      	ldr	r3, [r7, #12]
+ 8000efa:	4313      	orrs	r3, r2
+ 8000efc:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->RTSR = temp;
+ 8000efe:	4b18      	ldr	r3, [pc, #96]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000f00:	693a      	ldr	r2, [r7, #16]
+ 8000f02:	609a      	str	r2, [r3, #8]
+
+        temp = EXTI->FTSR;
+ 8000f04:	4b16      	ldr	r3, [pc, #88]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000f06:	68db      	ldr	r3, [r3, #12]
+ 8000f08:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 8000f0a:	68fb      	ldr	r3, [r7, #12]
+ 8000f0c:	43da      	mvns	r2, r3
+ 8000f0e:	693b      	ldr	r3, [r7, #16]
+ 8000f10:	4013      	ands	r3, r2
+ 8000f12:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
+ 8000f14:	683b      	ldr	r3, [r7, #0]
+ 8000f16:	685a      	ldr	r2, [r3, #4]
+ 8000f18:	2380      	movs	r3, #128	; 0x80
+ 8000f1a:	039b      	lsls	r3, r3, #14
+ 8000f1c:	4013      	ands	r3, r2
+ 8000f1e:	d003      	beq.n	8000f28 <HAL_GPIO_Init+0x2a4>
+        {
+          temp |= iocurrent;
+ 8000f20:	693a      	ldr	r2, [r7, #16]
+ 8000f22:	68fb      	ldr	r3, [r7, #12]
+ 8000f24:	4313      	orrs	r3, r2
+ 8000f26:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->FTSR = temp;
+ 8000f28:	4b0d      	ldr	r3, [pc, #52]	; (8000f60 <HAL_GPIO_Init+0x2dc>)
+ 8000f2a:	693a      	ldr	r2, [r7, #16]
+ 8000f2c:	60da      	str	r2, [r3, #12]
+      }
+    }
+
+    position++;
+ 8000f2e:	697b      	ldr	r3, [r7, #20]
+ 8000f30:	3301      	adds	r3, #1
+ 8000f32:	617b      	str	r3, [r7, #20]
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+ 8000f34:	683b      	ldr	r3, [r7, #0]
+ 8000f36:	681a      	ldr	r2, [r3, #0]
+ 8000f38:	697b      	ldr	r3, [r7, #20]
+ 8000f3a:	40da      	lsrs	r2, r3
+ 8000f3c:	1e13      	subs	r3, r2, #0
+ 8000f3e:	d000      	beq.n	8000f42 <HAL_GPIO_Init+0x2be>
+ 8000f40:	e6a8      	b.n	8000c94 <HAL_GPIO_Init+0x10>
+  } 
+}
+ 8000f42:	46c0      	nop			; (mov r8, r8)
+ 8000f44:	46c0      	nop			; (mov r8, r8)
+ 8000f46:	46bd      	mov	sp, r7
+ 8000f48:	b006      	add	sp, #24
+ 8000f4a:	bd80      	pop	{r7, pc}
+ 8000f4c:	40021000 	.word	0x40021000
+ 8000f50:	40010000 	.word	0x40010000
+ 8000f54:	48000400 	.word	0x48000400
+ 8000f58:	48000800 	.word	0x48000800
+ 8000f5c:	48000c00 	.word	0x48000c00
+ 8000f60:	40010400 	.word	0x40010400
+
+08000f64 <HAL_GPIO_WritePin>:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8000f64:	b580      	push	{r7, lr}
+ 8000f66:	b082      	sub	sp, #8
+ 8000f68:	af00      	add	r7, sp, #0
+ 8000f6a:	6078      	str	r0, [r7, #4]
+ 8000f6c:	0008      	movs	r0, r1
+ 8000f6e:	0011      	movs	r1, r2
+ 8000f70:	1cbb      	adds	r3, r7, #2
+ 8000f72:	1c02      	adds	r2, r0, #0
+ 8000f74:	801a      	strh	r2, [r3, #0]
+ 8000f76:	1c7b      	adds	r3, r7, #1
+ 8000f78:	1c0a      	adds	r2, r1, #0
+ 8000f7a:	701a      	strb	r2, [r3, #0]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+ 8000f7c:	1c7b      	adds	r3, r7, #1
+ 8000f7e:	781b      	ldrb	r3, [r3, #0]
+ 8000f80:	2b00      	cmp	r3, #0
+ 8000f82:	d004      	beq.n	8000f8e <HAL_GPIO_WritePin+0x2a>
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ 8000f84:	1cbb      	adds	r3, r7, #2
+ 8000f86:	881a      	ldrh	r2, [r3, #0]
+ 8000f88:	687b      	ldr	r3, [r7, #4]
+ 8000f8a:	619a      	str	r2, [r3, #24]
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+ 8000f8c:	e003      	b.n	8000f96 <HAL_GPIO_WritePin+0x32>
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+ 8000f8e:	1cbb      	adds	r3, r7, #2
+ 8000f90:	881a      	ldrh	r2, [r3, #0]
+ 8000f92:	687b      	ldr	r3, [r7, #4]
+ 8000f94:	629a      	str	r2, [r3, #40]	; 0x28
+}
+ 8000f96:	46c0      	nop			; (mov r8, r8)
+ 8000f98:	46bd      	mov	sp, r7
+ 8000f9a:	b002      	add	sp, #8
+ 8000f9c:	bd80      	pop	{r7, pc}
+	...
+
+08000fa0 <HAL_RCC_OscConfig>:
   *         supported by this macro. User should request a transition to HSE Off
   *         first and then HSE On or HSE Bypass.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
- 800060c:	b580      	push	{r7, lr}
- 800060e:	b088      	sub	sp, #32
- 8000610:	af00      	add	r7, sp, #0
- 8000612:	6078      	str	r0, [r7, #4]
+ 8000fa0:	b580      	push	{r7, lr}
+ 8000fa2:	b088      	sub	sp, #32
+ 8000fa4:	af00      	add	r7, sp, #0
+ 8000fa6:	6078      	str	r0, [r7, #4]
   uint32_t tickstart;
   uint32_t pll_config;
   uint32_t pll_config2;
 
   /* Check Null pointer */
   if(RCC_OscInitStruct == NULL)
- 8000614:	687b      	ldr	r3, [r7, #4]
- 8000616:	2b00      	cmp	r3, #0
- 8000618:	d101      	bne.n	800061e <HAL_RCC_OscConfig+0x12>
+ 8000fa8:	687b      	ldr	r3, [r7, #4]
+ 8000faa:	2b00      	cmp	r3, #0
+ 8000fac:	d101      	bne.n	8000fb2 <HAL_RCC_OscConfig+0x12>
   {
     return HAL_ERROR;
- 800061a:	2301      	movs	r3, #1
- 800061c:	e301      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8000fae:	2301      	movs	r3, #1
+ 8000fb0:	e301      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
 
   /* Check the parameters */
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 
   /*------------------------------- HSE Configuration ------------------------*/ 
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 800061e:	687b      	ldr	r3, [r7, #4]
- 8000620:	681b      	ldr	r3, [r3, #0]
- 8000622:	2201      	movs	r2, #1
- 8000624:	4013      	ands	r3, r2
- 8000626:	d100      	bne.n	800062a <HAL_RCC_OscConfig+0x1e>
- 8000628:	e08d      	b.n	8000746 <HAL_RCC_OscConfig+0x13a>
+ 8000fb2:	687b      	ldr	r3, [r7, #4]
+ 8000fb4:	681b      	ldr	r3, [r3, #0]
+ 8000fb6:	2201      	movs	r2, #1
+ 8000fb8:	4013      	ands	r3, r2
+ 8000fba:	d100      	bne.n	8000fbe <HAL_RCC_OscConfig+0x1e>
+ 8000fbc:	e08d      	b.n	80010da <HAL_RCC_OscConfig+0x13a>
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
 
     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
- 800062a:	4bc3      	ldr	r3, [pc, #780]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800062c:	685b      	ldr	r3, [r3, #4]
- 800062e:	220c      	movs	r2, #12
- 8000630:	4013      	ands	r3, r2
- 8000632:	2b04      	cmp	r3, #4
- 8000634:	d00e      	beq.n	8000654 <HAL_RCC_OscConfig+0x48>
+ 8000fbe:	4bc3      	ldr	r3, [pc, #780]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8000fc0:	685b      	ldr	r3, [r3, #4]
+ 8000fc2:	220c      	movs	r2, #12
+ 8000fc4:	4013      	ands	r3, r2
+ 8000fc6:	2b04      	cmp	r3, #4
+ 8000fc8:	d00e      	beq.n	8000fe8 <HAL_RCC_OscConfig+0x48>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
- 8000636:	4bc0      	ldr	r3, [pc, #768]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000638:	685b      	ldr	r3, [r3, #4]
- 800063a:	220c      	movs	r2, #12
- 800063c:	4013      	ands	r3, r2
- 800063e:	2b08      	cmp	r3, #8
- 8000640:	d116      	bne.n	8000670 <HAL_RCC_OscConfig+0x64>
- 8000642:	4bbd      	ldr	r3, [pc, #756]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000644:	685a      	ldr	r2, [r3, #4]
- 8000646:	2380      	movs	r3, #128	; 0x80
- 8000648:	025b      	lsls	r3, r3, #9
- 800064a:	401a      	ands	r2, r3
- 800064c:	2380      	movs	r3, #128	; 0x80
- 800064e:	025b      	lsls	r3, r3, #9
- 8000650:	429a      	cmp	r2, r3
- 8000652:	d10d      	bne.n	8000670 <HAL_RCC_OscConfig+0x64>
+ 8000fca:	4bc0      	ldr	r3, [pc, #768]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8000fcc:	685b      	ldr	r3, [r3, #4]
+ 8000fce:	220c      	movs	r2, #12
+ 8000fd0:	4013      	ands	r3, r2
+ 8000fd2:	2b08      	cmp	r3, #8
+ 8000fd4:	d116      	bne.n	8001004 <HAL_RCC_OscConfig+0x64>
+ 8000fd6:	4bbd      	ldr	r3, [pc, #756]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8000fd8:	685a      	ldr	r2, [r3, #4]
+ 8000fda:	2380      	movs	r3, #128	; 0x80
+ 8000fdc:	025b      	lsls	r3, r3, #9
+ 8000fde:	401a      	ands	r2, r3
+ 8000fe0:	2380      	movs	r3, #128	; 0x80
+ 8000fe2:	025b      	lsls	r3, r3, #9
+ 8000fe4:	429a      	cmp	r2, r3
+ 8000fe6:	d10d      	bne.n	8001004 <HAL_RCC_OscConfig+0x64>
     {
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8000654:	4bb8      	ldr	r3, [pc, #736]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000656:	681a      	ldr	r2, [r3, #0]
- 8000658:	2380      	movs	r3, #128	; 0x80
- 800065a:	029b      	lsls	r3, r3, #10
- 800065c:	4013      	ands	r3, r2
- 800065e:	d100      	bne.n	8000662 <HAL_RCC_OscConfig+0x56>
- 8000660:	e070      	b.n	8000744 <HAL_RCC_OscConfig+0x138>
- 8000662:	687b      	ldr	r3, [r7, #4]
- 8000664:	685b      	ldr	r3, [r3, #4]
- 8000666:	2b00      	cmp	r3, #0
- 8000668:	d000      	beq.n	800066c <HAL_RCC_OscConfig+0x60>
- 800066a:	e06b      	b.n	8000744 <HAL_RCC_OscConfig+0x138>
+ 8000fe8:	4bb8      	ldr	r3, [pc, #736]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8000fea:	681a      	ldr	r2, [r3, #0]
+ 8000fec:	2380      	movs	r3, #128	; 0x80
+ 8000fee:	029b      	lsls	r3, r3, #10
+ 8000ff0:	4013      	ands	r3, r2
+ 8000ff2:	d100      	bne.n	8000ff6 <HAL_RCC_OscConfig+0x56>
+ 8000ff4:	e070      	b.n	80010d8 <HAL_RCC_OscConfig+0x138>
+ 8000ff6:	687b      	ldr	r3, [r7, #4]
+ 8000ff8:	685b      	ldr	r3, [r3, #4]
+ 8000ffa:	2b00      	cmp	r3, #0
+ 8000ffc:	d000      	beq.n	8001000 <HAL_RCC_OscConfig+0x60>
+ 8000ffe:	e06b      	b.n	80010d8 <HAL_RCC_OscConfig+0x138>
       {
         return HAL_ERROR;
- 800066c:	2301      	movs	r3, #1
- 800066e:	e2d8      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001000:	2301      	movs	r3, #1
+ 8001002:	e2d8      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       }
     }
     else
     {
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8000670:	687b      	ldr	r3, [r7, #4]
- 8000672:	685b      	ldr	r3, [r3, #4]
- 8000674:	2b01      	cmp	r3, #1
- 8000676:	d107      	bne.n	8000688 <HAL_RCC_OscConfig+0x7c>
- 8000678:	4baf      	ldr	r3, [pc, #700]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800067a:	681a      	ldr	r2, [r3, #0]
- 800067c:	4bae      	ldr	r3, [pc, #696]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800067e:	2180      	movs	r1, #128	; 0x80
- 8000680:	0249      	lsls	r1, r1, #9
- 8000682:	430a      	orrs	r2, r1
- 8000684:	601a      	str	r2, [r3, #0]
- 8000686:	e02f      	b.n	80006e8 <HAL_RCC_OscConfig+0xdc>
- 8000688:	687b      	ldr	r3, [r7, #4]
- 800068a:	685b      	ldr	r3, [r3, #4]
- 800068c:	2b00      	cmp	r3, #0
- 800068e:	d10c      	bne.n	80006aa <HAL_RCC_OscConfig+0x9e>
- 8000690:	4ba9      	ldr	r3, [pc, #676]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000692:	681a      	ldr	r2, [r3, #0]
- 8000694:	4ba8      	ldr	r3, [pc, #672]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000696:	49a9      	ldr	r1, [pc, #676]	; (800093c <HAL_RCC_OscConfig+0x330>)
- 8000698:	400a      	ands	r2, r1
- 800069a:	601a      	str	r2, [r3, #0]
- 800069c:	4ba6      	ldr	r3, [pc, #664]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800069e:	681a      	ldr	r2, [r3, #0]
- 80006a0:	4ba5      	ldr	r3, [pc, #660]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006a2:	49a7      	ldr	r1, [pc, #668]	; (8000940 <HAL_RCC_OscConfig+0x334>)
- 80006a4:	400a      	ands	r2, r1
- 80006a6:	601a      	str	r2, [r3, #0]
- 80006a8:	e01e      	b.n	80006e8 <HAL_RCC_OscConfig+0xdc>
- 80006aa:	687b      	ldr	r3, [r7, #4]
- 80006ac:	685b      	ldr	r3, [r3, #4]
- 80006ae:	2b05      	cmp	r3, #5
- 80006b0:	d10e      	bne.n	80006d0 <HAL_RCC_OscConfig+0xc4>
- 80006b2:	4ba1      	ldr	r3, [pc, #644]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006b4:	681a      	ldr	r2, [r3, #0]
- 80006b6:	4ba0      	ldr	r3, [pc, #640]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006b8:	2180      	movs	r1, #128	; 0x80
- 80006ba:	02c9      	lsls	r1, r1, #11
- 80006bc:	430a      	orrs	r2, r1
- 80006be:	601a      	str	r2, [r3, #0]
- 80006c0:	4b9d      	ldr	r3, [pc, #628]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006c2:	681a      	ldr	r2, [r3, #0]
- 80006c4:	4b9c      	ldr	r3, [pc, #624]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006c6:	2180      	movs	r1, #128	; 0x80
- 80006c8:	0249      	lsls	r1, r1, #9
- 80006ca:	430a      	orrs	r2, r1
- 80006cc:	601a      	str	r2, [r3, #0]
- 80006ce:	e00b      	b.n	80006e8 <HAL_RCC_OscConfig+0xdc>
- 80006d0:	4b99      	ldr	r3, [pc, #612]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006d2:	681a      	ldr	r2, [r3, #0]
- 80006d4:	4b98      	ldr	r3, [pc, #608]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006d6:	4999      	ldr	r1, [pc, #612]	; (800093c <HAL_RCC_OscConfig+0x330>)
- 80006d8:	400a      	ands	r2, r1
- 80006da:	601a      	str	r2, [r3, #0]
- 80006dc:	4b96      	ldr	r3, [pc, #600]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006de:	681a      	ldr	r2, [r3, #0]
- 80006e0:	4b95      	ldr	r3, [pc, #596]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80006e2:	4997      	ldr	r1, [pc, #604]	; (8000940 <HAL_RCC_OscConfig+0x334>)
- 80006e4:	400a      	ands	r2, r1
- 80006e6:	601a      	str	r2, [r3, #0]
+ 8001004:	687b      	ldr	r3, [r7, #4]
+ 8001006:	685b      	ldr	r3, [r3, #4]
+ 8001008:	2b01      	cmp	r3, #1
+ 800100a:	d107      	bne.n	800101c <HAL_RCC_OscConfig+0x7c>
+ 800100c:	4baf      	ldr	r3, [pc, #700]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800100e:	681a      	ldr	r2, [r3, #0]
+ 8001010:	4bae      	ldr	r3, [pc, #696]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001012:	2180      	movs	r1, #128	; 0x80
+ 8001014:	0249      	lsls	r1, r1, #9
+ 8001016:	430a      	orrs	r2, r1
+ 8001018:	601a      	str	r2, [r3, #0]
+ 800101a:	e02f      	b.n	800107c <HAL_RCC_OscConfig+0xdc>
+ 800101c:	687b      	ldr	r3, [r7, #4]
+ 800101e:	685b      	ldr	r3, [r3, #4]
+ 8001020:	2b00      	cmp	r3, #0
+ 8001022:	d10c      	bne.n	800103e <HAL_RCC_OscConfig+0x9e>
+ 8001024:	4ba9      	ldr	r3, [pc, #676]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001026:	681a      	ldr	r2, [r3, #0]
+ 8001028:	4ba8      	ldr	r3, [pc, #672]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800102a:	49a9      	ldr	r1, [pc, #676]	; (80012d0 <HAL_RCC_OscConfig+0x330>)
+ 800102c:	400a      	ands	r2, r1
+ 800102e:	601a      	str	r2, [r3, #0]
+ 8001030:	4ba6      	ldr	r3, [pc, #664]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001032:	681a      	ldr	r2, [r3, #0]
+ 8001034:	4ba5      	ldr	r3, [pc, #660]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001036:	49a7      	ldr	r1, [pc, #668]	; (80012d4 <HAL_RCC_OscConfig+0x334>)
+ 8001038:	400a      	ands	r2, r1
+ 800103a:	601a      	str	r2, [r3, #0]
+ 800103c:	e01e      	b.n	800107c <HAL_RCC_OscConfig+0xdc>
+ 800103e:	687b      	ldr	r3, [r7, #4]
+ 8001040:	685b      	ldr	r3, [r3, #4]
+ 8001042:	2b05      	cmp	r3, #5
+ 8001044:	d10e      	bne.n	8001064 <HAL_RCC_OscConfig+0xc4>
+ 8001046:	4ba1      	ldr	r3, [pc, #644]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001048:	681a      	ldr	r2, [r3, #0]
+ 800104a:	4ba0      	ldr	r3, [pc, #640]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800104c:	2180      	movs	r1, #128	; 0x80
+ 800104e:	02c9      	lsls	r1, r1, #11
+ 8001050:	430a      	orrs	r2, r1
+ 8001052:	601a      	str	r2, [r3, #0]
+ 8001054:	4b9d      	ldr	r3, [pc, #628]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001056:	681a      	ldr	r2, [r3, #0]
+ 8001058:	4b9c      	ldr	r3, [pc, #624]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800105a:	2180      	movs	r1, #128	; 0x80
+ 800105c:	0249      	lsls	r1, r1, #9
+ 800105e:	430a      	orrs	r2, r1
+ 8001060:	601a      	str	r2, [r3, #0]
+ 8001062:	e00b      	b.n	800107c <HAL_RCC_OscConfig+0xdc>
+ 8001064:	4b99      	ldr	r3, [pc, #612]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001066:	681a      	ldr	r2, [r3, #0]
+ 8001068:	4b98      	ldr	r3, [pc, #608]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800106a:	4999      	ldr	r1, [pc, #612]	; (80012d0 <HAL_RCC_OscConfig+0x330>)
+ 800106c:	400a      	ands	r2, r1
+ 800106e:	601a      	str	r2, [r3, #0]
+ 8001070:	4b96      	ldr	r3, [pc, #600]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001072:	681a      	ldr	r2, [r3, #0]
+ 8001074:	4b95      	ldr	r3, [pc, #596]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001076:	4997      	ldr	r1, [pc, #604]	; (80012d4 <HAL_RCC_OscConfig+0x334>)
+ 8001078:	400a      	ands	r2, r1
+ 800107a:	601a      	str	r2, [r3, #0]
       
 
        /* Check the HSE State */
       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 80006e8:	687b      	ldr	r3, [r7, #4]
- 80006ea:	685b      	ldr	r3, [r3, #4]
- 80006ec:	2b00      	cmp	r3, #0
- 80006ee:	d014      	beq.n	800071a <HAL_RCC_OscConfig+0x10e>
+ 800107c:	687b      	ldr	r3, [r7, #4]
+ 800107e:	685b      	ldr	r3, [r3, #4]
+ 8001080:	2b00      	cmp	r3, #0
+ 8001082:	d014      	beq.n	80010ae <HAL_RCC_OscConfig+0x10e>
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80006f0:	f7ff fece 	bl	8000490 <HAL_GetTick>
- 80006f4:	0003      	movs	r3, r0
- 80006f6:	61bb      	str	r3, [r7, #24]
+ 8001084:	f7ff fb0a 	bl	800069c <HAL_GetTick>
+ 8001088:	0003      	movs	r3, r0
+ 800108a:	61bb      	str	r3, [r7, #24]
         
         /* Wait till HSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80006f8:	e008      	b.n	800070c <HAL_RCC_OscConfig+0x100>
+ 800108c:	e008      	b.n	80010a0 <HAL_RCC_OscConfig+0x100>
         {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 80006fa:	f7ff fec9 	bl	8000490 <HAL_GetTick>
- 80006fe:	0002      	movs	r2, r0
- 8000700:	69bb      	ldr	r3, [r7, #24]
- 8000702:	1ad3      	subs	r3, r2, r3
- 8000704:	2b64      	cmp	r3, #100	; 0x64
- 8000706:	d901      	bls.n	800070c <HAL_RCC_OscConfig+0x100>
+ 800108e:	f7ff fb05 	bl	800069c <HAL_GetTick>
+ 8001092:	0002      	movs	r2, r0
+ 8001094:	69bb      	ldr	r3, [r7, #24]
+ 8001096:	1ad3      	subs	r3, r2, r3
+ 8001098:	2b64      	cmp	r3, #100	; 0x64
+ 800109a:	d901      	bls.n	80010a0 <HAL_RCC_OscConfig+0x100>
           {
             return HAL_TIMEOUT;
- 8000708:	2303      	movs	r3, #3
- 800070a:	e28a      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 800109c:	2303      	movs	r3, #3
+ 800109e:	e28a      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800070c:	4b8a      	ldr	r3, [pc, #552]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800070e:	681a      	ldr	r2, [r3, #0]
- 8000710:	2380      	movs	r3, #128	; 0x80
- 8000712:	029b      	lsls	r3, r3, #10
- 8000714:	4013      	ands	r3, r2
- 8000716:	d0f0      	beq.n	80006fa <HAL_RCC_OscConfig+0xee>
- 8000718:	e015      	b.n	8000746 <HAL_RCC_OscConfig+0x13a>
+ 80010a0:	4b8a      	ldr	r3, [pc, #552]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80010a2:	681a      	ldr	r2, [r3, #0]
+ 80010a4:	2380      	movs	r3, #128	; 0x80
+ 80010a6:	029b      	lsls	r3, r3, #10
+ 80010a8:	4013      	ands	r3, r2
+ 80010aa:	d0f0      	beq.n	800108e <HAL_RCC_OscConfig+0xee>
+ 80010ac:	e015      	b.n	80010da <HAL_RCC_OscConfig+0x13a>
         }
       }
       else
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 800071a:	f7ff feb9 	bl	8000490 <HAL_GetTick>
- 800071e:	0003      	movs	r3, r0
- 8000720:	61bb      	str	r3, [r7, #24]
+ 80010ae:	f7ff faf5 	bl	800069c <HAL_GetTick>
+ 80010b2:	0003      	movs	r3, r0
+ 80010b4:	61bb      	str	r3, [r7, #24]
         
         /* Wait till HSE is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8000722:	e008      	b.n	8000736 <HAL_RCC_OscConfig+0x12a>
+ 80010b6:	e008      	b.n	80010ca <HAL_RCC_OscConfig+0x12a>
         {
            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8000724:	f7ff feb4 	bl	8000490 <HAL_GetTick>
- 8000728:	0002      	movs	r2, r0
- 800072a:	69bb      	ldr	r3, [r7, #24]
- 800072c:	1ad3      	subs	r3, r2, r3
- 800072e:	2b64      	cmp	r3, #100	; 0x64
- 8000730:	d901      	bls.n	8000736 <HAL_RCC_OscConfig+0x12a>
+ 80010b8:	f7ff faf0 	bl	800069c <HAL_GetTick>
+ 80010bc:	0002      	movs	r2, r0
+ 80010be:	69bb      	ldr	r3, [r7, #24]
+ 80010c0:	1ad3      	subs	r3, r2, r3
+ 80010c2:	2b64      	cmp	r3, #100	; 0x64
+ 80010c4:	d901      	bls.n	80010ca <HAL_RCC_OscConfig+0x12a>
           {
             return HAL_TIMEOUT;
- 8000732:	2303      	movs	r3, #3
- 8000734:	e275      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80010c6:	2303      	movs	r3, #3
+ 80010c8:	e275      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8000736:	4b80      	ldr	r3, [pc, #512]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000738:	681a      	ldr	r2, [r3, #0]
- 800073a:	2380      	movs	r3, #128	; 0x80
- 800073c:	029b      	lsls	r3, r3, #10
- 800073e:	4013      	ands	r3, r2
- 8000740:	d1f0      	bne.n	8000724 <HAL_RCC_OscConfig+0x118>
- 8000742:	e000      	b.n	8000746 <HAL_RCC_OscConfig+0x13a>
+ 80010ca:	4b80      	ldr	r3, [pc, #512]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80010cc:	681a      	ldr	r2, [r3, #0]
+ 80010ce:	2380      	movs	r3, #128	; 0x80
+ 80010d0:	029b      	lsls	r3, r3, #10
+ 80010d2:	4013      	ands	r3, r2
+ 80010d4:	d1f0      	bne.n	80010b8 <HAL_RCC_OscConfig+0x118>
+ 80010d6:	e000      	b.n	80010da <HAL_RCC_OscConfig+0x13a>
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8000744:	46c0      	nop			; (mov r8, r8)
+ 80010d8:	46c0      	nop			; (mov r8, r8)
         }
       }
     }
   }
   /*----------------------------- HSI Configuration --------------------------*/ 
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8000746:	687b      	ldr	r3, [r7, #4]
- 8000748:	681b      	ldr	r3, [r3, #0]
- 800074a:	2202      	movs	r2, #2
- 800074c:	4013      	ands	r3, r2
- 800074e:	d100      	bne.n	8000752 <HAL_RCC_OscConfig+0x146>
- 8000750:	e069      	b.n	8000826 <HAL_RCC_OscConfig+0x21a>
+ 80010da:	687b      	ldr	r3, [r7, #4]
+ 80010dc:	681b      	ldr	r3, [r3, #0]
+ 80010de:	2202      	movs	r2, #2
+ 80010e0:	4013      	ands	r3, r2
+ 80010e2:	d100      	bne.n	80010e6 <HAL_RCC_OscConfig+0x146>
+ 80010e4:	e069      	b.n	80011ba <HAL_RCC_OscConfig+0x21a>
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
     
     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
- 8000752:	4b79      	ldr	r3, [pc, #484]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000754:	685b      	ldr	r3, [r3, #4]
- 8000756:	220c      	movs	r2, #12
- 8000758:	4013      	ands	r3, r2
- 800075a:	d00b      	beq.n	8000774 <HAL_RCC_OscConfig+0x168>
+ 80010e6:	4b79      	ldr	r3, [pc, #484]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80010e8:	685b      	ldr	r3, [r3, #4]
+ 80010ea:	220c      	movs	r2, #12
+ 80010ec:	4013      	ands	r3, r2
+ 80010ee:	d00b      	beq.n	8001108 <HAL_RCC_OscConfig+0x168>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
- 800075c:	4b76      	ldr	r3, [pc, #472]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800075e:	685b      	ldr	r3, [r3, #4]
- 8000760:	220c      	movs	r2, #12
- 8000762:	4013      	ands	r3, r2
- 8000764:	2b08      	cmp	r3, #8
- 8000766:	d11c      	bne.n	80007a2 <HAL_RCC_OscConfig+0x196>
- 8000768:	4b73      	ldr	r3, [pc, #460]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800076a:	685a      	ldr	r2, [r3, #4]
- 800076c:	2380      	movs	r3, #128	; 0x80
- 800076e:	025b      	lsls	r3, r3, #9
- 8000770:	4013      	ands	r3, r2
- 8000772:	d116      	bne.n	80007a2 <HAL_RCC_OscConfig+0x196>
+ 80010f0:	4b76      	ldr	r3, [pc, #472]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80010f2:	685b      	ldr	r3, [r3, #4]
+ 80010f4:	220c      	movs	r2, #12
+ 80010f6:	4013      	ands	r3, r2
+ 80010f8:	2b08      	cmp	r3, #8
+ 80010fa:	d11c      	bne.n	8001136 <HAL_RCC_OscConfig+0x196>
+ 80010fc:	4b73      	ldr	r3, [pc, #460]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80010fe:	685a      	ldr	r2, [r3, #4]
+ 8001100:	2380      	movs	r3, #128	; 0x80
+ 8001102:	025b      	lsls	r3, r3, #9
+ 8001104:	4013      	ands	r3, r2
+ 8001106:	d116      	bne.n	8001136 <HAL_RCC_OscConfig+0x196>
     {
       /* When HSI is used as system clock it will not disabled */
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8000774:	4b70      	ldr	r3, [pc, #448]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000776:	681b      	ldr	r3, [r3, #0]
- 8000778:	2202      	movs	r2, #2
- 800077a:	4013      	ands	r3, r2
- 800077c:	d005      	beq.n	800078a <HAL_RCC_OscConfig+0x17e>
- 800077e:	687b      	ldr	r3, [r7, #4]
- 8000780:	68db      	ldr	r3, [r3, #12]
- 8000782:	2b01      	cmp	r3, #1
- 8000784:	d001      	beq.n	800078a <HAL_RCC_OscConfig+0x17e>
+ 8001108:	4b70      	ldr	r3, [pc, #448]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800110a:	681b      	ldr	r3, [r3, #0]
+ 800110c:	2202      	movs	r2, #2
+ 800110e:	4013      	ands	r3, r2
+ 8001110:	d005      	beq.n	800111e <HAL_RCC_OscConfig+0x17e>
+ 8001112:	687b      	ldr	r3, [r7, #4]
+ 8001114:	68db      	ldr	r3, [r3, #12]
+ 8001116:	2b01      	cmp	r3, #1
+ 8001118:	d001      	beq.n	800111e <HAL_RCC_OscConfig+0x17e>
       {
         return HAL_ERROR;
- 8000786:	2301      	movs	r3, #1
- 8000788:	e24b      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 800111a:	2301      	movs	r3, #1
+ 800111c:	e24b      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       }
       /* Otherwise, just the calibration is allowed */
       else
       {
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 800078a:	4b6b      	ldr	r3, [pc, #428]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800078c:	681b      	ldr	r3, [r3, #0]
- 800078e:	22f8      	movs	r2, #248	; 0xf8
- 8000790:	4393      	bics	r3, r2
- 8000792:	0019      	movs	r1, r3
- 8000794:	687b      	ldr	r3, [r7, #4]
- 8000796:	691b      	ldr	r3, [r3, #16]
- 8000798:	00da      	lsls	r2, r3, #3
- 800079a:	4b67      	ldr	r3, [pc, #412]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800079c:	430a      	orrs	r2, r1
- 800079e:	601a      	str	r2, [r3, #0]
+ 800111e:	4b6b      	ldr	r3, [pc, #428]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001120:	681b      	ldr	r3, [r3, #0]
+ 8001122:	22f8      	movs	r2, #248	; 0xf8
+ 8001124:	4393      	bics	r3, r2
+ 8001126:	0019      	movs	r1, r3
+ 8001128:	687b      	ldr	r3, [r7, #4]
+ 800112a:	691b      	ldr	r3, [r3, #16]
+ 800112c:	00da      	lsls	r2, r3, #3
+ 800112e:	4b67      	ldr	r3, [pc, #412]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001130:	430a      	orrs	r2, r1
+ 8001132:	601a      	str	r2, [r3, #0]
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80007a0:	e041      	b.n	8000826 <HAL_RCC_OscConfig+0x21a>
+ 8001134:	e041      	b.n	80011ba <HAL_RCC_OscConfig+0x21a>
       }
     }
     else
     {
       /* Check the HSI State */
       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- 80007a2:	687b      	ldr	r3, [r7, #4]
- 80007a4:	68db      	ldr	r3, [r3, #12]
- 80007a6:	2b00      	cmp	r3, #0
- 80007a8:	d024      	beq.n	80007f4 <HAL_RCC_OscConfig+0x1e8>
+ 8001136:	687b      	ldr	r3, [r7, #4]
+ 8001138:	68db      	ldr	r3, [r3, #12]
+ 800113a:	2b00      	cmp	r3, #0
+ 800113c:	d024      	beq.n	8001188 <HAL_RCC_OscConfig+0x1e8>
       {
        /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
- 80007aa:	4b63      	ldr	r3, [pc, #396]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007ac:	681a      	ldr	r2, [r3, #0]
- 80007ae:	4b62      	ldr	r3, [pc, #392]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007b0:	2101      	movs	r1, #1
- 80007b2:	430a      	orrs	r2, r1
- 80007b4:	601a      	str	r2, [r3, #0]
+ 800113e:	4b63      	ldr	r3, [pc, #396]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001140:	681a      	ldr	r2, [r3, #0]
+ 8001142:	4b62      	ldr	r3, [pc, #392]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001144:	2101      	movs	r1, #1
+ 8001146:	430a      	orrs	r2, r1
+ 8001148:	601a      	str	r2, [r3, #0]
         
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80007b6:	f7ff fe6b 	bl	8000490 <HAL_GetTick>
- 80007ba:	0003      	movs	r3, r0
- 80007bc:	61bb      	str	r3, [r7, #24]
+ 800114a:	f7ff faa7 	bl	800069c <HAL_GetTick>
+ 800114e:	0003      	movs	r3, r0
+ 8001150:	61bb      	str	r3, [r7, #24]
         
         /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80007be:	e008      	b.n	80007d2 <HAL_RCC_OscConfig+0x1c6>
+ 8001152:	e008      	b.n	8001166 <HAL_RCC_OscConfig+0x1c6>
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80007c0:	f7ff fe66 	bl	8000490 <HAL_GetTick>
- 80007c4:	0002      	movs	r2, r0
- 80007c6:	69bb      	ldr	r3, [r7, #24]
- 80007c8:	1ad3      	subs	r3, r2, r3
- 80007ca:	2b02      	cmp	r3, #2
- 80007cc:	d901      	bls.n	80007d2 <HAL_RCC_OscConfig+0x1c6>
+ 8001154:	f7ff faa2 	bl	800069c <HAL_GetTick>
+ 8001158:	0002      	movs	r2, r0
+ 800115a:	69bb      	ldr	r3, [r7, #24]
+ 800115c:	1ad3      	subs	r3, r2, r3
+ 800115e:	2b02      	cmp	r3, #2
+ 8001160:	d901      	bls.n	8001166 <HAL_RCC_OscConfig+0x1c6>
           {
             return HAL_TIMEOUT;
- 80007ce:	2303      	movs	r3, #3
- 80007d0:	e227      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001162:	2303      	movs	r3, #3
+ 8001164:	e227      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80007d2:	4b59      	ldr	r3, [pc, #356]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007d4:	681b      	ldr	r3, [r3, #0]
- 80007d6:	2202      	movs	r2, #2
- 80007d8:	4013      	ands	r3, r2
- 80007da:	d0f1      	beq.n	80007c0 <HAL_RCC_OscConfig+0x1b4>
+ 8001166:	4b59      	ldr	r3, [pc, #356]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001168:	681b      	ldr	r3, [r3, #0]
+ 800116a:	2202      	movs	r2, #2
+ 800116c:	4013      	ands	r3, r2
+ 800116e:	d0f1      	beq.n	8001154 <HAL_RCC_OscConfig+0x1b4>
           }
         }
                 
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80007dc:	4b56      	ldr	r3, [pc, #344]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007de:	681b      	ldr	r3, [r3, #0]
- 80007e0:	22f8      	movs	r2, #248	; 0xf8
- 80007e2:	4393      	bics	r3, r2
- 80007e4:	0019      	movs	r1, r3
- 80007e6:	687b      	ldr	r3, [r7, #4]
- 80007e8:	691b      	ldr	r3, [r3, #16]
- 80007ea:	00da      	lsls	r2, r3, #3
- 80007ec:	4b52      	ldr	r3, [pc, #328]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007ee:	430a      	orrs	r2, r1
- 80007f0:	601a      	str	r2, [r3, #0]
- 80007f2:	e018      	b.n	8000826 <HAL_RCC_OscConfig+0x21a>
+ 8001170:	4b56      	ldr	r3, [pc, #344]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001172:	681b      	ldr	r3, [r3, #0]
+ 8001174:	22f8      	movs	r2, #248	; 0xf8
+ 8001176:	4393      	bics	r3, r2
+ 8001178:	0019      	movs	r1, r3
+ 800117a:	687b      	ldr	r3, [r7, #4]
+ 800117c:	691b      	ldr	r3, [r3, #16]
+ 800117e:	00da      	lsls	r2, r3, #3
+ 8001180:	4b52      	ldr	r3, [pc, #328]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001182:	430a      	orrs	r2, r1
+ 8001184:	601a      	str	r2, [r3, #0]
+ 8001186:	e018      	b.n	80011ba <HAL_RCC_OscConfig+0x21a>
       }
       else
       {
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
- 80007f4:	4b50      	ldr	r3, [pc, #320]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007f6:	681a      	ldr	r2, [r3, #0]
- 80007f8:	4b4f      	ldr	r3, [pc, #316]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80007fa:	2101      	movs	r1, #1
- 80007fc:	438a      	bics	r2, r1
- 80007fe:	601a      	str	r2, [r3, #0]
+ 8001188:	4b50      	ldr	r3, [pc, #320]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800118a:	681a      	ldr	r2, [r3, #0]
+ 800118c:	4b4f      	ldr	r3, [pc, #316]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800118e:	2101      	movs	r1, #1
+ 8001190:	438a      	bics	r2, r1
+ 8001192:	601a      	str	r2, [r3, #0]
         
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8000800:	f7ff fe46 	bl	8000490 <HAL_GetTick>
- 8000804:	0003      	movs	r3, r0
- 8000806:	61bb      	str	r3, [r7, #24]
+ 8001194:	f7ff fa82 	bl	800069c <HAL_GetTick>
+ 8001198:	0003      	movs	r3, r0
+ 800119a:	61bb      	str	r3, [r7, #24]
         
         /* Wait till HSI is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8000808:	e008      	b.n	800081c <HAL_RCC_OscConfig+0x210>
+ 800119c:	e008      	b.n	80011b0 <HAL_RCC_OscConfig+0x210>
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 800080a:	f7ff fe41 	bl	8000490 <HAL_GetTick>
- 800080e:	0002      	movs	r2, r0
- 8000810:	69bb      	ldr	r3, [r7, #24]
- 8000812:	1ad3      	subs	r3, r2, r3
- 8000814:	2b02      	cmp	r3, #2
- 8000816:	d901      	bls.n	800081c <HAL_RCC_OscConfig+0x210>
+ 800119e:	f7ff fa7d 	bl	800069c <HAL_GetTick>
+ 80011a2:	0002      	movs	r2, r0
+ 80011a4:	69bb      	ldr	r3, [r7, #24]
+ 80011a6:	1ad3      	subs	r3, r2, r3
+ 80011a8:	2b02      	cmp	r3, #2
+ 80011aa:	d901      	bls.n	80011b0 <HAL_RCC_OscConfig+0x210>
           {
             return HAL_TIMEOUT;
- 8000818:	2303      	movs	r3, #3
- 800081a:	e202      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80011ac:	2303      	movs	r3, #3
+ 80011ae:	e202      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 800081c:	4b46      	ldr	r3, [pc, #280]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800081e:	681b      	ldr	r3, [r3, #0]
- 8000820:	2202      	movs	r2, #2
- 8000822:	4013      	ands	r3, r2
- 8000824:	d1f1      	bne.n	800080a <HAL_RCC_OscConfig+0x1fe>
+ 80011b0:	4b46      	ldr	r3, [pc, #280]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80011b2:	681b      	ldr	r3, [r3, #0]
+ 80011b4:	2202      	movs	r2, #2
+ 80011b6:	4013      	ands	r3, r2
+ 80011b8:	d1f1      	bne.n	800119e <HAL_RCC_OscConfig+0x1fe>
         }
       }
     }
   }
   /*------------------------------ LSI Configuration -------------------------*/ 
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8000826:	687b      	ldr	r3, [r7, #4]
- 8000828:	681b      	ldr	r3, [r3, #0]
- 800082a:	2208      	movs	r2, #8
- 800082c:	4013      	ands	r3, r2
- 800082e:	d036      	beq.n	800089e <HAL_RCC_OscConfig+0x292>
+ 80011ba:	687b      	ldr	r3, [r7, #4]
+ 80011bc:	681b      	ldr	r3, [r3, #0]
+ 80011be:	2208      	movs	r2, #8
+ 80011c0:	4013      	ands	r3, r2
+ 80011c2:	d036      	beq.n	8001232 <HAL_RCC_OscConfig+0x292>
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
     
     /* Check the LSI State */
     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- 8000830:	687b      	ldr	r3, [r7, #4]
- 8000832:	69db      	ldr	r3, [r3, #28]
- 8000834:	2b00      	cmp	r3, #0
- 8000836:	d019      	beq.n	800086c <HAL_RCC_OscConfig+0x260>
+ 80011c4:	687b      	ldr	r3, [r7, #4]
+ 80011c6:	69db      	ldr	r3, [r3, #28]
+ 80011c8:	2b00      	cmp	r3, #0
+ 80011ca:	d019      	beq.n	8001200 <HAL_RCC_OscConfig+0x260>
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
- 8000838:	4b3f      	ldr	r3, [pc, #252]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800083a:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 800083c:	4b3e      	ldr	r3, [pc, #248]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800083e:	2101      	movs	r1, #1
- 8000840:	430a      	orrs	r2, r1
- 8000842:	625a      	str	r2, [r3, #36]	; 0x24
+ 80011cc:	4b3f      	ldr	r3, [pc, #252]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80011ce:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 80011d0:	4b3e      	ldr	r3, [pc, #248]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80011d2:	2101      	movs	r1, #1
+ 80011d4:	430a      	orrs	r2, r1
+ 80011d6:	625a      	str	r2, [r3, #36]	; 0x24
       
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8000844:	f7ff fe24 	bl	8000490 <HAL_GetTick>
- 8000848:	0003      	movs	r3, r0
- 800084a:	61bb      	str	r3, [r7, #24]
+ 80011d8:	f7ff fa60 	bl	800069c <HAL_GetTick>
+ 80011dc:	0003      	movs	r3, r0
+ 80011de:	61bb      	str	r3, [r7, #24]
       
       /* Wait till LSI is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 800084c:	e008      	b.n	8000860 <HAL_RCC_OscConfig+0x254>
+ 80011e0:	e008      	b.n	80011f4 <HAL_RCC_OscConfig+0x254>
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800084e:	f7ff fe1f 	bl	8000490 <HAL_GetTick>
- 8000852:	0002      	movs	r2, r0
- 8000854:	69bb      	ldr	r3, [r7, #24]
- 8000856:	1ad3      	subs	r3, r2, r3
- 8000858:	2b02      	cmp	r3, #2
- 800085a:	d901      	bls.n	8000860 <HAL_RCC_OscConfig+0x254>
+ 80011e2:	f7ff fa5b 	bl	800069c <HAL_GetTick>
+ 80011e6:	0002      	movs	r2, r0
+ 80011e8:	69bb      	ldr	r3, [r7, #24]
+ 80011ea:	1ad3      	subs	r3, r2, r3
+ 80011ec:	2b02      	cmp	r3, #2
+ 80011ee:	d901      	bls.n	80011f4 <HAL_RCC_OscConfig+0x254>
         {
           return HAL_TIMEOUT;
- 800085c:	2303      	movs	r3, #3
- 800085e:	e1e0      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80011f0:	2303      	movs	r3, #3
+ 80011f2:	e1e0      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8000860:	4b35      	ldr	r3, [pc, #212]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000862:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000864:	2202      	movs	r2, #2
- 8000866:	4013      	ands	r3, r2
- 8000868:	d0f1      	beq.n	800084e <HAL_RCC_OscConfig+0x242>
- 800086a:	e018      	b.n	800089e <HAL_RCC_OscConfig+0x292>
+ 80011f4:	4b35      	ldr	r3, [pc, #212]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80011f6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80011f8:	2202      	movs	r2, #2
+ 80011fa:	4013      	ands	r3, r2
+ 80011fc:	d0f1      	beq.n	80011e2 <HAL_RCC_OscConfig+0x242>
+ 80011fe:	e018      	b.n	8001232 <HAL_RCC_OscConfig+0x292>
       }
     }
     else
     {
       /* Disable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_DISABLE();
- 800086c:	4b32      	ldr	r3, [pc, #200]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800086e:	6a5a      	ldr	r2, [r3, #36]	; 0x24
- 8000870:	4b31      	ldr	r3, [pc, #196]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000872:	2101      	movs	r1, #1
- 8000874:	438a      	bics	r2, r1
- 8000876:	625a      	str	r2, [r3, #36]	; 0x24
+ 8001200:	4b32      	ldr	r3, [pc, #200]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001202:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 8001204:	4b31      	ldr	r3, [pc, #196]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001206:	2101      	movs	r1, #1
+ 8001208:	438a      	bics	r2, r1
+ 800120a:	625a      	str	r2, [r3, #36]	; 0x24
       
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8000878:	f7ff fe0a 	bl	8000490 <HAL_GetTick>
- 800087c:	0003      	movs	r3, r0
- 800087e:	61bb      	str	r3, [r7, #24]
+ 800120c:	f7ff fa46 	bl	800069c <HAL_GetTick>
+ 8001210:	0003      	movs	r3, r0
+ 8001212:	61bb      	str	r3, [r7, #24]
       
       /* Wait till LSI is disabled */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8000880:	e008      	b.n	8000894 <HAL_RCC_OscConfig+0x288>
+ 8001214:	e008      	b.n	8001228 <HAL_RCC_OscConfig+0x288>
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8000882:	f7ff fe05 	bl	8000490 <HAL_GetTick>
- 8000886:	0002      	movs	r2, r0
- 8000888:	69bb      	ldr	r3, [r7, #24]
- 800088a:	1ad3      	subs	r3, r2, r3
- 800088c:	2b02      	cmp	r3, #2
- 800088e:	d901      	bls.n	8000894 <HAL_RCC_OscConfig+0x288>
+ 8001216:	f7ff fa41 	bl	800069c <HAL_GetTick>
+ 800121a:	0002      	movs	r2, r0
+ 800121c:	69bb      	ldr	r3, [r7, #24]
+ 800121e:	1ad3      	subs	r3, r2, r3
+ 8001220:	2b02      	cmp	r3, #2
+ 8001222:	d901      	bls.n	8001228 <HAL_RCC_OscConfig+0x288>
         {
           return HAL_TIMEOUT;
- 8000890:	2303      	movs	r3, #3
- 8000892:	e1c6      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001224:	2303      	movs	r3, #3
+ 8001226:	e1c6      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8000894:	4b28      	ldr	r3, [pc, #160]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000896:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000898:	2202      	movs	r2, #2
- 800089a:	4013      	ands	r3, r2
- 800089c:	d1f1      	bne.n	8000882 <HAL_RCC_OscConfig+0x276>
+ 8001228:	4b28      	ldr	r3, [pc, #160]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 800122a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800122c:	2202      	movs	r2, #2
+ 800122e:	4013      	ands	r3, r2
+ 8001230:	d1f1      	bne.n	8001216 <HAL_RCC_OscConfig+0x276>
         }
       }
     }
   }
   /*------------------------------ LSE Configuration -------------------------*/ 
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 800089e:	687b      	ldr	r3, [r7, #4]
- 80008a0:	681b      	ldr	r3, [r3, #0]
- 80008a2:	2204      	movs	r2, #4
- 80008a4:	4013      	ands	r3, r2
- 80008a6:	d100      	bne.n	80008aa <HAL_RCC_OscConfig+0x29e>
- 80008a8:	e0b4      	b.n	8000a14 <HAL_RCC_OscConfig+0x408>
+ 8001232:	687b      	ldr	r3, [r7, #4]
+ 8001234:	681b      	ldr	r3, [r3, #0]
+ 8001236:	2204      	movs	r2, #4
+ 8001238:	4013      	ands	r3, r2
+ 800123a:	d100      	bne.n	800123e <HAL_RCC_OscConfig+0x29e>
+ 800123c:	e0b4      	b.n	80013a8 <HAL_RCC_OscConfig+0x408>
   {
     FlagStatus       pwrclkchanged = RESET;
- 80008aa:	201f      	movs	r0, #31
- 80008ac:	183b      	adds	r3, r7, r0
- 80008ae:	2200      	movs	r2, #0
- 80008b0:	701a      	strb	r2, [r3, #0]
+ 800123e:	201f      	movs	r0, #31
+ 8001240:	183b      	adds	r3, r7, r0
+ 8001242:	2200      	movs	r2, #0
+ 8001244:	701a      	strb	r2, [r3, #0]
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 
     /* Update LSE configuration in Backup Domain control register    */
     /* Requires to enable write access to Backup Domain of necessary */
     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80008b2:	4b21      	ldr	r3, [pc, #132]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80008b4:	69da      	ldr	r2, [r3, #28]
- 80008b6:	2380      	movs	r3, #128	; 0x80
- 80008b8:	055b      	lsls	r3, r3, #21
- 80008ba:	4013      	ands	r3, r2
- 80008bc:	d110      	bne.n	80008e0 <HAL_RCC_OscConfig+0x2d4>
+ 8001246:	4b21      	ldr	r3, [pc, #132]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001248:	69da      	ldr	r2, [r3, #28]
+ 800124a:	2380      	movs	r3, #128	; 0x80
+ 800124c:	055b      	lsls	r3, r3, #21
+ 800124e:	4013      	ands	r3, r2
+ 8001250:	d110      	bne.n	8001274 <HAL_RCC_OscConfig+0x2d4>
     {
       __HAL_RCC_PWR_CLK_ENABLE();
- 80008be:	4b1e      	ldr	r3, [pc, #120]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80008c0:	69da      	ldr	r2, [r3, #28]
- 80008c2:	4b1d      	ldr	r3, [pc, #116]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80008c4:	2180      	movs	r1, #128	; 0x80
- 80008c6:	0549      	lsls	r1, r1, #21
- 80008c8:	430a      	orrs	r2, r1
- 80008ca:	61da      	str	r2, [r3, #28]
- 80008cc:	4b1a      	ldr	r3, [pc, #104]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 80008ce:	69da      	ldr	r2, [r3, #28]
- 80008d0:	2380      	movs	r3, #128	; 0x80
- 80008d2:	055b      	lsls	r3, r3, #21
- 80008d4:	4013      	ands	r3, r2
- 80008d6:	60fb      	str	r3, [r7, #12]
- 80008d8:	68fb      	ldr	r3, [r7, #12]
+ 8001252:	4b1e      	ldr	r3, [pc, #120]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001254:	69da      	ldr	r2, [r3, #28]
+ 8001256:	4b1d      	ldr	r3, [pc, #116]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001258:	2180      	movs	r1, #128	; 0x80
+ 800125a:	0549      	lsls	r1, r1, #21
+ 800125c:	430a      	orrs	r2, r1
+ 800125e:	61da      	str	r2, [r3, #28]
+ 8001260:	4b1a      	ldr	r3, [pc, #104]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 8001262:	69da      	ldr	r2, [r3, #28]
+ 8001264:	2380      	movs	r3, #128	; 0x80
+ 8001266:	055b      	lsls	r3, r3, #21
+ 8001268:	4013      	ands	r3, r2
+ 800126a:	60fb      	str	r3, [r7, #12]
+ 800126c:	68fb      	ldr	r3, [r7, #12]
       pwrclkchanged = SET;
- 80008da:	183b      	adds	r3, r7, r0
- 80008dc:	2201      	movs	r2, #1
- 80008de:	701a      	strb	r2, [r3, #0]
+ 800126e:	183b      	adds	r3, r7, r0
+ 8001270:	2201      	movs	r2, #1
+ 8001272:	701a      	strb	r2, [r3, #0]
     }
     
     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 80008e0:	4b18      	ldr	r3, [pc, #96]	; (8000944 <HAL_RCC_OscConfig+0x338>)
- 80008e2:	681a      	ldr	r2, [r3, #0]
- 80008e4:	2380      	movs	r3, #128	; 0x80
- 80008e6:	005b      	lsls	r3, r3, #1
- 80008e8:	4013      	ands	r3, r2
- 80008ea:	d11a      	bne.n	8000922 <HAL_RCC_OscConfig+0x316>
+ 8001274:	4b18      	ldr	r3, [pc, #96]	; (80012d8 <HAL_RCC_OscConfig+0x338>)
+ 8001276:	681a      	ldr	r2, [r3, #0]
+ 8001278:	2380      	movs	r3, #128	; 0x80
+ 800127a:	005b      	lsls	r3, r3, #1
+ 800127c:	4013      	ands	r3, r2
+ 800127e:	d11a      	bne.n	80012b6 <HAL_RCC_OscConfig+0x316>
     {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
- 80008ec:	4b15      	ldr	r3, [pc, #84]	; (8000944 <HAL_RCC_OscConfig+0x338>)
- 80008ee:	681a      	ldr	r2, [r3, #0]
- 80008f0:	4b14      	ldr	r3, [pc, #80]	; (8000944 <HAL_RCC_OscConfig+0x338>)
- 80008f2:	2180      	movs	r1, #128	; 0x80
- 80008f4:	0049      	lsls	r1, r1, #1
- 80008f6:	430a      	orrs	r2, r1
- 80008f8:	601a      	str	r2, [r3, #0]
+ 8001280:	4b15      	ldr	r3, [pc, #84]	; (80012d8 <HAL_RCC_OscConfig+0x338>)
+ 8001282:	681a      	ldr	r2, [r3, #0]
+ 8001284:	4b14      	ldr	r3, [pc, #80]	; (80012d8 <HAL_RCC_OscConfig+0x338>)
+ 8001286:	2180      	movs	r1, #128	; 0x80
+ 8001288:	0049      	lsls	r1, r1, #1
+ 800128a:	430a      	orrs	r2, r1
+ 800128c:	601a      	str	r2, [r3, #0]
       
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
- 80008fa:	f7ff fdc9 	bl	8000490 <HAL_GetTick>
- 80008fe:	0003      	movs	r3, r0
- 8000900:	61bb      	str	r3, [r7, #24]
+ 800128e:	f7ff fa05 	bl	800069c <HAL_GetTick>
+ 8001292:	0003      	movs	r3, r0
+ 8001294:	61bb      	str	r3, [r7, #24]
 
       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8000902:	e008      	b.n	8000916 <HAL_RCC_OscConfig+0x30a>
+ 8001296:	e008      	b.n	80012aa <HAL_RCC_OscConfig+0x30a>
       {
         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8000904:	f7ff fdc4 	bl	8000490 <HAL_GetTick>
- 8000908:	0002      	movs	r2, r0
- 800090a:	69bb      	ldr	r3, [r7, #24]
- 800090c:	1ad3      	subs	r3, r2, r3
- 800090e:	2b64      	cmp	r3, #100	; 0x64
- 8000910:	d901      	bls.n	8000916 <HAL_RCC_OscConfig+0x30a>
+ 8001298:	f7ff fa00 	bl	800069c <HAL_GetTick>
+ 800129c:	0002      	movs	r2, r0
+ 800129e:	69bb      	ldr	r3, [r7, #24]
+ 80012a0:	1ad3      	subs	r3, r2, r3
+ 80012a2:	2b64      	cmp	r3, #100	; 0x64
+ 80012a4:	d901      	bls.n	80012aa <HAL_RCC_OscConfig+0x30a>
         {
           return HAL_TIMEOUT;
- 8000912:	2303      	movs	r3, #3
- 8000914:	e185      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80012a6:	2303      	movs	r3, #3
+ 80012a8:	e185      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8000916:	4b0b      	ldr	r3, [pc, #44]	; (8000944 <HAL_RCC_OscConfig+0x338>)
- 8000918:	681a      	ldr	r2, [r3, #0]
- 800091a:	2380      	movs	r3, #128	; 0x80
- 800091c:	005b      	lsls	r3, r3, #1
- 800091e:	4013      	ands	r3, r2
- 8000920:	d0f0      	beq.n	8000904 <HAL_RCC_OscConfig+0x2f8>
+ 80012aa:	4b0b      	ldr	r3, [pc, #44]	; (80012d8 <HAL_RCC_OscConfig+0x338>)
+ 80012ac:	681a      	ldr	r2, [r3, #0]
+ 80012ae:	2380      	movs	r3, #128	; 0x80
+ 80012b0:	005b      	lsls	r3, r3, #1
+ 80012b2:	4013      	ands	r3, r2
+ 80012b4:	d0f0      	beq.n	8001298 <HAL_RCC_OscConfig+0x2f8>
         }
       }
     }
 
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8000922:	687b      	ldr	r3, [r7, #4]
- 8000924:	689b      	ldr	r3, [r3, #8]
- 8000926:	2b01      	cmp	r3, #1
- 8000928:	d10e      	bne.n	8000948 <HAL_RCC_OscConfig+0x33c>
- 800092a:	4b03      	ldr	r3, [pc, #12]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 800092c:	6a1a      	ldr	r2, [r3, #32]
- 800092e:	4b02      	ldr	r3, [pc, #8]	; (8000938 <HAL_RCC_OscConfig+0x32c>)
- 8000930:	2101      	movs	r1, #1
- 8000932:	430a      	orrs	r2, r1
- 8000934:	621a      	str	r2, [r3, #32]
- 8000936:	e035      	b.n	80009a4 <HAL_RCC_OscConfig+0x398>
- 8000938:	40021000 	.word	0x40021000
- 800093c:	fffeffff 	.word	0xfffeffff
- 8000940:	fffbffff 	.word	0xfffbffff
- 8000944:	40007000 	.word	0x40007000
- 8000948:	687b      	ldr	r3, [r7, #4]
- 800094a:	689b      	ldr	r3, [r3, #8]
- 800094c:	2b00      	cmp	r3, #0
- 800094e:	d10c      	bne.n	800096a <HAL_RCC_OscConfig+0x35e>
- 8000950:	4bb6      	ldr	r3, [pc, #728]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000952:	6a1a      	ldr	r2, [r3, #32]
- 8000954:	4bb5      	ldr	r3, [pc, #724]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000956:	2101      	movs	r1, #1
- 8000958:	438a      	bics	r2, r1
- 800095a:	621a      	str	r2, [r3, #32]
- 800095c:	4bb3      	ldr	r3, [pc, #716]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 800095e:	6a1a      	ldr	r2, [r3, #32]
- 8000960:	4bb2      	ldr	r3, [pc, #712]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000962:	2104      	movs	r1, #4
- 8000964:	438a      	bics	r2, r1
- 8000966:	621a      	str	r2, [r3, #32]
- 8000968:	e01c      	b.n	80009a4 <HAL_RCC_OscConfig+0x398>
- 800096a:	687b      	ldr	r3, [r7, #4]
- 800096c:	689b      	ldr	r3, [r3, #8]
- 800096e:	2b05      	cmp	r3, #5
- 8000970:	d10c      	bne.n	800098c <HAL_RCC_OscConfig+0x380>
- 8000972:	4bae      	ldr	r3, [pc, #696]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000974:	6a1a      	ldr	r2, [r3, #32]
- 8000976:	4bad      	ldr	r3, [pc, #692]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000978:	2104      	movs	r1, #4
- 800097a:	430a      	orrs	r2, r1
- 800097c:	621a      	str	r2, [r3, #32]
- 800097e:	4bab      	ldr	r3, [pc, #684]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000980:	6a1a      	ldr	r2, [r3, #32]
- 8000982:	4baa      	ldr	r3, [pc, #680]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000984:	2101      	movs	r1, #1
- 8000986:	430a      	orrs	r2, r1
- 8000988:	621a      	str	r2, [r3, #32]
- 800098a:	e00b      	b.n	80009a4 <HAL_RCC_OscConfig+0x398>
- 800098c:	4ba7      	ldr	r3, [pc, #668]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 800098e:	6a1a      	ldr	r2, [r3, #32]
- 8000990:	4ba6      	ldr	r3, [pc, #664]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000992:	2101      	movs	r1, #1
- 8000994:	438a      	bics	r2, r1
- 8000996:	621a      	str	r2, [r3, #32]
- 8000998:	4ba4      	ldr	r3, [pc, #656]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 800099a:	6a1a      	ldr	r2, [r3, #32]
- 800099c:	4ba3      	ldr	r3, [pc, #652]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 800099e:	2104      	movs	r1, #4
- 80009a0:	438a      	bics	r2, r1
- 80009a2:	621a      	str	r2, [r3, #32]
+ 80012b6:	687b      	ldr	r3, [r7, #4]
+ 80012b8:	689b      	ldr	r3, [r3, #8]
+ 80012ba:	2b01      	cmp	r3, #1
+ 80012bc:	d10e      	bne.n	80012dc <HAL_RCC_OscConfig+0x33c>
+ 80012be:	4b03      	ldr	r3, [pc, #12]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80012c0:	6a1a      	ldr	r2, [r3, #32]
+ 80012c2:	4b02      	ldr	r3, [pc, #8]	; (80012cc <HAL_RCC_OscConfig+0x32c>)
+ 80012c4:	2101      	movs	r1, #1
+ 80012c6:	430a      	orrs	r2, r1
+ 80012c8:	621a      	str	r2, [r3, #32]
+ 80012ca:	e035      	b.n	8001338 <HAL_RCC_OscConfig+0x398>
+ 80012cc:	40021000 	.word	0x40021000
+ 80012d0:	fffeffff 	.word	0xfffeffff
+ 80012d4:	fffbffff 	.word	0xfffbffff
+ 80012d8:	40007000 	.word	0x40007000
+ 80012dc:	687b      	ldr	r3, [r7, #4]
+ 80012de:	689b      	ldr	r3, [r3, #8]
+ 80012e0:	2b00      	cmp	r3, #0
+ 80012e2:	d10c      	bne.n	80012fe <HAL_RCC_OscConfig+0x35e>
+ 80012e4:	4bb6      	ldr	r3, [pc, #728]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80012e6:	6a1a      	ldr	r2, [r3, #32]
+ 80012e8:	4bb5      	ldr	r3, [pc, #724]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80012ea:	2101      	movs	r1, #1
+ 80012ec:	438a      	bics	r2, r1
+ 80012ee:	621a      	str	r2, [r3, #32]
+ 80012f0:	4bb3      	ldr	r3, [pc, #716]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80012f2:	6a1a      	ldr	r2, [r3, #32]
+ 80012f4:	4bb2      	ldr	r3, [pc, #712]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80012f6:	2104      	movs	r1, #4
+ 80012f8:	438a      	bics	r2, r1
+ 80012fa:	621a      	str	r2, [r3, #32]
+ 80012fc:	e01c      	b.n	8001338 <HAL_RCC_OscConfig+0x398>
+ 80012fe:	687b      	ldr	r3, [r7, #4]
+ 8001300:	689b      	ldr	r3, [r3, #8]
+ 8001302:	2b05      	cmp	r3, #5
+ 8001304:	d10c      	bne.n	8001320 <HAL_RCC_OscConfig+0x380>
+ 8001306:	4bae      	ldr	r3, [pc, #696]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001308:	6a1a      	ldr	r2, [r3, #32]
+ 800130a:	4bad      	ldr	r3, [pc, #692]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800130c:	2104      	movs	r1, #4
+ 800130e:	430a      	orrs	r2, r1
+ 8001310:	621a      	str	r2, [r3, #32]
+ 8001312:	4bab      	ldr	r3, [pc, #684]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001314:	6a1a      	ldr	r2, [r3, #32]
+ 8001316:	4baa      	ldr	r3, [pc, #680]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001318:	2101      	movs	r1, #1
+ 800131a:	430a      	orrs	r2, r1
+ 800131c:	621a      	str	r2, [r3, #32]
+ 800131e:	e00b      	b.n	8001338 <HAL_RCC_OscConfig+0x398>
+ 8001320:	4ba7      	ldr	r3, [pc, #668]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001322:	6a1a      	ldr	r2, [r3, #32]
+ 8001324:	4ba6      	ldr	r3, [pc, #664]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001326:	2101      	movs	r1, #1
+ 8001328:	438a      	bics	r2, r1
+ 800132a:	621a      	str	r2, [r3, #32]
+ 800132c:	4ba4      	ldr	r3, [pc, #656]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800132e:	6a1a      	ldr	r2, [r3, #32]
+ 8001330:	4ba3      	ldr	r3, [pc, #652]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001332:	2104      	movs	r1, #4
+ 8001334:	438a      	bics	r2, r1
+ 8001336:	621a      	str	r2, [r3, #32]
     /* Check the LSE State */
     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- 80009a4:	687b      	ldr	r3, [r7, #4]
- 80009a6:	689b      	ldr	r3, [r3, #8]
- 80009a8:	2b00      	cmp	r3, #0
- 80009aa:	d014      	beq.n	80009d6 <HAL_RCC_OscConfig+0x3ca>
+ 8001338:	687b      	ldr	r3, [r7, #4]
+ 800133a:	689b      	ldr	r3, [r3, #8]
+ 800133c:	2b00      	cmp	r3, #0
+ 800133e:	d014      	beq.n	800136a <HAL_RCC_OscConfig+0x3ca>
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 80009ac:	f7ff fd70 	bl	8000490 <HAL_GetTick>
- 80009b0:	0003      	movs	r3, r0
- 80009b2:	61bb      	str	r3, [r7, #24]
+ 8001340:	f7ff f9ac 	bl	800069c <HAL_GetTick>
+ 8001344:	0003      	movs	r3, r0
+ 8001346:	61bb      	str	r3, [r7, #24]
       
       /* Wait till LSE is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80009b4:	e009      	b.n	80009ca <HAL_RCC_OscConfig+0x3be>
+ 8001348:	e009      	b.n	800135e <HAL_RCC_OscConfig+0x3be>
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80009b6:	f7ff fd6b 	bl	8000490 <HAL_GetTick>
- 80009ba:	0002      	movs	r2, r0
- 80009bc:	69bb      	ldr	r3, [r7, #24]
- 80009be:	1ad3      	subs	r3, r2, r3
- 80009c0:	4a9b      	ldr	r2, [pc, #620]	; (8000c30 <HAL_RCC_OscConfig+0x624>)
- 80009c2:	4293      	cmp	r3, r2
- 80009c4:	d901      	bls.n	80009ca <HAL_RCC_OscConfig+0x3be>
+ 800134a:	f7ff f9a7 	bl	800069c <HAL_GetTick>
+ 800134e:	0002      	movs	r2, r0
+ 8001350:	69bb      	ldr	r3, [r7, #24]
+ 8001352:	1ad3      	subs	r3, r2, r3
+ 8001354:	4a9b      	ldr	r2, [pc, #620]	; (80015c4 <HAL_RCC_OscConfig+0x624>)
+ 8001356:	4293      	cmp	r3, r2
+ 8001358:	d901      	bls.n	800135e <HAL_RCC_OscConfig+0x3be>
         {
           return HAL_TIMEOUT;
- 80009c6:	2303      	movs	r3, #3
- 80009c8:	e12b      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 800135a:	2303      	movs	r3, #3
+ 800135c:	e12b      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80009ca:	4b98      	ldr	r3, [pc, #608]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 80009cc:	6a1b      	ldr	r3, [r3, #32]
- 80009ce:	2202      	movs	r2, #2
- 80009d0:	4013      	ands	r3, r2
- 80009d2:	d0f0      	beq.n	80009b6 <HAL_RCC_OscConfig+0x3aa>
- 80009d4:	e013      	b.n	80009fe <HAL_RCC_OscConfig+0x3f2>
+ 800135e:	4b98      	ldr	r3, [pc, #608]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001360:	6a1b      	ldr	r3, [r3, #32]
+ 8001362:	2202      	movs	r2, #2
+ 8001364:	4013      	ands	r3, r2
+ 8001366:	d0f0      	beq.n	800134a <HAL_RCC_OscConfig+0x3aa>
+ 8001368:	e013      	b.n	8001392 <HAL_RCC_OscConfig+0x3f2>
       }
     }
     else
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 80009d6:	f7ff fd5b 	bl	8000490 <HAL_GetTick>
- 80009da:	0003      	movs	r3, r0
- 80009dc:	61bb      	str	r3, [r7, #24]
+ 800136a:	f7ff f997 	bl	800069c <HAL_GetTick>
+ 800136e:	0003      	movs	r3, r0
+ 8001370:	61bb      	str	r3, [r7, #24]
       
       /* Wait till LSE is disabled */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80009de:	e009      	b.n	80009f4 <HAL_RCC_OscConfig+0x3e8>
+ 8001372:	e009      	b.n	8001388 <HAL_RCC_OscConfig+0x3e8>
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80009e0:	f7ff fd56 	bl	8000490 <HAL_GetTick>
- 80009e4:	0002      	movs	r2, r0
- 80009e6:	69bb      	ldr	r3, [r7, #24]
- 80009e8:	1ad3      	subs	r3, r2, r3
- 80009ea:	4a91      	ldr	r2, [pc, #580]	; (8000c30 <HAL_RCC_OscConfig+0x624>)
- 80009ec:	4293      	cmp	r3, r2
- 80009ee:	d901      	bls.n	80009f4 <HAL_RCC_OscConfig+0x3e8>
+ 8001374:	f7ff f992 	bl	800069c <HAL_GetTick>
+ 8001378:	0002      	movs	r2, r0
+ 800137a:	69bb      	ldr	r3, [r7, #24]
+ 800137c:	1ad3      	subs	r3, r2, r3
+ 800137e:	4a91      	ldr	r2, [pc, #580]	; (80015c4 <HAL_RCC_OscConfig+0x624>)
+ 8001380:	4293      	cmp	r3, r2
+ 8001382:	d901      	bls.n	8001388 <HAL_RCC_OscConfig+0x3e8>
         {
           return HAL_TIMEOUT;
- 80009f0:	2303      	movs	r3, #3
- 80009f2:	e116      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001384:	2303      	movs	r3, #3
+ 8001386:	e116      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80009f4:	4b8d      	ldr	r3, [pc, #564]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 80009f6:	6a1b      	ldr	r3, [r3, #32]
- 80009f8:	2202      	movs	r2, #2
- 80009fa:	4013      	ands	r3, r2
- 80009fc:	d1f0      	bne.n	80009e0 <HAL_RCC_OscConfig+0x3d4>
+ 8001388:	4b8d      	ldr	r3, [pc, #564]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800138a:	6a1b      	ldr	r3, [r3, #32]
+ 800138c:	2202      	movs	r2, #2
+ 800138e:	4013      	ands	r3, r2
+ 8001390:	d1f0      	bne.n	8001374 <HAL_RCC_OscConfig+0x3d4>
         }
       }
     }
 
     /* Require to disable power clock if necessary */
     if(pwrclkchanged == SET)
- 80009fe:	231f      	movs	r3, #31
- 8000a00:	18fb      	adds	r3, r7, r3
- 8000a02:	781b      	ldrb	r3, [r3, #0]
- 8000a04:	2b01      	cmp	r3, #1
- 8000a06:	d105      	bne.n	8000a14 <HAL_RCC_OscConfig+0x408>
+ 8001392:	231f      	movs	r3, #31
+ 8001394:	18fb      	adds	r3, r7, r3
+ 8001396:	781b      	ldrb	r3, [r3, #0]
+ 8001398:	2b01      	cmp	r3, #1
+ 800139a:	d105      	bne.n	80013a8 <HAL_RCC_OscConfig+0x408>
     {
       __HAL_RCC_PWR_CLK_DISABLE();
- 8000a08:	4b88      	ldr	r3, [pc, #544]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a0a:	69da      	ldr	r2, [r3, #28]
- 8000a0c:	4b87      	ldr	r3, [pc, #540]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a0e:	4989      	ldr	r1, [pc, #548]	; (8000c34 <HAL_RCC_OscConfig+0x628>)
- 8000a10:	400a      	ands	r2, r1
- 8000a12:	61da      	str	r2, [r3, #28]
+ 800139c:	4b88      	ldr	r3, [pc, #544]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800139e:	69da      	ldr	r2, [r3, #28]
+ 80013a0:	4b87      	ldr	r3, [pc, #540]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013a2:	4989      	ldr	r1, [pc, #548]	; (80015c8 <HAL_RCC_OscConfig+0x628>)
+ 80013a4:	400a      	ands	r2, r1
+ 80013a6:	61da      	str	r2, [r3, #28]
     }
   }
 
   /*----------------------------- HSI14 Configuration --------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
- 8000a14:	687b      	ldr	r3, [r7, #4]
- 8000a16:	681b      	ldr	r3, [r3, #0]
- 8000a18:	2210      	movs	r2, #16
- 8000a1a:	4013      	ands	r3, r2
- 8000a1c:	d063      	beq.n	8000ae6 <HAL_RCC_OscConfig+0x4da>
+ 80013a8:	687b      	ldr	r3, [r7, #4]
+ 80013aa:	681b      	ldr	r3, [r3, #0]
+ 80013ac:	2210      	movs	r2, #16
+ 80013ae:	4013      	ands	r3, r2
+ 80013b0:	d063      	beq.n	800147a <HAL_RCC_OscConfig+0x4da>
     /* Check the parameters */
     assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
 
     /* Check the HSI14 State */
     if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
- 8000a1e:	687b      	ldr	r3, [r7, #4]
- 8000a20:	695b      	ldr	r3, [r3, #20]
- 8000a22:	2b01      	cmp	r3, #1
- 8000a24:	d12a      	bne.n	8000a7c <HAL_RCC_OscConfig+0x470>
+ 80013b2:	687b      	ldr	r3, [r7, #4]
+ 80013b4:	695b      	ldr	r3, [r3, #20]
+ 80013b6:	2b01      	cmp	r3, #1
+ 80013b8:	d12a      	bne.n	8001410 <HAL_RCC_OscConfig+0x470>
     {
       /* Disable ADC control of the Internal High Speed oscillator HSI14 */
       __HAL_RCC_HSI14ADC_DISABLE();
- 8000a26:	4b81      	ldr	r3, [pc, #516]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a28:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8000a2a:	4b80      	ldr	r3, [pc, #512]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a2c:	2104      	movs	r1, #4
- 8000a2e:	430a      	orrs	r2, r1
- 8000a30:	635a      	str	r2, [r3, #52]	; 0x34
+ 80013ba:	4b81      	ldr	r3, [pc, #516]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013bc:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 80013be:	4b80      	ldr	r3, [pc, #512]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013c0:	2104      	movs	r1, #4
+ 80013c2:	430a      	orrs	r2, r1
+ 80013c4:	635a      	str	r2, [r3, #52]	; 0x34
 
       /* Enable the Internal High Speed oscillator (HSI). */
       __HAL_RCC_HSI14_ENABLE();
- 8000a32:	4b7e      	ldr	r3, [pc, #504]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a34:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8000a36:	4b7d      	ldr	r3, [pc, #500]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a38:	2101      	movs	r1, #1
- 8000a3a:	430a      	orrs	r2, r1
- 8000a3c:	635a      	str	r2, [r3, #52]	; 0x34
+ 80013c6:	4b7e      	ldr	r3, [pc, #504]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013c8:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 80013ca:	4b7d      	ldr	r3, [pc, #500]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013cc:	2101      	movs	r1, #1
+ 80013ce:	430a      	orrs	r2, r1
+ 80013d0:	635a      	str	r2, [r3, #52]	; 0x34
 
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8000a3e:	f7ff fd27 	bl	8000490 <HAL_GetTick>
- 8000a42:	0003      	movs	r3, r0
- 8000a44:	61bb      	str	r3, [r7, #24]
+ 80013d2:	f7ff f963 	bl	800069c <HAL_GetTick>
+ 80013d6:	0003      	movs	r3, r0
+ 80013d8:	61bb      	str	r3, [r7, #24]
       
       /* Wait till HSI is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
- 8000a46:	e008      	b.n	8000a5a <HAL_RCC_OscConfig+0x44e>
+ 80013da:	e008      	b.n	80013ee <HAL_RCC_OscConfig+0x44e>
       {
         if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
- 8000a48:	f7ff fd22 	bl	8000490 <HAL_GetTick>
- 8000a4c:	0002      	movs	r2, r0
- 8000a4e:	69bb      	ldr	r3, [r7, #24]
- 8000a50:	1ad3      	subs	r3, r2, r3
- 8000a52:	2b02      	cmp	r3, #2
- 8000a54:	d901      	bls.n	8000a5a <HAL_RCC_OscConfig+0x44e>
+ 80013dc:	f7ff f95e 	bl	800069c <HAL_GetTick>
+ 80013e0:	0002      	movs	r2, r0
+ 80013e2:	69bb      	ldr	r3, [r7, #24]
+ 80013e4:	1ad3      	subs	r3, r2, r3
+ 80013e6:	2b02      	cmp	r3, #2
+ 80013e8:	d901      	bls.n	80013ee <HAL_RCC_OscConfig+0x44e>
         {
           return HAL_TIMEOUT;
- 8000a56:	2303      	movs	r3, #3
- 8000a58:	e0e3      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80013ea:	2303      	movs	r3, #3
+ 80013ec:	e0e3      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
- 8000a5a:	4b74      	ldr	r3, [pc, #464]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a5c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8000a5e:	2202      	movs	r2, #2
- 8000a60:	4013      	ands	r3, r2
- 8000a62:	d0f1      	beq.n	8000a48 <HAL_RCC_OscConfig+0x43c>
+ 80013ee:	4b74      	ldr	r3, [pc, #464]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013f0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 80013f2:	2202      	movs	r2, #2
+ 80013f4:	4013      	ands	r3, r2
+ 80013f6:	d0f1      	beq.n	80013dc <HAL_RCC_OscConfig+0x43c>
         }      
       } 
 
       /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
       __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
- 8000a64:	4b71      	ldr	r3, [pc, #452]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a66:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8000a68:	22f8      	movs	r2, #248	; 0xf8
- 8000a6a:	4393      	bics	r3, r2
- 8000a6c:	0019      	movs	r1, r3
- 8000a6e:	687b      	ldr	r3, [r7, #4]
- 8000a70:	699b      	ldr	r3, [r3, #24]
- 8000a72:	00da      	lsls	r2, r3, #3
- 8000a74:	4b6d      	ldr	r3, [pc, #436]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a76:	430a      	orrs	r2, r1
- 8000a78:	635a      	str	r2, [r3, #52]	; 0x34
- 8000a7a:	e034      	b.n	8000ae6 <HAL_RCC_OscConfig+0x4da>
+ 80013f8:	4b71      	ldr	r3, [pc, #452]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80013fa:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 80013fc:	22f8      	movs	r2, #248	; 0xf8
+ 80013fe:	4393      	bics	r3, r2
+ 8001400:	0019      	movs	r1, r3
+ 8001402:	687b      	ldr	r3, [r7, #4]
+ 8001404:	699b      	ldr	r3, [r3, #24]
+ 8001406:	00da      	lsls	r2, r3, #3
+ 8001408:	4b6d      	ldr	r3, [pc, #436]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800140a:	430a      	orrs	r2, r1
+ 800140c:	635a      	str	r2, [r3, #52]	; 0x34
+ 800140e:	e034      	b.n	800147a <HAL_RCC_OscConfig+0x4da>
     }
     else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
- 8000a7c:	687b      	ldr	r3, [r7, #4]
- 8000a7e:	695b      	ldr	r3, [r3, #20]
- 8000a80:	3305      	adds	r3, #5
- 8000a82:	d111      	bne.n	8000aa8 <HAL_RCC_OscConfig+0x49c>
+ 8001410:	687b      	ldr	r3, [r7, #4]
+ 8001412:	695b      	ldr	r3, [r3, #20]
+ 8001414:	3305      	adds	r3, #5
+ 8001416:	d111      	bne.n	800143c <HAL_RCC_OscConfig+0x49c>
     {
       /* Enable ADC control of the Internal High Speed oscillator HSI14 */
       __HAL_RCC_HSI14ADC_ENABLE();
- 8000a84:	4b69      	ldr	r3, [pc, #420]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a86:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8000a88:	4b68      	ldr	r3, [pc, #416]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a8a:	2104      	movs	r1, #4
- 8000a8c:	438a      	bics	r2, r1
- 8000a8e:	635a      	str	r2, [r3, #52]	; 0x34
+ 8001418:	4b69      	ldr	r3, [pc, #420]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800141a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800141c:	4b68      	ldr	r3, [pc, #416]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800141e:	2104      	movs	r1, #4
+ 8001420:	438a      	bics	r2, r1
+ 8001422:	635a      	str	r2, [r3, #52]	; 0x34
 
       /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
       __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
- 8000a90:	4b66      	ldr	r3, [pc, #408]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000a92:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8000a94:	22f8      	movs	r2, #248	; 0xf8
- 8000a96:	4393      	bics	r3, r2
- 8000a98:	0019      	movs	r1, r3
- 8000a9a:	687b      	ldr	r3, [r7, #4]
- 8000a9c:	699b      	ldr	r3, [r3, #24]
- 8000a9e:	00da      	lsls	r2, r3, #3
- 8000aa0:	4b62      	ldr	r3, [pc, #392]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000aa2:	430a      	orrs	r2, r1
- 8000aa4:	635a      	str	r2, [r3, #52]	; 0x34
- 8000aa6:	e01e      	b.n	8000ae6 <HAL_RCC_OscConfig+0x4da>
+ 8001424:	4b66      	ldr	r3, [pc, #408]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001426:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8001428:	22f8      	movs	r2, #248	; 0xf8
+ 800142a:	4393      	bics	r3, r2
+ 800142c:	0019      	movs	r1, r3
+ 800142e:	687b      	ldr	r3, [r7, #4]
+ 8001430:	699b      	ldr	r3, [r3, #24]
+ 8001432:	00da      	lsls	r2, r3, #3
+ 8001434:	4b62      	ldr	r3, [pc, #392]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001436:	430a      	orrs	r2, r1
+ 8001438:	635a      	str	r2, [r3, #52]	; 0x34
+ 800143a:	e01e      	b.n	800147a <HAL_RCC_OscConfig+0x4da>
     }
     else
     {
       /* Disable ADC control of the Internal High Speed oscillator HSI14 */
       __HAL_RCC_HSI14ADC_DISABLE();
- 8000aa8:	4b60      	ldr	r3, [pc, #384]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000aaa:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8000aac:	4b5f      	ldr	r3, [pc, #380]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000aae:	2104      	movs	r1, #4
- 8000ab0:	430a      	orrs	r2, r1
- 8000ab2:	635a      	str	r2, [r3, #52]	; 0x34
+ 800143c:	4b60      	ldr	r3, [pc, #384]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800143e:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8001440:	4b5f      	ldr	r3, [pc, #380]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001442:	2104      	movs	r1, #4
+ 8001444:	430a      	orrs	r2, r1
+ 8001446:	635a      	str	r2, [r3, #52]	; 0x34
 
       /* Disable the Internal High Speed oscillator (HSI). */
       __HAL_RCC_HSI14_DISABLE();
- 8000ab4:	4b5d      	ldr	r3, [pc, #372]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000ab6:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8000ab8:	4b5c      	ldr	r3, [pc, #368]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000aba:	2101      	movs	r1, #1
- 8000abc:	438a      	bics	r2, r1
- 8000abe:	635a      	str	r2, [r3, #52]	; 0x34
+ 8001448:	4b5d      	ldr	r3, [pc, #372]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800144a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 800144c:	4b5c      	ldr	r3, [pc, #368]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800144e:	2101      	movs	r1, #1
+ 8001450:	438a      	bics	r2, r1
+ 8001452:	635a      	str	r2, [r3, #52]	; 0x34
 
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8000ac0:	f7ff fce6 	bl	8000490 <HAL_GetTick>
- 8000ac4:	0003      	movs	r3, r0
- 8000ac6:	61bb      	str	r3, [r7, #24]
+ 8001454:	f7ff f922 	bl	800069c <HAL_GetTick>
+ 8001458:	0003      	movs	r3, r0
+ 800145a:	61bb      	str	r3, [r7, #24]
       
       /* Wait till HSI is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
- 8000ac8:	e008      	b.n	8000adc <HAL_RCC_OscConfig+0x4d0>
+ 800145c:	e008      	b.n	8001470 <HAL_RCC_OscConfig+0x4d0>
       {
         if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
- 8000aca:	f7ff fce1 	bl	8000490 <HAL_GetTick>
- 8000ace:	0002      	movs	r2, r0
- 8000ad0:	69bb      	ldr	r3, [r7, #24]
- 8000ad2:	1ad3      	subs	r3, r2, r3
- 8000ad4:	2b02      	cmp	r3, #2
- 8000ad6:	d901      	bls.n	8000adc <HAL_RCC_OscConfig+0x4d0>
+ 800145e:	f7ff f91d 	bl	800069c <HAL_GetTick>
+ 8001462:	0002      	movs	r2, r0
+ 8001464:	69bb      	ldr	r3, [r7, #24]
+ 8001466:	1ad3      	subs	r3, r2, r3
+ 8001468:	2b02      	cmp	r3, #2
+ 800146a:	d901      	bls.n	8001470 <HAL_RCC_OscConfig+0x4d0>
         {
           return HAL_TIMEOUT;
- 8000ad8:	2303      	movs	r3, #3
- 8000ada:	e0a2      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 800146c:	2303      	movs	r3, #3
+ 800146e:	e0a2      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
- 8000adc:	4b53      	ldr	r3, [pc, #332]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000ade:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8000ae0:	2202      	movs	r2, #2
- 8000ae2:	4013      	ands	r3, r2
- 8000ae4:	d1f1      	bne.n	8000aca <HAL_RCC_OscConfig+0x4be>
+ 8001470:	4b53      	ldr	r3, [pc, #332]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001472:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8001474:	2202      	movs	r2, #2
+ 8001476:	4013      	ands	r3, r2
+ 8001478:	d1f1      	bne.n	800145e <HAL_RCC_OscConfig+0x4be>
 #endif /* RCC_HSI48_SUPPORT */
        
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Check the parameters */
   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8000ae6:	687b      	ldr	r3, [r7, #4]
- 8000ae8:	6a1b      	ldr	r3, [r3, #32]
- 8000aea:	2b00      	cmp	r3, #0
- 8000aec:	d100      	bne.n	8000af0 <HAL_RCC_OscConfig+0x4e4>
- 8000aee:	e097      	b.n	8000c20 <HAL_RCC_OscConfig+0x614>
+ 800147a:	687b      	ldr	r3, [r7, #4]
+ 800147c:	6a1b      	ldr	r3, [r3, #32]
+ 800147e:	2b00      	cmp	r3, #0
+ 8001480:	d100      	bne.n	8001484 <HAL_RCC_OscConfig+0x4e4>
+ 8001482:	e097      	b.n	80015b4 <HAL_RCC_OscConfig+0x614>
   {
     /* Check if the PLL is used as system clock or not */
     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8000af0:	4b4e      	ldr	r3, [pc, #312]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000af2:	685b      	ldr	r3, [r3, #4]
- 8000af4:	220c      	movs	r2, #12
- 8000af6:	4013      	ands	r3, r2
- 8000af8:	2b08      	cmp	r3, #8
- 8000afa:	d100      	bne.n	8000afe <HAL_RCC_OscConfig+0x4f2>
- 8000afc:	e06b      	b.n	8000bd6 <HAL_RCC_OscConfig+0x5ca>
+ 8001484:	4b4e      	ldr	r3, [pc, #312]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001486:	685b      	ldr	r3, [r3, #4]
+ 8001488:	220c      	movs	r2, #12
+ 800148a:	4013      	ands	r3, r2
+ 800148c:	2b08      	cmp	r3, #8
+ 800148e:	d100      	bne.n	8001492 <HAL_RCC_OscConfig+0x4f2>
+ 8001490:	e06b      	b.n	800156a <HAL_RCC_OscConfig+0x5ca>
     { 
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8000afe:	687b      	ldr	r3, [r7, #4]
- 8000b00:	6a1b      	ldr	r3, [r3, #32]
- 8000b02:	2b02      	cmp	r3, #2
- 8000b04:	d14c      	bne.n	8000ba0 <HAL_RCC_OscConfig+0x594>
+ 8001492:	687b      	ldr	r3, [r7, #4]
+ 8001494:	6a1b      	ldr	r3, [r3, #32]
+ 8001496:	2b02      	cmp	r3, #2
+ 8001498:	d14c      	bne.n	8001534 <HAL_RCC_OscConfig+0x594>
         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
         assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
   
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 8000b06:	4b49      	ldr	r3, [pc, #292]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b08:	681a      	ldr	r2, [r3, #0]
- 8000b0a:	4b48      	ldr	r3, [pc, #288]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b0c:	494a      	ldr	r1, [pc, #296]	; (8000c38 <HAL_RCC_OscConfig+0x62c>)
- 8000b0e:	400a      	ands	r2, r1
- 8000b10:	601a      	str	r2, [r3, #0]
+ 800149a:	4b49      	ldr	r3, [pc, #292]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800149c:	681a      	ldr	r2, [r3, #0]
+ 800149e:	4b48      	ldr	r3, [pc, #288]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014a0:	494a      	ldr	r1, [pc, #296]	; (80015cc <HAL_RCC_OscConfig+0x62c>)
+ 80014a2:	400a      	ands	r2, r1
+ 80014a4:	601a      	str	r2, [r3, #0]
         
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8000b12:	f7ff fcbd 	bl	8000490 <HAL_GetTick>
- 8000b16:	0003      	movs	r3, r0
- 8000b18:	61bb      	str	r3, [r7, #24]
+ 80014a6:	f7ff f8f9 	bl	800069c <HAL_GetTick>
+ 80014aa:	0003      	movs	r3, r0
+ 80014ac:	61bb      	str	r3, [r7, #24]
         
         /* Wait till PLL is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8000b1a:	e008      	b.n	8000b2e <HAL_RCC_OscConfig+0x522>
+ 80014ae:	e008      	b.n	80014c2 <HAL_RCC_OscConfig+0x522>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8000b1c:	f7ff fcb8 	bl	8000490 <HAL_GetTick>
- 8000b20:	0002      	movs	r2, r0
- 8000b22:	69bb      	ldr	r3, [r7, #24]
- 8000b24:	1ad3      	subs	r3, r2, r3
- 8000b26:	2b02      	cmp	r3, #2
- 8000b28:	d901      	bls.n	8000b2e <HAL_RCC_OscConfig+0x522>
+ 80014b0:	f7ff f8f4 	bl	800069c <HAL_GetTick>
+ 80014b4:	0002      	movs	r2, r0
+ 80014b6:	69bb      	ldr	r3, [r7, #24]
+ 80014b8:	1ad3      	subs	r3, r2, r3
+ 80014ba:	2b02      	cmp	r3, #2
+ 80014bc:	d901      	bls.n	80014c2 <HAL_RCC_OscConfig+0x522>
           {
             return HAL_TIMEOUT;
- 8000b2a:	2303      	movs	r3, #3
- 8000b2c:	e079      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80014be:	2303      	movs	r3, #3
+ 80014c0:	e079      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8000b2e:	4b3f      	ldr	r3, [pc, #252]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b30:	681a      	ldr	r2, [r3, #0]
- 8000b32:	2380      	movs	r3, #128	; 0x80
- 8000b34:	049b      	lsls	r3, r3, #18
- 8000b36:	4013      	ands	r3, r2
- 8000b38:	d1f0      	bne.n	8000b1c <HAL_RCC_OscConfig+0x510>
+ 80014c2:	4b3f      	ldr	r3, [pc, #252]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014c4:	681a      	ldr	r2, [r3, #0]
+ 80014c6:	2380      	movs	r3, #128	; 0x80
+ 80014c8:	049b      	lsls	r3, r3, #18
+ 80014ca:	4013      	ands	r3, r2
+ 80014cc:	d1f0      	bne.n	80014b0 <HAL_RCC_OscConfig+0x510>
           }
         }
 
         /* Configure the main PLL clock source, predivider and multiplication factor. */
         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8000b3a:	4b3c      	ldr	r3, [pc, #240]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b3c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8000b3e:	220f      	movs	r2, #15
- 8000b40:	4393      	bics	r3, r2
- 8000b42:	0019      	movs	r1, r3
- 8000b44:	687b      	ldr	r3, [r7, #4]
- 8000b46:	6ada      	ldr	r2, [r3, #44]	; 0x2c
- 8000b48:	4b38      	ldr	r3, [pc, #224]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b4a:	430a      	orrs	r2, r1
- 8000b4c:	62da      	str	r2, [r3, #44]	; 0x2c
- 8000b4e:	4b37      	ldr	r3, [pc, #220]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b50:	685b      	ldr	r3, [r3, #4]
- 8000b52:	4a3a      	ldr	r2, [pc, #232]	; (8000c3c <HAL_RCC_OscConfig+0x630>)
- 8000b54:	4013      	ands	r3, r2
- 8000b56:	0019      	movs	r1, r3
- 8000b58:	687b      	ldr	r3, [r7, #4]
- 8000b5a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
- 8000b5c:	687b      	ldr	r3, [r7, #4]
- 8000b5e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000b60:	431a      	orrs	r2, r3
- 8000b62:	4b32      	ldr	r3, [pc, #200]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b64:	430a      	orrs	r2, r1
- 8000b66:	605a      	str	r2, [r3, #4]
+ 80014ce:	4b3c      	ldr	r3, [pc, #240]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014d0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80014d2:	220f      	movs	r2, #15
+ 80014d4:	4393      	bics	r3, r2
+ 80014d6:	0019      	movs	r1, r3
+ 80014d8:	687b      	ldr	r3, [r7, #4]
+ 80014da:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 80014dc:	4b38      	ldr	r3, [pc, #224]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014de:	430a      	orrs	r2, r1
+ 80014e0:	62da      	str	r2, [r3, #44]	; 0x2c
+ 80014e2:	4b37      	ldr	r3, [pc, #220]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014e4:	685b      	ldr	r3, [r3, #4]
+ 80014e6:	4a3a      	ldr	r2, [pc, #232]	; (80015d0 <HAL_RCC_OscConfig+0x630>)
+ 80014e8:	4013      	ands	r3, r2
+ 80014ea:	0019      	movs	r1, r3
+ 80014ec:	687b      	ldr	r3, [r7, #4]
+ 80014ee:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 80014f0:	687b      	ldr	r3, [r7, #4]
+ 80014f2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80014f4:	431a      	orrs	r2, r3
+ 80014f6:	4b32      	ldr	r3, [pc, #200]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014f8:	430a      	orrs	r2, r1
+ 80014fa:	605a      	str	r2, [r3, #4]
                              RCC_OscInitStruct->PLL.PREDIV,
                              RCC_OscInitStruct->PLL.PLLMUL);
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
- 8000b68:	4b30      	ldr	r3, [pc, #192]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b6a:	681a      	ldr	r2, [r3, #0]
- 8000b6c:	4b2f      	ldr	r3, [pc, #188]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b6e:	2180      	movs	r1, #128	; 0x80
- 8000b70:	0449      	lsls	r1, r1, #17
- 8000b72:	430a      	orrs	r2, r1
- 8000b74:	601a      	str	r2, [r3, #0]
+ 80014fc:	4b30      	ldr	r3, [pc, #192]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 80014fe:	681a      	ldr	r2, [r3, #0]
+ 8001500:	4b2f      	ldr	r3, [pc, #188]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001502:	2180      	movs	r1, #128	; 0x80
+ 8001504:	0449      	lsls	r1, r1, #17
+ 8001506:	430a      	orrs	r2, r1
+ 8001508:	601a      	str	r2, [r3, #0]
         
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8000b76:	f7ff fc8b 	bl	8000490 <HAL_GetTick>
- 8000b7a:	0003      	movs	r3, r0
- 8000b7c:	61bb      	str	r3, [r7, #24]
+ 800150a:	f7ff f8c7 	bl	800069c <HAL_GetTick>
+ 800150e:	0003      	movs	r3, r0
+ 8001510:	61bb      	str	r3, [r7, #24]
         
         /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
- 8000b7e:	e008      	b.n	8000b92 <HAL_RCC_OscConfig+0x586>
+ 8001512:	e008      	b.n	8001526 <HAL_RCC_OscConfig+0x586>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8000b80:	f7ff fc86 	bl	8000490 <HAL_GetTick>
- 8000b84:	0002      	movs	r2, r0
- 8000b86:	69bb      	ldr	r3, [r7, #24]
- 8000b88:	1ad3      	subs	r3, r2, r3
- 8000b8a:	2b02      	cmp	r3, #2
- 8000b8c:	d901      	bls.n	8000b92 <HAL_RCC_OscConfig+0x586>
+ 8001514:	f7ff f8c2 	bl	800069c <HAL_GetTick>
+ 8001518:	0002      	movs	r2, r0
+ 800151a:	69bb      	ldr	r3, [r7, #24]
+ 800151c:	1ad3      	subs	r3, r2, r3
+ 800151e:	2b02      	cmp	r3, #2
+ 8001520:	d901      	bls.n	8001526 <HAL_RCC_OscConfig+0x586>
           {
             return HAL_TIMEOUT;
- 8000b8e:	2303      	movs	r3, #3
- 8000b90:	e047      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001522:	2303      	movs	r3, #3
+ 8001524:	e047      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
- 8000b92:	4b26      	ldr	r3, [pc, #152]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000b94:	681a      	ldr	r2, [r3, #0]
- 8000b96:	2380      	movs	r3, #128	; 0x80
- 8000b98:	049b      	lsls	r3, r3, #18
- 8000b9a:	4013      	ands	r3, r2
- 8000b9c:	d0f0      	beq.n	8000b80 <HAL_RCC_OscConfig+0x574>
- 8000b9e:	e03f      	b.n	8000c20 <HAL_RCC_OscConfig+0x614>
+ 8001526:	4b26      	ldr	r3, [pc, #152]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001528:	681a      	ldr	r2, [r3, #0]
+ 800152a:	2380      	movs	r3, #128	; 0x80
+ 800152c:	049b      	lsls	r3, r3, #18
+ 800152e:	4013      	ands	r3, r2
+ 8001530:	d0f0      	beq.n	8001514 <HAL_RCC_OscConfig+0x574>
+ 8001532:	e03f      	b.n	80015b4 <HAL_RCC_OscConfig+0x614>
         }
       }
       else
       {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 8000ba0:	4b22      	ldr	r3, [pc, #136]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000ba2:	681a      	ldr	r2, [r3, #0]
- 8000ba4:	4b21      	ldr	r3, [pc, #132]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000ba6:	4924      	ldr	r1, [pc, #144]	; (8000c38 <HAL_RCC_OscConfig+0x62c>)
- 8000ba8:	400a      	ands	r2, r1
- 8000baa:	601a      	str	r2, [r3, #0]
+ 8001534:	4b22      	ldr	r3, [pc, #136]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001536:	681a      	ldr	r2, [r3, #0]
+ 8001538:	4b21      	ldr	r3, [pc, #132]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800153a:	4924      	ldr	r1, [pc, #144]	; (80015cc <HAL_RCC_OscConfig+0x62c>)
+ 800153c:	400a      	ands	r2, r1
+ 800153e:	601a      	str	r2, [r3, #0]
  
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8000bac:	f7ff fc70 	bl	8000490 <HAL_GetTick>
- 8000bb0:	0003      	movs	r3, r0
- 8000bb2:	61bb      	str	r3, [r7, #24]
+ 8001540:	f7ff f8ac 	bl	800069c <HAL_GetTick>
+ 8001544:	0003      	movs	r3, r0
+ 8001546:	61bb      	str	r3, [r7, #24]
         
         /* Wait till PLL is disabled */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8000bb4:	e008      	b.n	8000bc8 <HAL_RCC_OscConfig+0x5bc>
+ 8001548:	e008      	b.n	800155c <HAL_RCC_OscConfig+0x5bc>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8000bb6:	f7ff fc6b 	bl	8000490 <HAL_GetTick>
- 8000bba:	0002      	movs	r2, r0
- 8000bbc:	69bb      	ldr	r3, [r7, #24]
- 8000bbe:	1ad3      	subs	r3, r2, r3
- 8000bc0:	2b02      	cmp	r3, #2
- 8000bc2:	d901      	bls.n	8000bc8 <HAL_RCC_OscConfig+0x5bc>
+ 800154a:	f7ff f8a7 	bl	800069c <HAL_GetTick>
+ 800154e:	0002      	movs	r2, r0
+ 8001550:	69bb      	ldr	r3, [r7, #24]
+ 8001552:	1ad3      	subs	r3, r2, r3
+ 8001554:	2b02      	cmp	r3, #2
+ 8001556:	d901      	bls.n	800155c <HAL_RCC_OscConfig+0x5bc>
           {
             return HAL_TIMEOUT;
- 8000bc4:	2303      	movs	r3, #3
- 8000bc6:	e02c      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001558:	2303      	movs	r3, #3
+ 800155a:	e02c      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
- 8000bc8:	4b18      	ldr	r3, [pc, #96]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000bca:	681a      	ldr	r2, [r3, #0]
- 8000bcc:	2380      	movs	r3, #128	; 0x80
- 8000bce:	049b      	lsls	r3, r3, #18
- 8000bd0:	4013      	ands	r3, r2
- 8000bd2:	d1f0      	bne.n	8000bb6 <HAL_RCC_OscConfig+0x5aa>
- 8000bd4:	e024      	b.n	8000c20 <HAL_RCC_OscConfig+0x614>
+ 800155c:	4b18      	ldr	r3, [pc, #96]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800155e:	681a      	ldr	r2, [r3, #0]
+ 8001560:	2380      	movs	r3, #128	; 0x80
+ 8001562:	049b      	lsls	r3, r3, #18
+ 8001564:	4013      	ands	r3, r2
+ 8001566:	d1f0      	bne.n	800154a <HAL_RCC_OscConfig+0x5aa>
+ 8001568:	e024      	b.n	80015b4 <HAL_RCC_OscConfig+0x614>
       }
     }
     else
     {
       /* Check if there is a request to disable the PLL used as System clock source */
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- 8000bd6:	687b      	ldr	r3, [r7, #4]
- 8000bd8:	6a1b      	ldr	r3, [r3, #32]
- 8000bda:	2b01      	cmp	r3, #1
- 8000bdc:	d101      	bne.n	8000be2 <HAL_RCC_OscConfig+0x5d6>
+ 800156a:	687b      	ldr	r3, [r7, #4]
+ 800156c:	6a1b      	ldr	r3, [r3, #32]
+ 800156e:	2b01      	cmp	r3, #1
+ 8001570:	d101      	bne.n	8001576 <HAL_RCC_OscConfig+0x5d6>
       {
         return HAL_ERROR;
- 8000bde:	2301      	movs	r3, #1
- 8000be0:	e01f      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 8001572:	2301      	movs	r3, #1
+ 8001574:	e01f      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
       }
       else
       {
         /* Do not return HAL_ERROR if request repeats the current configuration */
         pll_config  = RCC->CFGR;
- 8000be2:	4b12      	ldr	r3, [pc, #72]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000be4:	685b      	ldr	r3, [r3, #4]
- 8000be6:	617b      	str	r3, [r7, #20]
+ 8001576:	4b12      	ldr	r3, [pc, #72]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 8001578:	685b      	ldr	r3, [r3, #4]
+ 800157a:	617b      	str	r3, [r7, #20]
         pll_config2 = RCC->CFGR2;
- 8000be8:	4b10      	ldr	r3, [pc, #64]	; (8000c2c <HAL_RCC_OscConfig+0x620>)
- 8000bea:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8000bec:	613b      	str	r3, [r7, #16]
+ 800157c:	4b10      	ldr	r3, [pc, #64]	; (80015c0 <HAL_RCC_OscConfig+0x620>)
+ 800157e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8001580:	613b      	str	r3, [r7, #16]
         if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
- 8000bee:	697a      	ldr	r2, [r7, #20]
- 8000bf0:	2380      	movs	r3, #128	; 0x80
- 8000bf2:	025b      	lsls	r3, r3, #9
- 8000bf4:	401a      	ands	r2, r3
- 8000bf6:	687b      	ldr	r3, [r7, #4]
- 8000bf8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000bfa:	429a      	cmp	r2, r3
- 8000bfc:	d10e      	bne.n	8000c1c <HAL_RCC_OscConfig+0x610>
+ 8001582:	697a      	ldr	r2, [r7, #20]
+ 8001584:	2380      	movs	r3, #128	; 0x80
+ 8001586:	025b      	lsls	r3, r3, #9
+ 8001588:	401a      	ands	r2, r3
+ 800158a:	687b      	ldr	r3, [r7, #4]
+ 800158c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800158e:	429a      	cmp	r2, r3
+ 8001590:	d10e      	bne.n	80015b0 <HAL_RCC_OscConfig+0x610>
            (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
- 8000bfe:	693b      	ldr	r3, [r7, #16]
- 8000c00:	220f      	movs	r2, #15
- 8000c02:	401a      	ands	r2, r3
- 8000c04:	687b      	ldr	r3, [r7, #4]
- 8000c06:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8001592:	693b      	ldr	r3, [r7, #16]
+ 8001594:	220f      	movs	r2, #15
+ 8001596:	401a      	ands	r2, r3
+ 8001598:	687b      	ldr	r3, [r7, #4]
+ 800159a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
         if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
- 8000c08:	429a      	cmp	r2, r3
- 8000c0a:	d107      	bne.n	8000c1c <HAL_RCC_OscConfig+0x610>
+ 800159c:	429a      	cmp	r2, r3
+ 800159e:	d107      	bne.n	80015b0 <HAL_RCC_OscConfig+0x610>
            (READ_BIT(pll_config,  RCC_CFGR_PLLMUL)  != RCC_OscInitStruct->PLL.PLLMUL))
- 8000c0c:	697a      	ldr	r2, [r7, #20]
- 8000c0e:	23f0      	movs	r3, #240	; 0xf0
- 8000c10:	039b      	lsls	r3, r3, #14
- 8000c12:	401a      	ands	r2, r3
- 8000c14:	687b      	ldr	r3, [r7, #4]
- 8000c16:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 80015a0:	697a      	ldr	r2, [r7, #20]
+ 80015a2:	23f0      	movs	r3, #240	; 0xf0
+ 80015a4:	039b      	lsls	r3, r3, #14
+ 80015a6:	401a      	ands	r2, r3
+ 80015a8:	687b      	ldr	r3, [r7, #4]
+ 80015aa:	6a9b      	ldr	r3, [r3, #40]	; 0x28
            (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
- 8000c18:	429a      	cmp	r2, r3
- 8000c1a:	d001      	beq.n	8000c20 <HAL_RCC_OscConfig+0x614>
+ 80015ac:	429a      	cmp	r2, r3
+ 80015ae:	d001      	beq.n	80015b4 <HAL_RCC_OscConfig+0x614>
         {
           return HAL_ERROR;
- 8000c1c:	2301      	movs	r3, #1
- 8000c1e:	e000      	b.n	8000c22 <HAL_RCC_OscConfig+0x616>
+ 80015b0:	2301      	movs	r3, #1
+ 80015b2:	e000      	b.n	80015b6 <HAL_RCC_OscConfig+0x616>
         }
       }
     }
   }
 
   return HAL_OK;
- 8000c20:	2300      	movs	r3, #0
+ 80015b4:	2300      	movs	r3, #0
 }
- 8000c22:	0018      	movs	r0, r3
- 8000c24:	46bd      	mov	sp, r7
- 8000c26:	b008      	add	sp, #32
- 8000c28:	bd80      	pop	{r7, pc}
- 8000c2a:	46c0      	nop			; (mov r8, r8)
- 8000c2c:	40021000 	.word	0x40021000
- 8000c30:	00001388 	.word	0x00001388
- 8000c34:	efffffff 	.word	0xefffffff
- 8000c38:	feffffff 	.word	0xfeffffff
- 8000c3c:	ffc2ffff 	.word	0xffc2ffff
+ 80015b6:	0018      	movs	r0, r3
+ 80015b8:	46bd      	mov	sp, r7
+ 80015ba:	b008      	add	sp, #32
+ 80015bc:	bd80      	pop	{r7, pc}
+ 80015be:	46c0      	nop			; (mov r8, r8)
+ 80015c0:	40021000 	.word	0x40021000
+ 80015c4:	00001388 	.word	0x00001388
+ 80015c8:	efffffff 	.word	0xefffffff
+ 80015cc:	feffffff 	.word	0xfeffffff
+ 80015d0:	ffc2ffff 	.word	0xffc2ffff
 
-08000c40 <HAL_RCC_ClockConfig>:
+080015d4 <HAL_RCC_ClockConfig>:
   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
   *         currently used as system clock source.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 {
- 8000c40:	b580      	push	{r7, lr}
- 8000c42:	b084      	sub	sp, #16
- 8000c44:	af00      	add	r7, sp, #0
- 8000c46:	6078      	str	r0, [r7, #4]
- 8000c48:	6039      	str	r1, [r7, #0]
+ 80015d4:	b580      	push	{r7, lr}
+ 80015d6:	b084      	sub	sp, #16
+ 80015d8:	af00      	add	r7, sp, #0
+ 80015da:	6078      	str	r0, [r7, #4]
+ 80015dc:	6039      	str	r1, [r7, #0]
   uint32_t tickstart;
 
   /* Check Null pointer */
   if(RCC_ClkInitStruct == NULL)
- 8000c4a:	687b      	ldr	r3, [r7, #4]
- 8000c4c:	2b00      	cmp	r3, #0
- 8000c4e:	d101      	bne.n	8000c54 <HAL_RCC_ClockConfig+0x14>
+ 80015de:	687b      	ldr	r3, [r7, #4]
+ 80015e0:	2b00      	cmp	r3, #0
+ 80015e2:	d101      	bne.n	80015e8 <HAL_RCC_ClockConfig+0x14>
   {
     return HAL_ERROR;
- 8000c50:	2301      	movs	r3, #1
- 8000c52:	e0b3      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 80015e4:	2301      	movs	r3, #1
+ 80015e6:	e0b3      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
   /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
   must be correctly programmed according to the frequency of the CPU clock 
     (HCLK) of the device. */
 
   /* Increasing the number of wait states because of higher CPU frequency */
   if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8000c54:	4b5b      	ldr	r3, [pc, #364]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000c56:	681b      	ldr	r3, [r3, #0]
- 8000c58:	2201      	movs	r2, #1
- 8000c5a:	4013      	ands	r3, r2
- 8000c5c:	683a      	ldr	r2, [r7, #0]
- 8000c5e:	429a      	cmp	r2, r3
- 8000c60:	d911      	bls.n	8000c86 <HAL_RCC_ClockConfig+0x46>
+ 80015e8:	4b5b      	ldr	r3, [pc, #364]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 80015ea:	681b      	ldr	r3, [r3, #0]
+ 80015ec:	2201      	movs	r2, #1
+ 80015ee:	4013      	ands	r3, r2
+ 80015f0:	683a      	ldr	r2, [r7, #0]
+ 80015f2:	429a      	cmp	r2, r3
+ 80015f4:	d911      	bls.n	800161a <HAL_RCC_ClockConfig+0x46>
   {    
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8000c62:	4b58      	ldr	r3, [pc, #352]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000c64:	681b      	ldr	r3, [r3, #0]
- 8000c66:	2201      	movs	r2, #1
- 8000c68:	4393      	bics	r3, r2
- 8000c6a:	0019      	movs	r1, r3
- 8000c6c:	4b55      	ldr	r3, [pc, #340]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000c6e:	683a      	ldr	r2, [r7, #0]
- 8000c70:	430a      	orrs	r2, r1
- 8000c72:	601a      	str	r2, [r3, #0]
+ 80015f6:	4b58      	ldr	r3, [pc, #352]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 80015f8:	681b      	ldr	r3, [r3, #0]
+ 80015fa:	2201      	movs	r2, #1
+ 80015fc:	4393      	bics	r3, r2
+ 80015fe:	0019      	movs	r1, r3
+ 8001600:	4b55      	ldr	r3, [pc, #340]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 8001602:	683a      	ldr	r2, [r7, #0]
+ 8001604:	430a      	orrs	r2, r1
+ 8001606:	601a      	str	r2, [r3, #0]
     
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8000c74:	4b53      	ldr	r3, [pc, #332]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000c76:	681b      	ldr	r3, [r3, #0]
- 8000c78:	2201      	movs	r2, #1
- 8000c7a:	4013      	ands	r3, r2
- 8000c7c:	683a      	ldr	r2, [r7, #0]
- 8000c7e:	429a      	cmp	r2, r3
- 8000c80:	d001      	beq.n	8000c86 <HAL_RCC_ClockConfig+0x46>
+ 8001608:	4b53      	ldr	r3, [pc, #332]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 800160a:	681b      	ldr	r3, [r3, #0]
+ 800160c:	2201      	movs	r2, #1
+ 800160e:	4013      	ands	r3, r2
+ 8001610:	683a      	ldr	r2, [r7, #0]
+ 8001612:	429a      	cmp	r2, r3
+ 8001614:	d001      	beq.n	800161a <HAL_RCC_ClockConfig+0x46>
     {
       return HAL_ERROR;
- 8000c82:	2301      	movs	r3, #1
- 8000c84:	e09a      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 8001616:	2301      	movs	r3, #1
+ 8001618:	e09a      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
     }
   }
 
   /*-------------------------- HCLK Configuration --------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8000c86:	687b      	ldr	r3, [r7, #4]
- 8000c88:	681b      	ldr	r3, [r3, #0]
- 8000c8a:	2202      	movs	r2, #2
- 8000c8c:	4013      	ands	r3, r2
- 8000c8e:	d015      	beq.n	8000cbc <HAL_RCC_ClockConfig+0x7c>
+ 800161a:	687b      	ldr	r3, [r7, #4]
+ 800161c:	681b      	ldr	r3, [r3, #0]
+ 800161e:	2202      	movs	r2, #2
+ 8001620:	4013      	ands	r3, r2
+ 8001622:	d015      	beq.n	8001650 <HAL_RCC_ClockConfig+0x7c>
   {
     /* Set the highest APB divider in order to ensure that we do not go through
        a non-spec phase whatever we decrease or increase HCLK. */
     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8000c90:	687b      	ldr	r3, [r7, #4]
- 8000c92:	681b      	ldr	r3, [r3, #0]
- 8000c94:	2204      	movs	r2, #4
- 8000c96:	4013      	ands	r3, r2
- 8000c98:	d006      	beq.n	8000ca8 <HAL_RCC_ClockConfig+0x68>
+ 8001624:	687b      	ldr	r3, [r7, #4]
+ 8001626:	681b      	ldr	r3, [r3, #0]
+ 8001628:	2204      	movs	r2, #4
+ 800162a:	4013      	ands	r3, r2
+ 800162c:	d006      	beq.n	800163c <HAL_RCC_ClockConfig+0x68>
     {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
- 8000c9a:	4b4b      	ldr	r3, [pc, #300]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000c9c:	685a      	ldr	r2, [r3, #4]
- 8000c9e:	4b4a      	ldr	r3, [pc, #296]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000ca0:	21e0      	movs	r1, #224	; 0xe0
- 8000ca2:	00c9      	lsls	r1, r1, #3
- 8000ca4:	430a      	orrs	r2, r1
- 8000ca6:	605a      	str	r2, [r3, #4]
+ 800162e:	4b4b      	ldr	r3, [pc, #300]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 8001630:	685a      	ldr	r2, [r3, #4]
+ 8001632:	4b4a      	ldr	r3, [pc, #296]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 8001634:	21e0      	movs	r1, #224	; 0xe0
+ 8001636:	00c9      	lsls	r1, r1, #3
+ 8001638:	430a      	orrs	r2, r1
+ 800163a:	605a      	str	r2, [r3, #4]
     }
 
     /* Set the new HCLK clock divider */
     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8000ca8:	4b47      	ldr	r3, [pc, #284]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000caa:	685b      	ldr	r3, [r3, #4]
- 8000cac:	22f0      	movs	r2, #240	; 0xf0
- 8000cae:	4393      	bics	r3, r2
- 8000cb0:	0019      	movs	r1, r3
- 8000cb2:	687b      	ldr	r3, [r7, #4]
- 8000cb4:	689a      	ldr	r2, [r3, #8]
- 8000cb6:	4b44      	ldr	r3, [pc, #272]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000cb8:	430a      	orrs	r2, r1
- 8000cba:	605a      	str	r2, [r3, #4]
+ 800163c:	4b47      	ldr	r3, [pc, #284]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 800163e:	685b      	ldr	r3, [r3, #4]
+ 8001640:	22f0      	movs	r2, #240	; 0xf0
+ 8001642:	4393      	bics	r3, r2
+ 8001644:	0019      	movs	r1, r3
+ 8001646:	687b      	ldr	r3, [r7, #4]
+ 8001648:	689a      	ldr	r2, [r3, #8]
+ 800164a:	4b44      	ldr	r3, [pc, #272]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 800164c:	430a      	orrs	r2, r1
+ 800164e:	605a      	str	r2, [r3, #4]
   }
 
   /*------------------------- SYSCLK Configuration ---------------------------*/ 
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8000cbc:	687b      	ldr	r3, [r7, #4]
- 8000cbe:	681b      	ldr	r3, [r3, #0]
- 8000cc0:	2201      	movs	r2, #1
- 8000cc2:	4013      	ands	r3, r2
- 8000cc4:	d040      	beq.n	8000d48 <HAL_RCC_ClockConfig+0x108>
+ 8001650:	687b      	ldr	r3, [r7, #4]
+ 8001652:	681b      	ldr	r3, [r3, #0]
+ 8001654:	2201      	movs	r2, #1
+ 8001656:	4013      	ands	r3, r2
+ 8001658:	d040      	beq.n	80016dc <HAL_RCC_ClockConfig+0x108>
   {
     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
     
     /* HSE is selected as System Clock Source */
     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8000cc6:	687b      	ldr	r3, [r7, #4]
- 8000cc8:	685b      	ldr	r3, [r3, #4]
- 8000cca:	2b01      	cmp	r3, #1
- 8000ccc:	d107      	bne.n	8000cde <HAL_RCC_ClockConfig+0x9e>
+ 800165a:	687b      	ldr	r3, [r7, #4]
+ 800165c:	685b      	ldr	r3, [r3, #4]
+ 800165e:	2b01      	cmp	r3, #1
+ 8001660:	d107      	bne.n	8001672 <HAL_RCC_ClockConfig+0x9e>
     {
       /* Check the HSE ready flag */  
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8000cce:	4b3e      	ldr	r3, [pc, #248]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000cd0:	681a      	ldr	r2, [r3, #0]
- 8000cd2:	2380      	movs	r3, #128	; 0x80
- 8000cd4:	029b      	lsls	r3, r3, #10
- 8000cd6:	4013      	ands	r3, r2
- 8000cd8:	d114      	bne.n	8000d04 <HAL_RCC_ClockConfig+0xc4>
+ 8001662:	4b3e      	ldr	r3, [pc, #248]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 8001664:	681a      	ldr	r2, [r3, #0]
+ 8001666:	2380      	movs	r3, #128	; 0x80
+ 8001668:	029b      	lsls	r3, r3, #10
+ 800166a:	4013      	ands	r3, r2
+ 800166c:	d114      	bne.n	8001698 <HAL_RCC_ClockConfig+0xc4>
       {
         return HAL_ERROR;
- 8000cda:	2301      	movs	r3, #1
- 8000cdc:	e06e      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 800166e:	2301      	movs	r3, #1
+ 8001670:	e06e      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
       }
     }
     /* PLL is selected as System Clock Source */
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8000cde:	687b      	ldr	r3, [r7, #4]
- 8000ce0:	685b      	ldr	r3, [r3, #4]
- 8000ce2:	2b02      	cmp	r3, #2
- 8000ce4:	d107      	bne.n	8000cf6 <HAL_RCC_ClockConfig+0xb6>
+ 8001672:	687b      	ldr	r3, [r7, #4]
+ 8001674:	685b      	ldr	r3, [r3, #4]
+ 8001676:	2b02      	cmp	r3, #2
+ 8001678:	d107      	bne.n	800168a <HAL_RCC_ClockConfig+0xb6>
     {
       /* Check the PLL ready flag */  
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8000ce6:	4b38      	ldr	r3, [pc, #224]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000ce8:	681a      	ldr	r2, [r3, #0]
- 8000cea:	2380      	movs	r3, #128	; 0x80
- 8000cec:	049b      	lsls	r3, r3, #18
- 8000cee:	4013      	ands	r3, r2
- 8000cf0:	d108      	bne.n	8000d04 <HAL_RCC_ClockConfig+0xc4>
+ 800167a:	4b38      	ldr	r3, [pc, #224]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 800167c:	681a      	ldr	r2, [r3, #0]
+ 800167e:	2380      	movs	r3, #128	; 0x80
+ 8001680:	049b      	lsls	r3, r3, #18
+ 8001682:	4013      	ands	r3, r2
+ 8001684:	d108      	bne.n	8001698 <HAL_RCC_ClockConfig+0xc4>
       {
         return HAL_ERROR;
- 8000cf2:	2301      	movs	r3, #1
- 8000cf4:	e062      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 8001686:	2301      	movs	r3, #1
+ 8001688:	e062      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
 #endif /* RCC_CFGR_SWS_HSI48 */
     /* HSI is selected as System Clock Source */
     else
     {
       /* Check the HSI ready flag */  
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8000cf6:	4b34      	ldr	r3, [pc, #208]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000cf8:	681b      	ldr	r3, [r3, #0]
- 8000cfa:	2202      	movs	r2, #2
- 8000cfc:	4013      	ands	r3, r2
- 8000cfe:	d101      	bne.n	8000d04 <HAL_RCC_ClockConfig+0xc4>
+ 800168a:	4b34      	ldr	r3, [pc, #208]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 800168c:	681b      	ldr	r3, [r3, #0]
+ 800168e:	2202      	movs	r2, #2
+ 8001690:	4013      	ands	r3, r2
+ 8001692:	d101      	bne.n	8001698 <HAL_RCC_ClockConfig+0xc4>
       {
         return HAL_ERROR;
- 8000d00:	2301      	movs	r3, #1
- 8000d02:	e05b      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 8001694:	2301      	movs	r3, #1
+ 8001696:	e05b      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
       }
     }
     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 8000d04:	4b30      	ldr	r3, [pc, #192]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000d06:	685b      	ldr	r3, [r3, #4]
- 8000d08:	2203      	movs	r2, #3
- 8000d0a:	4393      	bics	r3, r2
- 8000d0c:	0019      	movs	r1, r3
- 8000d0e:	687b      	ldr	r3, [r7, #4]
- 8000d10:	685a      	ldr	r2, [r3, #4]
- 8000d12:	4b2d      	ldr	r3, [pc, #180]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000d14:	430a      	orrs	r2, r1
- 8000d16:	605a      	str	r2, [r3, #4]
+ 8001698:	4b30      	ldr	r3, [pc, #192]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 800169a:	685b      	ldr	r3, [r3, #4]
+ 800169c:	2203      	movs	r2, #3
+ 800169e:	4393      	bics	r3, r2
+ 80016a0:	0019      	movs	r1, r3
+ 80016a2:	687b      	ldr	r3, [r7, #4]
+ 80016a4:	685a      	ldr	r2, [r3, #4]
+ 80016a6:	4b2d      	ldr	r3, [pc, #180]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 80016a8:	430a      	orrs	r2, r1
+ 80016aa:	605a      	str	r2, [r3, #4]
 
     /* Get Start Tick */
     tickstart = HAL_GetTick();
- 8000d18:	f7ff fbba 	bl	8000490 <HAL_GetTick>
- 8000d1c:	0003      	movs	r3, r0
- 8000d1e:	60fb      	str	r3, [r7, #12]
+ 80016ac:	f7fe fff6 	bl	800069c <HAL_GetTick>
+ 80016b0:	0003      	movs	r3, r0
+ 80016b2:	60fb      	str	r3, [r7, #12]
     
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8000d20:	e009      	b.n	8000d36 <HAL_RCC_ClockConfig+0xf6>
+ 80016b4:	e009      	b.n	80016ca <HAL_RCC_ClockConfig+0xf6>
     {
       if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8000d22:	f7ff fbb5 	bl	8000490 <HAL_GetTick>
- 8000d26:	0002      	movs	r2, r0
- 8000d28:	68fb      	ldr	r3, [r7, #12]
- 8000d2a:	1ad3      	subs	r3, r2, r3
- 8000d2c:	4a27      	ldr	r2, [pc, #156]	; (8000dcc <HAL_RCC_ClockConfig+0x18c>)
- 8000d2e:	4293      	cmp	r3, r2
- 8000d30:	d901      	bls.n	8000d36 <HAL_RCC_ClockConfig+0xf6>
+ 80016b6:	f7fe fff1 	bl	800069c <HAL_GetTick>
+ 80016ba:	0002      	movs	r2, r0
+ 80016bc:	68fb      	ldr	r3, [r7, #12]
+ 80016be:	1ad3      	subs	r3, r2, r3
+ 80016c0:	4a27      	ldr	r2, [pc, #156]	; (8001760 <HAL_RCC_ClockConfig+0x18c>)
+ 80016c2:	4293      	cmp	r3, r2
+ 80016c4:	d901      	bls.n	80016ca <HAL_RCC_ClockConfig+0xf6>
       {
         return HAL_TIMEOUT;
- 8000d32:	2303      	movs	r3, #3
- 8000d34:	e042      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 80016c6:	2303      	movs	r3, #3
+ 80016c8:	e042      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8000d36:	4b24      	ldr	r3, [pc, #144]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000d38:	685b      	ldr	r3, [r3, #4]
- 8000d3a:	220c      	movs	r2, #12
- 8000d3c:	401a      	ands	r2, r3
- 8000d3e:	687b      	ldr	r3, [r7, #4]
- 8000d40:	685b      	ldr	r3, [r3, #4]
- 8000d42:	009b      	lsls	r3, r3, #2
- 8000d44:	429a      	cmp	r2, r3
- 8000d46:	d1ec      	bne.n	8000d22 <HAL_RCC_ClockConfig+0xe2>
+ 80016ca:	4b24      	ldr	r3, [pc, #144]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 80016cc:	685b      	ldr	r3, [r3, #4]
+ 80016ce:	220c      	movs	r2, #12
+ 80016d0:	401a      	ands	r2, r3
+ 80016d2:	687b      	ldr	r3, [r7, #4]
+ 80016d4:	685b      	ldr	r3, [r3, #4]
+ 80016d6:	009b      	lsls	r3, r3, #2
+ 80016d8:	429a      	cmp	r2, r3
+ 80016da:	d1ec      	bne.n	80016b6 <HAL_RCC_ClockConfig+0xe2>
       }
     }
   }
 
   /* Decreasing the number of wait states because of lower CPU frequency */
   if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8000d48:	4b1e      	ldr	r3, [pc, #120]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000d4a:	681b      	ldr	r3, [r3, #0]
- 8000d4c:	2201      	movs	r2, #1
- 8000d4e:	4013      	ands	r3, r2
- 8000d50:	683a      	ldr	r2, [r7, #0]
- 8000d52:	429a      	cmp	r2, r3
- 8000d54:	d211      	bcs.n	8000d7a <HAL_RCC_ClockConfig+0x13a>
+ 80016dc:	4b1e      	ldr	r3, [pc, #120]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 80016de:	681b      	ldr	r3, [r3, #0]
+ 80016e0:	2201      	movs	r2, #1
+ 80016e2:	4013      	ands	r3, r2
+ 80016e4:	683a      	ldr	r2, [r7, #0]
+ 80016e6:	429a      	cmp	r2, r3
+ 80016e8:	d211      	bcs.n	800170e <HAL_RCC_ClockConfig+0x13a>
   {    
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8000d56:	4b1b      	ldr	r3, [pc, #108]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000d58:	681b      	ldr	r3, [r3, #0]
- 8000d5a:	2201      	movs	r2, #1
- 8000d5c:	4393      	bics	r3, r2
- 8000d5e:	0019      	movs	r1, r3
- 8000d60:	4b18      	ldr	r3, [pc, #96]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000d62:	683a      	ldr	r2, [r7, #0]
- 8000d64:	430a      	orrs	r2, r1
- 8000d66:	601a      	str	r2, [r3, #0]
+ 80016ea:	4b1b      	ldr	r3, [pc, #108]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 80016ec:	681b      	ldr	r3, [r3, #0]
+ 80016ee:	2201      	movs	r2, #1
+ 80016f0:	4393      	bics	r3, r2
+ 80016f2:	0019      	movs	r1, r3
+ 80016f4:	4b18      	ldr	r3, [pc, #96]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 80016f6:	683a      	ldr	r2, [r7, #0]
+ 80016f8:	430a      	orrs	r2, r1
+ 80016fa:	601a      	str	r2, [r3, #0]
     
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8000d68:	4b16      	ldr	r3, [pc, #88]	; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
- 8000d6a:	681b      	ldr	r3, [r3, #0]
- 8000d6c:	2201      	movs	r2, #1
- 8000d6e:	4013      	ands	r3, r2
- 8000d70:	683a      	ldr	r2, [r7, #0]
- 8000d72:	429a      	cmp	r2, r3
- 8000d74:	d001      	beq.n	8000d7a <HAL_RCC_ClockConfig+0x13a>
+ 80016fc:	4b16      	ldr	r3, [pc, #88]	; (8001758 <HAL_RCC_ClockConfig+0x184>)
+ 80016fe:	681b      	ldr	r3, [r3, #0]
+ 8001700:	2201      	movs	r2, #1
+ 8001702:	4013      	ands	r3, r2
+ 8001704:	683a      	ldr	r2, [r7, #0]
+ 8001706:	429a      	cmp	r2, r3
+ 8001708:	d001      	beq.n	800170e <HAL_RCC_ClockConfig+0x13a>
     {
       return HAL_ERROR;
- 8000d76:	2301      	movs	r3, #1
- 8000d78:	e020      	b.n	8000dbc <HAL_RCC_ClockConfig+0x17c>
+ 800170a:	2301      	movs	r3, #1
+ 800170c:	e020      	b.n	8001750 <HAL_RCC_ClockConfig+0x17c>
     }
   }    
 
   /*-------------------------- PCLK1 Configuration ---------------------------*/ 
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8000d7a:	687b      	ldr	r3, [r7, #4]
- 8000d7c:	681b      	ldr	r3, [r3, #0]
- 8000d7e:	2204      	movs	r2, #4
- 8000d80:	4013      	ands	r3, r2
- 8000d82:	d009      	beq.n	8000d98 <HAL_RCC_ClockConfig+0x158>
+ 800170e:	687b      	ldr	r3, [r7, #4]
+ 8001710:	681b      	ldr	r3, [r3, #0]
+ 8001712:	2204      	movs	r2, #4
+ 8001714:	4013      	ands	r3, r2
+ 8001716:	d009      	beq.n	800172c <HAL_RCC_ClockConfig+0x158>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
- 8000d84:	4b10      	ldr	r3, [pc, #64]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000d86:	685b      	ldr	r3, [r3, #4]
- 8000d88:	4a11      	ldr	r2, [pc, #68]	; (8000dd0 <HAL_RCC_ClockConfig+0x190>)
- 8000d8a:	4013      	ands	r3, r2
- 8000d8c:	0019      	movs	r1, r3
- 8000d8e:	687b      	ldr	r3, [r7, #4]
- 8000d90:	68da      	ldr	r2, [r3, #12]
- 8000d92:	4b0d      	ldr	r3, [pc, #52]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000d94:	430a      	orrs	r2, r1
- 8000d96:	605a      	str	r2, [r3, #4]
+ 8001718:	4b10      	ldr	r3, [pc, #64]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 800171a:	685b      	ldr	r3, [r3, #4]
+ 800171c:	4a11      	ldr	r2, [pc, #68]	; (8001764 <HAL_RCC_ClockConfig+0x190>)
+ 800171e:	4013      	ands	r3, r2
+ 8001720:	0019      	movs	r1, r3
+ 8001722:	687b      	ldr	r3, [r7, #4]
+ 8001724:	68da      	ldr	r2, [r3, #12]
+ 8001726:	4b0d      	ldr	r3, [pc, #52]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 8001728:	430a      	orrs	r2, r1
+ 800172a:	605a      	str	r2, [r3, #4]
   }
   
   /* Update the SystemCoreClock global variable */
   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
- 8000d98:	f000 f820 	bl	8000ddc <HAL_RCC_GetSysClockFreq>
- 8000d9c:	0001      	movs	r1, r0
- 8000d9e:	4b0a      	ldr	r3, [pc, #40]	; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
- 8000da0:	685b      	ldr	r3, [r3, #4]
- 8000da2:	091b      	lsrs	r3, r3, #4
- 8000da4:	220f      	movs	r2, #15
- 8000da6:	4013      	ands	r3, r2
- 8000da8:	4a0a      	ldr	r2, [pc, #40]	; (8000dd4 <HAL_RCC_ClockConfig+0x194>)
- 8000daa:	5cd3      	ldrb	r3, [r2, r3]
- 8000dac:	000a      	movs	r2, r1
- 8000dae:	40da      	lsrs	r2, r3
- 8000db0:	4b09      	ldr	r3, [pc, #36]	; (8000dd8 <HAL_RCC_ClockConfig+0x198>)
- 8000db2:	601a      	str	r2, [r3, #0]
+ 800172c:	f000 f820 	bl	8001770 <HAL_RCC_GetSysClockFreq>
+ 8001730:	0001      	movs	r1, r0
+ 8001732:	4b0a      	ldr	r3, [pc, #40]	; (800175c <HAL_RCC_ClockConfig+0x188>)
+ 8001734:	685b      	ldr	r3, [r3, #4]
+ 8001736:	091b      	lsrs	r3, r3, #4
+ 8001738:	220f      	movs	r2, #15
+ 800173a:	4013      	ands	r3, r2
+ 800173c:	4a0a      	ldr	r2, [pc, #40]	; (8001768 <HAL_RCC_ClockConfig+0x194>)
+ 800173e:	5cd3      	ldrb	r3, [r2, r3]
+ 8001740:	000a      	movs	r2, r1
+ 8001742:	40da      	lsrs	r2, r3
+ 8001744:	4b09      	ldr	r3, [pc, #36]	; (800176c <HAL_RCC_ClockConfig+0x198>)
+ 8001746:	601a      	str	r2, [r3, #0]
 
   /* Configure the source of time base considering new system clocks settings*/
   HAL_InitTick (TICK_INT_PRIORITY);
- 8000db4:	2003      	movs	r0, #3
- 8000db6:	f7ff fb25 	bl	8000404 <HAL_InitTick>
+ 8001748:	2003      	movs	r0, #3
+ 800174a:	f7fe ff61 	bl	8000610 <HAL_InitTick>
   
   return HAL_OK;
- 8000dba:	2300      	movs	r3, #0
+ 800174e:	2300      	movs	r3, #0
 }
- 8000dbc:	0018      	movs	r0, r3
- 8000dbe:	46bd      	mov	sp, r7
- 8000dc0:	b004      	add	sp, #16
- 8000dc2:	bd80      	pop	{r7, pc}
- 8000dc4:	40022000 	.word	0x40022000
- 8000dc8:	40021000 	.word	0x40021000
- 8000dcc:	00001388 	.word	0x00001388
- 8000dd0:	fffff8ff 	.word	0xfffff8ff
- 8000dd4:	08000f3c 	.word	0x08000f3c
- 8000dd8:	20000000 	.word	0x20000000
+ 8001750:	0018      	movs	r0, r3
+ 8001752:	46bd      	mov	sp, r7
+ 8001754:	b004      	add	sp, #16
+ 8001756:	bd80      	pop	{r7, pc}
+ 8001758:	40022000 	.word	0x40022000
+ 800175c:	40021000 	.word	0x40021000
+ 8001760:	00001388 	.word	0x00001388
+ 8001764:	fffff8ff 	.word	0xfffff8ff
+ 8001768:	080018d0 	.word	0x080018d0
+ 800176c:	20000000 	.word	0x20000000
 
-08000ddc <HAL_RCC_GetSysClockFreq>:
+08001770 <HAL_RCC_GetSysClockFreq>:
   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
   *         
   * @retval SYSCLK frequency
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
- 8000ddc:	b590      	push	{r4, r7, lr}
- 8000dde:	b08f      	sub	sp, #60	; 0x3c
- 8000de0:	af00      	add	r7, sp, #0
+ 8001770:	b590      	push	{r4, r7, lr}
+ 8001772:	b08f      	sub	sp, #60	; 0x3c
+ 8001774:	af00      	add	r7, sp, #0
   const uint8_t aPLLMULFactorTable[16] = { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
- 8000de2:	2314      	movs	r3, #20
- 8000de4:	18fb      	adds	r3, r7, r3
- 8000de6:	4a2b      	ldr	r2, [pc, #172]	; (8000e94 <HAL_RCC_GetSysClockFreq+0xb8>)
- 8000de8:	ca13      	ldmia	r2!, {r0, r1, r4}
- 8000dea:	c313      	stmia	r3!, {r0, r1, r4}
- 8000dec:	6812      	ldr	r2, [r2, #0]
- 8000dee:	601a      	str	r2, [r3, #0]
+ 8001776:	2314      	movs	r3, #20
+ 8001778:	18fb      	adds	r3, r7, r3
+ 800177a:	4a2b      	ldr	r2, [pc, #172]	; (8001828 <HAL_RCC_GetSysClockFreq+0xb8>)
+ 800177c:	ca13      	ldmia	r2!, {r0, r1, r4}
+ 800177e:	c313      	stmia	r3!, {r0, r1, r4}
+ 8001780:	6812      	ldr	r2, [r2, #0]
+ 8001782:	601a      	str	r2, [r3, #0]
                                          10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
   const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
- 8000df0:	1d3b      	adds	r3, r7, #4
- 8000df2:	4a29      	ldr	r2, [pc, #164]	; (8000e98 <HAL_RCC_GetSysClockFreq+0xbc>)
- 8000df4:	ca13      	ldmia	r2!, {r0, r1, r4}
- 8000df6:	c313      	stmia	r3!, {r0, r1, r4}
- 8000df8:	6812      	ldr	r2, [r2, #0]
- 8000dfa:	601a      	str	r2, [r3, #0]
+ 8001784:	1d3b      	adds	r3, r7, #4
+ 8001786:	4a29      	ldr	r2, [pc, #164]	; (800182c <HAL_RCC_GetSysClockFreq+0xbc>)
+ 8001788:	ca13      	ldmia	r2!, {r0, r1, r4}
+ 800178a:	c313      	stmia	r3!, {r0, r1, r4}
+ 800178c:	6812      	ldr	r2, [r2, #0]
+ 800178e:	601a      	str	r2, [r3, #0]
                                            9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
 
   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
- 8000dfc:	2300      	movs	r3, #0
- 8000dfe:	62fb      	str	r3, [r7, #44]	; 0x2c
- 8000e00:	2300      	movs	r3, #0
- 8000e02:	62bb      	str	r3, [r7, #40]	; 0x28
- 8000e04:	2300      	movs	r3, #0
- 8000e06:	637b      	str	r3, [r7, #52]	; 0x34
- 8000e08:	2300      	movs	r3, #0
- 8000e0a:	627b      	str	r3, [r7, #36]	; 0x24
+ 8001790:	2300      	movs	r3, #0
+ 8001792:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 8001794:	2300      	movs	r3, #0
+ 8001796:	62bb      	str	r3, [r7, #40]	; 0x28
+ 8001798:	2300      	movs	r3, #0
+ 800179a:	637b      	str	r3, [r7, #52]	; 0x34
+ 800179c:	2300      	movs	r3, #0
+ 800179e:	627b      	str	r3, [r7, #36]	; 0x24
   uint32_t sysclockfreq = 0U;
- 8000e0c:	2300      	movs	r3, #0
- 8000e0e:	633b      	str	r3, [r7, #48]	; 0x30
+ 80017a0:	2300      	movs	r3, #0
+ 80017a2:	633b      	str	r3, [r7, #48]	; 0x30
   
   tmpreg = RCC->CFGR;
- 8000e10:	4b22      	ldr	r3, [pc, #136]	; (8000e9c <HAL_RCC_GetSysClockFreq+0xc0>)
- 8000e12:	685b      	ldr	r3, [r3, #4]
- 8000e14:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 80017a4:	4b22      	ldr	r3, [pc, #136]	; (8001830 <HAL_RCC_GetSysClockFreq+0xc0>)
+ 80017a6:	685b      	ldr	r3, [r3, #4]
+ 80017a8:	62fb      	str	r3, [r7, #44]	; 0x2c
   
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (tmpreg & RCC_CFGR_SWS)
- 8000e16:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8000e18:	220c      	movs	r2, #12
- 8000e1a:	4013      	ands	r3, r2
- 8000e1c:	2b04      	cmp	r3, #4
- 8000e1e:	d002      	beq.n	8000e26 <HAL_RCC_GetSysClockFreq+0x4a>
- 8000e20:	2b08      	cmp	r3, #8
- 8000e22:	d003      	beq.n	8000e2c <HAL_RCC_GetSysClockFreq+0x50>
- 8000e24:	e02d      	b.n	8000e82 <HAL_RCC_GetSysClockFreq+0xa6>
+ 80017aa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80017ac:	220c      	movs	r2, #12
+ 80017ae:	4013      	ands	r3, r2
+ 80017b0:	2b04      	cmp	r3, #4
+ 80017b2:	d002      	beq.n	80017ba <HAL_RCC_GetSysClockFreq+0x4a>
+ 80017b4:	2b08      	cmp	r3, #8
+ 80017b6:	d003      	beq.n	80017c0 <HAL_RCC_GetSysClockFreq+0x50>
+ 80017b8:	e02d      	b.n	8001816 <HAL_RCC_GetSysClockFreq+0xa6>
   {
     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
     {
       sysclockfreq = HSE_VALUE;
- 8000e26:	4b1e      	ldr	r3, [pc, #120]	; (8000ea0 <HAL_RCC_GetSysClockFreq+0xc4>)
- 8000e28:	633b      	str	r3, [r7, #48]	; 0x30
+ 80017ba:	4b1e      	ldr	r3, [pc, #120]	; (8001834 <HAL_RCC_GetSysClockFreq+0xc4>)
+ 80017bc:	633b      	str	r3, [r7, #48]	; 0x30
       break;
- 8000e2a:	e02d      	b.n	8000e88 <HAL_RCC_GetSysClockFreq+0xac>
+ 80017be:	e02d      	b.n	800181c <HAL_RCC_GetSysClockFreq+0xac>
     }
     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
     {
       pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
- 8000e2c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 8000e2e:	0c9b      	lsrs	r3, r3, #18
- 8000e30:	220f      	movs	r2, #15
- 8000e32:	4013      	ands	r3, r2
- 8000e34:	2214      	movs	r2, #20
- 8000e36:	18ba      	adds	r2, r7, r2
- 8000e38:	5cd3      	ldrb	r3, [r2, r3]
- 8000e3a:	627b      	str	r3, [r7, #36]	; 0x24
+ 80017c0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80017c2:	0c9b      	lsrs	r3, r3, #18
+ 80017c4:	220f      	movs	r2, #15
+ 80017c6:	4013      	ands	r3, r2
+ 80017c8:	2214      	movs	r2, #20
+ 80017ca:	18ba      	adds	r2, r7, r2
+ 80017cc:	5cd3      	ldrb	r3, [r2, r3]
+ 80017ce:	627b      	str	r3, [r7, #36]	; 0x24
       prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
- 8000e3c:	4b17      	ldr	r3, [pc, #92]	; (8000e9c <HAL_RCC_GetSysClockFreq+0xc0>)
- 8000e3e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8000e40:	220f      	movs	r2, #15
- 8000e42:	4013      	ands	r3, r2
- 8000e44:	1d3a      	adds	r2, r7, #4
- 8000e46:	5cd3      	ldrb	r3, [r2, r3]
- 8000e48:	62bb      	str	r3, [r7, #40]	; 0x28
+ 80017d0:	4b17      	ldr	r3, [pc, #92]	; (8001830 <HAL_RCC_GetSysClockFreq+0xc0>)
+ 80017d2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80017d4:	220f      	movs	r2, #15
+ 80017d6:	4013      	ands	r3, r2
+ 80017d8:	1d3a      	adds	r2, r7, #4
+ 80017da:	5cd3      	ldrb	r3, [r2, r3]
+ 80017dc:	62bb      	str	r3, [r7, #40]	; 0x28
       if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
- 8000e4a:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8000e4c:	2380      	movs	r3, #128	; 0x80
- 8000e4e:	025b      	lsls	r3, r3, #9
- 8000e50:	4013      	ands	r3, r2
- 8000e52:	d009      	beq.n	8000e68 <HAL_RCC_GetSysClockFreq+0x8c>
+ 80017de:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 80017e0:	2380      	movs	r3, #128	; 0x80
+ 80017e2:	025b      	lsls	r3, r3, #9
+ 80017e4:	4013      	ands	r3, r2
+ 80017e6:	d009      	beq.n	80017fc <HAL_RCC_GetSysClockFreq+0x8c>
       {
         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
         pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
- 8000e54:	6ab9      	ldr	r1, [r7, #40]	; 0x28
- 8000e56:	4812      	ldr	r0, [pc, #72]	; (8000ea0 <HAL_RCC_GetSysClockFreq+0xc4>)
- 8000e58:	f7ff f956 	bl	8000108 <__udivsi3>
- 8000e5c:	0003      	movs	r3, r0
- 8000e5e:	001a      	movs	r2, r3
- 8000e60:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 8000e62:	4353      	muls	r3, r2
- 8000e64:	637b      	str	r3, [r7, #52]	; 0x34
- 8000e66:	e009      	b.n	8000e7c <HAL_RCC_GetSysClockFreq+0xa0>
+ 80017e8:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 80017ea:	4812      	ldr	r0, [pc, #72]	; (8001834 <HAL_RCC_GetSysClockFreq+0xc4>)
+ 80017ec:	f7fe fc8c 	bl	8000108 <__udivsi3>
+ 80017f0:	0003      	movs	r3, r0
+ 80017f2:	001a      	movs	r2, r3
+ 80017f4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 80017f6:	4353      	muls	r3, r2
+ 80017f8:	637b      	str	r3, [r7, #52]	; 0x34
+ 80017fa:	e009      	b.n	8001810 <HAL_RCC_GetSysClockFreq+0xa0>
 #if  (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
         /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
         pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
 #else
         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
         pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
- 8000e68:	6a79      	ldr	r1, [r7, #36]	; 0x24
- 8000e6a:	000a      	movs	r2, r1
- 8000e6c:	0152      	lsls	r2, r2, #5
- 8000e6e:	1a52      	subs	r2, r2, r1
- 8000e70:	0193      	lsls	r3, r2, #6
- 8000e72:	1a9b      	subs	r3, r3, r2
- 8000e74:	00db      	lsls	r3, r3, #3
- 8000e76:	185b      	adds	r3, r3, r1
- 8000e78:	021b      	lsls	r3, r3, #8
- 8000e7a:	637b      	str	r3, [r7, #52]	; 0x34
+ 80017fc:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 80017fe:	000a      	movs	r2, r1
+ 8001800:	0152      	lsls	r2, r2, #5
+ 8001802:	1a52      	subs	r2, r2, r1
+ 8001804:	0193      	lsls	r3, r2, #6
+ 8001806:	1a9b      	subs	r3, r3, r2
+ 8001808:	00db      	lsls	r3, r3, #3
+ 800180a:	185b      	adds	r3, r3, r1
+ 800180c:	021b      	lsls	r3, r3, #8
+ 800180e:	637b      	str	r3, [r7, #52]	; 0x34
 #endif
       }
       sysclockfreq = pllclk;
- 8000e7c:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 8000e7e:	633b      	str	r3, [r7, #48]	; 0x30
+ 8001810:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8001812:	633b      	str	r3, [r7, #48]	; 0x30
       break;
- 8000e80:	e002      	b.n	8000e88 <HAL_RCC_GetSysClockFreq+0xac>
+ 8001814:	e002      	b.n	800181c <HAL_RCC_GetSysClockFreq+0xac>
     }
 #endif /* RCC_CFGR_SWS_HSI48 */
     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
     default: /* HSI used as system clock */
     {
       sysclockfreq = HSI_VALUE;
- 8000e82:	4b07      	ldr	r3, [pc, #28]	; (8000ea0 <HAL_RCC_GetSysClockFreq+0xc4>)
- 8000e84:	633b      	str	r3, [r7, #48]	; 0x30
+ 8001816:	4b07      	ldr	r3, [pc, #28]	; (8001834 <HAL_RCC_GetSysClockFreq+0xc4>)
+ 8001818:	633b      	str	r3, [r7, #48]	; 0x30
       break;
- 8000e86:	46c0      	nop			; (mov r8, r8)
+ 800181a:	46c0      	nop			; (mov r8, r8)
     }
   }
   return sysclockfreq;
- 8000e88:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+ 800181c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 }
- 8000e8a:	0018      	movs	r0, r3
- 8000e8c:	46bd      	mov	sp, r7
- 8000e8e:	b00f      	add	sp, #60	; 0x3c
- 8000e90:	bd90      	pop	{r4, r7, pc}
- 8000e92:	46c0      	nop			; (mov r8, r8)
- 8000e94:	08000f1c 	.word	0x08000f1c
- 8000e98:	08000f2c 	.word	0x08000f2c
- 8000e9c:	40021000 	.word	0x40021000
- 8000ea0:	007a1200 	.word	0x007a1200
+ 800181e:	0018      	movs	r0, r3
+ 8001820:	46bd      	mov	sp, r7
+ 8001822:	b00f      	add	sp, #60	; 0x3c
+ 8001824:	bd90      	pop	{r4, r7, pc}
+ 8001826:	46c0      	nop			; (mov r8, r8)
+ 8001828:	080018b0 	.word	0x080018b0
+ 800182c:	080018c0 	.word	0x080018c0
+ 8001830:	40021000 	.word	0x40021000
+ 8001834:	007a1200 	.word	0x007a1200
 
-08000ea4 <mymain>:
+08001838 <mymain>:
  *      Author: wuwenfeng
  */
 #include "my_main.h"
 
 void mymain()
 {
- 8000ea4:	b580      	push	{r7, lr}
- 8000ea6:	af00      	add	r7, sp, #0
+ 8001838:	b580      	push	{r7, lr}
+ 800183a:	af00      	add	r7, sp, #0
 
 	while(1)
- 8000ea8:	e7fe      	b.n	8000ea8 <mymain+0x4>
+ 800183c:	e7fe      	b.n	800183c <mymain+0x4>
 	...
 
-08000eac <__libc_init_array>:
- 8000eac:	b570      	push	{r4, r5, r6, lr}
- 8000eae:	2600      	movs	r6, #0
- 8000eb0:	4d0c      	ldr	r5, [pc, #48]	; (8000ee4 <__libc_init_array+0x38>)
- 8000eb2:	4c0d      	ldr	r4, [pc, #52]	; (8000ee8 <__libc_init_array+0x3c>)
- 8000eb4:	1b64      	subs	r4, r4, r5
- 8000eb6:	10a4      	asrs	r4, r4, #2
- 8000eb8:	42a6      	cmp	r6, r4
- 8000eba:	d109      	bne.n	8000ed0 <__libc_init_array+0x24>
- 8000ebc:	2600      	movs	r6, #0
- 8000ebe:	f000 f821 	bl	8000f04 <_init>
- 8000ec2:	4d0a      	ldr	r5, [pc, #40]	; (8000eec <__libc_init_array+0x40>)
- 8000ec4:	4c0a      	ldr	r4, [pc, #40]	; (8000ef0 <__libc_init_array+0x44>)
- 8000ec6:	1b64      	subs	r4, r4, r5
- 8000ec8:	10a4      	asrs	r4, r4, #2
- 8000eca:	42a6      	cmp	r6, r4
- 8000ecc:	d105      	bne.n	8000eda <__libc_init_array+0x2e>
- 8000ece:	bd70      	pop	{r4, r5, r6, pc}
- 8000ed0:	00b3      	lsls	r3, r6, #2
- 8000ed2:	58eb      	ldr	r3, [r5, r3]
- 8000ed4:	4798      	blx	r3
- 8000ed6:	3601      	adds	r6, #1
- 8000ed8:	e7ee      	b.n	8000eb8 <__libc_init_array+0xc>
- 8000eda:	00b3      	lsls	r3, r6, #2
- 8000edc:	58eb      	ldr	r3, [r5, r3]
- 8000ede:	4798      	blx	r3
- 8000ee0:	3601      	adds	r6, #1
- 8000ee2:	e7f2      	b.n	8000eca <__libc_init_array+0x1e>
- 8000ee4:	08000f4c 	.word	0x08000f4c
- 8000ee8:	08000f4c 	.word	0x08000f4c
- 8000eec:	08000f4c 	.word	0x08000f4c
- 8000ef0:	08000f50 	.word	0x08000f50
+08001840 <__libc_init_array>:
+ 8001840:	b570      	push	{r4, r5, r6, lr}
+ 8001842:	2600      	movs	r6, #0
+ 8001844:	4d0c      	ldr	r5, [pc, #48]	; (8001878 <__libc_init_array+0x38>)
+ 8001846:	4c0d      	ldr	r4, [pc, #52]	; (800187c <__libc_init_array+0x3c>)
+ 8001848:	1b64      	subs	r4, r4, r5
+ 800184a:	10a4      	asrs	r4, r4, #2
+ 800184c:	42a6      	cmp	r6, r4
+ 800184e:	d109      	bne.n	8001864 <__libc_init_array+0x24>
+ 8001850:	2600      	movs	r6, #0
+ 8001852:	f000 f821 	bl	8001898 <_init>
+ 8001856:	4d0a      	ldr	r5, [pc, #40]	; (8001880 <__libc_init_array+0x40>)
+ 8001858:	4c0a      	ldr	r4, [pc, #40]	; (8001884 <__libc_init_array+0x44>)
+ 800185a:	1b64      	subs	r4, r4, r5
+ 800185c:	10a4      	asrs	r4, r4, #2
+ 800185e:	42a6      	cmp	r6, r4
+ 8001860:	d105      	bne.n	800186e <__libc_init_array+0x2e>
+ 8001862:	bd70      	pop	{r4, r5, r6, pc}
+ 8001864:	00b3      	lsls	r3, r6, #2
+ 8001866:	58eb      	ldr	r3, [r5, r3]
+ 8001868:	4798      	blx	r3
+ 800186a:	3601      	adds	r6, #1
+ 800186c:	e7ee      	b.n	800184c <__libc_init_array+0xc>
+ 800186e:	00b3      	lsls	r3, r6, #2
+ 8001870:	58eb      	ldr	r3, [r5, r3]
+ 8001872:	4798      	blx	r3
+ 8001874:	3601      	adds	r6, #1
+ 8001876:	e7f2      	b.n	800185e <__libc_init_array+0x1e>
+ 8001878:	080018e0 	.word	0x080018e0
+ 800187c:	080018e0 	.word	0x080018e0
+ 8001880:	080018e0 	.word	0x080018e0
+ 8001884:	080018e4 	.word	0x080018e4
 
-08000ef4 <memset>:
- 8000ef4:	0003      	movs	r3, r0
- 8000ef6:	1882      	adds	r2, r0, r2
- 8000ef8:	4293      	cmp	r3, r2
- 8000efa:	d100      	bne.n	8000efe <memset+0xa>
- 8000efc:	4770      	bx	lr
- 8000efe:	7019      	strb	r1, [r3, #0]
- 8000f00:	3301      	adds	r3, #1
- 8000f02:	e7f9      	b.n	8000ef8 <memset+0x4>
+08001888 <memset>:
+ 8001888:	0003      	movs	r3, r0
+ 800188a:	1882      	adds	r2, r0, r2
+ 800188c:	4293      	cmp	r3, r2
+ 800188e:	d100      	bne.n	8001892 <memset+0xa>
+ 8001890:	4770      	bx	lr
+ 8001892:	7019      	strb	r1, [r3, #0]
+ 8001894:	3301      	adds	r3, #1
+ 8001896:	e7f9      	b.n	800188c <memset+0x4>
 
-08000f04 <_init>:
- 8000f04:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8000f06:	46c0      	nop			; (mov r8, r8)
- 8000f08:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8000f0a:	bc08      	pop	{r3}
- 8000f0c:	469e      	mov	lr, r3
- 8000f0e:	4770      	bx	lr
+08001898 <_init>:
+ 8001898:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 800189a:	46c0      	nop			; (mov r8, r8)
+ 800189c:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 800189e:	bc08      	pop	{r3}
+ 80018a0:	469e      	mov	lr, r3
+ 80018a2:	4770      	bx	lr
 
-08000f10 <_fini>:
- 8000f10:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8000f12:	46c0      	nop			; (mov r8, r8)
- 8000f14:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8000f16:	bc08      	pop	{r3}
- 8000f18:	469e      	mov	lr, r3
- 8000f1a:	4770      	bx	lr
+080018a4 <_fini>:
+ 80018a4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80018a6:	46c0      	nop			; (mov r8, r8)
+ 80018a8:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 80018aa:	bc08      	pop	{r3}
+ 80018ac:	469e      	mov	lr, r3
+ 80018ae:	4770      	bx	lr
diff --git a/Debug/Motor_Controller.map b/Debug/Motor_Controller.map
index bacd501..fda0e1f 100644
--- a/Debug/Motor_Controller.map
+++ b/Debug/Motor_Controller.map
@@ -20,6 +20,7 @@ Common symbol       size              file
 
 uwTick              0x4               ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
 pFlash              0x20              ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+hadc                0x40              ./Core/Src/main.o
 
 Discarded input sections
 
@@ -70,6 +71,9 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Core/Src/main.o
  .group         0x0000000000000000        0xc ./Core/Src/main.o
  .group         0x0000000000000000        0xc ./Core/Src/main.o
+ .group         0x0000000000000000        0xc ./Core/Src/main.o
+ .group         0x0000000000000000        0xc ./Core/Src/main.o
+ .group         0x0000000000000000        0xc ./Core/Src/main.o
  .text          0x0000000000000000        0x0 ./Core/Src/main.o
  .data          0x0000000000000000        0x0 ./Core/Src/main.o
  .bss           0x0000000000000000        0x0 ./Core/Src/main.o
@@ -109,11 +113,16 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_hal_msp.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_hal_msp.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_hal_msp.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_hal_msp.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_hal_msp.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_hal_msp.o
  .text          0x0000000000000000        0x0 ./Core/Src/stm32f0xx_hal_msp.o
  .data          0x0000000000000000        0x0 ./Core/Src/stm32f0xx_hal_msp.o
  .bss           0x0000000000000000        0x0 ./Core/Src/stm32f0xx_hal_msp.o
+ .text.HAL_ADC_MspDeInit
+                0x0000000000000000       0x40 ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000      0xa7e ./Core/Src/stm32f0xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x127 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x12d ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f0xx_hal_msp.o
@@ -140,6 +149,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x43 ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x28 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_macro   0x0000000000000000      0x33d ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_macro   0x0000000000000000       0xbc ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0xb0 ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x15a ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000      0x22c ./Core/Src/stm32f0xx_hal_msp.o
@@ -148,6 +159,10 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0x2b ./Core/Src/stm32f0xx_hal_msp.o
  .debug_macro   0x0000000000000000       0xf1 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_macro   0x0000000000000000       0x70 ./Core/Src/stm32f0xx_hal_msp.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_it.o
+ .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_it.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_it.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_it.o
  .group         0x0000000000000000        0xc ./Core/Src/stm32f0xx_it.o
@@ -188,7 +203,7 @@ Discarded input sections
  .data          0x0000000000000000        0x0 ./Core/Src/stm32f0xx_it.o
  .bss           0x0000000000000000        0x0 ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000      0xa7e ./Core/Src/stm32f0xx_it.o
- .debug_macro   0x0000000000000000      0x127 ./Core/Src/stm32f0xx_it.o
+ .debug_macro   0x0000000000000000      0x12d ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f0xx_it.o
@@ -215,6 +230,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0x43 ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0x28 ./Core/Src/stm32f0xx_it.o
+ .debug_macro   0x0000000000000000      0x33d ./Core/Src/stm32f0xx_it.o
+ .debug_macro   0x0000000000000000       0xbc ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0xb0 ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000      0x15a ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000      0x22c ./Core/Src/stm32f0xx_it.o
@@ -223,6 +240,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0x2b ./Core/Src/stm32f0xx_it.o
  .debug_macro   0x0000000000000000       0xf1 ./Core/Src/stm32f0xx_it.o
+ .debug_macro   0x0000000000000000       0x70 ./Core/Src/stm32f0xx_it.o
  .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
  .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
  .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
@@ -451,6 +469,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32f0xx.o
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32f0xx.o
  .group         0x0000000000000000        0xc ./Core/Src/system_stm32f0xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32f0xx.o
+ .group         0x0000000000000000        0xc ./Core/Src/system_stm32f0xx.o
  .text          0x0000000000000000        0x0 ./Core/Src/system_stm32f0xx.o
  .data          0x0000000000000000        0x0 ./Core/Src/system_stm32f0xx.o
  .bss           0x0000000000000000        0x0 ./Core/Src/system_stm32f0xx.o
@@ -473,7 +493,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000      0x391 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000     0x6e67 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000       0x66 ./Core/Src/system_stm32f0xx.o
- .debug_macro   0x0000000000000000      0x127 ./Core/Src/system_stm32f0xx.o
+ .debug_macro   0x0000000000000000      0x12d ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000     0x34a6 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000      0x174 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000       0x55 ./Core/Src/system_stm32f0xx.o
@@ -486,6 +506,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000       0x43 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000       0x28 ./Core/Src/system_stm32f0xx.o
+ .debug_macro   0x0000000000000000      0x33d ./Core/Src/system_stm32f0xx.o
+ .debug_macro   0x0000000000000000       0xbc ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000       0xb0 ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000      0x15a ./Core/Src/system_stm32f0xx.o
  .debug_macro   0x0000000000000000      0x22c ./Core/Src/system_stm32f0xx.o
@@ -533,6 +555,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
@@ -575,7 +599,7 @@ Discarded input sections
  .text.HAL_DBGMCU_DisableDBGStandbyMode
                 0x0000000000000000       0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
@@ -602,6 +626,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
@@ -610,6 +636,232 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_DeInit
+                0x0000000000000000      0x114 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_MspInit
+                0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_MspDeInit
+                0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_Start
+                0x0000000000000000       0xa8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_Stop
+                0x0000000000000000       0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_PollForConversion
+                0x0000000000000000      0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_PollForEvent
+                0x0000000000000000       0xc2 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_Start_IT
+                0x0000000000000000       0xe4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_Stop_IT
+                0x0000000000000000       0x94 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_Start_DMA
+                0x0000000000000000      0x104 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_Stop_DMA
+                0x0000000000000000       0xec ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_GetValue
+                0x0000000000000000       0x16 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_IRQHandler
+                0x0000000000000000      0x170 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_ConvCpltCallback
+                0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_ConvHalfCpltCallback
+                0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_LevelOutOfWindowCallback
+                0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_ErrorCallback
+                0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_AnalogWDGConfig
+                0x0000000000000000      0x11c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_GetState
+                0x0000000000000000       0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.HAL_ADC_GetError
+                0x0000000000000000       0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.ADC_Enable
+                0x0000000000000000      0x108 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.ADC_Disable
+                0x0000000000000000       0xe2 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.ADC_ConversionStop
+                0x0000000000000000       0x98 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.ADC_DMAConvCplt
+                0x0000000000000000       0xb4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.ADC_DMAHalfConvCplt
+                0x0000000000000000       0x1e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .text.ADC_DMAError
+                0x0000000000000000       0x36 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xb5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000     0x6e67 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x66 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000     0x34a6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x924 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xe5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x1af ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xb3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x1a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x1ed ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x61 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .text.HAL_ADCEx_Calibration_Start
+                0x0000000000000000      0x150 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_info    0x0000000000000000      0x65c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_abbrev  0x0000000000000000      0x149 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_aranges
+                0x0000000000000000       0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_ranges  0x0000000000000000       0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x1b9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xb5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000     0x6e67 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x66 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000     0x34a6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x924 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xe5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x1af ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xb3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x1a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x1ed ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x61 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_line    0x0000000000000000      0x773 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_str     0x0000000000000000    0x55477 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .debug_frame   0x0000000000000000       0x30 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .ARM.attributes
+                0x0000000000000000       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
@@ -684,7 +936,7 @@ Discarded input sections
  .text.HAL_SYSTICK_Callback
                 0x0000000000000000        0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
@@ -711,6 +963,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
@@ -755,6 +1009,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
@@ -793,9 +1049,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_ranges  0x0000000000000000       0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
@@ -822,6 +1078,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
@@ -830,8 +1088,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
- .debug_line    0x0000000000000000      0xc45 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
- .debug_str     0x0000000000000000    0x52d14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .debug_line    0x0000000000000000      0xc76 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
+ .debug_str     0x0000000000000000    0x55496 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .debug_frame   0x0000000000000000      0x1d0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
  .ARM.attributes
@@ -872,6 +1130,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
@@ -898,9 +1158,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_ranges  0x0000000000000000       0x50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
@@ -927,6 +1187,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
@@ -935,8 +1197,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
- .debug_line    0x0000000000000000      0x982 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
- .debug_str     0x0000000000000000    0x52ade ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .debug_line    0x0000000000000000      0x9b3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
+ .debug_str     0x0000000000000000    0x55260 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .debug_frame   0x0000000000000000      0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
  .ARM.attributes
@@ -977,6 +1239,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
@@ -1013,9 +1277,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_ranges  0x0000000000000000       0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
@@ -1042,6 +1306,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
@@ -1050,8 +1316,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
- .debug_line    0x0000000000000000      0x9f1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
- .debug_str     0x0000000000000000    0x52bf7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .debug_line    0x0000000000000000      0xa22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+ .debug_str     0x0000000000000000    0x55379 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .debug_frame   0x0000000000000000      0x1c4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
  .ARM.attributes
@@ -1093,6 +1359,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
@@ -1133,9 +1401,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x98 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_ranges  0x0000000000000000       0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x1ab ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x1bf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
@@ -1162,6 +1430,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
@@ -1170,8 +1440,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
- .debug_line    0x0000000000000000      0xaa0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
- .debug_str     0x0000000000000000    0x52d4a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .debug_line    0x0000000000000000      0xad1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
+ .debug_str     0x0000000000000000    0x554cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .debug_frame   0x0000000000000000      0x220 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o
  .ARM.attributes
@@ -1212,17 +1482,15 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .text.HAL_GPIO_Init
-                0x0000000000000000      0x2e0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .text.HAL_GPIO_DeInit
                 0x0000000000000000      0x1a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .text.HAL_GPIO_ReadPin
                 0x0000000000000000       0x3a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .text.HAL_GPIO_WritePin
-                0x0000000000000000       0x3a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .text.HAL_GPIO_TogglePin
                 0x0000000000000000       0x36 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .text.HAL_GPIO_LockPin
@@ -1231,14 +1499,8 @@ Discarded input sections
                 0x0000000000000000       0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .text.HAL_GPIO_EXTI_Callback
                 0x0000000000000000       0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_info    0x0000000000000000      0x6d3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_abbrev  0x0000000000000000      0x1e8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_aranges
-                0x0000000000000000       0x58 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_ranges  0x0000000000000000       0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x1a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
@@ -1265,6 +1527,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
@@ -1273,12 +1537,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_line    0x0000000000000000      0xaa6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_str     0x0000000000000000    0x52b1b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .debug_frame   0x0000000000000000      0x110 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
- .ARM.attributes
-                0x0000000000000000       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
@@ -1481,9 +1741,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000      0x290 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_ranges  0x0000000000000000      0x280 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
- .debug_macro   0x0000000000000000      0x25e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x272 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
@@ -1510,6 +1770,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
@@ -1518,8 +1780,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
- .debug_line    0x0000000000000000     0x3279 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
- .debug_str     0x0000000000000000    0x53bf0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .debug_line    0x0000000000000000     0x32aa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
+ .debug_str     0x0000000000000000    0x56372 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .debug_frame   0x0000000000000000      0xa24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o
  .ARM.attributes
@@ -1560,6 +1822,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
@@ -1576,9 +1840,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_ranges  0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
@@ -1605,6 +1869,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
@@ -1613,8 +1879,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
- .debug_line    0x0000000000000000      0x7ea ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
- .debug_str     0x0000000000000000    0x52eab ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .debug_line    0x0000000000000000      0x81b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
+ .debug_str     0x0000000000000000    0x5562d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .debug_frame   0x0000000000000000       0x90 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o
  .ARM.attributes
@@ -1655,6 +1921,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
@@ -1687,9 +1955,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_ranges  0x0000000000000000       0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
@@ -1716,6 +1984,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
@@ -1724,8 +1994,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
- .debug_line    0x0000000000000000      0x7f4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
- .debug_str     0x0000000000000000    0x52aa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .debug_line    0x0000000000000000      0x825 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
+ .debug_str     0x0000000000000000    0x55227 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .debug_frame   0x0000000000000000      0x170 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o
  .ARM.attributes
@@ -1766,6 +2036,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
@@ -1773,9 +2045,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x9a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x1b1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x1c5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
@@ -1802,6 +2074,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
@@ -1810,8 +2084,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
- .debug_line    0x0000000000000000      0x6a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
- .debug_str     0x0000000000000000    0x52937 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .debug_line    0x0000000000000000      0x6d8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
+ .debug_str     0x0000000000000000    0x550b9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
  .ARM.attributes
                 0x0000000000000000       0x31 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o
@@ -1851,6 +2125,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
@@ -1875,7 +2151,7 @@ Discarded input sections
  .text.HAL_RCC_CSSCallback
                 0x0000000000000000        0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
@@ -1902,6 +2178,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
@@ -1946,6 +2224,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
@@ -1960,9 +2240,9 @@ Discarded input sections
  .debug_aranges
                 0x0000000000000000       0x30 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_ranges  0x0000000000000000       0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
@@ -1989,6 +2269,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
@@ -1997,8 +2279,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
- .debug_line    0x0000000000000000      0x888 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
- .debug_str     0x0000000000000000    0x52a78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .debug_line    0x0000000000000000      0x8b9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
+ .debug_str     0x0000000000000000    0x551fa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .debug_frame   0x0000000000000000       0x70 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o
  .ARM.attributes
@@ -2039,6 +2321,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
@@ -2046,9 +2330,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x9a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
- .debug_macro   0x0000000000000000      0x19a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x1ae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
@@ -2075,6 +2359,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
@@ -2083,8 +2369,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
- .debug_line    0x0000000000000000      0x6a4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
- .debug_str     0x0000000000000000    0x528c2 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .debug_line    0x0000000000000000      0x6d5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
+ .debug_str     0x0000000000000000    0x55044 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
  .ARM.attributes
                 0x0000000000000000       0x31 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o
@@ -2124,6 +2410,8 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .group         0x0000000000000000        0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .text          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .data          0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .bss           0x0000000000000000        0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
@@ -2131,9 +2419,9 @@ Discarded input sections
  .debug_abbrev  0x0000000000000000       0x9a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_aranges
                 0x0000000000000000       0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
- .debug_macro   0x0000000000000000      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x1ad ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0xa7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
- .debug_macro   0x0000000000000000      0x127 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
@@ -2160,6 +2448,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000      0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .debug_macro   0x0000000000000000       0xbc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x15a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000      0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
@@ -2168,8 +2458,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0x2b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .debug_macro   0x0000000000000000       0xf1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
- .debug_line    0x0000000000000000      0x6a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
- .debug_str     0x0000000000000000    0x528c5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .debug_line    0x0000000000000000      0x6d8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
+ .debug_str     0x0000000000000000    0x55047 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .comment       0x0000000000000000       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
  .ARM.attributes
                 0x0000000000000000       0x31 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o
@@ -2209,11 +2499,14 @@ Discarded input sections
  .group         0x0000000000000000        0xc ./My_Soul/my_main.o
  .group         0x0000000000000000        0xc ./My_Soul/my_main.o
  .group         0x0000000000000000        0xc ./My_Soul/my_main.o
+ .group         0x0000000000000000        0xc ./My_Soul/my_main.o
+ .group         0x0000000000000000        0xc ./My_Soul/my_main.o
+ .group         0x0000000000000000        0xc ./My_Soul/my_main.o
  .text          0x0000000000000000        0x0 ./My_Soul/my_main.o
  .data          0x0000000000000000        0x0 ./My_Soul/my_main.o
  .bss           0x0000000000000000        0x0 ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000      0xa7e ./My_Soul/my_main.o
- .debug_macro   0x0000000000000000      0x127 ./My_Soul/my_main.o
+ .debug_macro   0x0000000000000000      0x12d ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0x2e ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0x22 ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0x22 ./My_Soul/my_main.o
@@ -2240,6 +2533,8 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x34 ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0x43 ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0x28 ./My_Soul/my_main.o
+ .debug_macro   0x0000000000000000      0x33d ./My_Soul/my_main.o
+ .debug_macro   0x0000000000000000       0xbc ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0xb0 ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000      0x15a ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000      0x22c ./My_Soul/my_main.o
@@ -2248,6 +2543,7 @@ Discarded input sections
  .debug_macro   0x0000000000000000       0x4c ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0x2b ./My_Soul/my_main.o
  .debug_macro   0x0000000000000000       0xf1 ./My_Soul/my_main.o
+ .debug_macro   0x0000000000000000       0x70 ./My_Soul/my_main.o
  .text          0x0000000000000000        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o)
  .data          0x0000000000000000        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o)
  .bss           0x0000000000000000        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o)
@@ -2313,6 +2609,8 @@ LOAD ./Core/Src/sysmem.o
 LOAD ./Core/Src/system_stm32f0xx.o
 LOAD ./Core/Startup/startup_stm32f030f4px.o
 LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o
 LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
 LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o
 LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o
@@ -2359,7 +2657,7 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
                 0x0000000008000000                g_pfnVectors
                 0x00000000080000c0                . = ALIGN (0x4)
 
-.text           0x00000000080000c0      0xe5c
+.text           0x00000000080000c0     0x17f0
                 0x00000000080000c0                . = ALIGN (0x4)
  *(.text)
  .text          0x00000000080000c0       0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
@@ -2371,183 +2669,201 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
                 0x000000000800021c                __aeabi_ldiv0
                 0x000000000800021c                __aeabi_idiv0
  *(.text*)
- .text.main     0x0000000008000220       0x16 ./Core/Src/main.o
+ .text.main     0x0000000008000220       0x1a ./Core/Src/main.o
                 0x0000000008000220                main
  .text.SystemClock_Config
-                0x0000000008000236       0x94 ./Core/Src/main.o
-                0x0000000008000236                SystemClock_Config
- *fill*         0x00000000080002ca        0x2 
+                0x000000000800023a       0xa0 ./Core/Src/main.o
+                0x000000000800023a                SystemClock_Config
+ *fill*         0x00000000080002da        0x2 
+ .text.MX_ADC_Init
+                0x00000000080002dc       0xb8 ./Core/Src/main.o
  .text.MX_GPIO_Init
-                0x00000000080002cc       0x30 ./Core/Src/main.o
+                0x0000000008000394       0xe8 ./Core/Src/main.o
  .text.Error_Handler
-                0x00000000080002fc        0xa ./Core/Src/main.o
-                0x00000000080002fc                Error_Handler
- *fill*         0x0000000008000306        0x2 
+                0x000000000800047c        0xa ./Core/Src/main.o
+                0x000000000800047c                Error_Handler
+ *fill*         0x0000000008000486        0x2 
  .text.HAL_MspInit
-                0x0000000008000308       0x48 ./Core/Src/stm32f0xx_hal_msp.o
-                0x0000000008000308                HAL_MspInit
+                0x0000000008000488       0x48 ./Core/Src/stm32f0xx_hal_msp.o
+                0x0000000008000488                HAL_MspInit
+ .text.HAL_ADC_MspInit
+                0x00000000080004d0       0x8c ./Core/Src/stm32f0xx_hal_msp.o
+                0x00000000080004d0                HAL_ADC_MspInit
  .text.NMI_Handler
-                0x0000000008000350        0x6 ./Core/Src/stm32f0xx_it.o
-                0x0000000008000350                NMI_Handler
+                0x000000000800055c        0x6 ./Core/Src/stm32f0xx_it.o
+                0x000000000800055c                NMI_Handler
  .text.HardFault_Handler
-                0x0000000008000356        0x6 ./Core/Src/stm32f0xx_it.o
-                0x0000000008000356                HardFault_Handler
+                0x0000000008000562        0x6 ./Core/Src/stm32f0xx_it.o
+                0x0000000008000562                HardFault_Handler
  .text.SVC_Handler
-                0x000000000800035c        0xa ./Core/Src/stm32f0xx_it.o
-                0x000000000800035c                SVC_Handler
+                0x0000000008000568        0xa ./Core/Src/stm32f0xx_it.o
+                0x0000000008000568                SVC_Handler
  .text.PendSV_Handler
-                0x0000000008000366        0xa ./Core/Src/stm32f0xx_it.o
-                0x0000000008000366                PendSV_Handler
+                0x0000000008000572        0xa ./Core/Src/stm32f0xx_it.o
+                0x0000000008000572                PendSV_Handler
  .text.SysTick_Handler
-                0x0000000008000370        0xe ./Core/Src/stm32f0xx_it.o
-                0x0000000008000370                SysTick_Handler
+                0x000000000800057c        0xe ./Core/Src/stm32f0xx_it.o
+                0x000000000800057c                SysTick_Handler
  .text.SystemInit
-                0x000000000800037e        0xa ./Core/Src/system_stm32f0xx.o
-                0x000000000800037e                SystemInit
+                0x000000000800058a        0xa ./Core/Src/system_stm32f0xx.o
+                0x000000000800058a                SystemInit
  .text.Reset_Handler
-                0x0000000008000388       0x50 ./Core/Startup/startup_stm32f030f4px.o
-                0x0000000008000388                Reset_Handler
+                0x0000000008000594       0x50 ./Core/Startup/startup_stm32f030f4px.o
+                0x0000000008000594                Reset_Handler
  .text.Default_Handler
-                0x00000000080003d8        0x2 ./Core/Startup/startup_stm32f030f4px.o
-                0x00000000080003d8                TIM1_BRK_UP_TRG_COM_IRQHandler
-                0x00000000080003d8                I2C1_IRQHandler
-                0x00000000080003d8                SPI1_IRQHandler
-                0x00000000080003d8                EXTI2_3_IRQHandler
-                0x00000000080003d8                ADC1_IRQHandler
-                0x00000000080003d8                TIM17_IRQHandler
-                0x00000000080003d8                RTC_IRQHandler
-                0x00000000080003d8                TIM16_IRQHandler
-                0x00000000080003d8                TIM3_IRQHandler
-                0x00000000080003d8                EXTI4_15_IRQHandler
-                0x00000000080003d8                RCC_IRQHandler
-                0x00000000080003d8                DMA1_Channel1_IRQHandler
-                0x00000000080003d8                Default_Handler
-                0x00000000080003d8                TIM14_IRQHandler
-                0x00000000080003d8                DMA1_Channel4_5_IRQHandler
-                0x00000000080003d8                EXTI0_1_IRQHandler
-                0x00000000080003d8                WWDG_IRQHandler
-                0x00000000080003d8                DMA1_Channel2_3_IRQHandler
-                0x00000000080003d8                FLASH_IRQHandler
-                0x00000000080003d8                USART1_IRQHandler
-                0x00000000080003d8                TIM1_CC_IRQHandler
- *fill*         0x00000000080003da        0x2 
+                0x00000000080005e4        0x2 ./Core/Startup/startup_stm32f030f4px.o
+                0x00000000080005e4                TIM1_BRK_UP_TRG_COM_IRQHandler
+                0x00000000080005e4                I2C1_IRQHandler
+                0x00000000080005e4                SPI1_IRQHandler
+                0x00000000080005e4                EXTI2_3_IRQHandler
+                0x00000000080005e4                ADC1_IRQHandler
+                0x00000000080005e4                TIM17_IRQHandler
+                0x00000000080005e4                RTC_IRQHandler
+                0x00000000080005e4                TIM16_IRQHandler
+                0x00000000080005e4                TIM3_IRQHandler
+                0x00000000080005e4                EXTI4_15_IRQHandler
+                0x00000000080005e4                RCC_IRQHandler
+                0x00000000080005e4                DMA1_Channel1_IRQHandler
+                0x00000000080005e4                Default_Handler
+                0x00000000080005e4                TIM14_IRQHandler
+                0x00000000080005e4                DMA1_Channel4_5_IRQHandler
+                0x00000000080005e4                EXTI0_1_IRQHandler
+                0x00000000080005e4                WWDG_IRQHandler
+                0x00000000080005e4                DMA1_Channel2_3_IRQHandler
+                0x00000000080005e4                FLASH_IRQHandler
+                0x00000000080005e4                USART1_IRQHandler
+                0x00000000080005e4                TIM1_CC_IRQHandler
+ *fill*         0x00000000080005e6        0x2 
  .text.HAL_Init
-                0x00000000080003dc       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
-                0x00000000080003dc                HAL_Init
+                0x00000000080005e8       0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+                0x00000000080005e8                HAL_Init
  .text.HAL_InitTick
-                0x0000000008000404       0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
-                0x0000000008000404                HAL_InitTick
+                0x0000000008000610       0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+                0x0000000008000610                HAL_InitTick
  .text.HAL_IncTick
-                0x000000000800046c       0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
-                0x000000000800046c                HAL_IncTick
+                0x0000000008000678       0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+                0x0000000008000678                HAL_IncTick
  .text.HAL_GetTick
-                0x0000000008000490       0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
-                0x0000000008000490                HAL_GetTick
+                0x000000000800069c       0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+                0x000000000800069c                HAL_GetTick
+ .text.HAL_ADC_Init
+                0x00000000080006b0      0x280 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+                0x00000000080006b0                HAL_ADC_Init
+ .text.HAL_ADC_ConfigChannel
+                0x0000000008000930      0x1ec ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+                0x0000000008000930                HAL_ADC_ConfigChannel
  .text.__NVIC_SetPriority
-                0x00000000080004a4       0xdc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+                0x0000000008000b1c       0xdc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .text.SysTick_Config
-                0x0000000008000580       0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+                0x0000000008000bf8       0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .text.HAL_NVIC_SetPriority
-                0x00000000080005c8       0x2a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
-                0x00000000080005c8                HAL_NVIC_SetPriority
+                0x0000000008000c40       0x2a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+                0x0000000008000c40                HAL_NVIC_SetPriority
  .text.HAL_SYSTICK_Config
-                0x00000000080005f2       0x1a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
-                0x00000000080005f2                HAL_SYSTICK_Config
+                0x0000000008000c6a       0x1a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+                0x0000000008000c6a                HAL_SYSTICK_Config
+ .text.HAL_GPIO_Init
+                0x0000000008000c84      0x2e0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+                0x0000000008000c84                HAL_GPIO_Init
+ .text.HAL_GPIO_WritePin
+                0x0000000008000f64       0x3a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+                0x0000000008000f64                HAL_GPIO_WritePin
+ *fill*         0x0000000008000f9e        0x2 
  .text.HAL_RCC_OscConfig
-                0x000000000800060c      0x634 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
-                0x000000000800060c                HAL_RCC_OscConfig
+                0x0000000008000fa0      0x634 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+                0x0000000008000fa0                HAL_RCC_OscConfig
  .text.HAL_RCC_ClockConfig
-                0x0000000008000c40      0x19c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
-                0x0000000008000c40                HAL_RCC_ClockConfig
+                0x00000000080015d4      0x19c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+                0x00000000080015d4                HAL_RCC_ClockConfig
  .text.HAL_RCC_GetSysClockFreq
-                0x0000000008000ddc       0xc8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
-                0x0000000008000ddc                HAL_RCC_GetSysClockFreq
- .text.mymain   0x0000000008000ea4        0x6 ./My_Soul/my_main.o
-                0x0000000008000ea4                mymain
- *fill*         0x0000000008000eaa        0x2 
+                0x0000000008001770       0xc8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+                0x0000000008001770                HAL_RCC_GetSysClockFreq
+ .text.mymain   0x0000000008001838        0x6 ./My_Soul/my_main.o
+                0x0000000008001838                mymain
+ *fill*         0x000000000800183e        0x2 
  .text.__libc_init_array
-                0x0000000008000eac       0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
-                0x0000000008000eac                __libc_init_array
- .text.memset   0x0000000008000ef4       0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
-                0x0000000008000ef4                memset
+                0x0000000008001840       0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+                0x0000000008001840                __libc_init_array
+ .text.memset   0x0000000008001888       0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+                0x0000000008001888                memset
  *(.glue_7)
- .glue_7        0x0000000008000f04        0x0 linker stubs
+ .glue_7        0x0000000008001898        0x0 linker stubs
  *(.glue_7t)
- .glue_7t       0x0000000008000f04        0x0 linker stubs
+ .glue_7t       0x0000000008001898        0x0 linker stubs
  *(.eh_frame)
- .eh_frame      0x0000000008000f04        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ .eh_frame      0x0000000008001898        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
  *(.init)
- .init          0x0000000008000f04        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
-                0x0000000008000f04                _init
- .init          0x0000000008000f08        0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+ .init          0x0000000008001898        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+                0x0000000008001898                _init
+ .init          0x000000000800189c        0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
  *(.fini)
- .fini          0x0000000008000f10        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
-                0x0000000008000f10                _fini
- .fini          0x0000000008000f14        0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
-                0x0000000008000f1c                . = ALIGN (0x4)
-                0x0000000008000f1c                _etext = .
+ .fini          0x00000000080018a4        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+                0x00000000080018a4                _fini
+ .fini          0x00000000080018a8        0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+                0x00000000080018b0                . = ALIGN (0x4)
+                0x00000000080018b0                _etext = .
 
-.vfp11_veneer   0x0000000008000f1c        0x0
- .vfp11_veneer  0x0000000008000f1c        0x0 linker stubs
+.vfp11_veneer   0x00000000080018b0        0x0
+ .vfp11_veneer  0x00000000080018b0        0x0 linker stubs
 
-.v4_bx          0x0000000008000f1c        0x0
- .v4_bx         0x0000000008000f1c        0x0 linker stubs
+.v4_bx          0x00000000080018b0        0x0
+ .v4_bx         0x00000000080018b0        0x0 linker stubs
 
-.iplt           0x0000000008000f1c        0x0
- .iplt          0x0000000008000f1c        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+.iplt           0x00000000080018b0        0x0
+ .iplt          0x00000000080018b0        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
 
-.rodata         0x0000000008000f1c       0x30
-                0x0000000008000f1c                . = ALIGN (0x4)
+.rodata         0x00000000080018b0       0x30
+                0x00000000080018b0                . = ALIGN (0x4)
  *(.rodata)
- .rodata        0x0000000008000f1c       0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .rodata        0x00000000080018b0       0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  *(.rodata*)
  .rodata.AHBPrescTable
-                0x0000000008000f3c       0x10 ./Core/Src/system_stm32f0xx.o
-                0x0000000008000f3c                AHBPrescTable
-                0x0000000008000f4c                . = ALIGN (0x4)
+                0x00000000080018d0       0x10 ./Core/Src/system_stm32f0xx.o
+                0x00000000080018d0                AHBPrescTable
+                0x00000000080018e0                . = ALIGN (0x4)
 
-.rel.dyn        0x0000000008000f4c        0x0
- .rel.iplt      0x0000000008000f4c        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+.rel.dyn        0x00000000080018e0        0x0
+ .rel.iplt      0x00000000080018e0        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
 
-.ARM.extab      0x0000000008000f4c        0x0
-                0x0000000008000f4c                . = ALIGN (0x4)
+.ARM.extab      0x00000000080018e0        0x0
+                0x00000000080018e0                . = ALIGN (0x4)
  *(.ARM.extab* .gnu.linkonce.armextab.*)
-                0x0000000008000f4c                . = ALIGN (0x4)
+                0x00000000080018e0                . = ALIGN (0x4)
 
-.ARM            0x0000000008000f4c        0x0
-                0x0000000008000f4c                . = ALIGN (0x4)
-                0x0000000008000f4c                __exidx_start = .
+.ARM            0x00000000080018e0        0x0
+                0x00000000080018e0                . = ALIGN (0x4)
+                0x00000000080018e0                __exidx_start = .
  *(.ARM.exidx*)
-                0x0000000008000f4c                __exidx_end = .
-                0x0000000008000f4c                . = ALIGN (0x4)
+                0x00000000080018e0                __exidx_end = .
+                0x00000000080018e0                . = ALIGN (0x4)
 
-.preinit_array  0x0000000008000f4c        0x0
-                0x0000000008000f4c                . = ALIGN (0x4)
-                0x0000000008000f4c                PROVIDE (__preinit_array_start = .)
+.preinit_array  0x00000000080018e0        0x0
+                0x00000000080018e0                . = ALIGN (0x4)
+                0x00000000080018e0                PROVIDE (__preinit_array_start = .)
  *(.preinit_array*)
-                0x0000000008000f4c                PROVIDE (__preinit_array_end = .)
-                0x0000000008000f4c                . = ALIGN (0x4)
+                0x00000000080018e0                PROVIDE (__preinit_array_end = .)
+                0x00000000080018e0                . = ALIGN (0x4)
 
-.init_array     0x0000000008000f4c        0x4
-                0x0000000008000f4c                . = ALIGN (0x4)
-                0x0000000008000f4c                PROVIDE (__init_array_start = .)
+.init_array     0x00000000080018e0        0x4
+                0x00000000080018e0                . = ALIGN (0x4)
+                0x00000000080018e0                PROVIDE (__init_array_start = .)
  *(SORT_BY_NAME(.init_array.*))
  *(.init_array*)
- .init_array    0x0000000008000f4c        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
-                0x0000000008000f50                PROVIDE (__init_array_end = .)
-                0x0000000008000f50                . = ALIGN (0x4)
+ .init_array    0x00000000080018e0        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+                0x00000000080018e4                PROVIDE (__init_array_end = .)
+                0x00000000080018e4                . = ALIGN (0x4)
 
-.fini_array     0x0000000008000f50        0x4
-                0x0000000008000f50                . = ALIGN (0x4)
+.fini_array     0x00000000080018e4        0x4
+                0x00000000080018e4                . = ALIGN (0x4)
                 [!provide]                        PROVIDE (__fini_array_start = .)
  *(SORT_BY_NAME(.fini_array.*))
  *(.fini_array*)
- .fini_array    0x0000000008000f50        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ .fini_array    0x00000000080018e4        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
                 [!provide]                        PROVIDE (__fini_array_end = .)
-                0x0000000008000f54                . = ALIGN (0x4)
-                0x0000000008000f54                _sidata = LOADADDR (.data)
+                0x00000000080018e8                . = ALIGN (0x4)
+                0x00000000080018e8                _sidata = LOADADDR (.data)
 
-.data           0x0000000020000000        0xc load address 0x0000000008000f54
+.data           0x0000000020000000        0xc load address 0x00000000080018e8
                 0x0000000020000000                . = ALIGN (0x4)
                 0x0000000020000000                _sdata = .
  *(.data)
@@ -2567,34 +2883,36 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
  *fill*         0x0000000020000009        0x3 
                 0x000000002000000c                _edata = .
 
-.igot.plt       0x000000002000000c        0x0 load address 0x0000000008000f60
+.igot.plt       0x000000002000000c        0x0 load address 0x00000000080018f4
  .igot.plt      0x000000002000000c        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
                 0x000000002000000c                . = ALIGN (0x4)
 
-.bss            0x000000002000000c       0x20 load address 0x0000000008000f60
+.bss            0x000000002000000c       0x60 load address 0x00000000080018f4
                 0x000000002000000c                _sbss = .
                 0x000000002000000c                __bss_start__ = _sbss
  *(.bss)
  .bss           0x000000002000000c       0x1c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
  *(.bss*)
  *(COMMON)
- COMMON         0x0000000020000028        0x4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
-                0x0000000020000028                uwTick
-                0x000000002000002c                . = ALIGN (0x4)
-                0x000000002000002c                _ebss = .
-                0x000000002000002c                __bss_end__ = _ebss
+ COMMON         0x0000000020000028       0x40 ./Core/Src/main.o
+                0x0000000020000028                hadc
+ COMMON         0x0000000020000068        0x4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+                0x0000000020000068                uwTick
+                0x000000002000006c                . = ALIGN (0x4)
+                0x000000002000006c                _ebss = .
+                0x000000002000006c                __bss_end__ = _ebss
 
 ._user_heap_stack
-                0x000000002000002c      0x604 load address 0x0000000008000f60
-                0x0000000020000030                . = ALIGN (0x8)
- *fill*         0x000000002000002c        0x4 
+                0x000000002000006c      0x604 load address 0x00000000080018f4
+                0x0000000020000070                . = ALIGN (0x8)
+ *fill*         0x000000002000006c        0x4 
                 [!provide]                        PROVIDE (end = .)
-                0x0000000020000030                PROVIDE (_end = .)
-                0x0000000020000230                . = (. + _Min_Heap_Size)
- *fill*         0x0000000020000030      0x200 
-                0x0000000020000630                . = (. + _Min_Stack_Size)
- *fill*         0x0000000020000230      0x400 
-                0x0000000020000630                . = ALIGN (0x8)
+                0x0000000020000070                PROVIDE (_end = .)
+                0x0000000020000270                . = (. + _Min_Heap_Size)
+ *fill*         0x0000000020000070      0x200 
+                0x0000000020000670                . = (. + _Min_Stack_Size)
+ *fill*         0x0000000020000270      0x400 
+                0x0000000020000670                . = ALIGN (0x8)
 
 /DISCARD/
  libc.a(*)
@@ -2621,156 +2939,181 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
  .ARM.attributes
                 0x000000000000011b       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
  .ARM.attributes
-                0x0000000000000147       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+                0x0000000000000147       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
  .ARM.attributes
-                0x0000000000000173       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+                0x0000000000000173       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
  .ARM.attributes
-                0x000000000000019f       0x2c ./My_Soul/my_main.o
+                0x000000000000019f       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .ARM.attributes
-                0x00000000000001cb       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+                0x00000000000001cb       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .ARM.attributes
-                0x00000000000001f7       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+                0x00000000000001f7       0x2c ./My_Soul/my_main.o
  .ARM.attributes
-                0x0000000000000223       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+                0x0000000000000223       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
  .ARM.attributes
-                0x0000000000000241       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+                0x000000000000024f       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
  .ARM.attributes
-                0x000000000000025f       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+                0x000000000000027b       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .ARM.attributes
+                0x0000000000000299       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .ARM.attributes
+                0x00000000000002b7       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
 OUTPUT(Motor_Controller.elf elf32-littlearm)
 LOAD linker stubs
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc.a
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
 
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+                                      0x550be (size before relaxing)
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                                          0x7b (size before relaxing)
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-                                      0x528bc (size before relaxing)
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+ .debug_str     0x0000000000056125      0x240 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+                                      0x554c8 (size before relaxing)
+ .debug_str     0x0000000000056365       0x1c ./My_Soul/my_main.o
+                                      0x551ce (size before relaxing)
 
 .comment        0x0000000000000000       0x53
  .comment       0x0000000000000000       0x53 ./Core/Src/main.o
@@ -2779,19 +3122,23 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
  .comment       0x0000000000000053       0x54 ./Core/Src/stm32f0xx_it.o
  .comment       0x0000000000000053       0x54 ./Core/Src/system_stm32f0xx.o
  .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
  .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
  .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
  .comment       0x0000000000000053       0x54 ./My_Soul/my_main.o
 
-.debug_frame    0x0000000000000000      0x914
- .debug_frame   0x0000000000000000       0x88 ./Core/Src/main.o
- .debug_frame   0x0000000000000088       0x30 ./Core/Src/stm32f0xx_hal_msp.o
- .debug_frame   0x00000000000000b8       0x9c ./Core/Src/stm32f0xx_it.o
- .debug_frame   0x0000000000000154       0x4c ./Core/Src/system_stm32f0xx.o
- .debug_frame   0x00000000000001a0      0x2a4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
- .debug_frame   0x0000000000000444      0x2a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
- .debug_frame   0x00000000000006e4      0x198 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
- .debug_frame   0x000000000000087c       0x2c ./My_Soul/my_main.o
- .debug_frame   0x00000000000008a8       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
- .debug_frame   0x00000000000008d4       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
- .debug_frame   0x00000000000008f4       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+.debug_frame    0x0000000000000000      0xe24
+ .debug_frame   0x0000000000000000       0xa8 ./Core/Src/main.o
+ .debug_frame   0x00000000000000a8       0x70 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_frame   0x0000000000000118       0x9c ./Core/Src/stm32f0xx_it.o
+ .debug_frame   0x00000000000001b4       0x4c ./Core/Src/system_stm32f0xx.o
+ .debug_frame   0x0000000000000200      0x2a4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_frame   0x00000000000004a4      0x3a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o
+ .debug_frame   0x0000000000000844      0x2a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_frame   0x0000000000000ae4      0x110 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_frame   0x0000000000000bf4      0x198 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_frame   0x0000000000000d8c       0x2c ./My_Soul/my_main.o
+ .debug_frame   0x0000000000000db8       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ .debug_frame   0x0000000000000de4       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ .debug_frame   0x0000000000000e04       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
diff --git a/Debug/My_Soul/my_main.d b/Debug/My_Soul/my_main.d
index 13312df..3249bd5 100644
--- a/Debug/My_Soul/my_main.d
+++ b/Debug/My_Soul/my_main.d
@@ -18,6 +18,8 @@ My_Soul/my_main.o: ../My_Soul/my_main.c ../My_Soul/my_main.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
  ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
@@ -67,6 +69,10 @@ My_Soul/my_main.o: ../My_Soul/my_main.c ../My_Soul/my_main.h \
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
 
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h:
+
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
 
 ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
diff --git a/Debug/objects.list b/Debug/objects.list
index da07740..e89e838 100644
--- a/Debug/objects.list
+++ b/Debug/objects.list
@@ -6,6 +6,8 @@
 "./Core/Src/system_stm32f0xx.o"
 "./Core/Startup/startup_stm32f030f4px.o"
 "./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o"
 "./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o"
 "./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o"
 "./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o"
diff --git a/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h b/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h
new file mode 100644
index 0000000..31771b1
--- /dev/null
+++ b/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h
@@ -0,0 +1,1019 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file containing functions prototypes of ADC HAL library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F0xx_HAL_ADC_H
+#define STM32F0xx_HAL_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"  
+
+/** @addtogroup STM32F0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+     
+/**
+  * @brief  Structure definition of ADC initialization and regular group  
+  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler')
+  *          - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler.
+                                       This parameter can be a value of @ref ADC_ClockPrescaler
+                                       Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. 
+                                       Note: This parameter can be modified only if the ADC is disabled */
+  uint32_t Resolution;            /*!< Configures the ADC resolution. 
+                                       This parameter can be a value of @ref ADC_Resolution */
+  uint32_t DataAlign;             /*!< Specifies whether the ADC data  alignment is left or right.  
+                                       This parameter can be a value of @ref ADC_Data_align */
+  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular group.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                       Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
+                                       If only 1 channel is set: Conversion is performed in single mode.
+                                       If several channels are set:  Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                                                     Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */ 
+  FunctionalState LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
+                                       conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue().
+                                       This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
+                                             and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
+  FunctionalState LowPowerAutoPowerOff;  /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+                                       This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
+  FunctionalState ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+                                       after the selected trigger occurred (software start or external trigger).
+                                       This parameter can be set to ENABLE or DISABLE. */
+  FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                       This parameter can be set to ENABLE or DISABLE
+                                       Note: Number of discontinuous ranks increment is fixed to one-by-one. */
+  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled.
+                                       This parameter can be a value of @ref ADC_External_trigger_source_Regular */
+  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
+                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+  FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+                                       This parameter can be set to ENABLE or DISABLE. */
+  uint32_t Overrun;               /*!< Select the behaviour in case of overrun: data preserved or overwritten 
+                                       This parameter has an effect on regular group only, including in DMA mode.
+                                       This parameter can be a value of @ref ADC_Overrun */
+  uint32_t SamplingTimeCommon;    /*!< Sampling time value to be set for the selected channel.
+                                       Unit: ADC clock cycles
+                                       Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                       Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+                                       This parameter can be a value of @ref ADC_sampling_times
+                                       Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                             sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                             Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
+}ADC_InitTypeDef;
+
+/** 
+  * @brief  Structure definition of ADC channel for regular group  
+  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct 
+{
+  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_channels
+                                        Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+  uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer. 
+                                        On STM32F0 devices,  number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...)..
+                                        Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+                                        This parameter can be a value of @ref ADC_rank */
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_sampling_times
+                                        Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set.
+                                        Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure.
+                                                 If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded.
+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
+}ADC_ChannelConfTypeDef;
+
+/** 
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
+  */
+typedef struct
+{
+  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all/none channels.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+  uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
+                                   This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
+                                   This parameter can be a value of @ref ADC_channels. */
+  FunctionalState ITMode;     /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+}ADC_AnalogWDGConfTypeDef;
+
+/** 
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:                                                         
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             (0x00000000U)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             (0x00000001U)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           (0x00000004U)    /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010U)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020U)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040U)    /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          (0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+                                                                       external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC           (0x00000200U)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           (0x00000400U)    /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800U)    /*!< Not available on STM32F0 device: End Of Sampling flag raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000U)    /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+                                                                       external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC           (0x00002000U)    /*!< Not available on STM32F0 device: Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000U)    /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              (0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              (0x00020000U)    /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              (0x00040000U)    /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000U)    /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
+
+
+/** 
+  * @brief  ADC handle Structure definition  
+  */ 
+typedef struct __ADC_HandleTypeDef
+{
+  ADC_TypeDef                   *Instance;              /*!< Register base address */
+
+  ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
+
+  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
+
+  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
+
+  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
+
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */ 
+#define HAL_ADC_ERROR_NONE        (0x00U)   /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL    (0x01U)   /*!< ADC IP internal error: if problem of clocking, 
+                                                 enable/disable, erroneous state                       */
+#define HAL_ADC_ERROR_OVR         (0x02U)   /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA         (0x04U)   /*!< DMA transfer error                                    */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
+  * @{
+  */     
+#define ADC_CLOCK_ASYNC_DIV1          (0x00000000U)          /*!< ADC asynchronous clock derived from ADC dedicated HSI */
+
+#define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC_CFGR2_CKMODE_0)  /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC_CFGR2_CKMODE_1)  /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Resolution ADC Resolution
+  * @{
+  */ 
+#define ADC_RESOLUTION_12B      (0x00000000U)           /*!<  ADC 12-bit resolution */
+#define ADC_RESOLUTION_10B      ((uint32_t)ADC_CFGR1_RES_0)      /*!<  ADC 10-bit resolution */
+#define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR1_RES_1)      /*!<  ADC 8-bit resolution */
+#define ADC_RESOLUTION_6B       ((uint32_t)ADC_CFGR1_RES)        /*!<  ADC 6-bit resolution */
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Data_align ADC Data_align
+  * @{
+  */ 
+#define ADC_DATAALIGN_RIGHT      (0x00000000U)
+#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR1_ALIGN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Scan_mode ADC Scan mode
+  * @{
+  */
+/* Note: Scan mode values must be compatible with other STM32 devices having  */
+/*       a configurable sequencer.                                            */
+/*       Scan direction setting values are defined by taking in account       */
+/*       already defined values for other STM32 devices:                      */
+/*         ADC_SCAN_DISABLE         (0x00000000U)                    */
+/*         ADC_SCAN_ENABLE          (0x00000001U)                    */
+/*       Scan direction forward is considered as default setting equivalent   */
+/*       to scan enable.                                                      */
+/*       Scan direction backward is considered as additional setting.         */
+/*       In case of migration from another STM32 device, the user will be     */
+/*       warned of change of setting choices with assert check.               */
+#define ADC_SCAN_DIRECTION_FORWARD        (0x00000001U)        /*!< Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_DIRECTION_BACKWARD       (0x00000002U)        /*!< Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_ENABLE         ADC_SCAN_DIRECTION_FORWARD       /* For compatibility with other STM32 devices */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
+  * @{
+  */ 
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000U)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR1_EXTEN_0)         
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR1_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR1_EXTEN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_EOCSelection ADC EOCSelection
+  * @{
+  */ 
+#define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Overrun ADC Overrun
+  * @{
+  */ 
+#define ADC_OVR_DATA_OVERWRITTEN            (0x00000000U)
+#define ADC_OVR_DATA_PRESERVED              (0x00000001U)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_rank ADC rank
+  * @{
+  */ 
+#define ADC_RANK_CHANNEL_NUMBER                 (0x00001000U)  /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE                           (0x00001001U)  /*!< Disable the selected rank (selected channel) from sequencer */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_times ADC sampling times
+  * @{
+  */
+/* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit         */
+/*       to distinguish this parameter versus reset value 0x00000000,         */
+/*       in the context of management of parameters "SamplingTimeCommon"      */
+/*       and "SamplingTime" (obsolete)).                                      */    
+#define ADC_SAMPLETIME_1CYCLE_5       (0x10000000U)                        /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t) ADC_SMPR_SMP_0)                   /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5     ((uint32_t) ADC_SMPR_SMP_1)                   /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5     ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5     ((uint32_t) ADC_SMPR_SMP_2)                   /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5     ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5     ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5    ((uint32_t) ADC_SMPR_SMP)                     /*!< Sampling time 239.5 ADC clock cycles */
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
+  * @{
+  */ 
+#define ADC_ANALOGWATCHDOG_NONE                 ( 0x00000000U)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR1_AWDEN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Event_type ADC Event type
+  * @{
+  */
+#define ADC_AWD_EVENT              ((uint32_t)ADC_FLAG_AWD)  /*!< ADC Analog watchdog 1 event */
+#define ADC_OVR_EVENT              ((uint32_t)ADC_FLAG_OVR)  /*!< ADC overrun event */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+  * @{
+  */
+#define ADC_IT_AWD           ADC_IER_AWDIE      /*!< ADC Analog watchdog interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOSEQIE    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
+/**
+  * @}
+  */ 
+    
+/** @defgroup ADC_flags_definition ADC flags definition
+  * @{
+  */
+#define ADC_FLAG_AWD           ADC_ISR_AWD      /*!< ADC Analog watchdog flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOSEQ    /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
+  * @{
+  */
+
+/* List of external triggers of regular group for ADC1:                       */
+/* (used internally by HAL driver. To not use into HAL structure parameters)  */
+#define ADC1_2_EXTERNALTRIG_T1_TRGO           (0x00000000U)
+#define ADC1_2_EXTERNALTRIG_T1_CC4            ((uint32_t)ADC_CFGR1_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T2_TRGO           ((uint32_t)ADC_CFGR1_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T3_TRGO           ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO          ((uint32_t)ADC_CFGR1_EXTSEL_2)
+/**
+  * @}
+  */ 
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL    (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/**
+  * @brief Enable the ADC peripheral
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE(__HANDLE__)                                           \
+  ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
+
+/**
+  * @brief Disable the ADC peripheral
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
+  do{                                                                          \
+      (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                              \
+      __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY));     \
+  } while(0)
+
+/**
+  * @brief Enable the ADC end of conversion interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+  *            @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+  *            @arg ADC_IT_OVR: ADC overrun interrupt source
+  *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+  *            @arg ADC_IT_RDY: ADC Ready interrupt source
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable the ADC end of conversion interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+  *            @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+  *            @arg ADC_IT_OVR: ADC overrun interrupt source
+  *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+  *            @arg ADC_IT_RDY: ADC Ready interrupt source
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC interrupt source to check
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+  *            @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+  *            @arg ADC_IT_OVR: ADC overrun interrupt source
+  *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+  *            @arg ADC_IT_RDY: ADC Ready interrupt source
+  * @retval State ofinterruption (SET or RESET)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+    
+/**
+  * @brief Get the selected ADC's flag status.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+  *            @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+  *            @arg ADC_FLAG_OVR: ADC overrun flag
+  *            @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+  *            @arg ADC_FLAG_RDY: ADC Ready flag
+  * @retval None
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear the ADC's pending flags
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+  *            @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+  *            @arg ADC_FLAG_OVR: ADC overrun flag
+  *            @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+  *            @arg ADC_FLAG_RDY: ADC Ready flag
+  * @retval None
+  */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/** @brief  Reset ADC handle state
+  * @param  __HANDLE__ ADC handle
+  * @retval None
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                \
+     (__HANDLE__)->MspInitCallback = NULL;                                     \
+     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
+    } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
+
+/**
+  * @}
+  */
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+
+/**
+  * @brief Verification of hardware constraints before ADC can be enabled
+  * @param __HANDLE__ ADC handle
+  * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+  */
+#define ADC_ENABLING_CONDITIONS(__HANDLE__)                                        \
+  (( ( ((__HANDLE__)->Instance->CR) &                                              \
+       (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \
+      ) == RESET                                                                   \
+   ) ? SET : RESET)
+
+/**
+  * @brief Verification of hardware constraints before ADC can be disabled
+  * @param __HANDLE__ ADC handle
+  * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+  */
+#define ADC_DISABLING_CONDITIONS(__HANDLE__)                                   \
+  (( ( ((__HANDLE__)->Instance->CR) &                                          \
+       (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN                          \
+   ) ? SET : RESET)
+
+/**
+  * @brief Verification of ADC state: enabled or disabled
+  * @param __HANDLE__ ADC handle
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are   */
+/*       performed automatically by hardware and flag ADC_FLAG_RDY is not     */
+/*       set.                                                                 */
+#define ADC_IS_ENABLE(__HANDLE__)                                                       \
+  (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) &&  \
+     (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)          ||      \
+      ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF)  )     \
+   ) ? SET : RESET)
+
+/**
+  * @brief Test if conversion trigger of regular group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
+  (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
+
+/**
+  * @brief Check if no conversion on going on regular group
+  * @param __HANDLE__ ADC handle
+  * @retval SET (conversion is on going) or RESET (no conversion is on going)
+  */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
+  (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET                  \
+  ) ? RESET : SET)
+
+/**
+  * @brief Returns resolution bits in CFGR1 register: RES[1:0].
+  *        Returned value is among parameters to @ref ADC_Resolution.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__)                                         \
+  (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
+
+/**
+  * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
+  *        Returned value is among parameters to @ref ADC_Resolution.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_GET_SAMPLINGTIME(__HANDLE__)                                       \
+  (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
+
+/**
+  * @brief Simultaneously clears and sets specific bits of the handle State
+  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Clear ADC error code (set it to error code: "no error")
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
+  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+
+/**
+  * @brief Configure the channel number into channel selection register
+  * @param _CHANNEL_ ADC Channel
+  * @retval None
+  */
+/* This function converts ADC channels from numbers (see defgroup ADC_channels) 
+   to bitfields, to get the equivalence of CMSIS channels:
+        ADC_CHANNEL_0           ((uint32_t) ADC_CHSELR_CHSEL0)
+        ADC_CHANNEL_1           ((uint32_t) ADC_CHSELR_CHSEL1)
+        ADC_CHANNEL_2           ((uint32_t) ADC_CHSELR_CHSEL2)
+        ADC_CHANNEL_3           ((uint32_t) ADC_CHSELR_CHSEL3)
+        ADC_CHANNEL_4           ((uint32_t) ADC_CHSELR_CHSEL4)
+        ADC_CHANNEL_5           ((uint32_t) ADC_CHSELR_CHSEL5)
+        ADC_CHANNEL_6           ((uint32_t) ADC_CHSELR_CHSEL6)
+        ADC_CHANNEL_7           ((uint32_t) ADC_CHSELR_CHSEL7)
+        ADC_CHANNEL_8           ((uint32_t) ADC_CHSELR_CHSEL8)
+        ADC_CHANNEL_9           ((uint32_t) ADC_CHSELR_CHSEL9)
+        ADC_CHANNEL_10          ((uint32_t) ADC_CHSELR_CHSEL10)
+        ADC_CHANNEL_11          ((uint32_t) ADC_CHSELR_CHSEL11)
+        ADC_CHANNEL_12          ((uint32_t) ADC_CHSELR_CHSEL12)
+        ADC_CHANNEL_13          ((uint32_t) ADC_CHSELR_CHSEL13)
+        ADC_CHANNEL_14          ((uint32_t) ADC_CHSELR_CHSEL14)
+        ADC_CHANNEL_15          ((uint32_t) ADC_CHSELR_CHSEL15)
+        ADC_CHANNEL_16          ((uint32_t) ADC_CHSELR_CHSEL16)
+        ADC_CHANNEL_17          ((uint32_t) ADC_CHSELR_CHSEL17)
+        ADC_CHANNEL_18          ((uint32_t) ADC_CHSELR_CHSEL18)
+*/
+#define ADC_CHSELR_CHANNEL(_CHANNEL_)                                          \
+  ( 1U << (_CHANNEL_))       
+
+/**
+  * @brief Set the ADC's sample time
+  * @param _SAMPLETIME_ Sample time parameter.
+  * @retval None
+  */
+/* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter       */
+/*       "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to      */
+/*       distinguish this parameter versus reset value 0x00000000,            */
+/*       in the context of management of parameters "SamplingTimeCommon"      */
+/*       and "SamplingTime" (obsolete)).                                      */
+#define ADC_SMPR_SET(_SAMPLETIME_)                                             \
+  ((_SAMPLETIME_) & (ADC_SMPR_SMP))
+
+/**
+  * @brief Set the Analog Watchdog 1 channel.
+  * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
+  * @retval None
+  */
+#define ADC_CFGR_AWDCH(_CHANNEL_)                                              \
+  ((_CHANNEL_) << 26U)
+
+/**
+  * @brief Enable ADC discontinuous conversion mode for regular group
+  * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_)                 \
+  ((_REG_DISCONTINUOUS_MODE_) << 16U)
+  
+/**
+  * @brief Enable the ADC auto off mode.
+  * @param _AUTOOFF_ Auto off bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR1_AUTOOFF(_AUTOOFF_)                                           \
+  ((_AUTOOFF_) << 15U)
+      
+/**
+  * @brief Enable the ADC auto delay mode.
+  * @param _AUTOWAIT_ Auto delay bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_)                                         \
+  ((_AUTOWAIT_) << 14U)
+
+/**
+  * @brief Enable ADC continuous conversion mode.
+  * @param _CONTINUOUS_MODE_ Continuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_)                                \
+  ((_CONTINUOUS_MODE_) << 13U)
+    
+/**
+  * @brief Enable ADC overrun mode.
+  * @param _OVERRUN_MODE_ Overrun mode.
+  * @retval Overun bit setting to be programmed into CFGR register
+  */
+/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant                   */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it    */
+/* as the default case to be compliant with other STM32 devices.              */
+#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)                                      \
+  ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED)                             \
+    )? (ADC_CFGR1_OVRMOD) : (0x00000000)                                       \
+  )
+
+/**
+  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+  * @param _SCAN_MODE_ Scan conversion mode.
+  * @retval None
+  */
+/* Note: Scan mode set using this macro (instead of parameter direct set)     */
+/*       due to different modes on other STM32 devices: to avoid any          */
+/*       unwanted setting, the exact parameter corresponding to the device    */
+/*       must be passed to this macro.                                        */
+#define ADC_SCANDIR(_SCAN_MODE_)                                               \
+  ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD)                           \
+    )? (ADC_CFGR1_SCANDIR) : (0x00000000)                                      \
+  )
+
+/**
+  * @brief Enable the ADC DMA continuous request.
+  * @param _DMACONTREQ_MODE_ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_)                                \
+  ((_DMACONTREQ_MODE_) << 1U)
+
+/**
+  * @brief Configure the analog watchdog high threshold into register TR.
+  * @param _Threshold_ Threshold value
+  * @retval None
+  */
+#define ADC_TRX_HIGHTHRESHOLD(_Threshold_)                                     \
+  ((_Threshold_) << 16U) 
+  
+/**
+  * @brief Shift the AWD threshold in function of the selected ADC resolution.
+  *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+  * @param __HANDLE__ ADC handle
+  * @param _Threshold_ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
+  ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2))
+
+          
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1)     || \
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4)   )
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_6B)    )
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
+                                     ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD)  )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
+                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)  )
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
+                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
+
+#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
+                               ((WATCHDOG) == ADC_RANK_NONE)             )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
+                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
+                                  ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
+                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
+                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)            )
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+                                  ((EVENT) == ADC_OVR_EVENT)   )
+
+/** @defgroup ADC_range_verification ADC range verification
+  * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+  * @{
+  */ 
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                         \
+   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= (0x00FFU))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= (0x003FU)))   )
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_rank_verification ADC regular rank verification
+  * @{
+  */ 
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U)))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */   
+
+/* Include ADC HAL Extension module */
+#include "stm32f0xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @{
+  */
+
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void              HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void              HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @{
+  */
+
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADC_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+  * @}
+  */
+
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F0xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h b/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h
new file mode 100644
index 0000000..96e74cc
--- /dev/null
+++ b/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h
@@ -0,0 +1,299 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_ADC_EX_H
+#define __STM32F0xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"  
+
+/** @addtogroup STM32F0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_CCR_ALL     (ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN)
+#else
+#define ADC_CCR_ALL     (ADC_CCR_TSEN | ADC_CCR_VREFEN)
+#endif
+
+/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
+  * @{
+  */
+/* List of external triggers with generic trigger name, sorted by trigger     */
+/* name:                                                                      */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_CC4         ADC1_2_EXTERNALTRIG_T1_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_SOFTWARE_START                  (ADC_CFGR1_EXTSEL + 1U)
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_2_EXTERNALTRIG_T2_TRGO
+#endif 
+
+#if !defined(STM32F030x6) && !defined(STM32F070x6) && !defined(STM32F042x6)
+#define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_2_EXTERNALTRIG_T15_TRGO
+#endif
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_channels ADC channels
+  * @{
+  */
+/* Note: Depending on devices, some channels may not be available on package  */
+/*       pins. Refer to device datasheet for channels availability.           */
+/* Note: Channels are used by bitfields for setting of channel selection      */
+/*       (register ADC_CHSELR) and used by number for setting of analog       */
+/*       watchdog channel (bits AWDCH in register ADC_CFGR1).                 */
+/*       Channels are defined with decimal numbers and converted them to      */
+/*       bitfields when needed.                                               */
+#define ADC_CHANNEL_0           ( 0x00000000U)
+#define ADC_CHANNEL_1           ( 0x00000001U)
+#define ADC_CHANNEL_2           ( 0x00000002U)
+#define ADC_CHANNEL_3           ( 0x00000003U)
+#define ADC_CHANNEL_4           ( 0x00000004U)
+#define ADC_CHANNEL_5           ( 0x00000005U)
+#define ADC_CHANNEL_6           ( 0x00000006U)
+#define ADC_CHANNEL_7           ( 0x00000007U)
+#define ADC_CHANNEL_8           ( 0x00000008U)
+#define ADC_CHANNEL_9           ( 0x00000009U)
+#define ADC_CHANNEL_10          ( 0x0000000AU)
+#define ADC_CHANNEL_11          ( 0x0000000BU)
+#define ADC_CHANNEL_12          ( 0x0000000CU)
+#define ADC_CHANNEL_13          ( 0x0000000DU)
+#define ADC_CHANNEL_14          ( 0x0000000EU)
+#define ADC_CHANNEL_15          ( 0x0000000FU)
+#define ADC_CHANNEL_16          ( 0x00000010U)
+#define ADC_CHANNEL_17          ( 0x00000011U)
+
+#define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16
+#define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17
+    
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_CHANNEL_18          ( 0x00000012U)
+#define ADC_CHANNEL_VBAT        ADC_CHANNEL_18 
+#endif
+    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+    
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macros ADCEx Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Test if the selected ADC channel is an internal channel
+  *        VrefInt/TempSensor/Vbat
+  *        Note: On STM32F0, availability of internal channel Vbat depends on
+  *              devices lines.
+  * @param __CHANNEL__ ADC channel
+  * @retval None
+  */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                                   \
+ (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) ||                                 \
+  ((__CHANNEL__) == ADC_CHANNEL_VREFINT)    ||                                 \
+  ((__CHANNEL__) == ADC_CHANNEL_VBAT)                                          \
+ )
+#else
+#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                                   \
+ (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) ||                                 \
+  ((__CHANNEL__) == ADC_CHANNEL_VREFINT)                                       \
+ )
+#endif
+   
+/**
+  * @brief Select the internal measurement path to be enabled/disabled 
+  *        corresponding to the selected ADC internal channel 
+  *        VrefInt/TempSensor/Vbat.
+  *        Note: On STM32F0, availability of internal channel Vbat depends on
+  *              devices lines.
+  * @param __CHANNEL__ ADC channel
+  * @retval Bit of register ADC_CCR
+  */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__)                                 \
+ (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR                                    \
+  )?                                                                           \
+   (ADC_CCR_TSEN)                                                              \
+   :                                                                           \
+   (                                                                           \
+     ( (__CHANNEL__) == ADC_CHANNEL_VREFINT                                    \
+     )?                                                                        \
+      (ADC_CCR_VREFEN)                                                         \
+      :                                                                        \
+      (ADC_CCR_VBATEN)                                                         \
+   )                                                                           \
+ )
+#else
+#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__)                                 \
+ (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR                                    \
+  )?                                                                           \
+   (ADC_CCR_TSEN)                                                              \
+   :                                                                           \
+   (ADC_CCR_VREFEN)                                                            \
+ )
+#endif
+   
+   
+#if defined (STM32F030x6) || defined (STM32F070x6)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
+                                 ((REGTRIG) == ADC_SOFTWARE_START))
+#elif defined (STM32F042x6)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
+                                 ((REGTRIG) == ADC_SOFTWARE_START))   
+
+#elif defined (STM32F030xC) || defined (STM32F070xB) || defined (STM32F030x8)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+                                 ((REGTRIG) == ADC_SOFTWARE_START))
+#else
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+                                 ((REGTRIG) == ADC_SOFTWARE_START))   
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
+                                 ((CHANNEL) == ADC_CHANNEL_VBAT)          )
+#else
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)       )
+#endif
+
+/**
+  * @}
+  */ 
+
+   
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* ADC calibration */
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c b/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
new file mode 100644
index 0000000..3bcf1c1
--- /dev/null
+++ b/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
@@ -0,0 +1,2497 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *             ++ Initialization and Configuration of ADC
+  *           + Operation functions
+  *             ++ Start, stop, get result of conversions of regular
+  *                group, using 3 possible modes: polling, interruption or DMA.
+  *           + Control functions
+  *             ++ Channels configuration on regular group
+  *             ++ Analog Watchdog configuration
+  *           + State functions
+  *             ++ ADC state machine management
+  *             ++ Interrupts and flags management
+  *          Other functions (extended functions) are available in file 
+  *          "stm32f0xx_hal_adc_ex.c".
+  *
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
+
+  (+) Interrupt generation at the end of regular conversion and in case of 
+      analog watchdog or overrun events.
+  
+  (+) Single and continuous conversion modes.
+  
+  (+) Scan mode for conversion of several channels sequentially.
+  
+  (+) Data alignment with in-built data coherency.
+  
+  (+) Programmable sampling time (common for all channels)
+  
+  (+) ADC conversion of regular group.
+
+  (+) External trigger (timer or EXTI) with configurable polarity
+
+  (+) DMA request generation for transfer of conversions data of regular group.
+
+  (+) ADC calibration
+  
+  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
+      slower speed.
+  
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+      (++) As prerequisite, ADC clock must be configured at RCC top level.
+           Caution: On STM32F0, ADC clock frequency max is 14MHz (refer
+                    to device datasheet).
+                    Therefore, ADC clock prescaler must be configured in 
+                    function of ADC clock source frequency to remain below
+                    this maximum frequency.
+
+        (++) Two clock settings are mandatory: 
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Two possible clock sources: synchronous clock derived from APB clock
+                   or asynchronous clock derived from ADC dedicated HSI RC oscillator
+                   14MHz.
+                   If asynchronous clock is selected, parameter "HSI14State" must be set either:
+                   - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control 
+                     the HSI14 oscillator enable/disable (if not used to supply the main 
+                     system clock): feature used if ADC mode LowPowerAutoPowerOff is 
+                     enabled.
+                   - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
+                     always enabled: can be used to supply the main system clock.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC1_CLK_ENABLE();                         (mandatory)
+
+               HI14 enable or let under control of ADC:           (optional: if asynchronous clock selected)
+               (+++) RCC_OscInitTypeDef   RCC_OscInitStructure;
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+               (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
+               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
+               (+++) RCC_OscInitStructure.PLL...   (optional if used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
+              into the function of corresponding ADC interruption vector 
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
+              into the function of corresponding DMA interruption vector 
+              DMAx_Channelx_IRQHandler().
+  
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number, 
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion 
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results 
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption: 
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results 
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_DeInit().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+     or HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+  
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+  /* Fixed timeout values for ADC calibration, enable settling time, disable  */
+  /* settling time.                                                           */
+  /* Values defined to be higher than worst cases: low clock frequency,       */
+  /* maximum prescaler.                                                       */
+  /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
+  /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits.     */
+  /* Unit: ms                                                                 */
+  #define ADC_ENABLE_TIMEOUT             ( 2U)
+  #define ADC_DISABLE_TIMEOUT            ( 2U)
+  #define ADC_STOP_CONVERSION_TIMEOUT    ( 2U)
+
+  /* Delay for ADC stabilization time.                                        */
+  /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
+  /* Unit: us                                                                 */
+  #define ADC_STAB_DELAY_US               ( 1U)
+
+  /* Delay for temperature sensor stabilization time.                         */
+  /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
+  /* Unit: us                                                                 */
+  #define ADC_TEMPSENSOR_DELAY_US         ( 10U)
+
+/**
+    * @}
+    */
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+    * @}
+    */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC. 
+      (+) De-initialize the ADC
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the ADC peripheral and regular group according to  
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         depending on both possible clock sources: APB clock of HSI clock.
+  *         See commented example code below that can be copied and uncommented 
+  *         into HAL_ADC_MspInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef  
+  *         structure on the fly, without modifying MSP configuration. If ADC  
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire 
+  *         ADC and scope of regular group. For parameters details, see comments 
+  *         of structure "ADC_InitTypeDef".
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpCFGR1 = 0U;
+
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));   
+  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));   
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+  
+  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
+  /* at RCC top level depending on both possible clock sources:               */
+  /* APB clock or HSI clock.                                                  */
+  /* Refer to header of this file for more details on clock enabling procedure*/
+  
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  /* - ADC voltage regulator enable                                           */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+  {
+    /* Initialize ADC error code */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Allocate lock resource and initialize it */
+    hadc->Lock = HAL_UNLOCKED;
+    
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+    
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  /* and if there is no conversion on going on regular group (ADC can be      */ 
+  /* enabled anyway, in case of call of this function to update a parameter   */
+  /* on the fly).                                                             */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+      (tmp_hal_status == HAL_OK)                                &&
+      (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)          )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - ADC clock mode                                                      */
+    /*  - ADC clock prescaler                                                 */
+    /*  - ADC resolution                                                      */
+    if (ADC_IS_ENABLE(hadc) == RESET)
+    {
+      /* Some parameters of this register are not reset, since they are set   */
+      /* by other functions and must be kept in case of usage of this         */
+      /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+      /* without needing to reconfigure all other ADC groups/channels         */
+      /* parameters):                                                         */
+      /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+      /*     (set into HAL_ADC_ConfigChannel() )                              */
+     
+      /* Configuration of ADC resolution                                      */
+      MODIFY_REG(hadc->Instance->CFGR1,
+                 ADC_CFGR1_RES        ,
+                 hadc->Init.Resolution );
+      
+      /* Configuration of ADC clock mode: clock source AHB or HSI with        */
+      /* selectable prescaler                                                 */
+      MODIFY_REG(hadc->Instance->CFGR2    ,
+                 ADC_CFGR2_CKMODE         ,
+                 hadc->Init.ClockPrescaler );
+    }
+      
+    /* Configuration of ADC:                                                  */
+    /*  - discontinuous mode                                                  */
+    /*  - LowPowerAutoWait mode                                               */
+    /*  - LowPowerAutoPowerOff mode                                           */
+    /*  - continuous conversion mode                                          */
+    /*  - overrun                                                             */
+    /*  - external trigger to start conversion                                */
+    /*  - external trigger polarity                                           */
+    /*  - data alignment                                                      */
+    /*  - resolution                                                          */
+    /*  - scan direction                                                      */
+    /*  - DMA continuous request                                              */
+    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN  |
+                                ADC_CFGR1_AUTOFF  |
+                                ADC_CFGR1_AUTDLY  |
+                                ADC_CFGR1_CONT    |
+                                ADC_CFGR1_OVRMOD  |
+                                ADC_CFGR1_EXTSEL  |
+                                ADC_CFGR1_EXTEN   |
+                                ADC_CFGR1_ALIGN   |
+                                ADC_CFGR1_SCANDIR |
+                                ADC_CFGR1_DMACFG   );
+
+    tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+                 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)     |
+                 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)    |
+                 ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                            |
+                 hadc->Init.DataAlign                                             |
+                 ADC_SCANDIR(hadc->Init.ScanConvMode)                             |
+                 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)  );
+    
+    /* Enable discontinuous mode only if continuous mode is disabled */
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      if (hadc->Init.ContinuousConvMode == DISABLE)
+      {
+        /* Enable the selected ADC group regular discontinuous mode */
+        tmpCFGR1 |= ADC_CFGR1_DISCEN;
+      }
+      else
+      {
+        /* ADC regular group discontinuous was intended to be enabled,        */
+        /* but ADC regular group modes continuous and sequencer discontinuous */
+        /* cannot be enabled simultaneously.                                  */
+        
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      }
+    }
+    
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /* Note: This configuration keeps the hardware feature of parameter       */
+    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+    /*       software start.                                                  */
+    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+    {
+      tmpCFGR1 |= ( hadc->Init.ExternalTrigConv    |
+                    hadc->Init.ExternalTrigConvEdge );
+    }
+    
+    /* Update ADC configuration register with previous settings */
+    hadc->Instance->CFGR1 |= tmpCFGR1;
+    
+    /* Channel sampling time configuration */
+    /* Management of parameters "SamplingTimeCommon" and "SamplingTime"       */
+    /* (obsolete): sampling time set in this function if parameter            */
+    /*  "SamplingTimeCommon" has been set to a valid sampling time.           */
+    /* Otherwise, sampling time is set into ADC channel initialization        */
+    /* structure with parameter "SamplingTime" (obsolete).                    */
+    if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+    {
+      /* Channel sampling time configuration */
+      /* Clear the old sample time */
+      hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+      
+      /* Set the new sample time */
+      hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
+    }
+    
+    /* Check back that ADC registers have effectively been configured to      */
+    /* ensure of no potential problem of ADC core IP clocking.                */
+    /* Check through register CFGR1 (excluding analog watchdog configuration: */
+    /* set into separate dedicated function, and bits of ADC resolution set   */
+    /* out of temporary variable 'tmpCFGR1').                                 */
+    if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
+         == tmpCFGR1)
+    {
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Set the ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_BUSY_INTERNAL,
+                        HAL_ADC_STATE_READY);
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_BUSY_INTERNAL,
+                        HAL_ADC_STATE_ERROR_INTERNAL);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      tmp_hal_status = HAL_ERROR;
+    }
+  
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.
+  * @note   For devices with several ADCs: reset of ADC common registers is done 
+  *         only if all ADCs sharing the same common group are disabled.
+  *         If this is not the case, reset of these common parameters reset is  
+  *         bypassed without error reporting: it can be the intended behaviour in
+  *         case of reset of a single ADC while the other ADCs sharing the same 
+  *         common group is still running.
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+  
+  /* Stop potential conversion on going, on regular group */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {   
+    /* Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status != HAL_ERROR)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_READY;
+    }
+  }
+  
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  if (tmp_hal_status != HAL_ERROR)
+  {
+  
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD   | ADC_IT_OVR  |
+                                ADC_IT_EOS   | ADC_IT_EOC  |
+                                ADC_IT_EOSMP | ADC_IT_RDY   ) );
+        
+    /* Reset register ISR */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD   | ADC_FLAG_OVR  |
+                                ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+                                ADC_FLAG_EOSMP | ADC_FLAG_RDY   ) );
+      
+    /* Reset register CR */
+    /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
+    /* "read-set": no direct reset applicable.                                */
+
+    /* Reset register CFGR1 */
+    hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH   | ADC_CFGR1_AWDEN  | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN |
+                               ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD |     
+                               ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN  | ADC_CFGR1_RES    |
+                               ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN                      );
+    
+    /* Reset register CFGR2 */
+    /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
+    /*       already done above.                                              */
+    hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+    
+    /* Reset register SMPR */
+    hadc->Instance->SMPR &= ~ADC_SMPR_SMP;
+    
+    /* Reset register TR1 */
+    hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT);
+    
+    /* Reset register CHSELR */
+    hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 |
+                                ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 |
+                                ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8  |
+                                ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4  |
+                                ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0   );
+    
+    /* Reset register DR */
+    /* bits in access mode read only, no direct reset applicable*/
+    
+    /* Reset register CCR */
+    ADC->CCR &= ~(ADC_CCR_ALL);
+
+    /* ========== Hard reset ADC peripheral ========== */
+    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
+    /* forced to a similar state after device power-on.                       */
+    /* If needed, copy-paste and uncomment the following reset code into      */
+    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
+    /*                                                                        */
+    /*  __HAL_RCC_ADC1_FORCE_RESET()                                                  */
+    /*  __HAL_RCC_ADC1_RELEASE_RESET()                                                */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    if (hadc->MspDeInitCallback == NULL)
+    {
+      hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+    }
+    
+    /* DeInit the low level hardware */
+    hadc->MspDeInitCallback(hadc);
+#else
+    /* DeInit the low level hardware */
+    HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Set ADC state */
+    hadc->State = HAL_ADC_STATE_RESET; 
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+    
+/**
+  * @brief  Initializes the ADC MSP.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the ADC MSP.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */ 
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+      
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+      
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+      
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+      
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+      
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+      
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+      
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+      
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+      
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+    
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+      
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+      
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+      
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+      
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+      
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+      
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+        
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+        
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+        
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+        
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+    
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+  
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables ADC, starts conversion of regular group.
+  *         Interruptions enabled in this function: None.
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+      
+    /* Enable the ADC peripheral */
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
+    /* performed automatically by hardware.                                   */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      tmp_hal_status = ADC_Enable(hadc);
+    }
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      hadc->Instance->CR |= ADC_CR_ADSTART;
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group, disable ADC peripheral.
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{ 
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on regular group */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function, with an exception:
+  *         if low power feature "LowPowerAutoWait" is enabled, flags are 
+  *         not cleared to not interfere with this feature until data register
+  *         is read using function HAL_ADC_GetValue().
+  * @note   This function cannot be used in a particular setup: ADC configured 
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still 
+  *         be performed on the complete sequence (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+  * @param  hadc ADC handle
+  * @param  Timeout Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_EOC;
+ 
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of conversion selected to end of sequence */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_EOC = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of each conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Verification that ADC configuration is compliant with polling for      */
+    /* each conversion:                                                       */
+    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+    /* several ranks and polling for end of each conversion.                  */
+    /* For code simplicity sake, this particular case is generalized to       */
+    /* ADC configured in DMA mode and and polling for end of each conversion. */
+    if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+      
+      return HAL_ERROR;
+    }
+    else
+    {
+      tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+    }
+  }
+  
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+  
+  /* Wait until End of Conversion flag is raised */
+  while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+    
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+  
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+     (hadc->Init.ContinuousConvMode == DISABLE)   )
+  {
+    /* If End of Sequence is reached, disable interrupts */
+    if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+    {
+      /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit             */
+      /* ADSTART==0 (no conversion on going)                                  */
+      if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+      {
+        /* Disable ADC end of single conversion interrupt on group regular */
+        /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+        /* HAL_Start_IT(), but is not disabled here because can be used       */
+        /* by overrun IRQ process below.                                      */
+        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+        
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+      else
+      {
+        /* Change ADC state to error state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      }
+    }
+  }
+  
+  /* Clear end of conversion flag of regular group if low power feature       */
+  /* "LowPowerAutoWait " is disabled, to not interfere with this feature      */
+  /* until data register is read using function HAL_ADC_GetValue().           */
+  if (hadc->Init.LowPowerAutoWait == DISABLE)
+  {
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for conversion event.
+  * @param  hadc ADC handle
+  * @param  EventType the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AWD_EVENT: ADC Analog watchdog event
+  *            @arg ADC_OVR_EVENT: ADC Overrun event
+  * @param  Timeout Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart=0; 
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+  
+  /* Get tick count */
+  tickstart = HAL_GetTick();   
+      
+  /* Check selected event flag */
+  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  switch(EventType)
+  {
+  /* Analog watchdog (level out of window) event */
+  case ADC_AWD_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+      
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+    break;
+  
+  /* Overrun event */
+  default: /* Case ADC_OVR_EVENT */
+    /* If overrun is set to overwrite previous data, overrun event is not     */
+    /* considered as an error.                                                */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+        
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+    }
+    
+    /* Clear ADC Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+    break;
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables ADC, starts conversion of regular group with interruption.
+  *         Interruptions enabled in this function:
+  *          - EOC (end of conversion of regular group) or EOS (end of 
+  *            sequence of regular group) depending on ADC initialization 
+  *            parameter "EOCSelection"
+  *          - overrun (if available)
+  *         Each of these interruptions has its dedicated callback function.
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+    
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+     
+    /* Enable the ADC peripheral */
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
+    /* performed automatically by hardware.                                   */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      tmp_hal_status = ADC_Enable(hadc);
+    }
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable ADC end of conversion interrupt */
+      /* Enable ADC overrun interrupt */  
+      switch(hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV: 
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+          __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+          break;
+      }
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      hadc->Instance->CR |= ADC_CR_ADSTART;
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }    
+    
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Stop ADC conversion of regular group, disable interruption of 
+  *         end-of-conversion, disable ADC peripheral.
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on regular group */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+   
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+    
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enables ADC, starts conversion of regular group and transfers result
+  *         through DMA.
+  *         Interruptions enabled in this function:
+  *          - DMA transfer complete
+  *          - DMA half transfer
+  *          - overrun
+  *         Each of these interruptions has its dedicated callback function.
+  * @param  hadc ADC handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are       */
+    /* performed automatically by hardware.                                     */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      tmp_hal_status = ADC_Enable(hadc);
+    }
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+      
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+      
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
+      /* start (in case of SW start):                                         */
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+      
+      /* Enable ADC DMA mode */
+      hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+      
+      /* Start the DMA channel */
+      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+           
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      hadc->Instance->CR |= ADC_CR_ADSTART;
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+    
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group, disable ADC DMA transfer, disable 
+  *         ADC peripheral.
+  *         Each of these interruptions has its dedicated callback function.
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{  
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on regular group */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+    hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* while DMA transfer is on going)                                        */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);   
+      
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status != HAL_OK)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep  */
+    /* in memory a potential failing status.                                  */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+    
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS 
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function: 
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion() 
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param  hadc ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+  
+  /* Return ADC converted value */ 
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Handles ADC interrupt request.  
+  * @param  hadc ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  
+  /* ========== Check End of Conversion flag for regular group ========== */
+  if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || 
+      (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS))   )
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
+    }
+    
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going.        */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+       (hadc->Init.ContinuousConvMode == DISABLE)   )
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+          
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+          
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    }
+    
+    /* Note: into callback, to determine if conversion has been triggered     */
+    /*       from EOC or EOS, possibility to use:                             */
+    /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    
+    /* Clear regular group conversion flag */
+    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+    /*       conversion flags clear induces the release of the preserved data.*/
+    /*       Therefore, if the preserved data value is needed, it must be     */
+    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
+  }
+   
+  /* ========== Check Analog watchdog flags ========== */
+  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+  {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->LevelOutOfWindowCallback(hadc);
+#else
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    
+    /* Clear ADC Analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+   
+  }
+  
+  
+  /* ========== Check Overrun flag ========== */
+  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)            ||
+        HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)  )
+    {
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      
+      /* Clear ADC overrun flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+      
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    
+    /* Clear the Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+
+}
+
+
+/**
+  * @brief  Conversion complete callback in non blocking mode 
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non blocking mode 
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog callback in non blocking mode. 
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non blocking mode
+  *        (ADC conversion with interruption or transfer by DMA)
+  * @param  hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the the selected channel to be linked to the regular
+  *         group.
+  * @note   In case of usage of internal measurement channels:
+  *         VrefInt/Vbat/TempSensor.
+  *         Sampling time constraints must be respected (sampling time can be 
+  *         adjusted in function of ADC clock frequency and sampling time 
+  *         setting).
+  *         Refer to device datasheet for timings values, parameters TS_vrefint,
+  *         TS_vbat, TS_temp (values rough order: 5us to 17us).
+  *         These internal paths can be be disabled using function 
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into regular group, following  
+  *         calls to this function can be used to reconfigure some parameters 
+  *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting 
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_ChannelConfTypeDef".
+  * @param  hadc ADC handle
+  * @param  sConfig Structure of ADC channel for regular group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  __IO uint32_t wait_loop_index = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_RANK(sConfig->Rank));
+  
+  if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+  {
+    assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel sampling time                                                 */
+  /*  - Management of internal measurement channels: VrefInt/TempSensor/Vbat  */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Configure channel: depending on rank setting, add it or remove it from */
+    /* ADC conversion sequencer.                                              */
+    if (sConfig->Rank != ADC_RANK_NONE)
+    {
+      /* Regular sequence configuration */
+      /* Set the channel selection register from the selected channel */
+      hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
+      
+      /* Channel sampling time configuration */
+      /* Management of parameters "SamplingTimeCommon" and "SamplingTime"     */
+      /* (obsolete): sampling time set in this function with                  */
+      /* parameter "SamplingTime" (obsolete) only if not already set into     */
+      /* ADC initialization structure with parameter "SamplingTimeCommon".    */
+      if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+      {
+        /* Modify sampling time if needed (not needed in case of reoccurrence */
+        /* for several channels programmed consecutively into the sequencer)  */
+        if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
+        {
+          /* Channel sampling time configuration */
+          /* Clear the old sample time */
+          hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+          
+          /* Set the new sample time */
+          hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
+        }
+      }
+      
+      /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+      /* internal measurement paths enable: If internal channel selected,     */
+      /* enable dedicated internal buffers and path.                          */
+      /* Note: these internal measurement paths can be disabled using         */
+      /*       HAL_ADC_DeInit() or removing the channel from sequencer with   */
+      /*       channel configuration parameter "Rank".                        */
+      if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+      {
+        /* If Channel_16 is selected, enable Temp. sensor measurement path. */
+        /* If Channel_17 is selected, enable VREFINT measurement path. */
+        /* If Channel_18 is selected, enable VBAT measurement path. */
+        ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
+        
+        /* If Temp. sensor is selected, wait for stabilization delay */
+        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+        {
+          /* Delay for temperature sensor stabilization time */
+          /* Compute number of CPU cycles to wait for */
+          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+          while(wait_loop_index != 0U)
+          {
+            wait_loop_index--;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Regular sequence configuration */
+      /* Reset the channel selection register from the selected channel */
+      hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
+      
+      /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+      /* internal measurement paths disable: If internal channel selected,    */
+      /* disable dedicated internal buffers and path.                         */
+      if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+      {
+        /* If Channel_16 is selected, disable Temp. sensor measurement path. */
+        /* If Channel_17 is selected, disable VREFINT measurement path. */
+        /* If Channel_18 is selected, disable VBAT measurement path. */
+        ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
+      }
+    }
+    
+  }
+   
+  /* If a conversion is on going on regular group, no update on regular       */
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Configures the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, following  
+  *         calls to this function can be used to reconfigure some parameters 
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting 
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @param  hadc ADC handle
+  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  uint32_t tmpAWDHighThresholdShifted;
+  uint32_t tmpAWDLowThresholdShifted;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+  /* Verify if threshold is within the selected ADC resolution */
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+
+  if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+  {
+    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Analog watchdog channels                                              */
+  /*  - Analog watchdog thresholds                                            */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Configuration of analog watchdog:                                      */
+    /*  - Set the analog watchdog enable mode: one or overall group of        */
+    /*    channels.                                                           */
+    /*  - Set the Analog watchdog channel (is not used if watchdog            */
+    /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                           */
+    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
+                                ADC_CFGR1_AWDEN  |
+                                ADC_CFGR1_AWDCH   );
+    
+    hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode            |
+                               ADC_CFGR_AWDCH(AnalogWDGConfig->Channel)  );
+
+    /* Shift the offset in function of the selected ADC resolution: Thresholds*/
+    /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0   */
+    tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+    tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+    
+    /* Set the high and low thresholds */
+    hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT);
+    hadc->Instance->TR |=  ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
+                             tmpAWDLowThresholdShifted                           );
+    
+    /* Clear the ADC Analog watchdog flag (in case of left enabled by         */
+    /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler()   */
+    /* or HAL_ADC_PollForEvent().                                             */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD);
+    
+    /* Configure ADC Analog watchdog interrupt */
+    if(AnalogWDGConfig->ITMode == ENABLE)
+    {
+      /* Enable the ADC Analog watchdog interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+    }
+    else
+    {
+      /* Disable the ADC Analog watchdog interrupt */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+    }
+    
+  }
+  /* If a conversion is on going on regular group, no update could be done    */
+  /* on neither of the AWD configuration structure parameters.                */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ *  @brief    Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions to get in run-time the status of the  
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC state
+  * @note   ADC state machine is managed by bitfields, ADC status must be 
+  *         compared with states bits.
+  *         For example:                                                         
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
+  * @param  hadc ADC handle
+  * @retval HAL state
+  */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Return ADC state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code
+  * @param  hadc ADC handle
+  * @retval ADC Error Code
+  */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @note   If low power mode AutoPowerOff is enabled, power-on/off phases are
+  *         performed automatically by hardware.
+  *         In this mode, this function is useless and must not be called because 
+  *         flag ADC_FLAG_RDY is not usable.
+  *         Therefore, this function must be called under condition of
+  *         "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0U;
+  __IO uint32_t wait_loop_index = 0U;
+  
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      return HAL_ERROR;
+    }
+    
+    /* Enable the ADC peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(wait_loop_index != 0U)
+    {
+      wait_loop_index--;
+    }
+
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+    
+    /* Wait for ADC effectively enabled */
+    while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+   
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0U;
+  
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if (ADC_IS_ENABLE(hadc) != RESET)
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
+    {
+      /* Disable the ADC peripheral */
+      __HAL_ADC_DISABLE(hadc);
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      return HAL_ERROR;
+    }
+     
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+    
+    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+    {
+      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Stop ADC conversion.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped to disable the ADC.
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+    
+  /* Verification if ADC is not already stopped on regular group to bypass    */
+  /* this function if not needed.                                             */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
+  {
+    
+    /* Stop potential conversion on going on regular group */
+    /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+    if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 
+        HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)                  )
+    {
+      /* Stop conversions on regular group */
+      hadc->Instance->CR |= ADC_CR_ADSTP;
+    }
+    
+    /* Wait for conversion effectively stopped */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+      
+    while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+   
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
+    
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going.        */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+       (hadc->Init.ContinuousConvMode == DISABLE)   )
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+          
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+          
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
+  }
+
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc); 
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+  
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+  
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc); 
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c b/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
new file mode 100644
index 0000000..4f914be
--- /dev/null
+++ b/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
@@ -0,0 +1,192 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          peripheral:
+  *           + Operation functions
+  *             ++ Calibration (ADC automatic self-calibration)
+  *          Other functions (generic functions) are available in file 
+  *          "stm32f0xx_hal_adc.c".
+  *
+  @verbatim
+  [..] 
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32l1xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
+  * @{
+  */ 
+ 
+/* Fixed timeout values for ADC calibration, enable settling time, disable  */
+  /* settling time.                                                           */
+  /* Values defined to be higher than worst cases: low clock frequency,       */
+  /* maximum prescaler.                                                       */
+  /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
+  /* prescaler 4.                                                             */
+  /* Unit: ms                                                                 */
+  #define ADC_DISABLE_TIMEOUT           2
+  #define ADC_CALIBRATION_TIMEOUT       2U      
+/**
+  * @}
+  */
+
+/* Private macros -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions 
+ *  @brief    Extended Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Perform the ADC calibration. 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @note   Calibration factor can be read after calibration, using function
+  *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
+  * @param  hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tickstart = 0U;
+  uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Calibration prerequisite: ADC must be disabled. */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State, 
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Disable ADC DMA transfer request during calibration */
+    /* Note: Specificity of this STM32 serie: Calibration factor is           */
+    /*       available in data register and also transfered by DMA.           */
+    /*       To not insert ADC calibration factor among ADC conversion data   */
+    /*       in array variable, DMA transfer must be disabled during          */
+    /*       calibration.                                                     */
+    backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+
+    /* Start ADC calibration */
+    hadc->Instance->CR |= ADC_CR_ADCAL;
+
+    tickstart = HAL_GetTick();  
+
+    /* Wait for calibration completion */
+    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+    {
+      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+        {
+          /* Update ADC state machine to error */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_BUSY_INTERNAL,
+                            HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+    
+    /* Restore ADC DMA transfer request after calibration */
+    SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Motor_Controller.ioc b/Motor_Controller.ioc
index 22fc47c..84770a7 100644
--- a/Motor_Controller.ioc
+++ b/Motor_Controller.ioc
@@ -2,16 +2,27 @@
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32F0
-Mcu.IP0=NVIC
-Mcu.IP1=RCC
-Mcu.IP2=SYS
-Mcu.IPNb=3
+Mcu.IP0=ADC
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IPNb=4
 Mcu.Name=STM32F030F4Px
 Mcu.Package=TSSOP20
-Mcu.Pin0=PA13
-Mcu.Pin1=PA14
-Mcu.Pin2=VP_SYS_VS_Systick
-Mcu.PinsNb=3
+Mcu.Pin0=PF0-OSC_IN
+Mcu.Pin1=PF1-OSC_OUT
+Mcu.Pin10=PA13
+Mcu.Pin11=PA14
+Mcu.Pin12=VP_SYS_VS_Systick
+Mcu.Pin2=PA0
+Mcu.Pin3=PA3
+Mcu.Pin4=PA4
+Mcu.Pin5=PA5
+Mcu.Pin6=PA6
+Mcu.Pin7=PA7
+Mcu.Pin8=PA9
+Mcu.Pin9=PA10
+Mcu.PinsNb=13
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F030F4Px
@@ -23,10 +34,54 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true
+PA0.Locked=true
+PA0.Mode=IN0
+PA0.Signal=ADC_IN0
+PA10.GPIOParameters=GPIO_Label
+PA10.GPIO_Label=KEY4
+PA10.Locked=true
+PA10.Signal=GPIO_Input
 PA13.Mode=Serial_Wire
 PA13.Signal=SYS_SWDIO
 PA14.Mode=Serial_Wire
 PA14.Signal=SYS_SWCLK
+PA3.GPIOParameters=GPIO_Speed,GPIO_Label
+PA3.GPIO_Label=HC595_DCK
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA3.Locked=true
+PA3.Signal=GPIO_Output
+PA4.GPIOParameters=GPIO_Speed,GPIO_Label
+PA4.GPIO_Label=HC595_RCK
+PA4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA4.Locked=true
+PA4.Signal=GPIO_Output
+PA5.GPIOParameters=GPIO_Speed,GPIO_Label
+PA5.GPIO_Label=HC595_SCK
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA5.Locked=true
+PA5.Signal=GPIO_Output
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=KEY1
+PA6.Locked=true
+PA6.Signal=GPIO_Input
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=KEY2
+PA7.Locked=true
+PA7.Signal=GPIO_Input
+PA9.GPIOParameters=GPIO_Label
+PA9.GPIO_Label=KEY3
+PA9.Locked=true
+PA9.Signal=GPIO_Input
+PF0-OSC_IN.GPIOParameters=GPIO_Speed,GPIO_Label
+PF0-OSC_IN.GPIO_Label=MOTA
+PF0-OSC_IN.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PF0-OSC_IN.Locked=true
+PF0-OSC_IN.Signal=GPIO_Output
+PF1-OSC_OUT.GPIOParameters=GPIO_Speed,GPIO_Label
+PF1-OSC_OUT.GPIO_Label=MOTB
+PF1-OSC_OUT.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PF1-OSC_OUT.Locked=true
+PF1-OSC_OUT.Signal=GPIO_Output
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -55,7 +110,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=STM32CubeIDE
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true
 RCC.AHBFreq_Value=48000000
 RCC.APB1Freq_Value=48000000
 RCC.APB1TimFreq_Value=48000000
diff --git a/STM32F030F4PX_FLASH.ld b/STM32F030F4PX_FLASH.ld
index e8c6e5b..c3e5bf6 100644
--- a/STM32F030F4PX_FLASH.ld
+++ b/STM32F030F4PX_FLASH.ld
@@ -39,8 +39,8 @@ ENTRY(Reset_Handler)
 /* Highest address of the user mode stack */
 _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
 
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
 
 /* Memories definition */
 MEMORY