Motor_Controller.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00002564 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000058 08002624 08002624 00012624 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800267c 0800267c 00020010 2**0 CONTENTS 4 .ARM 00000000 0800267c 0800267c 00020010 2**0 CONTENTS 5 .preinit_array 00000000 0800267c 0800267c 00020010 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800267c 0800267c 0001267c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08002680 08002680 00012680 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000010 20000000 08002684 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000000ac 20000010 08002694 00020010 2**2 ALLOC 10 ._user_heap_stack 00000804 200000bc 08002694 000200bc 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00020010 2**0 CONTENTS, READONLY 12 .debug_info 00004910 00000000 00000000 00020038 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001342 00000000 00000000 00024948 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000004b0 00000000 00000000 00025c90 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 000003f8 00000000 00000000 00026140 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0000e935 00000000 00000000 00026538 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00006e34 00000000 00000000 00034e6d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00056677 00000000 00000000 0003bca1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 00092318 2**0 CONTENTS, READONLY 20 .debug_frame 00000eb8 00000000 00000000 0009236c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 20000010 .word 0x20000010 80000e0: 00000000 .word 0x00000000 80000e4: 0800260c .word 0x0800260c 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000014 .word 0x20000014 8000104: 0800260c .word 0x0800260c 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__divsi3>: 800021c: 4603 mov r3, r0 800021e: 430b orrs r3, r1 8000220: d47f bmi.n 8000322 <__divsi3+0x106> 8000222: 2200 movs r2, #0 8000224: 0843 lsrs r3, r0, #1 8000226: 428b cmp r3, r1 8000228: d374 bcc.n 8000314 <__divsi3+0xf8> 800022a: 0903 lsrs r3, r0, #4 800022c: 428b cmp r3, r1 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4> 8000230: 0a03 lsrs r3, r0, #8 8000232: 428b cmp r3, r1 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4> 8000236: 0b03 lsrs r3, r0, #12 8000238: 428b cmp r3, r1 800023a: d328 bcc.n 800028e <__divsi3+0x72> 800023c: 0c03 lsrs r3, r0, #16 800023e: 428b cmp r3, r1 8000240: d30d bcc.n 800025e <__divsi3+0x42> 8000242: 22ff movs r2, #255 ; 0xff 8000244: 0209 lsls r1, r1, #8 8000246: ba12 rev r2, r2 8000248: 0c03 lsrs r3, r0, #16 800024a: 428b cmp r3, r1 800024c: d302 bcc.n 8000254 <__divsi3+0x38> 800024e: 1212 asrs r2, r2, #8 8000250: 0209 lsls r1, r1, #8 8000252: d065 beq.n 8000320 <__divsi3+0x104> 8000254: 0b03 lsrs r3, r0, #12 8000256: 428b cmp r3, r1 8000258: d319 bcc.n 800028e <__divsi3+0x72> 800025a: e000 b.n 800025e <__divsi3+0x42> 800025c: 0a09 lsrs r1, r1, #8 800025e: 0bc3 lsrs r3, r0, #15 8000260: 428b cmp r3, r1 8000262: d301 bcc.n 8000268 <__divsi3+0x4c> 8000264: 03cb lsls r3, r1, #15 8000266: 1ac0 subs r0, r0, r3 8000268: 4152 adcs r2, r2 800026a: 0b83 lsrs r3, r0, #14 800026c: 428b cmp r3, r1 800026e: d301 bcc.n 8000274 <__divsi3+0x58> 8000270: 038b lsls r3, r1, #14 8000272: 1ac0 subs r0, r0, r3 8000274: 4152 adcs r2, r2 8000276: 0b43 lsrs r3, r0, #13 8000278: 428b cmp r3, r1 800027a: d301 bcc.n 8000280 <__divsi3+0x64> 800027c: 034b lsls r3, r1, #13 800027e: 1ac0 subs r0, r0, r3 8000280: 4152 adcs r2, r2 8000282: 0b03 lsrs r3, r0, #12 8000284: 428b cmp r3, r1 8000286: d301 bcc.n 800028c <__divsi3+0x70> 8000288: 030b lsls r3, r1, #12 800028a: 1ac0 subs r0, r0, r3 800028c: 4152 adcs r2, r2 800028e: 0ac3 lsrs r3, r0, #11 8000290: 428b cmp r3, r1 8000292: d301 bcc.n 8000298 <__divsi3+0x7c> 8000294: 02cb lsls r3, r1, #11 8000296: 1ac0 subs r0, r0, r3 8000298: 4152 adcs r2, r2 800029a: 0a83 lsrs r3, r0, #10 800029c: 428b cmp r3, r1 800029e: d301 bcc.n 80002a4 <__divsi3+0x88> 80002a0: 028b lsls r3, r1, #10 80002a2: 1ac0 subs r0, r0, r3 80002a4: 4152 adcs r2, r2 80002a6: 0a43 lsrs r3, r0, #9 80002a8: 428b cmp r3, r1 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94> 80002ac: 024b lsls r3, r1, #9 80002ae: 1ac0 subs r0, r0, r3 80002b0: 4152 adcs r2, r2 80002b2: 0a03 lsrs r3, r0, #8 80002b4: 428b cmp r3, r1 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0> 80002b8: 020b lsls r3, r1, #8 80002ba: 1ac0 subs r0, r0, r3 80002bc: 4152 adcs r2, r2 80002be: d2cd bcs.n 800025c <__divsi3+0x40> 80002c0: 09c3 lsrs r3, r0, #7 80002c2: 428b cmp r3, r1 80002c4: d301 bcc.n 80002ca <__divsi3+0xae> 80002c6: 01cb lsls r3, r1, #7 80002c8: 1ac0 subs r0, r0, r3 80002ca: 4152 adcs r2, r2 80002cc: 0983 lsrs r3, r0, #6 80002ce: 428b cmp r3, r1 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba> 80002d2: 018b lsls r3, r1, #6 80002d4: 1ac0 subs r0, r0, r3 80002d6: 4152 adcs r2, r2 80002d8: 0943 lsrs r3, r0, #5 80002da: 428b cmp r3, r1 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6> 80002de: 014b lsls r3, r1, #5 80002e0: 1ac0 subs r0, r0, r3 80002e2: 4152 adcs r2, r2 80002e4: 0903 lsrs r3, r0, #4 80002e6: 428b cmp r3, r1 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2> 80002ea: 010b lsls r3, r1, #4 80002ec: 1ac0 subs r0, r0, r3 80002ee: 4152 adcs r2, r2 80002f0: 08c3 lsrs r3, r0, #3 80002f2: 428b cmp r3, r1 80002f4: d301 bcc.n 80002fa <__divsi3+0xde> 80002f6: 00cb lsls r3, r1, #3 80002f8: 1ac0 subs r0, r0, r3 80002fa: 4152 adcs r2, r2 80002fc: 0883 lsrs r3, r0, #2 80002fe: 428b cmp r3, r1 8000300: d301 bcc.n 8000306 <__divsi3+0xea> 8000302: 008b lsls r3, r1, #2 8000304: 1ac0 subs r0, r0, r3 8000306: 4152 adcs r2, r2 8000308: 0843 lsrs r3, r0, #1 800030a: 428b cmp r3, r1 800030c: d301 bcc.n 8000312 <__divsi3+0xf6> 800030e: 004b lsls r3, r1, #1 8000310: 1ac0 subs r0, r0, r3 8000312: 4152 adcs r2, r2 8000314: 1a41 subs r1, r0, r1 8000316: d200 bcs.n 800031a <__divsi3+0xfe> 8000318: 4601 mov r1, r0 800031a: 4152 adcs r2, r2 800031c: 4610 mov r0, r2 800031e: 4770 bx lr 8000320: e05d b.n 80003de <__divsi3+0x1c2> 8000322: 0fca lsrs r2, r1, #31 8000324: d000 beq.n 8000328 <__divsi3+0x10c> 8000326: 4249 negs r1, r1 8000328: 1003 asrs r3, r0, #32 800032a: d300 bcc.n 800032e <__divsi3+0x112> 800032c: 4240 negs r0, r0 800032e: 4053 eors r3, r2 8000330: 2200 movs r2, #0 8000332: 469c mov ip, r3 8000334: 0903 lsrs r3, r0, #4 8000336: 428b cmp r3, r1 8000338: d32d bcc.n 8000396 <__divsi3+0x17a> 800033a: 0a03 lsrs r3, r0, #8 800033c: 428b cmp r3, r1 800033e: d312 bcc.n 8000366 <__divsi3+0x14a> 8000340: 22fc movs r2, #252 ; 0xfc 8000342: 0189 lsls r1, r1, #6 8000344: ba12 rev r2, r2 8000346: 0a03 lsrs r3, r0, #8 8000348: 428b cmp r3, r1 800034a: d30c bcc.n 8000366 <__divsi3+0x14a> 800034c: 0189 lsls r1, r1, #6 800034e: 1192 asrs r2, r2, #6 8000350: 428b cmp r3, r1 8000352: d308 bcc.n 8000366 <__divsi3+0x14a> 8000354: 0189 lsls r1, r1, #6 8000356: 1192 asrs r2, r2, #6 8000358: 428b cmp r3, r1 800035a: d304 bcc.n 8000366 <__divsi3+0x14a> 800035c: 0189 lsls r1, r1, #6 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba> 8000360: 1192 asrs r2, r2, #6 8000362: e000 b.n 8000366 <__divsi3+0x14a> 8000364: 0989 lsrs r1, r1, #6 8000366: 09c3 lsrs r3, r0, #7 8000368: 428b cmp r3, r1 800036a: d301 bcc.n 8000370 <__divsi3+0x154> 800036c: 01cb lsls r3, r1, #7 800036e: 1ac0 subs r0, r0, r3 8000370: 4152 adcs r2, r2 8000372: 0983 lsrs r3, r0, #6 8000374: 428b cmp r3, r1 8000376: d301 bcc.n 800037c <__divsi3+0x160> 8000378: 018b lsls r3, r1, #6 800037a: 1ac0 subs r0, r0, r3 800037c: 4152 adcs r2, r2 800037e: 0943 lsrs r3, r0, #5 8000380: 428b cmp r3, r1 8000382: d301 bcc.n 8000388 <__divsi3+0x16c> 8000384: 014b lsls r3, r1, #5 8000386: 1ac0 subs r0, r0, r3 8000388: 4152 adcs r2, r2 800038a: 0903 lsrs r3, r0, #4 800038c: 428b cmp r3, r1 800038e: d301 bcc.n 8000394 <__divsi3+0x178> 8000390: 010b lsls r3, r1, #4 8000392: 1ac0 subs r0, r0, r3 8000394: 4152 adcs r2, r2 8000396: 08c3 lsrs r3, r0, #3 8000398: 428b cmp r3, r1 800039a: d301 bcc.n 80003a0 <__divsi3+0x184> 800039c: 00cb lsls r3, r1, #3 800039e: 1ac0 subs r0, r0, r3 80003a0: 4152 adcs r2, r2 80003a2: 0883 lsrs r3, r0, #2 80003a4: 428b cmp r3, r1 80003a6: d301 bcc.n 80003ac <__divsi3+0x190> 80003a8: 008b lsls r3, r1, #2 80003aa: 1ac0 subs r0, r0, r3 80003ac: 4152 adcs r2, r2 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148> 80003b0: 0843 lsrs r3, r0, #1 80003b2: 428b cmp r3, r1 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e> 80003b6: 004b lsls r3, r1, #1 80003b8: 1ac0 subs r0, r0, r3 80003ba: 4152 adcs r2, r2 80003bc: 1a41 subs r1, r0, r1 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6> 80003c0: 4601 mov r1, r0 80003c2: 4663 mov r3, ip 80003c4: 4152 adcs r2, r2 80003c6: 105b asrs r3, r3, #1 80003c8: 4610 mov r0, r2 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4> 80003cc: 4240 negs r0, r0 80003ce: 2b00 cmp r3, #0 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8> 80003d2: 4249 negs r1, r1 80003d4: 4770 bx lr 80003d6: 4663 mov r3, ip 80003d8: 105b asrs r3, r3, #1 80003da: d300 bcc.n 80003de <__divsi3+0x1c2> 80003dc: 4240 negs r0, r0 80003de: b501 push {r0, lr} 80003e0: 2000 movs r0, #0 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0> 80003e6: bd02 pop {r1, pc} 080003e8 <__aeabi_idivmod>: 80003e8: 2900 cmp r1, #0 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2> 80003ec: e716 b.n 800021c <__divsi3> 80003ee: 4770 bx lr 080003f0 <__aeabi_idiv0>: 80003f0: 4770 bx lr 80003f2: 46c0 nop ; (mov r8, r8) 080003f4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003f4: b580 push {r7, lr} 80003f6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80003f8: f000 f9e0 bl 80007bc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80003fc: f000 f807 bl 800040e /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000400: f000 f8b2 bl 8000568 MX_ADC_Init(); 8000404: f000 f854 bl 80004b0 /* USER CODE BEGIN 2 */ mymain(); 8000408: f001 fd08 bl 8001e1c /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 800040c: e7fe b.n 800040c 0800040e : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800040e: b590 push {r4, r7, lr} 8000410: b091 sub sp, #68 ; 0x44 8000412: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000414: 2410 movs r4, #16 8000416: 193b adds r3, r7, r4 8000418: 0018 movs r0, r3 800041a: 2330 movs r3, #48 ; 0x30 800041c: 001a movs r2, r3 800041e: 2100 movs r1, #0 8000420: f002 f8ec bl 80025fc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000424: 003b movs r3, r7 8000426: 0018 movs r0, r3 8000428: 2310 movs r3, #16 800042a: 001a movs r2, r3 800042c: 2100 movs r1, #0 800042e: f002 f8e5 bl 80025fc /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14; 8000432: 0021 movs r1, r4 8000434: 187b adds r3, r7, r1 8000436: 2212 movs r2, #18 8000438: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800043a: 187b adds r3, r7, r1 800043c: 2201 movs r2, #1 800043e: 60da str r2, [r3, #12] RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 8000440: 187b adds r3, r7, r1 8000442: 2201 movs r2, #1 8000444: 615a str r2, [r3, #20] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000446: 187b adds r3, r7, r1 8000448: 2210 movs r2, #16 800044a: 611a str r2, [r3, #16] RCC_OscInitStruct.HSI14CalibrationValue = 16; 800044c: 187b adds r3, r7, r1 800044e: 2210 movs r2, #16 8000450: 619a str r2, [r3, #24] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000452: 187b adds r3, r7, r1 8000454: 2202 movs r2, #2 8000456: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8000458: 187b adds r3, r7, r1 800045a: 2200 movs r2, #0 800045c: 625a str r2, [r3, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; 800045e: 187b adds r3, r7, r1 8000460: 22a0 movs r2, #160 ; 0xa0 8000462: 0392 lsls r2, r2, #14 8000464: 629a str r2, [r3, #40] ; 0x28 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; 8000466: 187b adds r3, r7, r1 8000468: 2200 movs r2, #0 800046a: 62da str r2, [r3, #44] ; 0x2c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800046c: 187b adds r3, r7, r1 800046e: 0018 movs r0, r3 8000470: f000 fe9c bl 80011ac 8000474: 1e03 subs r3, r0, #0 8000476: d001 beq.n 800047c { Error_Handler(); 8000478: f000 f8ea bl 8000650 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800047c: 003b movs r3, r7 800047e: 2207 movs r2, #7 8000480: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000482: 003b movs r3, r7 8000484: 2202 movs r2, #2 8000486: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000488: 003b movs r3, r7 800048a: 2200 movs r2, #0 800048c: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800048e: 003b movs r3, r7 8000490: 2200 movs r2, #0 8000492: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000494: 003b movs r3, r7 8000496: 2101 movs r1, #1 8000498: 0018 movs r0, r3 800049a: f001 f9a1 bl 80017e0 800049e: 1e03 subs r3, r0, #0 80004a0: d001 beq.n 80004a6 { Error_Handler(); 80004a2: f000 f8d5 bl 8000650 } } 80004a6: 46c0 nop ; (mov r8, r8) 80004a8: 46bd mov sp, r7 80004aa: b011 add sp, #68 ; 0x44 80004ac: bd90 pop {r4, r7, pc} ... 080004b0 : * @brief ADC Initialization Function * @param None * @retval None */ static void MX_ADC_Init(void) { 80004b0: b580 push {r7, lr} 80004b2: b084 sub sp, #16 80004b4: af00 add r7, sp, #0 /* USER CODE BEGIN ADC_Init 0 */ /* USER CODE END ADC_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80004b6: 1d3b adds r3, r7, #4 80004b8: 0018 movs r0, r3 80004ba: 230c movs r3, #12 80004bc: 001a movs r2, r3 80004be: 2100 movs r1, #0 80004c0: f002 f89c bl 80025fc /* USER CODE BEGIN ADC_Init 1 */ /* USER CODE END ADC_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc.Instance = ADC1; 80004c4: 4b26 ldr r3, [pc, #152] ; (8000560 ) 80004c6: 4a27 ldr r2, [pc, #156] ; (8000564 ) 80004c8: 601a str r2, [r3, #0] hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80004ca: 4b25 ldr r3, [pc, #148] ; (8000560 ) 80004cc: 2200 movs r2, #0 80004ce: 605a str r2, [r3, #4] hadc.Init.Resolution = ADC_RESOLUTION_12B; 80004d0: 4b23 ldr r3, [pc, #140] ; (8000560 ) 80004d2: 2200 movs r2, #0 80004d4: 609a str r2, [r3, #8] hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80004d6: 4b22 ldr r3, [pc, #136] ; (8000560 ) 80004d8: 2200 movs r2, #0 80004da: 60da str r2, [r3, #12] hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 80004dc: 4b20 ldr r3, [pc, #128] ; (8000560 ) 80004de: 2201 movs r2, #1 80004e0: 611a str r2, [r3, #16] hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80004e2: 4b1f ldr r3, [pc, #124] ; (8000560 ) 80004e4: 2204 movs r2, #4 80004e6: 615a str r2, [r3, #20] hadc.Init.LowPowerAutoWait = DISABLE; 80004e8: 4b1d ldr r3, [pc, #116] ; (8000560 ) 80004ea: 2200 movs r2, #0 80004ec: 761a strb r2, [r3, #24] hadc.Init.LowPowerAutoPowerOff = DISABLE; 80004ee: 4b1c ldr r3, [pc, #112] ; (8000560 ) 80004f0: 2200 movs r2, #0 80004f2: 765a strb r2, [r3, #25] hadc.Init.ContinuousConvMode = DISABLE; 80004f4: 4b1a ldr r3, [pc, #104] ; (8000560 ) 80004f6: 2200 movs r2, #0 80004f8: 769a strb r2, [r3, #26] hadc.Init.DiscontinuousConvMode = DISABLE; 80004fa: 4b19 ldr r3, [pc, #100] ; (8000560 ) 80004fc: 2200 movs r2, #0 80004fe: 76da strb r2, [r3, #27] hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000500: 4b17 ldr r3, [pc, #92] ; (8000560 ) 8000502: 22c2 movs r2, #194 ; 0xc2 8000504: 32ff adds r2, #255 ; 0xff 8000506: 61da str r2, [r3, #28] hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 8000508: 4b15 ldr r3, [pc, #84] ; (8000560 ) 800050a: 2200 movs r2, #0 800050c: 621a str r2, [r3, #32] hadc.Init.DMAContinuousRequests = DISABLE; 800050e: 4b14 ldr r3, [pc, #80] ; (8000560 ) 8000510: 2224 movs r2, #36 ; 0x24 8000512: 2100 movs r1, #0 8000514: 5499 strb r1, [r3, r2] hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000516: 4b12 ldr r3, [pc, #72] ; (8000560 ) 8000518: 2201 movs r2, #1 800051a: 629a str r2, [r3, #40] ; 0x28 if (HAL_ADC_Init(&hadc) != HAL_OK) 800051c: 4b10 ldr r3, [pc, #64] ; (8000560 ) 800051e: 0018 movs r0, r3 8000520: f000 f9b0 bl 8000884 8000524: 1e03 subs r3, r0, #0 8000526: d001 beq.n 800052c { Error_Handler(); 8000528: f000 f892 bl 8000650 } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_0; 800052c: 1d3b adds r3, r7, #4 800052e: 2200 movs r2, #0 8000530: 601a str r2, [r3, #0] sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 8000532: 1d3b adds r3, r7, #4 8000534: 2280 movs r2, #128 ; 0x80 8000536: 0152 lsls r2, r2, #5 8000538: 605a str r2, [r3, #4] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800053a: 1d3b adds r3, r7, #4 800053c: 2280 movs r2, #128 ; 0x80 800053e: 0552 lsls r2, r2, #21 8000540: 609a str r2, [r3, #8] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000542: 1d3a adds r2, r7, #4 8000544: 4b06 ldr r3, [pc, #24] ; (8000560 ) 8000546: 0011 movs r1, r2 8000548: 0018 movs r0, r3 800054a: f000 fadb bl 8000b04 800054e: 1e03 subs r3, r0, #0 8000550: d001 beq.n 8000556 { Error_Handler(); 8000552: f000 f87d bl 8000650 } /* USER CODE BEGIN ADC_Init 2 */ /* USER CODE END ADC_Init 2 */ } 8000556: 46c0 nop ; (mov r8, r8) 8000558: 46bd mov sp, r7 800055a: b004 add sp, #16 800055c: bd80 pop {r7, pc} 800055e: 46c0 nop ; (mov r8, r8) 8000560: 20000030 .word 0x20000030 8000564: 40012400 .word 0x40012400 08000568 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000568: b590 push {r4, r7, lr} 800056a: b089 sub sp, #36 ; 0x24 800056c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800056e: 240c movs r4, #12 8000570: 193b adds r3, r7, r4 8000572: 0018 movs r0, r3 8000574: 2314 movs r3, #20 8000576: 001a movs r2, r3 8000578: 2100 movs r1, #0 800057a: f002 f83f bl 80025fc /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 800057e: 4b32 ldr r3, [pc, #200] ; (8000648 ) 8000580: 695a ldr r2, [r3, #20] 8000582: 4b31 ldr r3, [pc, #196] ; (8000648 ) 8000584: 2180 movs r1, #128 ; 0x80 8000586: 03c9 lsls r1, r1, #15 8000588: 430a orrs r2, r1 800058a: 615a str r2, [r3, #20] 800058c: 4b2e ldr r3, [pc, #184] ; (8000648 ) 800058e: 695a ldr r2, [r3, #20] 8000590: 2380 movs r3, #128 ; 0x80 8000592: 03db lsls r3, r3, #15 8000594: 4013 ands r3, r2 8000596: 60bb str r3, [r7, #8] 8000598: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 800059a: 4b2b ldr r3, [pc, #172] ; (8000648 ) 800059c: 695a ldr r2, [r3, #20] 800059e: 4b2a ldr r3, [pc, #168] ; (8000648 ) 80005a0: 2180 movs r1, #128 ; 0x80 80005a2: 0289 lsls r1, r1, #10 80005a4: 430a orrs r2, r1 80005a6: 615a str r2, [r3, #20] 80005a8: 4b27 ldr r3, [pc, #156] ; (8000648 ) 80005aa: 695a ldr r2, [r3, #20] 80005ac: 2380 movs r3, #128 ; 0x80 80005ae: 029b lsls r3, r3, #10 80005b0: 4013 ands r3, r2 80005b2: 607b str r3, [r7, #4] 80005b4: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET); 80005b6: 4b25 ldr r3, [pc, #148] ; (800064c ) 80005b8: 2200 movs r2, #0 80005ba: 2103 movs r1, #3 80005bc: 0018 movs r0, r3 80005be: f000 fdd8 bl 8001172 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET); 80005c2: 2390 movs r3, #144 ; 0x90 80005c4: 05db lsls r3, r3, #23 80005c6: 2200 movs r2, #0 80005c8: 2138 movs r1, #56 ; 0x38 80005ca: 0018 movs r0, r3 80005cc: f000 fdd1 bl 8001172 /*Configure GPIO pins : MOTA_Pin MOTB_Pin */ GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin; 80005d0: 193b adds r3, r7, r4 80005d2: 2203 movs r2, #3 80005d4: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80005d6: 193b adds r3, r7, r4 80005d8: 2201 movs r2, #1 80005da: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80005dc: 193b adds r3, r7, r4 80005de: 2200 movs r2, #0 80005e0: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80005e2: 193b adds r3, r7, r4 80005e4: 2203 movs r2, #3 80005e6: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 80005e8: 193b adds r3, r7, r4 80005ea: 4a18 ldr r2, [pc, #96] ; (800064c ) 80005ec: 0019 movs r1, r3 80005ee: 0010 movs r0, r2 80005f0: f000 fc32 bl 8000e58 /*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */ GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin; 80005f4: 193b adds r3, r7, r4 80005f6: 2238 movs r2, #56 ; 0x38 80005f8: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80005fa: 193b adds r3, r7, r4 80005fc: 2201 movs r2, #1 80005fe: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 8000600: 193b adds r3, r7, r4 8000602: 2202 movs r2, #2 8000604: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000606: 193b adds r3, r7, r4 8000608: 2203 movs r2, #3 800060a: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800060c: 193a adds r2, r7, r4 800060e: 2390 movs r3, #144 ; 0x90 8000610: 05db lsls r3, r3, #23 8000612: 0011 movs r1, r2 8000614: 0018 movs r0, r3 8000616: f000 fc1f bl 8000e58 /*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */ GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin; 800061a: 0021 movs r1, r4 800061c: 187b adds r3, r7, r1 800061e: 22d8 movs r2, #216 ; 0xd8 8000620: 00d2 lsls r2, r2, #3 8000622: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000624: 187b adds r3, r7, r1 8000626: 2200 movs r2, #0 8000628: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800062a: 187b adds r3, r7, r1 800062c: 2202 movs r2, #2 800062e: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000630: 187a adds r2, r7, r1 8000632: 2390 movs r3, #144 ; 0x90 8000634: 05db lsls r3, r3, #23 8000636: 0011 movs r1, r2 8000638: 0018 movs r0, r3 800063a: f000 fc0d bl 8000e58 } 800063e: 46c0 nop ; (mov r8, r8) 8000640: 46bd mov sp, r7 8000642: b009 add sp, #36 ; 0x24 8000644: bd90 pop {r4, r7, pc} 8000646: 46c0 nop ; (mov r8, r8) 8000648: 40021000 .word 0x40021000 800064c: 48001400 .word 0x48001400 08000650 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000650: b580 push {r7, lr} 8000652: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000654: b672 cpsid i } 8000656: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000658: e7fe b.n 8000658 ... 0800065c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800065c: b580 push {r7, lr} 800065e: b082 sub sp, #8 8000660: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000662: 4b0f ldr r3, [pc, #60] ; (80006a0 ) 8000664: 699a ldr r2, [r3, #24] 8000666: 4b0e ldr r3, [pc, #56] ; (80006a0 ) 8000668: 2101 movs r1, #1 800066a: 430a orrs r2, r1 800066c: 619a str r2, [r3, #24] 800066e: 4b0c ldr r3, [pc, #48] ; (80006a0 ) 8000670: 699b ldr r3, [r3, #24] 8000672: 2201 movs r2, #1 8000674: 4013 ands r3, r2 8000676: 607b str r3, [r7, #4] 8000678: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 800067a: 4b09 ldr r3, [pc, #36] ; (80006a0 ) 800067c: 69da ldr r2, [r3, #28] 800067e: 4b08 ldr r3, [pc, #32] ; (80006a0 ) 8000680: 2180 movs r1, #128 ; 0x80 8000682: 0549 lsls r1, r1, #21 8000684: 430a orrs r2, r1 8000686: 61da str r2, [r3, #28] 8000688: 4b05 ldr r3, [pc, #20] ; (80006a0 ) 800068a: 69da ldr r2, [r3, #28] 800068c: 2380 movs r3, #128 ; 0x80 800068e: 055b lsls r3, r3, #21 8000690: 4013 ands r3, r2 8000692: 603b str r3, [r7, #0] 8000694: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000696: 46c0 nop ; (mov r8, r8) 8000698: 46bd mov sp, r7 800069a: b002 add sp, #8 800069c: bd80 pop {r7, pc} 800069e: 46c0 nop ; (mov r8, r8) 80006a0: 40021000 .word 0x40021000 080006a4 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 80006a4: b590 push {r4, r7, lr} 80006a6: b08b sub sp, #44 ; 0x2c 80006a8: af00 add r7, sp, #0 80006aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80006ac: 2414 movs r4, #20 80006ae: 193b adds r3, r7, r4 80006b0: 0018 movs r0, r3 80006b2: 2314 movs r3, #20 80006b4: 001a movs r2, r3 80006b6: 2100 movs r1, #0 80006b8: f001 ffa0 bl 80025fc if(hadc->Instance==ADC1) 80006bc: 687b ldr r3, [r7, #4] 80006be: 681b ldr r3, [r3, #0] 80006c0: 4a19 ldr r2, [pc, #100] ; (8000728 ) 80006c2: 4293 cmp r3, r2 80006c4: d12b bne.n 800071e { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80006c6: 4b19 ldr r3, [pc, #100] ; (800072c ) 80006c8: 699a ldr r2, [r3, #24] 80006ca: 4b18 ldr r3, [pc, #96] ; (800072c ) 80006cc: 2180 movs r1, #128 ; 0x80 80006ce: 0089 lsls r1, r1, #2 80006d0: 430a orrs r2, r1 80006d2: 619a str r2, [r3, #24] 80006d4: 4b15 ldr r3, [pc, #84] ; (800072c ) 80006d6: 699a ldr r2, [r3, #24] 80006d8: 2380 movs r3, #128 ; 0x80 80006da: 009b lsls r3, r3, #2 80006dc: 4013 ands r3, r2 80006de: 613b str r3, [r7, #16] 80006e0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80006e2: 4b12 ldr r3, [pc, #72] ; (800072c ) 80006e4: 695a ldr r2, [r3, #20] 80006e6: 4b11 ldr r3, [pc, #68] ; (800072c ) 80006e8: 2180 movs r1, #128 ; 0x80 80006ea: 0289 lsls r1, r1, #10 80006ec: 430a orrs r2, r1 80006ee: 615a str r2, [r3, #20] 80006f0: 4b0e ldr r3, [pc, #56] ; (800072c ) 80006f2: 695a ldr r2, [r3, #20] 80006f4: 2380 movs r3, #128 ; 0x80 80006f6: 029b lsls r3, r3, #10 80006f8: 4013 ands r3, r2 80006fa: 60fb str r3, [r7, #12] 80006fc: 68fb ldr r3, [r7, #12] /**ADC GPIO Configuration PA0 ------> ADC_IN0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; 80006fe: 193b adds r3, r7, r4 8000700: 2201 movs r2, #1 8000702: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000704: 193b adds r3, r7, r4 8000706: 2203 movs r2, #3 8000708: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 800070a: 193b adds r3, r7, r4 800070c: 2200 movs r2, #0 800070e: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000710: 193a adds r2, r7, r4 8000712: 2390 movs r3, #144 ; 0x90 8000714: 05db lsls r3, r3, #23 8000716: 0011 movs r1, r2 8000718: 0018 movs r0, r3 800071a: f000 fb9d bl 8000e58 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 800071e: 46c0 nop ; (mov r8, r8) 8000720: 46bd mov sp, r7 8000722: b00b add sp, #44 ; 0x2c 8000724: bd90 pop {r4, r7, pc} 8000726: 46c0 nop ; (mov r8, r8) 8000728: 40012400 .word 0x40012400 800072c: 40021000 .word 0x40021000 08000730 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000730: b580 push {r7, lr} 8000732: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000734: e7fe b.n 8000734 08000736 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000736: b580 push {r7, lr} 8000738: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800073a: e7fe b.n 800073a 0800073c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 8000740: 46c0 nop ; (mov r8, r8) 8000742: 46bd mov sp, r7 8000744: bd80 pop {r7, pc} 08000746 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000746: b580 push {r7, lr} 8000748: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800074a: 46c0 nop ; (mov r8, r8) 800074c: 46bd mov sp, r7 800074e: bd80 pop {r7, pc} 08000750 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000750: b580 push {r7, lr} 8000752: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000754: f000 f87a bl 800084c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000758: 46c0 nop ; (mov r8, r8) 800075a: 46bd mov sp, r7 800075c: bd80 pop {r7, pc} 0800075e : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 800075e: b580 push {r7, lr} 8000760: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 8000762: 46c0 nop ; (mov r8, r8) 8000764: 46bd mov sp, r7 8000766: bd80 pop {r7, pc} 08000768 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000768: 480d ldr r0, [pc, #52] ; (80007a0 ) mov sp, r0 /* set stack pointer */ 800076a: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800076c: 480d ldr r0, [pc, #52] ; (80007a4 ) ldr r1, =_edata 800076e: 490e ldr r1, [pc, #56] ; (80007a8 ) ldr r2, =_sidata 8000770: 4a0e ldr r2, [pc, #56] ; (80007ac ) movs r3, #0 8000772: 2300 movs r3, #0 b LoopCopyDataInit 8000774: e002 b.n 800077c 08000776 : CopyDataInit: ldr r4, [r2, r3] 8000776: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000778: 50c4 str r4, [r0, r3] adds r3, r3, #4 800077a: 3304 adds r3, #4 0800077c : LoopCopyDataInit: adds r4, r0, r3 800077c: 18c4 adds r4, r0, r3 cmp r4, r1 800077e: 428c cmp r4, r1 bcc CopyDataInit 8000780: d3f9 bcc.n 8000776 /* Zero fill the bss segment. */ ldr r2, =_sbss 8000782: 4a0b ldr r2, [pc, #44] ; (80007b0 ) ldr r4, =_ebss 8000784: 4c0b ldr r4, [pc, #44] ; (80007b4 ) movs r3, #0 8000786: 2300 movs r3, #0 b LoopFillZerobss 8000788: e001 b.n 800078e 0800078a : FillZerobss: str r3, [r2] 800078a: 6013 str r3, [r2, #0] adds r2, r2, #4 800078c: 3204 adds r2, #4 0800078e : LoopFillZerobss: cmp r2, r4 800078e: 42a2 cmp r2, r4 bcc FillZerobss 8000790: d3fb bcc.n 800078a /* Call the clock system intitialization function.*/ bl SystemInit 8000792: f7ff ffe4 bl 800075e /* Call static constructors */ bl __libc_init_array 8000796: f001 ff0d bl 80025b4 <__libc_init_array> /* Call the application's entry point.*/ bl main 800079a: f7ff fe2b bl 80003f4
0800079e : LoopForever: b LoopForever 800079e: e7fe b.n 800079e ldr r0, =_estack 80007a0: 20001000 .word 0x20001000 ldr r0, =_sdata 80007a4: 20000000 .word 0x20000000 ldr r1, =_edata 80007a8: 20000010 .word 0x20000010 ldr r2, =_sidata 80007ac: 08002684 .word 0x08002684 ldr r2, =_sbss 80007b0: 20000010 .word 0x20000010 ldr r4, =_ebss 80007b4: 200000bc .word 0x200000bc 080007b8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80007b8: e7fe b.n 80007b8 ... 080007bc : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80007bc: b580 push {r7, lr} 80007be: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80007c0: 4b07 ldr r3, [pc, #28] ; (80007e0 ) 80007c2: 681a ldr r2, [r3, #0] 80007c4: 4b06 ldr r3, [pc, #24] ; (80007e0 ) 80007c6: 2110 movs r1, #16 80007c8: 430a orrs r2, r1 80007ca: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80007cc: 2003 movs r0, #3 80007ce: f000 f809 bl 80007e4 /* Init the low level hardware */ HAL_MspInit(); 80007d2: f7ff ff43 bl 800065c /* Return function status */ return HAL_OK; 80007d6: 2300 movs r3, #0 } 80007d8: 0018 movs r0, r3 80007da: 46bd mov sp, r7 80007dc: bd80 pop {r7, pc} 80007de: 46c0 nop ; (mov r8, r8) 80007e0: 40022000 .word 0x40022000 080007e4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80007e4: b590 push {r4, r7, lr} 80007e6: b083 sub sp, #12 80007e8: af00 add r7, sp, #0 80007ea: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80007ec: 4b14 ldr r3, [pc, #80] ; (8000840 ) 80007ee: 681c ldr r4, [r3, #0] 80007f0: 4b14 ldr r3, [pc, #80] ; (8000844 ) 80007f2: 781b ldrb r3, [r3, #0] 80007f4: 0019 movs r1, r3 80007f6: 23fa movs r3, #250 ; 0xfa 80007f8: 0098 lsls r0, r3, #2 80007fa: f7ff fc85 bl 8000108 <__udivsi3> 80007fe: 0003 movs r3, r0 8000800: 0019 movs r1, r3 8000802: 0020 movs r0, r4 8000804: f7ff fc80 bl 8000108 <__udivsi3> 8000808: 0003 movs r3, r0 800080a: 0018 movs r0, r3 800080c: f000 fb17 bl 8000e3e 8000810: 1e03 subs r3, r0, #0 8000812: d001 beq.n 8000818 { return HAL_ERROR; 8000814: 2301 movs r3, #1 8000816: e00f b.n 8000838 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000818: 687b ldr r3, [r7, #4] 800081a: 2b03 cmp r3, #3 800081c: d80b bhi.n 8000836 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800081e: 6879 ldr r1, [r7, #4] 8000820: 2301 movs r3, #1 8000822: 425b negs r3, r3 8000824: 2200 movs r2, #0 8000826: 0018 movs r0, r3 8000828: f000 faf4 bl 8000e14 uwTickPrio = TickPriority; 800082c: 4b06 ldr r3, [pc, #24] ; (8000848 ) 800082e: 687a ldr r2, [r7, #4] 8000830: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000832: 2300 movs r3, #0 8000834: e000 b.n 8000838 return HAL_ERROR; 8000836: 2301 movs r3, #1 } 8000838: 0018 movs r0, r3 800083a: 46bd mov sp, r7 800083c: b003 add sp, #12 800083e: bd90 pop {r4, r7, pc} 8000840: 20000000 .word 0x20000000 8000844: 20000008 .word 0x20000008 8000848: 20000004 .word 0x20000004 0800084c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800084c: b580 push {r7, lr} 800084e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000850: 4b05 ldr r3, [pc, #20] ; (8000868 ) 8000852: 781b ldrb r3, [r3, #0] 8000854: 001a movs r2, r3 8000856: 4b05 ldr r3, [pc, #20] ; (800086c ) 8000858: 681b ldr r3, [r3, #0] 800085a: 18d2 adds r2, r2, r3 800085c: 4b03 ldr r3, [pc, #12] ; (800086c ) 800085e: 601a str r2, [r3, #0] } 8000860: 46c0 nop ; (mov r8, r8) 8000862: 46bd mov sp, r7 8000864: bd80 pop {r7, pc} 8000866: 46c0 nop ; (mov r8, r8) 8000868: 20000008 .word 0x20000008 800086c: 20000070 .word 0x20000070 08000870 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000870: b580 push {r7, lr} 8000872: af00 add r7, sp, #0 return uwTick; 8000874: 4b02 ldr r3, [pc, #8] ; (8000880 ) 8000876: 681b ldr r3, [r3, #0] } 8000878: 0018 movs r0, r3 800087a: 46bd mov sp, r7 800087c: bd80 pop {r7, pc} 800087e: 46c0 nop ; (mov r8, r8) 8000880: 20000070 .word 0x20000070 08000884 : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8000884: b580 push {r7, lr} 8000886: b084 sub sp, #16 8000888: af00 add r7, sp, #0 800088a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800088c: 230f movs r3, #15 800088e: 18fb adds r3, r7, r3 8000890: 2200 movs r2, #0 8000892: 701a strb r2, [r3, #0] uint32_t tmpCFGR1 = 0U; 8000894: 2300 movs r3, #0 8000896: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) 8000898: 687b ldr r3, [r7, #4] 800089a: 2b00 cmp r3, #0 800089c: d101 bne.n 80008a2 { return HAL_ERROR; 800089e: 2301 movs r3, #1 80008a0: e125 b.n 8000aee /* Refer to header of this file for more details on clock enabling procedure*/ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) 80008a2: 687b ldr r3, [r7, #4] 80008a4: 6b9b ldr r3, [r3, #56] ; 0x38 80008a6: 2b00 cmp r3, #0 80008a8: d10a bne.n 80008c0 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 80008aa: 687b ldr r3, [r7, #4] 80008ac: 2200 movs r2, #0 80008ae: 63da str r2, [r3, #60] ; 0x3c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 80008b0: 687b ldr r3, [r7, #4] 80008b2: 2234 movs r2, #52 ; 0x34 80008b4: 2100 movs r1, #0 80008b6: 5499 strb r1, [r3, r2] /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80008b8: 687b ldr r3, [r7, #4] 80008ba: 0018 movs r0, r3 80008bc: f7ff fef2 bl 80006a4 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ /* and if there is no conversion on going on regular group (ADC can be */ /* enabled anyway, in case of call of this function to update a parameter */ /* on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80008c0: 687b ldr r3, [r7, #4] 80008c2: 6b9b ldr r3, [r3, #56] ; 0x38 80008c4: 2210 movs r2, #16 80008c6: 4013 ands r3, r2 80008c8: d000 beq.n 80008cc 80008ca: e103 b.n 8000ad4 80008cc: 230f movs r3, #15 80008ce: 18fb adds r3, r7, r3 80008d0: 781b ldrb r3, [r3, #0] 80008d2: 2b00 cmp r3, #0 80008d4: d000 beq.n 80008d8 80008d6: e0fd b.n 8000ad4 (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 80008d8: 687b ldr r3, [r7, #4] 80008da: 681b ldr r3, [r3, #0] 80008dc: 689b ldr r3, [r3, #8] 80008de: 2204 movs r2, #4 80008e0: 4013 ands r3, r2 (tmp_hal_status == HAL_OK) && 80008e2: d000 beq.n 80008e6 80008e4: e0f6 b.n 8000ad4 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80008e6: 687b ldr r3, [r7, #4] 80008e8: 6b9b ldr r3, [r3, #56] ; 0x38 80008ea: 4a83 ldr r2, [pc, #524] ; (8000af8 ) 80008ec: 4013 ands r3, r2 80008ee: 2202 movs r2, #2 80008f0: 431a orrs r2, r3 80008f2: 687b ldr r3, [r7, #4] 80008f4: 639a str r2, [r3, #56] ; 0x38 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - ADC clock mode */ /* - ADC clock prescaler */ /* - ADC resolution */ if (ADC_IS_ENABLE(hadc) == RESET) 80008f6: 687b ldr r3, [r7, #4] 80008f8: 681b ldr r3, [r3, #0] 80008fa: 689b ldr r3, [r3, #8] 80008fc: 2203 movs r2, #3 80008fe: 4013 ands r3, r2 8000900: 2b01 cmp r3, #1 8000902: d112 bne.n 800092a 8000904: 687b ldr r3, [r7, #4] 8000906: 681b ldr r3, [r3, #0] 8000908: 681b ldr r3, [r3, #0] 800090a: 2201 movs r2, #1 800090c: 4013 ands r3, r2 800090e: 2b01 cmp r3, #1 8000910: d009 beq.n 8000926 8000912: 687b ldr r3, [r7, #4] 8000914: 681b ldr r3, [r3, #0] 8000916: 68da ldr r2, [r3, #12] 8000918: 2380 movs r3, #128 ; 0x80 800091a: 021b lsls r3, r3, #8 800091c: 401a ands r2, r3 800091e: 2380 movs r3, #128 ; 0x80 8000920: 021b lsls r3, r3, #8 8000922: 429a cmp r2, r3 8000924: d101 bne.n 800092a 8000926: 2301 movs r3, #1 8000928: e000 b.n 800092c 800092a: 2300 movs r3, #0 800092c: 2b00 cmp r3, #0 800092e: d116 bne.n 800095e /* parameters): */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ MODIFY_REG(hadc->Instance->CFGR1, 8000930: 687b ldr r3, [r7, #4] 8000932: 681b ldr r3, [r3, #0] 8000934: 68db ldr r3, [r3, #12] 8000936: 2218 movs r2, #24 8000938: 4393 bics r3, r2 800093a: 0019 movs r1, r3 800093c: 687b ldr r3, [r7, #4] 800093e: 689a ldr r2, [r3, #8] 8000940: 687b ldr r3, [r7, #4] 8000942: 681b ldr r3, [r3, #0] 8000944: 430a orrs r2, r1 8000946: 60da str r2, [r3, #12] ADC_CFGR1_RES , hadc->Init.Resolution ); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler */ MODIFY_REG(hadc->Instance->CFGR2 , 8000948: 687b ldr r3, [r7, #4] 800094a: 681b ldr r3, [r3, #0] 800094c: 691b ldr r3, [r3, #16] 800094e: 009b lsls r3, r3, #2 8000950: 0899 lsrs r1, r3, #2 8000952: 687b ldr r3, [r7, #4] 8000954: 685a ldr r2, [r3, #4] 8000956: 687b ldr r3, [r7, #4] 8000958: 681b ldr r3, [r3, #0] 800095a: 430a orrs r2, r1 800095c: 611a str r2, [r3, #16] /* - external trigger polarity */ /* - data alignment */ /* - resolution */ /* - scan direction */ /* - DMA continuous request */ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | 800095e: 687b ldr r3, [r7, #4] 8000960: 681b ldr r3, [r3, #0] 8000962: 68da ldr r2, [r3, #12] 8000964: 687b ldr r3, [r7, #4] 8000966: 681b ldr r3, [r3, #0] 8000968: 4964 ldr r1, [pc, #400] ; (8000afc ) 800096a: 400a ands r2, r1 800096c: 60da str r2, [r3, #12] ADC_CFGR1_EXTEN | ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG ); tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800096e: 687b ldr r3, [r7, #4] 8000970: 7e1b ldrb r3, [r3, #24] 8000972: 039a lsls r2, r3, #14 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000974: 687b ldr r3, [r7, #4] 8000976: 7e5b ldrb r3, [r3, #25] 8000978: 03db lsls r3, r3, #15 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800097a: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800097c: 687b ldr r3, [r7, #4] 800097e: 7e9b ldrb r3, [r3, #26] 8000980: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000982: 431a orrs r2, r3 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000984: 687b ldr r3, [r7, #4] 8000986: 6a9b ldr r3, [r3, #40] ; 0x28 8000988: 2b01 cmp r3, #1 800098a: d002 beq.n 8000992 800098c: 2380 movs r3, #128 ; 0x80 800098e: 015b lsls r3, r3, #5 8000990: e000 b.n 8000994 8000992: 2300 movs r3, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000994: 431a orrs r2, r3 hadc->Init.DataAlign | 8000996: 687b ldr r3, [r7, #4] 8000998: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 800099a: 431a orrs r2, r3 ADC_SCANDIR(hadc->Init.ScanConvMode) | 800099c: 687b ldr r3, [r7, #4] 800099e: 691b ldr r3, [r3, #16] 80009a0: 2b02 cmp r3, #2 80009a2: d101 bne.n 80009a8 80009a4: 2304 movs r3, #4 80009a6: e000 b.n 80009aa 80009a8: 2300 movs r3, #0 hadc->Init.DataAlign | 80009aa: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); 80009ac: 687b ldr r3, [r7, #4] 80009ae: 2124 movs r1, #36 ; 0x24 80009b0: 5c5b ldrb r3, [r3, r1] 80009b2: 005b lsls r3, r3, #1 ADC_SCANDIR(hadc->Init.ScanConvMode) | 80009b4: 4313 orrs r3, r2 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 80009b6: 68ba ldr r2, [r7, #8] 80009b8: 4313 orrs r3, r2 80009ba: 60bb str r3, [r7, #8] /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80009bc: 687b ldr r3, [r7, #4] 80009be: 7edb ldrb r3, [r3, #27] 80009c0: 2b01 cmp r3, #1 80009c2: d115 bne.n 80009f0 { if (hadc->Init.ContinuousConvMode == DISABLE) 80009c4: 687b ldr r3, [r7, #4] 80009c6: 7e9b ldrb r3, [r3, #26] 80009c8: 2b00 cmp r3, #0 80009ca: d105 bne.n 80009d8 { /* Enable the selected ADC group regular discontinuous mode */ tmpCFGR1 |= ADC_CFGR1_DISCEN; 80009cc: 68bb ldr r3, [r7, #8] 80009ce: 2280 movs r2, #128 ; 0x80 80009d0: 0252 lsls r2, r2, #9 80009d2: 4313 orrs r3, r2 80009d4: 60bb str r3, [r7, #8] 80009d6: e00b b.n 80009f0 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80009d8: 687b ldr r3, [r7, #4] 80009da: 6b9b ldr r3, [r3, #56] ; 0x38 80009dc: 2220 movs r2, #32 80009de: 431a orrs r2, r3 80009e0: 687b ldr r3, [r7, #4] 80009e2: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80009e4: 687b ldr r3, [r7, #4] 80009e6: 6bdb ldr r3, [r3, #60] ; 0x3c 80009e8: 2201 movs r2, #1 80009ea: 431a orrs r2, r3 80009ec: 687b ldr r3, [r7, #4] 80009ee: 63da str r2, [r3, #60] ; 0x3c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 80009f0: 687b ldr r3, [r7, #4] 80009f2: 69da ldr r2, [r3, #28] 80009f4: 23c2 movs r3, #194 ; 0xc2 80009f6: 33ff adds r3, #255 ; 0xff 80009f8: 429a cmp r2, r3 80009fa: d007 beq.n 8000a0c { tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 80009fc: 687b ldr r3, [r7, #4] 80009fe: 69da ldr r2, [r3, #28] hadc->Init.ExternalTrigConvEdge ); 8000a00: 687b ldr r3, [r7, #4] 8000a02: 6a1b ldr r3, [r3, #32] tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000a04: 4313 orrs r3, r2 8000a06: 68ba ldr r2, [r7, #8] 8000a08: 4313 orrs r3, r2 8000a0a: 60bb str r3, [r7, #8] } /* Update ADC configuration register with previous settings */ hadc->Instance->CFGR1 |= tmpCFGR1; 8000a0c: 687b ldr r3, [r7, #4] 8000a0e: 681b ldr r3, [r3, #0] 8000a10: 68d9 ldr r1, [r3, #12] 8000a12: 687b ldr r3, [r7, #4] 8000a14: 681b ldr r3, [r3, #0] 8000a16: 68ba ldr r2, [r7, #8] 8000a18: 430a orrs r2, r1 8000a1a: 60da str r2, [r3, #12] /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function if parameter */ /* "SamplingTimeCommon" has been set to a valid sampling time. */ /* Otherwise, sampling time is set into ADC channel initialization */ /* structure with parameter "SamplingTime" (obsolete). */ if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000a1c: 687b ldr r3, [r7, #4] 8000a1e: 6ada ldr r2, [r3, #44] ; 0x2c 8000a20: 2380 movs r3, #128 ; 0x80 8000a22: 055b lsls r3, r3, #21 8000a24: 429a cmp r2, r3 8000a26: d01b beq.n 8000a60 8000a28: 687b ldr r3, [r7, #4] 8000a2a: 6adb ldr r3, [r3, #44] ; 0x2c 8000a2c: 2b01 cmp r3, #1 8000a2e: d017 beq.n 8000a60 8000a30: 687b ldr r3, [r7, #4] 8000a32: 6adb ldr r3, [r3, #44] ; 0x2c 8000a34: 2b02 cmp r3, #2 8000a36: d013 beq.n 8000a60 8000a38: 687b ldr r3, [r7, #4] 8000a3a: 6adb ldr r3, [r3, #44] ; 0x2c 8000a3c: 2b03 cmp r3, #3 8000a3e: d00f beq.n 8000a60 8000a40: 687b ldr r3, [r7, #4] 8000a42: 6adb ldr r3, [r3, #44] ; 0x2c 8000a44: 2b04 cmp r3, #4 8000a46: d00b beq.n 8000a60 8000a48: 687b ldr r3, [r7, #4] 8000a4a: 6adb ldr r3, [r3, #44] ; 0x2c 8000a4c: 2b05 cmp r3, #5 8000a4e: d007 beq.n 8000a60 8000a50: 687b ldr r3, [r7, #4] 8000a52: 6adb ldr r3, [r3, #44] ; 0x2c 8000a54: 2b06 cmp r3, #6 8000a56: d003 beq.n 8000a60 8000a58: 687b ldr r3, [r7, #4] 8000a5a: 6adb ldr r3, [r3, #44] ; 0x2c 8000a5c: 2b07 cmp r3, #7 8000a5e: d112 bne.n 8000a86 { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000a60: 687b ldr r3, [r7, #4] 8000a62: 681b ldr r3, [r3, #0] 8000a64: 695a ldr r2, [r3, #20] 8000a66: 687b ldr r3, [r7, #4] 8000a68: 681b ldr r3, [r3, #0] 8000a6a: 2107 movs r1, #7 8000a6c: 438a bics r2, r1 8000a6e: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); 8000a70: 687b ldr r3, [r7, #4] 8000a72: 681b ldr r3, [r3, #0] 8000a74: 6959 ldr r1, [r3, #20] 8000a76: 687b ldr r3, [r7, #4] 8000a78: 6adb ldr r3, [r3, #44] ; 0x2c 8000a7a: 2207 movs r2, #7 8000a7c: 401a ands r2, r3 8000a7e: 687b ldr r3, [r7, #4] 8000a80: 681b ldr r3, [r3, #0] 8000a82: 430a orrs r2, r1 8000a84: 615a str r2, [r3, #20] /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ /* set into separate dedicated function, and bits of ADC resolution set */ /* out of temporary variable 'tmpCFGR1'). */ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000a86: 687b ldr r3, [r7, #4] 8000a88: 681b ldr r3, [r3, #0] 8000a8a: 68db ldr r3, [r3, #12] 8000a8c: 4a1c ldr r2, [pc, #112] ; (8000b00 ) 8000a8e: 4013 ands r3, r2 8000a90: 68ba ldr r2, [r7, #8] 8000a92: 429a cmp r2, r3 8000a94: d10b bne.n 8000aae == tmpCFGR1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8000a96: 687b ldr r3, [r7, #4] 8000a98: 2200 movs r2, #0 8000a9a: 63da str r2, [r3, #60] ; 0x3c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000a9c: 687b ldr r3, [r7, #4] 8000a9e: 6b9b ldr r3, [r3, #56] ; 0x38 8000aa0: 2203 movs r2, #3 8000aa2: 4393 bics r3, r2 8000aa4: 2201 movs r2, #1 8000aa6: 431a orrs r2, r3 8000aa8: 687b ldr r3, [r7, #4] 8000aaa: 639a str r2, [r3, #56] ; 0x38 if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000aac: e01c b.n 8000ae8 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8000aae: 687b ldr r3, [r7, #4] 8000ab0: 6b9b ldr r3, [r3, #56] ; 0x38 8000ab2: 2212 movs r2, #18 8000ab4: 4393 bics r3, r2 8000ab6: 2210 movs r2, #16 8000ab8: 431a orrs r2, r3 8000aba: 687b ldr r3, [r7, #4] 8000abc: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000abe: 687b ldr r3, [r7, #4] 8000ac0: 6bdb ldr r3, [r3, #60] ; 0x3c 8000ac2: 2201 movs r2, #1 8000ac4: 431a orrs r2, r3 8000ac6: 687b ldr r3, [r7, #4] 8000ac8: 63da str r2, [r3, #60] ; 0x3c tmp_hal_status = HAL_ERROR; 8000aca: 230f movs r3, #15 8000acc: 18fb adds r3, r7, r3 8000ace: 2201 movs r2, #1 8000ad0: 701a strb r2, [r3, #0] if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000ad2: e009 b.n 8000ae8 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000ad4: 687b ldr r3, [r7, #4] 8000ad6: 6b9b ldr r3, [r3, #56] ; 0x38 8000ad8: 2210 movs r2, #16 8000ada: 431a orrs r2, r3 8000adc: 687b ldr r3, [r7, #4] 8000ade: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000ae0: 230f movs r3, #15 8000ae2: 18fb adds r3, r7, r3 8000ae4: 2201 movs r2, #1 8000ae6: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000ae8: 230f movs r3, #15 8000aea: 18fb adds r3, r7, r3 8000aec: 781b ldrb r3, [r3, #0] } 8000aee: 0018 movs r0, r3 8000af0: 46bd mov sp, r7 8000af2: b004 add sp, #16 8000af4: bd80 pop {r7, pc} 8000af6: 46c0 nop ; (mov r8, r8) 8000af8: fffffefd .word 0xfffffefd 8000afc: fffe0219 .word 0xfffe0219 8000b00: 833fffe7 .word 0x833fffe7 08000b04 : * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8000b04: b580 push {r7, lr} 8000b06: b084 sub sp, #16 8000b08: af00 add r7, sp, #0 8000b0a: 6078 str r0, [r7, #4] 8000b0c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000b0e: 230f movs r3, #15 8000b10: 18fb adds r3, r7, r3 8000b12: 2200 movs r2, #0 8000b14: 701a strb r2, [r3, #0] __IO uint32_t wait_loop_index = 0U; 8000b16: 2300 movs r3, #0 8000b18: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_RANK(sConfig->Rank)); if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000b1a: 687b ldr r3, [r7, #4] 8000b1c: 6ada ldr r2, [r3, #44] ; 0x2c 8000b1e: 2380 movs r3, #128 ; 0x80 8000b20: 055b lsls r3, r3, #21 8000b22: 429a cmp r2, r3 8000b24: d011 beq.n 8000b4a 8000b26: 687b ldr r3, [r7, #4] 8000b28: 6adb ldr r3, [r3, #44] ; 0x2c 8000b2a: 2b01 cmp r3, #1 8000b2c: d00d beq.n 8000b4a 8000b2e: 687b ldr r3, [r7, #4] 8000b30: 6adb ldr r3, [r3, #44] ; 0x2c 8000b32: 2b02 cmp r3, #2 8000b34: d009 beq.n 8000b4a 8000b36: 687b ldr r3, [r7, #4] 8000b38: 6adb ldr r3, [r3, #44] ; 0x2c 8000b3a: 2b03 cmp r3, #3 8000b3c: d005 beq.n 8000b4a 8000b3e: 687b ldr r3, [r7, #4] 8000b40: 6adb ldr r3, [r3, #44] ; 0x2c 8000b42: 2b04 cmp r3, #4 8000b44: d001 beq.n 8000b4a 8000b46: 687b ldr r3, [r7, #4] 8000b48: 6adb ldr r3, [r3, #44] ; 0x2c { assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); } /* Process locked */ __HAL_LOCK(hadc); 8000b4a: 687b ldr r3, [r7, #4] 8000b4c: 2234 movs r2, #52 ; 0x34 8000b4e: 5c9b ldrb r3, [r3, r2] 8000b50: 2b01 cmp r3, #1 8000b52: d101 bne.n 8000b58 8000b54: 2302 movs r3, #2 8000b56: e0bb b.n 8000cd0 8000b58: 687b ldr r3, [r7, #4] 8000b5a: 2234 movs r2, #52 ; 0x34 8000b5c: 2101 movs r1, #1 8000b5e: 5499 strb r1, [r3, r2] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000b60: 687b ldr r3, [r7, #4] 8000b62: 681b ldr r3, [r3, #0] 8000b64: 689b ldr r3, [r3, #8] 8000b66: 2204 movs r2, #4 8000b68: 4013 ands r3, r2 8000b6a: d000 beq.n 8000b6e 8000b6c: e09f b.n 8000cae { /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC conversion sequencer. */ if (sConfig->Rank != ADC_RANK_NONE) 8000b6e: 683b ldr r3, [r7, #0] 8000b70: 685b ldr r3, [r3, #4] 8000b72: 4a59 ldr r2, [pc, #356] ; (8000cd8 ) 8000b74: 4293 cmp r3, r2 8000b76: d100 bne.n 8000b7a 8000b78: e077 b.n 8000c6a { /* Regular sequence configuration */ /* Set the channel selection register from the selected channel */ hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); 8000b7a: 687b ldr r3, [r7, #4] 8000b7c: 681b ldr r3, [r3, #0] 8000b7e: 6a99 ldr r1, [r3, #40] ; 0x28 8000b80: 683b ldr r3, [r7, #0] 8000b82: 681b ldr r3, [r3, #0] 8000b84: 2201 movs r2, #1 8000b86: 409a lsls r2, r3 8000b88: 687b ldr r3, [r7, #4] 8000b8a: 681b ldr r3, [r3, #0] 8000b8c: 430a orrs r2, r1 8000b8e: 629a str r2, [r3, #40] ; 0x28 /* Channel sampling time configuration */ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function with */ /* parameter "SamplingTime" (obsolete) only if not already set into */ /* ADC initialization structure with parameter "SamplingTimeCommon". */ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000b90: 687b ldr r3, [r7, #4] 8000b92: 6ada ldr r2, [r3, #44] ; 0x2c 8000b94: 2380 movs r3, #128 ; 0x80 8000b96: 055b lsls r3, r3, #21 8000b98: 429a cmp r2, r3 8000b9a: d037 beq.n 8000c0c 8000b9c: 687b ldr r3, [r7, #4] 8000b9e: 6adb ldr r3, [r3, #44] ; 0x2c 8000ba0: 2b01 cmp r3, #1 8000ba2: d033 beq.n 8000c0c 8000ba4: 687b ldr r3, [r7, #4] 8000ba6: 6adb ldr r3, [r3, #44] ; 0x2c 8000ba8: 2b02 cmp r3, #2 8000baa: d02f beq.n 8000c0c 8000bac: 687b ldr r3, [r7, #4] 8000bae: 6adb ldr r3, [r3, #44] ; 0x2c 8000bb0: 2b03 cmp r3, #3 8000bb2: d02b beq.n 8000c0c 8000bb4: 687b ldr r3, [r7, #4] 8000bb6: 6adb ldr r3, [r3, #44] ; 0x2c 8000bb8: 2b04 cmp r3, #4 8000bba: d027 beq.n 8000c0c 8000bbc: 687b ldr r3, [r7, #4] 8000bbe: 6adb ldr r3, [r3, #44] ; 0x2c 8000bc0: 2b05 cmp r3, #5 8000bc2: d023 beq.n 8000c0c 8000bc4: 687b ldr r3, [r7, #4] 8000bc6: 6adb ldr r3, [r3, #44] ; 0x2c 8000bc8: 2b06 cmp r3, #6 8000bca: d01f beq.n 8000c0c 8000bcc: 687b ldr r3, [r7, #4] 8000bce: 6adb ldr r3, [r3, #44] ; 0x2c 8000bd0: 2b07 cmp r3, #7 8000bd2: d01b beq.n 8000c0c { /* Modify sampling time if needed (not needed in case of reoccurrence */ /* for several channels programmed consecutively into the sequencer) */ if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) 8000bd4: 683b ldr r3, [r7, #0] 8000bd6: 689a ldr r2, [r3, #8] 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 681b ldr r3, [r3, #0] 8000bdc: 695b ldr r3, [r3, #20] 8000bde: 2107 movs r1, #7 8000be0: 400b ands r3, r1 8000be2: 429a cmp r2, r3 8000be4: d012 beq.n 8000c0c { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000be6: 687b ldr r3, [r7, #4] 8000be8: 681b ldr r3, [r3, #0] 8000bea: 695a ldr r2, [r3, #20] 8000bec: 687b ldr r3, [r7, #4] 8000bee: 681b ldr r3, [r3, #0] 8000bf0: 2107 movs r1, #7 8000bf2: 438a bics r2, r1 8000bf4: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); 8000bf6: 687b ldr r3, [r7, #4] 8000bf8: 681b ldr r3, [r3, #0] 8000bfa: 6959 ldr r1, [r3, #20] 8000bfc: 683b ldr r3, [r7, #0] 8000bfe: 689b ldr r3, [r3, #8] 8000c00: 2207 movs r2, #7 8000c02: 401a ands r2, r3 8000c04: 687b ldr r3, [r7, #4] 8000c06: 681b ldr r3, [r3, #0] 8000c08: 430a orrs r2, r1 8000c0a: 615a str r2, [r3, #20] /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8000c0c: 683b ldr r3, [r7, #0] 8000c0e: 681b ldr r3, [r3, #0] 8000c10: 2b10 cmp r3, #16 8000c12: d003 beq.n 8000c1c 8000c14: 683b ldr r3, [r7, #0] 8000c16: 681b ldr r3, [r3, #0] 8000c18: 2b11 cmp r3, #17 8000c1a: d152 bne.n 8000cc2 { /* If Channel_16 is selected, enable Temp. sensor measurement path. */ /* If Channel_17 is selected, enable VREFINT measurement path. */ /* If Channel_18 is selected, enable VBAT measurement path. */ ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 8000c1c: 4b2f ldr r3, [pc, #188] ; (8000cdc ) 8000c1e: 6819 ldr r1, [r3, #0] 8000c20: 683b ldr r3, [r7, #0] 8000c22: 681b ldr r3, [r3, #0] 8000c24: 2b10 cmp r3, #16 8000c26: d102 bne.n 8000c2e 8000c28: 2380 movs r3, #128 ; 0x80 8000c2a: 041b lsls r3, r3, #16 8000c2c: e001 b.n 8000c32 8000c2e: 2380 movs r3, #128 ; 0x80 8000c30: 03db lsls r3, r3, #15 8000c32: 4a2a ldr r2, [pc, #168] ; (8000cdc ) 8000c34: 430b orrs r3, r1 8000c36: 6013 str r3, [r2, #0] /* If Temp. sensor is selected, wait for stabilization delay */ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8000c38: 683b ldr r3, [r7, #0] 8000c3a: 681b ldr r3, [r3, #0] 8000c3c: 2b10 cmp r3, #16 8000c3e: d140 bne.n 8000cc2 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8000c40: 4b27 ldr r3, [pc, #156] ; (8000ce0 ) 8000c42: 681b ldr r3, [r3, #0] 8000c44: 4927 ldr r1, [pc, #156] ; (8000ce4 ) 8000c46: 0018 movs r0, r3 8000c48: f7ff fa5e bl 8000108 <__udivsi3> 8000c4c: 0003 movs r3, r0 8000c4e: 001a movs r2, r3 8000c50: 0013 movs r3, r2 8000c52: 009b lsls r3, r3, #2 8000c54: 189b adds r3, r3, r2 8000c56: 005b lsls r3, r3, #1 8000c58: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000c5a: e002 b.n 8000c62 { wait_loop_index--; 8000c5c: 68bb ldr r3, [r7, #8] 8000c5e: 3b01 subs r3, #1 8000c60: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000c62: 68bb ldr r3, [r7, #8] 8000c64: 2b00 cmp r3, #0 8000c66: d1f9 bne.n 8000c5c 8000c68: e02b b.n 8000cc2 } else { /* Regular sequence configuration */ /* Reset the channel selection register from the selected channel */ hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); 8000c6a: 687b ldr r3, [r7, #4] 8000c6c: 681b ldr r3, [r3, #0] 8000c6e: 6a9a ldr r2, [r3, #40] ; 0x28 8000c70: 683b ldr r3, [r7, #0] 8000c72: 681b ldr r3, [r3, #0] 8000c74: 2101 movs r1, #1 8000c76: 4099 lsls r1, r3 8000c78: 000b movs r3, r1 8000c7a: 43d9 mvns r1, r3 8000c7c: 687b ldr r3, [r7, #4] 8000c7e: 681b ldr r3, [r3, #0] 8000c80: 400a ands r2, r1 8000c82: 629a str r2, [r3, #40] ; 0x28 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths disable: If internal channel selected, */ /* disable dedicated internal buffers and path. */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8000c84: 683b ldr r3, [r7, #0] 8000c86: 681b ldr r3, [r3, #0] 8000c88: 2b10 cmp r3, #16 8000c8a: d003 beq.n 8000c94 8000c8c: 683b ldr r3, [r7, #0] 8000c8e: 681b ldr r3, [r3, #0] 8000c90: 2b11 cmp r3, #17 8000c92: d116 bne.n 8000cc2 { /* If Channel_16 is selected, disable Temp. sensor measurement path. */ /* If Channel_17 is selected, disable VREFINT measurement path. */ /* If Channel_18 is selected, disable VBAT measurement path. */ ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 8000c94: 4b11 ldr r3, [pc, #68] ; (8000cdc ) 8000c96: 6819 ldr r1, [r3, #0] 8000c98: 683b ldr r3, [r7, #0] 8000c9a: 681b ldr r3, [r3, #0] 8000c9c: 2b10 cmp r3, #16 8000c9e: d101 bne.n 8000ca4 8000ca0: 4a11 ldr r2, [pc, #68] ; (8000ce8 ) 8000ca2: e000 b.n 8000ca6 8000ca4: 4a11 ldr r2, [pc, #68] ; (8000cec ) 8000ca6: 4b0d ldr r3, [pc, #52] ; (8000cdc ) 8000ca8: 400a ands r2, r1 8000caa: 601a str r2, [r3, #0] 8000cac: e009 b.n 8000cc2 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000cae: 687b ldr r3, [r7, #4] 8000cb0: 6b9b ldr r3, [r3, #56] ; 0x38 8000cb2: 2220 movs r2, #32 8000cb4: 431a orrs r2, r3 8000cb6: 687b ldr r3, [r7, #4] 8000cb8: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000cba: 230f movs r3, #15 8000cbc: 18fb adds r3, r7, r3 8000cbe: 2201 movs r2, #1 8000cc0: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000cc2: 687b ldr r3, [r7, #4] 8000cc4: 2234 movs r2, #52 ; 0x34 8000cc6: 2100 movs r1, #0 8000cc8: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 8000cca: 230f movs r3, #15 8000ccc: 18fb adds r3, r7, r3 8000cce: 781b ldrb r3, [r3, #0] } 8000cd0: 0018 movs r0, r3 8000cd2: 46bd mov sp, r7 8000cd4: b004 add sp, #16 8000cd6: bd80 pop {r7, pc} 8000cd8: 00001001 .word 0x00001001 8000cdc: 40012708 .word 0x40012708 8000ce0: 20000000 .word 0x20000000 8000ce4: 000f4240 .word 0x000f4240 8000ce8: ff7fffff .word 0xff7fffff 8000cec: ffbfffff .word 0xffbfffff 08000cf0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000cf0: b590 push {r4, r7, lr} 8000cf2: b083 sub sp, #12 8000cf4: af00 add r7, sp, #0 8000cf6: 0002 movs r2, r0 8000cf8: 6039 str r1, [r7, #0] 8000cfa: 1dfb adds r3, r7, #7 8000cfc: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8000cfe: 1dfb adds r3, r7, #7 8000d00: 781b ldrb r3, [r3, #0] 8000d02: 2b7f cmp r3, #127 ; 0x7f 8000d04: d828 bhi.n 8000d58 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000d06: 4a2f ldr r2, [pc, #188] ; (8000dc4 <__NVIC_SetPriority+0xd4>) 8000d08: 1dfb adds r3, r7, #7 8000d0a: 781b ldrb r3, [r3, #0] 8000d0c: b25b sxtb r3, r3 8000d0e: 089b lsrs r3, r3, #2 8000d10: 33c0 adds r3, #192 ; 0xc0 8000d12: 009b lsls r3, r3, #2 8000d14: 589b ldr r3, [r3, r2] 8000d16: 1dfa adds r2, r7, #7 8000d18: 7812 ldrb r2, [r2, #0] 8000d1a: 0011 movs r1, r2 8000d1c: 2203 movs r2, #3 8000d1e: 400a ands r2, r1 8000d20: 00d2 lsls r2, r2, #3 8000d22: 21ff movs r1, #255 ; 0xff 8000d24: 4091 lsls r1, r2 8000d26: 000a movs r2, r1 8000d28: 43d2 mvns r2, r2 8000d2a: 401a ands r2, r3 8000d2c: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8000d2e: 683b ldr r3, [r7, #0] 8000d30: 019b lsls r3, r3, #6 8000d32: 22ff movs r2, #255 ; 0xff 8000d34: 401a ands r2, r3 8000d36: 1dfb adds r3, r7, #7 8000d38: 781b ldrb r3, [r3, #0] 8000d3a: 0018 movs r0, r3 8000d3c: 2303 movs r3, #3 8000d3e: 4003 ands r3, r0 8000d40: 00db lsls r3, r3, #3 8000d42: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000d44: 481f ldr r0, [pc, #124] ; (8000dc4 <__NVIC_SetPriority+0xd4>) 8000d46: 1dfb adds r3, r7, #7 8000d48: 781b ldrb r3, [r3, #0] 8000d4a: b25b sxtb r3, r3 8000d4c: 089b lsrs r3, r3, #2 8000d4e: 430a orrs r2, r1 8000d50: 33c0 adds r3, #192 ; 0xc0 8000d52: 009b lsls r3, r3, #2 8000d54: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8000d56: e031 b.n 8000dbc <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000d58: 4a1b ldr r2, [pc, #108] ; (8000dc8 <__NVIC_SetPriority+0xd8>) 8000d5a: 1dfb adds r3, r7, #7 8000d5c: 781b ldrb r3, [r3, #0] 8000d5e: 0019 movs r1, r3 8000d60: 230f movs r3, #15 8000d62: 400b ands r3, r1 8000d64: 3b08 subs r3, #8 8000d66: 089b lsrs r3, r3, #2 8000d68: 3306 adds r3, #6 8000d6a: 009b lsls r3, r3, #2 8000d6c: 18d3 adds r3, r2, r3 8000d6e: 3304 adds r3, #4 8000d70: 681b ldr r3, [r3, #0] 8000d72: 1dfa adds r2, r7, #7 8000d74: 7812 ldrb r2, [r2, #0] 8000d76: 0011 movs r1, r2 8000d78: 2203 movs r2, #3 8000d7a: 400a ands r2, r1 8000d7c: 00d2 lsls r2, r2, #3 8000d7e: 21ff movs r1, #255 ; 0xff 8000d80: 4091 lsls r1, r2 8000d82: 000a movs r2, r1 8000d84: 43d2 mvns r2, r2 8000d86: 401a ands r2, r3 8000d88: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8000d8a: 683b ldr r3, [r7, #0] 8000d8c: 019b lsls r3, r3, #6 8000d8e: 22ff movs r2, #255 ; 0xff 8000d90: 401a ands r2, r3 8000d92: 1dfb adds r3, r7, #7 8000d94: 781b ldrb r3, [r3, #0] 8000d96: 0018 movs r0, r3 8000d98: 2303 movs r3, #3 8000d9a: 4003 ands r3, r0 8000d9c: 00db lsls r3, r3, #3 8000d9e: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000da0: 4809 ldr r0, [pc, #36] ; (8000dc8 <__NVIC_SetPriority+0xd8>) 8000da2: 1dfb adds r3, r7, #7 8000da4: 781b ldrb r3, [r3, #0] 8000da6: 001c movs r4, r3 8000da8: 230f movs r3, #15 8000daa: 4023 ands r3, r4 8000dac: 3b08 subs r3, #8 8000dae: 089b lsrs r3, r3, #2 8000db0: 430a orrs r2, r1 8000db2: 3306 adds r3, #6 8000db4: 009b lsls r3, r3, #2 8000db6: 18c3 adds r3, r0, r3 8000db8: 3304 adds r3, #4 8000dba: 601a str r2, [r3, #0] } 8000dbc: 46c0 nop ; (mov r8, r8) 8000dbe: 46bd mov sp, r7 8000dc0: b003 add sp, #12 8000dc2: bd90 pop {r4, r7, pc} 8000dc4: e000e100 .word 0xe000e100 8000dc8: e000ed00 .word 0xe000ed00 08000dcc : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000dcc: b580 push {r7, lr} 8000dce: b082 sub sp, #8 8000dd0: af00 add r7, sp, #0 8000dd2: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000dd4: 687b ldr r3, [r7, #4] 8000dd6: 1e5a subs r2, r3, #1 8000dd8: 2380 movs r3, #128 ; 0x80 8000dda: 045b lsls r3, r3, #17 8000ddc: 429a cmp r2, r3 8000dde: d301 bcc.n 8000de4 { return (1UL); /* Reload value impossible */ 8000de0: 2301 movs r3, #1 8000de2: e010 b.n 8000e06 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000de4: 4b0a ldr r3, [pc, #40] ; (8000e10 ) 8000de6: 687a ldr r2, [r7, #4] 8000de8: 3a01 subs r2, #1 8000dea: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000dec: 2301 movs r3, #1 8000dee: 425b negs r3, r3 8000df0: 2103 movs r1, #3 8000df2: 0018 movs r0, r3 8000df4: f7ff ff7c bl 8000cf0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000df8: 4b05 ldr r3, [pc, #20] ; (8000e10 ) 8000dfa: 2200 movs r2, #0 8000dfc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000dfe: 4b04 ldr r3, [pc, #16] ; (8000e10 ) 8000e00: 2207 movs r2, #7 8000e02: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000e04: 2300 movs r3, #0 } 8000e06: 0018 movs r0, r3 8000e08: 46bd mov sp, r7 8000e0a: b002 add sp, #8 8000e0c: bd80 pop {r7, pc} 8000e0e: 46c0 nop ; (mov r8, r8) 8000e10: e000e010 .word 0xe000e010 08000e14 : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000e14: b580 push {r7, lr} 8000e16: b084 sub sp, #16 8000e18: af00 add r7, sp, #0 8000e1a: 60b9 str r1, [r7, #8] 8000e1c: 607a str r2, [r7, #4] 8000e1e: 210f movs r1, #15 8000e20: 187b adds r3, r7, r1 8000e22: 1c02 adds r2, r0, #0 8000e24: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 8000e26: 68ba ldr r2, [r7, #8] 8000e28: 187b adds r3, r7, r1 8000e2a: 781b ldrb r3, [r3, #0] 8000e2c: b25b sxtb r3, r3 8000e2e: 0011 movs r1, r2 8000e30: 0018 movs r0, r3 8000e32: f7ff ff5d bl 8000cf0 <__NVIC_SetPriority> } 8000e36: 46c0 nop ; (mov r8, r8) 8000e38: 46bd mov sp, r7 8000e3a: b004 add sp, #16 8000e3c: bd80 pop {r7, pc} 08000e3e : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000e3e: b580 push {r7, lr} 8000e40: b082 sub sp, #8 8000e42: af00 add r7, sp, #0 8000e44: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000e46: 687b ldr r3, [r7, #4] 8000e48: 0018 movs r0, r3 8000e4a: f7ff ffbf bl 8000dcc 8000e4e: 0003 movs r3, r0 } 8000e50: 0018 movs r0, r3 8000e52: 46bd mov sp, r7 8000e54: b002 add sp, #8 8000e56: bd80 pop {r7, pc} 08000e58 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000e58: b580 push {r7, lr} 8000e5a: b086 sub sp, #24 8000e5c: af00 add r7, sp, #0 8000e5e: 6078 str r0, [r7, #4] 8000e60: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000e62: 2300 movs r3, #0 8000e64: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000e66: e14f b.n 8001108 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8000e68: 683b ldr r3, [r7, #0] 8000e6a: 681b ldr r3, [r3, #0] 8000e6c: 2101 movs r1, #1 8000e6e: 697a ldr r2, [r7, #20] 8000e70: 4091 lsls r1, r2 8000e72: 000a movs r2, r1 8000e74: 4013 ands r3, r2 8000e76: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8000e78: 68fb ldr r3, [r7, #12] 8000e7a: 2b00 cmp r3, #0 8000e7c: d100 bne.n 8000e80 8000e7e: e140 b.n 8001102 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000e80: 683b ldr r3, [r7, #0] 8000e82: 685b ldr r3, [r3, #4] 8000e84: 2203 movs r2, #3 8000e86: 4013 ands r3, r2 8000e88: 2b01 cmp r3, #1 8000e8a: d005 beq.n 8000e98 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8000e8c: 683b ldr r3, [r7, #0] 8000e8e: 685b ldr r3, [r3, #4] 8000e90: 2203 movs r2, #3 8000e92: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000e94: 2b02 cmp r3, #2 8000e96: d130 bne.n 8000efa { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8000e98: 687b ldr r3, [r7, #4] 8000e9a: 689b ldr r3, [r3, #8] 8000e9c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 8000e9e: 697b ldr r3, [r7, #20] 8000ea0: 005b lsls r3, r3, #1 8000ea2: 2203 movs r2, #3 8000ea4: 409a lsls r2, r3 8000ea6: 0013 movs r3, r2 8000ea8: 43da mvns r2, r3 8000eaa: 693b ldr r3, [r7, #16] 8000eac: 4013 ands r3, r2 8000eae: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8000eb0: 683b ldr r3, [r7, #0] 8000eb2: 68da ldr r2, [r3, #12] 8000eb4: 697b ldr r3, [r7, #20] 8000eb6: 005b lsls r3, r3, #1 8000eb8: 409a lsls r2, r3 8000eba: 0013 movs r3, r2 8000ebc: 693a ldr r2, [r7, #16] 8000ebe: 4313 orrs r3, r2 8000ec0: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8000ec2: 687b ldr r3, [r7, #4] 8000ec4: 693a ldr r2, [r7, #16] 8000ec6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 685b ldr r3, [r3, #4] 8000ecc: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8000ece: 2201 movs r2, #1 8000ed0: 697b ldr r3, [r7, #20] 8000ed2: 409a lsls r2, r3 8000ed4: 0013 movs r3, r2 8000ed6: 43da mvns r2, r3 8000ed8: 693b ldr r3, [r7, #16] 8000eda: 4013 ands r3, r2 8000edc: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8000ede: 683b ldr r3, [r7, #0] 8000ee0: 685b ldr r3, [r3, #4] 8000ee2: 091b lsrs r3, r3, #4 8000ee4: 2201 movs r2, #1 8000ee6: 401a ands r2, r3 8000ee8: 697b ldr r3, [r7, #20] 8000eea: 409a lsls r2, r3 8000eec: 0013 movs r3, r2 8000eee: 693a ldr r2, [r7, #16] 8000ef0: 4313 orrs r3, r2 8000ef2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000ef4: 687b ldr r3, [r7, #4] 8000ef6: 693a ldr r2, [r7, #16] 8000ef8: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8000efa: 683b ldr r3, [r7, #0] 8000efc: 685b ldr r3, [r3, #4] 8000efe: 2203 movs r2, #3 8000f00: 4013 ands r3, r2 8000f02: 2b03 cmp r3, #3 8000f04: d017 beq.n 8000f36 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000f06: 687b ldr r3, [r7, #4] 8000f08: 68db ldr r3, [r3, #12] 8000f0a: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 8000f0c: 697b ldr r3, [r7, #20] 8000f0e: 005b lsls r3, r3, #1 8000f10: 2203 movs r2, #3 8000f12: 409a lsls r2, r3 8000f14: 0013 movs r3, r2 8000f16: 43da mvns r2, r3 8000f18: 693b ldr r3, [r7, #16] 8000f1a: 4013 ands r3, r2 8000f1c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8000f1e: 683b ldr r3, [r7, #0] 8000f20: 689a ldr r2, [r3, #8] 8000f22: 697b ldr r3, [r7, #20] 8000f24: 005b lsls r3, r3, #1 8000f26: 409a lsls r2, r3 8000f28: 0013 movs r3, r2 8000f2a: 693a ldr r2, [r7, #16] 8000f2c: 4313 orrs r3, r2 8000f2e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000f30: 687b ldr r3, [r7, #4] 8000f32: 693a ldr r2, [r7, #16] 8000f34: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8000f36: 683b ldr r3, [r7, #0] 8000f38: 685b ldr r3, [r3, #4] 8000f3a: 2203 movs r2, #3 8000f3c: 4013 ands r3, r2 8000f3e: 2b02 cmp r3, #2 8000f40: d123 bne.n 8000f8a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8000f42: 697b ldr r3, [r7, #20] 8000f44: 08da lsrs r2, r3, #3 8000f46: 687b ldr r3, [r7, #4] 8000f48: 3208 adds r2, #8 8000f4a: 0092 lsls r2, r2, #2 8000f4c: 58d3 ldr r3, [r2, r3] 8000f4e: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8000f50: 697b ldr r3, [r7, #20] 8000f52: 2207 movs r2, #7 8000f54: 4013 ands r3, r2 8000f56: 009b lsls r3, r3, #2 8000f58: 220f movs r2, #15 8000f5a: 409a lsls r2, r3 8000f5c: 0013 movs r3, r2 8000f5e: 43da mvns r2, r3 8000f60: 693b ldr r3, [r7, #16] 8000f62: 4013 ands r3, r2 8000f64: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8000f66: 683b ldr r3, [r7, #0] 8000f68: 691a ldr r2, [r3, #16] 8000f6a: 697b ldr r3, [r7, #20] 8000f6c: 2107 movs r1, #7 8000f6e: 400b ands r3, r1 8000f70: 009b lsls r3, r3, #2 8000f72: 409a lsls r2, r3 8000f74: 0013 movs r3, r2 8000f76: 693a ldr r2, [r7, #16] 8000f78: 4313 orrs r3, r2 8000f7a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8000f7c: 697b ldr r3, [r7, #20] 8000f7e: 08da lsrs r2, r3, #3 8000f80: 687b ldr r3, [r7, #4] 8000f82: 3208 adds r2, #8 8000f84: 0092 lsls r2, r2, #2 8000f86: 6939 ldr r1, [r7, #16] 8000f88: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8000f8a: 687b ldr r3, [r7, #4] 8000f8c: 681b ldr r3, [r3, #0] 8000f8e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8000f90: 697b ldr r3, [r7, #20] 8000f92: 005b lsls r3, r3, #1 8000f94: 2203 movs r2, #3 8000f96: 409a lsls r2, r3 8000f98: 0013 movs r3, r2 8000f9a: 43da mvns r2, r3 8000f9c: 693b ldr r3, [r7, #16] 8000f9e: 4013 ands r3, r2 8000fa0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8000fa2: 683b ldr r3, [r7, #0] 8000fa4: 685b ldr r3, [r3, #4] 8000fa6: 2203 movs r2, #3 8000fa8: 401a ands r2, r3 8000faa: 697b ldr r3, [r7, #20] 8000fac: 005b lsls r3, r3, #1 8000fae: 409a lsls r2, r3 8000fb0: 0013 movs r3, r2 8000fb2: 693a ldr r2, [r7, #16] 8000fb4: 4313 orrs r3, r2 8000fb6: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8000fb8: 687b ldr r3, [r7, #4] 8000fba: 693a ldr r2, [r7, #16] 8000fbc: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8000fbe: 683b ldr r3, [r7, #0] 8000fc0: 685a ldr r2, [r3, #4] 8000fc2: 23c0 movs r3, #192 ; 0xc0 8000fc4: 029b lsls r3, r3, #10 8000fc6: 4013 ands r3, r2 8000fc8: d100 bne.n 8000fcc 8000fca: e09a b.n 8001102 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000fcc: 4b54 ldr r3, [pc, #336] ; (8001120 ) 8000fce: 699a ldr r2, [r3, #24] 8000fd0: 4b53 ldr r3, [pc, #332] ; (8001120 ) 8000fd2: 2101 movs r1, #1 8000fd4: 430a orrs r2, r1 8000fd6: 619a str r2, [r3, #24] 8000fd8: 4b51 ldr r3, [pc, #324] ; (8001120 ) 8000fda: 699b ldr r3, [r3, #24] 8000fdc: 2201 movs r2, #1 8000fde: 4013 ands r3, r2 8000fe0: 60bb str r3, [r7, #8] 8000fe2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 8000fe4: 4a4f ldr r2, [pc, #316] ; (8001124 ) 8000fe6: 697b ldr r3, [r7, #20] 8000fe8: 089b lsrs r3, r3, #2 8000fea: 3302 adds r3, #2 8000fec: 009b lsls r3, r3, #2 8000fee: 589b ldr r3, [r3, r2] 8000ff0: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8000ff2: 697b ldr r3, [r7, #20] 8000ff4: 2203 movs r2, #3 8000ff6: 4013 ands r3, r2 8000ff8: 009b lsls r3, r3, #2 8000ffa: 220f movs r2, #15 8000ffc: 409a lsls r2, r3 8000ffe: 0013 movs r3, r2 8001000: 43da mvns r2, r3 8001002: 693b ldr r3, [r7, #16] 8001004: 4013 ands r3, r2 8001006: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8001008: 687a ldr r2, [r7, #4] 800100a: 2390 movs r3, #144 ; 0x90 800100c: 05db lsls r3, r3, #23 800100e: 429a cmp r2, r3 8001010: d013 beq.n 800103a 8001012: 687b ldr r3, [r7, #4] 8001014: 4a44 ldr r2, [pc, #272] ; (8001128 ) 8001016: 4293 cmp r3, r2 8001018: d00d beq.n 8001036 800101a: 687b ldr r3, [r7, #4] 800101c: 4a43 ldr r2, [pc, #268] ; (800112c ) 800101e: 4293 cmp r3, r2 8001020: d007 beq.n 8001032 8001022: 687b ldr r3, [r7, #4] 8001024: 4a42 ldr r2, [pc, #264] ; (8001130 ) 8001026: 4293 cmp r3, r2 8001028: d101 bne.n 800102e 800102a: 2303 movs r3, #3 800102c: e006 b.n 800103c 800102e: 2305 movs r3, #5 8001030: e004 b.n 800103c 8001032: 2302 movs r3, #2 8001034: e002 b.n 800103c 8001036: 2301 movs r3, #1 8001038: e000 b.n 800103c 800103a: 2300 movs r3, #0 800103c: 697a ldr r2, [r7, #20] 800103e: 2103 movs r1, #3 8001040: 400a ands r2, r1 8001042: 0092 lsls r2, r2, #2 8001044: 4093 lsls r3, r2 8001046: 693a ldr r2, [r7, #16] 8001048: 4313 orrs r3, r2 800104a: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 800104c: 4935 ldr r1, [pc, #212] ; (8001124 ) 800104e: 697b ldr r3, [r7, #20] 8001050: 089b lsrs r3, r3, #2 8001052: 3302 adds r3, #2 8001054: 009b lsls r3, r3, #2 8001056: 693a ldr r2, [r7, #16] 8001058: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ temp = EXTI->IMR; 800105a: 4b36 ldr r3, [pc, #216] ; (8001134 ) 800105c: 681b ldr r3, [r3, #0] 800105e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001060: 68fb ldr r3, [r7, #12] 8001062: 43da mvns r2, r3 8001064: 693b ldr r3, [r7, #16] 8001066: 4013 ands r3, r2 8001068: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 800106a: 683b ldr r3, [r7, #0] 800106c: 685a ldr r2, [r3, #4] 800106e: 2380 movs r3, #128 ; 0x80 8001070: 025b lsls r3, r3, #9 8001072: 4013 ands r3, r2 8001074: d003 beq.n 800107e { temp |= iocurrent; 8001076: 693a ldr r2, [r7, #16] 8001078: 68fb ldr r3, [r7, #12] 800107a: 4313 orrs r3, r2 800107c: 613b str r3, [r7, #16] } EXTI->IMR = temp; 800107e: 4b2d ldr r3, [pc, #180] ; (8001134 ) 8001080: 693a ldr r2, [r7, #16] 8001082: 601a str r2, [r3, #0] temp = EXTI->EMR; 8001084: 4b2b ldr r3, [pc, #172] ; (8001134 ) 8001086: 685b ldr r3, [r3, #4] 8001088: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800108a: 68fb ldr r3, [r7, #12] 800108c: 43da mvns r2, r3 800108e: 693b ldr r3, [r7, #16] 8001090: 4013 ands r3, r2 8001092: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8001094: 683b ldr r3, [r7, #0] 8001096: 685a ldr r2, [r3, #4] 8001098: 2380 movs r3, #128 ; 0x80 800109a: 029b lsls r3, r3, #10 800109c: 4013 ands r3, r2 800109e: d003 beq.n 80010a8 { temp |= iocurrent; 80010a0: 693a ldr r2, [r7, #16] 80010a2: 68fb ldr r3, [r7, #12] 80010a4: 4313 orrs r3, r2 80010a6: 613b str r3, [r7, #16] } EXTI->EMR = temp; 80010a8: 4b22 ldr r3, [pc, #136] ; (8001134 ) 80010aa: 693a ldr r2, [r7, #16] 80010ac: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 80010ae: 4b21 ldr r3, [pc, #132] ; (8001134 ) 80010b0: 689b ldr r3, [r3, #8] 80010b2: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80010b4: 68fb ldr r3, [r7, #12] 80010b6: 43da mvns r2, r3 80010b8: 693b ldr r3, [r7, #16] 80010ba: 4013 ands r3, r2 80010bc: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 80010be: 683b ldr r3, [r7, #0] 80010c0: 685a ldr r2, [r3, #4] 80010c2: 2380 movs r3, #128 ; 0x80 80010c4: 035b lsls r3, r3, #13 80010c6: 4013 ands r3, r2 80010c8: d003 beq.n 80010d2 { temp |= iocurrent; 80010ca: 693a ldr r2, [r7, #16] 80010cc: 68fb ldr r3, [r7, #12] 80010ce: 4313 orrs r3, r2 80010d0: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 80010d2: 4b18 ldr r3, [pc, #96] ; (8001134 ) 80010d4: 693a ldr r2, [r7, #16] 80010d6: 609a str r2, [r3, #8] temp = EXTI->FTSR; 80010d8: 4b16 ldr r3, [pc, #88] ; (8001134 ) 80010da: 68db ldr r3, [r3, #12] 80010dc: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80010de: 68fb ldr r3, [r7, #12] 80010e0: 43da mvns r2, r3 80010e2: 693b ldr r3, [r7, #16] 80010e4: 4013 ands r3, r2 80010e6: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 80010e8: 683b ldr r3, [r7, #0] 80010ea: 685a ldr r2, [r3, #4] 80010ec: 2380 movs r3, #128 ; 0x80 80010ee: 039b lsls r3, r3, #14 80010f0: 4013 ands r3, r2 80010f2: d003 beq.n 80010fc { temp |= iocurrent; 80010f4: 693a ldr r2, [r7, #16] 80010f6: 68fb ldr r3, [r7, #12] 80010f8: 4313 orrs r3, r2 80010fa: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 80010fc: 4b0d ldr r3, [pc, #52] ; (8001134 ) 80010fe: 693a ldr r2, [r7, #16] 8001100: 60da str r2, [r3, #12] } } position++; 8001102: 697b ldr r3, [r7, #20] 8001104: 3301 adds r3, #1 8001106: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8001108: 683b ldr r3, [r7, #0] 800110a: 681a ldr r2, [r3, #0] 800110c: 697b ldr r3, [r7, #20] 800110e: 40da lsrs r2, r3 8001110: 1e13 subs r3, r2, #0 8001112: d000 beq.n 8001116 8001114: e6a8 b.n 8000e68 } } 8001116: 46c0 nop ; (mov r8, r8) 8001118: 46c0 nop ; (mov r8, r8) 800111a: 46bd mov sp, r7 800111c: b006 add sp, #24 800111e: bd80 pop {r7, pc} 8001120: 40021000 .word 0x40021000 8001124: 40010000 .word 0x40010000 8001128: 48000400 .word 0x48000400 800112c: 48000800 .word 0x48000800 8001130: 48000c00 .word 0x48000c00 8001134: 40010400 .word 0x40010400 08001138 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001138: b580 push {r7, lr} 800113a: b084 sub sp, #16 800113c: af00 add r7, sp, #0 800113e: 6078 str r0, [r7, #4] 8001140: 000a movs r2, r1 8001142: 1cbb adds r3, r7, #2 8001144: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001146: 687b ldr r3, [r7, #4] 8001148: 691b ldr r3, [r3, #16] 800114a: 1cba adds r2, r7, #2 800114c: 8812 ldrh r2, [r2, #0] 800114e: 4013 ands r3, r2 8001150: d004 beq.n 800115c { bitstatus = GPIO_PIN_SET; 8001152: 230f movs r3, #15 8001154: 18fb adds r3, r7, r3 8001156: 2201 movs r2, #1 8001158: 701a strb r2, [r3, #0] 800115a: e003 b.n 8001164 } else { bitstatus = GPIO_PIN_RESET; 800115c: 230f movs r3, #15 800115e: 18fb adds r3, r7, r3 8001160: 2200 movs r2, #0 8001162: 701a strb r2, [r3, #0] } return bitstatus; 8001164: 230f movs r3, #15 8001166: 18fb adds r3, r7, r3 8001168: 781b ldrb r3, [r3, #0] } 800116a: 0018 movs r0, r3 800116c: 46bd mov sp, r7 800116e: b004 add sp, #16 8001170: bd80 pop {r7, pc} 08001172 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001172: b580 push {r7, lr} 8001174: b082 sub sp, #8 8001176: af00 add r7, sp, #0 8001178: 6078 str r0, [r7, #4] 800117a: 0008 movs r0, r1 800117c: 0011 movs r1, r2 800117e: 1cbb adds r3, r7, #2 8001180: 1c02 adds r2, r0, #0 8001182: 801a strh r2, [r3, #0] 8001184: 1c7b adds r3, r7, #1 8001186: 1c0a adds r2, r1, #0 8001188: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800118a: 1c7b adds r3, r7, #1 800118c: 781b ldrb r3, [r3, #0] 800118e: 2b00 cmp r3, #0 8001190: d004 beq.n 800119c { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001192: 1cbb adds r3, r7, #2 8001194: 881a ldrh r2, [r3, #0] 8001196: 687b ldr r3, [r7, #4] 8001198: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 800119a: e003 b.n 80011a4 GPIOx->BRR = (uint32_t)GPIO_Pin; 800119c: 1cbb adds r3, r7, #2 800119e: 881a ldrh r2, [r3, #0] 80011a0: 687b ldr r3, [r7, #4] 80011a2: 629a str r2, [r3, #40] ; 0x28 } 80011a4: 46c0 nop ; (mov r8, r8) 80011a6: 46bd mov sp, r7 80011a8: b002 add sp, #8 80011aa: bd80 pop {r7, pc} 080011ac : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80011ac: b580 push {r7, lr} 80011ae: b088 sub sp, #32 80011b0: af00 add r7, sp, #0 80011b2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 80011b4: 687b ldr r3, [r7, #4] 80011b6: 2b00 cmp r3, #0 80011b8: d101 bne.n 80011be { return HAL_ERROR; 80011ba: 2301 movs r3, #1 80011bc: e301 b.n 80017c2 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80011be: 687b ldr r3, [r7, #4] 80011c0: 681b ldr r3, [r3, #0] 80011c2: 2201 movs r2, #1 80011c4: 4013 ands r3, r2 80011c6: d100 bne.n 80011ca 80011c8: e08d b.n 80012e6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80011ca: 4bc3 ldr r3, [pc, #780] ; (80014d8 ) 80011cc: 685b ldr r3, [r3, #4] 80011ce: 220c movs r2, #12 80011d0: 4013 ands r3, r2 80011d2: 2b04 cmp r3, #4 80011d4: d00e beq.n 80011f4 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80011d6: 4bc0 ldr r3, [pc, #768] ; (80014d8 ) 80011d8: 685b ldr r3, [r3, #4] 80011da: 220c movs r2, #12 80011dc: 4013 ands r3, r2 80011de: 2b08 cmp r3, #8 80011e0: d116 bne.n 8001210 80011e2: 4bbd ldr r3, [pc, #756] ; (80014d8 ) 80011e4: 685a ldr r2, [r3, #4] 80011e6: 2380 movs r3, #128 ; 0x80 80011e8: 025b lsls r3, r3, #9 80011ea: 401a ands r2, r3 80011ec: 2380 movs r3, #128 ; 0x80 80011ee: 025b lsls r3, r3, #9 80011f0: 429a cmp r2, r3 80011f2: d10d bne.n 8001210 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80011f4: 4bb8 ldr r3, [pc, #736] ; (80014d8 ) 80011f6: 681a ldr r2, [r3, #0] 80011f8: 2380 movs r3, #128 ; 0x80 80011fa: 029b lsls r3, r3, #10 80011fc: 4013 ands r3, r2 80011fe: d100 bne.n 8001202 8001200: e070 b.n 80012e4 8001202: 687b ldr r3, [r7, #4] 8001204: 685b ldr r3, [r3, #4] 8001206: 2b00 cmp r3, #0 8001208: d000 beq.n 800120c 800120a: e06b b.n 80012e4 { return HAL_ERROR; 800120c: 2301 movs r3, #1 800120e: e2d8 b.n 80017c2 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001210: 687b ldr r3, [r7, #4] 8001212: 685b ldr r3, [r3, #4] 8001214: 2b01 cmp r3, #1 8001216: d107 bne.n 8001228 8001218: 4baf ldr r3, [pc, #700] ; (80014d8 ) 800121a: 681a ldr r2, [r3, #0] 800121c: 4bae ldr r3, [pc, #696] ; (80014d8 ) 800121e: 2180 movs r1, #128 ; 0x80 8001220: 0249 lsls r1, r1, #9 8001222: 430a orrs r2, r1 8001224: 601a str r2, [r3, #0] 8001226: e02f b.n 8001288 8001228: 687b ldr r3, [r7, #4] 800122a: 685b ldr r3, [r3, #4] 800122c: 2b00 cmp r3, #0 800122e: d10c bne.n 800124a 8001230: 4ba9 ldr r3, [pc, #676] ; (80014d8 ) 8001232: 681a ldr r2, [r3, #0] 8001234: 4ba8 ldr r3, [pc, #672] ; (80014d8 ) 8001236: 49a9 ldr r1, [pc, #676] ; (80014dc ) 8001238: 400a ands r2, r1 800123a: 601a str r2, [r3, #0] 800123c: 4ba6 ldr r3, [pc, #664] ; (80014d8 ) 800123e: 681a ldr r2, [r3, #0] 8001240: 4ba5 ldr r3, [pc, #660] ; (80014d8 ) 8001242: 49a7 ldr r1, [pc, #668] ; (80014e0 ) 8001244: 400a ands r2, r1 8001246: 601a str r2, [r3, #0] 8001248: e01e b.n 8001288 800124a: 687b ldr r3, [r7, #4] 800124c: 685b ldr r3, [r3, #4] 800124e: 2b05 cmp r3, #5 8001250: d10e bne.n 8001270 8001252: 4ba1 ldr r3, [pc, #644] ; (80014d8 ) 8001254: 681a ldr r2, [r3, #0] 8001256: 4ba0 ldr r3, [pc, #640] ; (80014d8 ) 8001258: 2180 movs r1, #128 ; 0x80 800125a: 02c9 lsls r1, r1, #11 800125c: 430a orrs r2, r1 800125e: 601a str r2, [r3, #0] 8001260: 4b9d ldr r3, [pc, #628] ; (80014d8 ) 8001262: 681a ldr r2, [r3, #0] 8001264: 4b9c ldr r3, [pc, #624] ; (80014d8 ) 8001266: 2180 movs r1, #128 ; 0x80 8001268: 0249 lsls r1, r1, #9 800126a: 430a orrs r2, r1 800126c: 601a str r2, [r3, #0] 800126e: e00b b.n 8001288 8001270: 4b99 ldr r3, [pc, #612] ; (80014d8 ) 8001272: 681a ldr r2, [r3, #0] 8001274: 4b98 ldr r3, [pc, #608] ; (80014d8 ) 8001276: 4999 ldr r1, [pc, #612] ; (80014dc ) 8001278: 400a ands r2, r1 800127a: 601a str r2, [r3, #0] 800127c: 4b96 ldr r3, [pc, #600] ; (80014d8 ) 800127e: 681a ldr r2, [r3, #0] 8001280: 4b95 ldr r3, [pc, #596] ; (80014d8 ) 8001282: 4997 ldr r1, [pc, #604] ; (80014e0 ) 8001284: 400a ands r2, r1 8001286: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001288: 687b ldr r3, [r7, #4] 800128a: 685b ldr r3, [r3, #4] 800128c: 2b00 cmp r3, #0 800128e: d014 beq.n 80012ba { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001290: f7ff faee bl 8000870 8001294: 0003 movs r3, r0 8001296: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001298: e008 b.n 80012ac { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 800129a: f7ff fae9 bl 8000870 800129e: 0002 movs r2, r0 80012a0: 69bb ldr r3, [r7, #24] 80012a2: 1ad3 subs r3, r2, r3 80012a4: 2b64 cmp r3, #100 ; 0x64 80012a6: d901 bls.n 80012ac { return HAL_TIMEOUT; 80012a8: 2303 movs r3, #3 80012aa: e28a b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80012ac: 4b8a ldr r3, [pc, #552] ; (80014d8 ) 80012ae: 681a ldr r2, [r3, #0] 80012b0: 2380 movs r3, #128 ; 0x80 80012b2: 029b lsls r3, r3, #10 80012b4: 4013 ands r3, r2 80012b6: d0f0 beq.n 800129a 80012b8: e015 b.n 80012e6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80012ba: f7ff fad9 bl 8000870 80012be: 0003 movs r3, r0 80012c0: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80012c2: e008 b.n 80012d6 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80012c4: f7ff fad4 bl 8000870 80012c8: 0002 movs r2, r0 80012ca: 69bb ldr r3, [r7, #24] 80012cc: 1ad3 subs r3, r2, r3 80012ce: 2b64 cmp r3, #100 ; 0x64 80012d0: d901 bls.n 80012d6 { return HAL_TIMEOUT; 80012d2: 2303 movs r3, #3 80012d4: e275 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80012d6: 4b80 ldr r3, [pc, #512] ; (80014d8 ) 80012d8: 681a ldr r2, [r3, #0] 80012da: 2380 movs r3, #128 ; 0x80 80012dc: 029b lsls r3, r3, #10 80012de: 4013 ands r3, r2 80012e0: d1f0 bne.n 80012c4 80012e2: e000 b.n 80012e6 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80012e4: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80012e6: 687b ldr r3, [r7, #4] 80012e8: 681b ldr r3, [r3, #0] 80012ea: 2202 movs r2, #2 80012ec: 4013 ands r3, r2 80012ee: d100 bne.n 80012f2 80012f0: e069 b.n 80013c6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80012f2: 4b79 ldr r3, [pc, #484] ; (80014d8 ) 80012f4: 685b ldr r3, [r3, #4] 80012f6: 220c movs r2, #12 80012f8: 4013 ands r3, r2 80012fa: d00b beq.n 8001314 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 80012fc: 4b76 ldr r3, [pc, #472] ; (80014d8 ) 80012fe: 685b ldr r3, [r3, #4] 8001300: 220c movs r2, #12 8001302: 4013 ands r3, r2 8001304: 2b08 cmp r3, #8 8001306: d11c bne.n 8001342 8001308: 4b73 ldr r3, [pc, #460] ; (80014d8 ) 800130a: 685a ldr r2, [r3, #4] 800130c: 2380 movs r3, #128 ; 0x80 800130e: 025b lsls r3, r3, #9 8001310: 4013 ands r3, r2 8001312: d116 bne.n 8001342 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001314: 4b70 ldr r3, [pc, #448] ; (80014d8 ) 8001316: 681b ldr r3, [r3, #0] 8001318: 2202 movs r2, #2 800131a: 4013 ands r3, r2 800131c: d005 beq.n 800132a 800131e: 687b ldr r3, [r7, #4] 8001320: 68db ldr r3, [r3, #12] 8001322: 2b01 cmp r3, #1 8001324: d001 beq.n 800132a { return HAL_ERROR; 8001326: 2301 movs r3, #1 8001328: e24b b.n 80017c2 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800132a: 4b6b ldr r3, [pc, #428] ; (80014d8 ) 800132c: 681b ldr r3, [r3, #0] 800132e: 22f8 movs r2, #248 ; 0xf8 8001330: 4393 bics r3, r2 8001332: 0019 movs r1, r3 8001334: 687b ldr r3, [r7, #4] 8001336: 691b ldr r3, [r3, #16] 8001338: 00da lsls r2, r3, #3 800133a: 4b67 ldr r3, [pc, #412] ; (80014d8 ) 800133c: 430a orrs r2, r1 800133e: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001340: e041 b.n 80013c6 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001342: 687b ldr r3, [r7, #4] 8001344: 68db ldr r3, [r3, #12] 8001346: 2b00 cmp r3, #0 8001348: d024 beq.n 8001394 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800134a: 4b63 ldr r3, [pc, #396] ; (80014d8 ) 800134c: 681a ldr r2, [r3, #0] 800134e: 4b62 ldr r3, [pc, #392] ; (80014d8 ) 8001350: 2101 movs r1, #1 8001352: 430a orrs r2, r1 8001354: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001356: f7ff fa8b bl 8000870 800135a: 0003 movs r3, r0 800135c: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800135e: e008 b.n 8001372 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001360: f7ff fa86 bl 8000870 8001364: 0002 movs r2, r0 8001366: 69bb ldr r3, [r7, #24] 8001368: 1ad3 subs r3, r2, r3 800136a: 2b02 cmp r3, #2 800136c: d901 bls.n 8001372 { return HAL_TIMEOUT; 800136e: 2303 movs r3, #3 8001370: e227 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001372: 4b59 ldr r3, [pc, #356] ; (80014d8 ) 8001374: 681b ldr r3, [r3, #0] 8001376: 2202 movs r2, #2 8001378: 4013 ands r3, r2 800137a: d0f1 beq.n 8001360 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800137c: 4b56 ldr r3, [pc, #344] ; (80014d8 ) 800137e: 681b ldr r3, [r3, #0] 8001380: 22f8 movs r2, #248 ; 0xf8 8001382: 4393 bics r3, r2 8001384: 0019 movs r1, r3 8001386: 687b ldr r3, [r7, #4] 8001388: 691b ldr r3, [r3, #16] 800138a: 00da lsls r2, r3, #3 800138c: 4b52 ldr r3, [pc, #328] ; (80014d8 ) 800138e: 430a orrs r2, r1 8001390: 601a str r2, [r3, #0] 8001392: e018 b.n 80013c6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001394: 4b50 ldr r3, [pc, #320] ; (80014d8 ) 8001396: 681a ldr r2, [r3, #0] 8001398: 4b4f ldr r3, [pc, #316] ; (80014d8 ) 800139a: 2101 movs r1, #1 800139c: 438a bics r2, r1 800139e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80013a0: f7ff fa66 bl 8000870 80013a4: 0003 movs r3, r0 80013a6: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80013a8: e008 b.n 80013bc { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80013aa: f7ff fa61 bl 8000870 80013ae: 0002 movs r2, r0 80013b0: 69bb ldr r3, [r7, #24] 80013b2: 1ad3 subs r3, r2, r3 80013b4: 2b02 cmp r3, #2 80013b6: d901 bls.n 80013bc { return HAL_TIMEOUT; 80013b8: 2303 movs r3, #3 80013ba: e202 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80013bc: 4b46 ldr r3, [pc, #280] ; (80014d8 ) 80013be: 681b ldr r3, [r3, #0] 80013c0: 2202 movs r2, #2 80013c2: 4013 ands r3, r2 80013c4: d1f1 bne.n 80013aa } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80013c6: 687b ldr r3, [r7, #4] 80013c8: 681b ldr r3, [r3, #0] 80013ca: 2208 movs r2, #8 80013cc: 4013 ands r3, r2 80013ce: d036 beq.n 800143e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80013d0: 687b ldr r3, [r7, #4] 80013d2: 69db ldr r3, [r3, #28] 80013d4: 2b00 cmp r3, #0 80013d6: d019 beq.n 800140c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80013d8: 4b3f ldr r3, [pc, #252] ; (80014d8 ) 80013da: 6a5a ldr r2, [r3, #36] ; 0x24 80013dc: 4b3e ldr r3, [pc, #248] ; (80014d8 ) 80013de: 2101 movs r1, #1 80013e0: 430a orrs r2, r1 80013e2: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 80013e4: f7ff fa44 bl 8000870 80013e8: 0003 movs r3, r0 80013ea: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80013ec: e008 b.n 8001400 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 80013ee: f7ff fa3f bl 8000870 80013f2: 0002 movs r2, r0 80013f4: 69bb ldr r3, [r7, #24] 80013f6: 1ad3 subs r3, r2, r3 80013f8: 2b02 cmp r3, #2 80013fa: d901 bls.n 8001400 { return HAL_TIMEOUT; 80013fc: 2303 movs r3, #3 80013fe: e1e0 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001400: 4b35 ldr r3, [pc, #212] ; (80014d8 ) 8001402: 6a5b ldr r3, [r3, #36] ; 0x24 8001404: 2202 movs r2, #2 8001406: 4013 ands r3, r2 8001408: d0f1 beq.n 80013ee 800140a: e018 b.n 800143e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800140c: 4b32 ldr r3, [pc, #200] ; (80014d8 ) 800140e: 6a5a ldr r2, [r3, #36] ; 0x24 8001410: 4b31 ldr r3, [pc, #196] ; (80014d8 ) 8001412: 2101 movs r1, #1 8001414: 438a bics r2, r1 8001416: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001418: f7ff fa2a bl 8000870 800141c: 0003 movs r3, r0 800141e: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001420: e008 b.n 8001434 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001422: f7ff fa25 bl 8000870 8001426: 0002 movs r2, r0 8001428: 69bb ldr r3, [r7, #24] 800142a: 1ad3 subs r3, r2, r3 800142c: 2b02 cmp r3, #2 800142e: d901 bls.n 8001434 { return HAL_TIMEOUT; 8001430: 2303 movs r3, #3 8001432: e1c6 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001434: 4b28 ldr r3, [pc, #160] ; (80014d8 ) 8001436: 6a5b ldr r3, [r3, #36] ; 0x24 8001438: 2202 movs r2, #2 800143a: 4013 ands r3, r2 800143c: d1f1 bne.n 8001422 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800143e: 687b ldr r3, [r7, #4] 8001440: 681b ldr r3, [r3, #0] 8001442: 2204 movs r2, #4 8001444: 4013 ands r3, r2 8001446: d100 bne.n 800144a 8001448: e0b4 b.n 80015b4 { FlagStatus pwrclkchanged = RESET; 800144a: 201f movs r0, #31 800144c: 183b adds r3, r7, r0 800144e: 2200 movs r2, #0 8001450: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001452: 4b21 ldr r3, [pc, #132] ; (80014d8 ) 8001454: 69da ldr r2, [r3, #28] 8001456: 2380 movs r3, #128 ; 0x80 8001458: 055b lsls r3, r3, #21 800145a: 4013 ands r3, r2 800145c: d110 bne.n 8001480 { __HAL_RCC_PWR_CLK_ENABLE(); 800145e: 4b1e ldr r3, [pc, #120] ; (80014d8 ) 8001460: 69da ldr r2, [r3, #28] 8001462: 4b1d ldr r3, [pc, #116] ; (80014d8 ) 8001464: 2180 movs r1, #128 ; 0x80 8001466: 0549 lsls r1, r1, #21 8001468: 430a orrs r2, r1 800146a: 61da str r2, [r3, #28] 800146c: 4b1a ldr r3, [pc, #104] ; (80014d8 ) 800146e: 69da ldr r2, [r3, #28] 8001470: 2380 movs r3, #128 ; 0x80 8001472: 055b lsls r3, r3, #21 8001474: 4013 ands r3, r2 8001476: 60fb str r3, [r7, #12] 8001478: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 800147a: 183b adds r3, r7, r0 800147c: 2201 movs r2, #1 800147e: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001480: 4b18 ldr r3, [pc, #96] ; (80014e4 ) 8001482: 681a ldr r2, [r3, #0] 8001484: 2380 movs r3, #128 ; 0x80 8001486: 005b lsls r3, r3, #1 8001488: 4013 ands r3, r2 800148a: d11a bne.n 80014c2 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800148c: 4b15 ldr r3, [pc, #84] ; (80014e4 ) 800148e: 681a ldr r2, [r3, #0] 8001490: 4b14 ldr r3, [pc, #80] ; (80014e4 ) 8001492: 2180 movs r1, #128 ; 0x80 8001494: 0049 lsls r1, r1, #1 8001496: 430a orrs r2, r1 8001498: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800149a: f7ff f9e9 bl 8000870 800149e: 0003 movs r3, r0 80014a0: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80014a2: e008 b.n 80014b6 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80014a4: f7ff f9e4 bl 8000870 80014a8: 0002 movs r2, r0 80014aa: 69bb ldr r3, [r7, #24] 80014ac: 1ad3 subs r3, r2, r3 80014ae: 2b64 cmp r3, #100 ; 0x64 80014b0: d901 bls.n 80014b6 { return HAL_TIMEOUT; 80014b2: 2303 movs r3, #3 80014b4: e185 b.n 80017c2 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80014b6: 4b0b ldr r3, [pc, #44] ; (80014e4 ) 80014b8: 681a ldr r2, [r3, #0] 80014ba: 2380 movs r3, #128 ; 0x80 80014bc: 005b lsls r3, r3, #1 80014be: 4013 ands r3, r2 80014c0: d0f0 beq.n 80014a4 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80014c2: 687b ldr r3, [r7, #4] 80014c4: 689b ldr r3, [r3, #8] 80014c6: 2b01 cmp r3, #1 80014c8: d10e bne.n 80014e8 80014ca: 4b03 ldr r3, [pc, #12] ; (80014d8 ) 80014cc: 6a1a ldr r2, [r3, #32] 80014ce: 4b02 ldr r3, [pc, #8] ; (80014d8 ) 80014d0: 2101 movs r1, #1 80014d2: 430a orrs r2, r1 80014d4: 621a str r2, [r3, #32] 80014d6: e035 b.n 8001544 80014d8: 40021000 .word 0x40021000 80014dc: fffeffff .word 0xfffeffff 80014e0: fffbffff .word 0xfffbffff 80014e4: 40007000 .word 0x40007000 80014e8: 687b ldr r3, [r7, #4] 80014ea: 689b ldr r3, [r3, #8] 80014ec: 2b00 cmp r3, #0 80014ee: d10c bne.n 800150a 80014f0: 4bb6 ldr r3, [pc, #728] ; (80017cc ) 80014f2: 6a1a ldr r2, [r3, #32] 80014f4: 4bb5 ldr r3, [pc, #724] ; (80017cc ) 80014f6: 2101 movs r1, #1 80014f8: 438a bics r2, r1 80014fa: 621a str r2, [r3, #32] 80014fc: 4bb3 ldr r3, [pc, #716] ; (80017cc ) 80014fe: 6a1a ldr r2, [r3, #32] 8001500: 4bb2 ldr r3, [pc, #712] ; (80017cc ) 8001502: 2104 movs r1, #4 8001504: 438a bics r2, r1 8001506: 621a str r2, [r3, #32] 8001508: e01c b.n 8001544 800150a: 687b ldr r3, [r7, #4] 800150c: 689b ldr r3, [r3, #8] 800150e: 2b05 cmp r3, #5 8001510: d10c bne.n 800152c 8001512: 4bae ldr r3, [pc, #696] ; (80017cc ) 8001514: 6a1a ldr r2, [r3, #32] 8001516: 4bad ldr r3, [pc, #692] ; (80017cc ) 8001518: 2104 movs r1, #4 800151a: 430a orrs r2, r1 800151c: 621a str r2, [r3, #32] 800151e: 4bab ldr r3, [pc, #684] ; (80017cc ) 8001520: 6a1a ldr r2, [r3, #32] 8001522: 4baa ldr r3, [pc, #680] ; (80017cc ) 8001524: 2101 movs r1, #1 8001526: 430a orrs r2, r1 8001528: 621a str r2, [r3, #32] 800152a: e00b b.n 8001544 800152c: 4ba7 ldr r3, [pc, #668] ; (80017cc ) 800152e: 6a1a ldr r2, [r3, #32] 8001530: 4ba6 ldr r3, [pc, #664] ; (80017cc ) 8001532: 2101 movs r1, #1 8001534: 438a bics r2, r1 8001536: 621a str r2, [r3, #32] 8001538: 4ba4 ldr r3, [pc, #656] ; (80017cc ) 800153a: 6a1a ldr r2, [r3, #32] 800153c: 4ba3 ldr r3, [pc, #652] ; (80017cc ) 800153e: 2104 movs r1, #4 8001540: 438a bics r2, r1 8001542: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001544: 687b ldr r3, [r7, #4] 8001546: 689b ldr r3, [r3, #8] 8001548: 2b00 cmp r3, #0 800154a: d014 beq.n 8001576 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800154c: f7ff f990 bl 8000870 8001550: 0003 movs r3, r0 8001552: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001554: e009 b.n 800156a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001556: f7ff f98b bl 8000870 800155a: 0002 movs r2, r0 800155c: 69bb ldr r3, [r7, #24] 800155e: 1ad3 subs r3, r2, r3 8001560: 4a9b ldr r2, [pc, #620] ; (80017d0 ) 8001562: 4293 cmp r3, r2 8001564: d901 bls.n 800156a { return HAL_TIMEOUT; 8001566: 2303 movs r3, #3 8001568: e12b b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800156a: 4b98 ldr r3, [pc, #608] ; (80017cc ) 800156c: 6a1b ldr r3, [r3, #32] 800156e: 2202 movs r2, #2 8001570: 4013 ands r3, r2 8001572: d0f0 beq.n 8001556 8001574: e013 b.n 800159e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001576: f7ff f97b bl 8000870 800157a: 0003 movs r3, r0 800157c: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800157e: e009 b.n 8001594 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001580: f7ff f976 bl 8000870 8001584: 0002 movs r2, r0 8001586: 69bb ldr r3, [r7, #24] 8001588: 1ad3 subs r3, r2, r3 800158a: 4a91 ldr r2, [pc, #580] ; (80017d0 ) 800158c: 4293 cmp r3, r2 800158e: d901 bls.n 8001594 { return HAL_TIMEOUT; 8001590: 2303 movs r3, #3 8001592: e116 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001594: 4b8d ldr r3, [pc, #564] ; (80017cc ) 8001596: 6a1b ldr r3, [r3, #32] 8001598: 2202 movs r2, #2 800159a: 4013 ands r3, r2 800159c: d1f0 bne.n 8001580 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 800159e: 231f movs r3, #31 80015a0: 18fb adds r3, r7, r3 80015a2: 781b ldrb r3, [r3, #0] 80015a4: 2b01 cmp r3, #1 80015a6: d105 bne.n 80015b4 { __HAL_RCC_PWR_CLK_DISABLE(); 80015a8: 4b88 ldr r3, [pc, #544] ; (80017cc ) 80015aa: 69da ldr r2, [r3, #28] 80015ac: 4b87 ldr r3, [pc, #540] ; (80017cc ) 80015ae: 4989 ldr r1, [pc, #548] ; (80017d4 ) 80015b0: 400a ands r2, r1 80015b2: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 80015b4: 687b ldr r3, [r7, #4] 80015b6: 681b ldr r3, [r3, #0] 80015b8: 2210 movs r2, #16 80015ba: 4013 ands r3, r2 80015bc: d063 beq.n 8001686 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 80015be: 687b ldr r3, [r7, #4] 80015c0: 695b ldr r3, [r3, #20] 80015c2: 2b01 cmp r3, #1 80015c4: d12a bne.n 800161c { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 80015c6: 4b81 ldr r3, [pc, #516] ; (80017cc ) 80015c8: 6b5a ldr r2, [r3, #52] ; 0x34 80015ca: 4b80 ldr r3, [pc, #512] ; (80017cc ) 80015cc: 2104 movs r1, #4 80015ce: 430a orrs r2, r1 80015d0: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 80015d2: 4b7e ldr r3, [pc, #504] ; (80017cc ) 80015d4: 6b5a ldr r2, [r3, #52] ; 0x34 80015d6: 4b7d ldr r3, [pc, #500] ; (80017cc ) 80015d8: 2101 movs r1, #1 80015da: 430a orrs r2, r1 80015dc: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 80015de: f7ff f947 bl 8000870 80015e2: 0003 movs r3, r0 80015e4: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 80015e6: e008 b.n 80015fa { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 80015e8: f7ff f942 bl 8000870 80015ec: 0002 movs r2, r0 80015ee: 69bb ldr r3, [r7, #24] 80015f0: 1ad3 subs r3, r2, r3 80015f2: 2b02 cmp r3, #2 80015f4: d901 bls.n 80015fa { return HAL_TIMEOUT; 80015f6: 2303 movs r3, #3 80015f8: e0e3 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 80015fa: 4b74 ldr r3, [pc, #464] ; (80017cc ) 80015fc: 6b5b ldr r3, [r3, #52] ; 0x34 80015fe: 2202 movs r2, #2 8001600: 4013 ands r3, r2 8001602: d0f1 beq.n 80015e8 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001604: 4b71 ldr r3, [pc, #452] ; (80017cc ) 8001606: 6b5b ldr r3, [r3, #52] ; 0x34 8001608: 22f8 movs r2, #248 ; 0xf8 800160a: 4393 bics r3, r2 800160c: 0019 movs r1, r3 800160e: 687b ldr r3, [r7, #4] 8001610: 699b ldr r3, [r3, #24] 8001612: 00da lsls r2, r3, #3 8001614: 4b6d ldr r3, [pc, #436] ; (80017cc ) 8001616: 430a orrs r2, r1 8001618: 635a str r2, [r3, #52] ; 0x34 800161a: e034 b.n 8001686 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 800161c: 687b ldr r3, [r7, #4] 800161e: 695b ldr r3, [r3, #20] 8001620: 3305 adds r3, #5 8001622: d111 bne.n 8001648 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001624: 4b69 ldr r3, [pc, #420] ; (80017cc ) 8001626: 6b5a ldr r2, [r3, #52] ; 0x34 8001628: 4b68 ldr r3, [pc, #416] ; (80017cc ) 800162a: 2104 movs r1, #4 800162c: 438a bics r2, r1 800162e: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001630: 4b66 ldr r3, [pc, #408] ; (80017cc ) 8001632: 6b5b ldr r3, [r3, #52] ; 0x34 8001634: 22f8 movs r2, #248 ; 0xf8 8001636: 4393 bics r3, r2 8001638: 0019 movs r1, r3 800163a: 687b ldr r3, [r7, #4] 800163c: 699b ldr r3, [r3, #24] 800163e: 00da lsls r2, r3, #3 8001640: 4b62 ldr r3, [pc, #392] ; (80017cc ) 8001642: 430a orrs r2, r1 8001644: 635a str r2, [r3, #52] ; 0x34 8001646: e01e b.n 8001686 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001648: 4b60 ldr r3, [pc, #384] ; (80017cc ) 800164a: 6b5a ldr r2, [r3, #52] ; 0x34 800164c: 4b5f ldr r3, [pc, #380] ; (80017cc ) 800164e: 2104 movs r1, #4 8001650: 430a orrs r2, r1 8001652: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001654: 4b5d ldr r3, [pc, #372] ; (80017cc ) 8001656: 6b5a ldr r2, [r3, #52] ; 0x34 8001658: 4b5c ldr r3, [pc, #368] ; (80017cc ) 800165a: 2101 movs r1, #1 800165c: 438a bics r2, r1 800165e: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001660: f7ff f906 bl 8000870 8001664: 0003 movs r3, r0 8001666: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001668: e008 b.n 800167c { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 800166a: f7ff f901 bl 8000870 800166e: 0002 movs r2, r0 8001670: 69bb ldr r3, [r7, #24] 8001672: 1ad3 subs r3, r2, r3 8001674: 2b02 cmp r3, #2 8001676: d901 bls.n 800167c { return HAL_TIMEOUT; 8001678: 2303 movs r3, #3 800167a: e0a2 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 800167c: 4b53 ldr r3, [pc, #332] ; (80017cc ) 800167e: 6b5b ldr r3, [r3, #52] ; 0x34 8001680: 2202 movs r2, #2 8001682: 4013 ands r3, r2 8001684: d1f1 bne.n 800166a #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001686: 687b ldr r3, [r7, #4] 8001688: 6a1b ldr r3, [r3, #32] 800168a: 2b00 cmp r3, #0 800168c: d100 bne.n 8001690 800168e: e097 b.n 80017c0 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001690: 4b4e ldr r3, [pc, #312] ; (80017cc ) 8001692: 685b ldr r3, [r3, #4] 8001694: 220c movs r2, #12 8001696: 4013 ands r3, r2 8001698: 2b08 cmp r3, #8 800169a: d100 bne.n 800169e 800169c: e06b b.n 8001776 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800169e: 687b ldr r3, [r7, #4] 80016a0: 6a1b ldr r3, [r3, #32] 80016a2: 2b02 cmp r3, #2 80016a4: d14c bne.n 8001740 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80016a6: 4b49 ldr r3, [pc, #292] ; (80017cc ) 80016a8: 681a ldr r2, [r3, #0] 80016aa: 4b48 ldr r3, [pc, #288] ; (80017cc ) 80016ac: 494a ldr r1, [pc, #296] ; (80017d8 ) 80016ae: 400a ands r2, r1 80016b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80016b2: f7ff f8dd bl 8000870 80016b6: 0003 movs r3, r0 80016b8: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80016ba: e008 b.n 80016ce { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80016bc: f7ff f8d8 bl 8000870 80016c0: 0002 movs r2, r0 80016c2: 69bb ldr r3, [r7, #24] 80016c4: 1ad3 subs r3, r2, r3 80016c6: 2b02 cmp r3, #2 80016c8: d901 bls.n 80016ce { return HAL_TIMEOUT; 80016ca: 2303 movs r3, #3 80016cc: e079 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80016ce: 4b3f ldr r3, [pc, #252] ; (80017cc ) 80016d0: 681a ldr r2, [r3, #0] 80016d2: 2380 movs r3, #128 ; 0x80 80016d4: 049b lsls r3, r3, #18 80016d6: 4013 ands r3, r2 80016d8: d1f0 bne.n 80016bc } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80016da: 4b3c ldr r3, [pc, #240] ; (80017cc ) 80016dc: 6adb ldr r3, [r3, #44] ; 0x2c 80016de: 220f movs r2, #15 80016e0: 4393 bics r3, r2 80016e2: 0019 movs r1, r3 80016e4: 687b ldr r3, [r7, #4] 80016e6: 6ada ldr r2, [r3, #44] ; 0x2c 80016e8: 4b38 ldr r3, [pc, #224] ; (80017cc ) 80016ea: 430a orrs r2, r1 80016ec: 62da str r2, [r3, #44] ; 0x2c 80016ee: 4b37 ldr r3, [pc, #220] ; (80017cc ) 80016f0: 685b ldr r3, [r3, #4] 80016f2: 4a3a ldr r2, [pc, #232] ; (80017dc ) 80016f4: 4013 ands r3, r2 80016f6: 0019 movs r1, r3 80016f8: 687b ldr r3, [r7, #4] 80016fa: 6a9a ldr r2, [r3, #40] ; 0x28 80016fc: 687b ldr r3, [r7, #4] 80016fe: 6a5b ldr r3, [r3, #36] ; 0x24 8001700: 431a orrs r2, r3 8001702: 4b32 ldr r3, [pc, #200] ; (80017cc ) 8001704: 430a orrs r2, r1 8001706: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001708: 4b30 ldr r3, [pc, #192] ; (80017cc ) 800170a: 681a ldr r2, [r3, #0] 800170c: 4b2f ldr r3, [pc, #188] ; (80017cc ) 800170e: 2180 movs r1, #128 ; 0x80 8001710: 0449 lsls r1, r1, #17 8001712: 430a orrs r2, r1 8001714: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001716: f7ff f8ab bl 8000870 800171a: 0003 movs r3, r0 800171c: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800171e: e008 b.n 8001732 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001720: f7ff f8a6 bl 8000870 8001724: 0002 movs r2, r0 8001726: 69bb ldr r3, [r7, #24] 8001728: 1ad3 subs r3, r2, r3 800172a: 2b02 cmp r3, #2 800172c: d901 bls.n 8001732 { return HAL_TIMEOUT; 800172e: 2303 movs r3, #3 8001730: e047 b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001732: 4b26 ldr r3, [pc, #152] ; (80017cc ) 8001734: 681a ldr r2, [r3, #0] 8001736: 2380 movs r3, #128 ; 0x80 8001738: 049b lsls r3, r3, #18 800173a: 4013 ands r3, r2 800173c: d0f0 beq.n 8001720 800173e: e03f b.n 80017c0 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001740: 4b22 ldr r3, [pc, #136] ; (80017cc ) 8001742: 681a ldr r2, [r3, #0] 8001744: 4b21 ldr r3, [pc, #132] ; (80017cc ) 8001746: 4924 ldr r1, [pc, #144] ; (80017d8 ) 8001748: 400a ands r2, r1 800174a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800174c: f7ff f890 bl 8000870 8001750: 0003 movs r3, r0 8001752: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001754: e008 b.n 8001768 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001756: f7ff f88b bl 8000870 800175a: 0002 movs r2, r0 800175c: 69bb ldr r3, [r7, #24] 800175e: 1ad3 subs r3, r2, r3 8001760: 2b02 cmp r3, #2 8001762: d901 bls.n 8001768 { return HAL_TIMEOUT; 8001764: 2303 movs r3, #3 8001766: e02c b.n 80017c2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001768: 4b18 ldr r3, [pc, #96] ; (80017cc ) 800176a: 681a ldr r2, [r3, #0] 800176c: 2380 movs r3, #128 ; 0x80 800176e: 049b lsls r3, r3, #18 8001770: 4013 ands r3, r2 8001772: d1f0 bne.n 8001756 8001774: e024 b.n 80017c0 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001776: 687b ldr r3, [r7, #4] 8001778: 6a1b ldr r3, [r3, #32] 800177a: 2b01 cmp r3, #1 800177c: d101 bne.n 8001782 { return HAL_ERROR; 800177e: 2301 movs r3, #1 8001780: e01f b.n 80017c2 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001782: 4b12 ldr r3, [pc, #72] ; (80017cc ) 8001784: 685b ldr r3, [r3, #4] 8001786: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001788: 4b10 ldr r3, [pc, #64] ; (80017cc ) 800178a: 6adb ldr r3, [r3, #44] ; 0x2c 800178c: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800178e: 697a ldr r2, [r7, #20] 8001790: 2380 movs r3, #128 ; 0x80 8001792: 025b lsls r3, r3, #9 8001794: 401a ands r2, r3 8001796: 687b ldr r3, [r7, #4] 8001798: 6a5b ldr r3, [r3, #36] ; 0x24 800179a: 429a cmp r2, r3 800179c: d10e bne.n 80017bc (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 800179e: 693b ldr r3, [r7, #16] 80017a0: 220f movs r2, #15 80017a2: 401a ands r2, r3 80017a4: 687b ldr r3, [r7, #4] 80017a6: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80017a8: 429a cmp r2, r3 80017aa: d107 bne.n 80017bc (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 80017ac: 697a ldr r2, [r7, #20] 80017ae: 23f0 movs r3, #240 ; 0xf0 80017b0: 039b lsls r3, r3, #14 80017b2: 401a ands r2, r3 80017b4: 687b ldr r3, [r7, #4] 80017b6: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 80017b8: 429a cmp r2, r3 80017ba: d001 beq.n 80017c0 { return HAL_ERROR; 80017bc: 2301 movs r3, #1 80017be: e000 b.n 80017c2 } } } } return HAL_OK; 80017c0: 2300 movs r3, #0 } 80017c2: 0018 movs r0, r3 80017c4: 46bd mov sp, r7 80017c6: b008 add sp, #32 80017c8: bd80 pop {r7, pc} 80017ca: 46c0 nop ; (mov r8, r8) 80017cc: 40021000 .word 0x40021000 80017d0: 00001388 .word 0x00001388 80017d4: efffffff .word 0xefffffff 80017d8: feffffff .word 0xfeffffff 80017dc: ffc2ffff .word 0xffc2ffff 080017e0 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80017e0: b580 push {r7, lr} 80017e2: b084 sub sp, #16 80017e4: af00 add r7, sp, #0 80017e6: 6078 str r0, [r7, #4] 80017e8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 80017ea: 687b ldr r3, [r7, #4] 80017ec: 2b00 cmp r3, #0 80017ee: d101 bne.n 80017f4 { return HAL_ERROR; 80017f0: 2301 movs r3, #1 80017f2: e0b3 b.n 800195c /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 80017f4: 4b5b ldr r3, [pc, #364] ; (8001964 ) 80017f6: 681b ldr r3, [r3, #0] 80017f8: 2201 movs r2, #1 80017fa: 4013 ands r3, r2 80017fc: 683a ldr r2, [r7, #0] 80017fe: 429a cmp r2, r3 8001800: d911 bls.n 8001826 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001802: 4b58 ldr r3, [pc, #352] ; (8001964 ) 8001804: 681b ldr r3, [r3, #0] 8001806: 2201 movs r2, #1 8001808: 4393 bics r3, r2 800180a: 0019 movs r1, r3 800180c: 4b55 ldr r3, [pc, #340] ; (8001964 ) 800180e: 683a ldr r2, [r7, #0] 8001810: 430a orrs r2, r1 8001812: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001814: 4b53 ldr r3, [pc, #332] ; (8001964 ) 8001816: 681b ldr r3, [r3, #0] 8001818: 2201 movs r2, #1 800181a: 4013 ands r3, r2 800181c: 683a ldr r2, [r7, #0] 800181e: 429a cmp r2, r3 8001820: d001 beq.n 8001826 { return HAL_ERROR; 8001822: 2301 movs r3, #1 8001824: e09a b.n 800195c } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001826: 687b ldr r3, [r7, #4] 8001828: 681b ldr r3, [r3, #0] 800182a: 2202 movs r2, #2 800182c: 4013 ands r3, r2 800182e: d015 beq.n 800185c { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001830: 687b ldr r3, [r7, #4] 8001832: 681b ldr r3, [r3, #0] 8001834: 2204 movs r2, #4 8001836: 4013 ands r3, r2 8001838: d006 beq.n 8001848 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 800183a: 4b4b ldr r3, [pc, #300] ; (8001968 ) 800183c: 685a ldr r2, [r3, #4] 800183e: 4b4a ldr r3, [pc, #296] ; (8001968 ) 8001840: 21e0 movs r1, #224 ; 0xe0 8001842: 00c9 lsls r1, r1, #3 8001844: 430a orrs r2, r1 8001846: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001848: 4b47 ldr r3, [pc, #284] ; (8001968 ) 800184a: 685b ldr r3, [r3, #4] 800184c: 22f0 movs r2, #240 ; 0xf0 800184e: 4393 bics r3, r2 8001850: 0019 movs r1, r3 8001852: 687b ldr r3, [r7, #4] 8001854: 689a ldr r2, [r3, #8] 8001856: 4b44 ldr r3, [pc, #272] ; (8001968 ) 8001858: 430a orrs r2, r1 800185a: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800185c: 687b ldr r3, [r7, #4] 800185e: 681b ldr r3, [r3, #0] 8001860: 2201 movs r2, #1 8001862: 4013 ands r3, r2 8001864: d040 beq.n 80018e8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8001866: 687b ldr r3, [r7, #4] 8001868: 685b ldr r3, [r3, #4] 800186a: 2b01 cmp r3, #1 800186c: d107 bne.n 800187e { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800186e: 4b3e ldr r3, [pc, #248] ; (8001968 ) 8001870: 681a ldr r2, [r3, #0] 8001872: 2380 movs r3, #128 ; 0x80 8001874: 029b lsls r3, r3, #10 8001876: 4013 ands r3, r2 8001878: d114 bne.n 80018a4 { return HAL_ERROR; 800187a: 2301 movs r3, #1 800187c: e06e b.n 800195c } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800187e: 687b ldr r3, [r7, #4] 8001880: 685b ldr r3, [r3, #4] 8001882: 2b02 cmp r3, #2 8001884: d107 bne.n 8001896 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001886: 4b38 ldr r3, [pc, #224] ; (8001968 ) 8001888: 681a ldr r2, [r3, #0] 800188a: 2380 movs r3, #128 ; 0x80 800188c: 049b lsls r3, r3, #18 800188e: 4013 ands r3, r2 8001890: d108 bne.n 80018a4 { return HAL_ERROR; 8001892: 2301 movs r3, #1 8001894: e062 b.n 800195c #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001896: 4b34 ldr r3, [pc, #208] ; (8001968 ) 8001898: 681b ldr r3, [r3, #0] 800189a: 2202 movs r2, #2 800189c: 4013 ands r3, r2 800189e: d101 bne.n 80018a4 { return HAL_ERROR; 80018a0: 2301 movs r3, #1 80018a2: e05b b.n 800195c } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80018a4: 4b30 ldr r3, [pc, #192] ; (8001968 ) 80018a6: 685b ldr r3, [r3, #4] 80018a8: 2203 movs r2, #3 80018aa: 4393 bics r3, r2 80018ac: 0019 movs r1, r3 80018ae: 687b ldr r3, [r7, #4] 80018b0: 685a ldr r2, [r3, #4] 80018b2: 4b2d ldr r3, [pc, #180] ; (8001968 ) 80018b4: 430a orrs r2, r1 80018b6: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80018b8: f7fe ffda bl 8000870 80018bc: 0003 movs r3, r0 80018be: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80018c0: e009 b.n 80018d6 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80018c2: f7fe ffd5 bl 8000870 80018c6: 0002 movs r2, r0 80018c8: 68fb ldr r3, [r7, #12] 80018ca: 1ad3 subs r3, r2, r3 80018cc: 4a27 ldr r2, [pc, #156] ; (800196c ) 80018ce: 4293 cmp r3, r2 80018d0: d901 bls.n 80018d6 { return HAL_TIMEOUT; 80018d2: 2303 movs r3, #3 80018d4: e042 b.n 800195c while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80018d6: 4b24 ldr r3, [pc, #144] ; (8001968 ) 80018d8: 685b ldr r3, [r3, #4] 80018da: 220c movs r2, #12 80018dc: 401a ands r2, r3 80018de: 687b ldr r3, [r7, #4] 80018e0: 685b ldr r3, [r3, #4] 80018e2: 009b lsls r3, r3, #2 80018e4: 429a cmp r2, r3 80018e6: d1ec bne.n 80018c2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 80018e8: 4b1e ldr r3, [pc, #120] ; (8001964 ) 80018ea: 681b ldr r3, [r3, #0] 80018ec: 2201 movs r2, #1 80018ee: 4013 ands r3, r2 80018f0: 683a ldr r2, [r7, #0] 80018f2: 429a cmp r2, r3 80018f4: d211 bcs.n 800191a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80018f6: 4b1b ldr r3, [pc, #108] ; (8001964 ) 80018f8: 681b ldr r3, [r3, #0] 80018fa: 2201 movs r2, #1 80018fc: 4393 bics r3, r2 80018fe: 0019 movs r1, r3 8001900: 4b18 ldr r3, [pc, #96] ; (8001964 ) 8001902: 683a ldr r2, [r7, #0] 8001904: 430a orrs r2, r1 8001906: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001908: 4b16 ldr r3, [pc, #88] ; (8001964 ) 800190a: 681b ldr r3, [r3, #0] 800190c: 2201 movs r2, #1 800190e: 4013 ands r3, r2 8001910: 683a ldr r2, [r7, #0] 8001912: 429a cmp r2, r3 8001914: d001 beq.n 800191a { return HAL_ERROR; 8001916: 2301 movs r3, #1 8001918: e020 b.n 800195c } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800191a: 687b ldr r3, [r7, #4] 800191c: 681b ldr r3, [r3, #0] 800191e: 2204 movs r2, #4 8001920: 4013 ands r3, r2 8001922: d009 beq.n 8001938 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8001924: 4b10 ldr r3, [pc, #64] ; (8001968 ) 8001926: 685b ldr r3, [r3, #4] 8001928: 4a11 ldr r2, [pc, #68] ; (8001970 ) 800192a: 4013 ands r3, r2 800192c: 0019 movs r1, r3 800192e: 687b ldr r3, [r7, #4] 8001930: 68da ldr r2, [r3, #12] 8001932: 4b0d ldr r3, [pc, #52] ; (8001968 ) 8001934: 430a orrs r2, r1 8001936: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8001938: f000 f820 bl 800197c 800193c: 0001 movs r1, r0 800193e: 4b0a ldr r3, [pc, #40] ; (8001968 ) 8001940: 685b ldr r3, [r3, #4] 8001942: 091b lsrs r3, r3, #4 8001944: 220f movs r2, #15 8001946: 4013 ands r3, r2 8001948: 4a0a ldr r2, [pc, #40] ; (8001974 ) 800194a: 5cd3 ldrb r3, [r2, r3] 800194c: 000a movs r2, r1 800194e: 40da lsrs r2, r3 8001950: 4b09 ldr r3, [pc, #36] ; (8001978 ) 8001952: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8001954: 2003 movs r0, #3 8001956: f7fe ff45 bl 80007e4 return HAL_OK; 800195a: 2300 movs r3, #0 } 800195c: 0018 movs r0, r3 800195e: 46bd mov sp, r7 8001960: b004 add sp, #16 8001962: bd80 pop {r7, pc} 8001964: 40022000 .word 0x40022000 8001968: 40021000 .word 0x40021000 800196c: 00001388 .word 0x00001388 8001970: fffff8ff .word 0xfffff8ff 8001974: 08002644 .word 0x08002644 8001978: 20000000 .word 0x20000000 0800197c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800197c: b590 push {r4, r7, lr} 800197e: b08f sub sp, #60 ; 0x3c 8001980: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 8001982: 2314 movs r3, #20 8001984: 18fb adds r3, r7, r3 8001986: 4a2b ldr r2, [pc, #172] ; (8001a34 ) 8001988: ca13 ldmia r2!, {r0, r1, r4} 800198a: c313 stmia r3!, {r0, r1, r4} 800198c: 6812 ldr r2, [r2, #0] 800198e: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8001990: 1d3b adds r3, r7, #4 8001992: 4a29 ldr r2, [pc, #164] ; (8001a38 ) 8001994: ca13 ldmia r2!, {r0, r1, r4} 8001996: c313 stmia r3!, {r0, r1, r4} 8001998: 6812 ldr r2, [r2, #0] 800199a: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 800199c: 2300 movs r3, #0 800199e: 62fb str r3, [r7, #44] ; 0x2c 80019a0: 2300 movs r3, #0 80019a2: 62bb str r3, [r7, #40] ; 0x28 80019a4: 2300 movs r3, #0 80019a6: 637b str r3, [r7, #52] ; 0x34 80019a8: 2300 movs r3, #0 80019aa: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 80019ac: 2300 movs r3, #0 80019ae: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 80019b0: 4b22 ldr r3, [pc, #136] ; (8001a3c ) 80019b2: 685b ldr r3, [r3, #4] 80019b4: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80019b6: 6afb ldr r3, [r7, #44] ; 0x2c 80019b8: 220c movs r2, #12 80019ba: 4013 ands r3, r2 80019bc: 2b04 cmp r3, #4 80019be: d002 beq.n 80019c6 80019c0: 2b08 cmp r3, #8 80019c2: d003 beq.n 80019cc 80019c4: e02d b.n 8001a22 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80019c6: 4b1e ldr r3, [pc, #120] ; (8001a40 ) 80019c8: 633b str r3, [r7, #48] ; 0x30 break; 80019ca: e02d b.n 8001a28 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 80019cc: 6afb ldr r3, [r7, #44] ; 0x2c 80019ce: 0c9b lsrs r3, r3, #18 80019d0: 220f movs r2, #15 80019d2: 4013 ands r3, r2 80019d4: 2214 movs r2, #20 80019d6: 18ba adds r2, r7, r2 80019d8: 5cd3 ldrb r3, [r2, r3] 80019da: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 80019dc: 4b17 ldr r3, [pc, #92] ; (8001a3c ) 80019de: 6adb ldr r3, [r3, #44] ; 0x2c 80019e0: 220f movs r2, #15 80019e2: 4013 ands r3, r2 80019e4: 1d3a adds r2, r7, #4 80019e6: 5cd3 ldrb r3, [r2, r3] 80019e8: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 80019ea: 6afa ldr r2, [r7, #44] ; 0x2c 80019ec: 2380 movs r3, #128 ; 0x80 80019ee: 025b lsls r3, r3, #9 80019f0: 4013 ands r3, r2 80019f2: d009 beq.n 8001a08 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80019f4: 6ab9 ldr r1, [r7, #40] ; 0x28 80019f6: 4812 ldr r0, [pc, #72] ; (8001a40 ) 80019f8: f7fe fb86 bl 8000108 <__udivsi3> 80019fc: 0003 movs r3, r0 80019fe: 001a movs r2, r3 8001a00: 6a7b ldr r3, [r7, #36] ; 0x24 8001a02: 4353 muls r3, r2 8001a04: 637b str r3, [r7, #52] ; 0x34 8001a06: e009 b.n 8001a1c #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 8001a08: 6a79 ldr r1, [r7, #36] ; 0x24 8001a0a: 000a movs r2, r1 8001a0c: 0152 lsls r2, r2, #5 8001a0e: 1a52 subs r2, r2, r1 8001a10: 0193 lsls r3, r2, #6 8001a12: 1a9b subs r3, r3, r2 8001a14: 00db lsls r3, r3, #3 8001a16: 185b adds r3, r3, r1 8001a18: 021b lsls r3, r3, #8 8001a1a: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 8001a1c: 6b7b ldr r3, [r7, #52] ; 0x34 8001a1e: 633b str r3, [r7, #48] ; 0x30 break; 8001a20: e002 b.n 8001a28 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8001a22: 4b07 ldr r3, [pc, #28] ; (8001a40 ) 8001a24: 633b str r3, [r7, #48] ; 0x30 break; 8001a26: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8001a28: 6b3b ldr r3, [r7, #48] ; 0x30 } 8001a2a: 0018 movs r0, r3 8001a2c: 46bd mov sp, r7 8001a2e: b00f add sp, #60 ; 0x3c 8001a30: bd90 pop {r4, r7, pc} 8001a32: 46c0 nop ; (mov r8, r8) 8001a34: 08002624 .word 0x08002624 8001a38: 08002634 .word 0x08002634 8001a3c: 40021000 .word 0x40021000 8001a40: 007a1200 .word 0x007a1200 08001a44 : */ #include "button.h" void GEI_BUTTON_CODE(struct button *bt,uint8_t in) { 8001a44: b580 push {r7, lr} 8001a46: b082 sub sp, #8 8001a48: af00 add r7, sp, #0 8001a4a: 6078 str r0, [r7, #4] 8001a4c: 000a movs r2, r1 8001a4e: 1cfb adds r3, r7, #3 8001a50: 701a strb r2, [r3, #0] #define t 250 bt->code=0; 8001a52: 687b ldr r3, [r7, #4] 8001a54: 2200 movs r2, #0 8001a56: 601a str r2, [r3, #0] if(in==1) 8001a58: 1cfb adds r3, r7, #3 8001a5a: 781b ldrb r3, [r3, #0] 8001a5c: 2b01 cmp r3, #1 8001a5e: d138 bne.n 8001ad2 { if(bt->lock==0) 8001a60: 687b ldr r3, [r7, #4] 8001a62: 791b ldrb r3, [r3, #4] 8001a64: 2b00 cmp r3, #0 8001a66: d120 bne.n 8001aaa { if(HAL_GetTick()time+t) 8001a68: f7fe ff02 bl 8000870 8001a6c: 0002 movs r2, r0 8001a6e: 687b ldr r3, [r7, #4] 8001a70: 689b ldr r3, [r3, #8] 8001a72: 33fa adds r3, #250 ; 0xfa 8001a74: 429a cmp r2, r3 8001a76: d20d bcs.n 8001a94 { bt->times++; 8001a78: 687b ldr r3, [r7, #4] 8001a7a: 68db ldr r3, [r3, #12] 8001a7c: 1c5a adds r2, r3, #1 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 8001a82: f7fe fef5 bl 8000870 8001a86: 0002 movs r2, r0 8001a88: 687b ldr r3, [r7, #4] 8001a8a: 609a str r2, [r3, #8] bt->lock=1; 8001a8c: 687b ldr r3, [r7, #4] 8001a8e: 2201 movs r2, #1 8001a90: 711a strb r2, [r3, #4] 8001a92: e00a b.n 8001aaa }else { bt->times=1; 8001a94: 687b ldr r3, [r7, #4] 8001a96: 2201 movs r2, #1 8001a98: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 8001a9a: f7fe fee9 bl 8000870 8001a9e: 0002 movs r2, r0 8001aa0: 687b ldr r3, [r7, #4] 8001aa2: 609a str r2, [r3, #8] bt->lock=1; 8001aa4: 687b ldr r3, [r7, #4] 8001aa6: 2201 movs r2, #1 8001aa8: 711a strb r2, [r3, #4] } } if(bt->lock==1) 8001aaa: 687b ldr r3, [r7, #4] 8001aac: 791b ldrb r3, [r3, #4] 8001aae: 2b01 cmp r3, #1 8001ab0: d10f bne.n 8001ad2 { if(HAL_GetTick()>bt->time+t) 8001ab2: f7fe fedd bl 8000870 8001ab6: 0002 movs r2, r0 8001ab8: 687b ldr r3, [r7, #4] 8001aba: 689b ldr r3, [r3, #8] 8001abc: 33fa adds r3, #250 ; 0xfa 8001abe: 429a cmp r2, r3 8001ac0: d907 bls.n 8001ad2 { bt->code=-1; 8001ac2: 687b ldr r3, [r7, #4] 8001ac4: 2201 movs r2, #1 8001ac6: 4252 negs r2, r2 8001ac8: 601a str r2, [r3, #0] bt->times=-1; 8001aca: 687b ldr r3, [r7, #4] 8001acc: 2201 movs r2, #1 8001ace: 4252 negs r2, r2 8001ad0: 60da str r2, [r3, #12] } } } if(in==0) 8001ad2: 1cfb adds r3, r7, #3 8001ad4: 781b ldrb r3, [r3, #0] 8001ad6: 2b00 cmp r3, #0 8001ad8: d10e bne.n 8001af8 { if(bt->lock==1) 8001ada: 687b ldr r3, [r7, #4] 8001adc: 791b ldrb r3, [r3, #4] 8001ade: 2b01 cmp r3, #1 8001ae0: d10a bne.n 8001af8 { if(bt->code==-1) 8001ae2: 687b ldr r3, [r7, #4] 8001ae4: 681b ldr r3, [r3, #0] 8001ae6: 3301 adds r3, #1 8001ae8: d003 beq.n 8001af2 { }else { bt->code=bt->times; 8001aea: 687b ldr r3, [r7, #4] 8001aec: 68da ldr r2, [r3, #12] 8001aee: 687b ldr r3, [r7, #4] 8001af0: 601a str r2, [r3, #0] } bt->lock=0; 8001af2: 687b ldr r3, [r7, #4] 8001af4: 2200 movs r2, #0 8001af6: 711a strb r2, [r3, #4] } } } 8001af8: 46c0 nop ; (mov r8, r8) 8001afa: 46bd mov sp, r7 8001afc: b002 add sp, #8 8001afe: bd80 pop {r7, pc} 08001b00 : char led_n:1; char led_err:1; }dis_buff; void Send_to_595(char h,char l) { 8001b00: b580 push {r7, lr} 8001b02: b084 sub sp, #16 8001b04: af00 add r7, sp, #0 8001b06: 0002 movs r2, r0 8001b08: 1dfb adds r3, r7, #7 8001b0a: 701a strb r2, [r3, #0] 8001b0c: 1dbb adds r3, r7, #6 8001b0e: 1c0a adds r2, r1, #0 8001b10: 701a strb r2, [r3, #0] for(int a=0;a<8;a++) 8001b12: 2300 movs r3, #0 8001b14: 60fb str r3, [r7, #12] 8001b16: e027 b.n 8001b68 { if((h< { HC595_DCK(1); 8001b28: 2390 movs r3, #144 ; 0x90 8001b2a: 05db lsls r3, r3, #23 8001b2c: 2201 movs r2, #1 8001b2e: 2108 movs r1, #8 8001b30: 0018 movs r0, r3 8001b32: f7ff fb1e bl 8001172 8001b36: e006 b.n 8001b46 }else { HC595_DCK(0); 8001b38: 2390 movs r3, #144 ; 0x90 8001b3a: 05db lsls r3, r3, #23 8001b3c: 2200 movs r2, #0 8001b3e: 2108 movs r1, #8 8001b40: 0018 movs r0, r3 8001b42: f7ff fb16 bl 8001172 } HC595_SCK(1); 8001b46: 2390 movs r3, #144 ; 0x90 8001b48: 05db lsls r3, r3, #23 8001b4a: 2201 movs r2, #1 8001b4c: 2120 movs r1, #32 8001b4e: 0018 movs r0, r3 8001b50: f7ff fb0f bl 8001172 HC595_SCK(0); 8001b54: 2390 movs r3, #144 ; 0x90 8001b56: 05db lsls r3, r3, #23 8001b58: 2200 movs r2, #0 8001b5a: 2120 movs r1, #32 8001b5c: 0018 movs r0, r3 8001b5e: f7ff fb08 bl 8001172 for(int a=0;a<8;a++) 8001b62: 68fb ldr r3, [r7, #12] 8001b64: 3301 adds r3, #1 8001b66: 60fb str r3, [r7, #12] 8001b68: 68fb ldr r3, [r7, #12] 8001b6a: 2b07 cmp r3, #7 8001b6c: ddd4 ble.n 8001b18 } for(int a=0;a<8;a++) 8001b6e: 2300 movs r3, #0 8001b70: 60bb str r3, [r7, #8] 8001b72: e027 b.n 8001bc4 { if((l< { HC595_DCK(1); 8001b84: 2390 movs r3, #144 ; 0x90 8001b86: 05db lsls r3, r3, #23 8001b88: 2201 movs r2, #1 8001b8a: 2108 movs r1, #8 8001b8c: 0018 movs r0, r3 8001b8e: f7ff faf0 bl 8001172 8001b92: e006 b.n 8001ba2 }else { HC595_DCK(0); 8001b94: 2390 movs r3, #144 ; 0x90 8001b96: 05db lsls r3, r3, #23 8001b98: 2200 movs r2, #0 8001b9a: 2108 movs r1, #8 8001b9c: 0018 movs r0, r3 8001b9e: f7ff fae8 bl 8001172 } HC595_SCK(1); 8001ba2: 2390 movs r3, #144 ; 0x90 8001ba4: 05db lsls r3, r3, #23 8001ba6: 2201 movs r2, #1 8001ba8: 2120 movs r1, #32 8001baa: 0018 movs r0, r3 8001bac: f7ff fae1 bl 8001172 HC595_SCK(0); 8001bb0: 2390 movs r3, #144 ; 0x90 8001bb2: 05db lsls r3, r3, #23 8001bb4: 2200 movs r2, #0 8001bb6: 2120 movs r1, #32 8001bb8: 0018 movs r0, r3 8001bba: f7ff fada bl 8001172 for(int a=0;a<8;a++) 8001bbe: 68bb ldr r3, [r7, #8] 8001bc0: 3301 adds r3, #1 8001bc2: 60bb str r3, [r7, #8] 8001bc4: 68bb ldr r3, [r7, #8] 8001bc6: 2b07 cmp r3, #7 8001bc8: ddd4 ble.n 8001b74 } HC595_RCK(1); 8001bca: 2390 movs r3, #144 ; 0x90 8001bcc: 05db lsls r3, r3, #23 8001bce: 2201 movs r2, #1 8001bd0: 2110 movs r1, #16 8001bd2: 0018 movs r0, r3 8001bd4: f7ff facd bl 8001172 HC595_RCK(0); 8001bd8: 2390 movs r3, #144 ; 0x90 8001bda: 05db lsls r3, r3, #23 8001bdc: 2200 movs r2, #0 8001bde: 2110 movs r1, #16 8001be0: 0018 movs r0, r3 8001be2: f7ff fac6 bl 8001172 } 8001be6: 46c0 nop ; (mov r8, r8) 8001be8: 46bd mov sp, r7 8001bea: b004 add sp, #16 8001bec: bd80 pop {r7, pc} ... 08001bf0 : void display() { 8001bf0: b580 push {r7, lr} 8001bf2: b082 sub sp, #8 8001bf4: af00 add r7, sp, #0 char h_buff=0,l_buff=0; 8001bf6: 1dfb adds r3, r7, #7 8001bf8: 2200 movs r2, #0 8001bfa: 701a strb r2, [r3, #0] 8001bfc: 1dbb adds r3, r7, #6 8001bfe: 2200 movs r2, #0 8001c00: 701a strb r2, [r3, #0] h_buff=0,l_buff=0; 8001c02: 1dfb adds r3, r7, #7 8001c04: 2200 movs r2, #0 8001c06: 701a strb r2, [r3, #0] 8001c08: 1dbb adds r3, r7, #6 8001c0a: 2200 movs r2, #0 8001c0c: 701a strb r2, [r3, #0] Send_to_595(h_buff,l_buff); 8001c0e: 1dbb adds r3, r7, #6 8001c10: 781a ldrb r2, [r3, #0] 8001c12: 1dfb adds r3, r7, #7 8001c14: 781b ldrb r3, [r3, #0] 8001c16: 0011 movs r1, r2 8001c18: 0018 movs r0, r3 8001c1a: f7ff ff71 bl 8001b00 h_buff=~0x01; 8001c1e: 1dfb adds r3, r7, #7 8001c20: 22fe movs r2, #254 ; 0xfe 8001c22: 701a strb r2, [r3, #0] l_buff=dis_buff.d_num[0]>=10?0:d_num_data[0][dis_buff.d_num[0]]; 8001c24: 4b7b ldr r3, [pc, #492] ; (8001e14 ) 8001c26: 781b ldrb r3, [r3, #0] 8001c28: 2b09 cmp r3, #9 8001c2a: d805 bhi.n 8001c38 8001c2c: 4b79 ldr r3, [pc, #484] ; (8001e14 ) 8001c2e: 781b ldrb r3, [r3, #0] 8001c30: 001a movs r2, r3 8001c32: 4b79 ldr r3, [pc, #484] ; (8001e18 ) 8001c34: 5c9a ldrb r2, [r3, r2] 8001c36: e000 b.n 8001c3a 8001c38: 2200 movs r2, #0 8001c3a: 1dbb adds r3, r7, #6 8001c3c: 701a strb r2, [r3, #0] if(dis_buff.dot1==1) 8001c3e: 4b75 ldr r3, [pc, #468] ; (8001e14 ) 8001c40: 791b ldrb r3, [r3, #4] 8001c42: 2201 movs r2, #1 8001c44: 4013 ands r3, r2 8001c46: b2db uxtb r3, r3 8001c48: 2b00 cmp r3, #0 8001c4a: d006 beq.n 8001c5a { l_buff|=0x80; 8001c4c: 1dbb adds r3, r7, #6 8001c4e: 1dba adds r2, r7, #6 8001c50: 7812 ldrb r2, [r2, #0] 8001c52: 2180 movs r1, #128 ; 0x80 8001c54: 4249 negs r1, r1 8001c56: 430a orrs r2, r1 8001c58: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001c5a: 1dbb adds r3, r7, #6 8001c5c: 781a ldrb r2, [r3, #0] 8001c5e: 1dfb adds r3, r7, #7 8001c60: 781b ldrb r3, [r3, #0] 8001c62: 0011 movs r1, r2 8001c64: 0018 movs r0, r3 8001c66: f7ff ff4b bl 8001b00 h_buff=0,l_buff=0; 8001c6a: 1dfb adds r3, r7, #7 8001c6c: 2200 movs r2, #0 8001c6e: 701a strb r2, [r3, #0] 8001c70: 1dbb adds r3, r7, #6 8001c72: 2200 movs r2, #0 8001c74: 701a strb r2, [r3, #0] Send_to_595(h_buff,l_buff); 8001c76: 1dbb adds r3, r7, #6 8001c78: 781a ldrb r2, [r3, #0] 8001c7a: 1dfb adds r3, r7, #7 8001c7c: 781b ldrb r3, [r3, #0] 8001c7e: 0011 movs r1, r2 8001c80: 0018 movs r0, r3 8001c82: f7ff ff3d bl 8001b00 h_buff=~0x80; 8001c86: 1dfb adds r3, r7, #7 8001c88: 227f movs r2, #127 ; 0x7f 8001c8a: 701a strb r2, [r3, #0] l_buff=dis_buff.d_num[1]>=10?0:d_num_data[1][dis_buff.d_num[1]]; 8001c8c: 4b61 ldr r3, [pc, #388] ; (8001e14 ) 8001c8e: 785b ldrb r3, [r3, #1] 8001c90: 2b09 cmp r3, #9 8001c92: d806 bhi.n 8001ca2 8001c94: 4b5f ldr r3, [pc, #380] ; (8001e14 ) 8001c96: 785b ldrb r3, [r3, #1] 8001c98: 001a movs r2, r3 8001c9a: 4b5f ldr r3, [pc, #380] ; (8001e18 ) 8001c9c: 189b adds r3, r3, r2 8001c9e: 7a9a ldrb r2, [r3, #10] 8001ca0: e000 b.n 8001ca4 8001ca2: 2200 movs r2, #0 8001ca4: 1dbb adds r3, r7, #6 8001ca6: 701a strb r2, [r3, #0] if(dis_buff.dot2==1) 8001ca8: 4b5a ldr r3, [pc, #360] ; (8001e14 ) 8001caa: 791b ldrb r3, [r3, #4] 8001cac: 2202 movs r2, #2 8001cae: 4013 ands r3, r2 8001cb0: b2db uxtb r3, r3 8001cb2: 2b00 cmp r3, #0 8001cb4: d005 beq.n 8001cc2 { l_buff|=0x10; 8001cb6: 1dbb adds r3, r7, #6 8001cb8: 1dba adds r2, r7, #6 8001cba: 7812 ldrb r2, [r2, #0] 8001cbc: 2110 movs r1, #16 8001cbe: 430a orrs r2, r1 8001cc0: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001cc2: 1dbb adds r3, r7, #6 8001cc4: 781a ldrb r2, [r3, #0] 8001cc6: 1dfb adds r3, r7, #7 8001cc8: 781b ldrb r3, [r3, #0] 8001cca: 0011 movs r1, r2 8001ccc: 0018 movs r0, r3 8001cce: f7ff ff17 bl 8001b00 h_buff=0,l_buff=0; 8001cd2: 1dfb adds r3, r7, #7 8001cd4: 2200 movs r2, #0 8001cd6: 701a strb r2, [r3, #0] 8001cd8: 1dbb adds r3, r7, #6 8001cda: 2200 movs r2, #0 8001cdc: 701a strb r2, [r3, #0] Send_to_595(h_buff,l_buff); 8001cde: 1dbb adds r3, r7, #6 8001ce0: 781a ldrb r2, [r3, #0] 8001ce2: 1dfb adds r3, r7, #7 8001ce4: 781b ldrb r3, [r3, #0] 8001ce6: 0011 movs r1, r2 8001ce8: 0018 movs r0, r3 8001cea: f7ff ff09 bl 8001b00 h_buff=~0x40; 8001cee: 1dfb adds r3, r7, #7 8001cf0: 22bf movs r2, #191 ; 0xbf 8001cf2: 701a strb r2, [r3, #0] l_buff=dis_buff.d_num[2]>=10?0:d_num_data[0][dis_buff.d_num[2]]; 8001cf4: 4b47 ldr r3, [pc, #284] ; (8001e14 ) 8001cf6: 789b ldrb r3, [r3, #2] 8001cf8: 2b09 cmp r3, #9 8001cfa: d805 bhi.n 8001d08 8001cfc: 4b45 ldr r3, [pc, #276] ; (8001e14 ) 8001cfe: 789b ldrb r3, [r3, #2] 8001d00: 001a movs r2, r3 8001d02: 4b45 ldr r3, [pc, #276] ; (8001e18 ) 8001d04: 5c9a ldrb r2, [r3, r2] 8001d06: e000 b.n 8001d0a 8001d08: 2200 movs r2, #0 8001d0a: 1dbb adds r3, r7, #6 8001d0c: 701a strb r2, [r3, #0] if(dis_buff.dot3==1) 8001d0e: 4b41 ldr r3, [pc, #260] ; (8001e14 ) 8001d10: 791b ldrb r3, [r3, #4] 8001d12: 2204 movs r2, #4 8001d14: 4013 ands r3, r2 8001d16: b2db uxtb r3, r3 8001d18: 2b00 cmp r3, #0 8001d1a: d006 beq.n 8001d2a { l_buff|=0x80; 8001d1c: 1dbb adds r3, r7, #6 8001d1e: 1dba adds r2, r7, #6 8001d20: 7812 ldrb r2, [r2, #0] 8001d22: 2180 movs r1, #128 ; 0x80 8001d24: 4249 negs r1, r1 8001d26: 430a orrs r2, r1 8001d28: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001d2a: 1dbb adds r3, r7, #6 8001d2c: 781a ldrb r2, [r3, #0] 8001d2e: 1dfb adds r3, r7, #7 8001d30: 781b ldrb r3, [r3, #0] 8001d32: 0011 movs r1, r2 8001d34: 0018 movs r0, r3 8001d36: f7ff fee3 bl 8001b00 h_buff=0,l_buff=0; 8001d3a: 1dfb adds r3, r7, #7 8001d3c: 2200 movs r2, #0 8001d3e: 701a strb r2, [r3, #0] 8001d40: 1dbb adds r3, r7, #6 8001d42: 2200 movs r2, #0 8001d44: 701a strb r2, [r3, #0] Send_to_595(h_buff,l_buff); 8001d46: 1dbb adds r3, r7, #6 8001d48: 781a ldrb r2, [r3, #0] 8001d4a: 1dfb adds r3, r7, #7 8001d4c: 781b ldrb r3, [r3, #0] 8001d4e: 0011 movs r1, r2 8001d50: 0018 movs r0, r3 8001d52: f7ff fed5 bl 8001b00 h_buff=0xC1; 8001d56: 1dfb adds r3, r7, #7 8001d58: 22c1 movs r2, #193 ; 0xc1 8001d5a: 701a strb r2, [r3, #0] l_buff=dis_buff.d_num[3]>=10?0:d_num_data[1][dis_buff.d_num[3]]; 8001d5c: 4b2d ldr r3, [pc, #180] ; (8001e14 ) 8001d5e: 78db ldrb r3, [r3, #3] 8001d60: 2b09 cmp r3, #9 8001d62: d806 bhi.n 8001d72 8001d64: 4b2b ldr r3, [pc, #172] ; (8001e14 ) 8001d66: 78db ldrb r3, [r3, #3] 8001d68: 001a movs r2, r3 8001d6a: 4b2b ldr r3, [pc, #172] ; (8001e18 ) 8001d6c: 189b adds r3, r3, r2 8001d6e: 7a9a ldrb r2, [r3, #10] 8001d70: e000 b.n 8001d74 8001d72: 2200 movs r2, #0 8001d74: 1dbb adds r3, r7, #6 8001d76: 701a strb r2, [r3, #0] if(dis_buff.dot4==1) 8001d78: 4b26 ldr r3, [pc, #152] ; (8001e14 ) 8001d7a: 791b ldrb r3, [r3, #4] 8001d7c: 2208 movs r2, #8 8001d7e: 4013 ands r3, r2 8001d80: b2db uxtb r3, r3 8001d82: 2b00 cmp r3, #0 8001d84: d005 beq.n 8001d92 { l_buff|=0x10; 8001d86: 1dbb adds r3, r7, #6 8001d88: 1dba adds r2, r7, #6 8001d8a: 7812 ldrb r2, [r2, #0] 8001d8c: 2110 movs r1, #16 8001d8e: 430a orrs r2, r1 8001d90: 701a strb r2, [r3, #0] } if(dis_buff.led_run==1) 8001d92: 4b20 ldr r3, [pc, #128] ; (8001e14 ) 8001d94: 791b ldrb r3, [r3, #4] 8001d96: 2210 movs r2, #16 8001d98: 4013 ands r3, r2 8001d9a: b2db uxtb r3, r3 8001d9c: 2b00 cmp r3, #0 8001d9e: d005 beq.n 8001dac { h_buff|=0x10; 8001da0: 1dfb adds r3, r7, #7 8001da2: 1dfa adds r2, r7, #7 8001da4: 7812 ldrb r2, [r2, #0] 8001da6: 2110 movs r1, #16 8001da8: 430a orrs r2, r1 8001daa: 701a strb r2, [r3, #0] } if(dis_buff.led_err==1) 8001dac: 4b19 ldr r3, [pc, #100] ; (8001e14 ) 8001dae: 791b ldrb r3, [r3, #4] 8001db0: 227f movs r2, #127 ; 0x7f 8001db2: 4393 bics r3, r2 8001db4: b2db uxtb r3, r3 8001db6: 2b00 cmp r3, #0 8001db8: d005 beq.n 8001dc6 { h_buff|=0x08; 8001dba: 1dfb adds r3, r7, #7 8001dbc: 1dfa adds r2, r7, #7 8001dbe: 7812 ldrb r2, [r2, #0] 8001dc0: 2108 movs r1, #8 8001dc2: 430a orrs r2, r1 8001dc4: 701a strb r2, [r3, #0] } if(dis_buff.led_n==1) 8001dc6: 4b13 ldr r3, [pc, #76] ; (8001e14 ) 8001dc8: 791b ldrb r3, [r3, #4] 8001dca: 2240 movs r2, #64 ; 0x40 8001dcc: 4013 ands r3, r2 8001dce: b2db uxtb r3, r3 8001dd0: 2b00 cmp r3, #0 8001dd2: d005 beq.n 8001de0 { h_buff|=0x04; 8001dd4: 1dfb adds r3, r7, #7 8001dd6: 1dfa adds r2, r7, #7 8001dd8: 7812 ldrb r2, [r2, #0] 8001dda: 2104 movs r1, #4 8001ddc: 430a orrs r2, r1 8001dde: 701a strb r2, [r3, #0] } if(dis_buff.led_p==1) 8001de0: 4b0c ldr r3, [pc, #48] ; (8001e14 ) 8001de2: 791b ldrb r3, [r3, #4] 8001de4: 2220 movs r2, #32 8001de6: 4013 ands r3, r2 8001de8: b2db uxtb r3, r3 8001dea: 2b00 cmp r3, #0 8001dec: d005 beq.n 8001dfa { h_buff|=0x02; 8001dee: 1dfb adds r3, r7, #7 8001df0: 1dfa adds r2, r7, #7 8001df2: 7812 ldrb r2, [r2, #0] 8001df4: 2102 movs r1, #2 8001df6: 430a orrs r2, r1 8001df8: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001dfa: 1dbb adds r3, r7, #6 8001dfc: 781a ldrb r2, [r3, #0] 8001dfe: 1dfb adds r3, r7, #7 8001e00: 781b ldrb r3, [r3, #0] 8001e02: 0011 movs r1, r2 8001e04: 0018 movs r0, r3 8001e06: f7ff fe7b bl 8001b00 } 8001e0a: 46c0 nop ; (mov r8, r8) 8001e0c: 46bd mov sp, r7 8001e0e: b002 add sp, #8 8001e10: bd80 pop {r7, pc} 8001e12: 46c0 nop ; (mov r8, r8) 8001e14: 20000084 .word 0x20000084 8001e18: 08002654 .word 0x08002654 08001e1c : long countdown=0; long countdown_set=15000; void mymain() { 8001e1c: b580 push {r7, lr} 8001e1e: b084 sub sp, #16 8001e20: af00 add r7, sp, #0 uint32_t runtime=0,move=0; 8001e22: 2300 movs r3, #0 8001e24: 60fb str r3, [r7, #12] 8001e26: 2300 movs r3, #0 8001e28: 60bb str r3, [r7, #8] uint8_t mode=0; 8001e2a: 1dfb adds r3, r7, #7 8001e2c: 2200 movs r2, #0 8001e2e: 701a strb r2, [r3, #0] uint16_t adc; MOTA(0); 8001e30: 4be9 ldr r3, [pc, #932] ; (80021d8 ) 8001e32: 2200 movs r2, #0 8001e34: 2101 movs r1, #1 8001e36: 0018 movs r0, r3 8001e38: f7ff f99b bl 8001172 MOTB(0); 8001e3c: 4be6 ldr r3, [pc, #920] ; (80021d8 ) 8001e3e: 2200 movs r2, #0 8001e40: 2102 movs r1, #2 8001e42: 0018 movs r0, r3 8001e44: f7ff f995 bl 8001172 HC595_DCK(0); 8001e48: 2390 movs r3, #144 ; 0x90 8001e4a: 05db lsls r3, r3, #23 8001e4c: 2200 movs r2, #0 8001e4e: 2108 movs r1, #8 8001e50: 0018 movs r0, r3 8001e52: f7ff f98e bl 8001172 HC595_RCK(0); 8001e56: 2390 movs r3, #144 ; 0x90 8001e58: 05db lsls r3, r3, #23 8001e5a: 2200 movs r2, #0 8001e5c: 2110 movs r1, #16 8001e5e: 0018 movs r0, r3 8001e60: f7ff f987 bl 8001172 HC595_SCK(0); 8001e64: 2390 movs r3, #144 ; 0x90 8001e66: 05db lsls r3, r3, #23 8001e68: 2200 movs r2, #0 8001e6a: 2120 movs r1, #32 8001e6c: 0018 movs r0, r3 8001e6e: f7ff f980 bl 8001172 dis_buff.d_num[0]=0xff; 8001e72: 4bda ldr r3, [pc, #872] ; (80021dc ) 8001e74: 22ff movs r2, #255 ; 0xff 8001e76: 701a strb r2, [r3, #0] dis_buff.d_num[1]=0xff; 8001e78: 4bd8 ldr r3, [pc, #864] ; (80021dc ) 8001e7a: 22ff movs r2, #255 ; 0xff 8001e7c: 705a strb r2, [r3, #1] dis_buff.d_num[2]=0xff; 8001e7e: 4bd7 ldr r3, [pc, #860] ; (80021dc ) 8001e80: 22ff movs r2, #255 ; 0xff 8001e82: 709a strb r2, [r3, #2] dis_buff.d_num[3]=0xff; 8001e84: 4bd5 ldr r3, [pc, #852] ; (80021dc ) 8001e86: 22ff movs r2, #255 ; 0xff 8001e88: 70da strb r2, [r3, #3] countdown=1000; 8001e8a: 4bd5 ldr r3, [pc, #852] ; (80021e0 ) 8001e8c: 22fa movs r2, #250 ; 0xfa 8001e8e: 0092 lsls r2, r2, #2 8001e90: 601a str r2, [r3, #0] while(1) { switch(mode) 8001e92: 1dfb adds r3, r7, #7 8001e94: 781b ldrb r3, [r3, #0] 8001e96: 2b04 cmp r3, #4 8001e98: d900 bls.n 8001e9c 8001e9a: e31c b.n 80024d6 8001e9c: 009a lsls r2, r3, #2 8001e9e: 4bd1 ldr r3, [pc, #836] ; (80021e4 ) 8001ea0: 18d3 adds r3, r2, r3 8001ea2: 681b ldr r3, [r3, #0] 8001ea4: 469f mov pc, r3 { case 0: //Startup if(HAL_GetTick()>move) 8001ea6: f7fe fce3 bl 8000870 8001eaa: 0002 movs r2, r0 8001eac: 68bb ldr r3, [r7, #8] 8001eae: 4293 cmp r3, r2 8001eb0: d300 bcc.n 8001eb4 8001eb2: e309 b.n 80024c8 { move=HAL_GetTick()+100; 8001eb4: f7fe fcdc bl 8000870 8001eb8: 0003 movs r3, r0 8001eba: 3364 adds r3, #100 ; 0x64 8001ebc: 60bb str r3, [r7, #8] countdown-=100; 8001ebe: 4bc8 ldr r3, [pc, #800] ; (80021e0 ) 8001ec0: 681b ldr r3, [r3, #0] 8001ec2: 3b64 subs r3, #100 ; 0x64 8001ec4: 001a movs r2, r3 8001ec6: 4bc6 ldr r3, [pc, #792] ; (80021e0 ) 8001ec8: 601a str r2, [r3, #0] if(countdown<0) 8001eca: 4bc5 ldr r3, [pc, #788] ; (80021e0 ) 8001ecc: 681b ldr r3, [r3, #0] 8001ece: 2b00 cmp r3, #0 8001ed0: da02 bge.n 8001ed8 { mode=1; 8001ed2: 1dfb adds r3, r7, #7 8001ed4: 2201 movs r2, #1 8001ed6: 701a strb r2, [r3, #0] } dis_buff.d_num[0]=((countdown/100)%10); 8001ed8: 4bc1 ldr r3, [pc, #772] ; (80021e0 ) 8001eda: 681b ldr r3, [r3, #0] 8001edc: 2164 movs r1, #100 ; 0x64 8001ede: 0018 movs r0, r3 8001ee0: f7fe f99c bl 800021c <__divsi3> 8001ee4: 0003 movs r3, r0 8001ee6: 210a movs r1, #10 8001ee8: 0018 movs r0, r3 8001eea: f7fe fa7d bl 80003e8 <__aeabi_idivmod> 8001eee: 000b movs r3, r1 8001ef0: b2da uxtb r2, r3 8001ef2: 4bba ldr r3, [pc, #744] ; (80021dc ) 8001ef4: 701a strb r2, [r3, #0] dis_buff.d_num[1]=((countdown/100)%10); 8001ef6: 4bba ldr r3, [pc, #744] ; (80021e0 ) 8001ef8: 681b ldr r3, [r3, #0] 8001efa: 2164 movs r1, #100 ; 0x64 8001efc: 0018 movs r0, r3 8001efe: f7fe f98d bl 800021c <__divsi3> 8001f02: 0003 movs r3, r0 8001f04: 210a movs r1, #10 8001f06: 0018 movs r0, r3 8001f08: f7fe fa6e bl 80003e8 <__aeabi_idivmod> 8001f0c: 000b movs r3, r1 8001f0e: b2da uxtb r2, r3 8001f10: 4bb2 ldr r3, [pc, #712] ; (80021dc ) 8001f12: 705a strb r2, [r3, #1] dis_buff.d_num[2]=((countdown/100)%10); 8001f14: 4bb2 ldr r3, [pc, #712] ; (80021e0 ) 8001f16: 681b ldr r3, [r3, #0] 8001f18: 2164 movs r1, #100 ; 0x64 8001f1a: 0018 movs r0, r3 8001f1c: f7fe f97e bl 800021c <__divsi3> 8001f20: 0003 movs r3, r0 8001f22: 210a movs r1, #10 8001f24: 0018 movs r0, r3 8001f26: f7fe fa5f bl 80003e8 <__aeabi_idivmod> 8001f2a: 000b movs r3, r1 8001f2c: b2da uxtb r2, r3 8001f2e: 4bab ldr r3, [pc, #684] ; (80021dc ) 8001f30: 709a strb r2, [r3, #2] dis_buff.d_num[3]=((countdown/100)%10); 8001f32: 4bab ldr r3, [pc, #684] ; (80021e0 ) 8001f34: 681b ldr r3, [r3, #0] 8001f36: 2164 movs r1, #100 ; 0x64 8001f38: 0018 movs r0, r3 8001f3a: f7fe f96f bl 800021c <__divsi3> 8001f3e: 0003 movs r3, r0 8001f40: 210a movs r1, #10 8001f42: 0018 movs r0, r3 8001f44: f7fe fa50 bl 80003e8 <__aeabi_idivmod> 8001f48: 000b movs r3, r1 8001f4a: b2da uxtb r2, r3 8001f4c: 4ba3 ldr r3, [pc, #652] ; (80021dc ) 8001f4e: 70da strb r2, [r3, #3] dis_buff.led_err=countdown>>0; 8001f50: 4ba3 ldr r3, [pc, #652] ; (80021e0 ) 8001f52: 681b ldr r3, [r3, #0] 8001f54: 1c1a adds r2, r3, #0 8001f56: 2301 movs r3, #1 8001f58: 4013 ands r3, r2 8001f5a: b2da uxtb r2, r3 8001f5c: 4b9f ldr r3, [pc, #636] ; (80021dc ) 8001f5e: 01d0 lsls r0, r2, #7 8001f60: 791a ldrb r2, [r3, #4] 8001f62: 217f movs r1, #127 ; 0x7f 8001f64: 400a ands r2, r1 8001f66: 1c11 adds r1, r2, #0 8001f68: 1c02 adds r2, r0, #0 8001f6a: 430a orrs r2, r1 8001f6c: 711a strb r2, [r3, #4] dis_buff.led_p=countdown>>1; 8001f6e: 4b9c ldr r3, [pc, #624] ; (80021e0 ) 8001f70: 681b ldr r3, [r3, #0] 8001f72: 105b asrs r3, r3, #1 8001f74: 1c1a adds r2, r3, #0 8001f76: 2301 movs r3, #1 8001f78: 4013 ands r3, r2 8001f7a: b2da uxtb r2, r3 8001f7c: 4b97 ldr r3, [pc, #604] ; (80021dc ) 8001f7e: 2101 movs r1, #1 8001f80: 400a ands r2, r1 8001f82: 0150 lsls r0, r2, #5 8001f84: 791a ldrb r2, [r3, #4] 8001f86: 2120 movs r1, #32 8001f88: 438a bics r2, r1 8001f8a: 1c11 adds r1, r2, #0 8001f8c: 1c02 adds r2, r0, #0 8001f8e: 430a orrs r2, r1 8001f90: 711a strb r2, [r3, #4] dis_buff.led_n=countdown>>2; 8001f92: 4b93 ldr r3, [pc, #588] ; (80021e0 ) 8001f94: 681b ldr r3, [r3, #0] 8001f96: 109b asrs r3, r3, #2 8001f98: 1c1a adds r2, r3, #0 8001f9a: 2301 movs r3, #1 8001f9c: 4013 ands r3, r2 8001f9e: b2da uxtb r2, r3 8001fa0: 4b8e ldr r3, [pc, #568] ; (80021dc ) 8001fa2: 2101 movs r1, #1 8001fa4: 400a ands r2, r1 8001fa6: 0190 lsls r0, r2, #6 8001fa8: 791a ldrb r2, [r3, #4] 8001faa: 2140 movs r1, #64 ; 0x40 8001fac: 438a bics r2, r1 8001fae: 1c11 adds r1, r2, #0 8001fb0: 1c02 adds r2, r0, #0 8001fb2: 430a orrs r2, r1 8001fb4: 711a strb r2, [r3, #4] dis_buff.dot1=countdown>>3; 8001fb6: 4b8a ldr r3, [pc, #552] ; (80021e0 ) 8001fb8: 681b ldr r3, [r3, #0] 8001fba: 10db asrs r3, r3, #3 8001fbc: 1c1a adds r2, r3, #0 8001fbe: 2301 movs r3, #1 8001fc0: 4013 ands r3, r2 8001fc2: b2da uxtb r2, r3 8001fc4: 4b85 ldr r3, [pc, #532] ; (80021dc ) 8001fc6: 2101 movs r1, #1 8001fc8: 400a ands r2, r1 8001fca: 0010 movs r0, r2 8001fcc: 791a ldrb r2, [r3, #4] 8001fce: 2101 movs r1, #1 8001fd0: 438a bics r2, r1 8001fd2: 1c11 adds r1, r2, #0 8001fd4: 1c02 adds r2, r0, #0 8001fd6: 430a orrs r2, r1 8001fd8: 711a strb r2, [r3, #4] dis_buff.dot2=countdown>>4; 8001fda: 4b81 ldr r3, [pc, #516] ; (80021e0 ) 8001fdc: 681b ldr r3, [r3, #0] 8001fde: 111b asrs r3, r3, #4 8001fe0: 1c1a adds r2, r3, #0 8001fe2: 2301 movs r3, #1 8001fe4: 4013 ands r3, r2 8001fe6: b2da uxtb r2, r3 8001fe8: 4b7c ldr r3, [pc, #496] ; (80021dc ) 8001fea: 2101 movs r1, #1 8001fec: 400a ands r2, r1 8001fee: 1890 adds r0, r2, r2 8001ff0: 791a ldrb r2, [r3, #4] 8001ff2: 2102 movs r1, #2 8001ff4: 438a bics r2, r1 8001ff6: 1c11 adds r1, r2, #0 8001ff8: 1c02 adds r2, r0, #0 8001ffa: 430a orrs r2, r1 8001ffc: 711a strb r2, [r3, #4] dis_buff.dot3=countdown>>5; 8001ffe: 4b78 ldr r3, [pc, #480] ; (80021e0 ) 8002000: 681b ldr r3, [r3, #0] 8002002: 115b asrs r3, r3, #5 8002004: 1c1a adds r2, r3, #0 8002006: 2301 movs r3, #1 8002008: 4013 ands r3, r2 800200a: b2da uxtb r2, r3 800200c: 4b73 ldr r3, [pc, #460] ; (80021dc ) 800200e: 2101 movs r1, #1 8002010: 400a ands r2, r1 8002012: 0090 lsls r0, r2, #2 8002014: 791a ldrb r2, [r3, #4] 8002016: 2104 movs r1, #4 8002018: 438a bics r2, r1 800201a: 1c11 adds r1, r2, #0 800201c: 1c02 adds r2, r0, #0 800201e: 430a orrs r2, r1 8002020: 711a strb r2, [r3, #4] dis_buff.dot4=countdown>>6; 8002022: 4b6f ldr r3, [pc, #444] ; (80021e0 ) 8002024: 681b ldr r3, [r3, #0] 8002026: 119b asrs r3, r3, #6 8002028: 1c1a adds r2, r3, #0 800202a: 2301 movs r3, #1 800202c: 4013 ands r3, r2 800202e: b2da uxtb r2, r3 8002030: 4b6a ldr r3, [pc, #424] ; (80021dc ) 8002032: 2101 movs r1, #1 8002034: 400a ands r2, r1 8002036: 00d0 lsls r0, r2, #3 8002038: 791a ldrb r2, [r3, #4] 800203a: 2108 movs r1, #8 800203c: 438a bics r2, r1 800203e: 1c11 adds r1, r2, #0 8002040: 1c02 adds r2, r0, #0 8002042: 430a orrs r2, r1 8002044: 711a strb r2, [r3, #4] } break; 8002046: e23f b.n 80024c8 case 1: //standby MOTA(0); 8002048: 4b63 ldr r3, [pc, #396] ; (80021d8 ) 800204a: 2200 movs r2, #0 800204c: 2101 movs r1, #1 800204e: 0018 movs r0, r3 8002050: f7ff f88f bl 8001172 MOTB(0); 8002054: 4b60 ldr r3, [pc, #384] ; (80021d8 ) 8002056: 2200 movs r2, #0 8002058: 2102 movs r1, #2 800205a: 0018 movs r0, r3 800205c: f7ff f889 bl 8001172 dis_buff.d_num[0]=0xff; 8002060: 4b5e ldr r3, [pc, #376] ; (80021dc ) 8002062: 22ff movs r2, #255 ; 0xff 8002064: 701a strb r2, [r3, #0] dis_buff.d_num[1]=0xff; 8002066: 4b5d ldr r3, [pc, #372] ; (80021dc ) 8002068: 22ff movs r2, #255 ; 0xff 800206a: 705a strb r2, [r3, #1] dis_buff.d_num[2]=0xff; 800206c: 4b5b ldr r3, [pc, #364] ; (80021dc ) 800206e: 22ff movs r2, #255 ; 0xff 8002070: 709a strb r2, [r3, #2] dis_buff.d_num[3]=0xff; 8002072: 4b5a ldr r3, [pc, #360] ; (80021dc ) 8002074: 22ff movs r2, #255 ; 0xff 8002076: 70da strb r2, [r3, #3] dis_buff.led_err=0; 8002078: 4b58 ldr r3, [pc, #352] ; (80021dc ) 800207a: 791a ldrb r2, [r3, #4] 800207c: 217f movs r1, #127 ; 0x7f 800207e: 400a ands r2, r1 8002080: 711a strb r2, [r3, #4] dis_buff.led_p=0; 8002082: 4b56 ldr r3, [pc, #344] ; (80021dc ) 8002084: 791a ldrb r2, [r3, #4] 8002086: 2120 movs r1, #32 8002088: 438a bics r2, r1 800208a: 711a strb r2, [r3, #4] dis_buff.led_n=0; 800208c: 4b53 ldr r3, [pc, #332] ; (80021dc ) 800208e: 791a ldrb r2, [r3, #4] 8002090: 2140 movs r1, #64 ; 0x40 8002092: 438a bics r2, r1 8002094: 711a strb r2, [r3, #4] dis_buff.dot1=0; 8002096: 4b51 ldr r3, [pc, #324] ; (80021dc ) 8002098: 791a ldrb r2, [r3, #4] 800209a: 2101 movs r1, #1 800209c: 438a bics r2, r1 800209e: 711a strb r2, [r3, #4] dis_buff.dot2=0; 80020a0: 4b4e ldr r3, [pc, #312] ; (80021dc ) 80020a2: 791a ldrb r2, [r3, #4] 80020a4: 2102 movs r1, #2 80020a6: 438a bics r2, r1 80020a8: 711a strb r2, [r3, #4] dis_buff.dot3=0; 80020aa: 4b4c ldr r3, [pc, #304] ; (80021dc ) 80020ac: 791a ldrb r2, [r3, #4] 80020ae: 2104 movs r1, #4 80020b0: 438a bics r2, r1 80020b2: 711a strb r2, [r3, #4] dis_buff.dot4=0; 80020b4: 4b49 ldr r3, [pc, #292] ; (80021dc ) 80020b6: 791a ldrb r2, [r3, #4] 80020b8: 2108 movs r1, #8 80020ba: 438a bics r2, r1 80020bc: 711a strb r2, [r3, #4] if(key2.code!=0) 80020be: 4b4a ldr r3, [pc, #296] ; (80021e8 ) 80020c0: 681b ldr r3, [r3, #0] 80020c2: 2b00 cmp r3, #0 80020c4: d006 beq.n 80020d4 { mode=2; 80020c6: 1dfb adds r3, r7, #7 80020c8: 2202 movs r2, #2 80020ca: 701a strb r2, [r3, #0] countdown=countdown_set; 80020cc: 4b47 ldr r3, [pc, #284] ; (80021ec ) 80020ce: 681a ldr r2, [r3, #0] 80020d0: 4b43 ldr r3, [pc, #268] ; (80021e0 ) 80020d2: 601a str r2, [r3, #0] } if(key3.code!=0) 80020d4: 4b46 ldr r3, [pc, #280] ; (80021f0 ) 80020d6: 681b ldr r3, [r3, #0] 80020d8: 2b00 cmp r3, #0 80020da: d006 beq.n 80020ea { mode=3; 80020dc: 1dfb adds r3, r7, #7 80020de: 2203 movs r2, #3 80020e0: 701a strb r2, [r3, #0] countdown=countdown_set; 80020e2: 4b42 ldr r3, [pc, #264] ; (80021ec ) 80020e4: 681a ldr r2, [r3, #0] 80020e6: 4b3e ldr r3, [pc, #248] ; (80021e0 ) 80020e8: 601a str r2, [r3, #0] } if(key1.code!=0) 80020ea: 4b42 ldr r3, [pc, #264] ; (80021f4 ) 80020ec: 681b ldr r3, [r3, #0] 80020ee: 2b00 cmp r3, #0 80020f0: d100 bne.n 80020f4 80020f2: e1eb b.n 80024cc { mode=4; 80020f4: 1dfb adds r3, r7, #7 80020f6: 2204 movs r2, #4 80020f8: 701a strb r2, [r3, #0] countdown=10000; 80020fa: 4b39 ldr r3, [pc, #228] ; (80021e0 ) 80020fc: 4a3e ldr r2, [pc, #248] ; (80021f8 ) 80020fe: 601a str r2, [r3, #0] } break; 8002100: e1e4 b.n 80024cc case 2: MOTA(0); 8002102: 4b35 ldr r3, [pc, #212] ; (80021d8 ) 8002104: 2200 movs r2, #0 8002106: 2101 movs r1, #1 8002108: 0018 movs r0, r3 800210a: f7ff f832 bl 8001172 MOTB(1); 800210e: 4b32 ldr r3, [pc, #200] ; (80021d8 ) 8002110: 2201 movs r2, #1 8002112: 2102 movs r1, #2 8002114: 0018 movs r0, r3 8002116: f7ff f82c bl 8001172 if(HAL_GetTick()>move) 800211a: f7fe fba9 bl 8000870 800211e: 0002 movs r2, r0 8002120: 68bb ldr r3, [r7, #8] 8002122: 4293 cmp r3, r2 8002124: d223 bcs.n 800216e { move=HAL_GetTick()+100; 8002126: f7fe fba3 bl 8000870 800212a: 0003 movs r3, r0 800212c: 3364 adds r3, #100 ; 0x64 800212e: 60bb str r3, [r7, #8] if(dis_buff.led_p==1) 8002130: 4b2a ldr r3, [pc, #168] ; (80021dc ) 8002132: 791b ldrb r3, [r3, #4] 8002134: 2220 movs r2, #32 8002136: 4013 ands r3, r2 8002138: b2db uxtb r3, r3 800213a: 2b00 cmp r3, #0 800213c: d005 beq.n 800214a { dis_buff.led_p=0; 800213e: 4b27 ldr r3, [pc, #156] ; (80021dc ) 8002140: 791a ldrb r2, [r3, #4] 8002142: 2120 movs r1, #32 8002144: 438a bics r2, r1 8002146: 711a strb r2, [r3, #4] 8002148: e004 b.n 8002154 }else { dis_buff.led_p=1; 800214a: 4b24 ldr r3, [pc, #144] ; (80021dc ) 800214c: 791a ldrb r2, [r3, #4] 800214e: 2120 movs r1, #32 8002150: 430a orrs r2, r1 8002152: 711a strb r2, [r3, #4] } countdown-=100; 8002154: 4b22 ldr r3, [pc, #136] ; (80021e0 ) 8002156: 681b ldr r3, [r3, #0] 8002158: 3b64 subs r3, #100 ; 0x64 800215a: 001a movs r2, r3 800215c: 4b20 ldr r3, [pc, #128] ; (80021e0 ) 800215e: 601a str r2, [r3, #0] if(countdown<0) 8002160: 4b1f ldr r3, [pc, #124] ; (80021e0 ) 8002162: 681b ldr r3, [r3, #0] 8002164: 2b00 cmp r3, #0 8002166: da02 bge.n 800216e { mode=1; 8002168: 1dfb adds r3, r7, #7 800216a: 2201 movs r2, #1 800216c: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 800216e: 4b1c ldr r3, [pc, #112] ; (80021e0 ) 8002170: 681b ldr r3, [r3, #0] 8002172: 2164 movs r1, #100 ; 0x64 8002174: 0018 movs r0, r3 8002176: f7fe f851 bl 800021c <__divsi3> 800217a: 0003 movs r3, r0 800217c: 210a movs r1, #10 800217e: 0018 movs r0, r3 8002180: f7fe f932 bl 80003e8 <__aeabi_idivmod> 8002184: 000b movs r3, r1 8002186: b2da uxtb r2, r3 8002188: 4b14 ldr r3, [pc, #80] ; (80021dc ) 800218a: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 800218c: 4b14 ldr r3, [pc, #80] ; (80021e0 ) 800218e: 681b ldr r3, [r3, #0] 8002190: 22fa movs r2, #250 ; 0xfa 8002192: 0091 lsls r1, r2, #2 8002194: 0018 movs r0, r3 8002196: f7fe f841 bl 800021c <__divsi3> 800219a: 0003 movs r3, r0 800219c: 210a movs r1, #10 800219e: 0018 movs r0, r3 80021a0: f7fe f922 bl 80003e8 <__aeabi_idivmod> 80021a4: 000b movs r3, r1 80021a6: b2da uxtb r2, r3 80021a8: 4b0c ldr r3, [pc, #48] ; (80021dc ) 80021aa: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 80021ac: 4b0c ldr r3, [pc, #48] ; (80021e0 ) 80021ae: 681b ldr r3, [r3, #0] 80021b0: 4911 ldr r1, [pc, #68] ; (80021f8 ) 80021b2: 0018 movs r0, r3 80021b4: f7fe f832 bl 800021c <__divsi3> 80021b8: 0003 movs r3, r0 80021ba: 210a movs r1, #10 80021bc: 0018 movs r0, r3 80021be: f7fe f913 bl 80003e8 <__aeabi_idivmod> 80021c2: 000b movs r3, r1 80021c4: b2da uxtb r2, r3 80021c6: 4b05 ldr r3, [pc, #20] ; (80021dc ) 80021c8: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1]; 80021ca: 4b04 ldr r3, [pc, #16] ; (80021dc ) 80021cc: 785b ldrb r3, [r3, #1] 80021ce: 2b00 cmp r3, #0 80021d0: d014 beq.n 80021fc 80021d2: 4b02 ldr r3, [pc, #8] ; (80021dc ) 80021d4: 785a ldrb r2, [r3, #1] 80021d6: e012 b.n 80021fe 80021d8: 48001400 .word 0x48001400 80021dc: 20000084 .word 0x20000084 80021e0: 2000002c .word 0x2000002c 80021e4: 08002668 .word 0x08002668 80021e8: 200000ac .word 0x200000ac 80021ec: 2000000c .word 0x2000000c 80021f0: 2000009c .word 0x2000009c 80021f4: 2000008c .word 0x2000008c 80021f8: 00002710 .word 0x00002710 80021fc: 22ff movs r2, #255 ; 0xff 80021fe: 4be2 ldr r3, [pc, #904] ; (8002588 ) 8002200: 705a strb r2, [r3, #1] dis_buff.dot3=1; 8002202: 4be1 ldr r3, [pc, #900] ; (8002588 ) 8002204: 791a ldrb r2, [r3, #4] 8002206: 2104 movs r1, #4 8002208: 430a orrs r2, r1 800220a: 711a strb r2, [r3, #4] dis_buff.led_n=0; 800220c: 4bde ldr r3, [pc, #888] ; (8002588 ) 800220e: 791a ldrb r2, [r3, #4] 8002210: 2140 movs r1, #64 ; 0x40 8002212: 438a bics r2, r1 8002214: 711a strb r2, [r3, #4] if(key3.code!=0) 8002216: 4bdd ldr r3, [pc, #884] ; (800258c ) 8002218: 681b ldr r3, [r3, #0] 800221a: 2b00 cmp r3, #0 800221c: d009 beq.n 8002232 { mode=3; 800221e: 1dfb adds r3, r7, #7 8002220: 2203 movs r2, #3 8002222: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 8002224: 4bda ldr r3, [pc, #872] ; (8002590 ) 8002226: 681a ldr r2, [r3, #0] 8002228: 4bda ldr r3, [pc, #872] ; (8002594 ) 800222a: 681b ldr r3, [r3, #0] 800222c: 1ad2 subs r2, r2, r3 800222e: 4bd9 ldr r3, [pc, #868] ; (8002594 ) 8002230: 601a str r2, [r3, #0] } if(key4.code!=0) 8002232: 4bd9 ldr r3, [pc, #868] ; (8002598 ) 8002234: 681b ldr r3, [r3, #0] 8002236: 2b00 cmp r3, #0 8002238: d100 bne.n 800223c 800223a: e149 b.n 80024d0 { mode=1; 800223c: 1dfb adds r3, r7, #7 800223e: 2201 movs r2, #1 8002240: 701a strb r2, [r3, #0] } break; 8002242: e145 b.n 80024d0 case 3: MOTB(0); 8002244: 4bd5 ldr r3, [pc, #852] ; (800259c ) 8002246: 2200 movs r2, #0 8002248: 2102 movs r1, #2 800224a: 0018 movs r0, r3 800224c: f7fe ff91 bl 8001172 MOTA(1); 8002250: 4bd2 ldr r3, [pc, #840] ; (800259c ) 8002252: 2201 movs r2, #1 8002254: 2101 movs r1, #1 8002256: 0018 movs r0, r3 8002258: f7fe ff8b bl 8001172 if(HAL_GetTick()>move) 800225c: f7fe fb08 bl 8000870 8002260: 0002 movs r2, r0 8002262: 68bb ldr r3, [r7, #8] 8002264: 4293 cmp r3, r2 8002266: d223 bcs.n 80022b0 { move=HAL_GetTick()+100; 8002268: f7fe fb02 bl 8000870 800226c: 0003 movs r3, r0 800226e: 3364 adds r3, #100 ; 0x64 8002270: 60bb str r3, [r7, #8] if(dis_buff.led_n==1) 8002272: 4bc5 ldr r3, [pc, #788] ; (8002588 ) 8002274: 791b ldrb r3, [r3, #4] 8002276: 2240 movs r2, #64 ; 0x40 8002278: 4013 ands r3, r2 800227a: b2db uxtb r3, r3 800227c: 2b00 cmp r3, #0 800227e: d005 beq.n 800228c { dis_buff.led_n=0; 8002280: 4bc1 ldr r3, [pc, #772] ; (8002588 ) 8002282: 791a ldrb r2, [r3, #4] 8002284: 2140 movs r1, #64 ; 0x40 8002286: 438a bics r2, r1 8002288: 711a strb r2, [r3, #4] 800228a: e004 b.n 8002296 }else { dis_buff.led_n=1; 800228c: 4bbe ldr r3, [pc, #760] ; (8002588 ) 800228e: 791a ldrb r2, [r3, #4] 8002290: 2140 movs r1, #64 ; 0x40 8002292: 430a orrs r2, r1 8002294: 711a strb r2, [r3, #4] } countdown-=100; 8002296: 4bbf ldr r3, [pc, #764] ; (8002594 ) 8002298: 681b ldr r3, [r3, #0] 800229a: 3b64 subs r3, #100 ; 0x64 800229c: 001a movs r2, r3 800229e: 4bbd ldr r3, [pc, #756] ; (8002594 ) 80022a0: 601a str r2, [r3, #0] if(countdown<0) 80022a2: 4bbc ldr r3, [pc, #752] ; (8002594 ) 80022a4: 681b ldr r3, [r3, #0] 80022a6: 2b00 cmp r3, #0 80022a8: da02 bge.n 80022b0 { mode=1; 80022aa: 1dfb adds r3, r7, #7 80022ac: 2201 movs r2, #1 80022ae: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 80022b0: 4bb8 ldr r3, [pc, #736] ; (8002594 ) 80022b2: 681b ldr r3, [r3, #0] 80022b4: 2164 movs r1, #100 ; 0x64 80022b6: 0018 movs r0, r3 80022b8: f7fd ffb0 bl 800021c <__divsi3> 80022bc: 0003 movs r3, r0 80022be: 210a movs r1, #10 80022c0: 0018 movs r0, r3 80022c2: f7fe f891 bl 80003e8 <__aeabi_idivmod> 80022c6: 000b movs r3, r1 80022c8: b2da uxtb r2, r3 80022ca: 4baf ldr r3, [pc, #700] ; (8002588 ) 80022cc: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 80022ce: 4bb1 ldr r3, [pc, #708] ; (8002594 ) 80022d0: 681b ldr r3, [r3, #0] 80022d2: 22fa movs r2, #250 ; 0xfa 80022d4: 0091 lsls r1, r2, #2 80022d6: 0018 movs r0, r3 80022d8: f7fd ffa0 bl 800021c <__divsi3> 80022dc: 0003 movs r3, r0 80022de: 210a movs r1, #10 80022e0: 0018 movs r0, r3 80022e2: f7fe f881 bl 80003e8 <__aeabi_idivmod> 80022e6: 000b movs r3, r1 80022e8: b2da uxtb r2, r3 80022ea: 4ba7 ldr r3, [pc, #668] ; (8002588 ) 80022ec: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 80022ee: 4ba9 ldr r3, [pc, #676] ; (8002594 ) 80022f0: 681b ldr r3, [r3, #0] 80022f2: 49ab ldr r1, [pc, #684] ; (80025a0 ) 80022f4: 0018 movs r0, r3 80022f6: f7fd ff91 bl 800021c <__divsi3> 80022fa: 0003 movs r3, r0 80022fc: 210a movs r1, #10 80022fe: 0018 movs r0, r3 8002300: f7fe f872 bl 80003e8 <__aeabi_idivmod> 8002304: 000b movs r3, r1 8002306: b2da uxtb r2, r3 8002308: 4b9f ldr r3, [pc, #636] ; (8002588 ) 800230a: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1]; 800230c: 4b9e ldr r3, [pc, #632] ; (8002588 ) 800230e: 785b ldrb r3, [r3, #1] 8002310: 2b00 cmp r3, #0 8002312: d002 beq.n 800231a 8002314: 4b9c ldr r3, [pc, #624] ; (8002588 ) 8002316: 785a ldrb r2, [r3, #1] 8002318: e000 b.n 800231c 800231a: 22ff movs r2, #255 ; 0xff 800231c: 4b9a ldr r3, [pc, #616] ; (8002588 ) 800231e: 705a strb r2, [r3, #1] dis_buff.dot3=1; 8002320: 4b99 ldr r3, [pc, #612] ; (8002588 ) 8002322: 791a ldrb r2, [r3, #4] 8002324: 2104 movs r1, #4 8002326: 430a orrs r2, r1 8002328: 711a strb r2, [r3, #4] dis_buff.led_p=0; 800232a: 4b97 ldr r3, [pc, #604] ; (8002588 ) 800232c: 791a ldrb r2, [r3, #4] 800232e: 2120 movs r1, #32 8002330: 438a bics r2, r1 8002332: 711a strb r2, [r3, #4] if(key2.code!=0) 8002334: 4b9b ldr r3, [pc, #620] ; (80025a4 ) 8002336: 681b ldr r3, [r3, #0] 8002338: 2b00 cmp r3, #0 800233a: d009 beq.n 8002350 { mode=2; 800233c: 1dfb adds r3, r7, #7 800233e: 2202 movs r2, #2 8002340: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 8002342: 4b93 ldr r3, [pc, #588] ; (8002590 ) 8002344: 681a ldr r2, [r3, #0] 8002346: 4b93 ldr r3, [pc, #588] ; (8002594 ) 8002348: 681b ldr r3, [r3, #0] 800234a: 1ad2 subs r2, r2, r3 800234c: 4b91 ldr r3, [pc, #580] ; (8002594 ) 800234e: 601a str r2, [r3, #0] } if(key4.code!=0) 8002350: 4b91 ldr r3, [pc, #580] ; (8002598 ) 8002352: 681b ldr r3, [r3, #0] 8002354: 2b00 cmp r3, #0 8002356: d100 bne.n 800235a 8002358: e0bc b.n 80024d4 { mode=1; 800235a: 1dfb adds r3, r7, #7 800235c: 2201 movs r2, #1 800235e: 701a strb r2, [r3, #0] } break; 8002360: e0b8 b.n 80024d4 case 4: //setting mode if(HAL_GetTick()>move) 8002362: f7fe fa85 bl 8000870 8002366: 0002 movs r2, r0 8002368: 68bb ldr r3, [r7, #8] 800236a: 4293 cmp r3, r2 800236c: d23e bcs.n 80023ec { move=HAL_GetTick()+100; 800236e: f7fe fa7f bl 8000870 8002372: 0003 movs r3, r0 8002374: 3364 adds r3, #100 ; 0x64 8002376: 60bb str r3, [r7, #8] if(dis_buff.dot1==1) 8002378: 4b83 ldr r3, [pc, #524] ; (8002588 ) 800237a: 791b ldrb r3, [r3, #4] 800237c: 2201 movs r2, #1 800237e: 4013 ands r3, r2 8002380: b2db uxtb r3, r3 8002382: 2b00 cmp r3, #0 8002384: d005 beq.n 8002392 { dis_buff.dot1=0; 8002386: 4b80 ldr r3, [pc, #512] ; (8002588 ) 8002388: 791a ldrb r2, [r3, #4] 800238a: 2101 movs r1, #1 800238c: 438a bics r2, r1 800238e: 711a strb r2, [r3, #4] 8002390: e004 b.n 800239c }else { dis_buff.dot1=1; 8002392: 4b7d ldr r3, [pc, #500] ; (8002588 ) 8002394: 791a ldrb r2, [r3, #4] 8002396: 2101 movs r1, #1 8002398: 430a orrs r2, r1 800239a: 711a strb r2, [r3, #4] } countdown-=100; 800239c: 4b7d ldr r3, [pc, #500] ; (8002594 ) 800239e: 681b ldr r3, [r3, #0] 80023a0: 3b64 subs r3, #100 ; 0x64 80023a2: 001a movs r2, r3 80023a4: 4b7b ldr r3, [pc, #492] ; (8002594 ) 80023a6: 601a str r2, [r3, #0] if(countdown<0) 80023a8: 4b7a ldr r3, [pc, #488] ; (8002594 ) 80023aa: 681b ldr r3, [r3, #0] 80023ac: 2b00 cmp r3, #0 80023ae: da02 bge.n 80023b6 { mode=1; 80023b0: 1dfb adds r3, r7, #7 80023b2: 2201 movs r2, #1 80023b4: 701a strb r2, [r3, #0] } if(key2.code<0){countdown_set+=1000;countdown=10000;} 80023b6: 4b7b ldr r3, [pc, #492] ; (80025a4 ) 80023b8: 681b ldr r3, [r3, #0] 80023ba: 2b00 cmp r3, #0 80023bc: da09 bge.n 80023d2 80023be: 4b74 ldr r3, [pc, #464] ; (8002590 ) 80023c0: 681b ldr r3, [r3, #0] 80023c2: 22fa movs r2, #250 ; 0xfa 80023c4: 0092 lsls r2, r2, #2 80023c6: 189a adds r2, r3, r2 80023c8: 4b71 ldr r3, [pc, #452] ; (8002590 ) 80023ca: 601a str r2, [r3, #0] 80023cc: 4b71 ldr r3, [pc, #452] ; (8002594 ) 80023ce: 4a74 ldr r2, [pc, #464] ; (80025a0 ) 80023d0: 601a str r2, [r3, #0] if(key3.code<0){countdown_set-=1000;countdown=10000;} 80023d2: 4b6e ldr r3, [pc, #440] ; (800258c ) 80023d4: 681b ldr r3, [r3, #0] 80023d6: 2b00 cmp r3, #0 80023d8: da08 bge.n 80023ec 80023da: 4b6d ldr r3, [pc, #436] ; (8002590 ) 80023dc: 681b ldr r3, [r3, #0] 80023de: 4a72 ldr r2, [pc, #456] ; (80025a8 ) 80023e0: 189a adds r2, r3, r2 80023e2: 4b6b ldr r3, [pc, #428] ; (8002590 ) 80023e4: 601a str r2, [r3, #0] 80023e6: 4b6b ldr r3, [pc, #428] ; (8002594 ) 80023e8: 4a6d ldr r2, [pc, #436] ; (80025a0 ) 80023ea: 601a str r2, [r3, #0] } if(key2.code>0){countdown_set+=100;countdown=10000;} 80023ec: 4b6d ldr r3, [pc, #436] ; (80025a4 ) 80023ee: 681b ldr r3, [r3, #0] 80023f0: 2b00 cmp r3, #0 80023f2: dd08 ble.n 8002406 80023f4: 4b66 ldr r3, [pc, #408] ; (8002590 ) 80023f6: 681b ldr r3, [r3, #0] 80023f8: 3364 adds r3, #100 ; 0x64 80023fa: 001a movs r2, r3 80023fc: 4b64 ldr r3, [pc, #400] ; (8002590 ) 80023fe: 601a str r2, [r3, #0] 8002400: 4b64 ldr r3, [pc, #400] ; (8002594 ) 8002402: 4a67 ldr r2, [pc, #412] ; (80025a0 ) 8002404: 601a str r2, [r3, #0] if(key3.code>0){countdown_set-=100;countdown=10000;} 8002406: 4b61 ldr r3, [pc, #388] ; (800258c ) 8002408: 681b ldr r3, [r3, #0] 800240a: 2b00 cmp r3, #0 800240c: dd08 ble.n 8002420 800240e: 4b60 ldr r3, [pc, #384] ; (8002590 ) 8002410: 681b ldr r3, [r3, #0] 8002412: 3b64 subs r3, #100 ; 0x64 8002414: 001a movs r2, r3 8002416: 4b5e ldr r3, [pc, #376] ; (8002590 ) 8002418: 601a str r2, [r3, #0] 800241a: 4b5e ldr r3, [pc, #376] ; (8002594 ) 800241c: 4a60 ldr r2, [pc, #384] ; (80025a0 ) 800241e: 601a str r2, [r3, #0] if(countdown_set<100){countdown_set=100;} 8002420: 4b5b ldr r3, [pc, #364] ; (8002590 ) 8002422: 681b ldr r3, [r3, #0] 8002424: 2b63 cmp r3, #99 ; 0x63 8002426: dc02 bgt.n 800242e 8002428: 4b59 ldr r3, [pc, #356] ; (8002590 ) 800242a: 2264 movs r2, #100 ; 0x64 800242c: 601a str r2, [r3, #0] if(countdown_set>60000){countdown_set=60000;} 800242e: 4b58 ldr r3, [pc, #352] ; (8002590 ) 8002430: 681b ldr r3, [r3, #0] 8002432: 4a5e ldr r2, [pc, #376] ; (80025ac ) 8002434: 4293 cmp r3, r2 8002436: dd02 ble.n 800243e 8002438: 4b55 ldr r3, [pc, #340] ; (8002590 ) 800243a: 4a5c ldr r2, [pc, #368] ; (80025ac ) 800243c: 601a str r2, [r3, #0] if(key1.code!=0){mode=1;} 800243e: 4b5c ldr r3, [pc, #368] ; (80025b0 ) 8002440: 681b ldr r3, [r3, #0] 8002442: 2b00 cmp r3, #0 8002444: d002 beq.n 800244c 8002446: 1dfb adds r3, r7, #7 8002448: 2201 movs r2, #1 800244a: 701a strb r2, [r3, #0] dis_buff.d_num[3]=(countdown_set/100)%10; 800244c: 4b50 ldr r3, [pc, #320] ; (8002590 ) 800244e: 681b ldr r3, [r3, #0] 8002450: 2164 movs r1, #100 ; 0x64 8002452: 0018 movs r0, r3 8002454: f7fd fee2 bl 800021c <__divsi3> 8002458: 0003 movs r3, r0 800245a: 210a movs r1, #10 800245c: 0018 movs r0, r3 800245e: f7fd ffc3 bl 80003e8 <__aeabi_idivmod> 8002462: 000b movs r3, r1 8002464: b2da uxtb r2, r3 8002466: 4b48 ldr r3, [pc, #288] ; (8002588 ) 8002468: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown_set/1000)%10; 800246a: 4b49 ldr r3, [pc, #292] ; (8002590 ) 800246c: 681b ldr r3, [r3, #0] 800246e: 22fa movs r2, #250 ; 0xfa 8002470: 0091 lsls r1, r2, #2 8002472: 0018 movs r0, r3 8002474: f7fd fed2 bl 800021c <__divsi3> 8002478: 0003 movs r3, r0 800247a: 210a movs r1, #10 800247c: 0018 movs r0, r3 800247e: f7fd ffb3 bl 80003e8 <__aeabi_idivmod> 8002482: 000b movs r3, r1 8002484: b2da uxtb r2, r3 8002486: 4b40 ldr r3, [pc, #256] ; (8002588 ) 8002488: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown_set/10000)%10); 800248a: 4b41 ldr r3, [pc, #260] ; (8002590 ) 800248c: 681b ldr r3, [r3, #0] 800248e: 4944 ldr r1, [pc, #272] ; (80025a0 ) 8002490: 0018 movs r0, r3 8002492: f7fd fec3 bl 800021c <__divsi3> 8002496: 0003 movs r3, r0 8002498: 210a movs r1, #10 800249a: 0018 movs r0, r3 800249c: f7fd ffa4 bl 80003e8 <__aeabi_idivmod> 80024a0: 000b movs r3, r1 80024a2: b2da uxtb r2, r3 80024a4: 4b38 ldr r3, [pc, #224] ; (8002588 ) 80024a6: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1]; 80024a8: 4b37 ldr r3, [pc, #220] ; (8002588 ) 80024aa: 785b ldrb r3, [r3, #1] 80024ac: 2b00 cmp r3, #0 80024ae: d002 beq.n 80024b6 80024b0: 4b35 ldr r3, [pc, #212] ; (8002588 ) 80024b2: 785a ldrb r2, [r3, #1] 80024b4: e000 b.n 80024b8 80024b6: 22ff movs r2, #255 ; 0xff 80024b8: 4b33 ldr r3, [pc, #204] ; (8002588 ) 80024ba: 705a strb r2, [r3, #1] dis_buff.dot3=1; 80024bc: 4b32 ldr r3, [pc, #200] ; (8002588 ) 80024be: 791a ldrb r2, [r3, #4] 80024c0: 2104 movs r1, #4 80024c2: 430a orrs r2, r1 80024c4: 711a strb r2, [r3, #4] break; 80024c6: e006 b.n 80024d6 break; 80024c8: 46c0 nop ; (mov r8, r8) 80024ca: e004 b.n 80024d6 break; 80024cc: 46c0 nop ; (mov r8, r8) 80024ce: e002 b.n 80024d6 break; 80024d0: 46c0 nop ; (mov r8, r8) 80024d2: e000 b.n 80024d6 break; 80024d4: 46c0 nop ; (mov r8, r8) } if(HAL_GetTick()>runtime) 80024d6: f7fe f9cb bl 8000870 80024da: 0002 movs r2, r0 80024dc: 68fb ldr r3, [r7, #12] 80024de: 4293 cmp r3, r2 80024e0: d217 bcs.n 8002512 { runtime+=1000; 80024e2: 68fb ldr r3, [r7, #12] 80024e4: 22fa movs r2, #250 ; 0xfa 80024e6: 0092 lsls r2, r2, #2 80024e8: 4694 mov ip, r2 80024ea: 4463 add r3, ip 80024ec: 60fb str r3, [r7, #12] dis_buff.led_err=rand()%2; dis_buff.led_n=rand()%2; dis_buff.led_p=rand()%2; dis_buff.led_run=rand()%2; */ if(dis_buff.led_run==1) 80024ee: 4b26 ldr r3, [pc, #152] ; (8002588 ) 80024f0: 791b ldrb r3, [r3, #4] 80024f2: 2210 movs r2, #16 80024f4: 4013 ands r3, r2 80024f6: b2db uxtb r3, r3 80024f8: 2b00 cmp r3, #0 80024fa: d005 beq.n 8002508 { dis_buff.led_run=0; 80024fc: 4b22 ldr r3, [pc, #136] ; (8002588 ) 80024fe: 791a ldrb r2, [r3, #4] 8002500: 2110 movs r1, #16 8002502: 438a bics r2, r1 8002504: 711a strb r2, [r3, #4] 8002506: e004 b.n 8002512 }else { dis_buff.led_run=1; 8002508: 4b1f ldr r3, [pc, #124] ; (8002588 ) 800250a: 791a ldrb r2, [r3, #4] 800250c: 2110 movs r1, #16 800250e: 430a orrs r2, r1 8002510: 711a strb r2, [r3, #4] } } GEI_BUTTON_CODE(&key1,KEY1); 8002512: 2390 movs r3, #144 ; 0x90 8002514: 05db lsls r3, r3, #23 8002516: 2180 movs r1, #128 ; 0x80 8002518: 0018 movs r0, r3 800251a: f7fe fe0d bl 8001138 800251e: 0003 movs r3, r0 8002520: 001a movs r2, r3 8002522: 4b23 ldr r3, [pc, #140] ; (80025b0 ) 8002524: 0011 movs r1, r2 8002526: 0018 movs r0, r3 8002528: f7ff fa8c bl 8001a44 GEI_BUTTON_CODE(&key2,KEY2); 800252c: 2380 movs r3, #128 ; 0x80 800252e: 009a lsls r2, r3, #2 8002530: 2390 movs r3, #144 ; 0x90 8002532: 05db lsls r3, r3, #23 8002534: 0011 movs r1, r2 8002536: 0018 movs r0, r3 8002538: f7fe fdfe bl 8001138 800253c: 0003 movs r3, r0 800253e: 001a movs r2, r3 8002540: 4b18 ldr r3, [pc, #96] ; (80025a4 ) 8002542: 0011 movs r1, r2 8002544: 0018 movs r0, r3 8002546: f7ff fa7d bl 8001a44 GEI_BUTTON_CODE(&key3,KEY3); 800254a: 2380 movs r3, #128 ; 0x80 800254c: 00da lsls r2, r3, #3 800254e: 2390 movs r3, #144 ; 0x90 8002550: 05db lsls r3, r3, #23 8002552: 0011 movs r1, r2 8002554: 0018 movs r0, r3 8002556: f7fe fdef bl 8001138 800255a: 0003 movs r3, r0 800255c: 001a movs r2, r3 800255e: 4b0b ldr r3, [pc, #44] ; (800258c ) 8002560: 0011 movs r1, r2 8002562: 0018 movs r0, r3 8002564: f7ff fa6e bl 8001a44 GEI_BUTTON_CODE(&key4,KEY4); 8002568: 2390 movs r3, #144 ; 0x90 800256a: 05db lsls r3, r3, #23 800256c: 2140 movs r1, #64 ; 0x40 800256e: 0018 movs r0, r3 8002570: f7fe fde2 bl 8001138 8002574: 0003 movs r3, r0 8002576: 001a movs r2, r3 8002578: 4b07 ldr r3, [pc, #28] ; (8002598 ) 800257a: 0011 movs r1, r2 800257c: 0018 movs r0, r3 800257e: f7ff fa61 bl 8001a44 display(); 8002582: f7ff fb35 bl 8001bf0 switch(mode) 8002586: e484 b.n 8001e92 8002588: 20000084 .word 0x20000084 800258c: 2000009c .word 0x2000009c 8002590: 2000000c .word 0x2000000c 8002594: 2000002c .word 0x2000002c 8002598: 20000074 .word 0x20000074 800259c: 48001400 .word 0x48001400 80025a0: 00002710 .word 0x00002710 80025a4: 200000ac .word 0x200000ac 80025a8: fffffc18 .word 0xfffffc18 80025ac: 0000ea60 .word 0x0000ea60 80025b0: 2000008c .word 0x2000008c 080025b4 <__libc_init_array>: 80025b4: b570 push {r4, r5, r6, lr} 80025b6: 2600 movs r6, #0 80025b8: 4d0c ldr r5, [pc, #48] ; (80025ec <__libc_init_array+0x38>) 80025ba: 4c0d ldr r4, [pc, #52] ; (80025f0 <__libc_init_array+0x3c>) 80025bc: 1b64 subs r4, r4, r5 80025be: 10a4 asrs r4, r4, #2 80025c0: 42a6 cmp r6, r4 80025c2: d109 bne.n 80025d8 <__libc_init_array+0x24> 80025c4: 2600 movs r6, #0 80025c6: f000 f821 bl 800260c <_init> 80025ca: 4d0a ldr r5, [pc, #40] ; (80025f4 <__libc_init_array+0x40>) 80025cc: 4c0a ldr r4, [pc, #40] ; (80025f8 <__libc_init_array+0x44>) 80025ce: 1b64 subs r4, r4, r5 80025d0: 10a4 asrs r4, r4, #2 80025d2: 42a6 cmp r6, r4 80025d4: d105 bne.n 80025e2 <__libc_init_array+0x2e> 80025d6: bd70 pop {r4, r5, r6, pc} 80025d8: 00b3 lsls r3, r6, #2 80025da: 58eb ldr r3, [r5, r3] 80025dc: 4798 blx r3 80025de: 3601 adds r6, #1 80025e0: e7ee b.n 80025c0 <__libc_init_array+0xc> 80025e2: 00b3 lsls r3, r6, #2 80025e4: 58eb ldr r3, [r5, r3] 80025e6: 4798 blx r3 80025e8: 3601 adds r6, #1 80025ea: e7f2 b.n 80025d2 <__libc_init_array+0x1e> 80025ec: 0800267c .word 0x0800267c 80025f0: 0800267c .word 0x0800267c 80025f4: 0800267c .word 0x0800267c 80025f8: 08002680 .word 0x08002680 080025fc : 80025fc: 0003 movs r3, r0 80025fe: 1882 adds r2, r0, r2 8002600: 4293 cmp r3, r2 8002602: d100 bne.n 8002606 8002604: 4770 bx lr 8002606: 7019 strb r1, [r3, #0] 8002608: 3301 adds r3, #1 800260a: e7f9 b.n 8002600 0800260c <_init>: 800260c: b5f8 push {r3, r4, r5, r6, r7, lr} 800260e: 46c0 nop ; (mov r8, r8) 8002610: bcf8 pop {r3, r4, r5, r6, r7} 8002612: bc08 pop {r3} 8002614: 469e mov lr, r3 8002616: 4770 bx lr 08002618 <_fini>: 8002618: b5f8 push {r3, r4, r5, r6, r7, lr} 800261a: 46c0 nop ; (mov r8, r8) 800261c: bcf8 pop {r3, r4, r5, r6, r7} 800261e: bc08 pop {r3} 8002620: 469e mov lr, r3 8002622: 4770 bx lr