Motor_Controller.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000032d8 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000190 08003398 08003398 00013398 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08003528 08003528 00020070 2**0 CONTENTS 4 .ARM 00000000 08003528 08003528 00020070 2**0 CONTENTS 5 .preinit_array 00000000 08003528 08003528 00020070 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08003528 08003528 00013528 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800352c 0800352c 0001352c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000070 20000000 08003530 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000000b4 20000070 080035a0 00020070 2**2 ALLOC 10 ._user_heap_stack 00000604 20000124 080035a0 00020124 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00020070 2**0 CONTENTS, READONLY 12 .debug_info 000062bf 00000000 00000000 00020098 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001790 00000000 00000000 00026357 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000578 00000000 00000000 00027ae8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 000004a0 00000000 00000000 00028060 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000100ed 00000000 00000000 00028500 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000078cb 00000000 00000000 000385ed 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0005be39 00000000 00000000 0003feb8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 0009bcf1 2**0 CONTENTS, READONLY 20 .debug_frame 00001b40 00000000 00000000 0009bd44 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 20000070 .word 0x20000070 80000e0: 00000000 .word 0x00000000 80000e4: 08003380 .word 0x08003380 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000074 .word 0x20000074 8000104: 08003380 .word 0x08003380 08000108 <__gnu_thumb1_case_shi>: 8000108: b403 push {r0, r1} 800010a: 4671 mov r1, lr 800010c: 0849 lsrs r1, r1, #1 800010e: 0040 lsls r0, r0, #1 8000110: 0049 lsls r1, r1, #1 8000112: 5e09 ldrsh r1, [r1, r0] 8000114: 0049 lsls r1, r1, #1 8000116: 448e add lr, r1 8000118: bc03 pop {r0, r1} 800011a: 4770 bx lr 0800011c <__udivsi3>: 800011c: 2200 movs r2, #0 800011e: 0843 lsrs r3, r0, #1 8000120: 428b cmp r3, r1 8000122: d374 bcc.n 800020e <__udivsi3+0xf2> 8000124: 0903 lsrs r3, r0, #4 8000126: 428b cmp r3, r1 8000128: d35f bcc.n 80001ea <__udivsi3+0xce> 800012a: 0a03 lsrs r3, r0, #8 800012c: 428b cmp r3, r1 800012e: d344 bcc.n 80001ba <__udivsi3+0x9e> 8000130: 0b03 lsrs r3, r0, #12 8000132: 428b cmp r3, r1 8000134: d328 bcc.n 8000188 <__udivsi3+0x6c> 8000136: 0c03 lsrs r3, r0, #16 8000138: 428b cmp r3, r1 800013a: d30d bcc.n 8000158 <__udivsi3+0x3c> 800013c: 22ff movs r2, #255 ; 0xff 800013e: 0209 lsls r1, r1, #8 8000140: ba12 rev r2, r2 8000142: 0c03 lsrs r3, r0, #16 8000144: 428b cmp r3, r1 8000146: d302 bcc.n 800014e <__udivsi3+0x32> 8000148: 1212 asrs r2, r2, #8 800014a: 0209 lsls r1, r1, #8 800014c: d065 beq.n 800021a <__udivsi3+0xfe> 800014e: 0b03 lsrs r3, r0, #12 8000150: 428b cmp r3, r1 8000152: d319 bcc.n 8000188 <__udivsi3+0x6c> 8000154: e000 b.n 8000158 <__udivsi3+0x3c> 8000156: 0a09 lsrs r1, r1, #8 8000158: 0bc3 lsrs r3, r0, #15 800015a: 428b cmp r3, r1 800015c: d301 bcc.n 8000162 <__udivsi3+0x46> 800015e: 03cb lsls r3, r1, #15 8000160: 1ac0 subs r0, r0, r3 8000162: 4152 adcs r2, r2 8000164: 0b83 lsrs r3, r0, #14 8000166: 428b cmp r3, r1 8000168: d301 bcc.n 800016e <__udivsi3+0x52> 800016a: 038b lsls r3, r1, #14 800016c: 1ac0 subs r0, r0, r3 800016e: 4152 adcs r2, r2 8000170: 0b43 lsrs r3, r0, #13 8000172: 428b cmp r3, r1 8000174: d301 bcc.n 800017a <__udivsi3+0x5e> 8000176: 034b lsls r3, r1, #13 8000178: 1ac0 subs r0, r0, r3 800017a: 4152 adcs r2, r2 800017c: 0b03 lsrs r3, r0, #12 800017e: 428b cmp r3, r1 8000180: d301 bcc.n 8000186 <__udivsi3+0x6a> 8000182: 030b lsls r3, r1, #12 8000184: 1ac0 subs r0, r0, r3 8000186: 4152 adcs r2, r2 8000188: 0ac3 lsrs r3, r0, #11 800018a: 428b cmp r3, r1 800018c: d301 bcc.n 8000192 <__udivsi3+0x76> 800018e: 02cb lsls r3, r1, #11 8000190: 1ac0 subs r0, r0, r3 8000192: 4152 adcs r2, r2 8000194: 0a83 lsrs r3, r0, #10 8000196: 428b cmp r3, r1 8000198: d301 bcc.n 800019e <__udivsi3+0x82> 800019a: 028b lsls r3, r1, #10 800019c: 1ac0 subs r0, r0, r3 800019e: 4152 adcs r2, r2 80001a0: 0a43 lsrs r3, r0, #9 80001a2: 428b cmp r3, r1 80001a4: d301 bcc.n 80001aa <__udivsi3+0x8e> 80001a6: 024b lsls r3, r1, #9 80001a8: 1ac0 subs r0, r0, r3 80001aa: 4152 adcs r2, r2 80001ac: 0a03 lsrs r3, r0, #8 80001ae: 428b cmp r3, r1 80001b0: d301 bcc.n 80001b6 <__udivsi3+0x9a> 80001b2: 020b lsls r3, r1, #8 80001b4: 1ac0 subs r0, r0, r3 80001b6: 4152 adcs r2, r2 80001b8: d2cd bcs.n 8000156 <__udivsi3+0x3a> 80001ba: 09c3 lsrs r3, r0, #7 80001bc: 428b cmp r3, r1 80001be: d301 bcc.n 80001c4 <__udivsi3+0xa8> 80001c0: 01cb lsls r3, r1, #7 80001c2: 1ac0 subs r0, r0, r3 80001c4: 4152 adcs r2, r2 80001c6: 0983 lsrs r3, r0, #6 80001c8: 428b cmp r3, r1 80001ca: d301 bcc.n 80001d0 <__udivsi3+0xb4> 80001cc: 018b lsls r3, r1, #6 80001ce: 1ac0 subs r0, r0, r3 80001d0: 4152 adcs r2, r2 80001d2: 0943 lsrs r3, r0, #5 80001d4: 428b cmp r3, r1 80001d6: d301 bcc.n 80001dc <__udivsi3+0xc0> 80001d8: 014b lsls r3, r1, #5 80001da: 1ac0 subs r0, r0, r3 80001dc: 4152 adcs r2, r2 80001de: 0903 lsrs r3, r0, #4 80001e0: 428b cmp r3, r1 80001e2: d301 bcc.n 80001e8 <__udivsi3+0xcc> 80001e4: 010b lsls r3, r1, #4 80001e6: 1ac0 subs r0, r0, r3 80001e8: 4152 adcs r2, r2 80001ea: 08c3 lsrs r3, r0, #3 80001ec: 428b cmp r3, r1 80001ee: d301 bcc.n 80001f4 <__udivsi3+0xd8> 80001f0: 00cb lsls r3, r1, #3 80001f2: 1ac0 subs r0, r0, r3 80001f4: 4152 adcs r2, r2 80001f6: 0883 lsrs r3, r0, #2 80001f8: 428b cmp r3, r1 80001fa: d301 bcc.n 8000200 <__udivsi3+0xe4> 80001fc: 008b lsls r3, r1, #2 80001fe: 1ac0 subs r0, r0, r3 8000200: 4152 adcs r2, r2 8000202: 0843 lsrs r3, r0, #1 8000204: 428b cmp r3, r1 8000206: d301 bcc.n 800020c <__udivsi3+0xf0> 8000208: 004b lsls r3, r1, #1 800020a: 1ac0 subs r0, r0, r3 800020c: 4152 adcs r2, r2 800020e: 1a41 subs r1, r0, r1 8000210: d200 bcs.n 8000214 <__udivsi3+0xf8> 8000212: 4601 mov r1, r0 8000214: 4152 adcs r2, r2 8000216: 4610 mov r0, r2 8000218: 4770 bx lr 800021a: e7ff b.n 800021c <__udivsi3+0x100> 800021c: b501 push {r0, lr} 800021e: 2000 movs r0, #0 8000220: f000 f8f0 bl 8000404 <__aeabi_idiv0> 8000224: bd02 pop {r1, pc} 8000226: 46c0 nop ; (mov r8, r8) 08000228 <__aeabi_uidivmod>: 8000228: 2900 cmp r1, #0 800022a: d0f7 beq.n 800021c <__udivsi3+0x100> 800022c: e776 b.n 800011c <__udivsi3> 800022e: 4770 bx lr 08000230 <__divsi3>: 8000230: 4603 mov r3, r0 8000232: 430b orrs r3, r1 8000234: d47f bmi.n 8000336 <__divsi3+0x106> 8000236: 2200 movs r2, #0 8000238: 0843 lsrs r3, r0, #1 800023a: 428b cmp r3, r1 800023c: d374 bcc.n 8000328 <__divsi3+0xf8> 800023e: 0903 lsrs r3, r0, #4 8000240: 428b cmp r3, r1 8000242: d35f bcc.n 8000304 <__divsi3+0xd4> 8000244: 0a03 lsrs r3, r0, #8 8000246: 428b cmp r3, r1 8000248: d344 bcc.n 80002d4 <__divsi3+0xa4> 800024a: 0b03 lsrs r3, r0, #12 800024c: 428b cmp r3, r1 800024e: d328 bcc.n 80002a2 <__divsi3+0x72> 8000250: 0c03 lsrs r3, r0, #16 8000252: 428b cmp r3, r1 8000254: d30d bcc.n 8000272 <__divsi3+0x42> 8000256: 22ff movs r2, #255 ; 0xff 8000258: 0209 lsls r1, r1, #8 800025a: ba12 rev r2, r2 800025c: 0c03 lsrs r3, r0, #16 800025e: 428b cmp r3, r1 8000260: d302 bcc.n 8000268 <__divsi3+0x38> 8000262: 1212 asrs r2, r2, #8 8000264: 0209 lsls r1, r1, #8 8000266: d065 beq.n 8000334 <__divsi3+0x104> 8000268: 0b03 lsrs r3, r0, #12 800026a: 428b cmp r3, r1 800026c: d319 bcc.n 80002a2 <__divsi3+0x72> 800026e: e000 b.n 8000272 <__divsi3+0x42> 8000270: 0a09 lsrs r1, r1, #8 8000272: 0bc3 lsrs r3, r0, #15 8000274: 428b cmp r3, r1 8000276: d301 bcc.n 800027c <__divsi3+0x4c> 8000278: 03cb lsls r3, r1, #15 800027a: 1ac0 subs r0, r0, r3 800027c: 4152 adcs r2, r2 800027e: 0b83 lsrs r3, r0, #14 8000280: 428b cmp r3, r1 8000282: d301 bcc.n 8000288 <__divsi3+0x58> 8000284: 038b lsls r3, r1, #14 8000286: 1ac0 subs r0, r0, r3 8000288: 4152 adcs r2, r2 800028a: 0b43 lsrs r3, r0, #13 800028c: 428b cmp r3, r1 800028e: d301 bcc.n 8000294 <__divsi3+0x64> 8000290: 034b lsls r3, r1, #13 8000292: 1ac0 subs r0, r0, r3 8000294: 4152 adcs r2, r2 8000296: 0b03 lsrs r3, r0, #12 8000298: 428b cmp r3, r1 800029a: d301 bcc.n 80002a0 <__divsi3+0x70> 800029c: 030b lsls r3, r1, #12 800029e: 1ac0 subs r0, r0, r3 80002a0: 4152 adcs r2, r2 80002a2: 0ac3 lsrs r3, r0, #11 80002a4: 428b cmp r3, r1 80002a6: d301 bcc.n 80002ac <__divsi3+0x7c> 80002a8: 02cb lsls r3, r1, #11 80002aa: 1ac0 subs r0, r0, r3 80002ac: 4152 adcs r2, r2 80002ae: 0a83 lsrs r3, r0, #10 80002b0: 428b cmp r3, r1 80002b2: d301 bcc.n 80002b8 <__divsi3+0x88> 80002b4: 028b lsls r3, r1, #10 80002b6: 1ac0 subs r0, r0, r3 80002b8: 4152 adcs r2, r2 80002ba: 0a43 lsrs r3, r0, #9 80002bc: 428b cmp r3, r1 80002be: d301 bcc.n 80002c4 <__divsi3+0x94> 80002c0: 024b lsls r3, r1, #9 80002c2: 1ac0 subs r0, r0, r3 80002c4: 4152 adcs r2, r2 80002c6: 0a03 lsrs r3, r0, #8 80002c8: 428b cmp r3, r1 80002ca: d301 bcc.n 80002d0 <__divsi3+0xa0> 80002cc: 020b lsls r3, r1, #8 80002ce: 1ac0 subs r0, r0, r3 80002d0: 4152 adcs r2, r2 80002d2: d2cd bcs.n 8000270 <__divsi3+0x40> 80002d4: 09c3 lsrs r3, r0, #7 80002d6: 428b cmp r3, r1 80002d8: d301 bcc.n 80002de <__divsi3+0xae> 80002da: 01cb lsls r3, r1, #7 80002dc: 1ac0 subs r0, r0, r3 80002de: 4152 adcs r2, r2 80002e0: 0983 lsrs r3, r0, #6 80002e2: 428b cmp r3, r1 80002e4: d301 bcc.n 80002ea <__divsi3+0xba> 80002e6: 018b lsls r3, r1, #6 80002e8: 1ac0 subs r0, r0, r3 80002ea: 4152 adcs r2, r2 80002ec: 0943 lsrs r3, r0, #5 80002ee: 428b cmp r3, r1 80002f0: d301 bcc.n 80002f6 <__divsi3+0xc6> 80002f2: 014b lsls r3, r1, #5 80002f4: 1ac0 subs r0, r0, r3 80002f6: 4152 adcs r2, r2 80002f8: 0903 lsrs r3, r0, #4 80002fa: 428b cmp r3, r1 80002fc: d301 bcc.n 8000302 <__divsi3+0xd2> 80002fe: 010b lsls r3, r1, #4 8000300: 1ac0 subs r0, r0, r3 8000302: 4152 adcs r2, r2 8000304: 08c3 lsrs r3, r0, #3 8000306: 428b cmp r3, r1 8000308: d301 bcc.n 800030e <__divsi3+0xde> 800030a: 00cb lsls r3, r1, #3 800030c: 1ac0 subs r0, r0, r3 800030e: 4152 adcs r2, r2 8000310: 0883 lsrs r3, r0, #2 8000312: 428b cmp r3, r1 8000314: d301 bcc.n 800031a <__divsi3+0xea> 8000316: 008b lsls r3, r1, #2 8000318: 1ac0 subs r0, r0, r3 800031a: 4152 adcs r2, r2 800031c: 0843 lsrs r3, r0, #1 800031e: 428b cmp r3, r1 8000320: d301 bcc.n 8000326 <__divsi3+0xf6> 8000322: 004b lsls r3, r1, #1 8000324: 1ac0 subs r0, r0, r3 8000326: 4152 adcs r2, r2 8000328: 1a41 subs r1, r0, r1 800032a: d200 bcs.n 800032e <__divsi3+0xfe> 800032c: 4601 mov r1, r0 800032e: 4152 adcs r2, r2 8000330: 4610 mov r0, r2 8000332: 4770 bx lr 8000334: e05d b.n 80003f2 <__divsi3+0x1c2> 8000336: 0fca lsrs r2, r1, #31 8000338: d000 beq.n 800033c <__divsi3+0x10c> 800033a: 4249 negs r1, r1 800033c: 1003 asrs r3, r0, #32 800033e: d300 bcc.n 8000342 <__divsi3+0x112> 8000340: 4240 negs r0, r0 8000342: 4053 eors r3, r2 8000344: 2200 movs r2, #0 8000346: 469c mov ip, r3 8000348: 0903 lsrs r3, r0, #4 800034a: 428b cmp r3, r1 800034c: d32d bcc.n 80003aa <__divsi3+0x17a> 800034e: 0a03 lsrs r3, r0, #8 8000350: 428b cmp r3, r1 8000352: d312 bcc.n 800037a <__divsi3+0x14a> 8000354: 22fc movs r2, #252 ; 0xfc 8000356: 0189 lsls r1, r1, #6 8000358: ba12 rev r2, r2 800035a: 0a03 lsrs r3, r0, #8 800035c: 428b cmp r3, r1 800035e: d30c bcc.n 800037a <__divsi3+0x14a> 8000360: 0189 lsls r1, r1, #6 8000362: 1192 asrs r2, r2, #6 8000364: 428b cmp r3, r1 8000366: d308 bcc.n 800037a <__divsi3+0x14a> 8000368: 0189 lsls r1, r1, #6 800036a: 1192 asrs r2, r2, #6 800036c: 428b cmp r3, r1 800036e: d304 bcc.n 800037a <__divsi3+0x14a> 8000370: 0189 lsls r1, r1, #6 8000372: d03a beq.n 80003ea <__divsi3+0x1ba> 8000374: 1192 asrs r2, r2, #6 8000376: e000 b.n 800037a <__divsi3+0x14a> 8000378: 0989 lsrs r1, r1, #6 800037a: 09c3 lsrs r3, r0, #7 800037c: 428b cmp r3, r1 800037e: d301 bcc.n 8000384 <__divsi3+0x154> 8000380: 01cb lsls r3, r1, #7 8000382: 1ac0 subs r0, r0, r3 8000384: 4152 adcs r2, r2 8000386: 0983 lsrs r3, r0, #6 8000388: 428b cmp r3, r1 800038a: d301 bcc.n 8000390 <__divsi3+0x160> 800038c: 018b lsls r3, r1, #6 800038e: 1ac0 subs r0, r0, r3 8000390: 4152 adcs r2, r2 8000392: 0943 lsrs r3, r0, #5 8000394: 428b cmp r3, r1 8000396: d301 bcc.n 800039c <__divsi3+0x16c> 8000398: 014b lsls r3, r1, #5 800039a: 1ac0 subs r0, r0, r3 800039c: 4152 adcs r2, r2 800039e: 0903 lsrs r3, r0, #4 80003a0: 428b cmp r3, r1 80003a2: d301 bcc.n 80003a8 <__divsi3+0x178> 80003a4: 010b lsls r3, r1, #4 80003a6: 1ac0 subs r0, r0, r3 80003a8: 4152 adcs r2, r2 80003aa: 08c3 lsrs r3, r0, #3 80003ac: 428b cmp r3, r1 80003ae: d301 bcc.n 80003b4 <__divsi3+0x184> 80003b0: 00cb lsls r3, r1, #3 80003b2: 1ac0 subs r0, r0, r3 80003b4: 4152 adcs r2, r2 80003b6: 0883 lsrs r3, r0, #2 80003b8: 428b cmp r3, r1 80003ba: d301 bcc.n 80003c0 <__divsi3+0x190> 80003bc: 008b lsls r3, r1, #2 80003be: 1ac0 subs r0, r0, r3 80003c0: 4152 adcs r2, r2 80003c2: d2d9 bcs.n 8000378 <__divsi3+0x148> 80003c4: 0843 lsrs r3, r0, #1 80003c6: 428b cmp r3, r1 80003c8: d301 bcc.n 80003ce <__divsi3+0x19e> 80003ca: 004b lsls r3, r1, #1 80003cc: 1ac0 subs r0, r0, r3 80003ce: 4152 adcs r2, r2 80003d0: 1a41 subs r1, r0, r1 80003d2: d200 bcs.n 80003d6 <__divsi3+0x1a6> 80003d4: 4601 mov r1, r0 80003d6: 4663 mov r3, ip 80003d8: 4152 adcs r2, r2 80003da: 105b asrs r3, r3, #1 80003dc: 4610 mov r0, r2 80003de: d301 bcc.n 80003e4 <__divsi3+0x1b4> 80003e0: 4240 negs r0, r0 80003e2: 2b00 cmp r3, #0 80003e4: d500 bpl.n 80003e8 <__divsi3+0x1b8> 80003e6: 4249 negs r1, r1 80003e8: 4770 bx lr 80003ea: 4663 mov r3, ip 80003ec: 105b asrs r3, r3, #1 80003ee: d300 bcc.n 80003f2 <__divsi3+0x1c2> 80003f0: 4240 negs r0, r0 80003f2: b501 push {r0, lr} 80003f4: 2000 movs r0, #0 80003f6: f000 f805 bl 8000404 <__aeabi_idiv0> 80003fa: bd02 pop {r1, pc} 080003fc <__aeabi_idivmod>: 80003fc: 2900 cmp r1, #0 80003fe: d0f8 beq.n 80003f2 <__divsi3+0x1c2> 8000400: e716 b.n 8000230 <__divsi3> 8000402: 4770 bx lr 08000404 <__aeabi_idiv0>: 8000404: 4770 bx lr 8000406: 46c0 nop ; (mov r8, r8) 08000408 <__aeabi_lmul>: 8000408: b5f0 push {r4, r5, r6, r7, lr} 800040a: 0415 lsls r5, r2, #16 800040c: 0c2d lsrs r5, r5, #16 800040e: 000f movs r7, r1 8000410: 0001 movs r1, r0 8000412: 002e movs r6, r5 8000414: 46c6 mov lr, r8 8000416: 4684 mov ip, r0 8000418: 0400 lsls r0, r0, #16 800041a: 0c14 lsrs r4, r2, #16 800041c: 0c00 lsrs r0, r0, #16 800041e: 0c09 lsrs r1, r1, #16 8000420: 4346 muls r6, r0 8000422: 434d muls r5, r1 8000424: 4360 muls r0, r4 8000426: 4361 muls r1, r4 8000428: 1940 adds r0, r0, r5 800042a: 0c34 lsrs r4, r6, #16 800042c: 1824 adds r4, r4, r0 800042e: b500 push {lr} 8000430: 42a5 cmp r5, r4 8000432: d903 bls.n 800043c <__aeabi_lmul+0x34> 8000434: 2080 movs r0, #128 ; 0x80 8000436: 0240 lsls r0, r0, #9 8000438: 4680 mov r8, r0 800043a: 4441 add r1, r8 800043c: 0c25 lsrs r5, r4, #16 800043e: 186d adds r5, r5, r1 8000440: 4661 mov r1, ip 8000442: 4359 muls r1, r3 8000444: 437a muls r2, r7 8000446: 0430 lsls r0, r6, #16 8000448: 1949 adds r1, r1, r5 800044a: 0424 lsls r4, r4, #16 800044c: 0c00 lsrs r0, r0, #16 800044e: 1820 adds r0, r4, r0 8000450: 1889 adds r1, r1, r2 8000452: bc80 pop {r7} 8000454: 46b8 mov r8, r7 8000456: bdf0 pop {r4, r5, r6, r7, pc} 08000458
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000458: b580 push {r7, lr} 800045a: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800045c: f000 fa9e bl 800099c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000460: f000 f807 bl 8000472 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000464: f000 f8b2 bl 80005cc MX_ADC_Init(); 8000468: f000 f854 bl 8000514 /* USER CODE BEGIN 2 */ mymain(); 800046c: f001 fd94 bl 8001f98 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000470: e7fe b.n 8000470 08000472 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000472: b590 push {r4, r7, lr} 8000474: b091 sub sp, #68 ; 0x44 8000476: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000478: 2410 movs r4, #16 800047a: 193b adds r3, r7, r4 800047c: 0018 movs r0, r3 800047e: 2330 movs r3, #48 ; 0x30 8000480: 001a movs r2, r3 8000482: 2100 movs r1, #0 8000484: f001 ff28 bl 80022d8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000488: 003b movs r3, r7 800048a: 0018 movs r0, r3 800048c: 2310 movs r3, #16 800048e: 001a movs r2, r3 8000490: 2100 movs r1, #0 8000492: f001 ff21 bl 80022d8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14; 8000496: 0021 movs r1, r4 8000498: 187b adds r3, r7, r1 800049a: 2212 movs r2, #18 800049c: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800049e: 187b adds r3, r7, r1 80004a0: 2201 movs r2, #1 80004a2: 60da str r2, [r3, #12] RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 80004a4: 187b adds r3, r7, r1 80004a6: 2201 movs r2, #1 80004a8: 615a str r2, [r3, #20] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80004aa: 187b adds r3, r7, r1 80004ac: 2210 movs r2, #16 80004ae: 611a str r2, [r3, #16] RCC_OscInitStruct.HSI14CalibrationValue = 16; 80004b0: 187b adds r3, r7, r1 80004b2: 2210 movs r2, #16 80004b4: 619a str r2, [r3, #24] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80004b6: 187b adds r3, r7, r1 80004b8: 2202 movs r2, #2 80004ba: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 80004bc: 187b adds r3, r7, r1 80004be: 2200 movs r2, #0 80004c0: 625a str r2, [r3, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; 80004c2: 187b adds r3, r7, r1 80004c4: 22a0 movs r2, #160 ; 0xa0 80004c6: 0392 lsls r2, r2, #14 80004c8: 629a str r2, [r3, #40] ; 0x28 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; 80004ca: 187b adds r3, r7, r1 80004cc: 2200 movs r2, #0 80004ce: 62da str r2, [r3, #44] ; 0x2c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80004d0: 187b adds r3, r7, r1 80004d2: 0018 movs r0, r3 80004d4: f000 ff5a bl 800138c 80004d8: 1e03 subs r3, r0, #0 80004da: d001 beq.n 80004e0 { Error_Handler(); 80004dc: f000 f8ea bl 80006b4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80004e0: 003b movs r3, r7 80004e2: 2207 movs r2, #7 80004e4: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80004e6: 003b movs r3, r7 80004e8: 2202 movs r2, #2 80004ea: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80004ec: 003b movs r3, r7 80004ee: 2200 movs r2, #0 80004f0: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80004f2: 003b movs r3, r7 80004f4: 2200 movs r2, #0 80004f6: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80004f8: 003b movs r3, r7 80004fa: 2101 movs r1, #1 80004fc: 0018 movs r0, r3 80004fe: f001 fa5f bl 80019c0 8000502: 1e03 subs r3, r0, #0 8000504: d001 beq.n 800050a { Error_Handler(); 8000506: f000 f8d5 bl 80006b4 } } 800050a: 46c0 nop ; (mov r8, r8) 800050c: 46bd mov sp, r7 800050e: b011 add sp, #68 ; 0x44 8000510: bd90 pop {r4, r7, pc} ... 08000514 : * @brief ADC Initialization Function * @param None * @retval None */ static void MX_ADC_Init(void) { 8000514: b580 push {r7, lr} 8000516: b084 sub sp, #16 8000518: af00 add r7, sp, #0 /* USER CODE BEGIN ADC_Init 0 */ /* USER CODE END ADC_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800051a: 1d3b adds r3, r7, #4 800051c: 0018 movs r0, r3 800051e: 230c movs r3, #12 8000520: 001a movs r2, r3 8000522: 2100 movs r1, #0 8000524: f001 fed8 bl 80022d8 /* USER CODE BEGIN ADC_Init 1 */ /* USER CODE END ADC_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc.Instance = ADC1; 8000528: 4b26 ldr r3, [pc, #152] ; (80005c4 ) 800052a: 4a27 ldr r2, [pc, #156] ; (80005c8 ) 800052c: 601a str r2, [r3, #0] hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 800052e: 4b25 ldr r3, [pc, #148] ; (80005c4 ) 8000530: 2200 movs r2, #0 8000532: 605a str r2, [r3, #4] hadc.Init.Resolution = ADC_RESOLUTION_12B; 8000534: 4b23 ldr r3, [pc, #140] ; (80005c4 ) 8000536: 2200 movs r2, #0 8000538: 609a str r2, [r3, #8] hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800053a: 4b22 ldr r3, [pc, #136] ; (80005c4 ) 800053c: 2200 movs r2, #0 800053e: 60da str r2, [r3, #12] hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 8000540: 4b20 ldr r3, [pc, #128] ; (80005c4 ) 8000542: 2201 movs r2, #1 8000544: 611a str r2, [r3, #16] hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8000546: 4b1f ldr r3, [pc, #124] ; (80005c4 ) 8000548: 2204 movs r2, #4 800054a: 615a str r2, [r3, #20] hadc.Init.LowPowerAutoWait = DISABLE; 800054c: 4b1d ldr r3, [pc, #116] ; (80005c4 ) 800054e: 2200 movs r2, #0 8000550: 761a strb r2, [r3, #24] hadc.Init.LowPowerAutoPowerOff = DISABLE; 8000552: 4b1c ldr r3, [pc, #112] ; (80005c4 ) 8000554: 2200 movs r2, #0 8000556: 765a strb r2, [r3, #25] hadc.Init.ContinuousConvMode = DISABLE; 8000558: 4b1a ldr r3, [pc, #104] ; (80005c4 ) 800055a: 2200 movs r2, #0 800055c: 769a strb r2, [r3, #26] hadc.Init.DiscontinuousConvMode = DISABLE; 800055e: 4b19 ldr r3, [pc, #100] ; (80005c4 ) 8000560: 2200 movs r2, #0 8000562: 76da strb r2, [r3, #27] hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000564: 4b17 ldr r3, [pc, #92] ; (80005c4 ) 8000566: 22c2 movs r2, #194 ; 0xc2 8000568: 32ff adds r2, #255 ; 0xff 800056a: 61da str r2, [r3, #28] hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 800056c: 4b15 ldr r3, [pc, #84] ; (80005c4 ) 800056e: 2200 movs r2, #0 8000570: 621a str r2, [r3, #32] hadc.Init.DMAContinuousRequests = DISABLE; 8000572: 4b14 ldr r3, [pc, #80] ; (80005c4 ) 8000574: 2224 movs r2, #36 ; 0x24 8000576: 2100 movs r1, #0 8000578: 5499 strb r1, [r3, r2] hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 800057a: 4b12 ldr r3, [pc, #72] ; (80005c4 ) 800057c: 2201 movs r2, #1 800057e: 629a str r2, [r3, #40] ; 0x28 if (HAL_ADC_Init(&hadc) != HAL_OK) 8000580: 4b10 ldr r3, [pc, #64] ; (80005c4 ) 8000582: 0018 movs r0, r3 8000584: f000 fa6e bl 8000a64 8000588: 1e03 subs r3, r0, #0 800058a: d001 beq.n 8000590 { Error_Handler(); 800058c: f000 f892 bl 80006b4 } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_0; 8000590: 1d3b adds r3, r7, #4 8000592: 2200 movs r2, #0 8000594: 601a str r2, [r3, #0] sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 8000596: 1d3b adds r3, r7, #4 8000598: 2280 movs r2, #128 ; 0x80 800059a: 0152 lsls r2, r2, #5 800059c: 605a str r2, [r3, #4] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800059e: 1d3b adds r3, r7, #4 80005a0: 2280 movs r2, #128 ; 0x80 80005a2: 0552 lsls r2, r2, #21 80005a4: 609a str r2, [r3, #8] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 80005a6: 1d3a adds r2, r7, #4 80005a8: 4b06 ldr r3, [pc, #24] ; (80005c4 ) 80005aa: 0011 movs r1, r2 80005ac: 0018 movs r0, r3 80005ae: f000 fb99 bl 8000ce4 80005b2: 1e03 subs r3, r0, #0 80005b4: d001 beq.n 80005ba { Error_Handler(); 80005b6: f000 f87d bl 80006b4 } /* USER CODE BEGIN ADC_Init 2 */ /* USER CODE END ADC_Init 2 */ } 80005ba: 46c0 nop ; (mov r8, r8) 80005bc: 46bd mov sp, r7 80005be: b004 add sp, #16 80005c0: bd80 pop {r7, pc} 80005c2: 46c0 nop ; (mov r8, r8) 80005c4: 20000098 .word 0x20000098 80005c8: 40012400 .word 0x40012400 080005cc : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80005cc: b590 push {r4, r7, lr} 80005ce: b089 sub sp, #36 ; 0x24 80005d0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80005d2: 240c movs r4, #12 80005d4: 193b adds r3, r7, r4 80005d6: 0018 movs r0, r3 80005d8: 2314 movs r3, #20 80005da: 001a movs r2, r3 80005dc: 2100 movs r1, #0 80005de: f001 fe7b bl 80022d8 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80005e2: 4b32 ldr r3, [pc, #200] ; (80006ac ) 80005e4: 695a ldr r2, [r3, #20] 80005e6: 4b31 ldr r3, [pc, #196] ; (80006ac ) 80005e8: 2180 movs r1, #128 ; 0x80 80005ea: 03c9 lsls r1, r1, #15 80005ec: 430a orrs r2, r1 80005ee: 615a str r2, [r3, #20] 80005f0: 4b2e ldr r3, [pc, #184] ; (80006ac ) 80005f2: 695a ldr r2, [r3, #20] 80005f4: 2380 movs r3, #128 ; 0x80 80005f6: 03db lsls r3, r3, #15 80005f8: 4013 ands r3, r2 80005fa: 60bb str r3, [r7, #8] 80005fc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80005fe: 4b2b ldr r3, [pc, #172] ; (80006ac ) 8000600: 695a ldr r2, [r3, #20] 8000602: 4b2a ldr r3, [pc, #168] ; (80006ac ) 8000604: 2180 movs r1, #128 ; 0x80 8000606: 0289 lsls r1, r1, #10 8000608: 430a orrs r2, r1 800060a: 615a str r2, [r3, #20] 800060c: 4b27 ldr r3, [pc, #156] ; (80006ac ) 800060e: 695a ldr r2, [r3, #20] 8000610: 2380 movs r3, #128 ; 0x80 8000612: 029b lsls r3, r3, #10 8000614: 4013 ands r3, r2 8000616: 607b str r3, [r7, #4] 8000618: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET); 800061a: 4b25 ldr r3, [pc, #148] ; (80006b0 ) 800061c: 2200 movs r2, #0 800061e: 2103 movs r1, #3 8000620: 0018 movs r0, r3 8000622: f000 fe96 bl 8001352 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET); 8000626: 2390 movs r3, #144 ; 0x90 8000628: 05db lsls r3, r3, #23 800062a: 2200 movs r2, #0 800062c: 2138 movs r1, #56 ; 0x38 800062e: 0018 movs r0, r3 8000630: f000 fe8f bl 8001352 /*Configure GPIO pins : MOTA_Pin MOTB_Pin */ GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin; 8000634: 193b adds r3, r7, r4 8000636: 2203 movs r2, #3 8000638: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800063a: 193b adds r3, r7, r4 800063c: 2201 movs r2, #1 800063e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000640: 193b adds r3, r7, r4 8000642: 2200 movs r2, #0 8000644: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000646: 193b adds r3, r7, r4 8000648: 2203 movs r2, #3 800064a: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 800064c: 193b adds r3, r7, r4 800064e: 4a18 ldr r2, [pc, #96] ; (80006b0 ) 8000650: 0019 movs r1, r3 8000652: 0010 movs r0, r2 8000654: f000 fcf0 bl 8001038 /*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */ GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin; 8000658: 193b adds r3, r7, r4 800065a: 2238 movs r2, #56 ; 0x38 800065c: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800065e: 193b adds r3, r7, r4 8000660: 2201 movs r2, #1 8000662: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000664: 193b adds r3, r7, r4 8000666: 2200 movs r2, #0 8000668: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800066a: 193b adds r3, r7, r4 800066c: 2203 movs r2, #3 800066e: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000670: 193a adds r2, r7, r4 8000672: 2390 movs r3, #144 ; 0x90 8000674: 05db lsls r3, r3, #23 8000676: 0011 movs r1, r2 8000678: 0018 movs r0, r3 800067a: f000 fcdd bl 8001038 /*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */ GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin; 800067e: 0021 movs r1, r4 8000680: 187b adds r3, r7, r1 8000682: 22d8 movs r2, #216 ; 0xd8 8000684: 00d2 lsls r2, r2, #3 8000686: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000688: 187b adds r3, r7, r1 800068a: 2200 movs r2, #0 800068c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 800068e: 187b adds r3, r7, r1 8000690: 2200 movs r2, #0 8000692: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000694: 187a adds r2, r7, r1 8000696: 2390 movs r3, #144 ; 0x90 8000698: 05db lsls r3, r3, #23 800069a: 0011 movs r1, r2 800069c: 0018 movs r0, r3 800069e: f000 fccb bl 8001038 } 80006a2: 46c0 nop ; (mov r8, r8) 80006a4: 46bd mov sp, r7 80006a6: b009 add sp, #36 ; 0x24 80006a8: bd90 pop {r4, r7, pc} 80006aa: 46c0 nop ; (mov r8, r8) 80006ac: 40021000 .word 0x40021000 80006b0: 48001400 .word 0x48001400 080006b4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80006b4: b580 push {r7, lr} 80006b6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80006b8: b672 cpsid i } 80006ba: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80006bc: e7fe b.n 80006bc ... 080006c0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80006c0: b580 push {r7, lr} 80006c2: b082 sub sp, #8 80006c4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80006c6: 4b0f ldr r3, [pc, #60] ; (8000704 ) 80006c8: 699a ldr r2, [r3, #24] 80006ca: 4b0e ldr r3, [pc, #56] ; (8000704 ) 80006cc: 2101 movs r1, #1 80006ce: 430a orrs r2, r1 80006d0: 619a str r2, [r3, #24] 80006d2: 4b0c ldr r3, [pc, #48] ; (8000704 ) 80006d4: 699b ldr r3, [r3, #24] 80006d6: 2201 movs r2, #1 80006d8: 4013 ands r3, r2 80006da: 607b str r3, [r7, #4] 80006dc: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 80006de: 4b09 ldr r3, [pc, #36] ; (8000704 ) 80006e0: 69da ldr r2, [r3, #28] 80006e2: 4b08 ldr r3, [pc, #32] ; (8000704 ) 80006e4: 2180 movs r1, #128 ; 0x80 80006e6: 0549 lsls r1, r1, #21 80006e8: 430a orrs r2, r1 80006ea: 61da str r2, [r3, #28] 80006ec: 4b05 ldr r3, [pc, #20] ; (8000704 ) 80006ee: 69da ldr r2, [r3, #28] 80006f0: 2380 movs r3, #128 ; 0x80 80006f2: 055b lsls r3, r3, #21 80006f4: 4013 ands r3, r2 80006f6: 603b str r3, [r7, #0] 80006f8: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80006fa: 46c0 nop ; (mov r8, r8) 80006fc: 46bd mov sp, r7 80006fe: b002 add sp, #8 8000700: bd80 pop {r7, pc} 8000702: 46c0 nop ; (mov r8, r8) 8000704: 40021000 .word 0x40021000 08000708 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8000708: b590 push {r4, r7, lr} 800070a: b08b sub sp, #44 ; 0x2c 800070c: af00 add r7, sp, #0 800070e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000710: 2414 movs r4, #20 8000712: 193b adds r3, r7, r4 8000714: 0018 movs r0, r3 8000716: 2314 movs r3, #20 8000718: 001a movs r2, r3 800071a: 2100 movs r1, #0 800071c: f001 fddc bl 80022d8 if(hadc->Instance==ADC1) 8000720: 687b ldr r3, [r7, #4] 8000722: 681b ldr r3, [r3, #0] 8000724: 4a19 ldr r2, [pc, #100] ; (800078c ) 8000726: 4293 cmp r3, r2 8000728: d12b bne.n 8000782 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 800072a: 4b19 ldr r3, [pc, #100] ; (8000790 ) 800072c: 699a ldr r2, [r3, #24] 800072e: 4b18 ldr r3, [pc, #96] ; (8000790 ) 8000730: 2180 movs r1, #128 ; 0x80 8000732: 0089 lsls r1, r1, #2 8000734: 430a orrs r2, r1 8000736: 619a str r2, [r3, #24] 8000738: 4b15 ldr r3, [pc, #84] ; (8000790 ) 800073a: 699a ldr r2, [r3, #24] 800073c: 2380 movs r3, #128 ; 0x80 800073e: 009b lsls r3, r3, #2 8000740: 4013 ands r3, r2 8000742: 613b str r3, [r7, #16] 8000744: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000746: 4b12 ldr r3, [pc, #72] ; (8000790 ) 8000748: 695a ldr r2, [r3, #20] 800074a: 4b11 ldr r3, [pc, #68] ; (8000790 ) 800074c: 2180 movs r1, #128 ; 0x80 800074e: 0289 lsls r1, r1, #10 8000750: 430a orrs r2, r1 8000752: 615a str r2, [r3, #20] 8000754: 4b0e ldr r3, [pc, #56] ; (8000790 ) 8000756: 695a ldr r2, [r3, #20] 8000758: 2380 movs r3, #128 ; 0x80 800075a: 029b lsls r3, r3, #10 800075c: 4013 ands r3, r2 800075e: 60fb str r3, [r7, #12] 8000760: 68fb ldr r3, [r7, #12] /**ADC GPIO Configuration PA0 ------> ADC_IN0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8000762: 193b adds r3, r7, r4 8000764: 2201 movs r2, #1 8000766: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000768: 193b adds r3, r7, r4 800076a: 2203 movs r2, #3 800076c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 800076e: 193b adds r3, r7, r4 8000770: 2200 movs r2, #0 8000772: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000774: 193a adds r2, r7, r4 8000776: 2390 movs r3, #144 ; 0x90 8000778: 05db lsls r3, r3, #23 800077a: 0011 movs r1, r2 800077c: 0018 movs r0, r3 800077e: f000 fc5b bl 8001038 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8000782: 46c0 nop ; (mov r8, r8) 8000784: 46bd mov sp, r7 8000786: b00b add sp, #44 ; 0x2c 8000788: bd90 pop {r4, r7, pc} 800078a: 46c0 nop ; (mov r8, r8) 800078c: 40012400 .word 0x40012400 8000790: 40021000 .word 0x40021000 08000794 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000794: b580 push {r7, lr} 8000796: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000798: e7fe b.n 8000798 0800079a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800079a: b580 push {r7, lr} 800079c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800079e: e7fe b.n 800079e 080007a0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80007a0: b580 push {r7, lr} 80007a2: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 80007a4: 46c0 nop ; (mov r8, r8) 80007a6: 46bd mov sp, r7 80007a8: bd80 pop {r7, pc} 080007aa : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80007aa: b580 push {r7, lr} 80007ac: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80007ae: 46c0 nop ; (mov r8, r8) 80007b0: 46bd mov sp, r7 80007b2: bd80 pop {r7, pc} 080007b4 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80007b4: b580 push {r7, lr} 80007b6: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80007b8: f000 f938 bl 8000a2c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80007bc: 46c0 nop ; (mov r8, r8) 80007be: 46bd mov sp, r7 80007c0: bd80 pop {r7, pc} 080007c2 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 80007c2: b580 push {r7, lr} 80007c4: af00 add r7, sp, #0 return 1; 80007c6: 2301 movs r3, #1 } 80007c8: 0018 movs r0, r3 80007ca: 46bd mov sp, r7 80007cc: bd80 pop {r7, pc} 080007ce <_kill>: int _kill(int pid, int sig) { 80007ce: b580 push {r7, lr} 80007d0: b082 sub sp, #8 80007d2: af00 add r7, sp, #0 80007d4: 6078 str r0, [r7, #4] 80007d6: 6039 str r1, [r7, #0] errno = EINVAL; 80007d8: f001 fd54 bl 8002284 <__errno> 80007dc: 0003 movs r3, r0 80007de: 2216 movs r2, #22 80007e0: 601a str r2, [r3, #0] return -1; 80007e2: 2301 movs r3, #1 80007e4: 425b negs r3, r3 } 80007e6: 0018 movs r0, r3 80007e8: 46bd mov sp, r7 80007ea: b002 add sp, #8 80007ec: bd80 pop {r7, pc} 080007ee <_exit>: void _exit (int status) { 80007ee: b580 push {r7, lr} 80007f0: b082 sub sp, #8 80007f2: af00 add r7, sp, #0 80007f4: 6078 str r0, [r7, #4] _kill(status, -1); 80007f6: 2301 movs r3, #1 80007f8: 425a negs r2, r3 80007fa: 687b ldr r3, [r7, #4] 80007fc: 0011 movs r1, r2 80007fe: 0018 movs r0, r3 8000800: f7ff ffe5 bl 80007ce <_kill> while (1) {} /* Make sure we hang here */ 8000804: e7fe b.n 8000804 <_exit+0x16> 08000806 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8000806: b580 push {r7, lr} 8000808: b086 sub sp, #24 800080a: af00 add r7, sp, #0 800080c: 60f8 str r0, [r7, #12] 800080e: 60b9 str r1, [r7, #8] 8000810: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8000812: 2300 movs r3, #0 8000814: 617b str r3, [r7, #20] 8000816: e00a b.n 800082e <_read+0x28> { *ptr++ = __io_getchar(); 8000818: e000 b.n 800081c <_read+0x16> 800081a: bf00 nop 800081c: 0001 movs r1, r0 800081e: 68bb ldr r3, [r7, #8] 8000820: 1c5a adds r2, r3, #1 8000822: 60ba str r2, [r7, #8] 8000824: b2ca uxtb r2, r1 8000826: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8000828: 697b ldr r3, [r7, #20] 800082a: 3301 adds r3, #1 800082c: 617b str r3, [r7, #20] 800082e: 697a ldr r2, [r7, #20] 8000830: 687b ldr r3, [r7, #4] 8000832: 429a cmp r2, r3 8000834: dbf0 blt.n 8000818 <_read+0x12> } return len; 8000836: 687b ldr r3, [r7, #4] } 8000838: 0018 movs r0, r3 800083a: 46bd mov sp, r7 800083c: b006 add sp, #24 800083e: bd80 pop {r7, pc} 08000840 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8000840: b580 push {r7, lr} 8000842: b086 sub sp, #24 8000844: af00 add r7, sp, #0 8000846: 60f8 str r0, [r7, #12] 8000848: 60b9 str r1, [r7, #8] 800084a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800084c: 2300 movs r3, #0 800084e: 617b str r3, [r7, #20] 8000850: e009 b.n 8000866 <_write+0x26> { __io_putchar(*ptr++); 8000852: 68bb ldr r3, [r7, #8] 8000854: 1c5a adds r2, r3, #1 8000856: 60ba str r2, [r7, #8] 8000858: 781b ldrb r3, [r3, #0] 800085a: 0018 movs r0, r3 800085c: e000 b.n 8000860 <_write+0x20> 800085e: bf00 nop for (DataIdx = 0; DataIdx < len; DataIdx++) 8000860: 697b ldr r3, [r7, #20] 8000862: 3301 adds r3, #1 8000864: 617b str r3, [r7, #20] 8000866: 697a ldr r2, [r7, #20] 8000868: 687b ldr r3, [r7, #4] 800086a: 429a cmp r2, r3 800086c: dbf1 blt.n 8000852 <_write+0x12> } return len; 800086e: 687b ldr r3, [r7, #4] } 8000870: 0018 movs r0, r3 8000872: 46bd mov sp, r7 8000874: b006 add sp, #24 8000876: bd80 pop {r7, pc} 08000878 <_close>: int _close(int file) { 8000878: b580 push {r7, lr} 800087a: b082 sub sp, #8 800087c: af00 add r7, sp, #0 800087e: 6078 str r0, [r7, #4] return -1; 8000880: 2301 movs r3, #1 8000882: 425b negs r3, r3 } 8000884: 0018 movs r0, r3 8000886: 46bd mov sp, r7 8000888: b002 add sp, #8 800088a: bd80 pop {r7, pc} 0800088c <_fstat>: int _fstat(int file, struct stat *st) { 800088c: b580 push {r7, lr} 800088e: b082 sub sp, #8 8000890: af00 add r7, sp, #0 8000892: 6078 str r0, [r7, #4] 8000894: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8000896: 683b ldr r3, [r7, #0] 8000898: 2280 movs r2, #128 ; 0x80 800089a: 0192 lsls r2, r2, #6 800089c: 605a str r2, [r3, #4] return 0; 800089e: 2300 movs r3, #0 } 80008a0: 0018 movs r0, r3 80008a2: 46bd mov sp, r7 80008a4: b002 add sp, #8 80008a6: bd80 pop {r7, pc} 080008a8 <_isatty>: int _isatty(int file) { 80008a8: b580 push {r7, lr} 80008aa: b082 sub sp, #8 80008ac: af00 add r7, sp, #0 80008ae: 6078 str r0, [r7, #4] return 1; 80008b0: 2301 movs r3, #1 } 80008b2: 0018 movs r0, r3 80008b4: 46bd mov sp, r7 80008b6: b002 add sp, #8 80008b8: bd80 pop {r7, pc} 080008ba <_lseek>: int _lseek(int file, int ptr, int dir) { 80008ba: b580 push {r7, lr} 80008bc: b084 sub sp, #16 80008be: af00 add r7, sp, #0 80008c0: 60f8 str r0, [r7, #12] 80008c2: 60b9 str r1, [r7, #8] 80008c4: 607a str r2, [r7, #4] return 0; 80008c6: 2300 movs r3, #0 } 80008c8: 0018 movs r0, r3 80008ca: 46bd mov sp, r7 80008cc: b004 add sp, #16 80008ce: bd80 pop {r7, pc} 080008d0 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80008d0: b580 push {r7, lr} 80008d2: b086 sub sp, #24 80008d4: af00 add r7, sp, #0 80008d6: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80008d8: 4a14 ldr r2, [pc, #80] ; (800092c <_sbrk+0x5c>) 80008da: 4b15 ldr r3, [pc, #84] ; (8000930 <_sbrk+0x60>) 80008dc: 1ad3 subs r3, r2, r3 80008de: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80008e0: 697b ldr r3, [r7, #20] 80008e2: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80008e4: 4b13 ldr r3, [pc, #76] ; (8000934 <_sbrk+0x64>) 80008e6: 681b ldr r3, [r3, #0] 80008e8: 2b00 cmp r3, #0 80008ea: d102 bne.n 80008f2 <_sbrk+0x22> { __sbrk_heap_end = &_end; 80008ec: 4b11 ldr r3, [pc, #68] ; (8000934 <_sbrk+0x64>) 80008ee: 4a12 ldr r2, [pc, #72] ; (8000938 <_sbrk+0x68>) 80008f0: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80008f2: 4b10 ldr r3, [pc, #64] ; (8000934 <_sbrk+0x64>) 80008f4: 681a ldr r2, [r3, #0] 80008f6: 687b ldr r3, [r7, #4] 80008f8: 18d3 adds r3, r2, r3 80008fa: 693a ldr r2, [r7, #16] 80008fc: 429a cmp r2, r3 80008fe: d207 bcs.n 8000910 <_sbrk+0x40> { errno = ENOMEM; 8000900: f001 fcc0 bl 8002284 <__errno> 8000904: 0003 movs r3, r0 8000906: 220c movs r2, #12 8000908: 601a str r2, [r3, #0] return (void *)-1; 800090a: 2301 movs r3, #1 800090c: 425b negs r3, r3 800090e: e009 b.n 8000924 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8000910: 4b08 ldr r3, [pc, #32] ; (8000934 <_sbrk+0x64>) 8000912: 681b ldr r3, [r3, #0] 8000914: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8000916: 4b07 ldr r3, [pc, #28] ; (8000934 <_sbrk+0x64>) 8000918: 681a ldr r2, [r3, #0] 800091a: 687b ldr r3, [r7, #4] 800091c: 18d2 adds r2, r2, r3 800091e: 4b05 ldr r3, [pc, #20] ; (8000934 <_sbrk+0x64>) 8000920: 601a str r2, [r3, #0] return (void *)prev_heap_end; 8000922: 68fb ldr r3, [r7, #12] } 8000924: 0018 movs r0, r3 8000926: 46bd mov sp, r7 8000928: b006 add sp, #24 800092a: bd80 pop {r7, pc} 800092c: 20001000 .word 0x20001000 8000930: 00000400 .word 0x00000400 8000934: 2000008c .word 0x2000008c 8000938: 20000128 .word 0x20000128 0800093c : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 800093c: b580 push {r7, lr} 800093e: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 8000940: 46c0 nop ; (mov r8, r8) 8000942: 46bd mov sp, r7 8000944: bd80 pop {r7, pc} ... 08000948 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000948: 480d ldr r0, [pc, #52] ; (8000980 ) mov sp, r0 /* set stack pointer */ 800094a: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800094c: 480d ldr r0, [pc, #52] ; (8000984 ) ldr r1, =_edata 800094e: 490e ldr r1, [pc, #56] ; (8000988 ) ldr r2, =_sidata 8000950: 4a0e ldr r2, [pc, #56] ; (800098c ) movs r3, #0 8000952: 2300 movs r3, #0 b LoopCopyDataInit 8000954: e002 b.n 800095c 08000956 : CopyDataInit: ldr r4, [r2, r3] 8000956: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000958: 50c4 str r4, [r0, r3] adds r3, r3, #4 800095a: 3304 adds r3, #4 0800095c : LoopCopyDataInit: adds r4, r0, r3 800095c: 18c4 adds r4, r0, r3 cmp r4, r1 800095e: 428c cmp r4, r1 bcc CopyDataInit 8000960: d3f9 bcc.n 8000956 /* Zero fill the bss segment. */ ldr r2, =_sbss 8000962: 4a0b ldr r2, [pc, #44] ; (8000990 ) ldr r4, =_ebss 8000964: 4c0b ldr r4, [pc, #44] ; (8000994 ) movs r3, #0 8000966: 2300 movs r3, #0 b LoopFillZerobss 8000968: e001 b.n 800096e 0800096a : FillZerobss: str r3, [r2] 800096a: 6013 str r3, [r2, #0] adds r2, r2, #4 800096c: 3204 adds r2, #4 0800096e : LoopFillZerobss: cmp r2, r4 800096e: 42a2 cmp r2, r4 bcc FillZerobss 8000970: d3fb bcc.n 800096a /* Call the clock system intitialization function.*/ bl SystemInit 8000972: f7ff ffe3 bl 800093c /* Call static constructors */ bl __libc_init_array 8000976: f001 fc8b bl 8002290 <__libc_init_array> /* Call the application's entry point.*/ bl main 800097a: f7ff fd6d bl 8000458
0800097e : LoopForever: b LoopForever 800097e: e7fe b.n 800097e ldr r0, =_estack 8000980: 20001000 .word 0x20001000 ldr r0, =_sdata 8000984: 20000000 .word 0x20000000 ldr r1, =_edata 8000988: 20000070 .word 0x20000070 ldr r2, =_sidata 800098c: 08003530 .word 0x08003530 ldr r2, =_sbss 8000990: 20000070 .word 0x20000070 ldr r4, =_ebss 8000994: 20000124 .word 0x20000124 08000998 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000998: e7fe b.n 8000998 ... 0800099c : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800099c: b580 push {r7, lr} 800099e: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80009a0: 4b07 ldr r3, [pc, #28] ; (80009c0 ) 80009a2: 681a ldr r2, [r3, #0] 80009a4: 4b06 ldr r3, [pc, #24] ; (80009c0 ) 80009a6: 2110 movs r1, #16 80009a8: 430a orrs r2, r1 80009aa: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80009ac: 2003 movs r0, #3 80009ae: f000 f809 bl 80009c4 /* Init the low level hardware */ HAL_MspInit(); 80009b2: f7ff fe85 bl 80006c0 /* Return function status */ return HAL_OK; 80009b6: 2300 movs r3, #0 } 80009b8: 0018 movs r0, r3 80009ba: 46bd mov sp, r7 80009bc: bd80 pop {r7, pc} 80009be: 46c0 nop ; (mov r8, r8) 80009c0: 40022000 .word 0x40022000 080009c4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80009c4: b590 push {r4, r7, lr} 80009c6: b083 sub sp, #12 80009c8: af00 add r7, sp, #0 80009ca: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80009cc: 4b14 ldr r3, [pc, #80] ; (8000a20 ) 80009ce: 681c ldr r4, [r3, #0] 80009d0: 4b14 ldr r3, [pc, #80] ; (8000a24 ) 80009d2: 781b ldrb r3, [r3, #0] 80009d4: 0019 movs r1, r3 80009d6: 23fa movs r3, #250 ; 0xfa 80009d8: 0098 lsls r0, r3, #2 80009da: f7ff fb9f bl 800011c <__udivsi3> 80009de: 0003 movs r3, r0 80009e0: 0019 movs r1, r3 80009e2: 0020 movs r0, r4 80009e4: f7ff fb9a bl 800011c <__udivsi3> 80009e8: 0003 movs r3, r0 80009ea: 0018 movs r0, r3 80009ec: f000 fb17 bl 800101e 80009f0: 1e03 subs r3, r0, #0 80009f2: d001 beq.n 80009f8 { return HAL_ERROR; 80009f4: 2301 movs r3, #1 80009f6: e00f b.n 8000a18 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80009f8: 687b ldr r3, [r7, #4] 80009fa: 2b03 cmp r3, #3 80009fc: d80b bhi.n 8000a16 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80009fe: 6879 ldr r1, [r7, #4] 8000a00: 2301 movs r3, #1 8000a02: 425b negs r3, r3 8000a04: 2200 movs r2, #0 8000a06: 0018 movs r0, r3 8000a08: f000 faf4 bl 8000ff4 uwTickPrio = TickPriority; 8000a0c: 4b06 ldr r3, [pc, #24] ; (8000a28 ) 8000a0e: 687a ldr r2, [r7, #4] 8000a10: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000a12: 2300 movs r3, #0 8000a14: e000 b.n 8000a18 return HAL_ERROR; 8000a16: 2301 movs r3, #1 } 8000a18: 0018 movs r0, r3 8000a1a: 46bd mov sp, r7 8000a1c: b003 add sp, #12 8000a1e: bd90 pop {r4, r7, pc} 8000a20: 20000000 .word 0x20000000 8000a24: 20000008 .word 0x20000008 8000a28: 20000004 .word 0x20000004 08000a2c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000a2c: b580 push {r7, lr} 8000a2e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000a30: 4b05 ldr r3, [pc, #20] ; (8000a48 ) 8000a32: 781b ldrb r3, [r3, #0] 8000a34: 001a movs r2, r3 8000a36: 4b05 ldr r3, [pc, #20] ; (8000a4c ) 8000a38: 681b ldr r3, [r3, #0] 8000a3a: 18d2 adds r2, r2, r3 8000a3c: 4b03 ldr r3, [pc, #12] ; (8000a4c ) 8000a3e: 601a str r2, [r3, #0] } 8000a40: 46c0 nop ; (mov r8, r8) 8000a42: 46bd mov sp, r7 8000a44: bd80 pop {r7, pc} 8000a46: 46c0 nop ; (mov r8, r8) 8000a48: 20000008 .word 0x20000008 8000a4c: 200000d8 .word 0x200000d8 08000a50 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000a50: b580 push {r7, lr} 8000a52: af00 add r7, sp, #0 return uwTick; 8000a54: 4b02 ldr r3, [pc, #8] ; (8000a60 ) 8000a56: 681b ldr r3, [r3, #0] } 8000a58: 0018 movs r0, r3 8000a5a: 46bd mov sp, r7 8000a5c: bd80 pop {r7, pc} 8000a5e: 46c0 nop ; (mov r8, r8) 8000a60: 200000d8 .word 0x200000d8 08000a64 : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8000a64: b580 push {r7, lr} 8000a66: b084 sub sp, #16 8000a68: af00 add r7, sp, #0 8000a6a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000a6c: 230f movs r3, #15 8000a6e: 18fb adds r3, r7, r3 8000a70: 2200 movs r2, #0 8000a72: 701a strb r2, [r3, #0] uint32_t tmpCFGR1 = 0U; 8000a74: 2300 movs r3, #0 8000a76: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) 8000a78: 687b ldr r3, [r7, #4] 8000a7a: 2b00 cmp r3, #0 8000a7c: d101 bne.n 8000a82 { return HAL_ERROR; 8000a7e: 2301 movs r3, #1 8000a80: e125 b.n 8000cce /* Refer to header of this file for more details on clock enabling procedure*/ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) 8000a82: 687b ldr r3, [r7, #4] 8000a84: 6b9b ldr r3, [r3, #56] ; 0x38 8000a86: 2b00 cmp r3, #0 8000a88: d10a bne.n 8000aa0 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8000a8a: 687b ldr r3, [r7, #4] 8000a8c: 2200 movs r2, #0 8000a8e: 63da str r2, [r3, #60] ; 0x3c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8000a90: 687b ldr r3, [r7, #4] 8000a92: 2234 movs r2, #52 ; 0x34 8000a94: 2100 movs r1, #0 8000a96: 5499 strb r1, [r3, r2] /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8000a98: 687b ldr r3, [r7, #4] 8000a9a: 0018 movs r0, r3 8000a9c: f7ff fe34 bl 8000708 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ /* and if there is no conversion on going on regular group (ADC can be */ /* enabled anyway, in case of call of this function to update a parameter */ /* on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8000aa0: 687b ldr r3, [r7, #4] 8000aa2: 6b9b ldr r3, [r3, #56] ; 0x38 8000aa4: 2210 movs r2, #16 8000aa6: 4013 ands r3, r2 8000aa8: d000 beq.n 8000aac 8000aaa: e103 b.n 8000cb4 8000aac: 230f movs r3, #15 8000aae: 18fb adds r3, r7, r3 8000ab0: 781b ldrb r3, [r3, #0] 8000ab2: 2b00 cmp r3, #0 8000ab4: d000 beq.n 8000ab8 8000ab6: e0fd b.n 8000cb4 (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 8000ab8: 687b ldr r3, [r7, #4] 8000aba: 681b ldr r3, [r3, #0] 8000abc: 689b ldr r3, [r3, #8] 8000abe: 2204 movs r2, #4 8000ac0: 4013 ands r3, r2 (tmp_hal_status == HAL_OK) && 8000ac2: d000 beq.n 8000ac6 8000ac4: e0f6 b.n 8000cb4 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000ac6: 687b ldr r3, [r7, #4] 8000ac8: 6b9b ldr r3, [r3, #56] ; 0x38 8000aca: 4a83 ldr r2, [pc, #524] ; (8000cd8 ) 8000acc: 4013 ands r3, r2 8000ace: 2202 movs r2, #2 8000ad0: 431a orrs r2, r3 8000ad2: 687b ldr r3, [r7, #4] 8000ad4: 639a str r2, [r3, #56] ; 0x38 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - ADC clock mode */ /* - ADC clock prescaler */ /* - ADC resolution */ if (ADC_IS_ENABLE(hadc) == RESET) 8000ad6: 687b ldr r3, [r7, #4] 8000ad8: 681b ldr r3, [r3, #0] 8000ada: 689b ldr r3, [r3, #8] 8000adc: 2203 movs r2, #3 8000ade: 4013 ands r3, r2 8000ae0: 2b01 cmp r3, #1 8000ae2: d112 bne.n 8000b0a 8000ae4: 687b ldr r3, [r7, #4] 8000ae6: 681b ldr r3, [r3, #0] 8000ae8: 681b ldr r3, [r3, #0] 8000aea: 2201 movs r2, #1 8000aec: 4013 ands r3, r2 8000aee: 2b01 cmp r3, #1 8000af0: d009 beq.n 8000b06 8000af2: 687b ldr r3, [r7, #4] 8000af4: 681b ldr r3, [r3, #0] 8000af6: 68da ldr r2, [r3, #12] 8000af8: 2380 movs r3, #128 ; 0x80 8000afa: 021b lsls r3, r3, #8 8000afc: 401a ands r2, r3 8000afe: 2380 movs r3, #128 ; 0x80 8000b00: 021b lsls r3, r3, #8 8000b02: 429a cmp r2, r3 8000b04: d101 bne.n 8000b0a 8000b06: 2301 movs r3, #1 8000b08: e000 b.n 8000b0c 8000b0a: 2300 movs r3, #0 8000b0c: 2b00 cmp r3, #0 8000b0e: d116 bne.n 8000b3e /* parameters): */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ MODIFY_REG(hadc->Instance->CFGR1, 8000b10: 687b ldr r3, [r7, #4] 8000b12: 681b ldr r3, [r3, #0] 8000b14: 68db ldr r3, [r3, #12] 8000b16: 2218 movs r2, #24 8000b18: 4393 bics r3, r2 8000b1a: 0019 movs r1, r3 8000b1c: 687b ldr r3, [r7, #4] 8000b1e: 689a ldr r2, [r3, #8] 8000b20: 687b ldr r3, [r7, #4] 8000b22: 681b ldr r3, [r3, #0] 8000b24: 430a orrs r2, r1 8000b26: 60da str r2, [r3, #12] ADC_CFGR1_RES , hadc->Init.Resolution ); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler */ MODIFY_REG(hadc->Instance->CFGR2 , 8000b28: 687b ldr r3, [r7, #4] 8000b2a: 681b ldr r3, [r3, #0] 8000b2c: 691b ldr r3, [r3, #16] 8000b2e: 009b lsls r3, r3, #2 8000b30: 0899 lsrs r1, r3, #2 8000b32: 687b ldr r3, [r7, #4] 8000b34: 685a ldr r2, [r3, #4] 8000b36: 687b ldr r3, [r7, #4] 8000b38: 681b ldr r3, [r3, #0] 8000b3a: 430a orrs r2, r1 8000b3c: 611a str r2, [r3, #16] /* - external trigger polarity */ /* - data alignment */ /* - resolution */ /* - scan direction */ /* - DMA continuous request */ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | 8000b3e: 687b ldr r3, [r7, #4] 8000b40: 681b ldr r3, [r3, #0] 8000b42: 68da ldr r2, [r3, #12] 8000b44: 687b ldr r3, [r7, #4] 8000b46: 681b ldr r3, [r3, #0] 8000b48: 4964 ldr r1, [pc, #400] ; (8000cdc ) 8000b4a: 400a ands r2, r1 8000b4c: 60da str r2, [r3, #12] ADC_CFGR1_EXTEN | ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG ); tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b4e: 687b ldr r3, [r7, #4] 8000b50: 7e1b ldrb r3, [r3, #24] 8000b52: 039a lsls r2, r3, #14 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b54: 687b ldr r3, [r7, #4] 8000b56: 7e5b ldrb r3, [r3, #25] 8000b58: 03db lsls r3, r3, #15 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b5a: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b5c: 687b ldr r3, [r7, #4] 8000b5e: 7e9b ldrb r3, [r3, #26] 8000b60: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b62: 431a orrs r2, r3 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b64: 687b ldr r3, [r7, #4] 8000b66: 6a9b ldr r3, [r3, #40] ; 0x28 8000b68: 2b01 cmp r3, #1 8000b6a: d002 beq.n 8000b72 8000b6c: 2380 movs r3, #128 ; 0x80 8000b6e: 015b lsls r3, r3, #5 8000b70: e000 b.n 8000b74 8000b72: 2300 movs r3, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b74: 431a orrs r2, r3 hadc->Init.DataAlign | 8000b76: 687b ldr r3, [r7, #4] 8000b78: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b7a: 431a orrs r2, r3 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b7c: 687b ldr r3, [r7, #4] 8000b7e: 691b ldr r3, [r3, #16] 8000b80: 2b02 cmp r3, #2 8000b82: d101 bne.n 8000b88 8000b84: 2304 movs r3, #4 8000b86: e000 b.n 8000b8a 8000b88: 2300 movs r3, #0 hadc->Init.DataAlign | 8000b8a: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); 8000b8c: 687b ldr r3, [r7, #4] 8000b8e: 2124 movs r1, #36 ; 0x24 8000b90: 5c5b ldrb r3, [r3, r1] 8000b92: 005b lsls r3, r3, #1 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b94: 4313 orrs r3, r2 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b96: 68ba ldr r2, [r7, #8] 8000b98: 4313 orrs r3, r2 8000b9a: 60bb str r3, [r7, #8] /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8000b9c: 687b ldr r3, [r7, #4] 8000b9e: 7edb ldrb r3, [r3, #27] 8000ba0: 2b01 cmp r3, #1 8000ba2: d115 bne.n 8000bd0 { if (hadc->Init.ContinuousConvMode == DISABLE) 8000ba4: 687b ldr r3, [r7, #4] 8000ba6: 7e9b ldrb r3, [r3, #26] 8000ba8: 2b00 cmp r3, #0 8000baa: d105 bne.n 8000bb8 { /* Enable the selected ADC group regular discontinuous mode */ tmpCFGR1 |= ADC_CFGR1_DISCEN; 8000bac: 68bb ldr r3, [r7, #8] 8000bae: 2280 movs r2, #128 ; 0x80 8000bb0: 0252 lsls r2, r2, #9 8000bb2: 4313 orrs r3, r2 8000bb4: 60bb str r3, [r7, #8] 8000bb6: e00b b.n 8000bd0 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000bb8: 687b ldr r3, [r7, #4] 8000bba: 6b9b ldr r3, [r3, #56] ; 0x38 8000bbc: 2220 movs r2, #32 8000bbe: 431a orrs r2, r3 8000bc0: 687b ldr r3, [r7, #4] 8000bc2: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000bc4: 687b ldr r3, [r7, #4] 8000bc6: 6bdb ldr r3, [r3, #60] ; 0x3c 8000bc8: 2201 movs r2, #1 8000bca: 431a orrs r2, r3 8000bcc: 687b ldr r3, [r7, #4] 8000bce: 63da str r2, [r3, #60] ; 0x3c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8000bd0: 687b ldr r3, [r7, #4] 8000bd2: 69da ldr r2, [r3, #28] 8000bd4: 23c2 movs r3, #194 ; 0xc2 8000bd6: 33ff adds r3, #255 ; 0xff 8000bd8: 429a cmp r2, r3 8000bda: d007 beq.n 8000bec { tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000bdc: 687b ldr r3, [r7, #4] 8000bde: 69da ldr r2, [r3, #28] hadc->Init.ExternalTrigConvEdge ); 8000be0: 687b ldr r3, [r7, #4] 8000be2: 6a1b ldr r3, [r3, #32] tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000be4: 4313 orrs r3, r2 8000be6: 68ba ldr r2, [r7, #8] 8000be8: 4313 orrs r3, r2 8000bea: 60bb str r3, [r7, #8] } /* Update ADC configuration register with previous settings */ hadc->Instance->CFGR1 |= tmpCFGR1; 8000bec: 687b ldr r3, [r7, #4] 8000bee: 681b ldr r3, [r3, #0] 8000bf0: 68d9 ldr r1, [r3, #12] 8000bf2: 687b ldr r3, [r7, #4] 8000bf4: 681b ldr r3, [r3, #0] 8000bf6: 68ba ldr r2, [r7, #8] 8000bf8: 430a orrs r2, r1 8000bfa: 60da str r2, [r3, #12] /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function if parameter */ /* "SamplingTimeCommon" has been set to a valid sampling time. */ /* Otherwise, sampling time is set into ADC channel initialization */ /* structure with parameter "SamplingTime" (obsolete). */ if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000bfc: 687b ldr r3, [r7, #4] 8000bfe: 6ada ldr r2, [r3, #44] ; 0x2c 8000c00: 2380 movs r3, #128 ; 0x80 8000c02: 055b lsls r3, r3, #21 8000c04: 429a cmp r2, r3 8000c06: d01b beq.n 8000c40 8000c08: 687b ldr r3, [r7, #4] 8000c0a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c0c: 2b01 cmp r3, #1 8000c0e: d017 beq.n 8000c40 8000c10: 687b ldr r3, [r7, #4] 8000c12: 6adb ldr r3, [r3, #44] ; 0x2c 8000c14: 2b02 cmp r3, #2 8000c16: d013 beq.n 8000c40 8000c18: 687b ldr r3, [r7, #4] 8000c1a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c1c: 2b03 cmp r3, #3 8000c1e: d00f beq.n 8000c40 8000c20: 687b ldr r3, [r7, #4] 8000c22: 6adb ldr r3, [r3, #44] ; 0x2c 8000c24: 2b04 cmp r3, #4 8000c26: d00b beq.n 8000c40 8000c28: 687b ldr r3, [r7, #4] 8000c2a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c2c: 2b05 cmp r3, #5 8000c2e: d007 beq.n 8000c40 8000c30: 687b ldr r3, [r7, #4] 8000c32: 6adb ldr r3, [r3, #44] ; 0x2c 8000c34: 2b06 cmp r3, #6 8000c36: d003 beq.n 8000c40 8000c38: 687b ldr r3, [r7, #4] 8000c3a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c3c: 2b07 cmp r3, #7 8000c3e: d112 bne.n 8000c66 { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000c40: 687b ldr r3, [r7, #4] 8000c42: 681b ldr r3, [r3, #0] 8000c44: 695a ldr r2, [r3, #20] 8000c46: 687b ldr r3, [r7, #4] 8000c48: 681b ldr r3, [r3, #0] 8000c4a: 2107 movs r1, #7 8000c4c: 438a bics r2, r1 8000c4e: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); 8000c50: 687b ldr r3, [r7, #4] 8000c52: 681b ldr r3, [r3, #0] 8000c54: 6959 ldr r1, [r3, #20] 8000c56: 687b ldr r3, [r7, #4] 8000c58: 6adb ldr r3, [r3, #44] ; 0x2c 8000c5a: 2207 movs r2, #7 8000c5c: 401a ands r2, r3 8000c5e: 687b ldr r3, [r7, #4] 8000c60: 681b ldr r3, [r3, #0] 8000c62: 430a orrs r2, r1 8000c64: 615a str r2, [r3, #20] /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ /* set into separate dedicated function, and bits of ADC resolution set */ /* out of temporary variable 'tmpCFGR1'). */ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c66: 687b ldr r3, [r7, #4] 8000c68: 681b ldr r3, [r3, #0] 8000c6a: 68db ldr r3, [r3, #12] 8000c6c: 4a1c ldr r2, [pc, #112] ; (8000ce0 ) 8000c6e: 4013 ands r3, r2 8000c70: 68ba ldr r2, [r7, #8] 8000c72: 429a cmp r2, r3 8000c74: d10b bne.n 8000c8e == tmpCFGR1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8000c76: 687b ldr r3, [r7, #4] 8000c78: 2200 movs r2, #0 8000c7a: 63da str r2, [r3, #60] ; 0x3c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000c7c: 687b ldr r3, [r7, #4] 8000c7e: 6b9b ldr r3, [r3, #56] ; 0x38 8000c80: 2203 movs r2, #3 8000c82: 4393 bics r3, r2 8000c84: 2201 movs r2, #1 8000c86: 431a orrs r2, r3 8000c88: 687b ldr r3, [r7, #4] 8000c8a: 639a str r2, [r3, #56] ; 0x38 if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c8c: e01c b.n 8000cc8 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8000c8e: 687b ldr r3, [r7, #4] 8000c90: 6b9b ldr r3, [r3, #56] ; 0x38 8000c92: 2212 movs r2, #18 8000c94: 4393 bics r3, r2 8000c96: 2210 movs r2, #16 8000c98: 431a orrs r2, r3 8000c9a: 687b ldr r3, [r7, #4] 8000c9c: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000c9e: 687b ldr r3, [r7, #4] 8000ca0: 6bdb ldr r3, [r3, #60] ; 0x3c 8000ca2: 2201 movs r2, #1 8000ca4: 431a orrs r2, r3 8000ca6: 687b ldr r3, [r7, #4] 8000ca8: 63da str r2, [r3, #60] ; 0x3c tmp_hal_status = HAL_ERROR; 8000caa: 230f movs r3, #15 8000cac: 18fb adds r3, r7, r3 8000cae: 2201 movs r2, #1 8000cb0: 701a strb r2, [r3, #0] if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000cb2: e009 b.n 8000cc8 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000cb4: 687b ldr r3, [r7, #4] 8000cb6: 6b9b ldr r3, [r3, #56] ; 0x38 8000cb8: 2210 movs r2, #16 8000cba: 431a orrs r2, r3 8000cbc: 687b ldr r3, [r7, #4] 8000cbe: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000cc0: 230f movs r3, #15 8000cc2: 18fb adds r3, r7, r3 8000cc4: 2201 movs r2, #1 8000cc6: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000cc8: 230f movs r3, #15 8000cca: 18fb adds r3, r7, r3 8000ccc: 781b ldrb r3, [r3, #0] } 8000cce: 0018 movs r0, r3 8000cd0: 46bd mov sp, r7 8000cd2: b004 add sp, #16 8000cd4: bd80 pop {r7, pc} 8000cd6: 46c0 nop ; (mov r8, r8) 8000cd8: fffffefd .word 0xfffffefd 8000cdc: fffe0219 .word 0xfffe0219 8000ce0: 833fffe7 .word 0x833fffe7 08000ce4 : * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8000ce4: b580 push {r7, lr} 8000ce6: b084 sub sp, #16 8000ce8: af00 add r7, sp, #0 8000cea: 6078 str r0, [r7, #4] 8000cec: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000cee: 230f movs r3, #15 8000cf0: 18fb adds r3, r7, r3 8000cf2: 2200 movs r2, #0 8000cf4: 701a strb r2, [r3, #0] __IO uint32_t wait_loop_index = 0U; 8000cf6: 2300 movs r3, #0 8000cf8: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_RANK(sConfig->Rank)); if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000cfa: 687b ldr r3, [r7, #4] 8000cfc: 6ada ldr r2, [r3, #44] ; 0x2c 8000cfe: 2380 movs r3, #128 ; 0x80 8000d00: 055b lsls r3, r3, #21 8000d02: 429a cmp r2, r3 8000d04: d011 beq.n 8000d2a 8000d06: 687b ldr r3, [r7, #4] 8000d08: 6adb ldr r3, [r3, #44] ; 0x2c 8000d0a: 2b01 cmp r3, #1 8000d0c: d00d beq.n 8000d2a 8000d0e: 687b ldr r3, [r7, #4] 8000d10: 6adb ldr r3, [r3, #44] ; 0x2c 8000d12: 2b02 cmp r3, #2 8000d14: d009 beq.n 8000d2a 8000d16: 687b ldr r3, [r7, #4] 8000d18: 6adb ldr r3, [r3, #44] ; 0x2c 8000d1a: 2b03 cmp r3, #3 8000d1c: d005 beq.n 8000d2a 8000d1e: 687b ldr r3, [r7, #4] 8000d20: 6adb ldr r3, [r3, #44] ; 0x2c 8000d22: 2b04 cmp r3, #4 8000d24: d001 beq.n 8000d2a 8000d26: 687b ldr r3, [r7, #4] 8000d28: 6adb ldr r3, [r3, #44] ; 0x2c { assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); } /* Process locked */ __HAL_LOCK(hadc); 8000d2a: 687b ldr r3, [r7, #4] 8000d2c: 2234 movs r2, #52 ; 0x34 8000d2e: 5c9b ldrb r3, [r3, r2] 8000d30: 2b01 cmp r3, #1 8000d32: d101 bne.n 8000d38 8000d34: 2302 movs r3, #2 8000d36: e0bb b.n 8000eb0 8000d38: 687b ldr r3, [r7, #4] 8000d3a: 2234 movs r2, #52 ; 0x34 8000d3c: 2101 movs r1, #1 8000d3e: 5499 strb r1, [r3, r2] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000d40: 687b ldr r3, [r7, #4] 8000d42: 681b ldr r3, [r3, #0] 8000d44: 689b ldr r3, [r3, #8] 8000d46: 2204 movs r2, #4 8000d48: 4013 ands r3, r2 8000d4a: d000 beq.n 8000d4e 8000d4c: e09f b.n 8000e8e { /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC conversion sequencer. */ if (sConfig->Rank != ADC_RANK_NONE) 8000d4e: 683b ldr r3, [r7, #0] 8000d50: 685b ldr r3, [r3, #4] 8000d52: 4a59 ldr r2, [pc, #356] ; (8000eb8 ) 8000d54: 4293 cmp r3, r2 8000d56: d100 bne.n 8000d5a 8000d58: e077 b.n 8000e4a { /* Regular sequence configuration */ /* Set the channel selection register from the selected channel */ hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); 8000d5a: 687b ldr r3, [r7, #4] 8000d5c: 681b ldr r3, [r3, #0] 8000d5e: 6a99 ldr r1, [r3, #40] ; 0x28 8000d60: 683b ldr r3, [r7, #0] 8000d62: 681b ldr r3, [r3, #0] 8000d64: 2201 movs r2, #1 8000d66: 409a lsls r2, r3 8000d68: 687b ldr r3, [r7, #4] 8000d6a: 681b ldr r3, [r3, #0] 8000d6c: 430a orrs r2, r1 8000d6e: 629a str r2, [r3, #40] ; 0x28 /* Channel sampling time configuration */ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function with */ /* parameter "SamplingTime" (obsolete) only if not already set into */ /* ADC initialization structure with parameter "SamplingTimeCommon". */ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000d70: 687b ldr r3, [r7, #4] 8000d72: 6ada ldr r2, [r3, #44] ; 0x2c 8000d74: 2380 movs r3, #128 ; 0x80 8000d76: 055b lsls r3, r3, #21 8000d78: 429a cmp r2, r3 8000d7a: d037 beq.n 8000dec 8000d7c: 687b ldr r3, [r7, #4] 8000d7e: 6adb ldr r3, [r3, #44] ; 0x2c 8000d80: 2b01 cmp r3, #1 8000d82: d033 beq.n 8000dec 8000d84: 687b ldr r3, [r7, #4] 8000d86: 6adb ldr r3, [r3, #44] ; 0x2c 8000d88: 2b02 cmp r3, #2 8000d8a: d02f beq.n 8000dec 8000d8c: 687b ldr r3, [r7, #4] 8000d8e: 6adb ldr r3, [r3, #44] ; 0x2c 8000d90: 2b03 cmp r3, #3 8000d92: d02b beq.n 8000dec 8000d94: 687b ldr r3, [r7, #4] 8000d96: 6adb ldr r3, [r3, #44] ; 0x2c 8000d98: 2b04 cmp r3, #4 8000d9a: d027 beq.n 8000dec 8000d9c: 687b ldr r3, [r7, #4] 8000d9e: 6adb ldr r3, [r3, #44] ; 0x2c 8000da0: 2b05 cmp r3, #5 8000da2: d023 beq.n 8000dec 8000da4: 687b ldr r3, [r7, #4] 8000da6: 6adb ldr r3, [r3, #44] ; 0x2c 8000da8: 2b06 cmp r3, #6 8000daa: d01f beq.n 8000dec 8000dac: 687b ldr r3, [r7, #4] 8000dae: 6adb ldr r3, [r3, #44] ; 0x2c 8000db0: 2b07 cmp r3, #7 8000db2: d01b beq.n 8000dec { /* Modify sampling time if needed (not needed in case of reoccurrence */ /* for several channels programmed consecutively into the sequencer) */ if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) 8000db4: 683b ldr r3, [r7, #0] 8000db6: 689a ldr r2, [r3, #8] 8000db8: 687b ldr r3, [r7, #4] 8000dba: 681b ldr r3, [r3, #0] 8000dbc: 695b ldr r3, [r3, #20] 8000dbe: 2107 movs r1, #7 8000dc0: 400b ands r3, r1 8000dc2: 429a cmp r2, r3 8000dc4: d012 beq.n 8000dec { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000dc6: 687b ldr r3, [r7, #4] 8000dc8: 681b ldr r3, [r3, #0] 8000dca: 695a ldr r2, [r3, #20] 8000dcc: 687b ldr r3, [r7, #4] 8000dce: 681b ldr r3, [r3, #0] 8000dd0: 2107 movs r1, #7 8000dd2: 438a bics r2, r1 8000dd4: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); 8000dd6: 687b ldr r3, [r7, #4] 8000dd8: 681b ldr r3, [r3, #0] 8000dda: 6959 ldr r1, [r3, #20] 8000ddc: 683b ldr r3, [r7, #0] 8000dde: 689b ldr r3, [r3, #8] 8000de0: 2207 movs r2, #7 8000de2: 401a ands r2, r3 8000de4: 687b ldr r3, [r7, #4] 8000de6: 681b ldr r3, [r3, #0] 8000de8: 430a orrs r2, r1 8000dea: 615a str r2, [r3, #20] /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8000dec: 683b ldr r3, [r7, #0] 8000dee: 681b ldr r3, [r3, #0] 8000df0: 2b10 cmp r3, #16 8000df2: d003 beq.n 8000dfc 8000df4: 683b ldr r3, [r7, #0] 8000df6: 681b ldr r3, [r3, #0] 8000df8: 2b11 cmp r3, #17 8000dfa: d152 bne.n 8000ea2 { /* If Channel_16 is selected, enable Temp. sensor measurement path. */ /* If Channel_17 is selected, enable VREFINT measurement path. */ /* If Channel_18 is selected, enable VBAT measurement path. */ ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 8000dfc: 4b2f ldr r3, [pc, #188] ; (8000ebc ) 8000dfe: 6819 ldr r1, [r3, #0] 8000e00: 683b ldr r3, [r7, #0] 8000e02: 681b ldr r3, [r3, #0] 8000e04: 2b10 cmp r3, #16 8000e06: d102 bne.n 8000e0e 8000e08: 2380 movs r3, #128 ; 0x80 8000e0a: 041b lsls r3, r3, #16 8000e0c: e001 b.n 8000e12 8000e0e: 2380 movs r3, #128 ; 0x80 8000e10: 03db lsls r3, r3, #15 8000e12: 4a2a ldr r2, [pc, #168] ; (8000ebc ) 8000e14: 430b orrs r3, r1 8000e16: 6013 str r3, [r2, #0] /* If Temp. sensor is selected, wait for stabilization delay */ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8000e18: 683b ldr r3, [r7, #0] 8000e1a: 681b ldr r3, [r3, #0] 8000e1c: 2b10 cmp r3, #16 8000e1e: d140 bne.n 8000ea2 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8000e20: 4b27 ldr r3, [pc, #156] ; (8000ec0 ) 8000e22: 681b ldr r3, [r3, #0] 8000e24: 4927 ldr r1, [pc, #156] ; (8000ec4 ) 8000e26: 0018 movs r0, r3 8000e28: f7ff f978 bl 800011c <__udivsi3> 8000e2c: 0003 movs r3, r0 8000e2e: 001a movs r2, r3 8000e30: 0013 movs r3, r2 8000e32: 009b lsls r3, r3, #2 8000e34: 189b adds r3, r3, r2 8000e36: 005b lsls r3, r3, #1 8000e38: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000e3a: e002 b.n 8000e42 { wait_loop_index--; 8000e3c: 68bb ldr r3, [r7, #8] 8000e3e: 3b01 subs r3, #1 8000e40: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000e42: 68bb ldr r3, [r7, #8] 8000e44: 2b00 cmp r3, #0 8000e46: d1f9 bne.n 8000e3c 8000e48: e02b b.n 8000ea2 } else { /* Regular sequence configuration */ /* Reset the channel selection register from the selected channel */ hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); 8000e4a: 687b ldr r3, [r7, #4] 8000e4c: 681b ldr r3, [r3, #0] 8000e4e: 6a9a ldr r2, [r3, #40] ; 0x28 8000e50: 683b ldr r3, [r7, #0] 8000e52: 681b ldr r3, [r3, #0] 8000e54: 2101 movs r1, #1 8000e56: 4099 lsls r1, r3 8000e58: 000b movs r3, r1 8000e5a: 43d9 mvns r1, r3 8000e5c: 687b ldr r3, [r7, #4] 8000e5e: 681b ldr r3, [r3, #0] 8000e60: 400a ands r2, r1 8000e62: 629a str r2, [r3, #40] ; 0x28 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths disable: If internal channel selected, */ /* disable dedicated internal buffers and path. */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8000e64: 683b ldr r3, [r7, #0] 8000e66: 681b ldr r3, [r3, #0] 8000e68: 2b10 cmp r3, #16 8000e6a: d003 beq.n 8000e74 8000e6c: 683b ldr r3, [r7, #0] 8000e6e: 681b ldr r3, [r3, #0] 8000e70: 2b11 cmp r3, #17 8000e72: d116 bne.n 8000ea2 { /* If Channel_16 is selected, disable Temp. sensor measurement path. */ /* If Channel_17 is selected, disable VREFINT measurement path. */ /* If Channel_18 is selected, disable VBAT measurement path. */ ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 8000e74: 4b11 ldr r3, [pc, #68] ; (8000ebc ) 8000e76: 6819 ldr r1, [r3, #0] 8000e78: 683b ldr r3, [r7, #0] 8000e7a: 681b ldr r3, [r3, #0] 8000e7c: 2b10 cmp r3, #16 8000e7e: d101 bne.n 8000e84 8000e80: 4a11 ldr r2, [pc, #68] ; (8000ec8 ) 8000e82: e000 b.n 8000e86 8000e84: 4a11 ldr r2, [pc, #68] ; (8000ecc ) 8000e86: 4b0d ldr r3, [pc, #52] ; (8000ebc ) 8000e88: 400a ands r2, r1 8000e8a: 601a str r2, [r3, #0] 8000e8c: e009 b.n 8000ea2 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000e8e: 687b ldr r3, [r7, #4] 8000e90: 6b9b ldr r3, [r3, #56] ; 0x38 8000e92: 2220 movs r2, #32 8000e94: 431a orrs r2, r3 8000e96: 687b ldr r3, [r7, #4] 8000e98: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000e9a: 230f movs r3, #15 8000e9c: 18fb adds r3, r7, r3 8000e9e: 2201 movs r2, #1 8000ea0: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000ea2: 687b ldr r3, [r7, #4] 8000ea4: 2234 movs r2, #52 ; 0x34 8000ea6: 2100 movs r1, #0 8000ea8: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 8000eaa: 230f movs r3, #15 8000eac: 18fb adds r3, r7, r3 8000eae: 781b ldrb r3, [r3, #0] } 8000eb0: 0018 movs r0, r3 8000eb2: 46bd mov sp, r7 8000eb4: b004 add sp, #16 8000eb6: bd80 pop {r7, pc} 8000eb8: 00001001 .word 0x00001001 8000ebc: 40012708 .word 0x40012708 8000ec0: 20000000 .word 0x20000000 8000ec4: 000f4240 .word 0x000f4240 8000ec8: ff7fffff .word 0xff7fffff 8000ecc: ffbfffff .word 0xffbfffff 08000ed0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000ed0: b590 push {r4, r7, lr} 8000ed2: b083 sub sp, #12 8000ed4: af00 add r7, sp, #0 8000ed6: 0002 movs r2, r0 8000ed8: 6039 str r1, [r7, #0] 8000eda: 1dfb adds r3, r7, #7 8000edc: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8000ede: 1dfb adds r3, r7, #7 8000ee0: 781b ldrb r3, [r3, #0] 8000ee2: 2b7f cmp r3, #127 ; 0x7f 8000ee4: d828 bhi.n 8000f38 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000ee6: 4a2f ldr r2, [pc, #188] ; (8000fa4 <__NVIC_SetPriority+0xd4>) 8000ee8: 1dfb adds r3, r7, #7 8000eea: 781b ldrb r3, [r3, #0] 8000eec: b25b sxtb r3, r3 8000eee: 089b lsrs r3, r3, #2 8000ef0: 33c0 adds r3, #192 ; 0xc0 8000ef2: 009b lsls r3, r3, #2 8000ef4: 589b ldr r3, [r3, r2] 8000ef6: 1dfa adds r2, r7, #7 8000ef8: 7812 ldrb r2, [r2, #0] 8000efa: 0011 movs r1, r2 8000efc: 2203 movs r2, #3 8000efe: 400a ands r2, r1 8000f00: 00d2 lsls r2, r2, #3 8000f02: 21ff movs r1, #255 ; 0xff 8000f04: 4091 lsls r1, r2 8000f06: 000a movs r2, r1 8000f08: 43d2 mvns r2, r2 8000f0a: 401a ands r2, r3 8000f0c: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8000f0e: 683b ldr r3, [r7, #0] 8000f10: 019b lsls r3, r3, #6 8000f12: 22ff movs r2, #255 ; 0xff 8000f14: 401a ands r2, r3 8000f16: 1dfb adds r3, r7, #7 8000f18: 781b ldrb r3, [r3, #0] 8000f1a: 0018 movs r0, r3 8000f1c: 2303 movs r3, #3 8000f1e: 4003 ands r3, r0 8000f20: 00db lsls r3, r3, #3 8000f22: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000f24: 481f ldr r0, [pc, #124] ; (8000fa4 <__NVIC_SetPriority+0xd4>) 8000f26: 1dfb adds r3, r7, #7 8000f28: 781b ldrb r3, [r3, #0] 8000f2a: b25b sxtb r3, r3 8000f2c: 089b lsrs r3, r3, #2 8000f2e: 430a orrs r2, r1 8000f30: 33c0 adds r3, #192 ; 0xc0 8000f32: 009b lsls r3, r3, #2 8000f34: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8000f36: e031 b.n 8000f9c <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000f38: 4a1b ldr r2, [pc, #108] ; (8000fa8 <__NVIC_SetPriority+0xd8>) 8000f3a: 1dfb adds r3, r7, #7 8000f3c: 781b ldrb r3, [r3, #0] 8000f3e: 0019 movs r1, r3 8000f40: 230f movs r3, #15 8000f42: 400b ands r3, r1 8000f44: 3b08 subs r3, #8 8000f46: 089b lsrs r3, r3, #2 8000f48: 3306 adds r3, #6 8000f4a: 009b lsls r3, r3, #2 8000f4c: 18d3 adds r3, r2, r3 8000f4e: 3304 adds r3, #4 8000f50: 681b ldr r3, [r3, #0] 8000f52: 1dfa adds r2, r7, #7 8000f54: 7812 ldrb r2, [r2, #0] 8000f56: 0011 movs r1, r2 8000f58: 2203 movs r2, #3 8000f5a: 400a ands r2, r1 8000f5c: 00d2 lsls r2, r2, #3 8000f5e: 21ff movs r1, #255 ; 0xff 8000f60: 4091 lsls r1, r2 8000f62: 000a movs r2, r1 8000f64: 43d2 mvns r2, r2 8000f66: 401a ands r2, r3 8000f68: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8000f6a: 683b ldr r3, [r7, #0] 8000f6c: 019b lsls r3, r3, #6 8000f6e: 22ff movs r2, #255 ; 0xff 8000f70: 401a ands r2, r3 8000f72: 1dfb adds r3, r7, #7 8000f74: 781b ldrb r3, [r3, #0] 8000f76: 0018 movs r0, r3 8000f78: 2303 movs r3, #3 8000f7a: 4003 ands r3, r0 8000f7c: 00db lsls r3, r3, #3 8000f7e: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000f80: 4809 ldr r0, [pc, #36] ; (8000fa8 <__NVIC_SetPriority+0xd8>) 8000f82: 1dfb adds r3, r7, #7 8000f84: 781b ldrb r3, [r3, #0] 8000f86: 001c movs r4, r3 8000f88: 230f movs r3, #15 8000f8a: 4023 ands r3, r4 8000f8c: 3b08 subs r3, #8 8000f8e: 089b lsrs r3, r3, #2 8000f90: 430a orrs r2, r1 8000f92: 3306 adds r3, #6 8000f94: 009b lsls r3, r3, #2 8000f96: 18c3 adds r3, r0, r3 8000f98: 3304 adds r3, #4 8000f9a: 601a str r2, [r3, #0] } 8000f9c: 46c0 nop ; (mov r8, r8) 8000f9e: 46bd mov sp, r7 8000fa0: b003 add sp, #12 8000fa2: bd90 pop {r4, r7, pc} 8000fa4: e000e100 .word 0xe000e100 8000fa8: e000ed00 .word 0xe000ed00 08000fac : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000fac: b580 push {r7, lr} 8000fae: b082 sub sp, #8 8000fb0: af00 add r7, sp, #0 8000fb2: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000fb4: 687b ldr r3, [r7, #4] 8000fb6: 1e5a subs r2, r3, #1 8000fb8: 2380 movs r3, #128 ; 0x80 8000fba: 045b lsls r3, r3, #17 8000fbc: 429a cmp r2, r3 8000fbe: d301 bcc.n 8000fc4 { return (1UL); /* Reload value impossible */ 8000fc0: 2301 movs r3, #1 8000fc2: e010 b.n 8000fe6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000fc4: 4b0a ldr r3, [pc, #40] ; (8000ff0 ) 8000fc6: 687a ldr r2, [r7, #4] 8000fc8: 3a01 subs r2, #1 8000fca: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000fcc: 2301 movs r3, #1 8000fce: 425b negs r3, r3 8000fd0: 2103 movs r1, #3 8000fd2: 0018 movs r0, r3 8000fd4: f7ff ff7c bl 8000ed0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000fd8: 4b05 ldr r3, [pc, #20] ; (8000ff0 ) 8000fda: 2200 movs r2, #0 8000fdc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000fde: 4b04 ldr r3, [pc, #16] ; (8000ff0 ) 8000fe0: 2207 movs r2, #7 8000fe2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000fe4: 2300 movs r3, #0 } 8000fe6: 0018 movs r0, r3 8000fe8: 46bd mov sp, r7 8000fea: b002 add sp, #8 8000fec: bd80 pop {r7, pc} 8000fee: 46c0 nop ; (mov r8, r8) 8000ff0: e000e010 .word 0xe000e010 08000ff4 : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000ff4: b580 push {r7, lr} 8000ff6: b084 sub sp, #16 8000ff8: af00 add r7, sp, #0 8000ffa: 60b9 str r1, [r7, #8] 8000ffc: 607a str r2, [r7, #4] 8000ffe: 210f movs r1, #15 8001000: 187b adds r3, r7, r1 8001002: 1c02 adds r2, r0, #0 8001004: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 8001006: 68ba ldr r2, [r7, #8] 8001008: 187b adds r3, r7, r1 800100a: 781b ldrb r3, [r3, #0] 800100c: b25b sxtb r3, r3 800100e: 0011 movs r1, r2 8001010: 0018 movs r0, r3 8001012: f7ff ff5d bl 8000ed0 <__NVIC_SetPriority> } 8001016: 46c0 nop ; (mov r8, r8) 8001018: 46bd mov sp, r7 800101a: b004 add sp, #16 800101c: bd80 pop {r7, pc} 0800101e : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800101e: b580 push {r7, lr} 8001020: b082 sub sp, #8 8001022: af00 add r7, sp, #0 8001024: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001026: 687b ldr r3, [r7, #4] 8001028: 0018 movs r0, r3 800102a: f7ff ffbf bl 8000fac 800102e: 0003 movs r3, r0 } 8001030: 0018 movs r0, r3 8001032: 46bd mov sp, r7 8001034: b002 add sp, #8 8001036: bd80 pop {r7, pc} 08001038 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001038: b580 push {r7, lr} 800103a: b086 sub sp, #24 800103c: af00 add r7, sp, #0 800103e: 6078 str r0, [r7, #4] 8001040: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8001042: 2300 movs r3, #0 8001044: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8001046: e14f b.n 80012e8 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8001048: 683b ldr r3, [r7, #0] 800104a: 681b ldr r3, [r3, #0] 800104c: 2101 movs r1, #1 800104e: 697a ldr r2, [r7, #20] 8001050: 4091 lsls r1, r2 8001052: 000a movs r2, r1 8001054: 4013 ands r3, r2 8001056: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8001058: 68fb ldr r3, [r7, #12] 800105a: 2b00 cmp r3, #0 800105c: d100 bne.n 8001060 800105e: e140 b.n 80012e2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001060: 683b ldr r3, [r7, #0] 8001062: 685b ldr r3, [r3, #4] 8001064: 2203 movs r2, #3 8001066: 4013 ands r3, r2 8001068: 2b01 cmp r3, #1 800106a: d005 beq.n 8001078 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800106c: 683b ldr r3, [r7, #0] 800106e: 685b ldr r3, [r3, #4] 8001070: 2203 movs r2, #3 8001072: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001074: 2b02 cmp r3, #2 8001076: d130 bne.n 80010da { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001078: 687b ldr r3, [r7, #4] 800107a: 689b ldr r3, [r3, #8] 800107c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 800107e: 697b ldr r3, [r7, #20] 8001080: 005b lsls r3, r3, #1 8001082: 2203 movs r2, #3 8001084: 409a lsls r2, r3 8001086: 0013 movs r3, r2 8001088: 43da mvns r2, r3 800108a: 693b ldr r3, [r7, #16] 800108c: 4013 ands r3, r2 800108e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8001090: 683b ldr r3, [r7, #0] 8001092: 68da ldr r2, [r3, #12] 8001094: 697b ldr r3, [r7, #20] 8001096: 005b lsls r3, r3, #1 8001098: 409a lsls r2, r3 800109a: 0013 movs r3, r2 800109c: 693a ldr r2, [r7, #16] 800109e: 4313 orrs r3, r2 80010a0: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80010a2: 687b ldr r3, [r7, #4] 80010a4: 693a ldr r2, [r7, #16] 80010a6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80010a8: 687b ldr r3, [r7, #4] 80010aa: 685b ldr r3, [r3, #4] 80010ac: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80010ae: 2201 movs r2, #1 80010b0: 697b ldr r3, [r7, #20] 80010b2: 409a lsls r2, r3 80010b4: 0013 movs r3, r2 80010b6: 43da mvns r2, r3 80010b8: 693b ldr r3, [r7, #16] 80010ba: 4013 ands r3, r2 80010bc: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80010be: 683b ldr r3, [r7, #0] 80010c0: 685b ldr r3, [r3, #4] 80010c2: 091b lsrs r3, r3, #4 80010c4: 2201 movs r2, #1 80010c6: 401a ands r2, r3 80010c8: 697b ldr r3, [r7, #20] 80010ca: 409a lsls r2, r3 80010cc: 0013 movs r3, r2 80010ce: 693a ldr r2, [r7, #16] 80010d0: 4313 orrs r3, r2 80010d2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80010d4: 687b ldr r3, [r7, #4] 80010d6: 693a ldr r2, [r7, #16] 80010d8: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80010da: 683b ldr r3, [r7, #0] 80010dc: 685b ldr r3, [r3, #4] 80010de: 2203 movs r2, #3 80010e0: 4013 ands r3, r2 80010e2: 2b03 cmp r3, #3 80010e4: d017 beq.n 8001116 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80010e6: 687b ldr r3, [r7, #4] 80010e8: 68db ldr r3, [r3, #12] 80010ea: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 80010ec: 697b ldr r3, [r7, #20] 80010ee: 005b lsls r3, r3, #1 80010f0: 2203 movs r2, #3 80010f2: 409a lsls r2, r3 80010f4: 0013 movs r3, r2 80010f6: 43da mvns r2, r3 80010f8: 693b ldr r3, [r7, #16] 80010fa: 4013 ands r3, r2 80010fc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 80010fe: 683b ldr r3, [r7, #0] 8001100: 689a ldr r2, [r3, #8] 8001102: 697b ldr r3, [r7, #20] 8001104: 005b lsls r3, r3, #1 8001106: 409a lsls r2, r3 8001108: 0013 movs r3, r2 800110a: 693a ldr r2, [r7, #16] 800110c: 4313 orrs r3, r2 800110e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001110: 687b ldr r3, [r7, #4] 8001112: 693a ldr r2, [r7, #16] 8001114: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001116: 683b ldr r3, [r7, #0] 8001118: 685b ldr r3, [r3, #4] 800111a: 2203 movs r2, #3 800111c: 4013 ands r3, r2 800111e: 2b02 cmp r3, #2 8001120: d123 bne.n 800116a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8001122: 697b ldr r3, [r7, #20] 8001124: 08da lsrs r2, r3, #3 8001126: 687b ldr r3, [r7, #4] 8001128: 3208 adds r2, #8 800112a: 0092 lsls r2, r2, #2 800112c: 58d3 ldr r3, [r2, r3] 800112e: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001130: 697b ldr r3, [r7, #20] 8001132: 2207 movs r2, #7 8001134: 4013 ands r3, r2 8001136: 009b lsls r3, r3, #2 8001138: 220f movs r2, #15 800113a: 409a lsls r2, r3 800113c: 0013 movs r3, r2 800113e: 43da mvns r2, r3 8001140: 693b ldr r3, [r7, #16] 8001142: 4013 ands r3, r2 8001144: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8001146: 683b ldr r3, [r7, #0] 8001148: 691a ldr r2, [r3, #16] 800114a: 697b ldr r3, [r7, #20] 800114c: 2107 movs r1, #7 800114e: 400b ands r3, r1 8001150: 009b lsls r3, r3, #2 8001152: 409a lsls r2, r3 8001154: 0013 movs r3, r2 8001156: 693a ldr r2, [r7, #16] 8001158: 4313 orrs r3, r2 800115a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 800115c: 697b ldr r3, [r7, #20] 800115e: 08da lsrs r2, r3, #3 8001160: 687b ldr r3, [r7, #4] 8001162: 3208 adds r2, #8 8001164: 0092 lsls r2, r2, #2 8001166: 6939 ldr r1, [r7, #16] 8001168: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800116a: 687b ldr r3, [r7, #4] 800116c: 681b ldr r3, [r3, #0] 800116e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8001170: 697b ldr r3, [r7, #20] 8001172: 005b lsls r3, r3, #1 8001174: 2203 movs r2, #3 8001176: 409a lsls r2, r3 8001178: 0013 movs r3, r2 800117a: 43da mvns r2, r3 800117c: 693b ldr r3, [r7, #16] 800117e: 4013 ands r3, r2 8001180: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8001182: 683b ldr r3, [r7, #0] 8001184: 685b ldr r3, [r3, #4] 8001186: 2203 movs r2, #3 8001188: 401a ands r2, r3 800118a: 697b ldr r3, [r7, #20] 800118c: 005b lsls r3, r3, #1 800118e: 409a lsls r2, r3 8001190: 0013 movs r3, r2 8001192: 693a ldr r2, [r7, #16] 8001194: 4313 orrs r3, r2 8001196: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001198: 687b ldr r3, [r7, #4] 800119a: 693a ldr r2, [r7, #16] 800119c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 800119e: 683b ldr r3, [r7, #0] 80011a0: 685a ldr r2, [r3, #4] 80011a2: 23c0 movs r3, #192 ; 0xc0 80011a4: 029b lsls r3, r3, #10 80011a6: 4013 ands r3, r2 80011a8: d100 bne.n 80011ac 80011aa: e09a b.n 80012e2 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80011ac: 4b54 ldr r3, [pc, #336] ; (8001300 ) 80011ae: 699a ldr r2, [r3, #24] 80011b0: 4b53 ldr r3, [pc, #332] ; (8001300 ) 80011b2: 2101 movs r1, #1 80011b4: 430a orrs r2, r1 80011b6: 619a str r2, [r3, #24] 80011b8: 4b51 ldr r3, [pc, #324] ; (8001300 ) 80011ba: 699b ldr r3, [r3, #24] 80011bc: 2201 movs r2, #1 80011be: 4013 ands r3, r2 80011c0: 60bb str r3, [r7, #8] 80011c2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 80011c4: 4a4f ldr r2, [pc, #316] ; (8001304 ) 80011c6: 697b ldr r3, [r7, #20] 80011c8: 089b lsrs r3, r3, #2 80011ca: 3302 adds r3, #2 80011cc: 009b lsls r3, r3, #2 80011ce: 589b ldr r3, [r3, r2] 80011d0: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80011d2: 697b ldr r3, [r7, #20] 80011d4: 2203 movs r2, #3 80011d6: 4013 ands r3, r2 80011d8: 009b lsls r3, r3, #2 80011da: 220f movs r2, #15 80011dc: 409a lsls r2, r3 80011de: 0013 movs r3, r2 80011e0: 43da mvns r2, r3 80011e2: 693b ldr r3, [r7, #16] 80011e4: 4013 ands r3, r2 80011e6: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 80011e8: 687a ldr r2, [r7, #4] 80011ea: 2390 movs r3, #144 ; 0x90 80011ec: 05db lsls r3, r3, #23 80011ee: 429a cmp r2, r3 80011f0: d013 beq.n 800121a 80011f2: 687b ldr r3, [r7, #4] 80011f4: 4a44 ldr r2, [pc, #272] ; (8001308 ) 80011f6: 4293 cmp r3, r2 80011f8: d00d beq.n 8001216 80011fa: 687b ldr r3, [r7, #4] 80011fc: 4a43 ldr r2, [pc, #268] ; (800130c ) 80011fe: 4293 cmp r3, r2 8001200: d007 beq.n 8001212 8001202: 687b ldr r3, [r7, #4] 8001204: 4a42 ldr r2, [pc, #264] ; (8001310 ) 8001206: 4293 cmp r3, r2 8001208: d101 bne.n 800120e 800120a: 2303 movs r3, #3 800120c: e006 b.n 800121c 800120e: 2305 movs r3, #5 8001210: e004 b.n 800121c 8001212: 2302 movs r3, #2 8001214: e002 b.n 800121c 8001216: 2301 movs r3, #1 8001218: e000 b.n 800121c 800121a: 2300 movs r3, #0 800121c: 697a ldr r2, [r7, #20] 800121e: 2103 movs r1, #3 8001220: 400a ands r2, r1 8001222: 0092 lsls r2, r2, #2 8001224: 4093 lsls r3, r2 8001226: 693a ldr r2, [r7, #16] 8001228: 4313 orrs r3, r2 800122a: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 800122c: 4935 ldr r1, [pc, #212] ; (8001304 ) 800122e: 697b ldr r3, [r7, #20] 8001230: 089b lsrs r3, r3, #2 8001232: 3302 adds r3, #2 8001234: 009b lsls r3, r3, #2 8001236: 693a ldr r2, [r7, #16] 8001238: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ temp = EXTI->IMR; 800123a: 4b36 ldr r3, [pc, #216] ; (8001314 ) 800123c: 681b ldr r3, [r3, #0] 800123e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001240: 68fb ldr r3, [r7, #12] 8001242: 43da mvns r2, r3 8001244: 693b ldr r3, [r7, #16] 8001246: 4013 ands r3, r2 8001248: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 800124a: 683b ldr r3, [r7, #0] 800124c: 685a ldr r2, [r3, #4] 800124e: 2380 movs r3, #128 ; 0x80 8001250: 025b lsls r3, r3, #9 8001252: 4013 ands r3, r2 8001254: d003 beq.n 800125e { temp |= iocurrent; 8001256: 693a ldr r2, [r7, #16] 8001258: 68fb ldr r3, [r7, #12] 800125a: 4313 orrs r3, r2 800125c: 613b str r3, [r7, #16] } EXTI->IMR = temp; 800125e: 4b2d ldr r3, [pc, #180] ; (8001314 ) 8001260: 693a ldr r2, [r7, #16] 8001262: 601a str r2, [r3, #0] temp = EXTI->EMR; 8001264: 4b2b ldr r3, [pc, #172] ; (8001314 ) 8001266: 685b ldr r3, [r3, #4] 8001268: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800126a: 68fb ldr r3, [r7, #12] 800126c: 43da mvns r2, r3 800126e: 693b ldr r3, [r7, #16] 8001270: 4013 ands r3, r2 8001272: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8001274: 683b ldr r3, [r7, #0] 8001276: 685a ldr r2, [r3, #4] 8001278: 2380 movs r3, #128 ; 0x80 800127a: 029b lsls r3, r3, #10 800127c: 4013 ands r3, r2 800127e: d003 beq.n 8001288 { temp |= iocurrent; 8001280: 693a ldr r2, [r7, #16] 8001282: 68fb ldr r3, [r7, #12] 8001284: 4313 orrs r3, r2 8001286: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8001288: 4b22 ldr r3, [pc, #136] ; (8001314 ) 800128a: 693a ldr r2, [r7, #16] 800128c: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 800128e: 4b21 ldr r3, [pc, #132] ; (8001314 ) 8001290: 689b ldr r3, [r3, #8] 8001292: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001294: 68fb ldr r3, [r7, #12] 8001296: 43da mvns r2, r3 8001298: 693b ldr r3, [r7, #16] 800129a: 4013 ands r3, r2 800129c: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 800129e: 683b ldr r3, [r7, #0] 80012a0: 685a ldr r2, [r3, #4] 80012a2: 2380 movs r3, #128 ; 0x80 80012a4: 035b lsls r3, r3, #13 80012a6: 4013 ands r3, r2 80012a8: d003 beq.n 80012b2 { temp |= iocurrent; 80012aa: 693a ldr r2, [r7, #16] 80012ac: 68fb ldr r3, [r7, #12] 80012ae: 4313 orrs r3, r2 80012b0: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 80012b2: 4b18 ldr r3, [pc, #96] ; (8001314 ) 80012b4: 693a ldr r2, [r7, #16] 80012b6: 609a str r2, [r3, #8] temp = EXTI->FTSR; 80012b8: 4b16 ldr r3, [pc, #88] ; (8001314 ) 80012ba: 68db ldr r3, [r3, #12] 80012bc: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80012be: 68fb ldr r3, [r7, #12] 80012c0: 43da mvns r2, r3 80012c2: 693b ldr r3, [r7, #16] 80012c4: 4013 ands r3, r2 80012c6: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 80012c8: 683b ldr r3, [r7, #0] 80012ca: 685a ldr r2, [r3, #4] 80012cc: 2380 movs r3, #128 ; 0x80 80012ce: 039b lsls r3, r3, #14 80012d0: 4013 ands r3, r2 80012d2: d003 beq.n 80012dc { temp |= iocurrent; 80012d4: 693a ldr r2, [r7, #16] 80012d6: 68fb ldr r3, [r7, #12] 80012d8: 4313 orrs r3, r2 80012da: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 80012dc: 4b0d ldr r3, [pc, #52] ; (8001314 ) 80012de: 693a ldr r2, [r7, #16] 80012e0: 60da str r2, [r3, #12] } } position++; 80012e2: 697b ldr r3, [r7, #20] 80012e4: 3301 adds r3, #1 80012e6: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 80012e8: 683b ldr r3, [r7, #0] 80012ea: 681a ldr r2, [r3, #0] 80012ec: 697b ldr r3, [r7, #20] 80012ee: 40da lsrs r2, r3 80012f0: 1e13 subs r3, r2, #0 80012f2: d000 beq.n 80012f6 80012f4: e6a8 b.n 8001048 } } 80012f6: 46c0 nop ; (mov r8, r8) 80012f8: 46c0 nop ; (mov r8, r8) 80012fa: 46bd mov sp, r7 80012fc: b006 add sp, #24 80012fe: bd80 pop {r7, pc} 8001300: 40021000 .word 0x40021000 8001304: 40010000 .word 0x40010000 8001308: 48000400 .word 0x48000400 800130c: 48000800 .word 0x48000800 8001310: 48000c00 .word 0x48000c00 8001314: 40010400 .word 0x40010400 08001318 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001318: b580 push {r7, lr} 800131a: b084 sub sp, #16 800131c: af00 add r7, sp, #0 800131e: 6078 str r0, [r7, #4] 8001320: 000a movs r2, r1 8001322: 1cbb adds r3, r7, #2 8001324: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001326: 687b ldr r3, [r7, #4] 8001328: 691b ldr r3, [r3, #16] 800132a: 1cba adds r2, r7, #2 800132c: 8812 ldrh r2, [r2, #0] 800132e: 4013 ands r3, r2 8001330: d004 beq.n 800133c { bitstatus = GPIO_PIN_SET; 8001332: 230f movs r3, #15 8001334: 18fb adds r3, r7, r3 8001336: 2201 movs r2, #1 8001338: 701a strb r2, [r3, #0] 800133a: e003 b.n 8001344 } else { bitstatus = GPIO_PIN_RESET; 800133c: 230f movs r3, #15 800133e: 18fb adds r3, r7, r3 8001340: 2200 movs r2, #0 8001342: 701a strb r2, [r3, #0] } return bitstatus; 8001344: 230f movs r3, #15 8001346: 18fb adds r3, r7, r3 8001348: 781b ldrb r3, [r3, #0] } 800134a: 0018 movs r0, r3 800134c: 46bd mov sp, r7 800134e: b004 add sp, #16 8001350: bd80 pop {r7, pc} 08001352 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001352: b580 push {r7, lr} 8001354: b082 sub sp, #8 8001356: af00 add r7, sp, #0 8001358: 6078 str r0, [r7, #4] 800135a: 0008 movs r0, r1 800135c: 0011 movs r1, r2 800135e: 1cbb adds r3, r7, #2 8001360: 1c02 adds r2, r0, #0 8001362: 801a strh r2, [r3, #0] 8001364: 1c7b adds r3, r7, #1 8001366: 1c0a adds r2, r1, #0 8001368: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800136a: 1c7b adds r3, r7, #1 800136c: 781b ldrb r3, [r3, #0] 800136e: 2b00 cmp r3, #0 8001370: d004 beq.n 800137c { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001372: 1cbb adds r3, r7, #2 8001374: 881a ldrh r2, [r3, #0] 8001376: 687b ldr r3, [r7, #4] 8001378: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 800137a: e003 b.n 8001384 GPIOx->BRR = (uint32_t)GPIO_Pin; 800137c: 1cbb adds r3, r7, #2 800137e: 881a ldrh r2, [r3, #0] 8001380: 687b ldr r3, [r7, #4] 8001382: 629a str r2, [r3, #40] ; 0x28 } 8001384: 46c0 nop ; (mov r8, r8) 8001386: 46bd mov sp, r7 8001388: b002 add sp, #8 800138a: bd80 pop {r7, pc} 0800138c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800138c: b580 push {r7, lr} 800138e: b088 sub sp, #32 8001390: af00 add r7, sp, #0 8001392: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8001394: 687b ldr r3, [r7, #4] 8001396: 2b00 cmp r3, #0 8001398: d101 bne.n 800139e { return HAL_ERROR; 800139a: 2301 movs r3, #1 800139c: e301 b.n 80019a2 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800139e: 687b ldr r3, [r7, #4] 80013a0: 681b ldr r3, [r3, #0] 80013a2: 2201 movs r2, #1 80013a4: 4013 ands r3, r2 80013a6: d100 bne.n 80013aa 80013a8: e08d b.n 80014c6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80013aa: 4bc3 ldr r3, [pc, #780] ; (80016b8 ) 80013ac: 685b ldr r3, [r3, #4] 80013ae: 220c movs r2, #12 80013b0: 4013 ands r3, r2 80013b2: 2b04 cmp r3, #4 80013b4: d00e beq.n 80013d4 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80013b6: 4bc0 ldr r3, [pc, #768] ; (80016b8 ) 80013b8: 685b ldr r3, [r3, #4] 80013ba: 220c movs r2, #12 80013bc: 4013 ands r3, r2 80013be: 2b08 cmp r3, #8 80013c0: d116 bne.n 80013f0 80013c2: 4bbd ldr r3, [pc, #756] ; (80016b8 ) 80013c4: 685a ldr r2, [r3, #4] 80013c6: 2380 movs r3, #128 ; 0x80 80013c8: 025b lsls r3, r3, #9 80013ca: 401a ands r2, r3 80013cc: 2380 movs r3, #128 ; 0x80 80013ce: 025b lsls r3, r3, #9 80013d0: 429a cmp r2, r3 80013d2: d10d bne.n 80013f0 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80013d4: 4bb8 ldr r3, [pc, #736] ; (80016b8 ) 80013d6: 681a ldr r2, [r3, #0] 80013d8: 2380 movs r3, #128 ; 0x80 80013da: 029b lsls r3, r3, #10 80013dc: 4013 ands r3, r2 80013de: d100 bne.n 80013e2 80013e0: e070 b.n 80014c4 80013e2: 687b ldr r3, [r7, #4] 80013e4: 685b ldr r3, [r3, #4] 80013e6: 2b00 cmp r3, #0 80013e8: d000 beq.n 80013ec 80013ea: e06b b.n 80014c4 { return HAL_ERROR; 80013ec: 2301 movs r3, #1 80013ee: e2d8 b.n 80019a2 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80013f0: 687b ldr r3, [r7, #4] 80013f2: 685b ldr r3, [r3, #4] 80013f4: 2b01 cmp r3, #1 80013f6: d107 bne.n 8001408 80013f8: 4baf ldr r3, [pc, #700] ; (80016b8 ) 80013fa: 681a ldr r2, [r3, #0] 80013fc: 4bae ldr r3, [pc, #696] ; (80016b8 ) 80013fe: 2180 movs r1, #128 ; 0x80 8001400: 0249 lsls r1, r1, #9 8001402: 430a orrs r2, r1 8001404: 601a str r2, [r3, #0] 8001406: e02f b.n 8001468 8001408: 687b ldr r3, [r7, #4] 800140a: 685b ldr r3, [r3, #4] 800140c: 2b00 cmp r3, #0 800140e: d10c bne.n 800142a 8001410: 4ba9 ldr r3, [pc, #676] ; (80016b8 ) 8001412: 681a ldr r2, [r3, #0] 8001414: 4ba8 ldr r3, [pc, #672] ; (80016b8 ) 8001416: 49a9 ldr r1, [pc, #676] ; (80016bc ) 8001418: 400a ands r2, r1 800141a: 601a str r2, [r3, #0] 800141c: 4ba6 ldr r3, [pc, #664] ; (80016b8 ) 800141e: 681a ldr r2, [r3, #0] 8001420: 4ba5 ldr r3, [pc, #660] ; (80016b8 ) 8001422: 49a7 ldr r1, [pc, #668] ; (80016c0 ) 8001424: 400a ands r2, r1 8001426: 601a str r2, [r3, #0] 8001428: e01e b.n 8001468 800142a: 687b ldr r3, [r7, #4] 800142c: 685b ldr r3, [r3, #4] 800142e: 2b05 cmp r3, #5 8001430: d10e bne.n 8001450 8001432: 4ba1 ldr r3, [pc, #644] ; (80016b8 ) 8001434: 681a ldr r2, [r3, #0] 8001436: 4ba0 ldr r3, [pc, #640] ; (80016b8 ) 8001438: 2180 movs r1, #128 ; 0x80 800143a: 02c9 lsls r1, r1, #11 800143c: 430a orrs r2, r1 800143e: 601a str r2, [r3, #0] 8001440: 4b9d ldr r3, [pc, #628] ; (80016b8 ) 8001442: 681a ldr r2, [r3, #0] 8001444: 4b9c ldr r3, [pc, #624] ; (80016b8 ) 8001446: 2180 movs r1, #128 ; 0x80 8001448: 0249 lsls r1, r1, #9 800144a: 430a orrs r2, r1 800144c: 601a str r2, [r3, #0] 800144e: e00b b.n 8001468 8001450: 4b99 ldr r3, [pc, #612] ; (80016b8 ) 8001452: 681a ldr r2, [r3, #0] 8001454: 4b98 ldr r3, [pc, #608] ; (80016b8 ) 8001456: 4999 ldr r1, [pc, #612] ; (80016bc ) 8001458: 400a ands r2, r1 800145a: 601a str r2, [r3, #0] 800145c: 4b96 ldr r3, [pc, #600] ; (80016b8 ) 800145e: 681a ldr r2, [r3, #0] 8001460: 4b95 ldr r3, [pc, #596] ; (80016b8 ) 8001462: 4997 ldr r1, [pc, #604] ; (80016c0 ) 8001464: 400a ands r2, r1 8001466: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001468: 687b ldr r3, [r7, #4] 800146a: 685b ldr r3, [r3, #4] 800146c: 2b00 cmp r3, #0 800146e: d014 beq.n 800149a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001470: f7ff faee bl 8000a50 8001474: 0003 movs r3, r0 8001476: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001478: e008 b.n 800148c { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 800147a: f7ff fae9 bl 8000a50 800147e: 0002 movs r2, r0 8001480: 69bb ldr r3, [r7, #24] 8001482: 1ad3 subs r3, r2, r3 8001484: 2b64 cmp r3, #100 ; 0x64 8001486: d901 bls.n 800148c { return HAL_TIMEOUT; 8001488: 2303 movs r3, #3 800148a: e28a b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800148c: 4b8a ldr r3, [pc, #552] ; (80016b8 ) 800148e: 681a ldr r2, [r3, #0] 8001490: 2380 movs r3, #128 ; 0x80 8001492: 029b lsls r3, r3, #10 8001494: 4013 ands r3, r2 8001496: d0f0 beq.n 800147a 8001498: e015 b.n 80014c6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800149a: f7ff fad9 bl 8000a50 800149e: 0003 movs r3, r0 80014a0: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80014a2: e008 b.n 80014b6 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80014a4: f7ff fad4 bl 8000a50 80014a8: 0002 movs r2, r0 80014aa: 69bb ldr r3, [r7, #24] 80014ac: 1ad3 subs r3, r2, r3 80014ae: 2b64 cmp r3, #100 ; 0x64 80014b0: d901 bls.n 80014b6 { return HAL_TIMEOUT; 80014b2: 2303 movs r3, #3 80014b4: e275 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80014b6: 4b80 ldr r3, [pc, #512] ; (80016b8 ) 80014b8: 681a ldr r2, [r3, #0] 80014ba: 2380 movs r3, #128 ; 0x80 80014bc: 029b lsls r3, r3, #10 80014be: 4013 ands r3, r2 80014c0: d1f0 bne.n 80014a4 80014c2: e000 b.n 80014c6 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80014c4: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80014c6: 687b ldr r3, [r7, #4] 80014c8: 681b ldr r3, [r3, #0] 80014ca: 2202 movs r2, #2 80014cc: 4013 ands r3, r2 80014ce: d100 bne.n 80014d2 80014d0: e069 b.n 80015a6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80014d2: 4b79 ldr r3, [pc, #484] ; (80016b8 ) 80014d4: 685b ldr r3, [r3, #4] 80014d6: 220c movs r2, #12 80014d8: 4013 ands r3, r2 80014da: d00b beq.n 80014f4 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 80014dc: 4b76 ldr r3, [pc, #472] ; (80016b8 ) 80014de: 685b ldr r3, [r3, #4] 80014e0: 220c movs r2, #12 80014e2: 4013 ands r3, r2 80014e4: 2b08 cmp r3, #8 80014e6: d11c bne.n 8001522 80014e8: 4b73 ldr r3, [pc, #460] ; (80016b8 ) 80014ea: 685a ldr r2, [r3, #4] 80014ec: 2380 movs r3, #128 ; 0x80 80014ee: 025b lsls r3, r3, #9 80014f0: 4013 ands r3, r2 80014f2: d116 bne.n 8001522 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80014f4: 4b70 ldr r3, [pc, #448] ; (80016b8 ) 80014f6: 681b ldr r3, [r3, #0] 80014f8: 2202 movs r2, #2 80014fa: 4013 ands r3, r2 80014fc: d005 beq.n 800150a 80014fe: 687b ldr r3, [r7, #4] 8001500: 68db ldr r3, [r3, #12] 8001502: 2b01 cmp r3, #1 8001504: d001 beq.n 800150a { return HAL_ERROR; 8001506: 2301 movs r3, #1 8001508: e24b b.n 80019a2 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800150a: 4b6b ldr r3, [pc, #428] ; (80016b8 ) 800150c: 681b ldr r3, [r3, #0] 800150e: 22f8 movs r2, #248 ; 0xf8 8001510: 4393 bics r3, r2 8001512: 0019 movs r1, r3 8001514: 687b ldr r3, [r7, #4] 8001516: 691b ldr r3, [r3, #16] 8001518: 00da lsls r2, r3, #3 800151a: 4b67 ldr r3, [pc, #412] ; (80016b8 ) 800151c: 430a orrs r2, r1 800151e: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001520: e041 b.n 80015a6 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001522: 687b ldr r3, [r7, #4] 8001524: 68db ldr r3, [r3, #12] 8001526: 2b00 cmp r3, #0 8001528: d024 beq.n 8001574 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800152a: 4b63 ldr r3, [pc, #396] ; (80016b8 ) 800152c: 681a ldr r2, [r3, #0] 800152e: 4b62 ldr r3, [pc, #392] ; (80016b8 ) 8001530: 2101 movs r1, #1 8001532: 430a orrs r2, r1 8001534: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001536: f7ff fa8b bl 8000a50 800153a: 0003 movs r3, r0 800153c: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800153e: e008 b.n 8001552 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001540: f7ff fa86 bl 8000a50 8001544: 0002 movs r2, r0 8001546: 69bb ldr r3, [r7, #24] 8001548: 1ad3 subs r3, r2, r3 800154a: 2b02 cmp r3, #2 800154c: d901 bls.n 8001552 { return HAL_TIMEOUT; 800154e: 2303 movs r3, #3 8001550: e227 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001552: 4b59 ldr r3, [pc, #356] ; (80016b8 ) 8001554: 681b ldr r3, [r3, #0] 8001556: 2202 movs r2, #2 8001558: 4013 ands r3, r2 800155a: d0f1 beq.n 8001540 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800155c: 4b56 ldr r3, [pc, #344] ; (80016b8 ) 800155e: 681b ldr r3, [r3, #0] 8001560: 22f8 movs r2, #248 ; 0xf8 8001562: 4393 bics r3, r2 8001564: 0019 movs r1, r3 8001566: 687b ldr r3, [r7, #4] 8001568: 691b ldr r3, [r3, #16] 800156a: 00da lsls r2, r3, #3 800156c: 4b52 ldr r3, [pc, #328] ; (80016b8 ) 800156e: 430a orrs r2, r1 8001570: 601a str r2, [r3, #0] 8001572: e018 b.n 80015a6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001574: 4b50 ldr r3, [pc, #320] ; (80016b8 ) 8001576: 681a ldr r2, [r3, #0] 8001578: 4b4f ldr r3, [pc, #316] ; (80016b8 ) 800157a: 2101 movs r1, #1 800157c: 438a bics r2, r1 800157e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001580: f7ff fa66 bl 8000a50 8001584: 0003 movs r3, r0 8001586: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001588: e008 b.n 800159c { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800158a: f7ff fa61 bl 8000a50 800158e: 0002 movs r2, r0 8001590: 69bb ldr r3, [r7, #24] 8001592: 1ad3 subs r3, r2, r3 8001594: 2b02 cmp r3, #2 8001596: d901 bls.n 800159c { return HAL_TIMEOUT; 8001598: 2303 movs r3, #3 800159a: e202 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800159c: 4b46 ldr r3, [pc, #280] ; (80016b8 ) 800159e: 681b ldr r3, [r3, #0] 80015a0: 2202 movs r2, #2 80015a2: 4013 ands r3, r2 80015a4: d1f1 bne.n 800158a } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80015a6: 687b ldr r3, [r7, #4] 80015a8: 681b ldr r3, [r3, #0] 80015aa: 2208 movs r2, #8 80015ac: 4013 ands r3, r2 80015ae: d036 beq.n 800161e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80015b0: 687b ldr r3, [r7, #4] 80015b2: 69db ldr r3, [r3, #28] 80015b4: 2b00 cmp r3, #0 80015b6: d019 beq.n 80015ec { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80015b8: 4b3f ldr r3, [pc, #252] ; (80016b8 ) 80015ba: 6a5a ldr r2, [r3, #36] ; 0x24 80015bc: 4b3e ldr r3, [pc, #248] ; (80016b8 ) 80015be: 2101 movs r1, #1 80015c0: 430a orrs r2, r1 80015c2: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 80015c4: f7ff fa44 bl 8000a50 80015c8: 0003 movs r3, r0 80015ca: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80015cc: e008 b.n 80015e0 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 80015ce: f7ff fa3f bl 8000a50 80015d2: 0002 movs r2, r0 80015d4: 69bb ldr r3, [r7, #24] 80015d6: 1ad3 subs r3, r2, r3 80015d8: 2b02 cmp r3, #2 80015da: d901 bls.n 80015e0 { return HAL_TIMEOUT; 80015dc: 2303 movs r3, #3 80015de: e1e0 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80015e0: 4b35 ldr r3, [pc, #212] ; (80016b8 ) 80015e2: 6a5b ldr r3, [r3, #36] ; 0x24 80015e4: 2202 movs r2, #2 80015e6: 4013 ands r3, r2 80015e8: d0f1 beq.n 80015ce 80015ea: e018 b.n 800161e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80015ec: 4b32 ldr r3, [pc, #200] ; (80016b8 ) 80015ee: 6a5a ldr r2, [r3, #36] ; 0x24 80015f0: 4b31 ldr r3, [pc, #196] ; (80016b8 ) 80015f2: 2101 movs r1, #1 80015f4: 438a bics r2, r1 80015f6: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 80015f8: f7ff fa2a bl 8000a50 80015fc: 0003 movs r3, r0 80015fe: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001600: e008 b.n 8001614 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001602: f7ff fa25 bl 8000a50 8001606: 0002 movs r2, r0 8001608: 69bb ldr r3, [r7, #24] 800160a: 1ad3 subs r3, r2, r3 800160c: 2b02 cmp r3, #2 800160e: d901 bls.n 8001614 { return HAL_TIMEOUT; 8001610: 2303 movs r3, #3 8001612: e1c6 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001614: 4b28 ldr r3, [pc, #160] ; (80016b8 ) 8001616: 6a5b ldr r3, [r3, #36] ; 0x24 8001618: 2202 movs r2, #2 800161a: 4013 ands r3, r2 800161c: d1f1 bne.n 8001602 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800161e: 687b ldr r3, [r7, #4] 8001620: 681b ldr r3, [r3, #0] 8001622: 2204 movs r2, #4 8001624: 4013 ands r3, r2 8001626: d100 bne.n 800162a 8001628: e0b4 b.n 8001794 { FlagStatus pwrclkchanged = RESET; 800162a: 201f movs r0, #31 800162c: 183b adds r3, r7, r0 800162e: 2200 movs r2, #0 8001630: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001632: 4b21 ldr r3, [pc, #132] ; (80016b8 ) 8001634: 69da ldr r2, [r3, #28] 8001636: 2380 movs r3, #128 ; 0x80 8001638: 055b lsls r3, r3, #21 800163a: 4013 ands r3, r2 800163c: d110 bne.n 8001660 { __HAL_RCC_PWR_CLK_ENABLE(); 800163e: 4b1e ldr r3, [pc, #120] ; (80016b8 ) 8001640: 69da ldr r2, [r3, #28] 8001642: 4b1d ldr r3, [pc, #116] ; (80016b8 ) 8001644: 2180 movs r1, #128 ; 0x80 8001646: 0549 lsls r1, r1, #21 8001648: 430a orrs r2, r1 800164a: 61da str r2, [r3, #28] 800164c: 4b1a ldr r3, [pc, #104] ; (80016b8 ) 800164e: 69da ldr r2, [r3, #28] 8001650: 2380 movs r3, #128 ; 0x80 8001652: 055b lsls r3, r3, #21 8001654: 4013 ands r3, r2 8001656: 60fb str r3, [r7, #12] 8001658: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 800165a: 183b adds r3, r7, r0 800165c: 2201 movs r2, #1 800165e: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001660: 4b18 ldr r3, [pc, #96] ; (80016c4 ) 8001662: 681a ldr r2, [r3, #0] 8001664: 2380 movs r3, #128 ; 0x80 8001666: 005b lsls r3, r3, #1 8001668: 4013 ands r3, r2 800166a: d11a bne.n 80016a2 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800166c: 4b15 ldr r3, [pc, #84] ; (80016c4 ) 800166e: 681a ldr r2, [r3, #0] 8001670: 4b14 ldr r3, [pc, #80] ; (80016c4 ) 8001672: 2180 movs r1, #128 ; 0x80 8001674: 0049 lsls r1, r1, #1 8001676: 430a orrs r2, r1 8001678: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800167a: f7ff f9e9 bl 8000a50 800167e: 0003 movs r3, r0 8001680: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001682: e008 b.n 8001696 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001684: f7ff f9e4 bl 8000a50 8001688: 0002 movs r2, r0 800168a: 69bb ldr r3, [r7, #24] 800168c: 1ad3 subs r3, r2, r3 800168e: 2b64 cmp r3, #100 ; 0x64 8001690: d901 bls.n 8001696 { return HAL_TIMEOUT; 8001692: 2303 movs r3, #3 8001694: e185 b.n 80019a2 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001696: 4b0b ldr r3, [pc, #44] ; (80016c4 ) 8001698: 681a ldr r2, [r3, #0] 800169a: 2380 movs r3, #128 ; 0x80 800169c: 005b lsls r3, r3, #1 800169e: 4013 ands r3, r2 80016a0: d0f0 beq.n 8001684 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80016a2: 687b ldr r3, [r7, #4] 80016a4: 689b ldr r3, [r3, #8] 80016a6: 2b01 cmp r3, #1 80016a8: d10e bne.n 80016c8 80016aa: 4b03 ldr r3, [pc, #12] ; (80016b8 ) 80016ac: 6a1a ldr r2, [r3, #32] 80016ae: 4b02 ldr r3, [pc, #8] ; (80016b8 ) 80016b0: 2101 movs r1, #1 80016b2: 430a orrs r2, r1 80016b4: 621a str r2, [r3, #32] 80016b6: e035 b.n 8001724 80016b8: 40021000 .word 0x40021000 80016bc: fffeffff .word 0xfffeffff 80016c0: fffbffff .word 0xfffbffff 80016c4: 40007000 .word 0x40007000 80016c8: 687b ldr r3, [r7, #4] 80016ca: 689b ldr r3, [r3, #8] 80016cc: 2b00 cmp r3, #0 80016ce: d10c bne.n 80016ea 80016d0: 4bb6 ldr r3, [pc, #728] ; (80019ac ) 80016d2: 6a1a ldr r2, [r3, #32] 80016d4: 4bb5 ldr r3, [pc, #724] ; (80019ac ) 80016d6: 2101 movs r1, #1 80016d8: 438a bics r2, r1 80016da: 621a str r2, [r3, #32] 80016dc: 4bb3 ldr r3, [pc, #716] ; (80019ac ) 80016de: 6a1a ldr r2, [r3, #32] 80016e0: 4bb2 ldr r3, [pc, #712] ; (80019ac ) 80016e2: 2104 movs r1, #4 80016e4: 438a bics r2, r1 80016e6: 621a str r2, [r3, #32] 80016e8: e01c b.n 8001724 80016ea: 687b ldr r3, [r7, #4] 80016ec: 689b ldr r3, [r3, #8] 80016ee: 2b05 cmp r3, #5 80016f0: d10c bne.n 800170c 80016f2: 4bae ldr r3, [pc, #696] ; (80019ac ) 80016f4: 6a1a ldr r2, [r3, #32] 80016f6: 4bad ldr r3, [pc, #692] ; (80019ac ) 80016f8: 2104 movs r1, #4 80016fa: 430a orrs r2, r1 80016fc: 621a str r2, [r3, #32] 80016fe: 4bab ldr r3, [pc, #684] ; (80019ac ) 8001700: 6a1a ldr r2, [r3, #32] 8001702: 4baa ldr r3, [pc, #680] ; (80019ac ) 8001704: 2101 movs r1, #1 8001706: 430a orrs r2, r1 8001708: 621a str r2, [r3, #32] 800170a: e00b b.n 8001724 800170c: 4ba7 ldr r3, [pc, #668] ; (80019ac ) 800170e: 6a1a ldr r2, [r3, #32] 8001710: 4ba6 ldr r3, [pc, #664] ; (80019ac ) 8001712: 2101 movs r1, #1 8001714: 438a bics r2, r1 8001716: 621a str r2, [r3, #32] 8001718: 4ba4 ldr r3, [pc, #656] ; (80019ac ) 800171a: 6a1a ldr r2, [r3, #32] 800171c: 4ba3 ldr r3, [pc, #652] ; (80019ac ) 800171e: 2104 movs r1, #4 8001720: 438a bics r2, r1 8001722: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001724: 687b ldr r3, [r7, #4] 8001726: 689b ldr r3, [r3, #8] 8001728: 2b00 cmp r3, #0 800172a: d014 beq.n 8001756 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800172c: f7ff f990 bl 8000a50 8001730: 0003 movs r3, r0 8001732: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001734: e009 b.n 800174a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001736: f7ff f98b bl 8000a50 800173a: 0002 movs r2, r0 800173c: 69bb ldr r3, [r7, #24] 800173e: 1ad3 subs r3, r2, r3 8001740: 4a9b ldr r2, [pc, #620] ; (80019b0 ) 8001742: 4293 cmp r3, r2 8001744: d901 bls.n 800174a { return HAL_TIMEOUT; 8001746: 2303 movs r3, #3 8001748: e12b b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800174a: 4b98 ldr r3, [pc, #608] ; (80019ac ) 800174c: 6a1b ldr r3, [r3, #32] 800174e: 2202 movs r2, #2 8001750: 4013 ands r3, r2 8001752: d0f0 beq.n 8001736 8001754: e013 b.n 800177e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001756: f7ff f97b bl 8000a50 800175a: 0003 movs r3, r0 800175c: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800175e: e009 b.n 8001774 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001760: f7ff f976 bl 8000a50 8001764: 0002 movs r2, r0 8001766: 69bb ldr r3, [r7, #24] 8001768: 1ad3 subs r3, r2, r3 800176a: 4a91 ldr r2, [pc, #580] ; (80019b0 ) 800176c: 4293 cmp r3, r2 800176e: d901 bls.n 8001774 { return HAL_TIMEOUT; 8001770: 2303 movs r3, #3 8001772: e116 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001774: 4b8d ldr r3, [pc, #564] ; (80019ac ) 8001776: 6a1b ldr r3, [r3, #32] 8001778: 2202 movs r2, #2 800177a: 4013 ands r3, r2 800177c: d1f0 bne.n 8001760 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 800177e: 231f movs r3, #31 8001780: 18fb adds r3, r7, r3 8001782: 781b ldrb r3, [r3, #0] 8001784: 2b01 cmp r3, #1 8001786: d105 bne.n 8001794 { __HAL_RCC_PWR_CLK_DISABLE(); 8001788: 4b88 ldr r3, [pc, #544] ; (80019ac ) 800178a: 69da ldr r2, [r3, #28] 800178c: 4b87 ldr r3, [pc, #540] ; (80019ac ) 800178e: 4989 ldr r1, [pc, #548] ; (80019b4 ) 8001790: 400a ands r2, r1 8001792: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8001794: 687b ldr r3, [r7, #4] 8001796: 681b ldr r3, [r3, #0] 8001798: 2210 movs r2, #16 800179a: 4013 ands r3, r2 800179c: d063 beq.n 8001866 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 800179e: 687b ldr r3, [r7, #4] 80017a0: 695b ldr r3, [r3, #20] 80017a2: 2b01 cmp r3, #1 80017a4: d12a bne.n 80017fc { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 80017a6: 4b81 ldr r3, [pc, #516] ; (80019ac ) 80017a8: 6b5a ldr r2, [r3, #52] ; 0x34 80017aa: 4b80 ldr r3, [pc, #512] ; (80019ac ) 80017ac: 2104 movs r1, #4 80017ae: 430a orrs r2, r1 80017b0: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 80017b2: 4b7e ldr r3, [pc, #504] ; (80019ac ) 80017b4: 6b5a ldr r2, [r3, #52] ; 0x34 80017b6: 4b7d ldr r3, [pc, #500] ; (80019ac ) 80017b8: 2101 movs r1, #1 80017ba: 430a orrs r2, r1 80017bc: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 80017be: f7ff f947 bl 8000a50 80017c2: 0003 movs r3, r0 80017c4: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 80017c6: e008 b.n 80017da { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 80017c8: f7ff f942 bl 8000a50 80017cc: 0002 movs r2, r0 80017ce: 69bb ldr r3, [r7, #24] 80017d0: 1ad3 subs r3, r2, r3 80017d2: 2b02 cmp r3, #2 80017d4: d901 bls.n 80017da { return HAL_TIMEOUT; 80017d6: 2303 movs r3, #3 80017d8: e0e3 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 80017da: 4b74 ldr r3, [pc, #464] ; (80019ac ) 80017dc: 6b5b ldr r3, [r3, #52] ; 0x34 80017de: 2202 movs r2, #2 80017e0: 4013 ands r3, r2 80017e2: d0f1 beq.n 80017c8 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 80017e4: 4b71 ldr r3, [pc, #452] ; (80019ac ) 80017e6: 6b5b ldr r3, [r3, #52] ; 0x34 80017e8: 22f8 movs r2, #248 ; 0xf8 80017ea: 4393 bics r3, r2 80017ec: 0019 movs r1, r3 80017ee: 687b ldr r3, [r7, #4] 80017f0: 699b ldr r3, [r3, #24] 80017f2: 00da lsls r2, r3, #3 80017f4: 4b6d ldr r3, [pc, #436] ; (80019ac ) 80017f6: 430a orrs r2, r1 80017f8: 635a str r2, [r3, #52] ; 0x34 80017fa: e034 b.n 8001866 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 80017fc: 687b ldr r3, [r7, #4] 80017fe: 695b ldr r3, [r3, #20] 8001800: 3305 adds r3, #5 8001802: d111 bne.n 8001828 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001804: 4b69 ldr r3, [pc, #420] ; (80019ac ) 8001806: 6b5a ldr r2, [r3, #52] ; 0x34 8001808: 4b68 ldr r3, [pc, #416] ; (80019ac ) 800180a: 2104 movs r1, #4 800180c: 438a bics r2, r1 800180e: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001810: 4b66 ldr r3, [pc, #408] ; (80019ac ) 8001812: 6b5b ldr r3, [r3, #52] ; 0x34 8001814: 22f8 movs r2, #248 ; 0xf8 8001816: 4393 bics r3, r2 8001818: 0019 movs r1, r3 800181a: 687b ldr r3, [r7, #4] 800181c: 699b ldr r3, [r3, #24] 800181e: 00da lsls r2, r3, #3 8001820: 4b62 ldr r3, [pc, #392] ; (80019ac ) 8001822: 430a orrs r2, r1 8001824: 635a str r2, [r3, #52] ; 0x34 8001826: e01e b.n 8001866 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001828: 4b60 ldr r3, [pc, #384] ; (80019ac ) 800182a: 6b5a ldr r2, [r3, #52] ; 0x34 800182c: 4b5f ldr r3, [pc, #380] ; (80019ac ) 800182e: 2104 movs r1, #4 8001830: 430a orrs r2, r1 8001832: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001834: 4b5d ldr r3, [pc, #372] ; (80019ac ) 8001836: 6b5a ldr r2, [r3, #52] ; 0x34 8001838: 4b5c ldr r3, [pc, #368] ; (80019ac ) 800183a: 2101 movs r1, #1 800183c: 438a bics r2, r1 800183e: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001840: f7ff f906 bl 8000a50 8001844: 0003 movs r3, r0 8001846: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001848: e008 b.n 800185c { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 800184a: f7ff f901 bl 8000a50 800184e: 0002 movs r2, r0 8001850: 69bb ldr r3, [r7, #24] 8001852: 1ad3 subs r3, r2, r3 8001854: 2b02 cmp r3, #2 8001856: d901 bls.n 800185c { return HAL_TIMEOUT; 8001858: 2303 movs r3, #3 800185a: e0a2 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 800185c: 4b53 ldr r3, [pc, #332] ; (80019ac ) 800185e: 6b5b ldr r3, [r3, #52] ; 0x34 8001860: 2202 movs r2, #2 8001862: 4013 ands r3, r2 8001864: d1f1 bne.n 800184a #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001866: 687b ldr r3, [r7, #4] 8001868: 6a1b ldr r3, [r3, #32] 800186a: 2b00 cmp r3, #0 800186c: d100 bne.n 8001870 800186e: e097 b.n 80019a0 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001870: 4b4e ldr r3, [pc, #312] ; (80019ac ) 8001872: 685b ldr r3, [r3, #4] 8001874: 220c movs r2, #12 8001876: 4013 ands r3, r2 8001878: 2b08 cmp r3, #8 800187a: d100 bne.n 800187e 800187c: e06b b.n 8001956 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800187e: 687b ldr r3, [r7, #4] 8001880: 6a1b ldr r3, [r3, #32] 8001882: 2b02 cmp r3, #2 8001884: d14c bne.n 8001920 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001886: 4b49 ldr r3, [pc, #292] ; (80019ac ) 8001888: 681a ldr r2, [r3, #0] 800188a: 4b48 ldr r3, [pc, #288] ; (80019ac ) 800188c: 494a ldr r1, [pc, #296] ; (80019b8 ) 800188e: 400a ands r2, r1 8001890: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001892: f7ff f8dd bl 8000a50 8001896: 0003 movs r3, r0 8001898: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800189a: e008 b.n 80018ae { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800189c: f7ff f8d8 bl 8000a50 80018a0: 0002 movs r2, r0 80018a2: 69bb ldr r3, [r7, #24] 80018a4: 1ad3 subs r3, r2, r3 80018a6: 2b02 cmp r3, #2 80018a8: d901 bls.n 80018ae { return HAL_TIMEOUT; 80018aa: 2303 movs r3, #3 80018ac: e079 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80018ae: 4b3f ldr r3, [pc, #252] ; (80019ac ) 80018b0: 681a ldr r2, [r3, #0] 80018b2: 2380 movs r3, #128 ; 0x80 80018b4: 049b lsls r3, r3, #18 80018b6: 4013 ands r3, r2 80018b8: d1f0 bne.n 800189c } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80018ba: 4b3c ldr r3, [pc, #240] ; (80019ac ) 80018bc: 6adb ldr r3, [r3, #44] ; 0x2c 80018be: 220f movs r2, #15 80018c0: 4393 bics r3, r2 80018c2: 0019 movs r1, r3 80018c4: 687b ldr r3, [r7, #4] 80018c6: 6ada ldr r2, [r3, #44] ; 0x2c 80018c8: 4b38 ldr r3, [pc, #224] ; (80019ac ) 80018ca: 430a orrs r2, r1 80018cc: 62da str r2, [r3, #44] ; 0x2c 80018ce: 4b37 ldr r3, [pc, #220] ; (80019ac ) 80018d0: 685b ldr r3, [r3, #4] 80018d2: 4a3a ldr r2, [pc, #232] ; (80019bc ) 80018d4: 4013 ands r3, r2 80018d6: 0019 movs r1, r3 80018d8: 687b ldr r3, [r7, #4] 80018da: 6a9a ldr r2, [r3, #40] ; 0x28 80018dc: 687b ldr r3, [r7, #4] 80018de: 6a5b ldr r3, [r3, #36] ; 0x24 80018e0: 431a orrs r2, r3 80018e2: 4b32 ldr r3, [pc, #200] ; (80019ac ) 80018e4: 430a orrs r2, r1 80018e6: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80018e8: 4b30 ldr r3, [pc, #192] ; (80019ac ) 80018ea: 681a ldr r2, [r3, #0] 80018ec: 4b2f ldr r3, [pc, #188] ; (80019ac ) 80018ee: 2180 movs r1, #128 ; 0x80 80018f0: 0449 lsls r1, r1, #17 80018f2: 430a orrs r2, r1 80018f4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80018f6: f7ff f8ab bl 8000a50 80018fa: 0003 movs r3, r0 80018fc: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80018fe: e008 b.n 8001912 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001900: f7ff f8a6 bl 8000a50 8001904: 0002 movs r2, r0 8001906: 69bb ldr r3, [r7, #24] 8001908: 1ad3 subs r3, r2, r3 800190a: 2b02 cmp r3, #2 800190c: d901 bls.n 8001912 { return HAL_TIMEOUT; 800190e: 2303 movs r3, #3 8001910: e047 b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001912: 4b26 ldr r3, [pc, #152] ; (80019ac ) 8001914: 681a ldr r2, [r3, #0] 8001916: 2380 movs r3, #128 ; 0x80 8001918: 049b lsls r3, r3, #18 800191a: 4013 ands r3, r2 800191c: d0f0 beq.n 8001900 800191e: e03f b.n 80019a0 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001920: 4b22 ldr r3, [pc, #136] ; (80019ac ) 8001922: 681a ldr r2, [r3, #0] 8001924: 4b21 ldr r3, [pc, #132] ; (80019ac ) 8001926: 4924 ldr r1, [pc, #144] ; (80019b8 ) 8001928: 400a ands r2, r1 800192a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800192c: f7ff f890 bl 8000a50 8001930: 0003 movs r3, r0 8001932: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001934: e008 b.n 8001948 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001936: f7ff f88b bl 8000a50 800193a: 0002 movs r2, r0 800193c: 69bb ldr r3, [r7, #24] 800193e: 1ad3 subs r3, r2, r3 8001940: 2b02 cmp r3, #2 8001942: d901 bls.n 8001948 { return HAL_TIMEOUT; 8001944: 2303 movs r3, #3 8001946: e02c b.n 80019a2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001948: 4b18 ldr r3, [pc, #96] ; (80019ac ) 800194a: 681a ldr r2, [r3, #0] 800194c: 2380 movs r3, #128 ; 0x80 800194e: 049b lsls r3, r3, #18 8001950: 4013 ands r3, r2 8001952: d1f0 bne.n 8001936 8001954: e024 b.n 80019a0 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001956: 687b ldr r3, [r7, #4] 8001958: 6a1b ldr r3, [r3, #32] 800195a: 2b01 cmp r3, #1 800195c: d101 bne.n 8001962 { return HAL_ERROR; 800195e: 2301 movs r3, #1 8001960: e01f b.n 80019a2 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001962: 4b12 ldr r3, [pc, #72] ; (80019ac ) 8001964: 685b ldr r3, [r3, #4] 8001966: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001968: 4b10 ldr r3, [pc, #64] ; (80019ac ) 800196a: 6adb ldr r3, [r3, #44] ; 0x2c 800196c: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800196e: 697a ldr r2, [r7, #20] 8001970: 2380 movs r3, #128 ; 0x80 8001972: 025b lsls r3, r3, #9 8001974: 401a ands r2, r3 8001976: 687b ldr r3, [r7, #4] 8001978: 6a5b ldr r3, [r3, #36] ; 0x24 800197a: 429a cmp r2, r3 800197c: d10e bne.n 800199c (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 800197e: 693b ldr r3, [r7, #16] 8001980: 220f movs r2, #15 8001982: 401a ands r2, r3 8001984: 687b ldr r3, [r7, #4] 8001986: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001988: 429a cmp r2, r3 800198a: d107 bne.n 800199c (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 800198c: 697a ldr r2, [r7, #20] 800198e: 23f0 movs r3, #240 ; 0xf0 8001990: 039b lsls r3, r3, #14 8001992: 401a ands r2, r3 8001994: 687b ldr r3, [r7, #4] 8001996: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001998: 429a cmp r2, r3 800199a: d001 beq.n 80019a0 { return HAL_ERROR; 800199c: 2301 movs r3, #1 800199e: e000 b.n 80019a2 } } } } return HAL_OK; 80019a0: 2300 movs r3, #0 } 80019a2: 0018 movs r0, r3 80019a4: 46bd mov sp, r7 80019a6: b008 add sp, #32 80019a8: bd80 pop {r7, pc} 80019aa: 46c0 nop ; (mov r8, r8) 80019ac: 40021000 .word 0x40021000 80019b0: 00001388 .word 0x00001388 80019b4: efffffff .word 0xefffffff 80019b8: feffffff .word 0xfeffffff 80019bc: ffc2ffff .word 0xffc2ffff 080019c0 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80019c0: b580 push {r7, lr} 80019c2: b084 sub sp, #16 80019c4: af00 add r7, sp, #0 80019c6: 6078 str r0, [r7, #4] 80019c8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 80019ca: 687b ldr r3, [r7, #4] 80019cc: 2b00 cmp r3, #0 80019ce: d101 bne.n 80019d4 { return HAL_ERROR; 80019d0: 2301 movs r3, #1 80019d2: e0b3 b.n 8001b3c /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 80019d4: 4b5b ldr r3, [pc, #364] ; (8001b44 ) 80019d6: 681b ldr r3, [r3, #0] 80019d8: 2201 movs r2, #1 80019da: 4013 ands r3, r2 80019dc: 683a ldr r2, [r7, #0] 80019de: 429a cmp r2, r3 80019e0: d911 bls.n 8001a06 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80019e2: 4b58 ldr r3, [pc, #352] ; (8001b44 ) 80019e4: 681b ldr r3, [r3, #0] 80019e6: 2201 movs r2, #1 80019e8: 4393 bics r3, r2 80019ea: 0019 movs r1, r3 80019ec: 4b55 ldr r3, [pc, #340] ; (8001b44 ) 80019ee: 683a ldr r2, [r7, #0] 80019f0: 430a orrs r2, r1 80019f2: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 80019f4: 4b53 ldr r3, [pc, #332] ; (8001b44 ) 80019f6: 681b ldr r3, [r3, #0] 80019f8: 2201 movs r2, #1 80019fa: 4013 ands r3, r2 80019fc: 683a ldr r2, [r7, #0] 80019fe: 429a cmp r2, r3 8001a00: d001 beq.n 8001a06 { return HAL_ERROR; 8001a02: 2301 movs r3, #1 8001a04: e09a b.n 8001b3c } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001a06: 687b ldr r3, [r7, #4] 8001a08: 681b ldr r3, [r3, #0] 8001a0a: 2202 movs r2, #2 8001a0c: 4013 ands r3, r2 8001a0e: d015 beq.n 8001a3c { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001a10: 687b ldr r3, [r7, #4] 8001a12: 681b ldr r3, [r3, #0] 8001a14: 2204 movs r2, #4 8001a16: 4013 ands r3, r2 8001a18: d006 beq.n 8001a28 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001a1a: 4b4b ldr r3, [pc, #300] ; (8001b48 ) 8001a1c: 685a ldr r2, [r3, #4] 8001a1e: 4b4a ldr r3, [pc, #296] ; (8001b48 ) 8001a20: 21e0 movs r1, #224 ; 0xe0 8001a22: 00c9 lsls r1, r1, #3 8001a24: 430a orrs r2, r1 8001a26: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001a28: 4b47 ldr r3, [pc, #284] ; (8001b48 ) 8001a2a: 685b ldr r3, [r3, #4] 8001a2c: 22f0 movs r2, #240 ; 0xf0 8001a2e: 4393 bics r3, r2 8001a30: 0019 movs r1, r3 8001a32: 687b ldr r3, [r7, #4] 8001a34: 689a ldr r2, [r3, #8] 8001a36: 4b44 ldr r3, [pc, #272] ; (8001b48 ) 8001a38: 430a orrs r2, r1 8001a3a: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001a3c: 687b ldr r3, [r7, #4] 8001a3e: 681b ldr r3, [r3, #0] 8001a40: 2201 movs r2, #1 8001a42: 4013 ands r3, r2 8001a44: d040 beq.n 8001ac8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8001a46: 687b ldr r3, [r7, #4] 8001a48: 685b ldr r3, [r3, #4] 8001a4a: 2b01 cmp r3, #1 8001a4c: d107 bne.n 8001a5e { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001a4e: 4b3e ldr r3, [pc, #248] ; (8001b48 ) 8001a50: 681a ldr r2, [r3, #0] 8001a52: 2380 movs r3, #128 ; 0x80 8001a54: 029b lsls r3, r3, #10 8001a56: 4013 ands r3, r2 8001a58: d114 bne.n 8001a84 { return HAL_ERROR; 8001a5a: 2301 movs r3, #1 8001a5c: e06e b.n 8001b3c } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001a5e: 687b ldr r3, [r7, #4] 8001a60: 685b ldr r3, [r3, #4] 8001a62: 2b02 cmp r3, #2 8001a64: d107 bne.n 8001a76 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001a66: 4b38 ldr r3, [pc, #224] ; (8001b48 ) 8001a68: 681a ldr r2, [r3, #0] 8001a6a: 2380 movs r3, #128 ; 0x80 8001a6c: 049b lsls r3, r3, #18 8001a6e: 4013 ands r3, r2 8001a70: d108 bne.n 8001a84 { return HAL_ERROR; 8001a72: 2301 movs r3, #1 8001a74: e062 b.n 8001b3c #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001a76: 4b34 ldr r3, [pc, #208] ; (8001b48 ) 8001a78: 681b ldr r3, [r3, #0] 8001a7a: 2202 movs r2, #2 8001a7c: 4013 ands r3, r2 8001a7e: d101 bne.n 8001a84 { return HAL_ERROR; 8001a80: 2301 movs r3, #1 8001a82: e05b b.n 8001b3c } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8001a84: 4b30 ldr r3, [pc, #192] ; (8001b48 ) 8001a86: 685b ldr r3, [r3, #4] 8001a88: 2203 movs r2, #3 8001a8a: 4393 bics r3, r2 8001a8c: 0019 movs r1, r3 8001a8e: 687b ldr r3, [r7, #4] 8001a90: 685a ldr r2, [r3, #4] 8001a92: 4b2d ldr r3, [pc, #180] ; (8001b48 ) 8001a94: 430a orrs r2, r1 8001a96: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a98: f7fe ffda bl 8000a50 8001a9c: 0003 movs r3, r0 8001a9e: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001aa0: e009 b.n 8001ab6 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001aa2: f7fe ffd5 bl 8000a50 8001aa6: 0002 movs r2, r0 8001aa8: 68fb ldr r3, [r7, #12] 8001aaa: 1ad3 subs r3, r2, r3 8001aac: 4a27 ldr r2, [pc, #156] ; (8001b4c ) 8001aae: 4293 cmp r3, r2 8001ab0: d901 bls.n 8001ab6 { return HAL_TIMEOUT; 8001ab2: 2303 movs r3, #3 8001ab4: e042 b.n 8001b3c while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001ab6: 4b24 ldr r3, [pc, #144] ; (8001b48 ) 8001ab8: 685b ldr r3, [r3, #4] 8001aba: 220c movs r2, #12 8001abc: 401a ands r2, r3 8001abe: 687b ldr r3, [r7, #4] 8001ac0: 685b ldr r3, [r3, #4] 8001ac2: 009b lsls r3, r3, #2 8001ac4: 429a cmp r2, r3 8001ac6: d1ec bne.n 8001aa2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8001ac8: 4b1e ldr r3, [pc, #120] ; (8001b44 ) 8001aca: 681b ldr r3, [r3, #0] 8001acc: 2201 movs r2, #1 8001ace: 4013 ands r3, r2 8001ad0: 683a ldr r2, [r7, #0] 8001ad2: 429a cmp r2, r3 8001ad4: d211 bcs.n 8001afa { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001ad6: 4b1b ldr r3, [pc, #108] ; (8001b44 ) 8001ad8: 681b ldr r3, [r3, #0] 8001ada: 2201 movs r2, #1 8001adc: 4393 bics r3, r2 8001ade: 0019 movs r1, r3 8001ae0: 4b18 ldr r3, [pc, #96] ; (8001b44 ) 8001ae2: 683a ldr r2, [r7, #0] 8001ae4: 430a orrs r2, r1 8001ae6: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001ae8: 4b16 ldr r3, [pc, #88] ; (8001b44 ) 8001aea: 681b ldr r3, [r3, #0] 8001aec: 2201 movs r2, #1 8001aee: 4013 ands r3, r2 8001af0: 683a ldr r2, [r7, #0] 8001af2: 429a cmp r2, r3 8001af4: d001 beq.n 8001afa { return HAL_ERROR; 8001af6: 2301 movs r3, #1 8001af8: e020 b.n 8001b3c } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001afa: 687b ldr r3, [r7, #4] 8001afc: 681b ldr r3, [r3, #0] 8001afe: 2204 movs r2, #4 8001b00: 4013 ands r3, r2 8001b02: d009 beq.n 8001b18 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8001b04: 4b10 ldr r3, [pc, #64] ; (8001b48 ) 8001b06: 685b ldr r3, [r3, #4] 8001b08: 4a11 ldr r2, [pc, #68] ; (8001b50 ) 8001b0a: 4013 ands r3, r2 8001b0c: 0019 movs r1, r3 8001b0e: 687b ldr r3, [r7, #4] 8001b10: 68da ldr r2, [r3, #12] 8001b12: 4b0d ldr r3, [pc, #52] ; (8001b48 ) 8001b14: 430a orrs r2, r1 8001b16: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8001b18: f000 f820 bl 8001b5c 8001b1c: 0001 movs r1, r0 8001b1e: 4b0a ldr r3, [pc, #40] ; (8001b48 ) 8001b20: 685b ldr r3, [r3, #4] 8001b22: 091b lsrs r3, r3, #4 8001b24: 220f movs r2, #15 8001b26: 4013 ands r3, r2 8001b28: 4a0a ldr r2, [pc, #40] ; (8001b54 ) 8001b2a: 5cd3 ldrb r3, [r2, r3] 8001b2c: 000a movs r2, r1 8001b2e: 40da lsrs r2, r3 8001b30: 4b09 ldr r3, [pc, #36] ; (8001b58 ) 8001b32: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8001b34: 2003 movs r0, #3 8001b36: f7fe ff45 bl 80009c4 return HAL_OK; 8001b3a: 2300 movs r3, #0 } 8001b3c: 0018 movs r0, r3 8001b3e: 46bd mov sp, r7 8001b40: b004 add sp, #16 8001b42: bd80 pop {r7, pc} 8001b44: 40022000 .word 0x40022000 8001b48: 40021000 .word 0x40021000 8001b4c: 00001388 .word 0x00001388 8001b50: fffff8ff .word 0xfffff8ff 8001b54: 080033b8 .word 0x080033b8 8001b58: 20000000 .word 0x20000000 08001b5c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8001b5c: b590 push {r4, r7, lr} 8001b5e: b08f sub sp, #60 ; 0x3c 8001b60: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 8001b62: 2314 movs r3, #20 8001b64: 18fb adds r3, r7, r3 8001b66: 4a2b ldr r2, [pc, #172] ; (8001c14 ) 8001b68: ca13 ldmia r2!, {r0, r1, r4} 8001b6a: c313 stmia r3!, {r0, r1, r4} 8001b6c: 6812 ldr r2, [r2, #0] 8001b6e: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8001b70: 1d3b adds r3, r7, #4 8001b72: 4a29 ldr r2, [pc, #164] ; (8001c18 ) 8001b74: ca13 ldmia r2!, {r0, r1, r4} 8001b76: c313 stmia r3!, {r0, r1, r4} 8001b78: 6812 ldr r2, [r2, #0] 8001b7a: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8001b7c: 2300 movs r3, #0 8001b7e: 62fb str r3, [r7, #44] ; 0x2c 8001b80: 2300 movs r3, #0 8001b82: 62bb str r3, [r7, #40] ; 0x28 8001b84: 2300 movs r3, #0 8001b86: 637b str r3, [r7, #52] ; 0x34 8001b88: 2300 movs r3, #0 8001b8a: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8001b8c: 2300 movs r3, #0 8001b8e: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 8001b90: 4b22 ldr r3, [pc, #136] ; (8001c1c ) 8001b92: 685b ldr r3, [r3, #4] 8001b94: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8001b96: 6afb ldr r3, [r7, #44] ; 0x2c 8001b98: 220c movs r2, #12 8001b9a: 4013 ands r3, r2 8001b9c: 2b04 cmp r3, #4 8001b9e: d002 beq.n 8001ba6 8001ba0: 2b08 cmp r3, #8 8001ba2: d003 beq.n 8001bac 8001ba4: e02d b.n 8001c02 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8001ba6: 4b1e ldr r3, [pc, #120] ; (8001c20 ) 8001ba8: 633b str r3, [r7, #48] ; 0x30 break; 8001baa: e02d b.n 8001c08 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 8001bac: 6afb ldr r3, [r7, #44] ; 0x2c 8001bae: 0c9b lsrs r3, r3, #18 8001bb0: 220f movs r2, #15 8001bb2: 4013 ands r3, r2 8001bb4: 2214 movs r2, #20 8001bb6: 18ba adds r2, r7, r2 8001bb8: 5cd3 ldrb r3, [r2, r3] 8001bba: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 8001bbc: 4b17 ldr r3, [pc, #92] ; (8001c1c ) 8001bbe: 6adb ldr r3, [r3, #44] ; 0x2c 8001bc0: 220f movs r2, #15 8001bc2: 4013 ands r3, r2 8001bc4: 1d3a adds r2, r7, #4 8001bc6: 5cd3 ldrb r3, [r2, r3] 8001bc8: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 8001bca: 6afa ldr r2, [r7, #44] ; 0x2c 8001bcc: 2380 movs r3, #128 ; 0x80 8001bce: 025b lsls r3, r3, #9 8001bd0: 4013 ands r3, r2 8001bd2: d009 beq.n 8001be8 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8001bd4: 6ab9 ldr r1, [r7, #40] ; 0x28 8001bd6: 4812 ldr r0, [pc, #72] ; (8001c20 ) 8001bd8: f7fe faa0 bl 800011c <__udivsi3> 8001bdc: 0003 movs r3, r0 8001bde: 001a movs r2, r3 8001be0: 6a7b ldr r3, [r7, #36] ; 0x24 8001be2: 4353 muls r3, r2 8001be4: 637b str r3, [r7, #52] ; 0x34 8001be6: e009 b.n 8001bfc #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 8001be8: 6a79 ldr r1, [r7, #36] ; 0x24 8001bea: 000a movs r2, r1 8001bec: 0152 lsls r2, r2, #5 8001bee: 1a52 subs r2, r2, r1 8001bf0: 0193 lsls r3, r2, #6 8001bf2: 1a9b subs r3, r3, r2 8001bf4: 00db lsls r3, r3, #3 8001bf6: 185b adds r3, r3, r1 8001bf8: 021b lsls r3, r3, #8 8001bfa: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 8001bfc: 6b7b ldr r3, [r7, #52] ; 0x34 8001bfe: 633b str r3, [r7, #48] ; 0x30 break; 8001c00: e002 b.n 8001c08 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8001c02: 4b07 ldr r3, [pc, #28] ; (8001c20 ) 8001c04: 633b str r3, [r7, #48] ; 0x30 break; 8001c06: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8001c08: 6b3b ldr r3, [r7, #48] ; 0x30 } 8001c0a: 0018 movs r0, r3 8001c0c: 46bd mov sp, r7 8001c0e: b00f add sp, #60 ; 0x3c 8001c10: bd90 pop {r4, r7, pc} 8001c12: 46c0 nop ; (mov r8, r8) 8001c14: 08003398 .word 0x08003398 8001c18: 080033a8 .word 0x080033a8 8001c1c: 40021000 .word 0x40021000 8001c20: 007a1200 .word 0x007a1200 08001c24 : */ #include "button.h" void GEI_BUTTON_CODE(struct button *bt,uint8_t in) { 8001c24: b580 push {r7, lr} 8001c26: b082 sub sp, #8 8001c28: af00 add r7, sp, #0 8001c2a: 6078 str r0, [r7, #4] 8001c2c: 000a movs r2, r1 8001c2e: 1cfb adds r3, r7, #3 8001c30: 701a strb r2, [r3, #0] #define t 250 bt->code=0; 8001c32: 687b ldr r3, [r7, #4] 8001c34: 2200 movs r2, #0 8001c36: 801a strh r2, [r3, #0] if(in==1) 8001c38: 1cfb adds r3, r7, #3 8001c3a: 781b ldrb r3, [r3, #0] 8001c3c: 2b01 cmp r3, #1 8001c3e: d137 bne.n 8001cb0 { if(bt->lock==0) 8001c40: 687b ldr r3, [r7, #4] 8001c42: 789b ldrb r3, [r3, #2] 8001c44: 2b00 cmp r3, #0 8001c46: d121 bne.n 8001c8c { if(HAL_GetTick()time+t) 8001c48: f7fe ff02 bl 8000a50 8001c4c: 0002 movs r2, r0 8001c4e: 687b ldr r3, [r7, #4] 8001c50: 685b ldr r3, [r3, #4] 8001c52: 33fa adds r3, #250 ; 0xfa 8001c54: 429a cmp r2, r3 8001c56: d20e bcs.n 8001c76 { bt->times++; 8001c58: 687b ldr r3, [r7, #4] 8001c5a: 891b ldrh r3, [r3, #8] 8001c5c: 3301 adds r3, #1 8001c5e: b29a uxth r2, r3 8001c60: 687b ldr r3, [r7, #4] 8001c62: 811a strh r2, [r3, #8] bt->time=HAL_GetTick(); 8001c64: f7fe fef4 bl 8000a50 8001c68: 0002 movs r2, r0 8001c6a: 687b ldr r3, [r7, #4] 8001c6c: 605a str r2, [r3, #4] bt->lock=1; 8001c6e: 687b ldr r3, [r7, #4] 8001c70: 2201 movs r2, #1 8001c72: 709a strb r2, [r3, #2] 8001c74: e00a b.n 8001c8c }else { bt->times=1; 8001c76: 687b ldr r3, [r7, #4] 8001c78: 2201 movs r2, #1 8001c7a: 811a strh r2, [r3, #8] bt->time=HAL_GetTick(); 8001c7c: f7fe fee8 bl 8000a50 8001c80: 0002 movs r2, r0 8001c82: 687b ldr r3, [r7, #4] 8001c84: 605a str r2, [r3, #4] bt->lock=1; 8001c86: 687b ldr r3, [r7, #4] 8001c88: 2201 movs r2, #1 8001c8a: 709a strb r2, [r3, #2] } } if(bt->lock==1) 8001c8c: 687b ldr r3, [r7, #4] 8001c8e: 789b ldrb r3, [r3, #2] 8001c90: 2b01 cmp r3, #1 8001c92: d10d bne.n 8001cb0 { if(HAL_GetTick()>bt->time+t) 8001c94: f7fe fedc bl 8000a50 8001c98: 0002 movs r2, r0 8001c9a: 687b ldr r3, [r7, #4] 8001c9c: 685b ldr r3, [r3, #4] 8001c9e: 33fa adds r3, #250 ; 0xfa 8001ca0: 429a cmp r2, r3 8001ca2: d905 bls.n 8001cb0 { bt->code=255; 8001ca4: 687b ldr r3, [r7, #4] 8001ca6: 22ff movs r2, #255 ; 0xff 8001ca8: 801a strh r2, [r3, #0] bt->times=255; 8001caa: 687b ldr r3, [r7, #4] 8001cac: 22ff movs r2, #255 ; 0xff 8001cae: 811a strh r2, [r3, #8] } } } if(in==0) 8001cb0: 1cfb adds r3, r7, #3 8001cb2: 781b ldrb r3, [r3, #0] 8001cb4: 2b00 cmp r3, #0 8001cb6: d10e bne.n 8001cd6 { if(bt->lock==1) 8001cb8: 687b ldr r3, [r7, #4] 8001cba: 789b ldrb r3, [r3, #2] 8001cbc: 2b01 cmp r3, #1 8001cbe: d10a bne.n 8001cd6 { if(bt->code==255) 8001cc0: 687b ldr r3, [r7, #4] 8001cc2: 881b ldrh r3, [r3, #0] 8001cc4: 2bff cmp r3, #255 ; 0xff 8001cc6: d003 beq.n 8001cd0 { }else { bt->code=bt->times; 8001cc8: 687b ldr r3, [r7, #4] 8001cca: 891a ldrh r2, [r3, #8] 8001ccc: 687b ldr r3, [r7, #4] 8001cce: 801a strh r2, [r3, #0] } bt->lock=0; 8001cd0: 687b ldr r3, [r7, #4] 8001cd2: 2200 movs r2, #0 8001cd4: 709a strb r2, [r3, #2] } } } 8001cd6: 46c0 nop ; (mov r8, r8) 8001cd8: 46bd mov sp, r7 8001cda: b002 add sp, #8 8001cdc: bd80 pop {r7, pc} 08001cde : char led_n:1; char led_err:1; }dis_buff; void Send_to_595(char h,char l) { 8001cde: b580 push {r7, lr} 8001ce0: b084 sub sp, #16 8001ce2: af00 add r7, sp, #0 8001ce4: 0002 movs r2, r0 8001ce6: 1dfb adds r3, r7, #7 8001ce8: 701a strb r2, [r3, #0] 8001cea: 1dbb adds r3, r7, #6 8001cec: 1c0a adds r2, r1, #0 8001cee: 701a strb r2, [r3, #0] for(int a=0;a<8;a++) 8001cf0: 2300 movs r3, #0 8001cf2: 60fb str r3, [r7, #12] 8001cf4: e027 b.n 8001d46 { if((h< { HC595_DCK(1); 8001d06: 2390 movs r3, #144 ; 0x90 8001d08: 05db lsls r3, r3, #23 8001d0a: 2201 movs r2, #1 8001d0c: 2108 movs r1, #8 8001d0e: 0018 movs r0, r3 8001d10: f7ff fb1f bl 8001352 8001d14: e006 b.n 8001d24 }else { HC595_DCK(0); 8001d16: 2390 movs r3, #144 ; 0x90 8001d18: 05db lsls r3, r3, #23 8001d1a: 2200 movs r2, #0 8001d1c: 2108 movs r1, #8 8001d1e: 0018 movs r0, r3 8001d20: f7ff fb17 bl 8001352 } HC595_SCK(1); 8001d24: 2390 movs r3, #144 ; 0x90 8001d26: 05db lsls r3, r3, #23 8001d28: 2201 movs r2, #1 8001d2a: 2120 movs r1, #32 8001d2c: 0018 movs r0, r3 8001d2e: f7ff fb10 bl 8001352 HC595_SCK(0); 8001d32: 2390 movs r3, #144 ; 0x90 8001d34: 05db lsls r3, r3, #23 8001d36: 2200 movs r2, #0 8001d38: 2120 movs r1, #32 8001d3a: 0018 movs r0, r3 8001d3c: f7ff fb09 bl 8001352 for(int a=0;a<8;a++) 8001d40: 68fb ldr r3, [r7, #12] 8001d42: 3301 adds r3, #1 8001d44: 60fb str r3, [r7, #12] 8001d46: 68fb ldr r3, [r7, #12] 8001d48: 2b07 cmp r3, #7 8001d4a: ddd4 ble.n 8001cf6 } for(int a=0;a<8;a++) 8001d4c: 2300 movs r3, #0 8001d4e: 60bb str r3, [r7, #8] 8001d50: e027 b.n 8001da2 { if((l< { HC595_DCK(1); 8001d62: 2390 movs r3, #144 ; 0x90 8001d64: 05db lsls r3, r3, #23 8001d66: 2201 movs r2, #1 8001d68: 2108 movs r1, #8 8001d6a: 0018 movs r0, r3 8001d6c: f7ff faf1 bl 8001352 8001d70: e006 b.n 8001d80 }else { HC595_DCK(0); 8001d72: 2390 movs r3, #144 ; 0x90 8001d74: 05db lsls r3, r3, #23 8001d76: 2200 movs r2, #0 8001d78: 2108 movs r1, #8 8001d7a: 0018 movs r0, r3 8001d7c: f7ff fae9 bl 8001352 } HC595_SCK(1); 8001d80: 2390 movs r3, #144 ; 0x90 8001d82: 05db lsls r3, r3, #23 8001d84: 2201 movs r2, #1 8001d86: 2120 movs r1, #32 8001d88: 0018 movs r0, r3 8001d8a: f7ff fae2 bl 8001352 HC595_SCK(0); 8001d8e: 2390 movs r3, #144 ; 0x90 8001d90: 05db lsls r3, r3, #23 8001d92: 2200 movs r2, #0 8001d94: 2120 movs r1, #32 8001d96: 0018 movs r0, r3 8001d98: f7ff fadb bl 8001352 for(int a=0;a<8;a++) 8001d9c: 68bb ldr r3, [r7, #8] 8001d9e: 3301 adds r3, #1 8001da0: 60bb str r3, [r7, #8] 8001da2: 68bb ldr r3, [r7, #8] 8001da4: 2b07 cmp r3, #7 8001da6: ddd4 ble.n 8001d52 } HC595_RCK(1); 8001da8: 2390 movs r3, #144 ; 0x90 8001daa: 05db lsls r3, r3, #23 8001dac: 2201 movs r2, #1 8001dae: 2110 movs r1, #16 8001db0: 0018 movs r0, r3 8001db2: f7ff face bl 8001352 HC595_RCK(0); 8001db6: 2390 movs r3, #144 ; 0x90 8001db8: 05db lsls r3, r3, #23 8001dba: 2200 movs r2, #0 8001dbc: 2110 movs r1, #16 8001dbe: 0018 movs r0, r3 8001dc0: f7ff fac7 bl 8001352 } 8001dc4: 46c0 nop ; (mov r8, r8) 8001dc6: 46bd mov sp, r7 8001dc8: b004 add sp, #16 8001dca: bd80 pop {r7, pc} 08001dcc : void display() { 8001dcc: b580 push {r7, lr} 8001dce: b082 sub sp, #8 8001dd0: af00 add r7, sp, #0 char h_buff=0,l_buff=0; 8001dd2: 1dfb adds r3, r7, #7 8001dd4: 2200 movs r2, #0 8001dd6: 701a strb r2, [r3, #0] 8001dd8: 1dbb adds r3, r7, #6 8001dda: 2200 movs r2, #0 8001ddc: 701a strb r2, [r3, #0] Send_to_595(h_buff,l_buff); 8001dde: 1dbb adds r3, r7, #6 8001de0: 781a ldrb r2, [r3, #0] 8001de2: 1dfb adds r3, r7, #7 8001de4: 781b ldrb r3, [r3, #0] 8001de6: 0011 movs r1, r2 8001de8: 0018 movs r0, r3 8001dea: f7ff ff78 bl 8001cde h_buff=0,l_buff=0; 8001dee: 1dfb adds r3, r7, #7 8001df0: 2200 movs r2, #0 8001df2: 701a strb r2, [r3, #0] 8001df4: 1dbb adds r3, r7, #6 8001df6: 2200 movs r2, #0 8001df8: 701a strb r2, [r3, #0] h_buff=~0x01; 8001dfa: 1dfb adds r3, r7, #7 8001dfc: 22fe movs r2, #254 ; 0xfe 8001dfe: 701a strb r2, [r3, #0] l_buff=d_num_data[0][dis_buff.d_num[0]]; 8001e00: 4b63 ldr r3, [pc, #396] ; (8001f90 ) 8001e02: 781b ldrb r3, [r3, #0] 8001e04: 0019 movs r1, r3 8001e06: 1dbb adds r3, r7, #6 8001e08: 4a62 ldr r2, [pc, #392] ; (8001f94 ) 8001e0a: 5c52 ldrb r2, [r2, r1] 8001e0c: 701a strb r2, [r3, #0] if(dis_buff.dot1==1) 8001e0e: 4b60 ldr r3, [pc, #384] ; (8001f90 ) 8001e10: 791b ldrb r3, [r3, #4] 8001e12: 2201 movs r2, #1 8001e14: 4013 ands r3, r2 8001e16: b2db uxtb r3, r3 8001e18: 2b00 cmp r3, #0 8001e1a: d006 beq.n 8001e2a { l_buff|=0x80; 8001e1c: 1dbb adds r3, r7, #6 8001e1e: 1dba adds r2, r7, #6 8001e20: 7812 ldrb r2, [r2, #0] 8001e22: 2180 movs r1, #128 ; 0x80 8001e24: 4249 negs r1, r1 8001e26: 430a orrs r2, r1 8001e28: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001e2a: 1dbb adds r3, r7, #6 8001e2c: 781a ldrb r2, [r3, #0] 8001e2e: 1dfb adds r3, r7, #7 8001e30: 781b ldrb r3, [r3, #0] 8001e32: 0011 movs r1, r2 8001e34: 0018 movs r0, r3 8001e36: f7ff ff52 bl 8001cde h_buff=0,l_buff=0; 8001e3a: 1dfb adds r3, r7, #7 8001e3c: 2200 movs r2, #0 8001e3e: 701a strb r2, [r3, #0] 8001e40: 1dbb adds r3, r7, #6 8001e42: 2200 movs r2, #0 8001e44: 701a strb r2, [r3, #0] h_buff=~0x80; 8001e46: 1dfb adds r3, r7, #7 8001e48: 227f movs r2, #127 ; 0x7f 8001e4a: 701a strb r2, [r3, #0] l_buff=d_num_data[1][dis_buff.d_num[1]]; 8001e4c: 4b50 ldr r3, [pc, #320] ; (8001f90 ) 8001e4e: 785b ldrb r3, [r3, #1] 8001e50: 0019 movs r1, r3 8001e52: 1dbb adds r3, r7, #6 8001e54: 4a4f ldr r2, [pc, #316] ; (8001f94 ) 8001e56: 1852 adds r2, r2, r1 8001e58: 7a92 ldrb r2, [r2, #10] 8001e5a: 701a strb r2, [r3, #0] if(dis_buff.dot2==1) 8001e5c: 4b4c ldr r3, [pc, #304] ; (8001f90 ) 8001e5e: 791b ldrb r3, [r3, #4] 8001e60: 2202 movs r2, #2 8001e62: 4013 ands r3, r2 8001e64: b2db uxtb r3, r3 8001e66: 2b00 cmp r3, #0 8001e68: d005 beq.n 8001e76 { l_buff|=0x10; 8001e6a: 1dbb adds r3, r7, #6 8001e6c: 1dba adds r2, r7, #6 8001e6e: 7812 ldrb r2, [r2, #0] 8001e70: 2110 movs r1, #16 8001e72: 430a orrs r2, r1 8001e74: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001e76: 1dbb adds r3, r7, #6 8001e78: 781a ldrb r2, [r3, #0] 8001e7a: 1dfb adds r3, r7, #7 8001e7c: 781b ldrb r3, [r3, #0] 8001e7e: 0011 movs r1, r2 8001e80: 0018 movs r0, r3 8001e82: f7ff ff2c bl 8001cde h_buff=0,l_buff=0; 8001e86: 1dfb adds r3, r7, #7 8001e88: 2200 movs r2, #0 8001e8a: 701a strb r2, [r3, #0] 8001e8c: 1dbb adds r3, r7, #6 8001e8e: 2200 movs r2, #0 8001e90: 701a strb r2, [r3, #0] h_buff=~0x40; 8001e92: 1dfb adds r3, r7, #7 8001e94: 22bf movs r2, #191 ; 0xbf 8001e96: 701a strb r2, [r3, #0] l_buff=d_num_data[0][dis_buff.d_num[2]]; 8001e98: 4b3d ldr r3, [pc, #244] ; (8001f90 ) 8001e9a: 789b ldrb r3, [r3, #2] 8001e9c: 0019 movs r1, r3 8001e9e: 1dbb adds r3, r7, #6 8001ea0: 4a3c ldr r2, [pc, #240] ; (8001f94 ) 8001ea2: 5c52 ldrb r2, [r2, r1] 8001ea4: 701a strb r2, [r3, #0] if(dis_buff.dot3==1) 8001ea6: 4b3a ldr r3, [pc, #232] ; (8001f90 ) 8001ea8: 791b ldrb r3, [r3, #4] 8001eaa: 2204 movs r2, #4 8001eac: 4013 ands r3, r2 8001eae: b2db uxtb r3, r3 8001eb0: 2b00 cmp r3, #0 8001eb2: d006 beq.n 8001ec2 { l_buff|=0x80; 8001eb4: 1dbb adds r3, r7, #6 8001eb6: 1dba adds r2, r7, #6 8001eb8: 7812 ldrb r2, [r2, #0] 8001eba: 2180 movs r1, #128 ; 0x80 8001ebc: 4249 negs r1, r1 8001ebe: 430a orrs r2, r1 8001ec0: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001ec2: 1dbb adds r3, r7, #6 8001ec4: 781a ldrb r2, [r3, #0] 8001ec6: 1dfb adds r3, r7, #7 8001ec8: 781b ldrb r3, [r3, #0] 8001eca: 0011 movs r1, r2 8001ecc: 0018 movs r0, r3 8001ece: f7ff ff06 bl 8001cde h_buff=0,l_buff=0; 8001ed2: 1dfb adds r3, r7, #7 8001ed4: 2200 movs r2, #0 8001ed6: 701a strb r2, [r3, #0] 8001ed8: 1dbb adds r3, r7, #6 8001eda: 2200 movs r2, #0 8001edc: 701a strb r2, [r3, #0] h_buff=0xC1; 8001ede: 1dfb adds r3, r7, #7 8001ee0: 22c1 movs r2, #193 ; 0xc1 8001ee2: 701a strb r2, [r3, #0] l_buff=d_num_data[1][dis_buff.d_num[3]]; 8001ee4: 4b2a ldr r3, [pc, #168] ; (8001f90 ) 8001ee6: 78db ldrb r3, [r3, #3] 8001ee8: 0019 movs r1, r3 8001eea: 1dbb adds r3, r7, #6 8001eec: 4a29 ldr r2, [pc, #164] ; (8001f94 ) 8001eee: 1852 adds r2, r2, r1 8001ef0: 7a92 ldrb r2, [r2, #10] 8001ef2: 701a strb r2, [r3, #0] if(dis_buff.dot4==1) 8001ef4: 4b26 ldr r3, [pc, #152] ; (8001f90 ) 8001ef6: 791b ldrb r3, [r3, #4] 8001ef8: 2208 movs r2, #8 8001efa: 4013 ands r3, r2 8001efc: b2db uxtb r3, r3 8001efe: 2b00 cmp r3, #0 8001f00: d005 beq.n 8001f0e { l_buff|=0x10; 8001f02: 1dbb adds r3, r7, #6 8001f04: 1dba adds r2, r7, #6 8001f06: 7812 ldrb r2, [r2, #0] 8001f08: 2110 movs r1, #16 8001f0a: 430a orrs r2, r1 8001f0c: 701a strb r2, [r3, #0] } if(dis_buff.led_run==1) 8001f0e: 4b20 ldr r3, [pc, #128] ; (8001f90 ) 8001f10: 791b ldrb r3, [r3, #4] 8001f12: 2210 movs r2, #16 8001f14: 4013 ands r3, r2 8001f16: b2db uxtb r3, r3 8001f18: 2b00 cmp r3, #0 8001f1a: d005 beq.n 8001f28 { h_buff|=0x10; 8001f1c: 1dfb adds r3, r7, #7 8001f1e: 1dfa adds r2, r7, #7 8001f20: 7812 ldrb r2, [r2, #0] 8001f22: 2110 movs r1, #16 8001f24: 430a orrs r2, r1 8001f26: 701a strb r2, [r3, #0] } if(dis_buff.led_err==1) 8001f28: 4b19 ldr r3, [pc, #100] ; (8001f90 ) 8001f2a: 791b ldrb r3, [r3, #4] 8001f2c: 227f movs r2, #127 ; 0x7f 8001f2e: 4393 bics r3, r2 8001f30: b2db uxtb r3, r3 8001f32: 2b00 cmp r3, #0 8001f34: d005 beq.n 8001f42 { h_buff|=0x08; 8001f36: 1dfb adds r3, r7, #7 8001f38: 1dfa adds r2, r7, #7 8001f3a: 7812 ldrb r2, [r2, #0] 8001f3c: 2108 movs r1, #8 8001f3e: 430a orrs r2, r1 8001f40: 701a strb r2, [r3, #0] } if(dis_buff.led_n==1) 8001f42: 4b13 ldr r3, [pc, #76] ; (8001f90 ) 8001f44: 791b ldrb r3, [r3, #4] 8001f46: 2240 movs r2, #64 ; 0x40 8001f48: 4013 ands r3, r2 8001f4a: b2db uxtb r3, r3 8001f4c: 2b00 cmp r3, #0 8001f4e: d005 beq.n 8001f5c { h_buff|=0x04; 8001f50: 1dfb adds r3, r7, #7 8001f52: 1dfa adds r2, r7, #7 8001f54: 7812 ldrb r2, [r2, #0] 8001f56: 2104 movs r1, #4 8001f58: 430a orrs r2, r1 8001f5a: 701a strb r2, [r3, #0] } if(dis_buff.led_p==1) 8001f5c: 4b0c ldr r3, [pc, #48] ; (8001f90 ) 8001f5e: 791b ldrb r3, [r3, #4] 8001f60: 2220 movs r2, #32 8001f62: 4013 ands r3, r2 8001f64: b2db uxtb r3, r3 8001f66: 2b00 cmp r3, #0 8001f68: d005 beq.n 8001f76 { h_buff|=0x02; 8001f6a: 1dfb adds r3, r7, #7 8001f6c: 1dfa adds r2, r7, #7 8001f6e: 7812 ldrb r2, [r2, #0] 8001f70: 2102 movs r1, #2 8001f72: 430a orrs r2, r1 8001f74: 701a strb r2, [r3, #0] } Send_to_595(h_buff,l_buff); 8001f76: 1dbb adds r3, r7, #6 8001f78: 781a ldrb r2, [r3, #0] 8001f7a: 1dfb adds r3, r7, #7 8001f7c: 781b ldrb r3, [r3, #0] 8001f7e: 0011 movs r1, r2 8001f80: 0018 movs r0, r3 8001f82: f7ff feac bl 8001cde } 8001f86: 46c0 nop ; (mov r8, r8) 8001f88: 46bd mov sp, r7 8001f8a: b002 add sp, #8 8001f8c: bd80 pop {r7, pc} 8001f8e: 46c0 nop ; (mov r8, r8) 8001f90: 200000e8 .word 0x200000e8 8001f94: 080033c8 .word 0x080033c8 08001f98 : void mymain() { 8001f98: b580 push {r7, lr} 8001f9a: b082 sub sp, #8 8001f9c: af00 add r7, sp, #0 uint32_t runtime=0; 8001f9e: 2300 movs r3, #0 8001fa0: 607b str r3, [r7, #4] MOTA(0); 8001fa2: 4bb1 ldr r3, [pc, #708] ; (8002268 ) 8001fa4: 2200 movs r2, #0 8001fa6: 2101 movs r1, #1 8001fa8: 0018 movs r0, r3 8001faa: f7ff f9d2 bl 8001352 MOTB(0); 8001fae: 4bae ldr r3, [pc, #696] ; (8002268 ) 8001fb0: 2200 movs r2, #0 8001fb2: 2102 movs r1, #2 8001fb4: 0018 movs r0, r3 8001fb6: f7ff f9cc bl 8001352 HC595_DCK(0); 8001fba: 2390 movs r3, #144 ; 0x90 8001fbc: 05db lsls r3, r3, #23 8001fbe: 2200 movs r2, #0 8001fc0: 2108 movs r1, #8 8001fc2: 0018 movs r0, r3 8001fc4: f7ff f9c5 bl 8001352 HC595_RCK(0); 8001fc8: 2390 movs r3, #144 ; 0x90 8001fca: 05db lsls r3, r3, #23 8001fcc: 2200 movs r2, #0 8001fce: 2110 movs r1, #16 8001fd0: 0018 movs r0, r3 8001fd2: f7ff f9be bl 8001352 HC595_SCK(0); 8001fd6: 2390 movs r3, #144 ; 0x90 8001fd8: 05db lsls r3, r3, #23 8001fda: 2200 movs r2, #0 8001fdc: 2120 movs r1, #32 8001fde: 0018 movs r0, r3 8001fe0: f7ff f9b7 bl 8001352 while(1) { if(HAL_GetTick()>runtime) 8001fe4: f7fe fd34 bl 8000a50 8001fe8: 0002 movs r2, r0 8001fea: 687b ldr r3, [r7, #4] 8001fec: 4293 cmp r3, r2 8001fee: d300 bcc.n 8001ff2 8001ff0: e0ff b.n 80021f2 { runtime+=1000; 8001ff2: 687b ldr r3, [r7, #4] 8001ff4: 22fa movs r2, #250 ; 0xfa 8001ff6: 0092 lsls r2, r2, #2 8001ff8: 4694 mov ip, r2 8001ffa: 4463 add r3, ip 8001ffc: 607b str r3, [r7, #4] dis_buff.d_num[0]=rand()%10; 8001ffe: f000 f973 bl 80022e8 8002002: 0003 movs r3, r0 8002004: 210a movs r1, #10 8002006: 0018 movs r0, r3 8002008: f7fe f9f8 bl 80003fc <__aeabi_idivmod> 800200c: 000b movs r3, r1 800200e: b2da uxtb r2, r3 8002010: 4b96 ldr r3, [pc, #600] ; (800226c ) 8002012: 701a strb r2, [r3, #0] dis_buff.d_num[1]=rand()%10; 8002014: f000 f968 bl 80022e8 8002018: 0003 movs r3, r0 800201a: 210a movs r1, #10 800201c: 0018 movs r0, r3 800201e: f7fe f9ed bl 80003fc <__aeabi_idivmod> 8002022: 000b movs r3, r1 8002024: b2da uxtb r2, r3 8002026: 4b91 ldr r3, [pc, #580] ; (800226c ) 8002028: 705a strb r2, [r3, #1] dis_buff.d_num[2]=rand()%10; 800202a: f000 f95d bl 80022e8 800202e: 0003 movs r3, r0 8002030: 210a movs r1, #10 8002032: 0018 movs r0, r3 8002034: f7fe f9e2 bl 80003fc <__aeabi_idivmod> 8002038: 000b movs r3, r1 800203a: b2da uxtb r2, r3 800203c: 4b8b ldr r3, [pc, #556] ; (800226c ) 800203e: 709a strb r2, [r3, #2] dis_buff.d_num[3]=rand()%10; 8002040: f000 f952 bl 80022e8 8002044: 0003 movs r3, r0 8002046: 210a movs r1, #10 8002048: 0018 movs r0, r3 800204a: f7fe f9d7 bl 80003fc <__aeabi_idivmod> 800204e: 000b movs r3, r1 8002050: b2da uxtb r2, r3 8002052: 4b86 ldr r3, [pc, #536] ; (800226c ) 8002054: 70da strb r2, [r3, #3] dis_buff.dot1=rand()%2; 8002056: f000 f947 bl 80022e8 800205a: 0003 movs r3, r0 800205c: 4a84 ldr r2, [pc, #528] ; (8002270 ) 800205e: 4013 ands r3, r2 8002060: d504 bpl.n 800206c 8002062: 3b01 subs r3, #1 8002064: 2202 movs r2, #2 8002066: 4252 negs r2, r2 8002068: 4313 orrs r3, r2 800206a: 3301 adds r3, #1 800206c: 1c1a adds r2, r3, #0 800206e: 2301 movs r3, #1 8002070: 4013 ands r3, r2 8002072: b2da uxtb r2, r3 8002074: 4b7d ldr r3, [pc, #500] ; (800226c ) 8002076: 2101 movs r1, #1 8002078: 400a ands r2, r1 800207a: 0010 movs r0, r2 800207c: 791a ldrb r2, [r3, #4] 800207e: 2101 movs r1, #1 8002080: 438a bics r2, r1 8002082: 1c11 adds r1, r2, #0 8002084: 1c02 adds r2, r0, #0 8002086: 430a orrs r2, r1 8002088: 711a strb r2, [r3, #4] dis_buff.dot2=rand()%2; 800208a: f000 f92d bl 80022e8 800208e: 0003 movs r3, r0 8002090: 4a77 ldr r2, [pc, #476] ; (8002270 ) 8002092: 4013 ands r3, r2 8002094: d504 bpl.n 80020a0 8002096: 3b01 subs r3, #1 8002098: 2202 movs r2, #2 800209a: 4252 negs r2, r2 800209c: 4313 orrs r3, r2 800209e: 3301 adds r3, #1 80020a0: 1c1a adds r2, r3, #0 80020a2: 2301 movs r3, #1 80020a4: 4013 ands r3, r2 80020a6: b2da uxtb r2, r3 80020a8: 4b70 ldr r3, [pc, #448] ; (800226c ) 80020aa: 2101 movs r1, #1 80020ac: 400a ands r2, r1 80020ae: 1890 adds r0, r2, r2 80020b0: 791a ldrb r2, [r3, #4] 80020b2: 2102 movs r1, #2 80020b4: 438a bics r2, r1 80020b6: 1c11 adds r1, r2, #0 80020b8: 1c02 adds r2, r0, #0 80020ba: 430a orrs r2, r1 80020bc: 711a strb r2, [r3, #4] dis_buff.dot3=rand()%2; 80020be: f000 f913 bl 80022e8 80020c2: 0003 movs r3, r0 80020c4: 4a6a ldr r2, [pc, #424] ; (8002270 ) 80020c6: 4013 ands r3, r2 80020c8: d504 bpl.n 80020d4 80020ca: 3b01 subs r3, #1 80020cc: 2202 movs r2, #2 80020ce: 4252 negs r2, r2 80020d0: 4313 orrs r3, r2 80020d2: 3301 adds r3, #1 80020d4: 1c1a adds r2, r3, #0 80020d6: 2301 movs r3, #1 80020d8: 4013 ands r3, r2 80020da: b2da uxtb r2, r3 80020dc: 4b63 ldr r3, [pc, #396] ; (800226c ) 80020de: 2101 movs r1, #1 80020e0: 400a ands r2, r1 80020e2: 0090 lsls r0, r2, #2 80020e4: 791a ldrb r2, [r3, #4] 80020e6: 2104 movs r1, #4 80020e8: 438a bics r2, r1 80020ea: 1c11 adds r1, r2, #0 80020ec: 1c02 adds r2, r0, #0 80020ee: 430a orrs r2, r1 80020f0: 711a strb r2, [r3, #4] dis_buff.dot4=rand()%2; 80020f2: f000 f8f9 bl 80022e8 80020f6: 0003 movs r3, r0 80020f8: 4a5d ldr r2, [pc, #372] ; (8002270 ) 80020fa: 4013 ands r3, r2 80020fc: d504 bpl.n 8002108 80020fe: 3b01 subs r3, #1 8002100: 2202 movs r2, #2 8002102: 4252 negs r2, r2 8002104: 4313 orrs r3, r2 8002106: 3301 adds r3, #1 8002108: 1c1a adds r2, r3, #0 800210a: 2301 movs r3, #1 800210c: 4013 ands r3, r2 800210e: b2da uxtb r2, r3 8002110: 4b56 ldr r3, [pc, #344] ; (800226c ) 8002112: 2101 movs r1, #1 8002114: 400a ands r2, r1 8002116: 00d0 lsls r0, r2, #3 8002118: 791a ldrb r2, [r3, #4] 800211a: 2108 movs r1, #8 800211c: 438a bics r2, r1 800211e: 1c11 adds r1, r2, #0 8002120: 1c02 adds r2, r0, #0 8002122: 430a orrs r2, r1 8002124: 711a strb r2, [r3, #4] dis_buff.led_err=rand()%2; 8002126: f000 f8df bl 80022e8 800212a: 0003 movs r3, r0 800212c: 4a50 ldr r2, [pc, #320] ; (8002270 ) 800212e: 4013 ands r3, r2 8002130: d504 bpl.n 800213c 8002132: 3b01 subs r3, #1 8002134: 2202 movs r2, #2 8002136: 4252 negs r2, r2 8002138: 4313 orrs r3, r2 800213a: 3301 adds r3, #1 800213c: 1c1a adds r2, r3, #0 800213e: 2301 movs r3, #1 8002140: 4013 ands r3, r2 8002142: b2da uxtb r2, r3 8002144: 4b49 ldr r3, [pc, #292] ; (800226c ) 8002146: 01d0 lsls r0, r2, #7 8002148: 791a ldrb r2, [r3, #4] 800214a: 217f movs r1, #127 ; 0x7f 800214c: 400a ands r2, r1 800214e: 1c11 adds r1, r2, #0 8002150: 1c02 adds r2, r0, #0 8002152: 430a orrs r2, r1 8002154: 711a strb r2, [r3, #4] dis_buff.led_n=rand()%2; 8002156: f000 f8c7 bl 80022e8 800215a: 0003 movs r3, r0 800215c: 4a44 ldr r2, [pc, #272] ; (8002270 ) 800215e: 4013 ands r3, r2 8002160: d504 bpl.n 800216c 8002162: 3b01 subs r3, #1 8002164: 2202 movs r2, #2 8002166: 4252 negs r2, r2 8002168: 4313 orrs r3, r2 800216a: 3301 adds r3, #1 800216c: 1c1a adds r2, r3, #0 800216e: 2301 movs r3, #1 8002170: 4013 ands r3, r2 8002172: b2da uxtb r2, r3 8002174: 4b3d ldr r3, [pc, #244] ; (800226c ) 8002176: 2101 movs r1, #1 8002178: 400a ands r2, r1 800217a: 0190 lsls r0, r2, #6 800217c: 791a ldrb r2, [r3, #4] 800217e: 2140 movs r1, #64 ; 0x40 8002180: 438a bics r2, r1 8002182: 1c11 adds r1, r2, #0 8002184: 1c02 adds r2, r0, #0 8002186: 430a orrs r2, r1 8002188: 711a strb r2, [r3, #4] dis_buff.led_p=rand()%2; 800218a: f000 f8ad bl 80022e8 800218e: 0003 movs r3, r0 8002190: 4a37 ldr r2, [pc, #220] ; (8002270 ) 8002192: 4013 ands r3, r2 8002194: d504 bpl.n 80021a0 8002196: 3b01 subs r3, #1 8002198: 2202 movs r2, #2 800219a: 4252 negs r2, r2 800219c: 4313 orrs r3, r2 800219e: 3301 adds r3, #1 80021a0: 1c1a adds r2, r3, #0 80021a2: 2301 movs r3, #1 80021a4: 4013 ands r3, r2 80021a6: b2da uxtb r2, r3 80021a8: 4b30 ldr r3, [pc, #192] ; (800226c ) 80021aa: 2101 movs r1, #1 80021ac: 400a ands r2, r1 80021ae: 0150 lsls r0, r2, #5 80021b0: 791a ldrb r2, [r3, #4] 80021b2: 2120 movs r1, #32 80021b4: 438a bics r2, r1 80021b6: 1c11 adds r1, r2, #0 80021b8: 1c02 adds r2, r0, #0 80021ba: 430a orrs r2, r1 80021bc: 711a strb r2, [r3, #4] dis_buff.led_run=rand()%2; 80021be: f000 f893 bl 80022e8 80021c2: 0003 movs r3, r0 80021c4: 4a2a ldr r2, [pc, #168] ; (8002270 ) 80021c6: 4013 ands r3, r2 80021c8: d504 bpl.n 80021d4 80021ca: 3b01 subs r3, #1 80021cc: 2202 movs r2, #2 80021ce: 4252 negs r2, r2 80021d0: 4313 orrs r3, r2 80021d2: 3301 adds r3, #1 80021d4: 1c1a adds r2, r3, #0 80021d6: 2301 movs r3, #1 80021d8: 4013 ands r3, r2 80021da: b2da uxtb r2, r3 80021dc: 4b23 ldr r3, [pc, #140] ; (800226c ) 80021de: 2101 movs r1, #1 80021e0: 400a ands r2, r1 80021e2: 0110 lsls r0, r2, #4 80021e4: 791a ldrb r2, [r3, #4] 80021e6: 2110 movs r1, #16 80021e8: 438a bics r2, r1 80021ea: 1c11 adds r1, r2, #0 80021ec: 1c02 adds r2, r0, #0 80021ee: 430a orrs r2, r1 80021f0: 711a strb r2, [r3, #4] } GEI_BUTTON_CODE(&key1,KEY1); 80021f2: 2390 movs r3, #144 ; 0x90 80021f4: 05db lsls r3, r3, #23 80021f6: 2140 movs r1, #64 ; 0x40 80021f8: 0018 movs r0, r3 80021fa: f7ff f88d bl 8001318 80021fe: 0003 movs r3, r0 8002200: 001a movs r2, r3 8002202: 4b1c ldr r3, [pc, #112] ; (8002274 ) 8002204: 0011 movs r1, r2 8002206: 0018 movs r0, r3 8002208: f7ff fd0c bl 8001c24 GEI_BUTTON_CODE(&key2,KEY2); 800220c: 2390 movs r3, #144 ; 0x90 800220e: 05db lsls r3, r3, #23 8002210: 2180 movs r1, #128 ; 0x80 8002212: 0018 movs r0, r3 8002214: f7ff f880 bl 8001318 8002218: 0003 movs r3, r0 800221a: 001a movs r2, r3 800221c: 4b16 ldr r3, [pc, #88] ; (8002278 ) 800221e: 0011 movs r1, r2 8002220: 0018 movs r0, r3 8002222: f7ff fcff bl 8001c24 GEI_BUTTON_CODE(&key3,KEY3); 8002226: 2380 movs r3, #128 ; 0x80 8002228: 009a lsls r2, r3, #2 800222a: 2390 movs r3, #144 ; 0x90 800222c: 05db lsls r3, r3, #23 800222e: 0011 movs r1, r2 8002230: 0018 movs r0, r3 8002232: f7ff f871 bl 8001318 8002236: 0003 movs r3, r0 8002238: 001a movs r2, r3 800223a: 4b10 ldr r3, [pc, #64] ; (800227c ) 800223c: 0011 movs r1, r2 800223e: 0018 movs r0, r3 8002240: f7ff fcf0 bl 8001c24 GEI_BUTTON_CODE(&key4,KEY4); 8002244: 2380 movs r3, #128 ; 0x80 8002246: 00da lsls r2, r3, #3 8002248: 2390 movs r3, #144 ; 0x90 800224a: 05db lsls r3, r3, #23 800224c: 0011 movs r1, r2 800224e: 0018 movs r0, r3 8002250: f7ff f862 bl 8001318 8002254: 0003 movs r3, r0 8002256: 001a movs r2, r3 8002258: 4b09 ldr r3, [pc, #36] ; (8002280 ) 800225a: 0011 movs r1, r2 800225c: 0018 movs r0, r3 800225e: f7ff fce1 bl 8001c24 display(); 8002262: f7ff fdb3 bl 8001dcc if(HAL_GetTick()>runtime) 8002266: e6bd b.n 8001fe4 8002268: 48001400 .word 0x48001400 800226c: 200000e8 .word 0x200000e8 8002270: 80000001 .word 0x80000001 8002274: 200000f0 .word 0x200000f0 8002278: 20000108 .word 0x20000108 800227c: 200000fc .word 0x200000fc 8002280: 200000dc .word 0x200000dc 08002284 <__errno>: 8002284: 4b01 ldr r3, [pc, #4] ; (800228c <__errno+0x8>) 8002286: 6818 ldr r0, [r3, #0] 8002288: 4770 bx lr 800228a: 46c0 nop ; (mov r8, r8) 800228c: 2000000c .word 0x2000000c 08002290 <__libc_init_array>: 8002290: b570 push {r4, r5, r6, lr} 8002292: 2600 movs r6, #0 8002294: 4d0c ldr r5, [pc, #48] ; (80022c8 <__libc_init_array+0x38>) 8002296: 4c0d ldr r4, [pc, #52] ; (80022cc <__libc_init_array+0x3c>) 8002298: 1b64 subs r4, r4, r5 800229a: 10a4 asrs r4, r4, #2 800229c: 42a6 cmp r6, r4 800229e: d109 bne.n 80022b4 <__libc_init_array+0x24> 80022a0: 2600 movs r6, #0 80022a2: f001 f86d bl 8003380 <_init> 80022a6: 4d0a ldr r5, [pc, #40] ; (80022d0 <__libc_init_array+0x40>) 80022a8: 4c0a ldr r4, [pc, #40] ; (80022d4 <__libc_init_array+0x44>) 80022aa: 1b64 subs r4, r4, r5 80022ac: 10a4 asrs r4, r4, #2 80022ae: 42a6 cmp r6, r4 80022b0: d105 bne.n 80022be <__libc_init_array+0x2e> 80022b2: bd70 pop {r4, r5, r6, pc} 80022b4: 00b3 lsls r3, r6, #2 80022b6: 58eb ldr r3, [r5, r3] 80022b8: 4798 blx r3 80022ba: 3601 adds r6, #1 80022bc: e7ee b.n 800229c <__libc_init_array+0xc> 80022be: 00b3 lsls r3, r6, #2 80022c0: 58eb ldr r3, [r5, r3] 80022c2: 4798 blx r3 80022c4: 3601 adds r6, #1 80022c6: e7f2 b.n 80022ae <__libc_init_array+0x1e> 80022c8: 08003528 .word 0x08003528 80022cc: 08003528 .word 0x08003528 80022d0: 08003528 .word 0x08003528 80022d4: 0800352c .word 0x0800352c 080022d8 : 80022d8: 0003 movs r3, r0 80022da: 1882 adds r2, r0, r2 80022dc: 4293 cmp r3, r2 80022de: d100 bne.n 80022e2 80022e0: 4770 bx lr 80022e2: 7019 strb r1, [r3, #0] 80022e4: 3301 adds r3, #1 80022e6: e7f9 b.n 80022dc 080022e8 : 80022e8: 4b16 ldr r3, [pc, #88] ; (8002344 ) 80022ea: b510 push {r4, lr} 80022ec: 681c ldr r4, [r3, #0] 80022ee: 6ba3 ldr r3, [r4, #56] ; 0x38 80022f0: 2b00 cmp r3, #0 80022f2: d116 bne.n 8002322 80022f4: 2018 movs r0, #24 80022f6: f000 f863 bl 80023c0 80022fa: 1e02 subs r2, r0, #0 80022fc: 63a0 str r0, [r4, #56] ; 0x38 80022fe: d104 bne.n 800230a 8002300: 214e movs r1, #78 ; 0x4e 8002302: 4b11 ldr r3, [pc, #68] ; (8002348 ) 8002304: 4811 ldr r0, [pc, #68] ; (800234c ) 8002306: f000 f82d bl 8002364 <__assert_func> 800230a: 4b11 ldr r3, [pc, #68] ; (8002350 ) 800230c: 2100 movs r1, #0 800230e: 6003 str r3, [r0, #0] 8002310: 4b10 ldr r3, [pc, #64] ; (8002354 ) 8002312: 6043 str r3, [r0, #4] 8002314: 4b10 ldr r3, [pc, #64] ; (8002358 ) 8002316: 6083 str r3, [r0, #8] 8002318: 230b movs r3, #11 800231a: 8183 strh r3, [r0, #12] 800231c: 2001 movs r0, #1 800231e: 6110 str r0, [r2, #16] 8002320: 6151 str r1, [r2, #20] 8002322: 6ba4 ldr r4, [r4, #56] ; 0x38 8002324: 4a0d ldr r2, [pc, #52] ; (800235c ) 8002326: 6920 ldr r0, [r4, #16] 8002328: 6961 ldr r1, [r4, #20] 800232a: 4b0d ldr r3, [pc, #52] ; (8002360 ) 800232c: f7fe f86c bl 8000408 <__aeabi_lmul> 8002330: 2201 movs r2, #1 8002332: 2300 movs r3, #0 8002334: 1880 adds r0, r0, r2 8002336: 4159 adcs r1, r3 8002338: 6120 str r0, [r4, #16] 800233a: 6161 str r1, [r4, #20] 800233c: 0048 lsls r0, r1, #1 800233e: 0840 lsrs r0, r0, #1 8002340: bd10 pop {r4, pc} 8002342: 46c0 nop ; (mov r8, r8) 8002344: 2000000c .word 0x2000000c 8002348: 080033e0 .word 0x080033e0 800234c: 080033f7 .word 0x080033f7 8002350: abcd330e .word 0xabcd330e 8002354: e66d1234 .word 0xe66d1234 8002358: 0005deec .word 0x0005deec 800235c: 4c957f2d .word 0x4c957f2d 8002360: 5851f42d .word 0x5851f42d 08002364 <__assert_func>: 8002364: b530 push {r4, r5, lr} 8002366: 0014 movs r4, r2 8002368: 001a movs r2, r3 800236a: 4b09 ldr r3, [pc, #36] ; (8002390 <__assert_func+0x2c>) 800236c: 0005 movs r5, r0 800236e: 681b ldr r3, [r3, #0] 8002370: b085 sub sp, #20 8002372: 68d8 ldr r0, [r3, #12] 8002374: 4b07 ldr r3, [pc, #28] ; (8002394 <__assert_func+0x30>) 8002376: 2c00 cmp r4, #0 8002378: d101 bne.n 800237e <__assert_func+0x1a> 800237a: 4b07 ldr r3, [pc, #28] ; (8002398 <__assert_func+0x34>) 800237c: 001c movs r4, r3 800237e: 9301 str r3, [sp, #4] 8002380: 9100 str r1, [sp, #0] 8002382: 002b movs r3, r5 8002384: 4905 ldr r1, [pc, #20] ; (800239c <__assert_func+0x38>) 8002386: 9402 str r4, [sp, #8] 8002388: f000 f80a bl 80023a0 800238c: f000 fc8e bl 8002cac 8002390: 2000000c .word 0x2000000c 8002394: 08003456 .word 0x08003456 8002398: 08003491 .word 0x08003491 800239c: 08003463 .word 0x08003463 080023a0 : 80023a0: b40e push {r1, r2, r3} 80023a2: b503 push {r0, r1, lr} 80023a4: 0001 movs r1, r0 80023a6: ab03 add r3, sp, #12 80023a8: 4804 ldr r0, [pc, #16] ; (80023bc ) 80023aa: cb04 ldmia r3!, {r2} 80023ac: 6800 ldr r0, [r0, #0] 80023ae: 9301 str r3, [sp, #4] 80023b0: f000 f8e0 bl 8002574 <_vfiprintf_r> 80023b4: b002 add sp, #8 80023b6: bc08 pop {r3} 80023b8: b003 add sp, #12 80023ba: 4718 bx r3 80023bc: 2000000c .word 0x2000000c 080023c0 : 80023c0: b510 push {r4, lr} 80023c2: 4b03 ldr r3, [pc, #12] ; (80023d0 ) 80023c4: 0001 movs r1, r0 80023c6: 6818 ldr r0, [r3, #0] 80023c8: f000 f84e bl 8002468 <_malloc_r> 80023cc: bd10 pop {r4, pc} 80023ce: 46c0 nop ; (mov r8, r8) 80023d0: 2000000c .word 0x2000000c 080023d4 <_free_r>: 80023d4: b570 push {r4, r5, r6, lr} 80023d6: 0005 movs r5, r0 80023d8: 2900 cmp r1, #0 80023da: d010 beq.n 80023fe <_free_r+0x2a> 80023dc: 1f0c subs r4, r1, #4 80023de: 6823 ldr r3, [r4, #0] 80023e0: 2b00 cmp r3, #0 80023e2: da00 bge.n 80023e6 <_free_r+0x12> 80023e4: 18e4 adds r4, r4, r3 80023e6: 0028 movs r0, r5 80023e8: f000 feb2 bl 8003150 <__malloc_lock> 80023ec: 4a1d ldr r2, [pc, #116] ; (8002464 <_free_r+0x90>) 80023ee: 6813 ldr r3, [r2, #0] 80023f0: 2b00 cmp r3, #0 80023f2: d105 bne.n 8002400 <_free_r+0x2c> 80023f4: 6063 str r3, [r4, #4] 80023f6: 6014 str r4, [r2, #0] 80023f8: 0028 movs r0, r5 80023fa: f000 feb1 bl 8003160 <__malloc_unlock> 80023fe: bd70 pop {r4, r5, r6, pc} 8002400: 42a3 cmp r3, r4 8002402: d908 bls.n 8002416 <_free_r+0x42> 8002404: 6821 ldr r1, [r4, #0] 8002406: 1860 adds r0, r4, r1 8002408: 4283 cmp r3, r0 800240a: d1f3 bne.n 80023f4 <_free_r+0x20> 800240c: 6818 ldr r0, [r3, #0] 800240e: 685b ldr r3, [r3, #4] 8002410: 1841 adds r1, r0, r1 8002412: 6021 str r1, [r4, #0] 8002414: e7ee b.n 80023f4 <_free_r+0x20> 8002416: 001a movs r2, r3 8002418: 685b ldr r3, [r3, #4] 800241a: 2b00 cmp r3, #0 800241c: d001 beq.n 8002422 <_free_r+0x4e> 800241e: 42a3 cmp r3, r4 8002420: d9f9 bls.n 8002416 <_free_r+0x42> 8002422: 6811 ldr r1, [r2, #0] 8002424: 1850 adds r0, r2, r1 8002426: 42a0 cmp r0, r4 8002428: d10b bne.n 8002442 <_free_r+0x6e> 800242a: 6820 ldr r0, [r4, #0] 800242c: 1809 adds r1, r1, r0 800242e: 1850 adds r0, r2, r1 8002430: 6011 str r1, [r2, #0] 8002432: 4283 cmp r3, r0 8002434: d1e0 bne.n 80023f8 <_free_r+0x24> 8002436: 6818 ldr r0, [r3, #0] 8002438: 685b ldr r3, [r3, #4] 800243a: 1841 adds r1, r0, r1 800243c: 6011 str r1, [r2, #0] 800243e: 6053 str r3, [r2, #4] 8002440: e7da b.n 80023f8 <_free_r+0x24> 8002442: 42a0 cmp r0, r4 8002444: d902 bls.n 800244c <_free_r+0x78> 8002446: 230c movs r3, #12 8002448: 602b str r3, [r5, #0] 800244a: e7d5 b.n 80023f8 <_free_r+0x24> 800244c: 6821 ldr r1, [r4, #0] 800244e: 1860 adds r0, r4, r1 8002450: 4283 cmp r3, r0 8002452: d103 bne.n 800245c <_free_r+0x88> 8002454: 6818 ldr r0, [r3, #0] 8002456: 685b ldr r3, [r3, #4] 8002458: 1841 adds r1, r0, r1 800245a: 6021 str r1, [r4, #0] 800245c: 6063 str r3, [r4, #4] 800245e: 6054 str r4, [r2, #4] 8002460: e7ca b.n 80023f8 <_free_r+0x24> 8002462: 46c0 nop ; (mov r8, r8) 8002464: 20000090 .word 0x20000090 08002468 <_malloc_r>: 8002468: b5f8 push {r3, r4, r5, r6, r7, lr} 800246a: 2303 movs r3, #3 800246c: 1ccd adds r5, r1, #3 800246e: 439d bics r5, r3 8002470: 3508 adds r5, #8 8002472: 0006 movs r6, r0 8002474: 2d0c cmp r5, #12 8002476: d21f bcs.n 80024b8 <_malloc_r+0x50> 8002478: 250c movs r5, #12 800247a: 42a9 cmp r1, r5 800247c: d81e bhi.n 80024bc <_malloc_r+0x54> 800247e: 0030 movs r0, r6 8002480: f000 fe66 bl 8003150 <__malloc_lock> 8002484: 4925 ldr r1, [pc, #148] ; (800251c <_malloc_r+0xb4>) 8002486: 680a ldr r2, [r1, #0] 8002488: 0014 movs r4, r2 800248a: 2c00 cmp r4, #0 800248c: d11a bne.n 80024c4 <_malloc_r+0x5c> 800248e: 4f24 ldr r7, [pc, #144] ; (8002520 <_malloc_r+0xb8>) 8002490: 683b ldr r3, [r7, #0] 8002492: 2b00 cmp r3, #0 8002494: d104 bne.n 80024a0 <_malloc_r+0x38> 8002496: 0021 movs r1, r4 8002498: 0030 movs r0, r6 800249a: f000 fb27 bl 8002aec <_sbrk_r> 800249e: 6038 str r0, [r7, #0] 80024a0: 0029 movs r1, r5 80024a2: 0030 movs r0, r6 80024a4: f000 fb22 bl 8002aec <_sbrk_r> 80024a8: 1c43 adds r3, r0, #1 80024aa: d12b bne.n 8002504 <_malloc_r+0x9c> 80024ac: 230c movs r3, #12 80024ae: 0030 movs r0, r6 80024b0: 6033 str r3, [r6, #0] 80024b2: f000 fe55 bl 8003160 <__malloc_unlock> 80024b6: e003 b.n 80024c0 <_malloc_r+0x58> 80024b8: 2d00 cmp r5, #0 80024ba: dade bge.n 800247a <_malloc_r+0x12> 80024bc: 230c movs r3, #12 80024be: 6033 str r3, [r6, #0] 80024c0: 2000 movs r0, #0 80024c2: bdf8 pop {r3, r4, r5, r6, r7, pc} 80024c4: 6823 ldr r3, [r4, #0] 80024c6: 1b5b subs r3, r3, r5 80024c8: d419 bmi.n 80024fe <_malloc_r+0x96> 80024ca: 2b0b cmp r3, #11 80024cc: d903 bls.n 80024d6 <_malloc_r+0x6e> 80024ce: 6023 str r3, [r4, #0] 80024d0: 18e4 adds r4, r4, r3 80024d2: 6025 str r5, [r4, #0] 80024d4: e003 b.n 80024de <_malloc_r+0x76> 80024d6: 6863 ldr r3, [r4, #4] 80024d8: 42a2 cmp r2, r4 80024da: d10e bne.n 80024fa <_malloc_r+0x92> 80024dc: 600b str r3, [r1, #0] 80024de: 0030 movs r0, r6 80024e0: f000 fe3e bl 8003160 <__malloc_unlock> 80024e4: 0020 movs r0, r4 80024e6: 2207 movs r2, #7 80024e8: 300b adds r0, #11 80024ea: 1d23 adds r3, r4, #4 80024ec: 4390 bics r0, r2 80024ee: 1ac2 subs r2, r0, r3 80024f0: 4298 cmp r0, r3 80024f2: d0e6 beq.n 80024c2 <_malloc_r+0x5a> 80024f4: 1a1b subs r3, r3, r0 80024f6: 50a3 str r3, [r4, r2] 80024f8: e7e3 b.n 80024c2 <_malloc_r+0x5a> 80024fa: 6053 str r3, [r2, #4] 80024fc: e7ef b.n 80024de <_malloc_r+0x76> 80024fe: 0022 movs r2, r4 8002500: 6864 ldr r4, [r4, #4] 8002502: e7c2 b.n 800248a <_malloc_r+0x22> 8002504: 2303 movs r3, #3 8002506: 1cc4 adds r4, r0, #3 8002508: 439c bics r4, r3 800250a: 42a0 cmp r0, r4 800250c: d0e1 beq.n 80024d2 <_malloc_r+0x6a> 800250e: 1a21 subs r1, r4, r0 8002510: 0030 movs r0, r6 8002512: f000 faeb bl 8002aec <_sbrk_r> 8002516: 1c43 adds r3, r0, #1 8002518: d1db bne.n 80024d2 <_malloc_r+0x6a> 800251a: e7c7 b.n 80024ac <_malloc_r+0x44> 800251c: 20000090 .word 0x20000090 8002520: 20000094 .word 0x20000094 08002524 <__sfputc_r>: 8002524: 6893 ldr r3, [r2, #8] 8002526: b510 push {r4, lr} 8002528: 3b01 subs r3, #1 800252a: 6093 str r3, [r2, #8] 800252c: 2b00 cmp r3, #0 800252e: da04 bge.n 800253a <__sfputc_r+0x16> 8002530: 6994 ldr r4, [r2, #24] 8002532: 42a3 cmp r3, r4 8002534: db07 blt.n 8002546 <__sfputc_r+0x22> 8002536: 290a cmp r1, #10 8002538: d005 beq.n 8002546 <__sfputc_r+0x22> 800253a: 6813 ldr r3, [r2, #0] 800253c: 1c58 adds r0, r3, #1 800253e: 6010 str r0, [r2, #0] 8002540: 7019 strb r1, [r3, #0] 8002542: 0008 movs r0, r1 8002544: bd10 pop {r4, pc} 8002546: f000 fae3 bl 8002b10 <__swbuf_r> 800254a: 0001 movs r1, r0 800254c: e7f9 b.n 8002542 <__sfputc_r+0x1e> 0800254e <__sfputs_r>: 800254e: b5f8 push {r3, r4, r5, r6, r7, lr} 8002550: 0006 movs r6, r0 8002552: 000f movs r7, r1 8002554: 0014 movs r4, r2 8002556: 18d5 adds r5, r2, r3 8002558: 42ac cmp r4, r5 800255a: d101 bne.n 8002560 <__sfputs_r+0x12> 800255c: 2000 movs r0, #0 800255e: e007 b.n 8002570 <__sfputs_r+0x22> 8002560: 7821 ldrb r1, [r4, #0] 8002562: 003a movs r2, r7 8002564: 0030 movs r0, r6 8002566: f7ff ffdd bl 8002524 <__sfputc_r> 800256a: 3401 adds r4, #1 800256c: 1c43 adds r3, r0, #1 800256e: d1f3 bne.n 8002558 <__sfputs_r+0xa> 8002570: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08002574 <_vfiprintf_r>: 8002574: b5f0 push {r4, r5, r6, r7, lr} 8002576: b0a1 sub sp, #132 ; 0x84 8002578: 0006 movs r6, r0 800257a: 000c movs r4, r1 800257c: 001f movs r7, r3 800257e: 9203 str r2, [sp, #12] 8002580: 2800 cmp r0, #0 8002582: d004 beq.n 800258e <_vfiprintf_r+0x1a> 8002584: 6983 ldr r3, [r0, #24] 8002586: 2b00 cmp r3, #0 8002588: d101 bne.n 800258e <_vfiprintf_r+0x1a> 800258a: f000 fcc5 bl 8002f18 <__sinit> 800258e: 4b8e ldr r3, [pc, #568] ; (80027c8 <_vfiprintf_r+0x254>) 8002590: 429c cmp r4, r3 8002592: d11c bne.n 80025ce <_vfiprintf_r+0x5a> 8002594: 6874 ldr r4, [r6, #4] 8002596: 6e63 ldr r3, [r4, #100] ; 0x64 8002598: 07db lsls r3, r3, #31 800259a: d405 bmi.n 80025a8 <_vfiprintf_r+0x34> 800259c: 89a3 ldrh r3, [r4, #12] 800259e: 059b lsls r3, r3, #22 80025a0: d402 bmi.n 80025a8 <_vfiprintf_r+0x34> 80025a2: 6da0 ldr r0, [r4, #88] ; 0x58 80025a4: f000 fd59 bl 800305a <__retarget_lock_acquire_recursive> 80025a8: 89a3 ldrh r3, [r4, #12] 80025aa: 071b lsls r3, r3, #28 80025ac: d502 bpl.n 80025b4 <_vfiprintf_r+0x40> 80025ae: 6923 ldr r3, [r4, #16] 80025b0: 2b00 cmp r3, #0 80025b2: d11d bne.n 80025f0 <_vfiprintf_r+0x7c> 80025b4: 0021 movs r1, r4 80025b6: 0030 movs r0, r6 80025b8: f000 fb00 bl 8002bbc <__swsetup_r> 80025bc: 2800 cmp r0, #0 80025be: d017 beq.n 80025f0 <_vfiprintf_r+0x7c> 80025c0: 6e63 ldr r3, [r4, #100] ; 0x64 80025c2: 07db lsls r3, r3, #31 80025c4: d50d bpl.n 80025e2 <_vfiprintf_r+0x6e> 80025c6: 2001 movs r0, #1 80025c8: 4240 negs r0, r0 80025ca: b021 add sp, #132 ; 0x84 80025cc: bdf0 pop {r4, r5, r6, r7, pc} 80025ce: 4b7f ldr r3, [pc, #508] ; (80027cc <_vfiprintf_r+0x258>) 80025d0: 429c cmp r4, r3 80025d2: d101 bne.n 80025d8 <_vfiprintf_r+0x64> 80025d4: 68b4 ldr r4, [r6, #8] 80025d6: e7de b.n 8002596 <_vfiprintf_r+0x22> 80025d8: 4b7d ldr r3, [pc, #500] ; (80027d0 <_vfiprintf_r+0x25c>) 80025da: 429c cmp r4, r3 80025dc: d1db bne.n 8002596 <_vfiprintf_r+0x22> 80025de: 68f4 ldr r4, [r6, #12] 80025e0: e7d9 b.n 8002596 <_vfiprintf_r+0x22> 80025e2: 89a3 ldrh r3, [r4, #12] 80025e4: 059b lsls r3, r3, #22 80025e6: d4ee bmi.n 80025c6 <_vfiprintf_r+0x52> 80025e8: 6da0 ldr r0, [r4, #88] ; 0x58 80025ea: f000 fd37 bl 800305c <__retarget_lock_release_recursive> 80025ee: e7ea b.n 80025c6 <_vfiprintf_r+0x52> 80025f0: 2300 movs r3, #0 80025f2: ad08 add r5, sp, #32 80025f4: 616b str r3, [r5, #20] 80025f6: 3320 adds r3, #32 80025f8: 766b strb r3, [r5, #25] 80025fa: 3310 adds r3, #16 80025fc: 76ab strb r3, [r5, #26] 80025fe: 9707 str r7, [sp, #28] 8002600: 9f03 ldr r7, [sp, #12] 8002602: 783b ldrb r3, [r7, #0] 8002604: 2b00 cmp r3, #0 8002606: d001 beq.n 800260c <_vfiprintf_r+0x98> 8002608: 2b25 cmp r3, #37 ; 0x25 800260a: d14e bne.n 80026aa <_vfiprintf_r+0x136> 800260c: 9b03 ldr r3, [sp, #12] 800260e: 1afb subs r3, r7, r3 8002610: 9305 str r3, [sp, #20] 8002612: 9b03 ldr r3, [sp, #12] 8002614: 429f cmp r7, r3 8002616: d00d beq.n 8002634 <_vfiprintf_r+0xc0> 8002618: 9b05 ldr r3, [sp, #20] 800261a: 0021 movs r1, r4 800261c: 0030 movs r0, r6 800261e: 9a03 ldr r2, [sp, #12] 8002620: f7ff ff95 bl 800254e <__sfputs_r> 8002624: 1c43 adds r3, r0, #1 8002626: d100 bne.n 800262a <_vfiprintf_r+0xb6> 8002628: e0b5 b.n 8002796 <_vfiprintf_r+0x222> 800262a: 696a ldr r2, [r5, #20] 800262c: 9b05 ldr r3, [sp, #20] 800262e: 4694 mov ip, r2 8002630: 4463 add r3, ip 8002632: 616b str r3, [r5, #20] 8002634: 783b ldrb r3, [r7, #0] 8002636: 2b00 cmp r3, #0 8002638: d100 bne.n 800263c <_vfiprintf_r+0xc8> 800263a: e0ac b.n 8002796 <_vfiprintf_r+0x222> 800263c: 2201 movs r2, #1 800263e: 1c7b adds r3, r7, #1 8002640: 9303 str r3, [sp, #12] 8002642: 2300 movs r3, #0 8002644: 4252 negs r2, r2 8002646: 606a str r2, [r5, #4] 8002648: a904 add r1, sp, #16 800264a: 3254 adds r2, #84 ; 0x54 800264c: 1852 adds r2, r2, r1 800264e: 602b str r3, [r5, #0] 8002650: 60eb str r3, [r5, #12] 8002652: 60ab str r3, [r5, #8] 8002654: 7013 strb r3, [r2, #0] 8002656: 65ab str r3, [r5, #88] ; 0x58 8002658: 9b03 ldr r3, [sp, #12] 800265a: 2205 movs r2, #5 800265c: 7819 ldrb r1, [r3, #0] 800265e: 485d ldr r0, [pc, #372] ; (80027d4 <_vfiprintf_r+0x260>) 8002660: f000 fd6a bl 8003138 8002664: 9b03 ldr r3, [sp, #12] 8002666: 1c5f adds r7, r3, #1 8002668: 2800 cmp r0, #0 800266a: d120 bne.n 80026ae <_vfiprintf_r+0x13a> 800266c: 682a ldr r2, [r5, #0] 800266e: 06d3 lsls r3, r2, #27 8002670: d504 bpl.n 800267c <_vfiprintf_r+0x108> 8002672: 2353 movs r3, #83 ; 0x53 8002674: a904 add r1, sp, #16 8002676: 185b adds r3, r3, r1 8002678: 2120 movs r1, #32 800267a: 7019 strb r1, [r3, #0] 800267c: 0713 lsls r3, r2, #28 800267e: d504 bpl.n 800268a <_vfiprintf_r+0x116> 8002680: 2353 movs r3, #83 ; 0x53 8002682: a904 add r1, sp, #16 8002684: 185b adds r3, r3, r1 8002686: 212b movs r1, #43 ; 0x2b 8002688: 7019 strb r1, [r3, #0] 800268a: 9b03 ldr r3, [sp, #12] 800268c: 781b ldrb r3, [r3, #0] 800268e: 2b2a cmp r3, #42 ; 0x2a 8002690: d016 beq.n 80026c0 <_vfiprintf_r+0x14c> 8002692: 2100 movs r1, #0 8002694: 68eb ldr r3, [r5, #12] 8002696: 9f03 ldr r7, [sp, #12] 8002698: 783a ldrb r2, [r7, #0] 800269a: 1c78 adds r0, r7, #1 800269c: 3a30 subs r2, #48 ; 0x30 800269e: 4684 mov ip, r0 80026a0: 2a09 cmp r2, #9 80026a2: d94f bls.n 8002744 <_vfiprintf_r+0x1d0> 80026a4: 2900 cmp r1, #0 80026a6: d111 bne.n 80026cc <_vfiprintf_r+0x158> 80026a8: e017 b.n 80026da <_vfiprintf_r+0x166> 80026aa: 3701 adds r7, #1 80026ac: e7a9 b.n 8002602 <_vfiprintf_r+0x8e> 80026ae: 4b49 ldr r3, [pc, #292] ; (80027d4 <_vfiprintf_r+0x260>) 80026b0: 682a ldr r2, [r5, #0] 80026b2: 1ac0 subs r0, r0, r3 80026b4: 2301 movs r3, #1 80026b6: 4083 lsls r3, r0 80026b8: 4313 orrs r3, r2 80026ba: 602b str r3, [r5, #0] 80026bc: 9703 str r7, [sp, #12] 80026be: e7cb b.n 8002658 <_vfiprintf_r+0xe4> 80026c0: 9b07 ldr r3, [sp, #28] 80026c2: 1d19 adds r1, r3, #4 80026c4: 681b ldr r3, [r3, #0] 80026c6: 9107 str r1, [sp, #28] 80026c8: 2b00 cmp r3, #0 80026ca: db01 blt.n 80026d0 <_vfiprintf_r+0x15c> 80026cc: 930b str r3, [sp, #44] ; 0x2c 80026ce: e004 b.n 80026da <_vfiprintf_r+0x166> 80026d0: 425b negs r3, r3 80026d2: 60eb str r3, [r5, #12] 80026d4: 2302 movs r3, #2 80026d6: 4313 orrs r3, r2 80026d8: 602b str r3, [r5, #0] 80026da: 783b ldrb r3, [r7, #0] 80026dc: 2b2e cmp r3, #46 ; 0x2e 80026de: d10a bne.n 80026f6 <_vfiprintf_r+0x182> 80026e0: 787b ldrb r3, [r7, #1] 80026e2: 2b2a cmp r3, #42 ; 0x2a 80026e4: d137 bne.n 8002756 <_vfiprintf_r+0x1e2> 80026e6: 9b07 ldr r3, [sp, #28] 80026e8: 3702 adds r7, #2 80026ea: 1d1a adds r2, r3, #4 80026ec: 681b ldr r3, [r3, #0] 80026ee: 9207 str r2, [sp, #28] 80026f0: 2b00 cmp r3, #0 80026f2: db2d blt.n 8002750 <_vfiprintf_r+0x1dc> 80026f4: 9309 str r3, [sp, #36] ; 0x24 80026f6: 2203 movs r2, #3 80026f8: 7839 ldrb r1, [r7, #0] 80026fa: 4837 ldr r0, [pc, #220] ; (80027d8 <_vfiprintf_r+0x264>) 80026fc: f000 fd1c bl 8003138 8002700: 2800 cmp r0, #0 8002702: d007 beq.n 8002714 <_vfiprintf_r+0x1a0> 8002704: 4b34 ldr r3, [pc, #208] ; (80027d8 <_vfiprintf_r+0x264>) 8002706: 682a ldr r2, [r5, #0] 8002708: 1ac0 subs r0, r0, r3 800270a: 2340 movs r3, #64 ; 0x40 800270c: 4083 lsls r3, r0 800270e: 4313 orrs r3, r2 8002710: 3701 adds r7, #1 8002712: 602b str r3, [r5, #0] 8002714: 7839 ldrb r1, [r7, #0] 8002716: 1c7b adds r3, r7, #1 8002718: 2206 movs r2, #6 800271a: 4830 ldr r0, [pc, #192] ; (80027dc <_vfiprintf_r+0x268>) 800271c: 9303 str r3, [sp, #12] 800271e: 7629 strb r1, [r5, #24] 8002720: f000 fd0a bl 8003138 8002724: 2800 cmp r0, #0 8002726: d045 beq.n 80027b4 <_vfiprintf_r+0x240> 8002728: 4b2d ldr r3, [pc, #180] ; (80027e0 <_vfiprintf_r+0x26c>) 800272a: 2b00 cmp r3, #0 800272c: d127 bne.n 800277e <_vfiprintf_r+0x20a> 800272e: 2207 movs r2, #7 8002730: 9b07 ldr r3, [sp, #28] 8002732: 3307 adds r3, #7 8002734: 4393 bics r3, r2 8002736: 3308 adds r3, #8 8002738: 9307 str r3, [sp, #28] 800273a: 696b ldr r3, [r5, #20] 800273c: 9a04 ldr r2, [sp, #16] 800273e: 189b adds r3, r3, r2 8002740: 616b str r3, [r5, #20] 8002742: e75d b.n 8002600 <_vfiprintf_r+0x8c> 8002744: 210a movs r1, #10 8002746: 434b muls r3, r1 8002748: 4667 mov r7, ip 800274a: 189b adds r3, r3, r2 800274c: 3909 subs r1, #9 800274e: e7a3 b.n 8002698 <_vfiprintf_r+0x124> 8002750: 2301 movs r3, #1 8002752: 425b negs r3, r3 8002754: e7ce b.n 80026f4 <_vfiprintf_r+0x180> 8002756: 2300 movs r3, #0 8002758: 001a movs r2, r3 800275a: 3701 adds r7, #1 800275c: 606b str r3, [r5, #4] 800275e: 7839 ldrb r1, [r7, #0] 8002760: 1c78 adds r0, r7, #1 8002762: 3930 subs r1, #48 ; 0x30 8002764: 4684 mov ip, r0 8002766: 2909 cmp r1, #9 8002768: d903 bls.n 8002772 <_vfiprintf_r+0x1fe> 800276a: 2b00 cmp r3, #0 800276c: d0c3 beq.n 80026f6 <_vfiprintf_r+0x182> 800276e: 9209 str r2, [sp, #36] ; 0x24 8002770: e7c1 b.n 80026f6 <_vfiprintf_r+0x182> 8002772: 230a movs r3, #10 8002774: 435a muls r2, r3 8002776: 4667 mov r7, ip 8002778: 1852 adds r2, r2, r1 800277a: 3b09 subs r3, #9 800277c: e7ef b.n 800275e <_vfiprintf_r+0x1ea> 800277e: ab07 add r3, sp, #28 8002780: 9300 str r3, [sp, #0] 8002782: 0022 movs r2, r4 8002784: 0029 movs r1, r5 8002786: 0030 movs r0, r6 8002788: 4b16 ldr r3, [pc, #88] ; (80027e4 <_vfiprintf_r+0x270>) 800278a: e000 b.n 800278e <_vfiprintf_r+0x21a> 800278c: bf00 nop 800278e: 9004 str r0, [sp, #16] 8002790: 9b04 ldr r3, [sp, #16] 8002792: 3301 adds r3, #1 8002794: d1d1 bne.n 800273a <_vfiprintf_r+0x1c6> 8002796: 6e63 ldr r3, [r4, #100] ; 0x64 8002798: 07db lsls r3, r3, #31 800279a: d405 bmi.n 80027a8 <_vfiprintf_r+0x234> 800279c: 89a3 ldrh r3, [r4, #12] 800279e: 059b lsls r3, r3, #22 80027a0: d402 bmi.n 80027a8 <_vfiprintf_r+0x234> 80027a2: 6da0 ldr r0, [r4, #88] ; 0x58 80027a4: f000 fc5a bl 800305c <__retarget_lock_release_recursive> 80027a8: 89a3 ldrh r3, [r4, #12] 80027aa: 065b lsls r3, r3, #25 80027ac: d500 bpl.n 80027b0 <_vfiprintf_r+0x23c> 80027ae: e70a b.n 80025c6 <_vfiprintf_r+0x52> 80027b0: 980d ldr r0, [sp, #52] ; 0x34 80027b2: e70a b.n 80025ca <_vfiprintf_r+0x56> 80027b4: ab07 add r3, sp, #28 80027b6: 9300 str r3, [sp, #0] 80027b8: 0022 movs r2, r4 80027ba: 0029 movs r1, r5 80027bc: 0030 movs r0, r6 80027be: 4b09 ldr r3, [pc, #36] ; (80027e4 <_vfiprintf_r+0x270>) 80027c0: f000 f882 bl 80028c8 <_printf_i> 80027c4: e7e3 b.n 800278e <_vfiprintf_r+0x21a> 80027c6: 46c0 nop ; (mov r8, r8) 80027c8: 080034e8 .word 0x080034e8 80027cc: 08003508 .word 0x08003508 80027d0: 080034c8 .word 0x080034c8 80027d4: 08003492 .word 0x08003492 80027d8: 08003498 .word 0x08003498 80027dc: 0800349c .word 0x0800349c 80027e0: 00000000 .word 0x00000000 80027e4: 0800254f .word 0x0800254f 080027e8 <_printf_common>: 80027e8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80027ea: 0015 movs r5, r2 80027ec: 9301 str r3, [sp, #4] 80027ee: 688a ldr r2, [r1, #8] 80027f0: 690b ldr r3, [r1, #16] 80027f2: 000c movs r4, r1 80027f4: 9000 str r0, [sp, #0] 80027f6: 4293 cmp r3, r2 80027f8: da00 bge.n 80027fc <_printf_common+0x14> 80027fa: 0013 movs r3, r2 80027fc: 0022 movs r2, r4 80027fe: 602b str r3, [r5, #0] 8002800: 3243 adds r2, #67 ; 0x43 8002802: 7812 ldrb r2, [r2, #0] 8002804: 2a00 cmp r2, #0 8002806: d001 beq.n 800280c <_printf_common+0x24> 8002808: 3301 adds r3, #1 800280a: 602b str r3, [r5, #0] 800280c: 6823 ldr r3, [r4, #0] 800280e: 069b lsls r3, r3, #26 8002810: d502 bpl.n 8002818 <_printf_common+0x30> 8002812: 682b ldr r3, [r5, #0] 8002814: 3302 adds r3, #2 8002816: 602b str r3, [r5, #0] 8002818: 6822 ldr r2, [r4, #0] 800281a: 2306 movs r3, #6 800281c: 0017 movs r7, r2 800281e: 401f ands r7, r3 8002820: 421a tst r2, r3 8002822: d027 beq.n 8002874 <_printf_common+0x8c> 8002824: 0023 movs r3, r4 8002826: 3343 adds r3, #67 ; 0x43 8002828: 781b ldrb r3, [r3, #0] 800282a: 1e5a subs r2, r3, #1 800282c: 4193 sbcs r3, r2 800282e: 6822 ldr r2, [r4, #0] 8002830: 0692 lsls r2, r2, #26 8002832: d430 bmi.n 8002896 <_printf_common+0xae> 8002834: 0022 movs r2, r4 8002836: 9901 ldr r1, [sp, #4] 8002838: 9800 ldr r0, [sp, #0] 800283a: 9e08 ldr r6, [sp, #32] 800283c: 3243 adds r2, #67 ; 0x43 800283e: 47b0 blx r6 8002840: 1c43 adds r3, r0, #1 8002842: d025 beq.n 8002890 <_printf_common+0xa8> 8002844: 2306 movs r3, #6 8002846: 6820 ldr r0, [r4, #0] 8002848: 682a ldr r2, [r5, #0] 800284a: 68e1 ldr r1, [r4, #12] 800284c: 2500 movs r5, #0 800284e: 4003 ands r3, r0 8002850: 2b04 cmp r3, #4 8002852: d103 bne.n 800285c <_printf_common+0x74> 8002854: 1a8d subs r5, r1, r2 8002856: 43eb mvns r3, r5 8002858: 17db asrs r3, r3, #31 800285a: 401d ands r5, r3 800285c: 68a3 ldr r3, [r4, #8] 800285e: 6922 ldr r2, [r4, #16] 8002860: 4293 cmp r3, r2 8002862: dd01 ble.n 8002868 <_printf_common+0x80> 8002864: 1a9b subs r3, r3, r2 8002866: 18ed adds r5, r5, r3 8002868: 2700 movs r7, #0 800286a: 42bd cmp r5, r7 800286c: d120 bne.n 80028b0 <_printf_common+0xc8> 800286e: 2000 movs r0, #0 8002870: e010 b.n 8002894 <_printf_common+0xac> 8002872: 3701 adds r7, #1 8002874: 68e3 ldr r3, [r4, #12] 8002876: 682a ldr r2, [r5, #0] 8002878: 1a9b subs r3, r3, r2 800287a: 42bb cmp r3, r7 800287c: ddd2 ble.n 8002824 <_printf_common+0x3c> 800287e: 0022 movs r2, r4 8002880: 2301 movs r3, #1 8002882: 9901 ldr r1, [sp, #4] 8002884: 9800 ldr r0, [sp, #0] 8002886: 9e08 ldr r6, [sp, #32] 8002888: 3219 adds r2, #25 800288a: 47b0 blx r6 800288c: 1c43 adds r3, r0, #1 800288e: d1f0 bne.n 8002872 <_printf_common+0x8a> 8002890: 2001 movs r0, #1 8002892: 4240 negs r0, r0 8002894: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8002896: 2030 movs r0, #48 ; 0x30 8002898: 18e1 adds r1, r4, r3 800289a: 3143 adds r1, #67 ; 0x43 800289c: 7008 strb r0, [r1, #0] 800289e: 0021 movs r1, r4 80028a0: 1c5a adds r2, r3, #1 80028a2: 3145 adds r1, #69 ; 0x45 80028a4: 7809 ldrb r1, [r1, #0] 80028a6: 18a2 adds r2, r4, r2 80028a8: 3243 adds r2, #67 ; 0x43 80028aa: 3302 adds r3, #2 80028ac: 7011 strb r1, [r2, #0] 80028ae: e7c1 b.n 8002834 <_printf_common+0x4c> 80028b0: 0022 movs r2, r4 80028b2: 2301 movs r3, #1 80028b4: 9901 ldr r1, [sp, #4] 80028b6: 9800 ldr r0, [sp, #0] 80028b8: 9e08 ldr r6, [sp, #32] 80028ba: 321a adds r2, #26 80028bc: 47b0 blx r6 80028be: 1c43 adds r3, r0, #1 80028c0: d0e6 beq.n 8002890 <_printf_common+0xa8> 80028c2: 3701 adds r7, #1 80028c4: e7d1 b.n 800286a <_printf_common+0x82> ... 080028c8 <_printf_i>: 80028c8: b5f0 push {r4, r5, r6, r7, lr} 80028ca: b08b sub sp, #44 ; 0x2c 80028cc: 9206 str r2, [sp, #24] 80028ce: 000a movs r2, r1 80028d0: 3243 adds r2, #67 ; 0x43 80028d2: 9307 str r3, [sp, #28] 80028d4: 9005 str r0, [sp, #20] 80028d6: 9204 str r2, [sp, #16] 80028d8: 7e0a ldrb r2, [r1, #24] 80028da: 000c movs r4, r1 80028dc: 9b10 ldr r3, [sp, #64] ; 0x40 80028de: 2a78 cmp r2, #120 ; 0x78 80028e0: d806 bhi.n 80028f0 <_printf_i+0x28> 80028e2: 2a62 cmp r2, #98 ; 0x62 80028e4: d808 bhi.n 80028f8 <_printf_i+0x30> 80028e6: 2a00 cmp r2, #0 80028e8: d100 bne.n 80028ec <_printf_i+0x24> 80028ea: e0c0 b.n 8002a6e <_printf_i+0x1a6> 80028ec: 2a58 cmp r2, #88 ; 0x58 80028ee: d052 beq.n 8002996 <_printf_i+0xce> 80028f0: 0026 movs r6, r4 80028f2: 3642 adds r6, #66 ; 0x42 80028f4: 7032 strb r2, [r6, #0] 80028f6: e022 b.n 800293e <_printf_i+0x76> 80028f8: 0010 movs r0, r2 80028fa: 3863 subs r0, #99 ; 0x63 80028fc: 2815 cmp r0, #21 80028fe: d8f7 bhi.n 80028f0 <_printf_i+0x28> 8002900: f7fd fc02 bl 8000108 <__gnu_thumb1_case_shi> 8002904: 001f0016 .word 0x001f0016 8002908: fff6fff6 .word 0xfff6fff6 800290c: fff6fff6 .word 0xfff6fff6 8002910: fff6001f .word 0xfff6001f 8002914: fff6fff6 .word 0xfff6fff6 8002918: 00a8fff6 .word 0x00a8fff6 800291c: 009a0036 .word 0x009a0036 8002920: fff6fff6 .word 0xfff6fff6 8002924: fff600b9 .word 0xfff600b9 8002928: fff60036 .word 0xfff60036 800292c: 009efff6 .word 0x009efff6 8002930: 0026 movs r6, r4 8002932: 681a ldr r2, [r3, #0] 8002934: 3642 adds r6, #66 ; 0x42 8002936: 1d11 adds r1, r2, #4 8002938: 6019 str r1, [r3, #0] 800293a: 6813 ldr r3, [r2, #0] 800293c: 7033 strb r3, [r6, #0] 800293e: 2301 movs r3, #1 8002940: e0a7 b.n 8002a92 <_printf_i+0x1ca> 8002942: 6808 ldr r0, [r1, #0] 8002944: 6819 ldr r1, [r3, #0] 8002946: 1d0a adds r2, r1, #4 8002948: 0605 lsls r5, r0, #24 800294a: d50b bpl.n 8002964 <_printf_i+0x9c> 800294c: 680d ldr r5, [r1, #0] 800294e: 601a str r2, [r3, #0] 8002950: 2d00 cmp r5, #0 8002952: da03 bge.n 800295c <_printf_i+0x94> 8002954: 232d movs r3, #45 ; 0x2d 8002956: 9a04 ldr r2, [sp, #16] 8002958: 426d negs r5, r5 800295a: 7013 strb r3, [r2, #0] 800295c: 4b61 ldr r3, [pc, #388] ; (8002ae4 <_printf_i+0x21c>) 800295e: 270a movs r7, #10 8002960: 9303 str r3, [sp, #12] 8002962: e032 b.n 80029ca <_printf_i+0x102> 8002964: 680d ldr r5, [r1, #0] 8002966: 601a str r2, [r3, #0] 8002968: 0641 lsls r1, r0, #25 800296a: d5f1 bpl.n 8002950 <_printf_i+0x88> 800296c: b22d sxth r5, r5 800296e: e7ef b.n 8002950 <_printf_i+0x88> 8002970: 680d ldr r5, [r1, #0] 8002972: 6819 ldr r1, [r3, #0] 8002974: 1d08 adds r0, r1, #4 8002976: 6018 str r0, [r3, #0] 8002978: 062e lsls r6, r5, #24 800297a: d501 bpl.n 8002980 <_printf_i+0xb8> 800297c: 680d ldr r5, [r1, #0] 800297e: e003 b.n 8002988 <_printf_i+0xc0> 8002980: 066d lsls r5, r5, #25 8002982: d5fb bpl.n 800297c <_printf_i+0xb4> 8002984: 680d ldr r5, [r1, #0] 8002986: b2ad uxth r5, r5 8002988: 4b56 ldr r3, [pc, #344] ; (8002ae4 <_printf_i+0x21c>) 800298a: 270a movs r7, #10 800298c: 9303 str r3, [sp, #12] 800298e: 2a6f cmp r2, #111 ; 0x6f 8002990: d117 bne.n 80029c2 <_printf_i+0xfa> 8002992: 2708 movs r7, #8 8002994: e015 b.n 80029c2 <_printf_i+0xfa> 8002996: 3145 adds r1, #69 ; 0x45 8002998: 700a strb r2, [r1, #0] 800299a: 4a52 ldr r2, [pc, #328] ; (8002ae4 <_printf_i+0x21c>) 800299c: 9203 str r2, [sp, #12] 800299e: 681a ldr r2, [r3, #0] 80029a0: 6821 ldr r1, [r4, #0] 80029a2: ca20 ldmia r2!, {r5} 80029a4: 601a str r2, [r3, #0] 80029a6: 0608 lsls r0, r1, #24 80029a8: d550 bpl.n 8002a4c <_printf_i+0x184> 80029aa: 07cb lsls r3, r1, #31 80029ac: d502 bpl.n 80029b4 <_printf_i+0xec> 80029ae: 2320 movs r3, #32 80029b0: 4319 orrs r1, r3 80029b2: 6021 str r1, [r4, #0] 80029b4: 2710 movs r7, #16 80029b6: 2d00 cmp r5, #0 80029b8: d103 bne.n 80029c2 <_printf_i+0xfa> 80029ba: 2320 movs r3, #32 80029bc: 6822 ldr r2, [r4, #0] 80029be: 439a bics r2, r3 80029c0: 6022 str r2, [r4, #0] 80029c2: 0023 movs r3, r4 80029c4: 2200 movs r2, #0 80029c6: 3343 adds r3, #67 ; 0x43 80029c8: 701a strb r2, [r3, #0] 80029ca: 6863 ldr r3, [r4, #4] 80029cc: 60a3 str r3, [r4, #8] 80029ce: 2b00 cmp r3, #0 80029d0: db03 blt.n 80029da <_printf_i+0x112> 80029d2: 2204 movs r2, #4 80029d4: 6821 ldr r1, [r4, #0] 80029d6: 4391 bics r1, r2 80029d8: 6021 str r1, [r4, #0] 80029da: 2d00 cmp r5, #0 80029dc: d102 bne.n 80029e4 <_printf_i+0x11c> 80029de: 9e04 ldr r6, [sp, #16] 80029e0: 2b00 cmp r3, #0 80029e2: d00c beq.n 80029fe <_printf_i+0x136> 80029e4: 9e04 ldr r6, [sp, #16] 80029e6: 0028 movs r0, r5 80029e8: 0039 movs r1, r7 80029ea: f7fd fc1d bl 8000228 <__aeabi_uidivmod> 80029ee: 9b03 ldr r3, [sp, #12] 80029f0: 3e01 subs r6, #1 80029f2: 5c5b ldrb r3, [r3, r1] 80029f4: 7033 strb r3, [r6, #0] 80029f6: 002b movs r3, r5 80029f8: 0005 movs r5, r0 80029fa: 429f cmp r7, r3 80029fc: d9f3 bls.n 80029e6 <_printf_i+0x11e> 80029fe: 2f08 cmp r7, #8 8002a00: d109 bne.n 8002a16 <_printf_i+0x14e> 8002a02: 6823 ldr r3, [r4, #0] 8002a04: 07db lsls r3, r3, #31 8002a06: d506 bpl.n 8002a16 <_printf_i+0x14e> 8002a08: 6863 ldr r3, [r4, #4] 8002a0a: 6922 ldr r2, [r4, #16] 8002a0c: 4293 cmp r3, r2 8002a0e: dc02 bgt.n 8002a16 <_printf_i+0x14e> 8002a10: 2330 movs r3, #48 ; 0x30 8002a12: 3e01 subs r6, #1 8002a14: 7033 strb r3, [r6, #0] 8002a16: 9b04 ldr r3, [sp, #16] 8002a18: 1b9b subs r3, r3, r6 8002a1a: 6123 str r3, [r4, #16] 8002a1c: 9b07 ldr r3, [sp, #28] 8002a1e: 0021 movs r1, r4 8002a20: 9300 str r3, [sp, #0] 8002a22: 9805 ldr r0, [sp, #20] 8002a24: 9b06 ldr r3, [sp, #24] 8002a26: aa09 add r2, sp, #36 ; 0x24 8002a28: f7ff fede bl 80027e8 <_printf_common> 8002a2c: 1c43 adds r3, r0, #1 8002a2e: d135 bne.n 8002a9c <_printf_i+0x1d4> 8002a30: 2001 movs r0, #1 8002a32: 4240 negs r0, r0 8002a34: b00b add sp, #44 ; 0x2c 8002a36: bdf0 pop {r4, r5, r6, r7, pc} 8002a38: 2220 movs r2, #32 8002a3a: 6809 ldr r1, [r1, #0] 8002a3c: 430a orrs r2, r1 8002a3e: 6022 str r2, [r4, #0] 8002a40: 0022 movs r2, r4 8002a42: 2178 movs r1, #120 ; 0x78 8002a44: 3245 adds r2, #69 ; 0x45 8002a46: 7011 strb r1, [r2, #0] 8002a48: 4a27 ldr r2, [pc, #156] ; (8002ae8 <_printf_i+0x220>) 8002a4a: e7a7 b.n 800299c <_printf_i+0xd4> 8002a4c: 0648 lsls r0, r1, #25 8002a4e: d5ac bpl.n 80029aa <_printf_i+0xe2> 8002a50: b2ad uxth r5, r5 8002a52: e7aa b.n 80029aa <_printf_i+0xe2> 8002a54: 681a ldr r2, [r3, #0] 8002a56: 680d ldr r5, [r1, #0] 8002a58: 1d10 adds r0, r2, #4 8002a5a: 6949 ldr r1, [r1, #20] 8002a5c: 6018 str r0, [r3, #0] 8002a5e: 6813 ldr r3, [r2, #0] 8002a60: 062e lsls r6, r5, #24 8002a62: d501 bpl.n 8002a68 <_printf_i+0x1a0> 8002a64: 6019 str r1, [r3, #0] 8002a66: e002 b.n 8002a6e <_printf_i+0x1a6> 8002a68: 066d lsls r5, r5, #25 8002a6a: d5fb bpl.n 8002a64 <_printf_i+0x19c> 8002a6c: 8019 strh r1, [r3, #0] 8002a6e: 2300 movs r3, #0 8002a70: 9e04 ldr r6, [sp, #16] 8002a72: 6123 str r3, [r4, #16] 8002a74: e7d2 b.n 8002a1c <_printf_i+0x154> 8002a76: 681a ldr r2, [r3, #0] 8002a78: 1d11 adds r1, r2, #4 8002a7a: 6019 str r1, [r3, #0] 8002a7c: 6816 ldr r6, [r2, #0] 8002a7e: 2100 movs r1, #0 8002a80: 0030 movs r0, r6 8002a82: 6862 ldr r2, [r4, #4] 8002a84: f000 fb58 bl 8003138 8002a88: 2800 cmp r0, #0 8002a8a: d001 beq.n 8002a90 <_printf_i+0x1c8> 8002a8c: 1b80 subs r0, r0, r6 8002a8e: 6060 str r0, [r4, #4] 8002a90: 6863 ldr r3, [r4, #4] 8002a92: 6123 str r3, [r4, #16] 8002a94: 2300 movs r3, #0 8002a96: 9a04 ldr r2, [sp, #16] 8002a98: 7013 strb r3, [r2, #0] 8002a9a: e7bf b.n 8002a1c <_printf_i+0x154> 8002a9c: 6923 ldr r3, [r4, #16] 8002a9e: 0032 movs r2, r6 8002aa0: 9906 ldr r1, [sp, #24] 8002aa2: 9805 ldr r0, [sp, #20] 8002aa4: 9d07 ldr r5, [sp, #28] 8002aa6: 47a8 blx r5 8002aa8: 1c43 adds r3, r0, #1 8002aaa: d0c1 beq.n 8002a30 <_printf_i+0x168> 8002aac: 6823 ldr r3, [r4, #0] 8002aae: 079b lsls r3, r3, #30 8002ab0: d415 bmi.n 8002ade <_printf_i+0x216> 8002ab2: 9b09 ldr r3, [sp, #36] ; 0x24 8002ab4: 68e0 ldr r0, [r4, #12] 8002ab6: 4298 cmp r0, r3 8002ab8: dabc bge.n 8002a34 <_printf_i+0x16c> 8002aba: 0018 movs r0, r3 8002abc: e7ba b.n 8002a34 <_printf_i+0x16c> 8002abe: 0022 movs r2, r4 8002ac0: 2301 movs r3, #1 8002ac2: 9906 ldr r1, [sp, #24] 8002ac4: 9805 ldr r0, [sp, #20] 8002ac6: 9e07 ldr r6, [sp, #28] 8002ac8: 3219 adds r2, #25 8002aca: 47b0 blx r6 8002acc: 1c43 adds r3, r0, #1 8002ace: d0af beq.n 8002a30 <_printf_i+0x168> 8002ad0: 3501 adds r5, #1 8002ad2: 68e3 ldr r3, [r4, #12] 8002ad4: 9a09 ldr r2, [sp, #36] ; 0x24 8002ad6: 1a9b subs r3, r3, r2 8002ad8: 42ab cmp r3, r5 8002ada: dcf0 bgt.n 8002abe <_printf_i+0x1f6> 8002adc: e7e9 b.n 8002ab2 <_printf_i+0x1ea> 8002ade: 2500 movs r5, #0 8002ae0: e7f7 b.n 8002ad2 <_printf_i+0x20a> 8002ae2: 46c0 nop ; (mov r8, r8) 8002ae4: 080034a3 .word 0x080034a3 8002ae8: 080034b4 .word 0x080034b4 08002aec <_sbrk_r>: 8002aec: 2300 movs r3, #0 8002aee: b570 push {r4, r5, r6, lr} 8002af0: 4d06 ldr r5, [pc, #24] ; (8002b0c <_sbrk_r+0x20>) 8002af2: 0004 movs r4, r0 8002af4: 0008 movs r0, r1 8002af6: 602b str r3, [r5, #0] 8002af8: f7fd feea bl 80008d0 <_sbrk> 8002afc: 1c43 adds r3, r0, #1 8002afe: d103 bne.n 8002b08 <_sbrk_r+0x1c> 8002b00: 682b ldr r3, [r5, #0] 8002b02: 2b00 cmp r3, #0 8002b04: d000 beq.n 8002b08 <_sbrk_r+0x1c> 8002b06: 6023 str r3, [r4, #0] 8002b08: bd70 pop {r4, r5, r6, pc} 8002b0a: 46c0 nop ; (mov r8, r8) 8002b0c: 20000120 .word 0x20000120 08002b10 <__swbuf_r>: 8002b10: b5f8 push {r3, r4, r5, r6, r7, lr} 8002b12: 0005 movs r5, r0 8002b14: 000e movs r6, r1 8002b16: 0014 movs r4, r2 8002b18: 2800 cmp r0, #0 8002b1a: d004 beq.n 8002b26 <__swbuf_r+0x16> 8002b1c: 6983 ldr r3, [r0, #24] 8002b1e: 2b00 cmp r3, #0 8002b20: d101 bne.n 8002b26 <__swbuf_r+0x16> 8002b22: f000 f9f9 bl 8002f18 <__sinit> 8002b26: 4b22 ldr r3, [pc, #136] ; (8002bb0 <__swbuf_r+0xa0>) 8002b28: 429c cmp r4, r3 8002b2a: d12e bne.n 8002b8a <__swbuf_r+0x7a> 8002b2c: 686c ldr r4, [r5, #4] 8002b2e: 69a3 ldr r3, [r4, #24] 8002b30: 60a3 str r3, [r4, #8] 8002b32: 89a3 ldrh r3, [r4, #12] 8002b34: 071b lsls r3, r3, #28 8002b36: d532 bpl.n 8002b9e <__swbuf_r+0x8e> 8002b38: 6923 ldr r3, [r4, #16] 8002b3a: 2b00 cmp r3, #0 8002b3c: d02f beq.n 8002b9e <__swbuf_r+0x8e> 8002b3e: 6823 ldr r3, [r4, #0] 8002b40: 6922 ldr r2, [r4, #16] 8002b42: b2f7 uxtb r7, r6 8002b44: 1a98 subs r0, r3, r2 8002b46: 6963 ldr r3, [r4, #20] 8002b48: b2f6 uxtb r6, r6 8002b4a: 4283 cmp r3, r0 8002b4c: dc05 bgt.n 8002b5a <__swbuf_r+0x4a> 8002b4e: 0021 movs r1, r4 8002b50: 0028 movs r0, r5 8002b52: f000 f93f bl 8002dd4 <_fflush_r> 8002b56: 2800 cmp r0, #0 8002b58: d127 bne.n 8002baa <__swbuf_r+0x9a> 8002b5a: 68a3 ldr r3, [r4, #8] 8002b5c: 3001 adds r0, #1 8002b5e: 3b01 subs r3, #1 8002b60: 60a3 str r3, [r4, #8] 8002b62: 6823 ldr r3, [r4, #0] 8002b64: 1c5a adds r2, r3, #1 8002b66: 6022 str r2, [r4, #0] 8002b68: 701f strb r7, [r3, #0] 8002b6a: 6963 ldr r3, [r4, #20] 8002b6c: 4283 cmp r3, r0 8002b6e: d004 beq.n 8002b7a <__swbuf_r+0x6a> 8002b70: 89a3 ldrh r3, [r4, #12] 8002b72: 07db lsls r3, r3, #31 8002b74: d507 bpl.n 8002b86 <__swbuf_r+0x76> 8002b76: 2e0a cmp r6, #10 8002b78: d105 bne.n 8002b86 <__swbuf_r+0x76> 8002b7a: 0021 movs r1, r4 8002b7c: 0028 movs r0, r5 8002b7e: f000 f929 bl 8002dd4 <_fflush_r> 8002b82: 2800 cmp r0, #0 8002b84: d111 bne.n 8002baa <__swbuf_r+0x9a> 8002b86: 0030 movs r0, r6 8002b88: bdf8 pop {r3, r4, r5, r6, r7, pc} 8002b8a: 4b0a ldr r3, [pc, #40] ; (8002bb4 <__swbuf_r+0xa4>) 8002b8c: 429c cmp r4, r3 8002b8e: d101 bne.n 8002b94 <__swbuf_r+0x84> 8002b90: 68ac ldr r4, [r5, #8] 8002b92: e7cc b.n 8002b2e <__swbuf_r+0x1e> 8002b94: 4b08 ldr r3, [pc, #32] ; (8002bb8 <__swbuf_r+0xa8>) 8002b96: 429c cmp r4, r3 8002b98: d1c9 bne.n 8002b2e <__swbuf_r+0x1e> 8002b9a: 68ec ldr r4, [r5, #12] 8002b9c: e7c7 b.n 8002b2e <__swbuf_r+0x1e> 8002b9e: 0021 movs r1, r4 8002ba0: 0028 movs r0, r5 8002ba2: f000 f80b bl 8002bbc <__swsetup_r> 8002ba6: 2800 cmp r0, #0 8002ba8: d0c9 beq.n 8002b3e <__swbuf_r+0x2e> 8002baa: 2601 movs r6, #1 8002bac: 4276 negs r6, r6 8002bae: e7ea b.n 8002b86 <__swbuf_r+0x76> 8002bb0: 080034e8 .word 0x080034e8 8002bb4: 08003508 .word 0x08003508 8002bb8: 080034c8 .word 0x080034c8 08002bbc <__swsetup_r>: 8002bbc: 4b37 ldr r3, [pc, #220] ; (8002c9c <__swsetup_r+0xe0>) 8002bbe: b570 push {r4, r5, r6, lr} 8002bc0: 681d ldr r5, [r3, #0] 8002bc2: 0006 movs r6, r0 8002bc4: 000c movs r4, r1 8002bc6: 2d00 cmp r5, #0 8002bc8: d005 beq.n 8002bd6 <__swsetup_r+0x1a> 8002bca: 69ab ldr r3, [r5, #24] 8002bcc: 2b00 cmp r3, #0 8002bce: d102 bne.n 8002bd6 <__swsetup_r+0x1a> 8002bd0: 0028 movs r0, r5 8002bd2: f000 f9a1 bl 8002f18 <__sinit> 8002bd6: 4b32 ldr r3, [pc, #200] ; (8002ca0 <__swsetup_r+0xe4>) 8002bd8: 429c cmp r4, r3 8002bda: d10f bne.n 8002bfc <__swsetup_r+0x40> 8002bdc: 686c ldr r4, [r5, #4] 8002bde: 230c movs r3, #12 8002be0: 5ee2 ldrsh r2, [r4, r3] 8002be2: b293 uxth r3, r2 8002be4: 0711 lsls r1, r2, #28 8002be6: d42d bmi.n 8002c44 <__swsetup_r+0x88> 8002be8: 06d9 lsls r1, r3, #27 8002bea: d411 bmi.n 8002c10 <__swsetup_r+0x54> 8002bec: 2309 movs r3, #9 8002bee: 2001 movs r0, #1 8002bf0: 6033 str r3, [r6, #0] 8002bf2: 3337 adds r3, #55 ; 0x37 8002bf4: 4313 orrs r3, r2 8002bf6: 81a3 strh r3, [r4, #12] 8002bf8: 4240 negs r0, r0 8002bfa: bd70 pop {r4, r5, r6, pc} 8002bfc: 4b29 ldr r3, [pc, #164] ; (8002ca4 <__swsetup_r+0xe8>) 8002bfe: 429c cmp r4, r3 8002c00: d101 bne.n 8002c06 <__swsetup_r+0x4a> 8002c02: 68ac ldr r4, [r5, #8] 8002c04: e7eb b.n 8002bde <__swsetup_r+0x22> 8002c06: 4b28 ldr r3, [pc, #160] ; (8002ca8 <__swsetup_r+0xec>) 8002c08: 429c cmp r4, r3 8002c0a: d1e8 bne.n 8002bde <__swsetup_r+0x22> 8002c0c: 68ec ldr r4, [r5, #12] 8002c0e: e7e6 b.n 8002bde <__swsetup_r+0x22> 8002c10: 075b lsls r3, r3, #29 8002c12: d513 bpl.n 8002c3c <__swsetup_r+0x80> 8002c14: 6b61 ldr r1, [r4, #52] ; 0x34 8002c16: 2900 cmp r1, #0 8002c18: d008 beq.n 8002c2c <__swsetup_r+0x70> 8002c1a: 0023 movs r3, r4 8002c1c: 3344 adds r3, #68 ; 0x44 8002c1e: 4299 cmp r1, r3 8002c20: d002 beq.n 8002c28 <__swsetup_r+0x6c> 8002c22: 0030 movs r0, r6 8002c24: f7ff fbd6 bl 80023d4 <_free_r> 8002c28: 2300 movs r3, #0 8002c2a: 6363 str r3, [r4, #52] ; 0x34 8002c2c: 2224 movs r2, #36 ; 0x24 8002c2e: 89a3 ldrh r3, [r4, #12] 8002c30: 4393 bics r3, r2 8002c32: 81a3 strh r3, [r4, #12] 8002c34: 2300 movs r3, #0 8002c36: 6063 str r3, [r4, #4] 8002c38: 6923 ldr r3, [r4, #16] 8002c3a: 6023 str r3, [r4, #0] 8002c3c: 2308 movs r3, #8 8002c3e: 89a2 ldrh r2, [r4, #12] 8002c40: 4313 orrs r3, r2 8002c42: 81a3 strh r3, [r4, #12] 8002c44: 6923 ldr r3, [r4, #16] 8002c46: 2b00 cmp r3, #0 8002c48: d10b bne.n 8002c62 <__swsetup_r+0xa6> 8002c4a: 21a0 movs r1, #160 ; 0xa0 8002c4c: 2280 movs r2, #128 ; 0x80 8002c4e: 89a3 ldrh r3, [r4, #12] 8002c50: 0089 lsls r1, r1, #2 8002c52: 0092 lsls r2, r2, #2 8002c54: 400b ands r3, r1 8002c56: 4293 cmp r3, r2 8002c58: d003 beq.n 8002c62 <__swsetup_r+0xa6> 8002c5a: 0021 movs r1, r4 8002c5c: 0030 movs r0, r6 8002c5e: f000 fa27 bl 80030b0 <__smakebuf_r> 8002c62: 220c movs r2, #12 8002c64: 5ea3 ldrsh r3, [r4, r2] 8002c66: 2001 movs r0, #1 8002c68: 001a movs r2, r3 8002c6a: b299 uxth r1, r3 8002c6c: 4002 ands r2, r0 8002c6e: 4203 tst r3, r0 8002c70: d00f beq.n 8002c92 <__swsetup_r+0xd6> 8002c72: 2200 movs r2, #0 8002c74: 60a2 str r2, [r4, #8] 8002c76: 6962 ldr r2, [r4, #20] 8002c78: 4252 negs r2, r2 8002c7a: 61a2 str r2, [r4, #24] 8002c7c: 2000 movs r0, #0 8002c7e: 6922 ldr r2, [r4, #16] 8002c80: 4282 cmp r2, r0 8002c82: d1ba bne.n 8002bfa <__swsetup_r+0x3e> 8002c84: 060a lsls r2, r1, #24 8002c86: d5b8 bpl.n 8002bfa <__swsetup_r+0x3e> 8002c88: 2240 movs r2, #64 ; 0x40 8002c8a: 4313 orrs r3, r2 8002c8c: 81a3 strh r3, [r4, #12] 8002c8e: 3801 subs r0, #1 8002c90: e7b3 b.n 8002bfa <__swsetup_r+0x3e> 8002c92: 0788 lsls r0, r1, #30 8002c94: d400 bmi.n 8002c98 <__swsetup_r+0xdc> 8002c96: 6962 ldr r2, [r4, #20] 8002c98: 60a2 str r2, [r4, #8] 8002c9a: e7ef b.n 8002c7c <__swsetup_r+0xc0> 8002c9c: 2000000c .word 0x2000000c 8002ca0: 080034e8 .word 0x080034e8 8002ca4: 08003508 .word 0x08003508 8002ca8: 080034c8 .word 0x080034c8 08002cac : 8002cac: 2006 movs r0, #6 8002cae: b510 push {r4, lr} 8002cb0: f000 fa88 bl 80031c4 8002cb4: 2001 movs r0, #1 8002cb6: f7fd fd9a bl 80007ee <_exit> ... 08002cbc <__sflush_r>: 8002cbc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8002cbe: 898b ldrh r3, [r1, #12] 8002cc0: 0005 movs r5, r0 8002cc2: 000c movs r4, r1 8002cc4: 071a lsls r2, r3, #28 8002cc6: d45f bmi.n 8002d88 <__sflush_r+0xcc> 8002cc8: 684a ldr r2, [r1, #4] 8002cca: 2a00 cmp r2, #0 8002ccc: dc04 bgt.n 8002cd8 <__sflush_r+0x1c> 8002cce: 6c0a ldr r2, [r1, #64] ; 0x40 8002cd0: 2a00 cmp r2, #0 8002cd2: dc01 bgt.n 8002cd8 <__sflush_r+0x1c> 8002cd4: 2000 movs r0, #0 8002cd6: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8002cd8: 6ae7 ldr r7, [r4, #44] ; 0x2c 8002cda: 2f00 cmp r7, #0 8002cdc: d0fa beq.n 8002cd4 <__sflush_r+0x18> 8002cde: 2200 movs r2, #0 8002ce0: 2180 movs r1, #128 ; 0x80 8002ce2: 682e ldr r6, [r5, #0] 8002ce4: 602a str r2, [r5, #0] 8002ce6: 001a movs r2, r3 8002ce8: 0149 lsls r1, r1, #5 8002cea: 400a ands r2, r1 8002cec: 420b tst r3, r1 8002cee: d034 beq.n 8002d5a <__sflush_r+0x9e> 8002cf0: 6d60 ldr r0, [r4, #84] ; 0x54 8002cf2: 89a3 ldrh r3, [r4, #12] 8002cf4: 075b lsls r3, r3, #29 8002cf6: d506 bpl.n 8002d06 <__sflush_r+0x4a> 8002cf8: 6863 ldr r3, [r4, #4] 8002cfa: 1ac0 subs r0, r0, r3 8002cfc: 6b63 ldr r3, [r4, #52] ; 0x34 8002cfe: 2b00 cmp r3, #0 8002d00: d001 beq.n 8002d06 <__sflush_r+0x4a> 8002d02: 6c23 ldr r3, [r4, #64] ; 0x40 8002d04: 1ac0 subs r0, r0, r3 8002d06: 0002 movs r2, r0 8002d08: 6a21 ldr r1, [r4, #32] 8002d0a: 2300 movs r3, #0 8002d0c: 0028 movs r0, r5 8002d0e: 6ae7 ldr r7, [r4, #44] ; 0x2c 8002d10: 47b8 blx r7 8002d12: 89a1 ldrh r1, [r4, #12] 8002d14: 1c43 adds r3, r0, #1 8002d16: d106 bne.n 8002d26 <__sflush_r+0x6a> 8002d18: 682b ldr r3, [r5, #0] 8002d1a: 2b1d cmp r3, #29 8002d1c: d831 bhi.n 8002d82 <__sflush_r+0xc6> 8002d1e: 4a2c ldr r2, [pc, #176] ; (8002dd0 <__sflush_r+0x114>) 8002d20: 40da lsrs r2, r3 8002d22: 07d3 lsls r3, r2, #31 8002d24: d52d bpl.n 8002d82 <__sflush_r+0xc6> 8002d26: 2300 movs r3, #0 8002d28: 6063 str r3, [r4, #4] 8002d2a: 6923 ldr r3, [r4, #16] 8002d2c: 6023 str r3, [r4, #0] 8002d2e: 04cb lsls r3, r1, #19 8002d30: d505 bpl.n 8002d3e <__sflush_r+0x82> 8002d32: 1c43 adds r3, r0, #1 8002d34: d102 bne.n 8002d3c <__sflush_r+0x80> 8002d36: 682b ldr r3, [r5, #0] 8002d38: 2b00 cmp r3, #0 8002d3a: d100 bne.n 8002d3e <__sflush_r+0x82> 8002d3c: 6560 str r0, [r4, #84] ; 0x54 8002d3e: 6b61 ldr r1, [r4, #52] ; 0x34 8002d40: 602e str r6, [r5, #0] 8002d42: 2900 cmp r1, #0 8002d44: d0c6 beq.n 8002cd4 <__sflush_r+0x18> 8002d46: 0023 movs r3, r4 8002d48: 3344 adds r3, #68 ; 0x44 8002d4a: 4299 cmp r1, r3 8002d4c: d002 beq.n 8002d54 <__sflush_r+0x98> 8002d4e: 0028 movs r0, r5 8002d50: f7ff fb40 bl 80023d4 <_free_r> 8002d54: 2000 movs r0, #0 8002d56: 6360 str r0, [r4, #52] ; 0x34 8002d58: e7bd b.n 8002cd6 <__sflush_r+0x1a> 8002d5a: 2301 movs r3, #1 8002d5c: 0028 movs r0, r5 8002d5e: 6a21 ldr r1, [r4, #32] 8002d60: 47b8 blx r7 8002d62: 1c43 adds r3, r0, #1 8002d64: d1c5 bne.n 8002cf2 <__sflush_r+0x36> 8002d66: 682b ldr r3, [r5, #0] 8002d68: 2b00 cmp r3, #0 8002d6a: d0c2 beq.n 8002cf2 <__sflush_r+0x36> 8002d6c: 2b1d cmp r3, #29 8002d6e: d001 beq.n 8002d74 <__sflush_r+0xb8> 8002d70: 2b16 cmp r3, #22 8002d72: d101 bne.n 8002d78 <__sflush_r+0xbc> 8002d74: 602e str r6, [r5, #0] 8002d76: e7ad b.n 8002cd4 <__sflush_r+0x18> 8002d78: 2340 movs r3, #64 ; 0x40 8002d7a: 89a2 ldrh r2, [r4, #12] 8002d7c: 4313 orrs r3, r2 8002d7e: 81a3 strh r3, [r4, #12] 8002d80: e7a9 b.n 8002cd6 <__sflush_r+0x1a> 8002d82: 2340 movs r3, #64 ; 0x40 8002d84: 430b orrs r3, r1 8002d86: e7fa b.n 8002d7e <__sflush_r+0xc2> 8002d88: 690f ldr r7, [r1, #16] 8002d8a: 2f00 cmp r7, #0 8002d8c: d0a2 beq.n 8002cd4 <__sflush_r+0x18> 8002d8e: 680a ldr r2, [r1, #0] 8002d90: 600f str r7, [r1, #0] 8002d92: 1bd2 subs r2, r2, r7 8002d94: 9201 str r2, [sp, #4] 8002d96: 2200 movs r2, #0 8002d98: 079b lsls r3, r3, #30 8002d9a: d100 bne.n 8002d9e <__sflush_r+0xe2> 8002d9c: 694a ldr r2, [r1, #20] 8002d9e: 60a2 str r2, [r4, #8] 8002da0: 9b01 ldr r3, [sp, #4] 8002da2: 2b00 cmp r3, #0 8002da4: dc00 bgt.n 8002da8 <__sflush_r+0xec> 8002da6: e795 b.n 8002cd4 <__sflush_r+0x18> 8002da8: 003a movs r2, r7 8002daa: 0028 movs r0, r5 8002dac: 9b01 ldr r3, [sp, #4] 8002dae: 6a21 ldr r1, [r4, #32] 8002db0: 6aa6 ldr r6, [r4, #40] ; 0x28 8002db2: 47b0 blx r6 8002db4: 2800 cmp r0, #0 8002db6: dc06 bgt.n 8002dc6 <__sflush_r+0x10a> 8002db8: 2340 movs r3, #64 ; 0x40 8002dba: 2001 movs r0, #1 8002dbc: 89a2 ldrh r2, [r4, #12] 8002dbe: 4240 negs r0, r0 8002dc0: 4313 orrs r3, r2 8002dc2: 81a3 strh r3, [r4, #12] 8002dc4: e787 b.n 8002cd6 <__sflush_r+0x1a> 8002dc6: 9b01 ldr r3, [sp, #4] 8002dc8: 183f adds r7, r7, r0 8002dca: 1a1b subs r3, r3, r0 8002dcc: 9301 str r3, [sp, #4] 8002dce: e7e7 b.n 8002da0 <__sflush_r+0xe4> 8002dd0: 20400001 .word 0x20400001 08002dd4 <_fflush_r>: 8002dd4: 690b ldr r3, [r1, #16] 8002dd6: b570 push {r4, r5, r6, lr} 8002dd8: 0005 movs r5, r0 8002dda: 000c movs r4, r1 8002ddc: 2b00 cmp r3, #0 8002dde: d102 bne.n 8002de6 <_fflush_r+0x12> 8002de0: 2500 movs r5, #0 8002de2: 0028 movs r0, r5 8002de4: bd70 pop {r4, r5, r6, pc} 8002de6: 2800 cmp r0, #0 8002de8: d004 beq.n 8002df4 <_fflush_r+0x20> 8002dea: 6983 ldr r3, [r0, #24] 8002dec: 2b00 cmp r3, #0 8002dee: d101 bne.n 8002df4 <_fflush_r+0x20> 8002df0: f000 f892 bl 8002f18 <__sinit> 8002df4: 4b14 ldr r3, [pc, #80] ; (8002e48 <_fflush_r+0x74>) 8002df6: 429c cmp r4, r3 8002df8: d11b bne.n 8002e32 <_fflush_r+0x5e> 8002dfa: 686c ldr r4, [r5, #4] 8002dfc: 220c movs r2, #12 8002dfe: 5ea3 ldrsh r3, [r4, r2] 8002e00: 2b00 cmp r3, #0 8002e02: d0ed beq.n 8002de0 <_fflush_r+0xc> 8002e04: 6e62 ldr r2, [r4, #100] ; 0x64 8002e06: 07d2 lsls r2, r2, #31 8002e08: d404 bmi.n 8002e14 <_fflush_r+0x40> 8002e0a: 059b lsls r3, r3, #22 8002e0c: d402 bmi.n 8002e14 <_fflush_r+0x40> 8002e0e: 6da0 ldr r0, [r4, #88] ; 0x58 8002e10: f000 f923 bl 800305a <__retarget_lock_acquire_recursive> 8002e14: 0028 movs r0, r5 8002e16: 0021 movs r1, r4 8002e18: f7ff ff50 bl 8002cbc <__sflush_r> 8002e1c: 6e63 ldr r3, [r4, #100] ; 0x64 8002e1e: 0005 movs r5, r0 8002e20: 07db lsls r3, r3, #31 8002e22: d4de bmi.n 8002de2 <_fflush_r+0xe> 8002e24: 89a3 ldrh r3, [r4, #12] 8002e26: 059b lsls r3, r3, #22 8002e28: d4db bmi.n 8002de2 <_fflush_r+0xe> 8002e2a: 6da0 ldr r0, [r4, #88] ; 0x58 8002e2c: f000 f916 bl 800305c <__retarget_lock_release_recursive> 8002e30: e7d7 b.n 8002de2 <_fflush_r+0xe> 8002e32: 4b06 ldr r3, [pc, #24] ; (8002e4c <_fflush_r+0x78>) 8002e34: 429c cmp r4, r3 8002e36: d101 bne.n 8002e3c <_fflush_r+0x68> 8002e38: 68ac ldr r4, [r5, #8] 8002e3a: e7df b.n 8002dfc <_fflush_r+0x28> 8002e3c: 4b04 ldr r3, [pc, #16] ; (8002e50 <_fflush_r+0x7c>) 8002e3e: 429c cmp r4, r3 8002e40: d1dc bne.n 8002dfc <_fflush_r+0x28> 8002e42: 68ec ldr r4, [r5, #12] 8002e44: e7da b.n 8002dfc <_fflush_r+0x28> 8002e46: 46c0 nop ; (mov r8, r8) 8002e48: 080034e8 .word 0x080034e8 8002e4c: 08003508 .word 0x08003508 8002e50: 080034c8 .word 0x080034c8 08002e54 : 8002e54: 2300 movs r3, #0 8002e56: b510 push {r4, lr} 8002e58: 0004 movs r4, r0 8002e5a: 6003 str r3, [r0, #0] 8002e5c: 6043 str r3, [r0, #4] 8002e5e: 6083 str r3, [r0, #8] 8002e60: 8181 strh r1, [r0, #12] 8002e62: 6643 str r3, [r0, #100] ; 0x64 8002e64: 0019 movs r1, r3 8002e66: 81c2 strh r2, [r0, #14] 8002e68: 6103 str r3, [r0, #16] 8002e6a: 6143 str r3, [r0, #20] 8002e6c: 6183 str r3, [r0, #24] 8002e6e: 2208 movs r2, #8 8002e70: 305c adds r0, #92 ; 0x5c 8002e72: f7ff fa31 bl 80022d8 8002e76: 4b05 ldr r3, [pc, #20] ; (8002e8c ) 8002e78: 6263 str r3, [r4, #36] ; 0x24 8002e7a: 4b05 ldr r3, [pc, #20] ; (8002e90 ) 8002e7c: 6224 str r4, [r4, #32] 8002e7e: 62a3 str r3, [r4, #40] ; 0x28 8002e80: 4b04 ldr r3, [pc, #16] ; (8002e94 ) 8002e82: 62e3 str r3, [r4, #44] ; 0x2c 8002e84: 4b04 ldr r3, [pc, #16] ; (8002e98 ) 8002e86: 6323 str r3, [r4, #48] ; 0x30 8002e88: bd10 pop {r4, pc} 8002e8a: 46c0 nop ; (mov r8, r8) 8002e8c: 08003205 .word 0x08003205 8002e90: 0800322d .word 0x0800322d 8002e94: 08003265 .word 0x08003265 8002e98: 08003291 .word 0x08003291 08002e9c <_cleanup_r>: 8002e9c: b510 push {r4, lr} 8002e9e: 4902 ldr r1, [pc, #8] ; (8002ea8 <_cleanup_r+0xc>) 8002ea0: f000 f8ba bl 8003018 <_fwalk_reent> 8002ea4: bd10 pop {r4, pc} 8002ea6: 46c0 nop ; (mov r8, r8) 8002ea8: 08002dd5 .word 0x08002dd5 08002eac <__sfmoreglue>: 8002eac: b570 push {r4, r5, r6, lr} 8002eae: 2568 movs r5, #104 ; 0x68 8002eb0: 1e4a subs r2, r1, #1 8002eb2: 4355 muls r5, r2 8002eb4: 000e movs r6, r1 8002eb6: 0029 movs r1, r5 8002eb8: 3174 adds r1, #116 ; 0x74 8002eba: f7ff fad5 bl 8002468 <_malloc_r> 8002ebe: 1e04 subs r4, r0, #0 8002ec0: d008 beq.n 8002ed4 <__sfmoreglue+0x28> 8002ec2: 2100 movs r1, #0 8002ec4: 002a movs r2, r5 8002ec6: 6001 str r1, [r0, #0] 8002ec8: 6046 str r6, [r0, #4] 8002eca: 300c adds r0, #12 8002ecc: 60a0 str r0, [r4, #8] 8002ece: 3268 adds r2, #104 ; 0x68 8002ed0: f7ff fa02 bl 80022d8 8002ed4: 0020 movs r0, r4 8002ed6: bd70 pop {r4, r5, r6, pc} 08002ed8 <__sfp_lock_acquire>: 8002ed8: b510 push {r4, lr} 8002eda: 4802 ldr r0, [pc, #8] ; (8002ee4 <__sfp_lock_acquire+0xc>) 8002edc: f000 f8bd bl 800305a <__retarget_lock_acquire_recursive> 8002ee0: bd10 pop {r4, pc} 8002ee2: 46c0 nop ; (mov r8, r8) 8002ee4: 2000011c .word 0x2000011c 08002ee8 <__sfp_lock_release>: 8002ee8: b510 push {r4, lr} 8002eea: 4802 ldr r0, [pc, #8] ; (8002ef4 <__sfp_lock_release+0xc>) 8002eec: f000 f8b6 bl 800305c <__retarget_lock_release_recursive> 8002ef0: bd10 pop {r4, pc} 8002ef2: 46c0 nop ; (mov r8, r8) 8002ef4: 2000011c .word 0x2000011c 08002ef8 <__sinit_lock_acquire>: 8002ef8: b510 push {r4, lr} 8002efa: 4802 ldr r0, [pc, #8] ; (8002f04 <__sinit_lock_acquire+0xc>) 8002efc: f000 f8ad bl 800305a <__retarget_lock_acquire_recursive> 8002f00: bd10 pop {r4, pc} 8002f02: 46c0 nop ; (mov r8, r8) 8002f04: 20000117 .word 0x20000117 08002f08 <__sinit_lock_release>: 8002f08: b510 push {r4, lr} 8002f0a: 4802 ldr r0, [pc, #8] ; (8002f14 <__sinit_lock_release+0xc>) 8002f0c: f000 f8a6 bl 800305c <__retarget_lock_release_recursive> 8002f10: bd10 pop {r4, pc} 8002f12: 46c0 nop ; (mov r8, r8) 8002f14: 20000117 .word 0x20000117 08002f18 <__sinit>: 8002f18: b513 push {r0, r1, r4, lr} 8002f1a: 0004 movs r4, r0 8002f1c: f7ff ffec bl 8002ef8 <__sinit_lock_acquire> 8002f20: 69a3 ldr r3, [r4, #24] 8002f22: 2b00 cmp r3, #0 8002f24: d002 beq.n 8002f2c <__sinit+0x14> 8002f26: f7ff ffef bl 8002f08 <__sinit_lock_release> 8002f2a: bd13 pop {r0, r1, r4, pc} 8002f2c: 64a3 str r3, [r4, #72] ; 0x48 8002f2e: 64e3 str r3, [r4, #76] ; 0x4c 8002f30: 6523 str r3, [r4, #80] ; 0x50 8002f32: 4b13 ldr r3, [pc, #76] ; (8002f80 <__sinit+0x68>) 8002f34: 4a13 ldr r2, [pc, #76] ; (8002f84 <__sinit+0x6c>) 8002f36: 681b ldr r3, [r3, #0] 8002f38: 62a2 str r2, [r4, #40] ; 0x28 8002f3a: 9301 str r3, [sp, #4] 8002f3c: 42a3 cmp r3, r4 8002f3e: d101 bne.n 8002f44 <__sinit+0x2c> 8002f40: 2301 movs r3, #1 8002f42: 61a3 str r3, [r4, #24] 8002f44: 0020 movs r0, r4 8002f46: f000 f81f bl 8002f88 <__sfp> 8002f4a: 6060 str r0, [r4, #4] 8002f4c: 0020 movs r0, r4 8002f4e: f000 f81b bl 8002f88 <__sfp> 8002f52: 60a0 str r0, [r4, #8] 8002f54: 0020 movs r0, r4 8002f56: f000 f817 bl 8002f88 <__sfp> 8002f5a: 2200 movs r2, #0 8002f5c: 2104 movs r1, #4 8002f5e: 60e0 str r0, [r4, #12] 8002f60: 6860 ldr r0, [r4, #4] 8002f62: f7ff ff77 bl 8002e54 8002f66: 2201 movs r2, #1 8002f68: 2109 movs r1, #9 8002f6a: 68a0 ldr r0, [r4, #8] 8002f6c: f7ff ff72 bl 8002e54 8002f70: 2202 movs r2, #2 8002f72: 2112 movs r1, #18 8002f74: 68e0 ldr r0, [r4, #12] 8002f76: f7ff ff6d bl 8002e54 8002f7a: 2301 movs r3, #1 8002f7c: 61a3 str r3, [r4, #24] 8002f7e: e7d2 b.n 8002f26 <__sinit+0xe> 8002f80: 080033dc .word 0x080033dc 8002f84: 08002e9d .word 0x08002e9d 08002f88 <__sfp>: 8002f88: b5f8 push {r3, r4, r5, r6, r7, lr} 8002f8a: 0007 movs r7, r0 8002f8c: f7ff ffa4 bl 8002ed8 <__sfp_lock_acquire> 8002f90: 4b1f ldr r3, [pc, #124] ; (8003010 <__sfp+0x88>) 8002f92: 681e ldr r6, [r3, #0] 8002f94: 69b3 ldr r3, [r6, #24] 8002f96: 2b00 cmp r3, #0 8002f98: d102 bne.n 8002fa0 <__sfp+0x18> 8002f9a: 0030 movs r0, r6 8002f9c: f7ff ffbc bl 8002f18 <__sinit> 8002fa0: 3648 adds r6, #72 ; 0x48 8002fa2: 68b4 ldr r4, [r6, #8] 8002fa4: 6873 ldr r3, [r6, #4] 8002fa6: 3b01 subs r3, #1 8002fa8: d504 bpl.n 8002fb4 <__sfp+0x2c> 8002faa: 6833 ldr r3, [r6, #0] 8002fac: 2b00 cmp r3, #0 8002fae: d022 beq.n 8002ff6 <__sfp+0x6e> 8002fb0: 6836 ldr r6, [r6, #0] 8002fb2: e7f6 b.n 8002fa2 <__sfp+0x1a> 8002fb4: 220c movs r2, #12 8002fb6: 5ea5 ldrsh r5, [r4, r2] 8002fb8: 2d00 cmp r5, #0 8002fba: d11a bne.n 8002ff2 <__sfp+0x6a> 8002fbc: 0020 movs r0, r4 8002fbe: 4b15 ldr r3, [pc, #84] ; (8003014 <__sfp+0x8c>) 8002fc0: 3058 adds r0, #88 ; 0x58 8002fc2: 60e3 str r3, [r4, #12] 8002fc4: 6665 str r5, [r4, #100] ; 0x64 8002fc6: f000 f847 bl 8003058 <__retarget_lock_init_recursive> 8002fca: f7ff ff8d bl 8002ee8 <__sfp_lock_release> 8002fce: 0020 movs r0, r4 8002fd0: 2208 movs r2, #8 8002fd2: 0029 movs r1, r5 8002fd4: 6025 str r5, [r4, #0] 8002fd6: 60a5 str r5, [r4, #8] 8002fd8: 6065 str r5, [r4, #4] 8002fda: 6125 str r5, [r4, #16] 8002fdc: 6165 str r5, [r4, #20] 8002fde: 61a5 str r5, [r4, #24] 8002fe0: 305c adds r0, #92 ; 0x5c 8002fe2: f7ff f979 bl 80022d8 8002fe6: 6365 str r5, [r4, #52] ; 0x34 8002fe8: 63a5 str r5, [r4, #56] ; 0x38 8002fea: 64a5 str r5, [r4, #72] ; 0x48 8002fec: 64e5 str r5, [r4, #76] ; 0x4c 8002fee: 0020 movs r0, r4 8002ff0: bdf8 pop {r3, r4, r5, r6, r7, pc} 8002ff2: 3468 adds r4, #104 ; 0x68 8002ff4: e7d7 b.n 8002fa6 <__sfp+0x1e> 8002ff6: 2104 movs r1, #4 8002ff8: 0038 movs r0, r7 8002ffa: f7ff ff57 bl 8002eac <__sfmoreglue> 8002ffe: 1e04 subs r4, r0, #0 8003000: 6030 str r0, [r6, #0] 8003002: d1d5 bne.n 8002fb0 <__sfp+0x28> 8003004: f7ff ff70 bl 8002ee8 <__sfp_lock_release> 8003008: 230c movs r3, #12 800300a: 603b str r3, [r7, #0] 800300c: e7ef b.n 8002fee <__sfp+0x66> 800300e: 46c0 nop ; (mov r8, r8) 8003010: 080033dc .word 0x080033dc 8003014: ffff0001 .word 0xffff0001 08003018 <_fwalk_reent>: 8003018: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800301a: 0004 movs r4, r0 800301c: 0006 movs r6, r0 800301e: 2700 movs r7, #0 8003020: 9101 str r1, [sp, #4] 8003022: 3448 adds r4, #72 ; 0x48 8003024: 6863 ldr r3, [r4, #4] 8003026: 68a5 ldr r5, [r4, #8] 8003028: 9300 str r3, [sp, #0] 800302a: 9b00 ldr r3, [sp, #0] 800302c: 3b01 subs r3, #1 800302e: 9300 str r3, [sp, #0] 8003030: d504 bpl.n 800303c <_fwalk_reent+0x24> 8003032: 6824 ldr r4, [r4, #0] 8003034: 2c00 cmp r4, #0 8003036: d1f5 bne.n 8003024 <_fwalk_reent+0xc> 8003038: 0038 movs r0, r7 800303a: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 800303c: 89ab ldrh r3, [r5, #12] 800303e: 2b01 cmp r3, #1 8003040: d908 bls.n 8003054 <_fwalk_reent+0x3c> 8003042: 220e movs r2, #14 8003044: 5eab ldrsh r3, [r5, r2] 8003046: 3301 adds r3, #1 8003048: d004 beq.n 8003054 <_fwalk_reent+0x3c> 800304a: 0029 movs r1, r5 800304c: 0030 movs r0, r6 800304e: 9b01 ldr r3, [sp, #4] 8003050: 4798 blx r3 8003052: 4307 orrs r7, r0 8003054: 3568 adds r5, #104 ; 0x68 8003056: e7e8 b.n 800302a <_fwalk_reent+0x12> 08003058 <__retarget_lock_init_recursive>: 8003058: 4770 bx lr 0800305a <__retarget_lock_acquire_recursive>: 800305a: 4770 bx lr 0800305c <__retarget_lock_release_recursive>: 800305c: 4770 bx lr ... 08003060 <__swhatbuf_r>: 8003060: b570 push {r4, r5, r6, lr} 8003062: 000e movs r6, r1 8003064: 001d movs r5, r3 8003066: 230e movs r3, #14 8003068: 5ec9 ldrsh r1, [r1, r3] 800306a: 0014 movs r4, r2 800306c: b096 sub sp, #88 ; 0x58 800306e: 2900 cmp r1, #0 8003070: da07 bge.n 8003082 <__swhatbuf_r+0x22> 8003072: 2300 movs r3, #0 8003074: 602b str r3, [r5, #0] 8003076: 89b3 ldrh r3, [r6, #12] 8003078: 061b lsls r3, r3, #24 800307a: d411 bmi.n 80030a0 <__swhatbuf_r+0x40> 800307c: 2380 movs r3, #128 ; 0x80 800307e: 00db lsls r3, r3, #3 8003080: e00f b.n 80030a2 <__swhatbuf_r+0x42> 8003082: 466a mov r2, sp 8003084: f000 f930 bl 80032e8 <_fstat_r> 8003088: 2800 cmp r0, #0 800308a: dbf2 blt.n 8003072 <__swhatbuf_r+0x12> 800308c: 23f0 movs r3, #240 ; 0xf0 800308e: 9901 ldr r1, [sp, #4] 8003090: 021b lsls r3, r3, #8 8003092: 4019 ands r1, r3 8003094: 4b05 ldr r3, [pc, #20] ; (80030ac <__swhatbuf_r+0x4c>) 8003096: 18c9 adds r1, r1, r3 8003098: 424b negs r3, r1 800309a: 4159 adcs r1, r3 800309c: 6029 str r1, [r5, #0] 800309e: e7ed b.n 800307c <__swhatbuf_r+0x1c> 80030a0: 2340 movs r3, #64 ; 0x40 80030a2: 2000 movs r0, #0 80030a4: 6023 str r3, [r4, #0] 80030a6: b016 add sp, #88 ; 0x58 80030a8: bd70 pop {r4, r5, r6, pc} 80030aa: 46c0 nop ; (mov r8, r8) 80030ac: ffffe000 .word 0xffffe000 080030b0 <__smakebuf_r>: 80030b0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80030b2: 2602 movs r6, #2 80030b4: 898b ldrh r3, [r1, #12] 80030b6: 0005 movs r5, r0 80030b8: 000c movs r4, r1 80030ba: 4233 tst r3, r6 80030bc: d006 beq.n 80030cc <__smakebuf_r+0x1c> 80030be: 0023 movs r3, r4 80030c0: 3347 adds r3, #71 ; 0x47 80030c2: 6023 str r3, [r4, #0] 80030c4: 6123 str r3, [r4, #16] 80030c6: 2301 movs r3, #1 80030c8: 6163 str r3, [r4, #20] 80030ca: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc} 80030cc: 466a mov r2, sp 80030ce: ab01 add r3, sp, #4 80030d0: f7ff ffc6 bl 8003060 <__swhatbuf_r> 80030d4: 9900 ldr r1, [sp, #0] 80030d6: 0007 movs r7, r0 80030d8: 0028 movs r0, r5 80030da: f7ff f9c5 bl 8002468 <_malloc_r> 80030de: 2800 cmp r0, #0 80030e0: d108 bne.n 80030f4 <__smakebuf_r+0x44> 80030e2: 220c movs r2, #12 80030e4: 5ea3 ldrsh r3, [r4, r2] 80030e6: 059a lsls r2, r3, #22 80030e8: d4ef bmi.n 80030ca <__smakebuf_r+0x1a> 80030ea: 2203 movs r2, #3 80030ec: 4393 bics r3, r2 80030ee: 431e orrs r6, r3 80030f0: 81a6 strh r6, [r4, #12] 80030f2: e7e4 b.n 80030be <__smakebuf_r+0xe> 80030f4: 4b0f ldr r3, [pc, #60] ; (8003134 <__smakebuf_r+0x84>) 80030f6: 62ab str r3, [r5, #40] ; 0x28 80030f8: 2380 movs r3, #128 ; 0x80 80030fa: 89a2 ldrh r2, [r4, #12] 80030fc: 6020 str r0, [r4, #0] 80030fe: 4313 orrs r3, r2 8003100: 81a3 strh r3, [r4, #12] 8003102: 9b00 ldr r3, [sp, #0] 8003104: 6120 str r0, [r4, #16] 8003106: 6163 str r3, [r4, #20] 8003108: 9b01 ldr r3, [sp, #4] 800310a: 2b00 cmp r3, #0 800310c: d00d beq.n 800312a <__smakebuf_r+0x7a> 800310e: 0028 movs r0, r5 8003110: 230e movs r3, #14 8003112: 5ee1 ldrsh r1, [r4, r3] 8003114: f000 f8fa bl 800330c <_isatty_r> 8003118: 2800 cmp r0, #0 800311a: d006 beq.n 800312a <__smakebuf_r+0x7a> 800311c: 2203 movs r2, #3 800311e: 89a3 ldrh r3, [r4, #12] 8003120: 4393 bics r3, r2 8003122: 001a movs r2, r3 8003124: 2301 movs r3, #1 8003126: 4313 orrs r3, r2 8003128: 81a3 strh r3, [r4, #12] 800312a: 89a0 ldrh r0, [r4, #12] 800312c: 4307 orrs r7, r0 800312e: 81a7 strh r7, [r4, #12] 8003130: e7cb b.n 80030ca <__smakebuf_r+0x1a> 8003132: 46c0 nop ; (mov r8, r8) 8003134: 08002e9d .word 0x08002e9d 08003138 : 8003138: b2c9 uxtb r1, r1 800313a: 1882 adds r2, r0, r2 800313c: 4290 cmp r0, r2 800313e: d101 bne.n 8003144 8003140: 2000 movs r0, #0 8003142: 4770 bx lr 8003144: 7803 ldrb r3, [r0, #0] 8003146: 428b cmp r3, r1 8003148: d0fb beq.n 8003142 800314a: 3001 adds r0, #1 800314c: e7f6 b.n 800313c ... 08003150 <__malloc_lock>: 8003150: b510 push {r4, lr} 8003152: 4802 ldr r0, [pc, #8] ; (800315c <__malloc_lock+0xc>) 8003154: f7ff ff81 bl 800305a <__retarget_lock_acquire_recursive> 8003158: bd10 pop {r4, pc} 800315a: 46c0 nop ; (mov r8, r8) 800315c: 20000118 .word 0x20000118 08003160 <__malloc_unlock>: 8003160: b510 push {r4, lr} 8003162: 4802 ldr r0, [pc, #8] ; (800316c <__malloc_unlock+0xc>) 8003164: f7ff ff7a bl 800305c <__retarget_lock_release_recursive> 8003168: bd10 pop {r4, pc} 800316a: 46c0 nop ; (mov r8, r8) 800316c: 20000118 .word 0x20000118 08003170 <_raise_r>: 8003170: b570 push {r4, r5, r6, lr} 8003172: 0004 movs r4, r0 8003174: 000d movs r5, r1 8003176: 291f cmp r1, #31 8003178: d904 bls.n 8003184 <_raise_r+0x14> 800317a: 2316 movs r3, #22 800317c: 6003 str r3, [r0, #0] 800317e: 2001 movs r0, #1 8003180: 4240 negs r0, r0 8003182: bd70 pop {r4, r5, r6, pc} 8003184: 6c43 ldr r3, [r0, #68] ; 0x44 8003186: 2b00 cmp r3, #0 8003188: d004 beq.n 8003194 <_raise_r+0x24> 800318a: 008a lsls r2, r1, #2 800318c: 189b adds r3, r3, r2 800318e: 681a ldr r2, [r3, #0] 8003190: 2a00 cmp r2, #0 8003192: d108 bne.n 80031a6 <_raise_r+0x36> 8003194: 0020 movs r0, r4 8003196: f000 f831 bl 80031fc <_getpid_r> 800319a: 002a movs r2, r5 800319c: 0001 movs r1, r0 800319e: 0020 movs r0, r4 80031a0: f000 f81a bl 80031d8 <_kill_r> 80031a4: e7ed b.n 8003182 <_raise_r+0x12> 80031a6: 2000 movs r0, #0 80031a8: 2a01 cmp r2, #1 80031aa: d0ea beq.n 8003182 <_raise_r+0x12> 80031ac: 1c51 adds r1, r2, #1 80031ae: d103 bne.n 80031b8 <_raise_r+0x48> 80031b0: 2316 movs r3, #22 80031b2: 3001 adds r0, #1 80031b4: 6023 str r3, [r4, #0] 80031b6: e7e4 b.n 8003182 <_raise_r+0x12> 80031b8: 2400 movs r4, #0 80031ba: 0028 movs r0, r5 80031bc: 601c str r4, [r3, #0] 80031be: 4790 blx r2 80031c0: 0020 movs r0, r4 80031c2: e7de b.n 8003182 <_raise_r+0x12> 080031c4 : 80031c4: b510 push {r4, lr} 80031c6: 4b03 ldr r3, [pc, #12] ; (80031d4 ) 80031c8: 0001 movs r1, r0 80031ca: 6818 ldr r0, [r3, #0] 80031cc: f7ff ffd0 bl 8003170 <_raise_r> 80031d0: bd10 pop {r4, pc} 80031d2: 46c0 nop ; (mov r8, r8) 80031d4: 2000000c .word 0x2000000c 080031d8 <_kill_r>: 80031d8: 2300 movs r3, #0 80031da: b570 push {r4, r5, r6, lr} 80031dc: 4d06 ldr r5, [pc, #24] ; (80031f8 <_kill_r+0x20>) 80031de: 0004 movs r4, r0 80031e0: 0008 movs r0, r1 80031e2: 0011 movs r1, r2 80031e4: 602b str r3, [r5, #0] 80031e6: f7fd faf2 bl 80007ce <_kill> 80031ea: 1c43 adds r3, r0, #1 80031ec: d103 bne.n 80031f6 <_kill_r+0x1e> 80031ee: 682b ldr r3, [r5, #0] 80031f0: 2b00 cmp r3, #0 80031f2: d000 beq.n 80031f6 <_kill_r+0x1e> 80031f4: 6023 str r3, [r4, #0] 80031f6: bd70 pop {r4, r5, r6, pc} 80031f8: 20000120 .word 0x20000120 080031fc <_getpid_r>: 80031fc: b510 push {r4, lr} 80031fe: f7fd fae0 bl 80007c2 <_getpid> 8003202: bd10 pop {r4, pc} 08003204 <__sread>: 8003204: b570 push {r4, r5, r6, lr} 8003206: 000c movs r4, r1 8003208: 250e movs r5, #14 800320a: 5f49 ldrsh r1, [r1, r5] 800320c: f000 f8a4 bl 8003358 <_read_r> 8003210: 2800 cmp r0, #0 8003212: db03 blt.n 800321c <__sread+0x18> 8003214: 6d63 ldr r3, [r4, #84] ; 0x54 8003216: 181b adds r3, r3, r0 8003218: 6563 str r3, [r4, #84] ; 0x54 800321a: bd70 pop {r4, r5, r6, pc} 800321c: 89a3 ldrh r3, [r4, #12] 800321e: 4a02 ldr r2, [pc, #8] ; (8003228 <__sread+0x24>) 8003220: 4013 ands r3, r2 8003222: 81a3 strh r3, [r4, #12] 8003224: e7f9 b.n 800321a <__sread+0x16> 8003226: 46c0 nop ; (mov r8, r8) 8003228: ffffefff .word 0xffffefff 0800322c <__swrite>: 800322c: b5f8 push {r3, r4, r5, r6, r7, lr} 800322e: 001f movs r7, r3 8003230: 898b ldrh r3, [r1, #12] 8003232: 0005 movs r5, r0 8003234: 000c movs r4, r1 8003236: 0016 movs r6, r2 8003238: 05db lsls r3, r3, #23 800323a: d505 bpl.n 8003248 <__swrite+0x1c> 800323c: 230e movs r3, #14 800323e: 5ec9 ldrsh r1, [r1, r3] 8003240: 2200 movs r2, #0 8003242: 2302 movs r3, #2 8003244: f000 f874 bl 8003330 <_lseek_r> 8003248: 89a3 ldrh r3, [r4, #12] 800324a: 4a05 ldr r2, [pc, #20] ; (8003260 <__swrite+0x34>) 800324c: 0028 movs r0, r5 800324e: 4013 ands r3, r2 8003250: 81a3 strh r3, [r4, #12] 8003252: 0032 movs r2, r6 8003254: 230e movs r3, #14 8003256: 5ee1 ldrsh r1, [r4, r3] 8003258: 003b movs r3, r7 800325a: f000 f81f bl 800329c <_write_r> 800325e: bdf8 pop {r3, r4, r5, r6, r7, pc} 8003260: ffffefff .word 0xffffefff 08003264 <__sseek>: 8003264: b570 push {r4, r5, r6, lr} 8003266: 000c movs r4, r1 8003268: 250e movs r5, #14 800326a: 5f49 ldrsh r1, [r1, r5] 800326c: f000 f860 bl 8003330 <_lseek_r> 8003270: 89a3 ldrh r3, [r4, #12] 8003272: 1c42 adds r2, r0, #1 8003274: d103 bne.n 800327e <__sseek+0x1a> 8003276: 4a05 ldr r2, [pc, #20] ; (800328c <__sseek+0x28>) 8003278: 4013 ands r3, r2 800327a: 81a3 strh r3, [r4, #12] 800327c: bd70 pop {r4, r5, r6, pc} 800327e: 2280 movs r2, #128 ; 0x80 8003280: 0152 lsls r2, r2, #5 8003282: 4313 orrs r3, r2 8003284: 81a3 strh r3, [r4, #12] 8003286: 6560 str r0, [r4, #84] ; 0x54 8003288: e7f8 b.n 800327c <__sseek+0x18> 800328a: 46c0 nop ; (mov r8, r8) 800328c: ffffefff .word 0xffffefff 08003290 <__sclose>: 8003290: b510 push {r4, lr} 8003292: 230e movs r3, #14 8003294: 5ec9 ldrsh r1, [r1, r3] 8003296: f000 f815 bl 80032c4 <_close_r> 800329a: bd10 pop {r4, pc} 0800329c <_write_r>: 800329c: b570 push {r4, r5, r6, lr} 800329e: 0004 movs r4, r0 80032a0: 0008 movs r0, r1 80032a2: 0011 movs r1, r2 80032a4: 001a movs r2, r3 80032a6: 2300 movs r3, #0 80032a8: 4d05 ldr r5, [pc, #20] ; (80032c0 <_write_r+0x24>) 80032aa: 602b str r3, [r5, #0] 80032ac: f7fd fac8 bl 8000840 <_write> 80032b0: 1c43 adds r3, r0, #1 80032b2: d103 bne.n 80032bc <_write_r+0x20> 80032b4: 682b ldr r3, [r5, #0] 80032b6: 2b00 cmp r3, #0 80032b8: d000 beq.n 80032bc <_write_r+0x20> 80032ba: 6023 str r3, [r4, #0] 80032bc: bd70 pop {r4, r5, r6, pc} 80032be: 46c0 nop ; (mov r8, r8) 80032c0: 20000120 .word 0x20000120 080032c4 <_close_r>: 80032c4: 2300 movs r3, #0 80032c6: b570 push {r4, r5, r6, lr} 80032c8: 4d06 ldr r5, [pc, #24] ; (80032e4 <_close_r+0x20>) 80032ca: 0004 movs r4, r0 80032cc: 0008 movs r0, r1 80032ce: 602b str r3, [r5, #0] 80032d0: f7fd fad2 bl 8000878 <_close> 80032d4: 1c43 adds r3, r0, #1 80032d6: d103 bne.n 80032e0 <_close_r+0x1c> 80032d8: 682b ldr r3, [r5, #0] 80032da: 2b00 cmp r3, #0 80032dc: d000 beq.n 80032e0 <_close_r+0x1c> 80032de: 6023 str r3, [r4, #0] 80032e0: bd70 pop {r4, r5, r6, pc} 80032e2: 46c0 nop ; (mov r8, r8) 80032e4: 20000120 .word 0x20000120 080032e8 <_fstat_r>: 80032e8: 2300 movs r3, #0 80032ea: b570 push {r4, r5, r6, lr} 80032ec: 4d06 ldr r5, [pc, #24] ; (8003308 <_fstat_r+0x20>) 80032ee: 0004 movs r4, r0 80032f0: 0008 movs r0, r1 80032f2: 0011 movs r1, r2 80032f4: 602b str r3, [r5, #0] 80032f6: f7fd fac9 bl 800088c <_fstat> 80032fa: 1c43 adds r3, r0, #1 80032fc: d103 bne.n 8003306 <_fstat_r+0x1e> 80032fe: 682b ldr r3, [r5, #0] 8003300: 2b00 cmp r3, #0 8003302: d000 beq.n 8003306 <_fstat_r+0x1e> 8003304: 6023 str r3, [r4, #0] 8003306: bd70 pop {r4, r5, r6, pc} 8003308: 20000120 .word 0x20000120 0800330c <_isatty_r>: 800330c: 2300 movs r3, #0 800330e: b570 push {r4, r5, r6, lr} 8003310: 4d06 ldr r5, [pc, #24] ; (800332c <_isatty_r+0x20>) 8003312: 0004 movs r4, r0 8003314: 0008 movs r0, r1 8003316: 602b str r3, [r5, #0] 8003318: f7fd fac6 bl 80008a8 <_isatty> 800331c: 1c43 adds r3, r0, #1 800331e: d103 bne.n 8003328 <_isatty_r+0x1c> 8003320: 682b ldr r3, [r5, #0] 8003322: 2b00 cmp r3, #0 8003324: d000 beq.n 8003328 <_isatty_r+0x1c> 8003326: 6023 str r3, [r4, #0] 8003328: bd70 pop {r4, r5, r6, pc} 800332a: 46c0 nop ; (mov r8, r8) 800332c: 20000120 .word 0x20000120 08003330 <_lseek_r>: 8003330: b570 push {r4, r5, r6, lr} 8003332: 0004 movs r4, r0 8003334: 0008 movs r0, r1 8003336: 0011 movs r1, r2 8003338: 001a movs r2, r3 800333a: 2300 movs r3, #0 800333c: 4d05 ldr r5, [pc, #20] ; (8003354 <_lseek_r+0x24>) 800333e: 602b str r3, [r5, #0] 8003340: f7fd fabb bl 80008ba <_lseek> 8003344: 1c43 adds r3, r0, #1 8003346: d103 bne.n 8003350 <_lseek_r+0x20> 8003348: 682b ldr r3, [r5, #0] 800334a: 2b00 cmp r3, #0 800334c: d000 beq.n 8003350 <_lseek_r+0x20> 800334e: 6023 str r3, [r4, #0] 8003350: bd70 pop {r4, r5, r6, pc} 8003352: 46c0 nop ; (mov r8, r8) 8003354: 20000120 .word 0x20000120 08003358 <_read_r>: 8003358: b570 push {r4, r5, r6, lr} 800335a: 0004 movs r4, r0 800335c: 0008 movs r0, r1 800335e: 0011 movs r1, r2 8003360: 001a movs r2, r3 8003362: 2300 movs r3, #0 8003364: 4d05 ldr r5, [pc, #20] ; (800337c <_read_r+0x24>) 8003366: 602b str r3, [r5, #0] 8003368: f7fd fa4d bl 8000806 <_read> 800336c: 1c43 adds r3, r0, #1 800336e: d103 bne.n 8003378 <_read_r+0x20> 8003370: 682b ldr r3, [r5, #0] 8003372: 2b00 cmp r3, #0 8003374: d000 beq.n 8003378 <_read_r+0x20> 8003376: 6023 str r3, [r4, #0] 8003378: bd70 pop {r4, r5, r6, pc} 800337a: 46c0 nop ; (mov r8, r8) 800337c: 20000120 .word 0x20000120 08003380 <_init>: 8003380: b5f8 push {r3, r4, r5, r6, r7, lr} 8003382: 46c0 nop ; (mov r8, r8) 8003384: bcf8 pop {r3, r4, r5, r6, r7} 8003386: bc08 pop {r3} 8003388: 469e mov lr, r3 800338a: 4770 bx lr 0800338c <_fini>: 800338c: b5f8 push {r3, r4, r5, r6, r7, lr} 800338e: 46c0 nop ; (mov r8, r8) 8003390: bcf8 pop {r3, r4, r5, r6, r7} 8003392: bc08 pop {r3} 8003394: 469e mov lr, r3 8003396: 4770 bx lr