Motor_Controller.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00000e50 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000030 08000f10 08000f10 00010f10 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08000f40 08000f40 0002000c 2**0 CONTENTS 4 .ARM 00000000 08000f40 08000f40 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 08000f40 08000f40 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08000f40 08000f40 00010f40 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08000f44 08000f44 00010f44 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 08000f48 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 2000000c 08000f54 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000002c 08000f54 0002002c 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 0000222a 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00000c01 00000000 00000000 0002225e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000002f8 00000000 00000000 00022e60 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000280 00000000 00000000 00023158 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0000dcca 00000000 00000000 000233d8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00003cac 00000000 00000000 000310a2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0005320b 00000000 00000000 00034d4e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 00087f59 2**0 CONTENTS, READONLY 20 .debug_frame 000008e8 00000000 00000000 00087fac 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 2000000c .word 0x2000000c 80000e0: 00000000 .word 0x00000000 80000e4: 08000ef8 .word 0x08000ef8 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000010 .word 0x20000010 8000104: 08000ef8 .word 0x08000ef8 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f806 bl 800021c <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__aeabi_idiv0>: 800021c: 4770 bx lr 800021e: 46c0 nop ; (mov r8, r8) 08000220
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000220: b580 push {r7, lr} 8000222: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000224: f000 f8d8 bl 80003d8 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000228: f000 f803 bl 8000232 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800022c: f000 f84c bl 80002c8 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000230: e7fe b.n 8000230 08000232 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000232: b590 push {r4, r7, lr} 8000234: b091 sub sp, #68 ; 0x44 8000236: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000238: 2410 movs r4, #16 800023a: 193b adds r3, r7, r4 800023c: 0018 movs r0, r3 800023e: 2330 movs r3, #48 ; 0x30 8000240: 001a movs r2, r3 8000242: 2100 movs r1, #0 8000244: f000 fe50 bl 8000ee8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000248: 003b movs r3, r7 800024a: 0018 movs r0, r3 800024c: 2310 movs r3, #16 800024e: 001a movs r2, r3 8000250: 2100 movs r1, #0 8000252: f000 fe49 bl 8000ee8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8000256: 0021 movs r1, r4 8000258: 187b adds r3, r7, r1 800025a: 2202 movs r2, #2 800025c: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800025e: 187b adds r3, r7, r1 8000260: 2201 movs r2, #1 8000262: 60da str r2, [r3, #12] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000264: 187b adds r3, r7, r1 8000266: 2210 movs r2, #16 8000268: 611a str r2, [r3, #16] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800026a: 187b adds r3, r7, r1 800026c: 2202 movs r2, #2 800026e: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8000270: 187b adds r3, r7, r1 8000272: 2200 movs r2, #0 8000274: 625a str r2, [r3, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; 8000276: 187b adds r3, r7, r1 8000278: 22a0 movs r2, #160 ; 0xa0 800027a: 0392 lsls r2, r2, #14 800027c: 629a str r2, [r3, #40] ; 0x28 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; 800027e: 187b adds r3, r7, r1 8000280: 2200 movs r2, #0 8000282: 62da str r2, [r3, #44] ; 0x2c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000284: 187b adds r3, r7, r1 8000286: 0018 movs r0, r3 8000288: f000 f9be bl 8000608 800028c: 1e03 subs r3, r0, #0 800028e: d001 beq.n 8000294 { Error_Handler(); 8000290: f000 f832 bl 80002f8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000294: 003b movs r3, r7 8000296: 2207 movs r2, #7 8000298: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800029a: 003b movs r3, r7 800029c: 2202 movs r2, #2 800029e: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002a0: 003b movs r3, r7 80002a2: 2200 movs r2, #0 80002a4: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80002a6: 003b movs r3, r7 80002a8: 2200 movs r2, #0 80002aa: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80002ac: 003b movs r3, r7 80002ae: 2101 movs r1, #1 80002b0: 0018 movs r0, r3 80002b2: f000 fcc3 bl 8000c3c 80002b6: 1e03 subs r3, r0, #0 80002b8: d001 beq.n 80002be { Error_Handler(); 80002ba: f000 f81d bl 80002f8 } } 80002be: 46c0 nop ; (mov r8, r8) 80002c0: 46bd mov sp, r7 80002c2: b011 add sp, #68 ; 0x44 80002c4: bd90 pop {r4, r7, pc} ... 080002c8 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80002c8: b580 push {r7, lr} 80002ca: b082 sub sp, #8 80002cc: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80002ce: 4b09 ldr r3, [pc, #36] ; (80002f4 ) 80002d0: 695a ldr r2, [r3, #20] 80002d2: 4b08 ldr r3, [pc, #32] ; (80002f4 ) 80002d4: 2180 movs r1, #128 ; 0x80 80002d6: 0289 lsls r1, r1, #10 80002d8: 430a orrs r2, r1 80002da: 615a str r2, [r3, #20] 80002dc: 4b05 ldr r3, [pc, #20] ; (80002f4 ) 80002de: 695a ldr r2, [r3, #20] 80002e0: 2380 movs r3, #128 ; 0x80 80002e2: 029b lsls r3, r3, #10 80002e4: 4013 ands r3, r2 80002e6: 607b str r3, [r7, #4] 80002e8: 687b ldr r3, [r7, #4] } 80002ea: 46c0 nop ; (mov r8, r8) 80002ec: 46bd mov sp, r7 80002ee: b002 add sp, #8 80002f0: bd80 pop {r7, pc} 80002f2: 46c0 nop ; (mov r8, r8) 80002f4: 40021000 .word 0x40021000 080002f8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80002f8: b580 push {r7, lr} 80002fa: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80002fc: b672 cpsid i } 80002fe: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000300: e7fe b.n 8000300 ... 08000304 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000304: b580 push {r7, lr} 8000306: b082 sub sp, #8 8000308: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800030a: 4b0f ldr r3, [pc, #60] ; (8000348 ) 800030c: 699a ldr r2, [r3, #24] 800030e: 4b0e ldr r3, [pc, #56] ; (8000348 ) 8000310: 2101 movs r1, #1 8000312: 430a orrs r2, r1 8000314: 619a str r2, [r3, #24] 8000316: 4b0c ldr r3, [pc, #48] ; (8000348 ) 8000318: 699b ldr r3, [r3, #24] 800031a: 2201 movs r2, #1 800031c: 4013 ands r3, r2 800031e: 607b str r3, [r7, #4] 8000320: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000322: 4b09 ldr r3, [pc, #36] ; (8000348 ) 8000324: 69da ldr r2, [r3, #28] 8000326: 4b08 ldr r3, [pc, #32] ; (8000348 ) 8000328: 2180 movs r1, #128 ; 0x80 800032a: 0549 lsls r1, r1, #21 800032c: 430a orrs r2, r1 800032e: 61da str r2, [r3, #28] 8000330: 4b05 ldr r3, [pc, #20] ; (8000348 ) 8000332: 69da ldr r2, [r3, #28] 8000334: 2380 movs r3, #128 ; 0x80 8000336: 055b lsls r3, r3, #21 8000338: 4013 ands r3, r2 800033a: 603b str r3, [r7, #0] 800033c: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800033e: 46c0 nop ; (mov r8, r8) 8000340: 46bd mov sp, r7 8000342: b002 add sp, #8 8000344: bd80 pop {r7, pc} 8000346: 46c0 nop ; (mov r8, r8) 8000348: 40021000 .word 0x40021000 0800034c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800034c: b580 push {r7, lr} 800034e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000350: e7fe b.n 8000350 08000352 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000352: b580 push {r7, lr} 8000354: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000356: e7fe b.n 8000356 08000358 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000358: b580 push {r7, lr} 800035a: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 800035c: 46c0 nop ; (mov r8, r8) 800035e: 46bd mov sp, r7 8000360: bd80 pop {r7, pc} 08000362 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000362: b580 push {r7, lr} 8000364: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000366: 46c0 nop ; (mov r8, r8) 8000368: 46bd mov sp, r7 800036a: bd80 pop {r7, pc} 0800036c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800036c: b580 push {r7, lr} 800036e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000370: f000 f87a bl 8000468 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000374: 46c0 nop ; (mov r8, r8) 8000376: 46bd mov sp, r7 8000378: bd80 pop {r7, pc} 0800037a : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 800037a: b580 push {r7, lr} 800037c: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 800037e: 46c0 nop ; (mov r8, r8) 8000380: 46bd mov sp, r7 8000382: bd80 pop {r7, pc} 08000384 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000384: 480d ldr r0, [pc, #52] ; (80003bc ) mov sp, r0 /* set stack pointer */ 8000386: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000388: 480d ldr r0, [pc, #52] ; (80003c0 ) ldr r1, =_edata 800038a: 490e ldr r1, [pc, #56] ; (80003c4 ) ldr r2, =_sidata 800038c: 4a0e ldr r2, [pc, #56] ; (80003c8 ) movs r3, #0 800038e: 2300 movs r3, #0 b LoopCopyDataInit 8000390: e002 b.n 8000398 08000392 : CopyDataInit: ldr r4, [r2, r3] 8000392: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000394: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000396: 3304 adds r3, #4 08000398 : LoopCopyDataInit: adds r4, r0, r3 8000398: 18c4 adds r4, r0, r3 cmp r4, r1 800039a: 428c cmp r4, r1 bcc CopyDataInit 800039c: d3f9 bcc.n 8000392 /* Zero fill the bss segment. */ ldr r2, =_sbss 800039e: 4a0b ldr r2, [pc, #44] ; (80003cc ) ldr r4, =_ebss 80003a0: 4c0b ldr r4, [pc, #44] ; (80003d0 ) movs r3, #0 80003a2: 2300 movs r3, #0 b LoopFillZerobss 80003a4: e001 b.n 80003aa 080003a6 : FillZerobss: str r3, [r2] 80003a6: 6013 str r3, [r2, #0] adds r2, r2, #4 80003a8: 3204 adds r2, #4 080003aa : LoopFillZerobss: cmp r2, r4 80003aa: 42a2 cmp r2, r4 bcc FillZerobss 80003ac: d3fb bcc.n 80003a6 /* Call the clock system intitialization function.*/ bl SystemInit 80003ae: f7ff ffe4 bl 800037a /* Call static constructors */ bl __libc_init_array 80003b2: f000 fd75 bl 8000ea0 <__libc_init_array> /* Call the application's entry point.*/ bl main 80003b6: f7ff ff33 bl 8000220
080003ba : LoopForever: b LoopForever 80003ba: e7fe b.n 80003ba ldr r0, =_estack 80003bc: 20001000 .word 0x20001000 ldr r0, =_sdata 80003c0: 20000000 .word 0x20000000 ldr r1, =_edata 80003c4: 2000000c .word 0x2000000c ldr r2, =_sidata 80003c8: 08000f48 .word 0x08000f48 ldr r2, =_sbss 80003cc: 2000000c .word 0x2000000c ldr r4, =_ebss 80003d0: 2000002c .word 0x2000002c 080003d4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80003d4: e7fe b.n 80003d4 ... 080003d8 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80003d8: b580 push {r7, lr} 80003da: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80003dc: 4b07 ldr r3, [pc, #28] ; (80003fc ) 80003de: 681a ldr r2, [r3, #0] 80003e0: 4b06 ldr r3, [pc, #24] ; (80003fc ) 80003e2: 2110 movs r1, #16 80003e4: 430a orrs r2, r1 80003e6: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80003e8: 2003 movs r0, #3 80003ea: f000 f809 bl 8000400 /* Init the low level hardware */ HAL_MspInit(); 80003ee: f7ff ff89 bl 8000304 /* Return function status */ return HAL_OK; 80003f2: 2300 movs r3, #0 } 80003f4: 0018 movs r0, r3 80003f6: 46bd mov sp, r7 80003f8: bd80 pop {r7, pc} 80003fa: 46c0 nop ; (mov r8, r8) 80003fc: 40022000 .word 0x40022000 08000400 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000400: b590 push {r4, r7, lr} 8000402: b083 sub sp, #12 8000404: af00 add r7, sp, #0 8000406: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000408: 4b14 ldr r3, [pc, #80] ; (800045c ) 800040a: 681c ldr r4, [r3, #0] 800040c: 4b14 ldr r3, [pc, #80] ; (8000460 ) 800040e: 781b ldrb r3, [r3, #0] 8000410: 0019 movs r1, r3 8000412: 23fa movs r3, #250 ; 0xfa 8000414: 0098 lsls r0, r3, #2 8000416: f7ff fe77 bl 8000108 <__udivsi3> 800041a: 0003 movs r3, r0 800041c: 0019 movs r1, r3 800041e: 0020 movs r0, r4 8000420: f7ff fe72 bl 8000108 <__udivsi3> 8000424: 0003 movs r3, r0 8000426: 0018 movs r0, r3 8000428: f000 f8e1 bl 80005ee 800042c: 1e03 subs r3, r0, #0 800042e: d001 beq.n 8000434 { return HAL_ERROR; 8000430: 2301 movs r3, #1 8000432: e00f b.n 8000454 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000434: 687b ldr r3, [r7, #4] 8000436: 2b03 cmp r3, #3 8000438: d80b bhi.n 8000452 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800043a: 6879 ldr r1, [r7, #4] 800043c: 2301 movs r3, #1 800043e: 425b negs r3, r3 8000440: 2200 movs r2, #0 8000442: 0018 movs r0, r3 8000444: f000 f8be bl 80005c4 uwTickPrio = TickPriority; 8000448: 4b06 ldr r3, [pc, #24] ; (8000464 ) 800044a: 687a ldr r2, [r7, #4] 800044c: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800044e: 2300 movs r3, #0 8000450: e000 b.n 8000454 return HAL_ERROR; 8000452: 2301 movs r3, #1 } 8000454: 0018 movs r0, r3 8000456: 46bd mov sp, r7 8000458: b003 add sp, #12 800045a: bd90 pop {r4, r7, pc} 800045c: 20000000 .word 0x20000000 8000460: 20000008 .word 0x20000008 8000464: 20000004 .word 0x20000004 08000468 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000468: b580 push {r7, lr} 800046a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800046c: 4b05 ldr r3, [pc, #20] ; (8000484 ) 800046e: 781b ldrb r3, [r3, #0] 8000470: 001a movs r2, r3 8000472: 4b05 ldr r3, [pc, #20] ; (8000488 ) 8000474: 681b ldr r3, [r3, #0] 8000476: 18d2 adds r2, r2, r3 8000478: 4b03 ldr r3, [pc, #12] ; (8000488 ) 800047a: 601a str r2, [r3, #0] } 800047c: 46c0 nop ; (mov r8, r8) 800047e: 46bd mov sp, r7 8000480: bd80 pop {r7, pc} 8000482: 46c0 nop ; (mov r8, r8) 8000484: 20000008 .word 0x20000008 8000488: 20000028 .word 0x20000028 0800048c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800048c: b580 push {r7, lr} 800048e: af00 add r7, sp, #0 return uwTick; 8000490: 4b02 ldr r3, [pc, #8] ; (800049c ) 8000492: 681b ldr r3, [r3, #0] } 8000494: 0018 movs r0, r3 8000496: 46bd mov sp, r7 8000498: bd80 pop {r7, pc} 800049a: 46c0 nop ; (mov r8, r8) 800049c: 20000028 .word 0x20000028 080004a0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80004a0: b590 push {r4, r7, lr} 80004a2: b083 sub sp, #12 80004a4: af00 add r7, sp, #0 80004a6: 0002 movs r2, r0 80004a8: 6039 str r1, [r7, #0] 80004aa: 1dfb adds r3, r7, #7 80004ac: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80004ae: 1dfb adds r3, r7, #7 80004b0: 781b ldrb r3, [r3, #0] 80004b2: 2b7f cmp r3, #127 ; 0x7f 80004b4: d828 bhi.n 8000508 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80004b6: 4a2f ldr r2, [pc, #188] ; (8000574 <__NVIC_SetPriority+0xd4>) 80004b8: 1dfb adds r3, r7, #7 80004ba: 781b ldrb r3, [r3, #0] 80004bc: b25b sxtb r3, r3 80004be: 089b lsrs r3, r3, #2 80004c0: 33c0 adds r3, #192 ; 0xc0 80004c2: 009b lsls r3, r3, #2 80004c4: 589b ldr r3, [r3, r2] 80004c6: 1dfa adds r2, r7, #7 80004c8: 7812 ldrb r2, [r2, #0] 80004ca: 0011 movs r1, r2 80004cc: 2203 movs r2, #3 80004ce: 400a ands r2, r1 80004d0: 00d2 lsls r2, r2, #3 80004d2: 21ff movs r1, #255 ; 0xff 80004d4: 4091 lsls r1, r2 80004d6: 000a movs r2, r1 80004d8: 43d2 mvns r2, r2 80004da: 401a ands r2, r3 80004dc: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80004de: 683b ldr r3, [r7, #0] 80004e0: 019b lsls r3, r3, #6 80004e2: 22ff movs r2, #255 ; 0xff 80004e4: 401a ands r2, r3 80004e6: 1dfb adds r3, r7, #7 80004e8: 781b ldrb r3, [r3, #0] 80004ea: 0018 movs r0, r3 80004ec: 2303 movs r3, #3 80004ee: 4003 ands r3, r0 80004f0: 00db lsls r3, r3, #3 80004f2: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80004f4: 481f ldr r0, [pc, #124] ; (8000574 <__NVIC_SetPriority+0xd4>) 80004f6: 1dfb adds r3, r7, #7 80004f8: 781b ldrb r3, [r3, #0] 80004fa: b25b sxtb r3, r3 80004fc: 089b lsrs r3, r3, #2 80004fe: 430a orrs r2, r1 8000500: 33c0 adds r3, #192 ; 0xc0 8000502: 009b lsls r3, r3, #2 8000504: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8000506: e031 b.n 800056c <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000508: 4a1b ldr r2, [pc, #108] ; (8000578 <__NVIC_SetPriority+0xd8>) 800050a: 1dfb adds r3, r7, #7 800050c: 781b ldrb r3, [r3, #0] 800050e: 0019 movs r1, r3 8000510: 230f movs r3, #15 8000512: 400b ands r3, r1 8000514: 3b08 subs r3, #8 8000516: 089b lsrs r3, r3, #2 8000518: 3306 adds r3, #6 800051a: 009b lsls r3, r3, #2 800051c: 18d3 adds r3, r2, r3 800051e: 3304 adds r3, #4 8000520: 681b ldr r3, [r3, #0] 8000522: 1dfa adds r2, r7, #7 8000524: 7812 ldrb r2, [r2, #0] 8000526: 0011 movs r1, r2 8000528: 2203 movs r2, #3 800052a: 400a ands r2, r1 800052c: 00d2 lsls r2, r2, #3 800052e: 21ff movs r1, #255 ; 0xff 8000530: 4091 lsls r1, r2 8000532: 000a movs r2, r1 8000534: 43d2 mvns r2, r2 8000536: 401a ands r2, r3 8000538: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800053a: 683b ldr r3, [r7, #0] 800053c: 019b lsls r3, r3, #6 800053e: 22ff movs r2, #255 ; 0xff 8000540: 401a ands r2, r3 8000542: 1dfb adds r3, r7, #7 8000544: 781b ldrb r3, [r3, #0] 8000546: 0018 movs r0, r3 8000548: 2303 movs r3, #3 800054a: 4003 ands r3, r0 800054c: 00db lsls r3, r3, #3 800054e: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000550: 4809 ldr r0, [pc, #36] ; (8000578 <__NVIC_SetPriority+0xd8>) 8000552: 1dfb adds r3, r7, #7 8000554: 781b ldrb r3, [r3, #0] 8000556: 001c movs r4, r3 8000558: 230f movs r3, #15 800055a: 4023 ands r3, r4 800055c: 3b08 subs r3, #8 800055e: 089b lsrs r3, r3, #2 8000560: 430a orrs r2, r1 8000562: 3306 adds r3, #6 8000564: 009b lsls r3, r3, #2 8000566: 18c3 adds r3, r0, r3 8000568: 3304 adds r3, #4 800056a: 601a str r2, [r3, #0] } 800056c: 46c0 nop ; (mov r8, r8) 800056e: 46bd mov sp, r7 8000570: b003 add sp, #12 8000572: bd90 pop {r4, r7, pc} 8000574: e000e100 .word 0xe000e100 8000578: e000ed00 .word 0xe000ed00 0800057c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800057c: b580 push {r7, lr} 800057e: b082 sub sp, #8 8000580: af00 add r7, sp, #0 8000582: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000584: 687b ldr r3, [r7, #4] 8000586: 1e5a subs r2, r3, #1 8000588: 2380 movs r3, #128 ; 0x80 800058a: 045b lsls r3, r3, #17 800058c: 429a cmp r2, r3 800058e: d301 bcc.n 8000594 { return (1UL); /* Reload value impossible */ 8000590: 2301 movs r3, #1 8000592: e010 b.n 80005b6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000594: 4b0a ldr r3, [pc, #40] ; (80005c0 ) 8000596: 687a ldr r2, [r7, #4] 8000598: 3a01 subs r2, #1 800059a: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800059c: 2301 movs r3, #1 800059e: 425b negs r3, r3 80005a0: 2103 movs r1, #3 80005a2: 0018 movs r0, r3 80005a4: f7ff ff7c bl 80004a0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80005a8: 4b05 ldr r3, [pc, #20] ; (80005c0 ) 80005aa: 2200 movs r2, #0 80005ac: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80005ae: 4b04 ldr r3, [pc, #16] ; (80005c0 ) 80005b0: 2207 movs r2, #7 80005b2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80005b4: 2300 movs r3, #0 } 80005b6: 0018 movs r0, r3 80005b8: 46bd mov sp, r7 80005ba: b002 add sp, #8 80005bc: bd80 pop {r7, pc} 80005be: 46c0 nop ; (mov r8, r8) 80005c0: e000e010 .word 0xe000e010 080005c4 : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80005c4: b580 push {r7, lr} 80005c6: b084 sub sp, #16 80005c8: af00 add r7, sp, #0 80005ca: 60b9 str r1, [r7, #8] 80005cc: 607a str r2, [r7, #4] 80005ce: 210f movs r1, #15 80005d0: 187b adds r3, r7, r1 80005d2: 1c02 adds r2, r0, #0 80005d4: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 80005d6: 68ba ldr r2, [r7, #8] 80005d8: 187b adds r3, r7, r1 80005da: 781b ldrb r3, [r3, #0] 80005dc: b25b sxtb r3, r3 80005de: 0011 movs r1, r2 80005e0: 0018 movs r0, r3 80005e2: f7ff ff5d bl 80004a0 <__NVIC_SetPriority> } 80005e6: 46c0 nop ; (mov r8, r8) 80005e8: 46bd mov sp, r7 80005ea: b004 add sp, #16 80005ec: bd80 pop {r7, pc} 080005ee : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80005ee: b580 push {r7, lr} 80005f0: b082 sub sp, #8 80005f2: af00 add r7, sp, #0 80005f4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80005f6: 687b ldr r3, [r7, #4] 80005f8: 0018 movs r0, r3 80005fa: f7ff ffbf bl 800057c 80005fe: 0003 movs r3, r0 } 8000600: 0018 movs r0, r3 8000602: 46bd mov sp, r7 8000604: b002 add sp, #8 8000606: bd80 pop {r7, pc} 08000608 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000608: b580 push {r7, lr} 800060a: b088 sub sp, #32 800060c: af00 add r7, sp, #0 800060e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8000610: 687b ldr r3, [r7, #4] 8000612: 2b00 cmp r3, #0 8000614: d101 bne.n 800061a { return HAL_ERROR; 8000616: 2301 movs r3, #1 8000618: e301 b.n 8000c1e /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800061a: 687b ldr r3, [r7, #4] 800061c: 681b ldr r3, [r3, #0] 800061e: 2201 movs r2, #1 8000620: 4013 ands r3, r2 8000622: d100 bne.n 8000626 8000624: e08d b.n 8000742 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000626: 4bc3 ldr r3, [pc, #780] ; (8000934 ) 8000628: 685b ldr r3, [r3, #4] 800062a: 220c movs r2, #12 800062c: 4013 ands r3, r2 800062e: 2b04 cmp r3, #4 8000630: d00e beq.n 8000650 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000632: 4bc0 ldr r3, [pc, #768] ; (8000934 ) 8000634: 685b ldr r3, [r3, #4] 8000636: 220c movs r2, #12 8000638: 4013 ands r3, r2 800063a: 2b08 cmp r3, #8 800063c: d116 bne.n 800066c 800063e: 4bbd ldr r3, [pc, #756] ; (8000934 ) 8000640: 685a ldr r2, [r3, #4] 8000642: 2380 movs r3, #128 ; 0x80 8000644: 025b lsls r3, r3, #9 8000646: 401a ands r2, r3 8000648: 2380 movs r3, #128 ; 0x80 800064a: 025b lsls r3, r3, #9 800064c: 429a cmp r2, r3 800064e: d10d bne.n 800066c { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000650: 4bb8 ldr r3, [pc, #736] ; (8000934 ) 8000652: 681a ldr r2, [r3, #0] 8000654: 2380 movs r3, #128 ; 0x80 8000656: 029b lsls r3, r3, #10 8000658: 4013 ands r3, r2 800065a: d100 bne.n 800065e 800065c: e070 b.n 8000740 800065e: 687b ldr r3, [r7, #4] 8000660: 685b ldr r3, [r3, #4] 8000662: 2b00 cmp r3, #0 8000664: d000 beq.n 8000668 8000666: e06b b.n 8000740 { return HAL_ERROR; 8000668: 2301 movs r3, #1 800066a: e2d8 b.n 8000c1e } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800066c: 687b ldr r3, [r7, #4] 800066e: 685b ldr r3, [r3, #4] 8000670: 2b01 cmp r3, #1 8000672: d107 bne.n 8000684 8000674: 4baf ldr r3, [pc, #700] ; (8000934 ) 8000676: 681a ldr r2, [r3, #0] 8000678: 4bae ldr r3, [pc, #696] ; (8000934 ) 800067a: 2180 movs r1, #128 ; 0x80 800067c: 0249 lsls r1, r1, #9 800067e: 430a orrs r2, r1 8000680: 601a str r2, [r3, #0] 8000682: e02f b.n 80006e4 8000684: 687b ldr r3, [r7, #4] 8000686: 685b ldr r3, [r3, #4] 8000688: 2b00 cmp r3, #0 800068a: d10c bne.n 80006a6 800068c: 4ba9 ldr r3, [pc, #676] ; (8000934 ) 800068e: 681a ldr r2, [r3, #0] 8000690: 4ba8 ldr r3, [pc, #672] ; (8000934 ) 8000692: 49a9 ldr r1, [pc, #676] ; (8000938 ) 8000694: 400a ands r2, r1 8000696: 601a str r2, [r3, #0] 8000698: 4ba6 ldr r3, [pc, #664] ; (8000934 ) 800069a: 681a ldr r2, [r3, #0] 800069c: 4ba5 ldr r3, [pc, #660] ; (8000934 ) 800069e: 49a7 ldr r1, [pc, #668] ; (800093c ) 80006a0: 400a ands r2, r1 80006a2: 601a str r2, [r3, #0] 80006a4: e01e b.n 80006e4 80006a6: 687b ldr r3, [r7, #4] 80006a8: 685b ldr r3, [r3, #4] 80006aa: 2b05 cmp r3, #5 80006ac: d10e bne.n 80006cc 80006ae: 4ba1 ldr r3, [pc, #644] ; (8000934 ) 80006b0: 681a ldr r2, [r3, #0] 80006b2: 4ba0 ldr r3, [pc, #640] ; (8000934 ) 80006b4: 2180 movs r1, #128 ; 0x80 80006b6: 02c9 lsls r1, r1, #11 80006b8: 430a orrs r2, r1 80006ba: 601a str r2, [r3, #0] 80006bc: 4b9d ldr r3, [pc, #628] ; (8000934 ) 80006be: 681a ldr r2, [r3, #0] 80006c0: 4b9c ldr r3, [pc, #624] ; (8000934 ) 80006c2: 2180 movs r1, #128 ; 0x80 80006c4: 0249 lsls r1, r1, #9 80006c6: 430a orrs r2, r1 80006c8: 601a str r2, [r3, #0] 80006ca: e00b b.n 80006e4 80006cc: 4b99 ldr r3, [pc, #612] ; (8000934 ) 80006ce: 681a ldr r2, [r3, #0] 80006d0: 4b98 ldr r3, [pc, #608] ; (8000934 ) 80006d2: 4999 ldr r1, [pc, #612] ; (8000938 ) 80006d4: 400a ands r2, r1 80006d6: 601a str r2, [r3, #0] 80006d8: 4b96 ldr r3, [pc, #600] ; (8000934 ) 80006da: 681a ldr r2, [r3, #0] 80006dc: 4b95 ldr r3, [pc, #596] ; (8000934 ) 80006de: 4997 ldr r1, [pc, #604] ; (800093c ) 80006e0: 400a ands r2, r1 80006e2: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80006e4: 687b ldr r3, [r7, #4] 80006e6: 685b ldr r3, [r3, #4] 80006e8: 2b00 cmp r3, #0 80006ea: d014 beq.n 8000716 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80006ec: f7ff fece bl 800048c 80006f0: 0003 movs r3, r0 80006f2: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80006f4: e008 b.n 8000708 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80006f6: f7ff fec9 bl 800048c 80006fa: 0002 movs r2, r0 80006fc: 69bb ldr r3, [r7, #24] 80006fe: 1ad3 subs r3, r2, r3 8000700: 2b64 cmp r3, #100 ; 0x64 8000702: d901 bls.n 8000708 { return HAL_TIMEOUT; 8000704: 2303 movs r3, #3 8000706: e28a b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000708: 4b8a ldr r3, [pc, #552] ; (8000934 ) 800070a: 681a ldr r2, [r3, #0] 800070c: 2380 movs r3, #128 ; 0x80 800070e: 029b lsls r3, r3, #10 8000710: 4013 ands r3, r2 8000712: d0f0 beq.n 80006f6 8000714: e015 b.n 8000742 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000716: f7ff feb9 bl 800048c 800071a: 0003 movs r3, r0 800071c: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800071e: e008 b.n 8000732 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000720: f7ff feb4 bl 800048c 8000724: 0002 movs r2, r0 8000726: 69bb ldr r3, [r7, #24] 8000728: 1ad3 subs r3, r2, r3 800072a: 2b64 cmp r3, #100 ; 0x64 800072c: d901 bls.n 8000732 { return HAL_TIMEOUT; 800072e: 2303 movs r3, #3 8000730: e275 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000732: 4b80 ldr r3, [pc, #512] ; (8000934 ) 8000734: 681a ldr r2, [r3, #0] 8000736: 2380 movs r3, #128 ; 0x80 8000738: 029b lsls r3, r3, #10 800073a: 4013 ands r3, r2 800073c: d1f0 bne.n 8000720 800073e: e000 b.n 8000742 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000740: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000742: 687b ldr r3, [r7, #4] 8000744: 681b ldr r3, [r3, #0] 8000746: 2202 movs r2, #2 8000748: 4013 ands r3, r2 800074a: d100 bne.n 800074e 800074c: e069 b.n 8000822 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800074e: 4b79 ldr r3, [pc, #484] ; (8000934 ) 8000750: 685b ldr r3, [r3, #4] 8000752: 220c movs r2, #12 8000754: 4013 ands r3, r2 8000756: d00b beq.n 8000770 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8000758: 4b76 ldr r3, [pc, #472] ; (8000934 ) 800075a: 685b ldr r3, [r3, #4] 800075c: 220c movs r2, #12 800075e: 4013 ands r3, r2 8000760: 2b08 cmp r3, #8 8000762: d11c bne.n 800079e 8000764: 4b73 ldr r3, [pc, #460] ; (8000934 ) 8000766: 685a ldr r2, [r3, #4] 8000768: 2380 movs r3, #128 ; 0x80 800076a: 025b lsls r3, r3, #9 800076c: 4013 ands r3, r2 800076e: d116 bne.n 800079e { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000770: 4b70 ldr r3, [pc, #448] ; (8000934 ) 8000772: 681b ldr r3, [r3, #0] 8000774: 2202 movs r2, #2 8000776: 4013 ands r3, r2 8000778: d005 beq.n 8000786 800077a: 687b ldr r3, [r7, #4] 800077c: 68db ldr r3, [r3, #12] 800077e: 2b01 cmp r3, #1 8000780: d001 beq.n 8000786 { return HAL_ERROR; 8000782: 2301 movs r3, #1 8000784: e24b b.n 8000c1e } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000786: 4b6b ldr r3, [pc, #428] ; (8000934 ) 8000788: 681b ldr r3, [r3, #0] 800078a: 22f8 movs r2, #248 ; 0xf8 800078c: 4393 bics r3, r2 800078e: 0019 movs r1, r3 8000790: 687b ldr r3, [r7, #4] 8000792: 691b ldr r3, [r3, #16] 8000794: 00da lsls r2, r3, #3 8000796: 4b67 ldr r3, [pc, #412] ; (8000934 ) 8000798: 430a orrs r2, r1 800079a: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800079c: e041 b.n 8000822 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800079e: 687b ldr r3, [r7, #4] 80007a0: 68db ldr r3, [r3, #12] 80007a2: 2b00 cmp r3, #0 80007a4: d024 beq.n 80007f0 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80007a6: 4b63 ldr r3, [pc, #396] ; (8000934 ) 80007a8: 681a ldr r2, [r3, #0] 80007aa: 4b62 ldr r3, [pc, #392] ; (8000934 ) 80007ac: 2101 movs r1, #1 80007ae: 430a orrs r2, r1 80007b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80007b2: f7ff fe6b bl 800048c 80007b6: 0003 movs r3, r0 80007b8: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80007ba: e008 b.n 80007ce { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80007bc: f7ff fe66 bl 800048c 80007c0: 0002 movs r2, r0 80007c2: 69bb ldr r3, [r7, #24] 80007c4: 1ad3 subs r3, r2, r3 80007c6: 2b02 cmp r3, #2 80007c8: d901 bls.n 80007ce { return HAL_TIMEOUT; 80007ca: 2303 movs r3, #3 80007cc: e227 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80007ce: 4b59 ldr r3, [pc, #356] ; (8000934 ) 80007d0: 681b ldr r3, [r3, #0] 80007d2: 2202 movs r2, #2 80007d4: 4013 ands r3, r2 80007d6: d0f1 beq.n 80007bc } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80007d8: 4b56 ldr r3, [pc, #344] ; (8000934 ) 80007da: 681b ldr r3, [r3, #0] 80007dc: 22f8 movs r2, #248 ; 0xf8 80007de: 4393 bics r3, r2 80007e0: 0019 movs r1, r3 80007e2: 687b ldr r3, [r7, #4] 80007e4: 691b ldr r3, [r3, #16] 80007e6: 00da lsls r2, r3, #3 80007e8: 4b52 ldr r3, [pc, #328] ; (8000934 ) 80007ea: 430a orrs r2, r1 80007ec: 601a str r2, [r3, #0] 80007ee: e018 b.n 8000822 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80007f0: 4b50 ldr r3, [pc, #320] ; (8000934 ) 80007f2: 681a ldr r2, [r3, #0] 80007f4: 4b4f ldr r3, [pc, #316] ; (8000934 ) 80007f6: 2101 movs r1, #1 80007f8: 438a bics r2, r1 80007fa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80007fc: f7ff fe46 bl 800048c 8000800: 0003 movs r3, r0 8000802: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000804: e008 b.n 8000818 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000806: f7ff fe41 bl 800048c 800080a: 0002 movs r2, r0 800080c: 69bb ldr r3, [r7, #24] 800080e: 1ad3 subs r3, r2, r3 8000810: 2b02 cmp r3, #2 8000812: d901 bls.n 8000818 { return HAL_TIMEOUT; 8000814: 2303 movs r3, #3 8000816: e202 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000818: 4b46 ldr r3, [pc, #280] ; (8000934 ) 800081a: 681b ldr r3, [r3, #0] 800081c: 2202 movs r2, #2 800081e: 4013 ands r3, r2 8000820: d1f1 bne.n 8000806 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000822: 687b ldr r3, [r7, #4] 8000824: 681b ldr r3, [r3, #0] 8000826: 2208 movs r2, #8 8000828: 4013 ands r3, r2 800082a: d036 beq.n 800089a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800082c: 687b ldr r3, [r7, #4] 800082e: 69db ldr r3, [r3, #28] 8000830: 2b00 cmp r3, #0 8000832: d019 beq.n 8000868 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000834: 4b3f ldr r3, [pc, #252] ; (8000934 ) 8000836: 6a5a ldr r2, [r3, #36] ; 0x24 8000838: 4b3e ldr r3, [pc, #248] ; (8000934 ) 800083a: 2101 movs r1, #1 800083c: 430a orrs r2, r1 800083e: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000840: f7ff fe24 bl 800048c 8000844: 0003 movs r3, r0 8000846: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000848: e008 b.n 800085c { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800084a: f7ff fe1f bl 800048c 800084e: 0002 movs r2, r0 8000850: 69bb ldr r3, [r7, #24] 8000852: 1ad3 subs r3, r2, r3 8000854: 2b02 cmp r3, #2 8000856: d901 bls.n 800085c { return HAL_TIMEOUT; 8000858: 2303 movs r3, #3 800085a: e1e0 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800085c: 4b35 ldr r3, [pc, #212] ; (8000934 ) 800085e: 6a5b ldr r3, [r3, #36] ; 0x24 8000860: 2202 movs r2, #2 8000862: 4013 ands r3, r2 8000864: d0f1 beq.n 800084a 8000866: e018 b.n 800089a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000868: 4b32 ldr r3, [pc, #200] ; (8000934 ) 800086a: 6a5a ldr r2, [r3, #36] ; 0x24 800086c: 4b31 ldr r3, [pc, #196] ; (8000934 ) 800086e: 2101 movs r1, #1 8000870: 438a bics r2, r1 8000872: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000874: f7ff fe0a bl 800048c 8000878: 0003 movs r3, r0 800087a: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800087c: e008 b.n 8000890 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800087e: f7ff fe05 bl 800048c 8000882: 0002 movs r2, r0 8000884: 69bb ldr r3, [r7, #24] 8000886: 1ad3 subs r3, r2, r3 8000888: 2b02 cmp r3, #2 800088a: d901 bls.n 8000890 { return HAL_TIMEOUT; 800088c: 2303 movs r3, #3 800088e: e1c6 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000890: 4b28 ldr r3, [pc, #160] ; (8000934 ) 8000892: 6a5b ldr r3, [r3, #36] ; 0x24 8000894: 2202 movs r2, #2 8000896: 4013 ands r3, r2 8000898: d1f1 bne.n 800087e } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800089a: 687b ldr r3, [r7, #4] 800089c: 681b ldr r3, [r3, #0] 800089e: 2204 movs r2, #4 80008a0: 4013 ands r3, r2 80008a2: d100 bne.n 80008a6 80008a4: e0b4 b.n 8000a10 { FlagStatus pwrclkchanged = RESET; 80008a6: 201f movs r0, #31 80008a8: 183b adds r3, r7, r0 80008aa: 2200 movs r2, #0 80008ac: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80008ae: 4b21 ldr r3, [pc, #132] ; (8000934 ) 80008b0: 69da ldr r2, [r3, #28] 80008b2: 2380 movs r3, #128 ; 0x80 80008b4: 055b lsls r3, r3, #21 80008b6: 4013 ands r3, r2 80008b8: d110 bne.n 80008dc { __HAL_RCC_PWR_CLK_ENABLE(); 80008ba: 4b1e ldr r3, [pc, #120] ; (8000934 ) 80008bc: 69da ldr r2, [r3, #28] 80008be: 4b1d ldr r3, [pc, #116] ; (8000934 ) 80008c0: 2180 movs r1, #128 ; 0x80 80008c2: 0549 lsls r1, r1, #21 80008c4: 430a orrs r2, r1 80008c6: 61da str r2, [r3, #28] 80008c8: 4b1a ldr r3, [pc, #104] ; (8000934 ) 80008ca: 69da ldr r2, [r3, #28] 80008cc: 2380 movs r3, #128 ; 0x80 80008ce: 055b lsls r3, r3, #21 80008d0: 4013 ands r3, r2 80008d2: 60fb str r3, [r7, #12] 80008d4: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80008d6: 183b adds r3, r7, r0 80008d8: 2201 movs r2, #1 80008da: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80008dc: 4b18 ldr r3, [pc, #96] ; (8000940 ) 80008de: 681a ldr r2, [r3, #0] 80008e0: 2380 movs r3, #128 ; 0x80 80008e2: 005b lsls r3, r3, #1 80008e4: 4013 ands r3, r2 80008e6: d11a bne.n 800091e { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80008e8: 4b15 ldr r3, [pc, #84] ; (8000940 ) 80008ea: 681a ldr r2, [r3, #0] 80008ec: 4b14 ldr r3, [pc, #80] ; (8000940 ) 80008ee: 2180 movs r1, #128 ; 0x80 80008f0: 0049 lsls r1, r1, #1 80008f2: 430a orrs r2, r1 80008f4: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80008f6: f7ff fdc9 bl 800048c 80008fa: 0003 movs r3, r0 80008fc: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80008fe: e008 b.n 8000912 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000900: f7ff fdc4 bl 800048c 8000904: 0002 movs r2, r0 8000906: 69bb ldr r3, [r7, #24] 8000908: 1ad3 subs r3, r2, r3 800090a: 2b64 cmp r3, #100 ; 0x64 800090c: d901 bls.n 8000912 { return HAL_TIMEOUT; 800090e: 2303 movs r3, #3 8000910: e185 b.n 8000c1e while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000912: 4b0b ldr r3, [pc, #44] ; (8000940 ) 8000914: 681a ldr r2, [r3, #0] 8000916: 2380 movs r3, #128 ; 0x80 8000918: 005b lsls r3, r3, #1 800091a: 4013 ands r3, r2 800091c: d0f0 beq.n 8000900 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800091e: 687b ldr r3, [r7, #4] 8000920: 689b ldr r3, [r3, #8] 8000922: 2b01 cmp r3, #1 8000924: d10e bne.n 8000944 8000926: 4b03 ldr r3, [pc, #12] ; (8000934 ) 8000928: 6a1a ldr r2, [r3, #32] 800092a: 4b02 ldr r3, [pc, #8] ; (8000934 ) 800092c: 2101 movs r1, #1 800092e: 430a orrs r2, r1 8000930: 621a str r2, [r3, #32] 8000932: e035 b.n 80009a0 8000934: 40021000 .word 0x40021000 8000938: fffeffff .word 0xfffeffff 800093c: fffbffff .word 0xfffbffff 8000940: 40007000 .word 0x40007000 8000944: 687b ldr r3, [r7, #4] 8000946: 689b ldr r3, [r3, #8] 8000948: 2b00 cmp r3, #0 800094a: d10c bne.n 8000966 800094c: 4bb6 ldr r3, [pc, #728] ; (8000c28 ) 800094e: 6a1a ldr r2, [r3, #32] 8000950: 4bb5 ldr r3, [pc, #724] ; (8000c28 ) 8000952: 2101 movs r1, #1 8000954: 438a bics r2, r1 8000956: 621a str r2, [r3, #32] 8000958: 4bb3 ldr r3, [pc, #716] ; (8000c28 ) 800095a: 6a1a ldr r2, [r3, #32] 800095c: 4bb2 ldr r3, [pc, #712] ; (8000c28 ) 800095e: 2104 movs r1, #4 8000960: 438a bics r2, r1 8000962: 621a str r2, [r3, #32] 8000964: e01c b.n 80009a0 8000966: 687b ldr r3, [r7, #4] 8000968: 689b ldr r3, [r3, #8] 800096a: 2b05 cmp r3, #5 800096c: d10c bne.n 8000988 800096e: 4bae ldr r3, [pc, #696] ; (8000c28 ) 8000970: 6a1a ldr r2, [r3, #32] 8000972: 4bad ldr r3, [pc, #692] ; (8000c28 ) 8000974: 2104 movs r1, #4 8000976: 430a orrs r2, r1 8000978: 621a str r2, [r3, #32] 800097a: 4bab ldr r3, [pc, #684] ; (8000c28 ) 800097c: 6a1a ldr r2, [r3, #32] 800097e: 4baa ldr r3, [pc, #680] ; (8000c28 ) 8000980: 2101 movs r1, #1 8000982: 430a orrs r2, r1 8000984: 621a str r2, [r3, #32] 8000986: e00b b.n 80009a0 8000988: 4ba7 ldr r3, [pc, #668] ; (8000c28 ) 800098a: 6a1a ldr r2, [r3, #32] 800098c: 4ba6 ldr r3, [pc, #664] ; (8000c28 ) 800098e: 2101 movs r1, #1 8000990: 438a bics r2, r1 8000992: 621a str r2, [r3, #32] 8000994: 4ba4 ldr r3, [pc, #656] ; (8000c28 ) 8000996: 6a1a ldr r2, [r3, #32] 8000998: 4ba3 ldr r3, [pc, #652] ; (8000c28 ) 800099a: 2104 movs r1, #4 800099c: 438a bics r2, r1 800099e: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80009a0: 687b ldr r3, [r7, #4] 80009a2: 689b ldr r3, [r3, #8] 80009a4: 2b00 cmp r3, #0 80009a6: d014 beq.n 80009d2 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80009a8: f7ff fd70 bl 800048c 80009ac: 0003 movs r3, r0 80009ae: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80009b0: e009 b.n 80009c6 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80009b2: f7ff fd6b bl 800048c 80009b6: 0002 movs r2, r0 80009b8: 69bb ldr r3, [r7, #24] 80009ba: 1ad3 subs r3, r2, r3 80009bc: 4a9b ldr r2, [pc, #620] ; (8000c2c ) 80009be: 4293 cmp r3, r2 80009c0: d901 bls.n 80009c6 { return HAL_TIMEOUT; 80009c2: 2303 movs r3, #3 80009c4: e12b b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80009c6: 4b98 ldr r3, [pc, #608] ; (8000c28 ) 80009c8: 6a1b ldr r3, [r3, #32] 80009ca: 2202 movs r2, #2 80009cc: 4013 ands r3, r2 80009ce: d0f0 beq.n 80009b2 80009d0: e013 b.n 80009fa } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80009d2: f7ff fd5b bl 800048c 80009d6: 0003 movs r3, r0 80009d8: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80009da: e009 b.n 80009f0 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80009dc: f7ff fd56 bl 800048c 80009e0: 0002 movs r2, r0 80009e2: 69bb ldr r3, [r7, #24] 80009e4: 1ad3 subs r3, r2, r3 80009e6: 4a91 ldr r2, [pc, #580] ; (8000c2c ) 80009e8: 4293 cmp r3, r2 80009ea: d901 bls.n 80009f0 { return HAL_TIMEOUT; 80009ec: 2303 movs r3, #3 80009ee: e116 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80009f0: 4b8d ldr r3, [pc, #564] ; (8000c28 ) 80009f2: 6a1b ldr r3, [r3, #32] 80009f4: 2202 movs r2, #2 80009f6: 4013 ands r3, r2 80009f8: d1f0 bne.n 80009dc } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 80009fa: 231f movs r3, #31 80009fc: 18fb adds r3, r7, r3 80009fe: 781b ldrb r3, [r3, #0] 8000a00: 2b01 cmp r3, #1 8000a02: d105 bne.n 8000a10 { __HAL_RCC_PWR_CLK_DISABLE(); 8000a04: 4b88 ldr r3, [pc, #544] ; (8000c28 ) 8000a06: 69da ldr r2, [r3, #28] 8000a08: 4b87 ldr r3, [pc, #540] ; (8000c28 ) 8000a0a: 4989 ldr r1, [pc, #548] ; (8000c30 ) 8000a0c: 400a ands r2, r1 8000a0e: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8000a10: 687b ldr r3, [r7, #4] 8000a12: 681b ldr r3, [r3, #0] 8000a14: 2210 movs r2, #16 8000a16: 4013 ands r3, r2 8000a18: d063 beq.n 8000ae2 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 8000a1a: 687b ldr r3, [r7, #4] 8000a1c: 695b ldr r3, [r3, #20] 8000a1e: 2b01 cmp r3, #1 8000a20: d12a bne.n 8000a78 { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8000a22: 4b81 ldr r3, [pc, #516] ; (8000c28 ) 8000a24: 6b5a ldr r2, [r3, #52] ; 0x34 8000a26: 4b80 ldr r3, [pc, #512] ; (8000c28 ) 8000a28: 2104 movs r1, #4 8000a2a: 430a orrs r2, r1 8000a2c: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 8000a2e: 4b7e ldr r3, [pc, #504] ; (8000c28 ) 8000a30: 6b5a ldr r2, [r3, #52] ; 0x34 8000a32: 4b7d ldr r3, [pc, #500] ; (8000c28 ) 8000a34: 2101 movs r1, #1 8000a36: 430a orrs r2, r1 8000a38: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000a3a: f7ff fd27 bl 800048c 8000a3e: 0003 movs r3, r0 8000a40: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8000a42: e008 b.n 8000a56 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8000a44: f7ff fd22 bl 800048c 8000a48: 0002 movs r2, r0 8000a4a: 69bb ldr r3, [r7, #24] 8000a4c: 1ad3 subs r3, r2, r3 8000a4e: 2b02 cmp r3, #2 8000a50: d901 bls.n 8000a56 { return HAL_TIMEOUT; 8000a52: 2303 movs r3, #3 8000a54: e0e3 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8000a56: 4b74 ldr r3, [pc, #464] ; (8000c28 ) 8000a58: 6b5b ldr r3, [r3, #52] ; 0x34 8000a5a: 2202 movs r2, #2 8000a5c: 4013 ands r3, r2 8000a5e: d0f1 beq.n 8000a44 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8000a60: 4b71 ldr r3, [pc, #452] ; (8000c28 ) 8000a62: 6b5b ldr r3, [r3, #52] ; 0x34 8000a64: 22f8 movs r2, #248 ; 0xf8 8000a66: 4393 bics r3, r2 8000a68: 0019 movs r1, r3 8000a6a: 687b ldr r3, [r7, #4] 8000a6c: 699b ldr r3, [r3, #24] 8000a6e: 00da lsls r2, r3, #3 8000a70: 4b6d ldr r3, [pc, #436] ; (8000c28 ) 8000a72: 430a orrs r2, r1 8000a74: 635a str r2, [r3, #52] ; 0x34 8000a76: e034 b.n 8000ae2 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8000a78: 687b ldr r3, [r7, #4] 8000a7a: 695b ldr r3, [r3, #20] 8000a7c: 3305 adds r3, #5 8000a7e: d111 bne.n 8000aa4 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8000a80: 4b69 ldr r3, [pc, #420] ; (8000c28 ) 8000a82: 6b5a ldr r2, [r3, #52] ; 0x34 8000a84: 4b68 ldr r3, [pc, #416] ; (8000c28 ) 8000a86: 2104 movs r1, #4 8000a88: 438a bics r2, r1 8000a8a: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8000a8c: 4b66 ldr r3, [pc, #408] ; (8000c28 ) 8000a8e: 6b5b ldr r3, [r3, #52] ; 0x34 8000a90: 22f8 movs r2, #248 ; 0xf8 8000a92: 4393 bics r3, r2 8000a94: 0019 movs r1, r3 8000a96: 687b ldr r3, [r7, #4] 8000a98: 699b ldr r3, [r3, #24] 8000a9a: 00da lsls r2, r3, #3 8000a9c: 4b62 ldr r3, [pc, #392] ; (8000c28 ) 8000a9e: 430a orrs r2, r1 8000aa0: 635a str r2, [r3, #52] ; 0x34 8000aa2: e01e b.n 8000ae2 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8000aa4: 4b60 ldr r3, [pc, #384] ; (8000c28 ) 8000aa6: 6b5a ldr r2, [r3, #52] ; 0x34 8000aa8: 4b5f ldr r3, [pc, #380] ; (8000c28 ) 8000aaa: 2104 movs r1, #4 8000aac: 430a orrs r2, r1 8000aae: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8000ab0: 4b5d ldr r3, [pc, #372] ; (8000c28 ) 8000ab2: 6b5a ldr r2, [r3, #52] ; 0x34 8000ab4: 4b5c ldr r3, [pc, #368] ; (8000c28 ) 8000ab6: 2101 movs r1, #1 8000ab8: 438a bics r2, r1 8000aba: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000abc: f7ff fce6 bl 800048c 8000ac0: 0003 movs r3, r0 8000ac2: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8000ac4: e008 b.n 8000ad8 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8000ac6: f7ff fce1 bl 800048c 8000aca: 0002 movs r2, r0 8000acc: 69bb ldr r3, [r7, #24] 8000ace: 1ad3 subs r3, r2, r3 8000ad0: 2b02 cmp r3, #2 8000ad2: d901 bls.n 8000ad8 { return HAL_TIMEOUT; 8000ad4: 2303 movs r3, #3 8000ad6: e0a2 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8000ad8: 4b53 ldr r3, [pc, #332] ; (8000c28 ) 8000ada: 6b5b ldr r3, [r3, #52] ; 0x34 8000adc: 2202 movs r2, #2 8000ade: 4013 ands r3, r2 8000ae0: d1f1 bne.n 8000ac6 #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8000ae2: 687b ldr r3, [r7, #4] 8000ae4: 6a1b ldr r3, [r3, #32] 8000ae6: 2b00 cmp r3, #0 8000ae8: d100 bne.n 8000aec 8000aea: e097 b.n 8000c1c { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8000aec: 4b4e ldr r3, [pc, #312] ; (8000c28 ) 8000aee: 685b ldr r3, [r3, #4] 8000af0: 220c movs r2, #12 8000af2: 4013 ands r3, r2 8000af4: 2b08 cmp r3, #8 8000af6: d100 bne.n 8000afa 8000af8: e06b b.n 8000bd2 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000afa: 687b ldr r3, [r7, #4] 8000afc: 6a1b ldr r3, [r3, #32] 8000afe: 2b02 cmp r3, #2 8000b00: d14c bne.n 8000b9c assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000b02: 4b49 ldr r3, [pc, #292] ; (8000c28 ) 8000b04: 681a ldr r2, [r3, #0] 8000b06: 4b48 ldr r3, [pc, #288] ; (8000c28 ) 8000b08: 494a ldr r1, [pc, #296] ; (8000c34 ) 8000b0a: 400a ands r2, r1 8000b0c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b0e: f7ff fcbd bl 800048c 8000b12: 0003 movs r3, r0 8000b14: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000b16: e008 b.n 8000b2a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000b18: f7ff fcb8 bl 800048c 8000b1c: 0002 movs r2, r0 8000b1e: 69bb ldr r3, [r7, #24] 8000b20: 1ad3 subs r3, r2, r3 8000b22: 2b02 cmp r3, #2 8000b24: d901 bls.n 8000b2a { return HAL_TIMEOUT; 8000b26: 2303 movs r3, #3 8000b28: e079 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000b2a: 4b3f ldr r3, [pc, #252] ; (8000c28 ) 8000b2c: 681a ldr r2, [r3, #0] 8000b2e: 2380 movs r3, #128 ; 0x80 8000b30: 049b lsls r3, r3, #18 8000b32: 4013 ands r3, r2 8000b34: d1f0 bne.n 8000b18 } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000b36: 4b3c ldr r3, [pc, #240] ; (8000c28 ) 8000b38: 6adb ldr r3, [r3, #44] ; 0x2c 8000b3a: 220f movs r2, #15 8000b3c: 4393 bics r3, r2 8000b3e: 0019 movs r1, r3 8000b40: 687b ldr r3, [r7, #4] 8000b42: 6ada ldr r2, [r3, #44] ; 0x2c 8000b44: 4b38 ldr r3, [pc, #224] ; (8000c28 ) 8000b46: 430a orrs r2, r1 8000b48: 62da str r2, [r3, #44] ; 0x2c 8000b4a: 4b37 ldr r3, [pc, #220] ; (8000c28 ) 8000b4c: 685b ldr r3, [r3, #4] 8000b4e: 4a3a ldr r2, [pc, #232] ; (8000c38 ) 8000b50: 4013 ands r3, r2 8000b52: 0019 movs r1, r3 8000b54: 687b ldr r3, [r7, #4] 8000b56: 6a9a ldr r2, [r3, #40] ; 0x28 8000b58: 687b ldr r3, [r7, #4] 8000b5a: 6a5b ldr r3, [r3, #36] ; 0x24 8000b5c: 431a orrs r2, r3 8000b5e: 4b32 ldr r3, [pc, #200] ; (8000c28 ) 8000b60: 430a orrs r2, r1 8000b62: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8000b64: 4b30 ldr r3, [pc, #192] ; (8000c28 ) 8000b66: 681a ldr r2, [r3, #0] 8000b68: 4b2f ldr r3, [pc, #188] ; (8000c28 ) 8000b6a: 2180 movs r1, #128 ; 0x80 8000b6c: 0449 lsls r1, r1, #17 8000b6e: 430a orrs r2, r1 8000b70: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b72: f7ff fc8b bl 800048c 8000b76: 0003 movs r3, r0 8000b78: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000b7a: e008 b.n 8000b8e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000b7c: f7ff fc86 bl 800048c 8000b80: 0002 movs r2, r0 8000b82: 69bb ldr r3, [r7, #24] 8000b84: 1ad3 subs r3, r2, r3 8000b86: 2b02 cmp r3, #2 8000b88: d901 bls.n 8000b8e { return HAL_TIMEOUT; 8000b8a: 2303 movs r3, #3 8000b8c: e047 b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000b8e: 4b26 ldr r3, [pc, #152] ; (8000c28 ) 8000b90: 681a ldr r2, [r3, #0] 8000b92: 2380 movs r3, #128 ; 0x80 8000b94: 049b lsls r3, r3, #18 8000b96: 4013 ands r3, r2 8000b98: d0f0 beq.n 8000b7c 8000b9a: e03f b.n 8000c1c } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000b9c: 4b22 ldr r3, [pc, #136] ; (8000c28 ) 8000b9e: 681a ldr r2, [r3, #0] 8000ba0: 4b21 ldr r3, [pc, #132] ; (8000c28 ) 8000ba2: 4924 ldr r1, [pc, #144] ; (8000c34 ) 8000ba4: 400a ands r2, r1 8000ba6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ba8: f7ff fc70 bl 800048c 8000bac: 0003 movs r3, r0 8000bae: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000bb0: e008 b.n 8000bc4 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000bb2: f7ff fc6b bl 800048c 8000bb6: 0002 movs r2, r0 8000bb8: 69bb ldr r3, [r7, #24] 8000bba: 1ad3 subs r3, r2, r3 8000bbc: 2b02 cmp r3, #2 8000bbe: d901 bls.n 8000bc4 { return HAL_TIMEOUT; 8000bc0: 2303 movs r3, #3 8000bc2: e02c b.n 8000c1e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000bc4: 4b18 ldr r3, [pc, #96] ; (8000c28 ) 8000bc6: 681a ldr r2, [r3, #0] 8000bc8: 2380 movs r3, #128 ; 0x80 8000bca: 049b lsls r3, r3, #18 8000bcc: 4013 ands r3, r2 8000bce: d1f0 bne.n 8000bb2 8000bd0: e024 b.n 8000c1c } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8000bd2: 687b ldr r3, [r7, #4] 8000bd4: 6a1b ldr r3, [r3, #32] 8000bd6: 2b01 cmp r3, #1 8000bd8: d101 bne.n 8000bde { return HAL_ERROR; 8000bda: 2301 movs r3, #1 8000bdc: e01f b.n 8000c1e } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8000bde: 4b12 ldr r3, [pc, #72] ; (8000c28 ) 8000be0: 685b ldr r3, [r3, #4] 8000be2: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8000be4: 4b10 ldr r3, [pc, #64] ; (8000c28 ) 8000be6: 6adb ldr r3, [r3, #44] ; 0x2c 8000be8: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8000bea: 697a ldr r2, [r7, #20] 8000bec: 2380 movs r3, #128 ; 0x80 8000bee: 025b lsls r3, r3, #9 8000bf0: 401a ands r2, r3 8000bf2: 687b ldr r3, [r7, #4] 8000bf4: 6a5b ldr r3, [r3, #36] ; 0x24 8000bf6: 429a cmp r2, r3 8000bf8: d10e bne.n 8000c18 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8000bfa: 693b ldr r3, [r7, #16] 8000bfc: 220f movs r2, #15 8000bfe: 401a ands r2, r3 8000c00: 687b ldr r3, [r7, #4] 8000c02: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8000c04: 429a cmp r2, r3 8000c06: d107 bne.n 8000c18 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 8000c08: 697a ldr r2, [r7, #20] 8000c0a: 23f0 movs r3, #240 ; 0xf0 8000c0c: 039b lsls r3, r3, #14 8000c0e: 401a ands r2, r3 8000c10: 687b ldr r3, [r7, #4] 8000c12: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8000c14: 429a cmp r2, r3 8000c16: d001 beq.n 8000c1c { return HAL_ERROR; 8000c18: 2301 movs r3, #1 8000c1a: e000 b.n 8000c1e } } } } return HAL_OK; 8000c1c: 2300 movs r3, #0 } 8000c1e: 0018 movs r0, r3 8000c20: 46bd mov sp, r7 8000c22: b008 add sp, #32 8000c24: bd80 pop {r7, pc} 8000c26: 46c0 nop ; (mov r8, r8) 8000c28: 40021000 .word 0x40021000 8000c2c: 00001388 .word 0x00001388 8000c30: efffffff .word 0xefffffff 8000c34: feffffff .word 0xfeffffff 8000c38: ffc2ffff .word 0xffc2ffff 08000c3c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8000c3c: b580 push {r7, lr} 8000c3e: b084 sub sp, #16 8000c40: af00 add r7, sp, #0 8000c42: 6078 str r0, [r7, #4] 8000c44: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8000c46: 687b ldr r3, [r7, #4] 8000c48: 2b00 cmp r3, #0 8000c4a: d101 bne.n 8000c50 { return HAL_ERROR; 8000c4c: 2301 movs r3, #1 8000c4e: e0b3 b.n 8000db8 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8000c50: 4b5b ldr r3, [pc, #364] ; (8000dc0 ) 8000c52: 681b ldr r3, [r3, #0] 8000c54: 2201 movs r2, #1 8000c56: 4013 ands r3, r2 8000c58: 683a ldr r2, [r7, #0] 8000c5a: 429a cmp r2, r3 8000c5c: d911 bls.n 8000c82 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8000c5e: 4b58 ldr r3, [pc, #352] ; (8000dc0 ) 8000c60: 681b ldr r3, [r3, #0] 8000c62: 2201 movs r2, #1 8000c64: 4393 bics r3, r2 8000c66: 0019 movs r1, r3 8000c68: 4b55 ldr r3, [pc, #340] ; (8000dc0 ) 8000c6a: 683a ldr r2, [r7, #0] 8000c6c: 430a orrs r2, r1 8000c6e: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8000c70: 4b53 ldr r3, [pc, #332] ; (8000dc0 ) 8000c72: 681b ldr r3, [r3, #0] 8000c74: 2201 movs r2, #1 8000c76: 4013 ands r3, r2 8000c78: 683a ldr r2, [r7, #0] 8000c7a: 429a cmp r2, r3 8000c7c: d001 beq.n 8000c82 { return HAL_ERROR; 8000c7e: 2301 movs r3, #1 8000c80: e09a b.n 8000db8 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8000c82: 687b ldr r3, [r7, #4] 8000c84: 681b ldr r3, [r3, #0] 8000c86: 2202 movs r2, #2 8000c88: 4013 ands r3, r2 8000c8a: d015 beq.n 8000cb8 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000c8c: 687b ldr r3, [r7, #4] 8000c8e: 681b ldr r3, [r3, #0] 8000c90: 2204 movs r2, #4 8000c92: 4013 ands r3, r2 8000c94: d006 beq.n 8000ca4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8000c96: 4b4b ldr r3, [pc, #300] ; (8000dc4 ) 8000c98: 685a ldr r2, [r3, #4] 8000c9a: 4b4a ldr r3, [pc, #296] ; (8000dc4 ) 8000c9c: 21e0 movs r1, #224 ; 0xe0 8000c9e: 00c9 lsls r1, r1, #3 8000ca0: 430a orrs r2, r1 8000ca2: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8000ca4: 4b47 ldr r3, [pc, #284] ; (8000dc4 ) 8000ca6: 685b ldr r3, [r3, #4] 8000ca8: 22f0 movs r2, #240 ; 0xf0 8000caa: 4393 bics r3, r2 8000cac: 0019 movs r1, r3 8000cae: 687b ldr r3, [r7, #4] 8000cb0: 689a ldr r2, [r3, #8] 8000cb2: 4b44 ldr r3, [pc, #272] ; (8000dc4 ) 8000cb4: 430a orrs r2, r1 8000cb6: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8000cb8: 687b ldr r3, [r7, #4] 8000cba: 681b ldr r3, [r3, #0] 8000cbc: 2201 movs r2, #1 8000cbe: 4013 ands r3, r2 8000cc0: d040 beq.n 8000d44 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8000cc2: 687b ldr r3, [r7, #4] 8000cc4: 685b ldr r3, [r3, #4] 8000cc6: 2b01 cmp r3, #1 8000cc8: d107 bne.n 8000cda { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000cca: 4b3e ldr r3, [pc, #248] ; (8000dc4 ) 8000ccc: 681a ldr r2, [r3, #0] 8000cce: 2380 movs r3, #128 ; 0x80 8000cd0: 029b lsls r3, r3, #10 8000cd2: 4013 ands r3, r2 8000cd4: d114 bne.n 8000d00 { return HAL_ERROR; 8000cd6: 2301 movs r3, #1 8000cd8: e06e b.n 8000db8 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8000cda: 687b ldr r3, [r7, #4] 8000cdc: 685b ldr r3, [r3, #4] 8000cde: 2b02 cmp r3, #2 8000ce0: d107 bne.n 8000cf2 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000ce2: 4b38 ldr r3, [pc, #224] ; (8000dc4 ) 8000ce4: 681a ldr r2, [r3, #0] 8000ce6: 2380 movs r3, #128 ; 0x80 8000ce8: 049b lsls r3, r3, #18 8000cea: 4013 ands r3, r2 8000cec: d108 bne.n 8000d00 { return HAL_ERROR; 8000cee: 2301 movs r3, #1 8000cf0: e062 b.n 8000db8 #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000cf2: 4b34 ldr r3, [pc, #208] ; (8000dc4 ) 8000cf4: 681b ldr r3, [r3, #0] 8000cf6: 2202 movs r2, #2 8000cf8: 4013 ands r3, r2 8000cfa: d101 bne.n 8000d00 { return HAL_ERROR; 8000cfc: 2301 movs r3, #1 8000cfe: e05b b.n 8000db8 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8000d00: 4b30 ldr r3, [pc, #192] ; (8000dc4 ) 8000d02: 685b ldr r3, [r3, #4] 8000d04: 2203 movs r2, #3 8000d06: 4393 bics r3, r2 8000d08: 0019 movs r1, r3 8000d0a: 687b ldr r3, [r7, #4] 8000d0c: 685a ldr r2, [r3, #4] 8000d0e: 4b2d ldr r3, [pc, #180] ; (8000dc4 ) 8000d10: 430a orrs r2, r1 8000d12: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000d14: f7ff fbba bl 800048c 8000d18: 0003 movs r3, r0 8000d1a: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8000d1c: e009 b.n 8000d32 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8000d1e: f7ff fbb5 bl 800048c 8000d22: 0002 movs r2, r0 8000d24: 68fb ldr r3, [r7, #12] 8000d26: 1ad3 subs r3, r2, r3 8000d28: 4a27 ldr r2, [pc, #156] ; (8000dc8 ) 8000d2a: 4293 cmp r3, r2 8000d2c: d901 bls.n 8000d32 { return HAL_TIMEOUT; 8000d2e: 2303 movs r3, #3 8000d30: e042 b.n 8000db8 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8000d32: 4b24 ldr r3, [pc, #144] ; (8000dc4 ) 8000d34: 685b ldr r3, [r3, #4] 8000d36: 220c movs r2, #12 8000d38: 401a ands r2, r3 8000d3a: 687b ldr r3, [r7, #4] 8000d3c: 685b ldr r3, [r3, #4] 8000d3e: 009b lsls r3, r3, #2 8000d40: 429a cmp r2, r3 8000d42: d1ec bne.n 8000d1e } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8000d44: 4b1e ldr r3, [pc, #120] ; (8000dc0 ) 8000d46: 681b ldr r3, [r3, #0] 8000d48: 2201 movs r2, #1 8000d4a: 4013 ands r3, r2 8000d4c: 683a ldr r2, [r7, #0] 8000d4e: 429a cmp r2, r3 8000d50: d211 bcs.n 8000d76 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8000d52: 4b1b ldr r3, [pc, #108] ; (8000dc0 ) 8000d54: 681b ldr r3, [r3, #0] 8000d56: 2201 movs r2, #1 8000d58: 4393 bics r3, r2 8000d5a: 0019 movs r1, r3 8000d5c: 4b18 ldr r3, [pc, #96] ; (8000dc0 ) 8000d5e: 683a ldr r2, [r7, #0] 8000d60: 430a orrs r2, r1 8000d62: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8000d64: 4b16 ldr r3, [pc, #88] ; (8000dc0 ) 8000d66: 681b ldr r3, [r3, #0] 8000d68: 2201 movs r2, #1 8000d6a: 4013 ands r3, r2 8000d6c: 683a ldr r2, [r7, #0] 8000d6e: 429a cmp r2, r3 8000d70: d001 beq.n 8000d76 { return HAL_ERROR; 8000d72: 2301 movs r3, #1 8000d74: e020 b.n 8000db8 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000d76: 687b ldr r3, [r7, #4] 8000d78: 681b ldr r3, [r3, #0] 8000d7a: 2204 movs r2, #4 8000d7c: 4013 ands r3, r2 8000d7e: d009 beq.n 8000d94 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8000d80: 4b10 ldr r3, [pc, #64] ; (8000dc4 ) 8000d82: 685b ldr r3, [r3, #4] 8000d84: 4a11 ldr r2, [pc, #68] ; (8000dcc ) 8000d86: 4013 ands r3, r2 8000d88: 0019 movs r1, r3 8000d8a: 687b ldr r3, [r7, #4] 8000d8c: 68da ldr r2, [r3, #12] 8000d8e: 4b0d ldr r3, [pc, #52] ; (8000dc4 ) 8000d90: 430a orrs r2, r1 8000d92: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8000d94: f000 f820 bl 8000dd8 8000d98: 0001 movs r1, r0 8000d9a: 4b0a ldr r3, [pc, #40] ; (8000dc4 ) 8000d9c: 685b ldr r3, [r3, #4] 8000d9e: 091b lsrs r3, r3, #4 8000da0: 220f movs r2, #15 8000da2: 4013 ands r3, r2 8000da4: 4a0a ldr r2, [pc, #40] ; (8000dd0 ) 8000da6: 5cd3 ldrb r3, [r2, r3] 8000da8: 000a movs r2, r1 8000daa: 40da lsrs r2, r3 8000dac: 4b09 ldr r3, [pc, #36] ; (8000dd4 ) 8000dae: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8000db0: 2003 movs r0, #3 8000db2: f7ff fb25 bl 8000400 return HAL_OK; 8000db6: 2300 movs r3, #0 } 8000db8: 0018 movs r0, r3 8000dba: 46bd mov sp, r7 8000dbc: b004 add sp, #16 8000dbe: bd80 pop {r7, pc} 8000dc0: 40022000 .word 0x40022000 8000dc4: 40021000 .word 0x40021000 8000dc8: 00001388 .word 0x00001388 8000dcc: fffff8ff .word 0xfffff8ff 8000dd0: 08000f30 .word 0x08000f30 8000dd4: 20000000 .word 0x20000000 08000dd8 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8000dd8: b590 push {r4, r7, lr} 8000dda: b08f sub sp, #60 ; 0x3c 8000ddc: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 8000dde: 2314 movs r3, #20 8000de0: 18fb adds r3, r7, r3 8000de2: 4a2b ldr r2, [pc, #172] ; (8000e90 ) 8000de4: ca13 ldmia r2!, {r0, r1, r4} 8000de6: c313 stmia r3!, {r0, r1, r4} 8000de8: 6812 ldr r2, [r2, #0] 8000dea: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8000dec: 1d3b adds r3, r7, #4 8000dee: 4a29 ldr r2, [pc, #164] ; (8000e94 ) 8000df0: ca13 ldmia r2!, {r0, r1, r4} 8000df2: c313 stmia r3!, {r0, r1, r4} 8000df4: 6812 ldr r2, [r2, #0] 8000df6: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8000df8: 2300 movs r3, #0 8000dfa: 62fb str r3, [r7, #44] ; 0x2c 8000dfc: 2300 movs r3, #0 8000dfe: 62bb str r3, [r7, #40] ; 0x28 8000e00: 2300 movs r3, #0 8000e02: 637b str r3, [r7, #52] ; 0x34 8000e04: 2300 movs r3, #0 8000e06: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8000e08: 2300 movs r3, #0 8000e0a: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 8000e0c: 4b22 ldr r3, [pc, #136] ; (8000e98 ) 8000e0e: 685b ldr r3, [r3, #4] 8000e10: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8000e12: 6afb ldr r3, [r7, #44] ; 0x2c 8000e14: 220c movs r2, #12 8000e16: 4013 ands r3, r2 8000e18: 2b04 cmp r3, #4 8000e1a: d002 beq.n 8000e22 8000e1c: 2b08 cmp r3, #8 8000e1e: d003 beq.n 8000e28 8000e20: e02d b.n 8000e7e { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8000e22: 4b1e ldr r3, [pc, #120] ; (8000e9c ) 8000e24: 633b str r3, [r7, #48] ; 0x30 break; 8000e26: e02d b.n 8000e84 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 8000e28: 6afb ldr r3, [r7, #44] ; 0x2c 8000e2a: 0c9b lsrs r3, r3, #18 8000e2c: 220f movs r2, #15 8000e2e: 4013 ands r3, r2 8000e30: 2214 movs r2, #20 8000e32: 18ba adds r2, r7, r2 8000e34: 5cd3 ldrb r3, [r2, r3] 8000e36: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 8000e38: 4b17 ldr r3, [pc, #92] ; (8000e98 ) 8000e3a: 6adb ldr r3, [r3, #44] ; 0x2c 8000e3c: 220f movs r2, #15 8000e3e: 4013 ands r3, r2 8000e40: 1d3a adds r2, r7, #4 8000e42: 5cd3 ldrb r3, [r2, r3] 8000e44: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 8000e46: 6afa ldr r2, [r7, #44] ; 0x2c 8000e48: 2380 movs r3, #128 ; 0x80 8000e4a: 025b lsls r3, r3, #9 8000e4c: 4013 ands r3, r2 8000e4e: d009 beq.n 8000e64 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8000e50: 6ab9 ldr r1, [r7, #40] ; 0x28 8000e52: 4812 ldr r0, [pc, #72] ; (8000e9c ) 8000e54: f7ff f958 bl 8000108 <__udivsi3> 8000e58: 0003 movs r3, r0 8000e5a: 001a movs r2, r3 8000e5c: 6a7b ldr r3, [r7, #36] ; 0x24 8000e5e: 4353 muls r3, r2 8000e60: 637b str r3, [r7, #52] ; 0x34 8000e62: e009 b.n 8000e78 #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 8000e64: 6a79 ldr r1, [r7, #36] ; 0x24 8000e66: 000a movs r2, r1 8000e68: 0152 lsls r2, r2, #5 8000e6a: 1a52 subs r2, r2, r1 8000e6c: 0193 lsls r3, r2, #6 8000e6e: 1a9b subs r3, r3, r2 8000e70: 00db lsls r3, r3, #3 8000e72: 185b adds r3, r3, r1 8000e74: 021b lsls r3, r3, #8 8000e76: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 8000e78: 6b7b ldr r3, [r7, #52] ; 0x34 8000e7a: 633b str r3, [r7, #48] ; 0x30 break; 8000e7c: e002 b.n 8000e84 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8000e7e: 4b07 ldr r3, [pc, #28] ; (8000e9c ) 8000e80: 633b str r3, [r7, #48] ; 0x30 break; 8000e82: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8000e84: 6b3b ldr r3, [r7, #48] ; 0x30 } 8000e86: 0018 movs r0, r3 8000e88: 46bd mov sp, r7 8000e8a: b00f add sp, #60 ; 0x3c 8000e8c: bd90 pop {r4, r7, pc} 8000e8e: 46c0 nop ; (mov r8, r8) 8000e90: 08000f10 .word 0x08000f10 8000e94: 08000f20 .word 0x08000f20 8000e98: 40021000 .word 0x40021000 8000e9c: 007a1200 .word 0x007a1200 08000ea0 <__libc_init_array>: 8000ea0: b570 push {r4, r5, r6, lr} 8000ea2: 2600 movs r6, #0 8000ea4: 4d0c ldr r5, [pc, #48] ; (8000ed8 <__libc_init_array+0x38>) 8000ea6: 4c0d ldr r4, [pc, #52] ; (8000edc <__libc_init_array+0x3c>) 8000ea8: 1b64 subs r4, r4, r5 8000eaa: 10a4 asrs r4, r4, #2 8000eac: 42a6 cmp r6, r4 8000eae: d109 bne.n 8000ec4 <__libc_init_array+0x24> 8000eb0: 2600 movs r6, #0 8000eb2: f000 f821 bl 8000ef8 <_init> 8000eb6: 4d0a ldr r5, [pc, #40] ; (8000ee0 <__libc_init_array+0x40>) 8000eb8: 4c0a ldr r4, [pc, #40] ; (8000ee4 <__libc_init_array+0x44>) 8000eba: 1b64 subs r4, r4, r5 8000ebc: 10a4 asrs r4, r4, #2 8000ebe: 42a6 cmp r6, r4 8000ec0: d105 bne.n 8000ece <__libc_init_array+0x2e> 8000ec2: bd70 pop {r4, r5, r6, pc} 8000ec4: 00b3 lsls r3, r6, #2 8000ec6: 58eb ldr r3, [r5, r3] 8000ec8: 4798 blx r3 8000eca: 3601 adds r6, #1 8000ecc: e7ee b.n 8000eac <__libc_init_array+0xc> 8000ece: 00b3 lsls r3, r6, #2 8000ed0: 58eb ldr r3, [r5, r3] 8000ed2: 4798 blx r3 8000ed4: 3601 adds r6, #1 8000ed6: e7f2 b.n 8000ebe <__libc_init_array+0x1e> 8000ed8: 08000f40 .word 0x08000f40 8000edc: 08000f40 .word 0x08000f40 8000ee0: 08000f40 .word 0x08000f40 8000ee4: 08000f44 .word 0x08000f44 08000ee8 : 8000ee8: 0003 movs r3, r0 8000eea: 1882 adds r2, r0, r2 8000eec: 4293 cmp r3, r2 8000eee: d100 bne.n 8000ef2 8000ef0: 4770 bx lr 8000ef2: 7019 strb r1, [r3, #0] 8000ef4: 3301 adds r3, #1 8000ef6: e7f9 b.n 8000eec 08000ef8 <_init>: 8000ef8: b5f8 push {r3, r4, r5, r6, r7, lr} 8000efa: 46c0 nop ; (mov r8, r8) 8000efc: bcf8 pop {r3, r4, r5, r6, r7} 8000efe: bc08 pop {r3} 8000f00: 469e mov lr, r3 8000f02: 4770 bx lr 08000f04 <_fini>: 8000f04: b5f8 push {r3, r4, r5, r6, r7, lr} 8000f06: 46c0 nop ; (mov r8, r8) 8000f08: bcf8 pop {r3, r4, r5, r6, r7} 8000f0a: bc08 pop {r3} 8000f0c: 469e mov lr, r3 8000f0e: 4770 bx lr