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motor_controller/Debug/Motor_Controller.list
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Motor_Controller.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002b7c 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000005c 08002c3c 08002c3c 00012c3c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002c98 08002c98 00020010 2**0
CONTENTS
4 .ARM 00000000 08002c98 08002c98 00020010 2**0
CONTENTS
5 .preinit_array 00000000 08002c98 08002c98 00020010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002c98 08002c98 00012c98 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002c9c 08002c9c 00012c9c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000010 20000000 08002ca0 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000bc 20000010 08002cb0 00020010 2**2
ALLOC
10 ._user_heap_stack 00000804 200000cc 08002cb0 000200cc 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 00020010 2**0
CONTENTS, READONLY
12 .debug_info 00004dc5 00000000 00000000 00020038 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001353 00000000 00000000 00024dfd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000004b0 00000000 00000000 00026150 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 000003f8 00000000 00000000 00026600 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0000e935 00000000 00000000 000269f8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00006f12 00000000 00000000 0003532d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000566a2 00000000 00000000 0003c23f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 000928e1 2**0
CONTENTS, READONLY
20 .debug_frame 00000eb8 00000000 00000000 00092934 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 20000010 .word 0x20000010
80000e0: 00000000 .word 0x00000000
80000e4: 08002c24 .word 0x08002c24
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000014 .word 0x20000014
8000104: 08002c24 .word 0x08002c24
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__divsi3>:
800021c: 4603 mov r3, r0
800021e: 430b orrs r3, r1
8000220: d47f bmi.n 8000322 <__divsi3+0x106>
8000222: 2200 movs r2, #0
8000224: 0843 lsrs r3, r0, #1
8000226: 428b cmp r3, r1
8000228: d374 bcc.n 8000314 <__divsi3+0xf8>
800022a: 0903 lsrs r3, r0, #4
800022c: 428b cmp r3, r1
800022e: d35f bcc.n 80002f0 <__divsi3+0xd4>
8000230: 0a03 lsrs r3, r0, #8
8000232: 428b cmp r3, r1
8000234: d344 bcc.n 80002c0 <__divsi3+0xa4>
8000236: 0b03 lsrs r3, r0, #12
8000238: 428b cmp r3, r1
800023a: d328 bcc.n 800028e <__divsi3+0x72>
800023c: 0c03 lsrs r3, r0, #16
800023e: 428b cmp r3, r1
8000240: d30d bcc.n 800025e <__divsi3+0x42>
8000242: 22ff movs r2, #255 ; 0xff
8000244: 0209 lsls r1, r1, #8
8000246: ba12 rev r2, r2
8000248: 0c03 lsrs r3, r0, #16
800024a: 428b cmp r3, r1
800024c: d302 bcc.n 8000254 <__divsi3+0x38>
800024e: 1212 asrs r2, r2, #8
8000250: 0209 lsls r1, r1, #8
8000252: d065 beq.n 8000320 <__divsi3+0x104>
8000254: 0b03 lsrs r3, r0, #12
8000256: 428b cmp r3, r1
8000258: d319 bcc.n 800028e <__divsi3+0x72>
800025a: e000 b.n 800025e <__divsi3+0x42>
800025c: 0a09 lsrs r1, r1, #8
800025e: 0bc3 lsrs r3, r0, #15
8000260: 428b cmp r3, r1
8000262: d301 bcc.n 8000268 <__divsi3+0x4c>
8000264: 03cb lsls r3, r1, #15
8000266: 1ac0 subs r0, r0, r3
8000268: 4152 adcs r2, r2
800026a: 0b83 lsrs r3, r0, #14
800026c: 428b cmp r3, r1
800026e: d301 bcc.n 8000274 <__divsi3+0x58>
8000270: 038b lsls r3, r1, #14
8000272: 1ac0 subs r0, r0, r3
8000274: 4152 adcs r2, r2
8000276: 0b43 lsrs r3, r0, #13
8000278: 428b cmp r3, r1
800027a: d301 bcc.n 8000280 <__divsi3+0x64>
800027c: 034b lsls r3, r1, #13
800027e: 1ac0 subs r0, r0, r3
8000280: 4152 adcs r2, r2
8000282: 0b03 lsrs r3, r0, #12
8000284: 428b cmp r3, r1
8000286: d301 bcc.n 800028c <__divsi3+0x70>
8000288: 030b lsls r3, r1, #12
800028a: 1ac0 subs r0, r0, r3
800028c: 4152 adcs r2, r2
800028e: 0ac3 lsrs r3, r0, #11
8000290: 428b cmp r3, r1
8000292: d301 bcc.n 8000298 <__divsi3+0x7c>
8000294: 02cb lsls r3, r1, #11
8000296: 1ac0 subs r0, r0, r3
8000298: 4152 adcs r2, r2
800029a: 0a83 lsrs r3, r0, #10
800029c: 428b cmp r3, r1
800029e: d301 bcc.n 80002a4 <__divsi3+0x88>
80002a0: 028b lsls r3, r1, #10
80002a2: 1ac0 subs r0, r0, r3
80002a4: 4152 adcs r2, r2
80002a6: 0a43 lsrs r3, r0, #9
80002a8: 428b cmp r3, r1
80002aa: d301 bcc.n 80002b0 <__divsi3+0x94>
80002ac: 024b lsls r3, r1, #9
80002ae: 1ac0 subs r0, r0, r3
80002b0: 4152 adcs r2, r2
80002b2: 0a03 lsrs r3, r0, #8
80002b4: 428b cmp r3, r1
80002b6: d301 bcc.n 80002bc <__divsi3+0xa0>
80002b8: 020b lsls r3, r1, #8
80002ba: 1ac0 subs r0, r0, r3
80002bc: 4152 adcs r2, r2
80002be: d2cd bcs.n 800025c <__divsi3+0x40>
80002c0: 09c3 lsrs r3, r0, #7
80002c2: 428b cmp r3, r1
80002c4: d301 bcc.n 80002ca <__divsi3+0xae>
80002c6: 01cb lsls r3, r1, #7
80002c8: 1ac0 subs r0, r0, r3
80002ca: 4152 adcs r2, r2
80002cc: 0983 lsrs r3, r0, #6
80002ce: 428b cmp r3, r1
80002d0: d301 bcc.n 80002d6 <__divsi3+0xba>
80002d2: 018b lsls r3, r1, #6
80002d4: 1ac0 subs r0, r0, r3
80002d6: 4152 adcs r2, r2
80002d8: 0943 lsrs r3, r0, #5
80002da: 428b cmp r3, r1
80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6>
80002de: 014b lsls r3, r1, #5
80002e0: 1ac0 subs r0, r0, r3
80002e2: 4152 adcs r2, r2
80002e4: 0903 lsrs r3, r0, #4
80002e6: 428b cmp r3, r1
80002e8: d301 bcc.n 80002ee <__divsi3+0xd2>
80002ea: 010b lsls r3, r1, #4
80002ec: 1ac0 subs r0, r0, r3
80002ee: 4152 adcs r2, r2
80002f0: 08c3 lsrs r3, r0, #3
80002f2: 428b cmp r3, r1
80002f4: d301 bcc.n 80002fa <__divsi3+0xde>
80002f6: 00cb lsls r3, r1, #3
80002f8: 1ac0 subs r0, r0, r3
80002fa: 4152 adcs r2, r2
80002fc: 0883 lsrs r3, r0, #2
80002fe: 428b cmp r3, r1
8000300: d301 bcc.n 8000306 <__divsi3+0xea>
8000302: 008b lsls r3, r1, #2
8000304: 1ac0 subs r0, r0, r3
8000306: 4152 adcs r2, r2
8000308: 0843 lsrs r3, r0, #1
800030a: 428b cmp r3, r1
800030c: d301 bcc.n 8000312 <__divsi3+0xf6>
800030e: 004b lsls r3, r1, #1
8000310: 1ac0 subs r0, r0, r3
8000312: 4152 adcs r2, r2
8000314: 1a41 subs r1, r0, r1
8000316: d200 bcs.n 800031a <__divsi3+0xfe>
8000318: 4601 mov r1, r0
800031a: 4152 adcs r2, r2
800031c: 4610 mov r0, r2
800031e: 4770 bx lr
8000320: e05d b.n 80003de <__divsi3+0x1c2>
8000322: 0fca lsrs r2, r1, #31
8000324: d000 beq.n 8000328 <__divsi3+0x10c>
8000326: 4249 negs r1, r1
8000328: 1003 asrs r3, r0, #32
800032a: d300 bcc.n 800032e <__divsi3+0x112>
800032c: 4240 negs r0, r0
800032e: 4053 eors r3, r2
8000330: 2200 movs r2, #0
8000332: 469c mov ip, r3
8000334: 0903 lsrs r3, r0, #4
8000336: 428b cmp r3, r1
8000338: d32d bcc.n 8000396 <__divsi3+0x17a>
800033a: 0a03 lsrs r3, r0, #8
800033c: 428b cmp r3, r1
800033e: d312 bcc.n 8000366 <__divsi3+0x14a>
8000340: 22fc movs r2, #252 ; 0xfc
8000342: 0189 lsls r1, r1, #6
8000344: ba12 rev r2, r2
8000346: 0a03 lsrs r3, r0, #8
8000348: 428b cmp r3, r1
800034a: d30c bcc.n 8000366 <__divsi3+0x14a>
800034c: 0189 lsls r1, r1, #6
800034e: 1192 asrs r2, r2, #6
8000350: 428b cmp r3, r1
8000352: d308 bcc.n 8000366 <__divsi3+0x14a>
8000354: 0189 lsls r1, r1, #6
8000356: 1192 asrs r2, r2, #6
8000358: 428b cmp r3, r1
800035a: d304 bcc.n 8000366 <__divsi3+0x14a>
800035c: 0189 lsls r1, r1, #6
800035e: d03a beq.n 80003d6 <__divsi3+0x1ba>
8000360: 1192 asrs r2, r2, #6
8000362: e000 b.n 8000366 <__divsi3+0x14a>
8000364: 0989 lsrs r1, r1, #6
8000366: 09c3 lsrs r3, r0, #7
8000368: 428b cmp r3, r1
800036a: d301 bcc.n 8000370 <__divsi3+0x154>
800036c: 01cb lsls r3, r1, #7
800036e: 1ac0 subs r0, r0, r3
8000370: 4152 adcs r2, r2
8000372: 0983 lsrs r3, r0, #6
8000374: 428b cmp r3, r1
8000376: d301 bcc.n 800037c <__divsi3+0x160>
8000378: 018b lsls r3, r1, #6
800037a: 1ac0 subs r0, r0, r3
800037c: 4152 adcs r2, r2
800037e: 0943 lsrs r3, r0, #5
8000380: 428b cmp r3, r1
8000382: d301 bcc.n 8000388 <__divsi3+0x16c>
8000384: 014b lsls r3, r1, #5
8000386: 1ac0 subs r0, r0, r3
8000388: 4152 adcs r2, r2
800038a: 0903 lsrs r3, r0, #4
800038c: 428b cmp r3, r1
800038e: d301 bcc.n 8000394 <__divsi3+0x178>
8000390: 010b lsls r3, r1, #4
8000392: 1ac0 subs r0, r0, r3
8000394: 4152 adcs r2, r2
8000396: 08c3 lsrs r3, r0, #3
8000398: 428b cmp r3, r1
800039a: d301 bcc.n 80003a0 <__divsi3+0x184>
800039c: 00cb lsls r3, r1, #3
800039e: 1ac0 subs r0, r0, r3
80003a0: 4152 adcs r2, r2
80003a2: 0883 lsrs r3, r0, #2
80003a4: 428b cmp r3, r1
80003a6: d301 bcc.n 80003ac <__divsi3+0x190>
80003a8: 008b lsls r3, r1, #2
80003aa: 1ac0 subs r0, r0, r3
80003ac: 4152 adcs r2, r2
80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148>
80003b0: 0843 lsrs r3, r0, #1
80003b2: 428b cmp r3, r1
80003b4: d301 bcc.n 80003ba <__divsi3+0x19e>
80003b6: 004b lsls r3, r1, #1
80003b8: 1ac0 subs r0, r0, r3
80003ba: 4152 adcs r2, r2
80003bc: 1a41 subs r1, r0, r1
80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6>
80003c0: 4601 mov r1, r0
80003c2: 4663 mov r3, ip
80003c4: 4152 adcs r2, r2
80003c6: 105b asrs r3, r3, #1
80003c8: 4610 mov r0, r2
80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4>
80003cc: 4240 negs r0, r0
80003ce: 2b00 cmp r3, #0
80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8>
80003d2: 4249 negs r1, r1
80003d4: 4770 bx lr
80003d6: 4663 mov r3, ip
80003d8: 105b asrs r3, r3, #1
80003da: d300 bcc.n 80003de <__divsi3+0x1c2>
80003dc: 4240 negs r0, r0
80003de: b501 push {r0, lr}
80003e0: 2000 movs r0, #0
80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0>
80003e6: bd02 pop {r1, pc}
080003e8 <__aeabi_idivmod>:
80003e8: 2900 cmp r1, #0
80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2>
80003ec: e716 b.n 800021c <__divsi3>
80003ee: 4770 bx lr
080003f0 <__aeabi_idiv0>:
80003f0: 4770 bx lr
80003f2: 46c0 nop ; (mov r8, r8)
080003f4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80003f4: b580 push {r7, lr}
80003f6: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80003f8: f000 f9e0 bl 80007bc <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80003fc: f000 f807 bl 800040e <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000400: f000 f8b2 bl 8000568 <MX_GPIO_Init>
MX_ADC_Init();
8000404: f000 f854 bl 80004b0 <MX_ADC_Init>
/* USER CODE BEGIN 2 */
mymain();
8000408: f001 feea bl 80021e0 <mymain>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
800040c: e7fe b.n 800040c <main+0x18>
0800040e <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800040e: b590 push {r4, r7, lr}
8000410: b091 sub sp, #68 ; 0x44
8000412: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000414: 2410 movs r4, #16
8000416: 193b adds r3, r7, r4
8000418: 0018 movs r0, r3
800041a: 2330 movs r3, #48 ; 0x30
800041c: 001a movs r2, r3
800041e: 2100 movs r1, #0
8000420: f002 fbf8 bl 8002c14 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000424: 003b movs r3, r7
8000426: 0018 movs r0, r3
8000428: 2310 movs r3, #16
800042a: 001a movs r2, r3
800042c: 2100 movs r1, #0
800042e: f002 fbf1 bl 8002c14 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14;
8000432: 0021 movs r1, r4
8000434: 187b adds r3, r7, r1
8000436: 2212 movs r2, #18
8000438: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800043a: 187b adds r3, r7, r1
800043c: 2201 movs r2, #1
800043e: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
8000440: 187b adds r3, r7, r1
8000442: 2201 movs r2, #1
8000444: 615a str r2, [r3, #20]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000446: 187b adds r3, r7, r1
8000448: 2210 movs r2, #16
800044a: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSI14CalibrationValue = 16;
800044c: 187b adds r3, r7, r1
800044e: 2210 movs r2, #16
8000450: 619a str r2, [r3, #24]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000452: 187b adds r3, r7, r1
8000454: 2202 movs r2, #2
8000456: 621a str r2, [r3, #32]
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000458: 187b adds r3, r7, r1
800045a: 2200 movs r2, #0
800045c: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
800045e: 187b adds r3, r7, r1
8000460: 22a0 movs r2, #160 ; 0xa0
8000462: 0392 lsls r2, r2, #14
8000464: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
8000466: 187b adds r3, r7, r1
8000468: 2200 movs r2, #0
800046a: 62da str r2, [r3, #44] ; 0x2c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800046c: 187b adds r3, r7, r1
800046e: 0018 movs r0, r3
8000470: f001 f87e bl 8001570 <HAL_RCC_OscConfig>
8000474: 1e03 subs r3, r0, #0
8000476: d001 beq.n 800047c <SystemClock_Config+0x6e>
{
Error_Handler();
8000478: f000 f8ea bl 8000650 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800047c: 003b movs r3, r7
800047e: 2207 movs r2, #7
8000480: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000482: 003b movs r3, r7
8000484: 2202 movs r2, #2
8000486: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000488: 003b movs r3, r7
800048a: 2200 movs r2, #0
800048c: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800048e: 003b movs r3, r7
8000490: 2200 movs r2, #0
8000492: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
8000494: 003b movs r3, r7
8000496: 2101 movs r1, #1
8000498: 0018 movs r0, r3
800049a: f001 fb83 bl 8001ba4 <HAL_RCC_ClockConfig>
800049e: 1e03 subs r3, r0, #0
80004a0: d001 beq.n 80004a6 <SystemClock_Config+0x98>
{
Error_Handler();
80004a2: f000 f8d5 bl 8000650 <Error_Handler>
}
}
80004a6: 46c0 nop ; (mov r8, r8)
80004a8: 46bd mov sp, r7
80004aa: b011 add sp, #68 ; 0x44
80004ac: bd90 pop {r4, r7, pc}
...
080004b0 <MX_ADC_Init>:
* @brief ADC Initialization Function
* @param None
* @retval None
*/
static void MX_ADC_Init(void)
{
80004b0: b580 push {r7, lr}
80004b2: b084 sub sp, #16
80004b4: af00 add r7, sp, #0
/* USER CODE BEGIN ADC_Init 0 */
/* USER CODE END ADC_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80004b6: 1d3b adds r3, r7, #4
80004b8: 0018 movs r0, r3
80004ba: 230c movs r3, #12
80004bc: 001a movs r2, r3
80004be: 2100 movs r1, #0
80004c0: f002 fba8 bl 8002c14 <memset>
/* USER CODE BEGIN ADC_Init 1 */
/* USER CODE END ADC_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc.Instance = ADC1;
80004c4: 4b26 ldr r3, [pc, #152] ; (8000560 <MX_ADC_Init+0xb0>)
80004c6: 4a27 ldr r2, [pc, #156] ; (8000564 <MX_ADC_Init+0xb4>)
80004c8: 601a str r2, [r3, #0]
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
80004ca: 4b25 ldr r3, [pc, #148] ; (8000560 <MX_ADC_Init+0xb0>)
80004cc: 2200 movs r2, #0
80004ce: 605a str r2, [r3, #4]
hadc.Init.Resolution = ADC_RESOLUTION_12B;
80004d0: 4b23 ldr r3, [pc, #140] ; (8000560 <MX_ADC_Init+0xb0>)
80004d2: 2200 movs r2, #0
80004d4: 609a str r2, [r3, #8]
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80004d6: 4b22 ldr r3, [pc, #136] ; (8000560 <MX_ADC_Init+0xb0>)
80004d8: 2200 movs r2, #0
80004da: 60da str r2, [r3, #12]
hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
80004dc: 4b20 ldr r3, [pc, #128] ; (8000560 <MX_ADC_Init+0xb0>)
80004de: 2201 movs r2, #1
80004e0: 611a str r2, [r3, #16]
hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
80004e2: 4b1f ldr r3, [pc, #124] ; (8000560 <MX_ADC_Init+0xb0>)
80004e4: 2204 movs r2, #4
80004e6: 615a str r2, [r3, #20]
hadc.Init.LowPowerAutoWait = DISABLE;
80004e8: 4b1d ldr r3, [pc, #116] ; (8000560 <MX_ADC_Init+0xb0>)
80004ea: 2200 movs r2, #0
80004ec: 761a strb r2, [r3, #24]
hadc.Init.LowPowerAutoPowerOff = DISABLE;
80004ee: 4b1c ldr r3, [pc, #112] ; (8000560 <MX_ADC_Init+0xb0>)
80004f0: 2200 movs r2, #0
80004f2: 765a strb r2, [r3, #25]
hadc.Init.ContinuousConvMode = DISABLE;
80004f4: 4b1a ldr r3, [pc, #104] ; (8000560 <MX_ADC_Init+0xb0>)
80004f6: 2200 movs r2, #0
80004f8: 769a strb r2, [r3, #26]
hadc.Init.DiscontinuousConvMode = DISABLE;
80004fa: 4b19 ldr r3, [pc, #100] ; (8000560 <MX_ADC_Init+0xb0>)
80004fc: 2200 movs r2, #0
80004fe: 76da strb r2, [r3, #27]
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000500: 4b17 ldr r3, [pc, #92] ; (8000560 <MX_ADC_Init+0xb0>)
8000502: 22c2 movs r2, #194 ; 0xc2
8000504: 32ff adds r2, #255 ; 0xff
8000506: 61da str r2, [r3, #28]
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000508: 4b15 ldr r3, [pc, #84] ; (8000560 <MX_ADC_Init+0xb0>)
800050a: 2200 movs r2, #0
800050c: 621a str r2, [r3, #32]
hadc.Init.DMAContinuousRequests = DISABLE;
800050e: 4b14 ldr r3, [pc, #80] ; (8000560 <MX_ADC_Init+0xb0>)
8000510: 2224 movs r2, #36 ; 0x24
8000512: 2100 movs r1, #0
8000514: 5499 strb r1, [r3, r2]
hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000516: 4b12 ldr r3, [pc, #72] ; (8000560 <MX_ADC_Init+0xb0>)
8000518: 2201 movs r2, #1
800051a: 629a str r2, [r3, #40] ; 0x28
if (HAL_ADC_Init(&hadc) != HAL_OK)
800051c: 4b10 ldr r3, [pc, #64] ; (8000560 <MX_ADC_Init+0xb0>)
800051e: 0018 movs r0, r3
8000520: f000 f9b0 bl 8000884 <HAL_ADC_Init>
8000524: 1e03 subs r3, r0, #0
8000526: d001 beq.n 800052c <MX_ADC_Init+0x7c>
{
Error_Handler();
8000528: f000 f892 bl 8000650 <Error_Handler>
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_0;
800052c: 1d3b adds r3, r7, #4
800052e: 2200 movs r2, #0
8000530: 601a str r2, [r3, #0]
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
8000532: 1d3b adds r3, r7, #4
8000534: 2280 movs r2, #128 ; 0x80
8000536: 0152 lsls r2, r2, #5
8000538: 605a str r2, [r3, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
800053a: 1d3b adds r3, r7, #4
800053c: 2280 movs r2, #128 ; 0x80
800053e: 0552 lsls r2, r2, #21
8000540: 609a str r2, [r3, #8]
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
8000542: 1d3a adds r2, r7, #4
8000544: 4b06 ldr r3, [pc, #24] ; (8000560 <MX_ADC_Init+0xb0>)
8000546: 0011 movs r1, r2
8000548: 0018 movs r0, r3
800054a: f000 fb7b bl 8000c44 <HAL_ADC_ConfigChannel>
800054e: 1e03 subs r3, r0, #0
8000550: d001 beq.n 8000556 <MX_ADC_Init+0xa6>
{
Error_Handler();
8000552: f000 f87d bl 8000650 <Error_Handler>
}
/* USER CODE BEGIN ADC_Init 2 */
/* USER CODE END ADC_Init 2 */
}
8000556: 46c0 nop ; (mov r8, r8)
8000558: 46bd mov sp, r7
800055a: b004 add sp, #16
800055c: bd80 pop {r7, pc}
800055e: 46c0 nop ; (mov r8, r8)
8000560: 20000030 .word 0x20000030
8000564: 40012400 .word 0x40012400
08000568 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000568: b590 push {r4, r7, lr}
800056a: b089 sub sp, #36 ; 0x24
800056c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800056e: 240c movs r4, #12
8000570: 193b adds r3, r7, r4
8000572: 0018 movs r0, r3
8000574: 2314 movs r3, #20
8000576: 001a movs r2, r3
8000578: 2100 movs r1, #0
800057a: f002 fb4b bl 8002c14 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
800057e: 4b32 ldr r3, [pc, #200] ; (8000648 <MX_GPIO_Init+0xe0>)
8000580: 695a ldr r2, [r3, #20]
8000582: 4b31 ldr r3, [pc, #196] ; (8000648 <MX_GPIO_Init+0xe0>)
8000584: 2180 movs r1, #128 ; 0x80
8000586: 03c9 lsls r1, r1, #15
8000588: 430a orrs r2, r1
800058a: 615a str r2, [r3, #20]
800058c: 4b2e ldr r3, [pc, #184] ; (8000648 <MX_GPIO_Init+0xe0>)
800058e: 695a ldr r2, [r3, #20]
8000590: 2380 movs r3, #128 ; 0x80
8000592: 03db lsls r3, r3, #15
8000594: 4013 ands r3, r2
8000596: 60bb str r3, [r7, #8]
8000598: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800059a: 4b2b ldr r3, [pc, #172] ; (8000648 <MX_GPIO_Init+0xe0>)
800059c: 695a ldr r2, [r3, #20]
800059e: 4b2a ldr r3, [pc, #168] ; (8000648 <MX_GPIO_Init+0xe0>)
80005a0: 2180 movs r1, #128 ; 0x80
80005a2: 0289 lsls r1, r1, #10
80005a4: 430a orrs r2, r1
80005a6: 615a str r2, [r3, #20]
80005a8: 4b27 ldr r3, [pc, #156] ; (8000648 <MX_GPIO_Init+0xe0>)
80005aa: 695a ldr r2, [r3, #20]
80005ac: 2380 movs r3, #128 ; 0x80
80005ae: 029b lsls r3, r3, #10
80005b0: 4013 ands r3, r2
80005b2: 607b str r3, [r7, #4]
80005b4: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET);
80005b6: 4b25 ldr r3, [pc, #148] ; (800064c <MX_GPIO_Init+0xe4>)
80005b8: 2200 movs r2, #0
80005ba: 2103 movs r1, #3
80005bc: 0018 movs r0, r3
80005be: f000 ffba bl 8001536 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET);
80005c2: 2390 movs r3, #144 ; 0x90
80005c4: 05db lsls r3, r3, #23
80005c6: 2200 movs r2, #0
80005c8: 2138 movs r1, #56 ; 0x38
80005ca: 0018 movs r0, r3
80005cc: f000 ffb3 bl 8001536 <HAL_GPIO_WritePin>
/*Configure GPIO pins : MOTA_Pin MOTB_Pin */
GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin;
80005d0: 193b adds r3, r7, r4
80005d2: 2203 movs r2, #3
80005d4: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80005d6: 193b adds r3, r7, r4
80005d8: 2201 movs r2, #1
80005da: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005dc: 193b adds r3, r7, r4
80005de: 2200 movs r2, #0
80005e0: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80005e2: 193b adds r3, r7, r4
80005e4: 2203 movs r2, #3
80005e6: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80005e8: 193b adds r3, r7, r4
80005ea: 4a18 ldr r2, [pc, #96] ; (800064c <MX_GPIO_Init+0xe4>)
80005ec: 0019 movs r1, r3
80005ee: 0010 movs r0, r2
80005f0: f000 fe14 bl 800121c <HAL_GPIO_Init>
/*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */
GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin;
80005f4: 193b adds r3, r7, r4
80005f6: 2238 movs r2, #56 ; 0x38
80005f8: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80005fa: 193b adds r3, r7, r4
80005fc: 2201 movs r2, #1
80005fe: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8000600: 193b adds r3, r7, r4
8000602: 2202 movs r2, #2
8000604: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000606: 193b adds r3, r7, r4
8000608: 2203 movs r2, #3
800060a: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800060c: 193a adds r2, r7, r4
800060e: 2390 movs r3, #144 ; 0x90
8000610: 05db lsls r3, r3, #23
8000612: 0011 movs r1, r2
8000614: 0018 movs r0, r3
8000616: f000 fe01 bl 800121c <HAL_GPIO_Init>
/*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */
GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin;
800061a: 0021 movs r1, r4
800061c: 187b adds r3, r7, r1
800061e: 22d8 movs r2, #216 ; 0xd8
8000620: 00d2 lsls r2, r2, #3
8000622: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000624: 187b adds r3, r7, r1
8000626: 2200 movs r2, #0
8000628: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
800062a: 187b adds r3, r7, r1
800062c: 2202 movs r2, #2
800062e: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000630: 187a adds r2, r7, r1
8000632: 2390 movs r3, #144 ; 0x90
8000634: 05db lsls r3, r3, #23
8000636: 0011 movs r1, r2
8000638: 0018 movs r0, r3
800063a: f000 fdef bl 800121c <HAL_GPIO_Init>
}
800063e: 46c0 nop ; (mov r8, r8)
8000640: 46bd mov sp, r7
8000642: b009 add sp, #36 ; 0x24
8000644: bd90 pop {r4, r7, pc}
8000646: 46c0 nop ; (mov r8, r8)
8000648: 40021000 .word 0x40021000
800064c: 48001400 .word 0x48001400
08000650 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000650: b580 push {r7, lr}
8000652: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000654: b672 cpsid i
}
8000656: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000658: e7fe b.n 8000658 <Error_Handler+0x8>
...
0800065c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800065c: b580 push {r7, lr}
800065e: b082 sub sp, #8
8000660: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000662: 4b0f ldr r3, [pc, #60] ; (80006a0 <HAL_MspInit+0x44>)
8000664: 699a ldr r2, [r3, #24]
8000666: 4b0e ldr r3, [pc, #56] ; (80006a0 <HAL_MspInit+0x44>)
8000668: 2101 movs r1, #1
800066a: 430a orrs r2, r1
800066c: 619a str r2, [r3, #24]
800066e: 4b0c ldr r3, [pc, #48] ; (80006a0 <HAL_MspInit+0x44>)
8000670: 699b ldr r3, [r3, #24]
8000672: 2201 movs r2, #1
8000674: 4013 ands r3, r2
8000676: 607b str r3, [r7, #4]
8000678: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800067a: 4b09 ldr r3, [pc, #36] ; (80006a0 <HAL_MspInit+0x44>)
800067c: 69da ldr r2, [r3, #28]
800067e: 4b08 ldr r3, [pc, #32] ; (80006a0 <HAL_MspInit+0x44>)
8000680: 2180 movs r1, #128 ; 0x80
8000682: 0549 lsls r1, r1, #21
8000684: 430a orrs r2, r1
8000686: 61da str r2, [r3, #28]
8000688: 4b05 ldr r3, [pc, #20] ; (80006a0 <HAL_MspInit+0x44>)
800068a: 69da ldr r2, [r3, #28]
800068c: 2380 movs r3, #128 ; 0x80
800068e: 055b lsls r3, r3, #21
8000690: 4013 ands r3, r2
8000692: 603b str r3, [r7, #0]
8000694: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000696: 46c0 nop ; (mov r8, r8)
8000698: 46bd mov sp, r7
800069a: b002 add sp, #8
800069c: bd80 pop {r7, pc}
800069e: 46c0 nop ; (mov r8, r8)
80006a0: 40021000 .word 0x40021000
080006a4 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
80006a4: b590 push {r4, r7, lr}
80006a6: b08b sub sp, #44 ; 0x2c
80006a8: af00 add r7, sp, #0
80006aa: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006ac: 2414 movs r4, #20
80006ae: 193b adds r3, r7, r4
80006b0: 0018 movs r0, r3
80006b2: 2314 movs r3, #20
80006b4: 001a movs r2, r3
80006b6: 2100 movs r1, #0
80006b8: f002 faac bl 8002c14 <memset>
if(hadc->Instance==ADC1)
80006bc: 687b ldr r3, [r7, #4]
80006be: 681b ldr r3, [r3, #0]
80006c0: 4a19 ldr r2, [pc, #100] ; (8000728 <HAL_ADC_MspInit+0x84>)
80006c2: 4293 cmp r3, r2
80006c4: d12b bne.n 800071e <HAL_ADC_MspInit+0x7a>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
80006c6: 4b19 ldr r3, [pc, #100] ; (800072c <HAL_ADC_MspInit+0x88>)
80006c8: 699a ldr r2, [r3, #24]
80006ca: 4b18 ldr r3, [pc, #96] ; (800072c <HAL_ADC_MspInit+0x88>)
80006cc: 2180 movs r1, #128 ; 0x80
80006ce: 0089 lsls r1, r1, #2
80006d0: 430a orrs r2, r1
80006d2: 619a str r2, [r3, #24]
80006d4: 4b15 ldr r3, [pc, #84] ; (800072c <HAL_ADC_MspInit+0x88>)
80006d6: 699a ldr r2, [r3, #24]
80006d8: 2380 movs r3, #128 ; 0x80
80006da: 009b lsls r3, r3, #2
80006dc: 4013 ands r3, r2
80006de: 613b str r3, [r7, #16]
80006e0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80006e2: 4b12 ldr r3, [pc, #72] ; (800072c <HAL_ADC_MspInit+0x88>)
80006e4: 695a ldr r2, [r3, #20]
80006e6: 4b11 ldr r3, [pc, #68] ; (800072c <HAL_ADC_MspInit+0x88>)
80006e8: 2180 movs r1, #128 ; 0x80
80006ea: 0289 lsls r1, r1, #10
80006ec: 430a orrs r2, r1
80006ee: 615a str r2, [r3, #20]
80006f0: 4b0e ldr r3, [pc, #56] ; (800072c <HAL_ADC_MspInit+0x88>)
80006f2: 695a ldr r2, [r3, #20]
80006f4: 2380 movs r3, #128 ; 0x80
80006f6: 029b lsls r3, r3, #10
80006f8: 4013 ands r3, r2
80006fa: 60fb str r3, [r7, #12]
80006fc: 68fb ldr r3, [r7, #12]
/**ADC GPIO Configuration
PA0 ------> ADC_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
80006fe: 193b adds r3, r7, r4
8000700: 2201 movs r2, #1
8000702: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000704: 193b adds r3, r7, r4
8000706: 2203 movs r2, #3
8000708: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800070a: 193b adds r3, r7, r4
800070c: 2200 movs r2, #0
800070e: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000710: 193a adds r2, r7, r4
8000712: 2390 movs r3, #144 ; 0x90
8000714: 05db lsls r3, r3, #23
8000716: 0011 movs r1, r2
8000718: 0018 movs r0, r3
800071a: f000 fd7f bl 800121c <HAL_GPIO_Init>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
800071e: 46c0 nop ; (mov r8, r8)
8000720: 46bd mov sp, r7
8000722: b00b add sp, #44 ; 0x2c
8000724: bd90 pop {r4, r7, pc}
8000726: 46c0 nop ; (mov r8, r8)
8000728: 40012400 .word 0x40012400
800072c: 40021000 .word 0x40021000
08000730 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000730: b580 push {r7, lr}
8000732: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000734: e7fe b.n 8000734 <NMI_Handler+0x4>
08000736 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000736: b580 push {r7, lr}
8000738: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800073a: e7fe b.n 800073a <HardFault_Handler+0x4>
0800073c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800073c: b580 push {r7, lr}
800073e: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000740: 46c0 nop ; (mov r8, r8)
8000742: 46bd mov sp, r7
8000744: bd80 pop {r7, pc}
08000746 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000746: b580 push {r7, lr}
8000748: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800074a: 46c0 nop ; (mov r8, r8)
800074c: 46bd mov sp, r7
800074e: bd80 pop {r7, pc}
08000750 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000750: b580 push {r7, lr}
8000752: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000754: f000 f87a bl 800084c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000758: 46c0 nop ; (mov r8, r8)
800075a: 46bd mov sp, r7
800075c: bd80 pop {r7, pc}
0800075e <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
800075e: b580 push {r7, lr}
8000760: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
8000762: 46c0 nop ; (mov r8, r8)
8000764: 46bd mov sp, r7
8000766: bd80 pop {r7, pc}
08000768 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000768: 480d ldr r0, [pc, #52] ; (80007a0 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
800076a: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800076c: 480d ldr r0, [pc, #52] ; (80007a4 <LoopForever+0x6>)
ldr r1, =_edata
800076e: 490e ldr r1, [pc, #56] ; (80007a8 <LoopForever+0xa>)
ldr r2, =_sidata
8000770: 4a0e ldr r2, [pc, #56] ; (80007ac <LoopForever+0xe>)
movs r3, #0
8000772: 2300 movs r3, #0
b LoopCopyDataInit
8000774: e002 b.n 800077c <LoopCopyDataInit>
08000776 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000776: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000778: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800077a: 3304 adds r3, #4
0800077c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800077c: 18c4 adds r4, r0, r3
cmp r4, r1
800077e: 428c cmp r4, r1
bcc CopyDataInit
8000780: d3f9 bcc.n 8000776 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000782: 4a0b ldr r2, [pc, #44] ; (80007b0 <LoopForever+0x12>)
ldr r4, =_ebss
8000784: 4c0b ldr r4, [pc, #44] ; (80007b4 <LoopForever+0x16>)
movs r3, #0
8000786: 2300 movs r3, #0
b LoopFillZerobss
8000788: e001 b.n 800078e <LoopFillZerobss>
0800078a <FillZerobss>:
FillZerobss:
str r3, [r2]
800078a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800078c: 3204 adds r2, #4
0800078e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800078e: 42a2 cmp r2, r4
bcc FillZerobss
8000790: d3fb bcc.n 800078a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000792: f7ff ffe4 bl 800075e <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000796: f002 fa19 bl 8002bcc <__libc_init_array>
/* Call the application's entry point.*/
bl main
800079a: f7ff fe2b bl 80003f4 <main>
0800079e <LoopForever>:
LoopForever:
b LoopForever
800079e: e7fe b.n 800079e <LoopForever>
ldr r0, =_estack
80007a0: 20001000 .word 0x20001000
ldr r0, =_sdata
80007a4: 20000000 .word 0x20000000
ldr r1, =_edata
80007a8: 20000010 .word 0x20000010
ldr r2, =_sidata
80007ac: 08002ca0 .word 0x08002ca0
ldr r2, =_sbss
80007b0: 20000010 .word 0x20000010
ldr r4, =_ebss
80007b4: 200000cc .word 0x200000cc
080007b8 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80007b8: e7fe b.n 80007b8 <ADC1_IRQHandler>
...
080007bc <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80007bc: b580 push {r7, lr}
80007be: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80007c0: 4b07 ldr r3, [pc, #28] ; (80007e0 <HAL_Init+0x24>)
80007c2: 681a ldr r2, [r3, #0]
80007c4: 4b06 ldr r3, [pc, #24] ; (80007e0 <HAL_Init+0x24>)
80007c6: 2110 movs r1, #16
80007c8: 430a orrs r2, r1
80007ca: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80007cc: 2003 movs r0, #3
80007ce: f000 f809 bl 80007e4 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80007d2: f7ff ff43 bl 800065c <HAL_MspInit>
/* Return function status */
return HAL_OK;
80007d6: 2300 movs r3, #0
}
80007d8: 0018 movs r0, r3
80007da: 46bd mov sp, r7
80007dc: bd80 pop {r7, pc}
80007de: 46c0 nop ; (mov r8, r8)
80007e0: 40022000 .word 0x40022000
080007e4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80007e4: b590 push {r4, r7, lr}
80007e6: b083 sub sp, #12
80007e8: af00 add r7, sp, #0
80007ea: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80007ec: 4b14 ldr r3, [pc, #80] ; (8000840 <HAL_InitTick+0x5c>)
80007ee: 681c ldr r4, [r3, #0]
80007f0: 4b14 ldr r3, [pc, #80] ; (8000844 <HAL_InitTick+0x60>)
80007f2: 781b ldrb r3, [r3, #0]
80007f4: 0019 movs r1, r3
80007f6: 23fa movs r3, #250 ; 0xfa
80007f8: 0098 lsls r0, r3, #2
80007fa: f7ff fc85 bl 8000108 <__udivsi3>
80007fe: 0003 movs r3, r0
8000800: 0019 movs r1, r3
8000802: 0020 movs r0, r4
8000804: f7ff fc80 bl 8000108 <__udivsi3>
8000808: 0003 movs r3, r0
800080a: 0018 movs r0, r3
800080c: f000 fcf9 bl 8001202 <HAL_SYSTICK_Config>
8000810: 1e03 subs r3, r0, #0
8000812: d001 beq.n 8000818 <HAL_InitTick+0x34>
{
return HAL_ERROR;
8000814: 2301 movs r3, #1
8000816: e00f b.n 8000838 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000818: 687b ldr r3, [r7, #4]
800081a: 2b03 cmp r3, #3
800081c: d80b bhi.n 8000836 <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800081e: 6879 ldr r1, [r7, #4]
8000820: 2301 movs r3, #1
8000822: 425b negs r3, r3
8000824: 2200 movs r2, #0
8000826: 0018 movs r0, r3
8000828: f000 fcd6 bl 80011d8 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800082c: 4b06 ldr r3, [pc, #24] ; (8000848 <HAL_InitTick+0x64>)
800082e: 687a ldr r2, [r7, #4]
8000830: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000832: 2300 movs r3, #0
8000834: e000 b.n 8000838 <HAL_InitTick+0x54>
return HAL_ERROR;
8000836: 2301 movs r3, #1
}
8000838: 0018 movs r0, r3
800083a: 46bd mov sp, r7
800083c: b003 add sp, #12
800083e: bd90 pop {r4, r7, pc}
8000840: 20000000 .word 0x20000000
8000844: 20000008 .word 0x20000008
8000848: 20000004 .word 0x20000004
0800084c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800084c: b580 push {r7, lr}
800084e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000850: 4b05 ldr r3, [pc, #20] ; (8000868 <HAL_IncTick+0x1c>)
8000852: 781b ldrb r3, [r3, #0]
8000854: 001a movs r2, r3
8000856: 4b05 ldr r3, [pc, #20] ; (800086c <HAL_IncTick+0x20>)
8000858: 681b ldr r3, [r3, #0]
800085a: 18d2 adds r2, r2, r3
800085c: 4b03 ldr r3, [pc, #12] ; (800086c <HAL_IncTick+0x20>)
800085e: 601a str r2, [r3, #0]
}
8000860: 46c0 nop ; (mov r8, r8)
8000862: 46bd mov sp, r7
8000864: bd80 pop {r7, pc}
8000866: 46c0 nop ; (mov r8, r8)
8000868: 20000008 .word 0x20000008
800086c: 20000070 .word 0x20000070
08000870 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000870: b580 push {r7, lr}
8000872: af00 add r7, sp, #0
return uwTick;
8000874: 4b02 ldr r3, [pc, #8] ; (8000880 <HAL_GetTick+0x10>)
8000876: 681b ldr r3, [r3, #0]
}
8000878: 0018 movs r0, r3
800087a: 46bd mov sp, r7
800087c: bd80 pop {r7, pc}
800087e: 46c0 nop ; (mov r8, r8)
8000880: 20000070 .word 0x20000070
08000884 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8000884: b580 push {r7, lr}
8000886: b084 sub sp, #16
8000888: af00 add r7, sp, #0
800088a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800088c: 230f movs r3, #15
800088e: 18fb adds r3, r7, r3
8000890: 2200 movs r2, #0
8000892: 701a strb r2, [r3, #0]
uint32_t tmpCFGR1 = 0U;
8000894: 2300 movs r3, #0
8000896: 60bb str r3, [r7, #8]
/* Check ADC handle */
if(hadc == NULL)
8000898: 687b ldr r3, [r7, #4]
800089a: 2b00 cmp r3, #0
800089c: d101 bne.n 80008a2 <HAL_ADC_Init+0x1e>
{
return HAL_ERROR;
800089e: 2301 movs r3, #1
80008a0: e125 b.n 8000aee <HAL_ADC_Init+0x26a>
/* Refer to header of this file for more details on clock enabling procedure*/
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
/* - ADC voltage regulator enable */
if (hadc->State == HAL_ADC_STATE_RESET)
80008a2: 687b ldr r3, [r7, #4]
80008a4: 6b9b ldr r3, [r3, #56] ; 0x38
80008a6: 2b00 cmp r3, #0
80008a8: d10a bne.n 80008c0 <HAL_ADC_Init+0x3c>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
80008aa: 687b ldr r3, [r7, #4]
80008ac: 2200 movs r2, #0
80008ae: 63da str r2, [r3, #60] ; 0x3c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
80008b0: 687b ldr r3, [r7, #4]
80008b2: 2234 movs r2, #52 ; 0x34
80008b4: 2100 movs r1, #0
80008b6: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80008b8: 687b ldr r3, [r7, #4]
80008ba: 0018 movs r0, r3
80008bc: f7ff fef2 bl 80006a4 <HAL_ADC_MspInit>
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
/* and if there is no conversion on going on regular group (ADC can be */
/* enabled anyway, in case of call of this function to update a parameter */
/* on the fly). */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
80008c0: 687b ldr r3, [r7, #4]
80008c2: 6b9b ldr r3, [r3, #56] ; 0x38
80008c4: 2210 movs r2, #16
80008c6: 4013 ands r3, r2
80008c8: d000 beq.n 80008cc <HAL_ADC_Init+0x48>
80008ca: e103 b.n 8000ad4 <HAL_ADC_Init+0x250>
80008cc: 230f movs r3, #15
80008ce: 18fb adds r3, r7, r3
80008d0: 781b ldrb r3, [r3, #0]
80008d2: 2b00 cmp r3, #0
80008d4: d000 beq.n 80008d8 <HAL_ADC_Init+0x54>
80008d6: e0fd b.n 8000ad4 <HAL_ADC_Init+0x250>
(tmp_hal_status == HAL_OK) &&
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
80008d8: 687b ldr r3, [r7, #4]
80008da: 681b ldr r3, [r3, #0]
80008dc: 689b ldr r3, [r3, #8]
80008de: 2204 movs r2, #4
80008e0: 4013 ands r3, r2
(tmp_hal_status == HAL_OK) &&
80008e2: d000 beq.n 80008e6 <HAL_ADC_Init+0x62>
80008e4: e0f6 b.n 8000ad4 <HAL_ADC_Init+0x250>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80008e6: 687b ldr r3, [r7, #4]
80008e8: 6b9b ldr r3, [r3, #56] ; 0x38
80008ea: 4a83 ldr r2, [pc, #524] ; (8000af8 <HAL_ADC_Init+0x274>)
80008ec: 4013 ands r3, r2
80008ee: 2202 movs r2, #2
80008f0: 431a orrs r2, r3
80008f2: 687b ldr r3, [r7, #4]
80008f4: 639a str r2, [r3, #56] ; 0x38
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - ADC clock mode */
/* - ADC clock prescaler */
/* - ADC resolution */
if (ADC_IS_ENABLE(hadc) == RESET)
80008f6: 687b ldr r3, [r7, #4]
80008f8: 681b ldr r3, [r3, #0]
80008fa: 689b ldr r3, [r3, #8]
80008fc: 2203 movs r2, #3
80008fe: 4013 ands r3, r2
8000900: 2b01 cmp r3, #1
8000902: d112 bne.n 800092a <HAL_ADC_Init+0xa6>
8000904: 687b ldr r3, [r7, #4]
8000906: 681b ldr r3, [r3, #0]
8000908: 681b ldr r3, [r3, #0]
800090a: 2201 movs r2, #1
800090c: 4013 ands r3, r2
800090e: 2b01 cmp r3, #1
8000910: d009 beq.n 8000926 <HAL_ADC_Init+0xa2>
8000912: 687b ldr r3, [r7, #4]
8000914: 681b ldr r3, [r3, #0]
8000916: 68da ldr r2, [r3, #12]
8000918: 2380 movs r3, #128 ; 0x80
800091a: 021b lsls r3, r3, #8
800091c: 401a ands r2, r3
800091e: 2380 movs r3, #128 ; 0x80
8000920: 021b lsls r3, r3, #8
8000922: 429a cmp r2, r3
8000924: d101 bne.n 800092a <HAL_ADC_Init+0xa6>
8000926: 2301 movs r3, #1
8000928: e000 b.n 800092c <HAL_ADC_Init+0xa8>
800092a: 2300 movs r3, #0
800092c: 2b00 cmp r3, #0
800092e: d116 bne.n 800095e <HAL_ADC_Init+0xda>
/* parameters): */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() ) */
/* Configuration of ADC resolution */
MODIFY_REG(hadc->Instance->CFGR1,
8000930: 687b ldr r3, [r7, #4]
8000932: 681b ldr r3, [r3, #0]
8000934: 68db ldr r3, [r3, #12]
8000936: 2218 movs r2, #24
8000938: 4393 bics r3, r2
800093a: 0019 movs r1, r3
800093c: 687b ldr r3, [r7, #4]
800093e: 689a ldr r2, [r3, #8]
8000940: 687b ldr r3, [r7, #4]
8000942: 681b ldr r3, [r3, #0]
8000944: 430a orrs r2, r1
8000946: 60da str r2, [r3, #12]
ADC_CFGR1_RES ,
hadc->Init.Resolution );
/* Configuration of ADC clock mode: clock source AHB or HSI with */
/* selectable prescaler */
MODIFY_REG(hadc->Instance->CFGR2 ,
8000948: 687b ldr r3, [r7, #4]
800094a: 681b ldr r3, [r3, #0]
800094c: 691b ldr r3, [r3, #16]
800094e: 009b lsls r3, r3, #2
8000950: 0899 lsrs r1, r3, #2
8000952: 687b ldr r3, [r7, #4]
8000954: 685a ldr r2, [r3, #4]
8000956: 687b ldr r3, [r7, #4]
8000958: 681b ldr r3, [r3, #0]
800095a: 430a orrs r2, r1
800095c: 611a str r2, [r3, #16]
/* - external trigger polarity */
/* - data alignment */
/* - resolution */
/* - scan direction */
/* - DMA continuous request */
hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN |
800095e: 687b ldr r3, [r7, #4]
8000960: 681b ldr r3, [r3, #0]
8000962: 68da ldr r2, [r3, #12]
8000964: 687b ldr r3, [r7, #4]
8000966: 681b ldr r3, [r3, #0]
8000968: 4964 ldr r1, [pc, #400] ; (8000afc <HAL_ADC_Init+0x278>)
800096a: 400a ands r2, r1
800096c: 60da str r2, [r3, #12]
ADC_CFGR1_EXTEN |
ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG );
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800096e: 687b ldr r3, [r7, #4]
8000970: 7e1b ldrb r3, [r3, #24]
8000972: 039a lsls r2, r3, #14
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8000974: 687b ldr r3, [r7, #4]
8000976: 7e5b ldrb r3, [r3, #25]
8000978: 03db lsls r3, r3, #15
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800097a: 431a orrs r2, r3
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
800097c: 687b ldr r3, [r7, #4]
800097e: 7e9b ldrb r3, [r3, #26]
8000980: 035b lsls r3, r3, #13
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8000982: 431a orrs r2, r3
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8000984: 687b ldr r3, [r7, #4]
8000986: 6a9b ldr r3, [r3, #40] ; 0x28
8000988: 2b01 cmp r3, #1
800098a: d002 beq.n 8000992 <HAL_ADC_Init+0x10e>
800098c: 2380 movs r3, #128 ; 0x80
800098e: 015b lsls r3, r3, #5
8000990: e000 b.n 8000994 <HAL_ADC_Init+0x110>
8000992: 2300 movs r3, #0
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000994: 431a orrs r2, r3
hadc->Init.DataAlign |
8000996: 687b ldr r3, [r7, #4]
8000998: 68db ldr r3, [r3, #12]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
800099a: 431a orrs r2, r3
ADC_SCANDIR(hadc->Init.ScanConvMode) |
800099c: 687b ldr r3, [r7, #4]
800099e: 691b ldr r3, [r3, #16]
80009a0: 2b02 cmp r3, #2
80009a2: d101 bne.n 80009a8 <HAL_ADC_Init+0x124>
80009a4: 2304 movs r3, #4
80009a6: e000 b.n 80009aa <HAL_ADC_Init+0x126>
80009a8: 2300 movs r3, #0
hadc->Init.DataAlign |
80009aa: 431a orrs r2, r3
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
80009ac: 687b ldr r3, [r7, #4]
80009ae: 2124 movs r1, #36 ; 0x24
80009b0: 5c5b ldrb r3, [r3, r1]
80009b2: 005b lsls r3, r3, #1
ADC_SCANDIR(hadc->Init.ScanConvMode) |
80009b4: 4313 orrs r3, r2
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
80009b6: 68ba ldr r2, [r7, #8]
80009b8: 4313 orrs r3, r2
80009ba: 60bb str r3, [r7, #8]
/* Enable discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80009bc: 687b ldr r3, [r7, #4]
80009be: 7edb ldrb r3, [r3, #27]
80009c0: 2b01 cmp r3, #1
80009c2: d115 bne.n 80009f0 <HAL_ADC_Init+0x16c>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
80009c4: 687b ldr r3, [r7, #4]
80009c6: 7e9b ldrb r3, [r3, #26]
80009c8: 2b00 cmp r3, #0
80009ca: d105 bne.n 80009d8 <HAL_ADC_Init+0x154>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
80009cc: 68bb ldr r3, [r7, #8]
80009ce: 2280 movs r2, #128 ; 0x80
80009d0: 0252 lsls r2, r2, #9
80009d2: 4313 orrs r3, r2
80009d4: 60bb str r3, [r7, #8]
80009d6: e00b b.n 80009f0 <HAL_ADC_Init+0x16c>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80009d8: 687b ldr r3, [r7, #4]
80009da: 6b9b ldr r3, [r3, #56] ; 0x38
80009dc: 2220 movs r2, #32
80009de: 431a orrs r2, r3
80009e0: 687b ldr r3, [r7, #4]
80009e2: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80009e4: 687b ldr r3, [r7, #4]
80009e6: 6bdb ldr r3, [r3, #60] ; 0x3c
80009e8: 2201 movs r2, #1
80009ea: 431a orrs r2, r3
80009ec: 687b ldr r3, [r7, #4]
80009ee: 63da str r2, [r3, #60] ; 0x3c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
80009f0: 687b ldr r3, [r7, #4]
80009f2: 69da ldr r2, [r3, #28]
80009f4: 23c2 movs r3, #194 ; 0xc2
80009f6: 33ff adds r3, #255 ; 0xff
80009f8: 429a cmp r2, r3
80009fa: d007 beq.n 8000a0c <HAL_ADC_Init+0x188>
{
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
80009fc: 687b ldr r3, [r7, #4]
80009fe: 69da ldr r2, [r3, #28]
hadc->Init.ExternalTrigConvEdge );
8000a00: 687b ldr r3, [r7, #4]
8000a02: 6a1b ldr r3, [r3, #32]
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000a04: 4313 orrs r3, r2
8000a06: 68ba ldr r2, [r7, #8]
8000a08: 4313 orrs r3, r2
8000a0a: 60bb str r3, [r7, #8]
}
/* Update ADC configuration register with previous settings */
hadc->Instance->CFGR1 |= tmpCFGR1;
8000a0c: 687b ldr r3, [r7, #4]
8000a0e: 681b ldr r3, [r3, #0]
8000a10: 68d9 ldr r1, [r3, #12]
8000a12: 687b ldr r3, [r7, #4]
8000a14: 681b ldr r3, [r3, #0]
8000a16: 68ba ldr r2, [r7, #8]
8000a18: 430a orrs r2, r1
8000a1a: 60da str r2, [r3, #12]
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function if parameter */
/* "SamplingTimeCommon" has been set to a valid sampling time. */
/* Otherwise, sampling time is set into ADC channel initialization */
/* structure with parameter "SamplingTime" (obsolete). */
if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000a1c: 687b ldr r3, [r7, #4]
8000a1e: 6ada ldr r2, [r3, #44] ; 0x2c
8000a20: 2380 movs r3, #128 ; 0x80
8000a22: 055b lsls r3, r3, #21
8000a24: 429a cmp r2, r3
8000a26: d01b beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a28: 687b ldr r3, [r7, #4]
8000a2a: 6adb ldr r3, [r3, #44] ; 0x2c
8000a2c: 2b01 cmp r3, #1
8000a2e: d017 beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a30: 687b ldr r3, [r7, #4]
8000a32: 6adb ldr r3, [r3, #44] ; 0x2c
8000a34: 2b02 cmp r3, #2
8000a36: d013 beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a38: 687b ldr r3, [r7, #4]
8000a3a: 6adb ldr r3, [r3, #44] ; 0x2c
8000a3c: 2b03 cmp r3, #3
8000a3e: d00f beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a40: 687b ldr r3, [r7, #4]
8000a42: 6adb ldr r3, [r3, #44] ; 0x2c
8000a44: 2b04 cmp r3, #4
8000a46: d00b beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a48: 687b ldr r3, [r7, #4]
8000a4a: 6adb ldr r3, [r3, #44] ; 0x2c
8000a4c: 2b05 cmp r3, #5
8000a4e: d007 beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a50: 687b ldr r3, [r7, #4]
8000a52: 6adb ldr r3, [r3, #44] ; 0x2c
8000a54: 2b06 cmp r3, #6
8000a56: d003 beq.n 8000a60 <HAL_ADC_Init+0x1dc>
8000a58: 687b ldr r3, [r7, #4]
8000a5a: 6adb ldr r3, [r3, #44] ; 0x2c
8000a5c: 2b07 cmp r3, #7
8000a5e: d112 bne.n 8000a86 <HAL_ADC_Init+0x202>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000a60: 687b ldr r3, [r7, #4]
8000a62: 681b ldr r3, [r3, #0]
8000a64: 695a ldr r2, [r3, #20]
8000a66: 687b ldr r3, [r7, #4]
8000a68: 681b ldr r3, [r3, #0]
8000a6a: 2107 movs r1, #7
8000a6c: 438a bics r2, r1
8000a6e: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
8000a70: 687b ldr r3, [r7, #4]
8000a72: 681b ldr r3, [r3, #0]
8000a74: 6959 ldr r1, [r3, #20]
8000a76: 687b ldr r3, [r7, #4]
8000a78: 6adb ldr r3, [r3, #44] ; 0x2c
8000a7a: 2207 movs r2, #7
8000a7c: 401a ands r2, r3
8000a7e: 687b ldr r3, [r7, #4]
8000a80: 681b ldr r3, [r3, #0]
8000a82: 430a orrs r2, r1
8000a84: 615a str r2, [r3, #20]
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
/* set into separate dedicated function, and bits of ADC resolution set */
/* out of temporary variable 'tmpCFGR1'). */
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000a86: 687b ldr r3, [r7, #4]
8000a88: 681b ldr r3, [r3, #0]
8000a8a: 68db ldr r3, [r3, #12]
8000a8c: 4a1c ldr r2, [pc, #112] ; (8000b00 <HAL_ADC_Init+0x27c>)
8000a8e: 4013 ands r3, r2
8000a90: 68ba ldr r2, [r7, #8]
8000a92: 429a cmp r2, r3
8000a94: d10b bne.n 8000aae <HAL_ADC_Init+0x22a>
== tmpCFGR1)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8000a96: 687b ldr r3, [r7, #4]
8000a98: 2200 movs r2, #0
8000a9a: 63da str r2, [r3, #60] ; 0x3c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000a9c: 687b ldr r3, [r7, #4]
8000a9e: 6b9b ldr r3, [r3, #56] ; 0x38
8000aa0: 2203 movs r2, #3
8000aa2: 4393 bics r3, r2
8000aa4: 2201 movs r2, #1
8000aa6: 431a orrs r2, r3
8000aa8: 687b ldr r3, [r7, #4]
8000aaa: 639a str r2, [r3, #56] ; 0x38
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000aac: e01c b.n 8000ae8 <HAL_ADC_Init+0x264>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8000aae: 687b ldr r3, [r7, #4]
8000ab0: 6b9b ldr r3, [r3, #56] ; 0x38
8000ab2: 2212 movs r2, #18
8000ab4: 4393 bics r3, r2
8000ab6: 2210 movs r2, #16
8000ab8: 431a orrs r2, r3
8000aba: 687b ldr r3, [r7, #4]
8000abc: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000abe: 687b ldr r3, [r7, #4]
8000ac0: 6bdb ldr r3, [r3, #60] ; 0x3c
8000ac2: 2201 movs r2, #1
8000ac4: 431a orrs r2, r3
8000ac6: 687b ldr r3, [r7, #4]
8000ac8: 63da str r2, [r3, #60] ; 0x3c
tmp_hal_status = HAL_ERROR;
8000aca: 230f movs r3, #15
8000acc: 18fb adds r3, r7, r3
8000ace: 2201 movs r2, #1
8000ad0: 701a strb r2, [r3, #0]
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000ad2: e009 b.n 8000ae8 <HAL_ADC_Init+0x264>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000ad4: 687b ldr r3, [r7, #4]
8000ad6: 6b9b ldr r3, [r3, #56] ; 0x38
8000ad8: 2210 movs r2, #16
8000ada: 431a orrs r2, r3
8000adc: 687b ldr r3, [r7, #4]
8000ade: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
8000ae0: 230f movs r3, #15
8000ae2: 18fb adds r3, r7, r3
8000ae4: 2201 movs r2, #1
8000ae6: 701a strb r2, [r3, #0]
}
/* Return function status */
return tmp_hal_status;
8000ae8: 230f movs r3, #15
8000aea: 18fb adds r3, r7, r3
8000aec: 781b ldrb r3, [r3, #0]
}
8000aee: 0018 movs r0, r3
8000af0: 46bd mov sp, r7
8000af2: b004 add sp, #16
8000af4: bd80 pop {r7, pc}
8000af6: 46c0 nop ; (mov r8, r8)
8000af8: fffffefd .word 0xfffffefd
8000afc: fffe0219 .word 0xfffe0219
8000b00: 833fffe7 .word 0x833fffe7
08000b04 <HAL_ADC_Start>:
* Interruptions enabled in this function: None.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
8000b04: b590 push {r4, r7, lr}
8000b06: b085 sub sp, #20
8000b08: af00 add r7, sp, #0
8000b0a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000b0c: 230f movs r3, #15
8000b0e: 18fb adds r3, r7, r3
8000b10: 2200 movs r2, #0
8000b12: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8000b14: 687b ldr r3, [r7, #4]
8000b16: 681b ldr r3, [r3, #0]
8000b18: 689b ldr r3, [r3, #8]
8000b1a: 2204 movs r2, #4
8000b1c: 4013 ands r3, r2
8000b1e: d138 bne.n 8000b92 <HAL_ADC_Start+0x8e>
{
/* Process locked */
__HAL_LOCK(hadc);
8000b20: 687b ldr r3, [r7, #4]
8000b22: 2234 movs r2, #52 ; 0x34
8000b24: 5c9b ldrb r3, [r3, r2]
8000b26: 2b01 cmp r3, #1
8000b28: d101 bne.n 8000b2e <HAL_ADC_Start+0x2a>
8000b2a: 2302 movs r3, #2
8000b2c: e038 b.n 8000ba0 <HAL_ADC_Start+0x9c>
8000b2e: 687b ldr r3, [r7, #4]
8000b30: 2234 movs r2, #52 ; 0x34
8000b32: 2101 movs r1, #1
8000b34: 5499 strb r1, [r3, r2]
/* Enable the ADC peripheral */
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
8000b36: 687b ldr r3, [r7, #4]
8000b38: 7e5b ldrb r3, [r3, #25]
8000b3a: 2b01 cmp r3, #1
8000b3c: d007 beq.n 8000b4e <HAL_ADC_Start+0x4a>
{
tmp_hal_status = ADC_Enable(hadc);
8000b3e: 230f movs r3, #15
8000b40: 18fc adds r4, r7, r3
8000b42: 687b ldr r3, [r7, #4]
8000b44: 0018 movs r0, r3
8000b46: f000 f973 bl 8000e30 <ADC_Enable>
8000b4a: 0003 movs r3, r0
8000b4c: 7023 strb r3, [r4, #0]
}
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
8000b4e: 230f movs r3, #15
8000b50: 18fb adds r3, r7, r3
8000b52: 781b ldrb r3, [r3, #0]
8000b54: 2b00 cmp r3, #0
8000b56: d120 bne.n 8000b9a <HAL_ADC_Start+0x96>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
8000b58: 687b ldr r3, [r7, #4]
8000b5a: 6b9b ldr r3, [r3, #56] ; 0x38
8000b5c: 4a12 ldr r2, [pc, #72] ; (8000ba8 <HAL_ADC_Start+0xa4>)
8000b5e: 4013 ands r3, r2
8000b60: 2280 movs r2, #128 ; 0x80
8000b62: 0052 lsls r2, r2, #1
8000b64: 431a orrs r2, r3
8000b66: 687b ldr r3, [r7, #4]
8000b68: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8000b6a: 687b ldr r3, [r7, #4]
8000b6c: 2200 movs r2, #0
8000b6e: 63da str r2, [r3, #60] ; 0x3c
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8000b70: 687b ldr r3, [r7, #4]
8000b72: 2234 movs r2, #52 ; 0x34
8000b74: 2100 movs r1, #0
8000b76: 5499 strb r1, [r3, r2]
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
8000b78: 687b ldr r3, [r7, #4]
8000b7a: 681b ldr r3, [r3, #0]
8000b7c: 221c movs r2, #28
8000b7e: 601a str r2, [r3, #0]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
8000b80: 687b ldr r3, [r7, #4]
8000b82: 681b ldr r3, [r3, #0]
8000b84: 689a ldr r2, [r3, #8]
8000b86: 687b ldr r3, [r7, #4]
8000b88: 681b ldr r3, [r3, #0]
8000b8a: 2104 movs r1, #4
8000b8c: 430a orrs r2, r1
8000b8e: 609a str r2, [r3, #8]
8000b90: e003 b.n 8000b9a <HAL_ADC_Start+0x96>
}
}
else
{
tmp_hal_status = HAL_BUSY;
8000b92: 230f movs r3, #15
8000b94: 18fb adds r3, r7, r3
8000b96: 2202 movs r2, #2
8000b98: 701a strb r2, [r3, #0]
}
/* Return function status */
return tmp_hal_status;
8000b9a: 230f movs r3, #15
8000b9c: 18fb adds r3, r7, r3
8000b9e: 781b ldrb r3, [r3, #0]
}
8000ba0: 0018 movs r0, r3
8000ba2: 46bd mov sp, r7
8000ba4: b005 add sp, #20
8000ba6: bd90 pop {r4, r7, pc}
8000ba8: fffff0fe .word 0xfffff0fe
08000bac <HAL_ADC_Stop>:
* @brief Stop ADC conversion of regular group, disable ADC peripheral.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
8000bac: b5b0 push {r4, r5, r7, lr}
8000bae: b084 sub sp, #16
8000bb0: af00 add r7, sp, #0
8000bb2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000bb4: 230f movs r3, #15
8000bb6: 18fb adds r3, r7, r3
8000bb8: 2200 movs r2, #0
8000bba: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8000bbc: 687b ldr r3, [r7, #4]
8000bbe: 2234 movs r2, #52 ; 0x34
8000bc0: 5c9b ldrb r3, [r3, r2]
8000bc2: 2b01 cmp r3, #1
8000bc4: d101 bne.n 8000bca <HAL_ADC_Stop+0x1e>
8000bc6: 2302 movs r3, #2
8000bc8: e029 b.n 8000c1e <HAL_ADC_Stop+0x72>
8000bca: 687b ldr r3, [r7, #4]
8000bcc: 2234 movs r2, #52 ; 0x34
8000bce: 2101 movs r1, #1
8000bd0: 5499 strb r1, [r3, r2]
/* 1. Stop potential conversion on going, on regular group */
tmp_hal_status = ADC_ConversionStop(hadc);
8000bd2: 250f movs r5, #15
8000bd4: 197c adds r4, r7, r5
8000bd6: 687b ldr r3, [r7, #4]
8000bd8: 0018 movs r0, r3
8000bda: f000 fa1e bl 800101a <ADC_ConversionStop>
8000bde: 0003 movs r3, r0
8000be0: 7023 strb r3, [r4, #0]
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
8000be2: 197b adds r3, r7, r5
8000be4: 781b ldrb r3, [r3, #0]
8000be6: 2b00 cmp r3, #0
8000be8: d112 bne.n 8000c10 <HAL_ADC_Stop+0x64>
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
8000bea: 197c adds r4, r7, r5
8000bec: 687b ldr r3, [r7, #4]
8000bee: 0018 movs r0, r3
8000bf0: f000 f9a2 bl 8000f38 <ADC_Disable>
8000bf4: 0003 movs r3, r0
8000bf6: 7023 strb r3, [r4, #0]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
8000bf8: 197b adds r3, r7, r5
8000bfa: 781b ldrb r3, [r3, #0]
8000bfc: 2b00 cmp r3, #0
8000bfe: d107 bne.n 8000c10 <HAL_ADC_Stop+0x64>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000c00: 687b ldr r3, [r7, #4]
8000c02: 6b9b ldr r3, [r3, #56] ; 0x38
8000c04: 4a08 ldr r2, [pc, #32] ; (8000c28 <HAL_ADC_Stop+0x7c>)
8000c06: 4013 ands r3, r2
8000c08: 2201 movs r2, #1
8000c0a: 431a orrs r2, r3
8000c0c: 687b ldr r3, [r7, #4]
8000c0e: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_READY);
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000c10: 687b ldr r3, [r7, #4]
8000c12: 2234 movs r2, #52 ; 0x34
8000c14: 2100 movs r1, #0
8000c16: 5499 strb r1, [r3, r2]
/* Return function status */
return tmp_hal_status;
8000c18: 230f movs r3, #15
8000c1a: 18fb adds r3, r7, r3
8000c1c: 781b ldrb r3, [r3, #0]
}
8000c1e: 0018 movs r0, r3
8000c20: 46bd mov sp, r7
8000c22: b004 add sp, #16
8000c24: bdb0 pop {r4, r5, r7, pc}
8000c26: 46c0 nop ; (mov r8, r8)
8000c28: fffffefe .word 0xfffffefe
08000c2c <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
8000c2c: b580 push {r7, lr}
8000c2e: b082 sub sp, #8
8000c30: af00 add r7, sp, #0
8000c32: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8000c34: 687b ldr r3, [r7, #4]
8000c36: 681b ldr r3, [r3, #0]
8000c38: 6c1b ldr r3, [r3, #64] ; 0x40
}
8000c3a: 0018 movs r0, r3
8000c3c: 46bd mov sp, r7
8000c3e: b002 add sp, #8
8000c40: bd80 pop {r7, pc}
...
08000c44 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8000c44: b580 push {r7, lr}
8000c46: b084 sub sp, #16
8000c48: af00 add r7, sp, #0
8000c4a: 6078 str r0, [r7, #4]
8000c4c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000c4e: 230f movs r3, #15
8000c50: 18fb adds r3, r7, r3
8000c52: 2200 movs r2, #0
8000c54: 701a strb r2, [r3, #0]
__IO uint32_t wait_loop_index = 0U;
8000c56: 2300 movs r3, #0
8000c58: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_RANK(sConfig->Rank));
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000c5a: 687b ldr r3, [r7, #4]
8000c5c: 6ada ldr r2, [r3, #44] ; 0x2c
8000c5e: 2380 movs r3, #128 ; 0x80
8000c60: 055b lsls r3, r3, #21
8000c62: 429a cmp r2, r3
8000c64: d011 beq.n 8000c8a <HAL_ADC_ConfigChannel+0x46>
8000c66: 687b ldr r3, [r7, #4]
8000c68: 6adb ldr r3, [r3, #44] ; 0x2c
8000c6a: 2b01 cmp r3, #1
8000c6c: d00d beq.n 8000c8a <HAL_ADC_ConfigChannel+0x46>
8000c6e: 687b ldr r3, [r7, #4]
8000c70: 6adb ldr r3, [r3, #44] ; 0x2c
8000c72: 2b02 cmp r3, #2
8000c74: d009 beq.n 8000c8a <HAL_ADC_ConfigChannel+0x46>
8000c76: 687b ldr r3, [r7, #4]
8000c78: 6adb ldr r3, [r3, #44] ; 0x2c
8000c7a: 2b03 cmp r3, #3
8000c7c: d005 beq.n 8000c8a <HAL_ADC_ConfigChannel+0x46>
8000c7e: 687b ldr r3, [r7, #4]
8000c80: 6adb ldr r3, [r3, #44] ; 0x2c
8000c82: 2b04 cmp r3, #4
8000c84: d001 beq.n 8000c8a <HAL_ADC_ConfigChannel+0x46>
8000c86: 687b ldr r3, [r7, #4]
8000c88: 6adb ldr r3, [r3, #44] ; 0x2c
{
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
}
/* Process locked */
__HAL_LOCK(hadc);
8000c8a: 687b ldr r3, [r7, #4]
8000c8c: 2234 movs r2, #52 ; 0x34
8000c8e: 5c9b ldrb r3, [r3, r2]
8000c90: 2b01 cmp r3, #1
8000c92: d101 bne.n 8000c98 <HAL_ADC_ConfigChannel+0x54>
8000c94: 2302 movs r3, #2
8000c96: e0bb b.n 8000e10 <HAL_ADC_ConfigChannel+0x1cc>
8000c98: 687b ldr r3, [r7, #4]
8000c9a: 2234 movs r2, #52 ; 0x34
8000c9c: 2101 movs r1, #1
8000c9e: 5499 strb r1, [r3, r2]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8000ca0: 687b ldr r3, [r7, #4]
8000ca2: 681b ldr r3, [r3, #0]
8000ca4: 689b ldr r3, [r3, #8]
8000ca6: 2204 movs r2, #4
8000ca8: 4013 ands r3, r2
8000caa: d000 beq.n 8000cae <HAL_ADC_ConfigChannel+0x6a>
8000cac: e09f b.n 8000dee <HAL_ADC_ConfigChannel+0x1aa>
{
/* Configure channel: depending on rank setting, add it or remove it from */
/* ADC conversion sequencer. */
if (sConfig->Rank != ADC_RANK_NONE)
8000cae: 683b ldr r3, [r7, #0]
8000cb0: 685b ldr r3, [r3, #4]
8000cb2: 4a59 ldr r2, [pc, #356] ; (8000e18 <HAL_ADC_ConfigChannel+0x1d4>)
8000cb4: 4293 cmp r3, r2
8000cb6: d100 bne.n 8000cba <HAL_ADC_ConfigChannel+0x76>
8000cb8: e077 b.n 8000daa <HAL_ADC_ConfigChannel+0x166>
{
/* Regular sequence configuration */
/* Set the channel selection register from the selected channel */
hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
8000cba: 687b ldr r3, [r7, #4]
8000cbc: 681b ldr r3, [r3, #0]
8000cbe: 6a99 ldr r1, [r3, #40] ; 0x28
8000cc0: 683b ldr r3, [r7, #0]
8000cc2: 681b ldr r3, [r3, #0]
8000cc4: 2201 movs r2, #1
8000cc6: 409a lsls r2, r3
8000cc8: 687b ldr r3, [r7, #4]
8000cca: 681b ldr r3, [r3, #0]
8000ccc: 430a orrs r2, r1
8000cce: 629a str r2, [r3, #40] ; 0x28
/* Channel sampling time configuration */
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function with */
/* parameter "SamplingTime" (obsolete) only if not already set into */
/* ADC initialization structure with parameter "SamplingTimeCommon". */
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000cd0: 687b ldr r3, [r7, #4]
8000cd2: 6ada ldr r2, [r3, #44] ; 0x2c
8000cd4: 2380 movs r3, #128 ; 0x80
8000cd6: 055b lsls r3, r3, #21
8000cd8: 429a cmp r2, r3
8000cda: d037 beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000cdc: 687b ldr r3, [r7, #4]
8000cde: 6adb ldr r3, [r3, #44] ; 0x2c
8000ce0: 2b01 cmp r3, #1
8000ce2: d033 beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000ce4: 687b ldr r3, [r7, #4]
8000ce6: 6adb ldr r3, [r3, #44] ; 0x2c
8000ce8: 2b02 cmp r3, #2
8000cea: d02f beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000cec: 687b ldr r3, [r7, #4]
8000cee: 6adb ldr r3, [r3, #44] ; 0x2c
8000cf0: 2b03 cmp r3, #3
8000cf2: d02b beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 6adb ldr r3, [r3, #44] ; 0x2c
8000cf8: 2b04 cmp r3, #4
8000cfa: d027 beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000cfc: 687b ldr r3, [r7, #4]
8000cfe: 6adb ldr r3, [r3, #44] ; 0x2c
8000d00: 2b05 cmp r3, #5
8000d02: d023 beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000d04: 687b ldr r3, [r7, #4]
8000d06: 6adb ldr r3, [r3, #44] ; 0x2c
8000d08: 2b06 cmp r3, #6
8000d0a: d01f beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
8000d0c: 687b ldr r3, [r7, #4]
8000d0e: 6adb ldr r3, [r3, #44] ; 0x2c
8000d10: 2b07 cmp r3, #7
8000d12: d01b beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
{
/* Modify sampling time if needed (not needed in case of reoccurrence */
/* for several channels programmed consecutively into the sequencer) */
if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
8000d14: 683b ldr r3, [r7, #0]
8000d16: 689a ldr r2, [r3, #8]
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 681b ldr r3, [r3, #0]
8000d1c: 695b ldr r3, [r3, #20]
8000d1e: 2107 movs r1, #7
8000d20: 400b ands r3, r1
8000d22: 429a cmp r2, r3
8000d24: d012 beq.n 8000d4c <HAL_ADC_ConfigChannel+0x108>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000d26: 687b ldr r3, [r7, #4]
8000d28: 681b ldr r3, [r3, #0]
8000d2a: 695a ldr r2, [r3, #20]
8000d2c: 687b ldr r3, [r7, #4]
8000d2e: 681b ldr r3, [r3, #0]
8000d30: 2107 movs r1, #7
8000d32: 438a bics r2, r1
8000d34: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
8000d36: 687b ldr r3, [r7, #4]
8000d38: 681b ldr r3, [r3, #0]
8000d3a: 6959 ldr r1, [r3, #20]
8000d3c: 683b ldr r3, [r7, #0]
8000d3e: 689b ldr r3, [r3, #8]
8000d40: 2207 movs r2, #7
8000d42: 401a ands r2, r3
8000d44: 687b ldr r3, [r7, #4]
8000d46: 681b ldr r3, [r3, #0]
8000d48: 430a orrs r2, r1
8000d4a: 615a str r2, [r3, #20]
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000d4c: 683b ldr r3, [r7, #0]
8000d4e: 681b ldr r3, [r3, #0]
8000d50: 2b10 cmp r3, #16
8000d52: d003 beq.n 8000d5c <HAL_ADC_ConfigChannel+0x118>
8000d54: 683b ldr r3, [r7, #0]
8000d56: 681b ldr r3, [r3, #0]
8000d58: 2b11 cmp r3, #17
8000d5a: d152 bne.n 8000e02 <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, enable Temp. sensor measurement path. */
/* If Channel_17 is selected, enable VREFINT measurement path. */
/* If Channel_18 is selected, enable VBAT measurement path. */
ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000d5c: 4b2f ldr r3, [pc, #188] ; (8000e1c <HAL_ADC_ConfigChannel+0x1d8>)
8000d5e: 6819 ldr r1, [r3, #0]
8000d60: 683b ldr r3, [r7, #0]
8000d62: 681b ldr r3, [r3, #0]
8000d64: 2b10 cmp r3, #16
8000d66: d102 bne.n 8000d6e <HAL_ADC_ConfigChannel+0x12a>
8000d68: 2380 movs r3, #128 ; 0x80
8000d6a: 041b lsls r3, r3, #16
8000d6c: e001 b.n 8000d72 <HAL_ADC_ConfigChannel+0x12e>
8000d6e: 2380 movs r3, #128 ; 0x80
8000d70: 03db lsls r3, r3, #15
8000d72: 4a2a ldr r2, [pc, #168] ; (8000e1c <HAL_ADC_ConfigChannel+0x1d8>)
8000d74: 430b orrs r3, r1
8000d76: 6013 str r3, [r2, #0]
/* If Temp. sensor is selected, wait for stabilization delay */
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8000d78: 683b ldr r3, [r7, #0]
8000d7a: 681b ldr r3, [r3, #0]
8000d7c: 2b10 cmp r3, #16
8000d7e: d140 bne.n 8000e02 <HAL_ADC_ConfigChannel+0x1be>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8000d80: 4b27 ldr r3, [pc, #156] ; (8000e20 <HAL_ADC_ConfigChannel+0x1dc>)
8000d82: 681b ldr r3, [r3, #0]
8000d84: 4927 ldr r1, [pc, #156] ; (8000e24 <HAL_ADC_ConfigChannel+0x1e0>)
8000d86: 0018 movs r0, r3
8000d88: f7ff f9be bl 8000108 <__udivsi3>
8000d8c: 0003 movs r3, r0
8000d8e: 001a movs r2, r3
8000d90: 0013 movs r3, r2
8000d92: 009b lsls r3, r3, #2
8000d94: 189b adds r3, r3, r2
8000d96: 005b lsls r3, r3, #1
8000d98: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000d9a: e002 b.n 8000da2 <HAL_ADC_ConfigChannel+0x15e>
{
wait_loop_index--;
8000d9c: 68bb ldr r3, [r7, #8]
8000d9e: 3b01 subs r3, #1
8000da0: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000da2: 68bb ldr r3, [r7, #8]
8000da4: 2b00 cmp r3, #0
8000da6: d1f9 bne.n 8000d9c <HAL_ADC_ConfigChannel+0x158>
8000da8: e02b b.n 8000e02 <HAL_ADC_ConfigChannel+0x1be>
}
else
{
/* Regular sequence configuration */
/* Reset the channel selection register from the selected channel */
hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
8000daa: 687b ldr r3, [r7, #4]
8000dac: 681b ldr r3, [r3, #0]
8000dae: 6a9a ldr r2, [r3, #40] ; 0x28
8000db0: 683b ldr r3, [r7, #0]
8000db2: 681b ldr r3, [r3, #0]
8000db4: 2101 movs r1, #1
8000db6: 4099 lsls r1, r3
8000db8: 000b movs r3, r1
8000dba: 43d9 mvns r1, r3
8000dbc: 687b ldr r3, [r7, #4]
8000dbe: 681b ldr r3, [r3, #0]
8000dc0: 400a ands r2, r1
8000dc2: 629a str r2, [r3, #40] ; 0x28
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths disable: If internal channel selected, */
/* disable dedicated internal buffers and path. */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000dc4: 683b ldr r3, [r7, #0]
8000dc6: 681b ldr r3, [r3, #0]
8000dc8: 2b10 cmp r3, #16
8000dca: d003 beq.n 8000dd4 <HAL_ADC_ConfigChannel+0x190>
8000dcc: 683b ldr r3, [r7, #0]
8000dce: 681b ldr r3, [r3, #0]
8000dd0: 2b11 cmp r3, #17
8000dd2: d116 bne.n 8000e02 <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, disable Temp. sensor measurement path. */
/* If Channel_17 is selected, disable VREFINT measurement path. */
/* If Channel_18 is selected, disable VBAT measurement path. */
ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000dd4: 4b11 ldr r3, [pc, #68] ; (8000e1c <HAL_ADC_ConfigChannel+0x1d8>)
8000dd6: 6819 ldr r1, [r3, #0]
8000dd8: 683b ldr r3, [r7, #0]
8000dda: 681b ldr r3, [r3, #0]
8000ddc: 2b10 cmp r3, #16
8000dde: d101 bne.n 8000de4 <HAL_ADC_ConfigChannel+0x1a0>
8000de0: 4a11 ldr r2, [pc, #68] ; (8000e28 <HAL_ADC_ConfigChannel+0x1e4>)
8000de2: e000 b.n 8000de6 <HAL_ADC_ConfigChannel+0x1a2>
8000de4: 4a11 ldr r2, [pc, #68] ; (8000e2c <HAL_ADC_ConfigChannel+0x1e8>)
8000de6: 4b0d ldr r3, [pc, #52] ; (8000e1c <HAL_ADC_ConfigChannel+0x1d8>)
8000de8: 400a ands r2, r1
8000dea: 601a str r2, [r3, #0]
8000dec: e009 b.n 8000e02 <HAL_ADC_ConfigChannel+0x1be>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000dee: 687b ldr r3, [r7, #4]
8000df0: 6b9b ldr r3, [r3, #56] ; 0x38
8000df2: 2220 movs r2, #32
8000df4: 431a orrs r2, r3
8000df6: 687b ldr r3, [r7, #4]
8000df8: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
8000dfa: 230f movs r3, #15
8000dfc: 18fb adds r3, r7, r3
8000dfe: 2201 movs r2, #1
8000e00: 701a strb r2, [r3, #0]
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000e02: 687b ldr r3, [r7, #4]
8000e04: 2234 movs r2, #52 ; 0x34
8000e06: 2100 movs r1, #0
8000e08: 5499 strb r1, [r3, r2]
/* Return function status */
return tmp_hal_status;
8000e0a: 230f movs r3, #15
8000e0c: 18fb adds r3, r7, r3
8000e0e: 781b ldrb r3, [r3, #0]
}
8000e10: 0018 movs r0, r3
8000e12: 46bd mov sp, r7
8000e14: b004 add sp, #16
8000e16: bd80 pop {r7, pc}
8000e18: 00001001 .word 0x00001001
8000e1c: 40012708 .word 0x40012708
8000e20: 20000000 .word 0x20000000
8000e24: 000f4240 .word 0x000f4240
8000e28: ff7fffff .word 0xff7fffff
8000e2c: ffbfffff .word 0xffbfffff
08000e30 <ADC_Enable>:
* "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
8000e30: b580 push {r7, lr}
8000e32: b084 sub sp, #16
8000e34: af00 add r7, sp, #0
8000e36: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8000e38: 2300 movs r3, #0
8000e3a: 60fb str r3, [r7, #12]
__IO uint32_t wait_loop_index = 0U;
8000e3c: 2300 movs r3, #0
8000e3e: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (ADC_IS_ENABLE(hadc) == RESET)
8000e40: 687b ldr r3, [r7, #4]
8000e42: 681b ldr r3, [r3, #0]
8000e44: 689b ldr r3, [r3, #8]
8000e46: 2203 movs r2, #3
8000e48: 4013 ands r3, r2
8000e4a: 2b01 cmp r3, #1
8000e4c: d112 bne.n 8000e74 <ADC_Enable+0x44>
8000e4e: 687b ldr r3, [r7, #4]
8000e50: 681b ldr r3, [r3, #0]
8000e52: 681b ldr r3, [r3, #0]
8000e54: 2201 movs r2, #1
8000e56: 4013 ands r3, r2
8000e58: 2b01 cmp r3, #1
8000e5a: d009 beq.n 8000e70 <ADC_Enable+0x40>
8000e5c: 687b ldr r3, [r7, #4]
8000e5e: 681b ldr r3, [r3, #0]
8000e60: 68da ldr r2, [r3, #12]
8000e62: 2380 movs r3, #128 ; 0x80
8000e64: 021b lsls r3, r3, #8
8000e66: 401a ands r2, r3
8000e68: 2380 movs r3, #128 ; 0x80
8000e6a: 021b lsls r3, r3, #8
8000e6c: 429a cmp r2, r3
8000e6e: d101 bne.n 8000e74 <ADC_Enable+0x44>
8000e70: 2301 movs r3, #1
8000e72: e000 b.n 8000e76 <ADC_Enable+0x46>
8000e74: 2300 movs r3, #0
8000e76: 2b00 cmp r3, #0
8000e78: d152 bne.n 8000f20 <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
8000e7a: 687b ldr r3, [r7, #4]
8000e7c: 681b ldr r3, [r3, #0]
8000e7e: 689b ldr r3, [r3, #8]
8000e80: 4a2a ldr r2, [pc, #168] ; (8000f2c <ADC_Enable+0xfc>)
8000e82: 4013 ands r3, r2
8000e84: d00d beq.n 8000ea2 <ADC_Enable+0x72>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000e86: 687b ldr r3, [r7, #4]
8000e88: 6b9b ldr r3, [r3, #56] ; 0x38
8000e8a: 2210 movs r2, #16
8000e8c: 431a orrs r2, r3
8000e8e: 687b ldr r3, [r7, #4]
8000e90: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000e92: 687b ldr r3, [r7, #4]
8000e94: 6bdb ldr r3, [r3, #60] ; 0x3c
8000e96: 2201 movs r2, #1
8000e98: 431a orrs r2, r3
8000e9a: 687b ldr r3, [r7, #4]
8000e9c: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8000e9e: 2301 movs r3, #1
8000ea0: e03f b.n 8000f22 <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
__HAL_ADC_ENABLE(hadc);
8000ea2: 687b ldr r3, [r7, #4]
8000ea4: 681b ldr r3, [r3, #0]
8000ea6: 689a ldr r2, [r3, #8]
8000ea8: 687b ldr r3, [r7, #4]
8000eaa: 681b ldr r3, [r3, #0]
8000eac: 2101 movs r1, #1
8000eae: 430a orrs r2, r1
8000eb0: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
8000eb2: 4b1f ldr r3, [pc, #124] ; (8000f30 <ADC_Enable+0x100>)
8000eb4: 681b ldr r3, [r3, #0]
8000eb6: 491f ldr r1, [pc, #124] ; (8000f34 <ADC_Enable+0x104>)
8000eb8: 0018 movs r0, r3
8000eba: f7ff f925 bl 8000108 <__udivsi3>
8000ebe: 0003 movs r3, r0
8000ec0: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000ec2: e002 b.n 8000eca <ADC_Enable+0x9a>
{
wait_loop_index--;
8000ec4: 68bb ldr r3, [r7, #8]
8000ec6: 3b01 subs r3, #1
8000ec8: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000eca: 68bb ldr r3, [r7, #8]
8000ecc: 2b00 cmp r3, #0
8000ece: d1f9 bne.n 8000ec4 <ADC_Enable+0x94>
}
/* Get tick count */
tickstart = HAL_GetTick();
8000ed0: f7ff fcce bl 8000870 <HAL_GetTick>
8000ed4: 0003 movs r3, r0
8000ed6: 60fb str r3, [r7, #12]
/* Wait for ADC effectively enabled */
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
8000ed8: e01b b.n 8000f12 <ADC_Enable+0xe2>
{
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8000eda: f7ff fcc9 bl 8000870 <HAL_GetTick>
8000ede: 0002 movs r2, r0
8000ee0: 68fb ldr r3, [r7, #12]
8000ee2: 1ad3 subs r3, r2, r3
8000ee4: 2b02 cmp r3, #2
8000ee6: d914 bls.n 8000f12 <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
8000ee8: 687b ldr r3, [r7, #4]
8000eea: 681b ldr r3, [r3, #0]
8000eec: 681b ldr r3, [r3, #0]
8000eee: 2201 movs r2, #1
8000ef0: 4013 ands r3, r2
8000ef2: 2b01 cmp r3, #1
8000ef4: d00d beq.n 8000f12 <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000ef6: 687b ldr r3, [r7, #4]
8000ef8: 6b9b ldr r3, [r3, #56] ; 0x38
8000efa: 2210 movs r2, #16
8000efc: 431a orrs r2, r3
8000efe: 687b ldr r3, [r7, #4]
8000f00: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000f02: 687b ldr r3, [r7, #4]
8000f04: 6bdb ldr r3, [r3, #60] ; 0x3c
8000f06: 2201 movs r2, #1
8000f08: 431a orrs r2, r3
8000f0a: 687b ldr r3, [r7, #4]
8000f0c: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8000f0e: 2301 movs r3, #1
8000f10: e007 b.n 8000f22 <ADC_Enable+0xf2>
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
8000f12: 687b ldr r3, [r7, #4]
8000f14: 681b ldr r3, [r3, #0]
8000f16: 681b ldr r3, [r3, #0]
8000f18: 2201 movs r2, #1
8000f1a: 4013 ands r3, r2
8000f1c: 2b01 cmp r3, #1
8000f1e: d1dc bne.n 8000eda <ADC_Enable+0xaa>
}
}
}
/* Return HAL status */
return HAL_OK;
8000f20: 2300 movs r3, #0
}
8000f22: 0018 movs r0, r3
8000f24: 46bd mov sp, r7
8000f26: b004 add sp, #16
8000f28: bd80 pop {r7, pc}
8000f2a: 46c0 nop ; (mov r8, r8)
8000f2c: 80000017 .word 0x80000017
8000f30: 20000000 .word 0x20000000
8000f34: 000f4240 .word 0x000f4240
08000f38 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
{
8000f38: b580 push {r7, lr}
8000f3a: b084 sub sp, #16
8000f3c: af00 add r7, sp, #0
8000f3e: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8000f40: 2300 movs r3, #0
8000f42: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if (ADC_IS_ENABLE(hadc) != RESET)
8000f44: 687b ldr r3, [r7, #4]
8000f46: 681b ldr r3, [r3, #0]
8000f48: 689b ldr r3, [r3, #8]
8000f4a: 2203 movs r2, #3
8000f4c: 4013 ands r3, r2
8000f4e: 2b01 cmp r3, #1
8000f50: d112 bne.n 8000f78 <ADC_Disable+0x40>
8000f52: 687b ldr r3, [r7, #4]
8000f54: 681b ldr r3, [r3, #0]
8000f56: 681b ldr r3, [r3, #0]
8000f58: 2201 movs r2, #1
8000f5a: 4013 ands r3, r2
8000f5c: 2b01 cmp r3, #1
8000f5e: d009 beq.n 8000f74 <ADC_Disable+0x3c>
8000f60: 687b ldr r3, [r7, #4]
8000f62: 681b ldr r3, [r3, #0]
8000f64: 68da ldr r2, [r3, #12]
8000f66: 2380 movs r3, #128 ; 0x80
8000f68: 021b lsls r3, r3, #8
8000f6a: 401a ands r2, r3
8000f6c: 2380 movs r3, #128 ; 0x80
8000f6e: 021b lsls r3, r3, #8
8000f70: 429a cmp r2, r3
8000f72: d101 bne.n 8000f78 <ADC_Disable+0x40>
8000f74: 2301 movs r3, #1
8000f76: e000 b.n 8000f7a <ADC_Disable+0x42>
8000f78: 2300 movs r3, #0
8000f7a: 2b00 cmp r3, #0
8000f7c: d048 beq.n 8001010 <ADC_Disable+0xd8>
{
/* Check if conditions to disable the ADC are fulfilled */
if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
8000f7e: 687b ldr r3, [r7, #4]
8000f80: 681b ldr r3, [r3, #0]
8000f82: 689b ldr r3, [r3, #8]
8000f84: 2205 movs r2, #5
8000f86: 4013 ands r3, r2
8000f88: 2b01 cmp r3, #1
8000f8a: d110 bne.n 8000fae <ADC_Disable+0x76>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8000f8c: 687b ldr r3, [r7, #4]
8000f8e: 681b ldr r3, [r3, #0]
8000f90: 689a ldr r2, [r3, #8]
8000f92: 687b ldr r3, [r7, #4]
8000f94: 681b ldr r3, [r3, #0]
8000f96: 2102 movs r1, #2
8000f98: 430a orrs r2, r1
8000f9a: 609a str r2, [r3, #8]
8000f9c: 687b ldr r3, [r7, #4]
8000f9e: 681b ldr r3, [r3, #0]
8000fa0: 2203 movs r2, #3
8000fa2: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
8000fa4: f7ff fc64 bl 8000870 <HAL_GetTick>
8000fa8: 0003 movs r3, r0
8000faa: 60fb str r3, [r7, #12]
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
8000fac: e029 b.n 8001002 <ADC_Disable+0xca>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000fae: 687b ldr r3, [r7, #4]
8000fb0: 6b9b ldr r3, [r3, #56] ; 0x38
8000fb2: 2210 movs r2, #16
8000fb4: 431a orrs r2, r3
8000fb6: 687b ldr r3, [r7, #4]
8000fb8: 639a str r2, [r3, #56] ; 0x38
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000fba: 687b ldr r3, [r7, #4]
8000fbc: 6bdb ldr r3, [r3, #60] ; 0x3c
8000fbe: 2201 movs r2, #1
8000fc0: 431a orrs r2, r3
8000fc2: 687b ldr r3, [r7, #4]
8000fc4: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8000fc6: 2301 movs r3, #1
8000fc8: e023 b.n 8001012 <ADC_Disable+0xda>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8000fca: f7ff fc51 bl 8000870 <HAL_GetTick>
8000fce: 0002 movs r2, r0
8000fd0: 68fb ldr r3, [r7, #12]
8000fd2: 1ad3 subs r3, r2, r3
8000fd4: 2b02 cmp r3, #2
8000fd6: d914 bls.n 8001002 <ADC_Disable+0xca>
{
/* New check to avoid false timeout detection in case of preemption */
if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
8000fd8: 687b ldr r3, [r7, #4]
8000fda: 681b ldr r3, [r3, #0]
8000fdc: 689b ldr r3, [r3, #8]
8000fde: 2201 movs r2, #1
8000fe0: 4013 ands r3, r2
8000fe2: 2b01 cmp r3, #1
8000fe4: d10d bne.n 8001002 <ADC_Disable+0xca>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000fe6: 687b ldr r3, [r7, #4]
8000fe8: 6b9b ldr r3, [r3, #56] ; 0x38
8000fea: 2210 movs r2, #16
8000fec: 431a orrs r2, r3
8000fee: 687b ldr r3, [r7, #4]
8000ff0: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000ff2: 687b ldr r3, [r7, #4]
8000ff4: 6bdb ldr r3, [r3, #60] ; 0x3c
8000ff6: 2201 movs r2, #1
8000ff8: 431a orrs r2, r3
8000ffa: 687b ldr r3, [r7, #4]
8000ffc: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8000ffe: 2301 movs r3, #1
8001000: e007 b.n 8001012 <ADC_Disable+0xda>
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
8001002: 687b ldr r3, [r7, #4]
8001004: 681b ldr r3, [r3, #0]
8001006: 689b ldr r3, [r3, #8]
8001008: 2201 movs r2, #1
800100a: 4013 ands r3, r2
800100c: 2b01 cmp r3, #1
800100e: d0dc beq.n 8000fca <ADC_Disable+0x92>
}
}
}
/* Return HAL status */
return HAL_OK;
8001010: 2300 movs r3, #0
}
8001012: 0018 movs r0, r3
8001014: 46bd mov sp, r7
8001016: b004 add sp, #16
8001018: bd80 pop {r7, pc}
0800101a <ADC_ConversionStop>:
* stopped to disable the ADC.
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
{
800101a: b580 push {r7, lr}
800101c: b084 sub sp, #16
800101e: af00 add r7, sp, #0
8001020: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8001022: 2300 movs r3, #0
8001024: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Verification if ADC is not already stopped on regular group to bypass */
/* this function if not needed. */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
8001026: 687b ldr r3, [r7, #4]
8001028: 681b ldr r3, [r3, #0]
800102a: 689b ldr r3, [r3, #8]
800102c: 2204 movs r2, #4
800102e: 4013 ands r3, r2
8001030: d03a beq.n 80010a8 <ADC_ConversionStop+0x8e>
{
/* Stop potential conversion on going on regular group */
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
8001032: 687b ldr r3, [r7, #4]
8001034: 681b ldr r3, [r3, #0]
8001036: 689b ldr r3, [r3, #8]
8001038: 2204 movs r2, #4
800103a: 4013 ands r3, r2
800103c: 2b04 cmp r3, #4
800103e: d10d bne.n 800105c <ADC_ConversionStop+0x42>
HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
8001040: 687b ldr r3, [r7, #4]
8001042: 681b ldr r3, [r3, #0]
8001044: 689b ldr r3, [r3, #8]
8001046: 2202 movs r2, #2
8001048: 4013 ands r3, r2
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
800104a: d107 bne.n 800105c <ADC_ConversionStop+0x42>
{
/* Stop conversions on regular group */
hadc->Instance->CR |= ADC_CR_ADSTP;
800104c: 687b ldr r3, [r7, #4]
800104e: 681b ldr r3, [r3, #0]
8001050: 689a ldr r2, [r3, #8]
8001052: 687b ldr r3, [r7, #4]
8001054: 681b ldr r3, [r3, #0]
8001056: 2110 movs r1, #16
8001058: 430a orrs r2, r1
800105a: 609a str r2, [r3, #8]
}
/* Wait for conversion effectively stopped */
/* Get tick count */
tickstart = HAL_GetTick();
800105c: f7ff fc08 bl 8000870 <HAL_GetTick>
8001060: 0003 movs r3, r0
8001062: 60fb str r3, [r7, #12]
while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
8001064: e01a b.n 800109c <ADC_ConversionStop+0x82>
{
if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
8001066: f7ff fc03 bl 8000870 <HAL_GetTick>
800106a: 0002 movs r2, r0
800106c: 68fb ldr r3, [r7, #12]
800106e: 1ad3 subs r3, r2, r3
8001070: 2b02 cmp r3, #2
8001072: d913 bls.n 800109c <ADC_ConversionStop+0x82>
{
/* New check to avoid false timeout detection in case of preemption */
if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
8001074: 687b ldr r3, [r7, #4]
8001076: 681b ldr r3, [r3, #0]
8001078: 689b ldr r3, [r3, #8]
800107a: 2204 movs r2, #4
800107c: 4013 ands r3, r2
800107e: d00d beq.n 800109c <ADC_ConversionStop+0x82>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001080: 687b ldr r3, [r7, #4]
8001082: 6b9b ldr r3, [r3, #56] ; 0x38
8001084: 2210 movs r2, #16
8001086: 431a orrs r2, r3
8001088: 687b ldr r3, [r7, #4]
800108a: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800108c: 687b ldr r3, [r7, #4]
800108e: 6bdb ldr r3, [r3, #60] ; 0x3c
8001090: 2201 movs r2, #1
8001092: 431a orrs r2, r3
8001094: 687b ldr r3, [r7, #4]
8001096: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8001098: 2301 movs r3, #1
800109a: e006 b.n 80010aa <ADC_ConversionStop+0x90>
while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
800109c: 687b ldr r3, [r7, #4]
800109e: 681b ldr r3, [r3, #0]
80010a0: 689b ldr r3, [r3, #8]
80010a2: 2204 movs r2, #4
80010a4: 4013 ands r3, r2
80010a6: d1de bne.n 8001066 <ADC_ConversionStop+0x4c>
}
}
}
/* Return HAL status */
return HAL_OK;
80010a8: 2300 movs r3, #0
}
80010aa: 0018 movs r0, r3
80010ac: 46bd mov sp, r7
80010ae: b004 add sp, #16
80010b0: bd80 pop {r7, pc}
...
080010b4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80010b4: b590 push {r4, r7, lr}
80010b6: b083 sub sp, #12
80010b8: af00 add r7, sp, #0
80010ba: 0002 movs r2, r0
80010bc: 6039 str r1, [r7, #0]
80010be: 1dfb adds r3, r7, #7
80010c0: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80010c2: 1dfb adds r3, r7, #7
80010c4: 781b ldrb r3, [r3, #0]
80010c6: 2b7f cmp r3, #127 ; 0x7f
80010c8: d828 bhi.n 800111c <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80010ca: 4a2f ldr r2, [pc, #188] ; (8001188 <__NVIC_SetPriority+0xd4>)
80010cc: 1dfb adds r3, r7, #7
80010ce: 781b ldrb r3, [r3, #0]
80010d0: b25b sxtb r3, r3
80010d2: 089b lsrs r3, r3, #2
80010d4: 33c0 adds r3, #192 ; 0xc0
80010d6: 009b lsls r3, r3, #2
80010d8: 589b ldr r3, [r3, r2]
80010da: 1dfa adds r2, r7, #7
80010dc: 7812 ldrb r2, [r2, #0]
80010de: 0011 movs r1, r2
80010e0: 2203 movs r2, #3
80010e2: 400a ands r2, r1
80010e4: 00d2 lsls r2, r2, #3
80010e6: 21ff movs r1, #255 ; 0xff
80010e8: 4091 lsls r1, r2
80010ea: 000a movs r2, r1
80010ec: 43d2 mvns r2, r2
80010ee: 401a ands r2, r3
80010f0: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80010f2: 683b ldr r3, [r7, #0]
80010f4: 019b lsls r3, r3, #6
80010f6: 22ff movs r2, #255 ; 0xff
80010f8: 401a ands r2, r3
80010fa: 1dfb adds r3, r7, #7
80010fc: 781b ldrb r3, [r3, #0]
80010fe: 0018 movs r0, r3
8001100: 2303 movs r3, #3
8001102: 4003 ands r3, r0
8001104: 00db lsls r3, r3, #3
8001106: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001108: 481f ldr r0, [pc, #124] ; (8001188 <__NVIC_SetPriority+0xd4>)
800110a: 1dfb adds r3, r7, #7
800110c: 781b ldrb r3, [r3, #0]
800110e: b25b sxtb r3, r3
8001110: 089b lsrs r3, r3, #2
8001112: 430a orrs r2, r1
8001114: 33c0 adds r3, #192 ; 0xc0
8001116: 009b lsls r3, r3, #2
8001118: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
800111a: e031 b.n 8001180 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800111c: 4a1b ldr r2, [pc, #108] ; (800118c <__NVIC_SetPriority+0xd8>)
800111e: 1dfb adds r3, r7, #7
8001120: 781b ldrb r3, [r3, #0]
8001122: 0019 movs r1, r3
8001124: 230f movs r3, #15
8001126: 400b ands r3, r1
8001128: 3b08 subs r3, #8
800112a: 089b lsrs r3, r3, #2
800112c: 3306 adds r3, #6
800112e: 009b lsls r3, r3, #2
8001130: 18d3 adds r3, r2, r3
8001132: 3304 adds r3, #4
8001134: 681b ldr r3, [r3, #0]
8001136: 1dfa adds r2, r7, #7
8001138: 7812 ldrb r2, [r2, #0]
800113a: 0011 movs r1, r2
800113c: 2203 movs r2, #3
800113e: 400a ands r2, r1
8001140: 00d2 lsls r2, r2, #3
8001142: 21ff movs r1, #255 ; 0xff
8001144: 4091 lsls r1, r2
8001146: 000a movs r2, r1
8001148: 43d2 mvns r2, r2
800114a: 401a ands r2, r3
800114c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800114e: 683b ldr r3, [r7, #0]
8001150: 019b lsls r3, r3, #6
8001152: 22ff movs r2, #255 ; 0xff
8001154: 401a ands r2, r3
8001156: 1dfb adds r3, r7, #7
8001158: 781b ldrb r3, [r3, #0]
800115a: 0018 movs r0, r3
800115c: 2303 movs r3, #3
800115e: 4003 ands r3, r0
8001160: 00db lsls r3, r3, #3
8001162: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001164: 4809 ldr r0, [pc, #36] ; (800118c <__NVIC_SetPriority+0xd8>)
8001166: 1dfb adds r3, r7, #7
8001168: 781b ldrb r3, [r3, #0]
800116a: 001c movs r4, r3
800116c: 230f movs r3, #15
800116e: 4023 ands r3, r4
8001170: 3b08 subs r3, #8
8001172: 089b lsrs r3, r3, #2
8001174: 430a orrs r2, r1
8001176: 3306 adds r3, #6
8001178: 009b lsls r3, r3, #2
800117a: 18c3 adds r3, r0, r3
800117c: 3304 adds r3, #4
800117e: 601a str r2, [r3, #0]
}
8001180: 46c0 nop ; (mov r8, r8)
8001182: 46bd mov sp, r7
8001184: b003 add sp, #12
8001186: bd90 pop {r4, r7, pc}
8001188: e000e100 .word 0xe000e100
800118c: e000ed00 .word 0xe000ed00
08001190 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001190: b580 push {r7, lr}
8001192: b082 sub sp, #8
8001194: af00 add r7, sp, #0
8001196: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001198: 687b ldr r3, [r7, #4]
800119a: 1e5a subs r2, r3, #1
800119c: 2380 movs r3, #128 ; 0x80
800119e: 045b lsls r3, r3, #17
80011a0: 429a cmp r2, r3
80011a2: d301 bcc.n 80011a8 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
80011a4: 2301 movs r3, #1
80011a6: e010 b.n 80011ca <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80011a8: 4b0a ldr r3, [pc, #40] ; (80011d4 <SysTick_Config+0x44>)
80011aa: 687a ldr r2, [r7, #4]
80011ac: 3a01 subs r2, #1
80011ae: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80011b0: 2301 movs r3, #1
80011b2: 425b negs r3, r3
80011b4: 2103 movs r1, #3
80011b6: 0018 movs r0, r3
80011b8: f7ff ff7c bl 80010b4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80011bc: 4b05 ldr r3, [pc, #20] ; (80011d4 <SysTick_Config+0x44>)
80011be: 2200 movs r2, #0
80011c0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80011c2: 4b04 ldr r3, [pc, #16] ; (80011d4 <SysTick_Config+0x44>)
80011c4: 2207 movs r2, #7
80011c6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80011c8: 2300 movs r3, #0
}
80011ca: 0018 movs r0, r3
80011cc: 46bd mov sp, r7
80011ce: b002 add sp, #8
80011d0: bd80 pop {r7, pc}
80011d2: 46c0 nop ; (mov r8, r8)
80011d4: e000e010 .word 0xe000e010
080011d8 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80011d8: b580 push {r7, lr}
80011da: b084 sub sp, #16
80011dc: af00 add r7, sp, #0
80011de: 60b9 str r1, [r7, #8]
80011e0: 607a str r2, [r7, #4]
80011e2: 210f movs r1, #15
80011e4: 187b adds r3, r7, r1
80011e6: 1c02 adds r2, r0, #0
80011e8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
80011ea: 68ba ldr r2, [r7, #8]
80011ec: 187b adds r3, r7, r1
80011ee: 781b ldrb r3, [r3, #0]
80011f0: b25b sxtb r3, r3
80011f2: 0011 movs r1, r2
80011f4: 0018 movs r0, r3
80011f6: f7ff ff5d bl 80010b4 <__NVIC_SetPriority>
}
80011fa: 46c0 nop ; (mov r8, r8)
80011fc: 46bd mov sp, r7
80011fe: b004 add sp, #16
8001200: bd80 pop {r7, pc}
08001202 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8001202: b580 push {r7, lr}
8001204: b082 sub sp, #8
8001206: af00 add r7, sp, #0
8001208: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
800120a: 687b ldr r3, [r7, #4]
800120c: 0018 movs r0, r3
800120e: f7ff ffbf bl 8001190 <SysTick_Config>
8001212: 0003 movs r3, r0
}
8001214: 0018 movs r0, r3
8001216: 46bd mov sp, r7
8001218: b002 add sp, #8
800121a: bd80 pop {r7, pc}
0800121c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800121c: b580 push {r7, lr}
800121e: b086 sub sp, #24
8001220: af00 add r7, sp, #0
8001222: 6078 str r0, [r7, #4]
8001224: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001226: 2300 movs r3, #0
8001228: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800122a: e14f b.n 80014cc <HAL_GPIO_Init+0x2b0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
800122c: 683b ldr r3, [r7, #0]
800122e: 681b ldr r3, [r3, #0]
8001230: 2101 movs r1, #1
8001232: 697a ldr r2, [r7, #20]
8001234: 4091 lsls r1, r2
8001236: 000a movs r2, r1
8001238: 4013 ands r3, r2
800123a: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
800123c: 68fb ldr r3, [r7, #12]
800123e: 2b00 cmp r3, #0
8001240: d100 bne.n 8001244 <HAL_GPIO_Init+0x28>
8001242: e140 b.n 80014c6 <HAL_GPIO_Init+0x2aa>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001244: 683b ldr r3, [r7, #0]
8001246: 685b ldr r3, [r3, #4]
8001248: 2203 movs r2, #3
800124a: 4013 ands r3, r2
800124c: 2b01 cmp r3, #1
800124e: d005 beq.n 800125c <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001250: 683b ldr r3, [r7, #0]
8001252: 685b ldr r3, [r3, #4]
8001254: 2203 movs r2, #3
8001256: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001258: 2b02 cmp r3, #2
800125a: d130 bne.n 80012be <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800125c: 687b ldr r3, [r7, #4]
800125e: 689b ldr r3, [r3, #8]
8001260: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8001262: 697b ldr r3, [r7, #20]
8001264: 005b lsls r3, r3, #1
8001266: 2203 movs r2, #3
8001268: 409a lsls r2, r3
800126a: 0013 movs r3, r2
800126c: 43da mvns r2, r3
800126e: 693b ldr r3, [r7, #16]
8001270: 4013 ands r3, r2
8001272: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001274: 683b ldr r3, [r7, #0]
8001276: 68da ldr r2, [r3, #12]
8001278: 697b ldr r3, [r7, #20]
800127a: 005b lsls r3, r3, #1
800127c: 409a lsls r2, r3
800127e: 0013 movs r3, r2
8001280: 693a ldr r2, [r7, #16]
8001282: 4313 orrs r3, r2
8001284: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001286: 687b ldr r3, [r7, #4]
8001288: 693a ldr r2, [r7, #16]
800128a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800128c: 687b ldr r3, [r7, #4]
800128e: 685b ldr r3, [r3, #4]
8001290: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001292: 2201 movs r2, #1
8001294: 697b ldr r3, [r7, #20]
8001296: 409a lsls r2, r3
8001298: 0013 movs r3, r2
800129a: 43da mvns r2, r3
800129c: 693b ldr r3, [r7, #16]
800129e: 4013 ands r3, r2
80012a0: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80012a2: 683b ldr r3, [r7, #0]
80012a4: 685b ldr r3, [r3, #4]
80012a6: 091b lsrs r3, r3, #4
80012a8: 2201 movs r2, #1
80012aa: 401a ands r2, r3
80012ac: 697b ldr r3, [r7, #20]
80012ae: 409a lsls r2, r3
80012b0: 0013 movs r3, r2
80012b2: 693a ldr r2, [r7, #16]
80012b4: 4313 orrs r3, r2
80012b6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80012b8: 687b ldr r3, [r7, #4]
80012ba: 693a ldr r2, [r7, #16]
80012bc: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80012be: 683b ldr r3, [r7, #0]
80012c0: 685b ldr r3, [r3, #4]
80012c2: 2203 movs r2, #3
80012c4: 4013 ands r3, r2
80012c6: 2b03 cmp r3, #3
80012c8: d017 beq.n 80012fa <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80012ca: 687b ldr r3, [r7, #4]
80012cc: 68db ldr r3, [r3, #12]
80012ce: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
80012d0: 697b ldr r3, [r7, #20]
80012d2: 005b lsls r3, r3, #1
80012d4: 2203 movs r2, #3
80012d6: 409a lsls r2, r3
80012d8: 0013 movs r3, r2
80012da: 43da mvns r2, r3
80012dc: 693b ldr r3, [r7, #16]
80012de: 4013 ands r3, r2
80012e0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80012e2: 683b ldr r3, [r7, #0]
80012e4: 689a ldr r2, [r3, #8]
80012e6: 697b ldr r3, [r7, #20]
80012e8: 005b lsls r3, r3, #1
80012ea: 409a lsls r2, r3
80012ec: 0013 movs r3, r2
80012ee: 693a ldr r2, [r7, #16]
80012f0: 4313 orrs r3, r2
80012f2: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80012f4: 687b ldr r3, [r7, #4]
80012f6: 693a ldr r2, [r7, #16]
80012f8: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80012fa: 683b ldr r3, [r7, #0]
80012fc: 685b ldr r3, [r3, #4]
80012fe: 2203 movs r2, #3
8001300: 4013 ands r3, r2
8001302: 2b02 cmp r3, #2
8001304: d123 bne.n 800134e <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8001306: 697b ldr r3, [r7, #20]
8001308: 08da lsrs r2, r3, #3
800130a: 687b ldr r3, [r7, #4]
800130c: 3208 adds r2, #8
800130e: 0092 lsls r2, r2, #2
8001310: 58d3 ldr r3, [r2, r3]
8001312: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8001314: 697b ldr r3, [r7, #20]
8001316: 2207 movs r2, #7
8001318: 4013 ands r3, r2
800131a: 009b lsls r3, r3, #2
800131c: 220f movs r2, #15
800131e: 409a lsls r2, r3
8001320: 0013 movs r3, r2
8001322: 43da mvns r2, r3
8001324: 693b ldr r3, [r7, #16]
8001326: 4013 ands r3, r2
8001328: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
800132a: 683b ldr r3, [r7, #0]
800132c: 691a ldr r2, [r3, #16]
800132e: 697b ldr r3, [r7, #20]
8001330: 2107 movs r1, #7
8001332: 400b ands r3, r1
8001334: 009b lsls r3, r3, #2
8001336: 409a lsls r2, r3
8001338: 0013 movs r3, r2
800133a: 693a ldr r2, [r7, #16]
800133c: 4313 orrs r3, r2
800133e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001340: 697b ldr r3, [r7, #20]
8001342: 08da lsrs r2, r3, #3
8001344: 687b ldr r3, [r7, #4]
8001346: 3208 adds r2, #8
8001348: 0092 lsls r2, r2, #2
800134a: 6939 ldr r1, [r7, #16]
800134c: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800134e: 687b ldr r3, [r7, #4]
8001350: 681b ldr r3, [r3, #0]
8001352: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8001354: 697b ldr r3, [r7, #20]
8001356: 005b lsls r3, r3, #1
8001358: 2203 movs r2, #3
800135a: 409a lsls r2, r3
800135c: 0013 movs r3, r2
800135e: 43da mvns r2, r3
8001360: 693b ldr r3, [r7, #16]
8001362: 4013 ands r3, r2
8001364: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001366: 683b ldr r3, [r7, #0]
8001368: 685b ldr r3, [r3, #4]
800136a: 2203 movs r2, #3
800136c: 401a ands r2, r3
800136e: 697b ldr r3, [r7, #20]
8001370: 005b lsls r3, r3, #1
8001372: 409a lsls r2, r3
8001374: 0013 movs r3, r2
8001376: 693a ldr r2, [r7, #16]
8001378: 4313 orrs r3, r2
800137a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
800137c: 687b ldr r3, [r7, #4]
800137e: 693a ldr r2, [r7, #16]
8001380: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001382: 683b ldr r3, [r7, #0]
8001384: 685a ldr r2, [r3, #4]
8001386: 23c0 movs r3, #192 ; 0xc0
8001388: 029b lsls r3, r3, #10
800138a: 4013 ands r3, r2
800138c: d100 bne.n 8001390 <HAL_GPIO_Init+0x174>
800138e: e09a b.n 80014c6 <HAL_GPIO_Init+0x2aa>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001390: 4b54 ldr r3, [pc, #336] ; (80014e4 <HAL_GPIO_Init+0x2c8>)
8001392: 699a ldr r2, [r3, #24]
8001394: 4b53 ldr r3, [pc, #332] ; (80014e4 <HAL_GPIO_Init+0x2c8>)
8001396: 2101 movs r1, #1
8001398: 430a orrs r2, r1
800139a: 619a str r2, [r3, #24]
800139c: 4b51 ldr r3, [pc, #324] ; (80014e4 <HAL_GPIO_Init+0x2c8>)
800139e: 699b ldr r3, [r3, #24]
80013a0: 2201 movs r2, #1
80013a2: 4013 ands r3, r2
80013a4: 60bb str r3, [r7, #8]
80013a6: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
80013a8: 4a4f ldr r2, [pc, #316] ; (80014e8 <HAL_GPIO_Init+0x2cc>)
80013aa: 697b ldr r3, [r7, #20]
80013ac: 089b lsrs r3, r3, #2
80013ae: 3302 adds r3, #2
80013b0: 009b lsls r3, r3, #2
80013b2: 589b ldr r3, [r3, r2]
80013b4: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
80013b6: 697b ldr r3, [r7, #20]
80013b8: 2203 movs r2, #3
80013ba: 4013 ands r3, r2
80013bc: 009b lsls r3, r3, #2
80013be: 220f movs r2, #15
80013c0: 409a lsls r2, r3
80013c2: 0013 movs r3, r2
80013c4: 43da mvns r2, r3
80013c6: 693b ldr r3, [r7, #16]
80013c8: 4013 ands r3, r2
80013ca: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80013cc: 687a ldr r2, [r7, #4]
80013ce: 2390 movs r3, #144 ; 0x90
80013d0: 05db lsls r3, r3, #23
80013d2: 429a cmp r2, r3
80013d4: d013 beq.n 80013fe <HAL_GPIO_Init+0x1e2>
80013d6: 687b ldr r3, [r7, #4]
80013d8: 4a44 ldr r2, [pc, #272] ; (80014ec <HAL_GPIO_Init+0x2d0>)
80013da: 4293 cmp r3, r2
80013dc: d00d beq.n 80013fa <HAL_GPIO_Init+0x1de>
80013de: 687b ldr r3, [r7, #4]
80013e0: 4a43 ldr r2, [pc, #268] ; (80014f0 <HAL_GPIO_Init+0x2d4>)
80013e2: 4293 cmp r3, r2
80013e4: d007 beq.n 80013f6 <HAL_GPIO_Init+0x1da>
80013e6: 687b ldr r3, [r7, #4]
80013e8: 4a42 ldr r2, [pc, #264] ; (80014f4 <HAL_GPIO_Init+0x2d8>)
80013ea: 4293 cmp r3, r2
80013ec: d101 bne.n 80013f2 <HAL_GPIO_Init+0x1d6>
80013ee: 2303 movs r3, #3
80013f0: e006 b.n 8001400 <HAL_GPIO_Init+0x1e4>
80013f2: 2305 movs r3, #5
80013f4: e004 b.n 8001400 <HAL_GPIO_Init+0x1e4>
80013f6: 2302 movs r3, #2
80013f8: e002 b.n 8001400 <HAL_GPIO_Init+0x1e4>
80013fa: 2301 movs r3, #1
80013fc: e000 b.n 8001400 <HAL_GPIO_Init+0x1e4>
80013fe: 2300 movs r3, #0
8001400: 697a ldr r2, [r7, #20]
8001402: 2103 movs r1, #3
8001404: 400a ands r2, r1
8001406: 0092 lsls r2, r2, #2
8001408: 4093 lsls r3, r2
800140a: 693a ldr r2, [r7, #16]
800140c: 4313 orrs r3, r2
800140e: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001410: 4935 ldr r1, [pc, #212] ; (80014e8 <HAL_GPIO_Init+0x2cc>)
8001412: 697b ldr r3, [r7, #20]
8001414: 089b lsrs r3, r3, #2
8001416: 3302 adds r3, #2
8001418: 009b lsls r3, r3, #2
800141a: 693a ldr r2, [r7, #16]
800141c: 505a str r2, [r3, r1]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800141e: 4b36 ldr r3, [pc, #216] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
8001420: 681b ldr r3, [r3, #0]
8001422: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001424: 68fb ldr r3, [r7, #12]
8001426: 43da mvns r2, r3
8001428: 693b ldr r3, [r7, #16]
800142a: 4013 ands r3, r2
800142c: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
800142e: 683b ldr r3, [r7, #0]
8001430: 685a ldr r2, [r3, #4]
8001432: 2380 movs r3, #128 ; 0x80
8001434: 025b lsls r3, r3, #9
8001436: 4013 ands r3, r2
8001438: d003 beq.n 8001442 <HAL_GPIO_Init+0x226>
{
temp |= iocurrent;
800143a: 693a ldr r2, [r7, #16]
800143c: 68fb ldr r3, [r7, #12]
800143e: 4313 orrs r3, r2
8001440: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8001442: 4b2d ldr r3, [pc, #180] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
8001444: 693a ldr r2, [r7, #16]
8001446: 601a str r2, [r3, #0]
temp = EXTI->EMR;
8001448: 4b2b ldr r3, [pc, #172] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
800144a: 685b ldr r3, [r3, #4]
800144c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800144e: 68fb ldr r3, [r7, #12]
8001450: 43da mvns r2, r3
8001452: 693b ldr r3, [r7, #16]
8001454: 4013 ands r3, r2
8001456: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001458: 683b ldr r3, [r7, #0]
800145a: 685a ldr r2, [r3, #4]
800145c: 2380 movs r3, #128 ; 0x80
800145e: 029b lsls r3, r3, #10
8001460: 4013 ands r3, r2
8001462: d003 beq.n 800146c <HAL_GPIO_Init+0x250>
{
temp |= iocurrent;
8001464: 693a ldr r2, [r7, #16]
8001466: 68fb ldr r3, [r7, #12]
8001468: 4313 orrs r3, r2
800146a: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
800146c: 4b22 ldr r3, [pc, #136] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
800146e: 693a ldr r2, [r7, #16]
8001470: 605a str r2, [r3, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001472: 4b21 ldr r3, [pc, #132] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
8001474: 689b ldr r3, [r3, #8]
8001476: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001478: 68fb ldr r3, [r7, #12]
800147a: 43da mvns r2, r3
800147c: 693b ldr r3, [r7, #16]
800147e: 4013 ands r3, r2
8001480: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001482: 683b ldr r3, [r7, #0]
8001484: 685a ldr r2, [r3, #4]
8001486: 2380 movs r3, #128 ; 0x80
8001488: 035b lsls r3, r3, #13
800148a: 4013 ands r3, r2
800148c: d003 beq.n 8001496 <HAL_GPIO_Init+0x27a>
{
temp |= iocurrent;
800148e: 693a ldr r2, [r7, #16]
8001490: 68fb ldr r3, [r7, #12]
8001492: 4313 orrs r3, r2
8001494: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001496: 4b18 ldr r3, [pc, #96] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
8001498: 693a ldr r2, [r7, #16]
800149a: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
800149c: 4b16 ldr r3, [pc, #88] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
800149e: 68db ldr r3, [r3, #12]
80014a0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80014a2: 68fb ldr r3, [r7, #12]
80014a4: 43da mvns r2, r3
80014a6: 693b ldr r3, [r7, #16]
80014a8: 4013 ands r3, r2
80014aa: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
80014ac: 683b ldr r3, [r7, #0]
80014ae: 685a ldr r2, [r3, #4]
80014b0: 2380 movs r3, #128 ; 0x80
80014b2: 039b lsls r3, r3, #14
80014b4: 4013 ands r3, r2
80014b6: d003 beq.n 80014c0 <HAL_GPIO_Init+0x2a4>
{
temp |= iocurrent;
80014b8: 693a ldr r2, [r7, #16]
80014ba: 68fb ldr r3, [r7, #12]
80014bc: 4313 orrs r3, r2
80014be: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
80014c0: 4b0d ldr r3, [pc, #52] ; (80014f8 <HAL_GPIO_Init+0x2dc>)
80014c2: 693a ldr r2, [r7, #16]
80014c4: 60da str r2, [r3, #12]
}
}
position++;
80014c6: 697b ldr r3, [r7, #20]
80014c8: 3301 adds r3, #1
80014ca: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80014cc: 683b ldr r3, [r7, #0]
80014ce: 681a ldr r2, [r3, #0]
80014d0: 697b ldr r3, [r7, #20]
80014d2: 40da lsrs r2, r3
80014d4: 1e13 subs r3, r2, #0
80014d6: d000 beq.n 80014da <HAL_GPIO_Init+0x2be>
80014d8: e6a8 b.n 800122c <HAL_GPIO_Init+0x10>
}
}
80014da: 46c0 nop ; (mov r8, r8)
80014dc: 46c0 nop ; (mov r8, r8)
80014de: 46bd mov sp, r7
80014e0: b006 add sp, #24
80014e2: bd80 pop {r7, pc}
80014e4: 40021000 .word 0x40021000
80014e8: 40010000 .word 0x40010000
80014ec: 48000400 .word 0x48000400
80014f0: 48000800 .word 0x48000800
80014f4: 48000c00 .word 0x48000c00
80014f8: 40010400 .word 0x40010400
080014fc <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
80014fc: b580 push {r7, lr}
80014fe: b084 sub sp, #16
8001500: af00 add r7, sp, #0
8001502: 6078 str r0, [r7, #4]
8001504: 000a movs r2, r1
8001506: 1cbb adds r3, r7, #2
8001508: 801a strh r2, [r3, #0]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
800150a: 687b ldr r3, [r7, #4]
800150c: 691b ldr r3, [r3, #16]
800150e: 1cba adds r2, r7, #2
8001510: 8812 ldrh r2, [r2, #0]
8001512: 4013 ands r3, r2
8001514: d004 beq.n 8001520 <HAL_GPIO_ReadPin+0x24>
{
bitstatus = GPIO_PIN_SET;
8001516: 230f movs r3, #15
8001518: 18fb adds r3, r7, r3
800151a: 2201 movs r2, #1
800151c: 701a strb r2, [r3, #0]
800151e: e003 b.n 8001528 <HAL_GPIO_ReadPin+0x2c>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001520: 230f movs r3, #15
8001522: 18fb adds r3, r7, r3
8001524: 2200 movs r2, #0
8001526: 701a strb r2, [r3, #0]
}
return bitstatus;
8001528: 230f movs r3, #15
800152a: 18fb adds r3, r7, r3
800152c: 781b ldrb r3, [r3, #0]
}
800152e: 0018 movs r0, r3
8001530: 46bd mov sp, r7
8001532: b004 add sp, #16
8001534: bd80 pop {r7, pc}
08001536 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001536: b580 push {r7, lr}
8001538: b082 sub sp, #8
800153a: af00 add r7, sp, #0
800153c: 6078 str r0, [r7, #4]
800153e: 0008 movs r0, r1
8001540: 0011 movs r1, r2
8001542: 1cbb adds r3, r7, #2
8001544: 1c02 adds r2, r0, #0
8001546: 801a strh r2, [r3, #0]
8001548: 1c7b adds r3, r7, #1
800154a: 1c0a adds r2, r1, #0
800154c: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
800154e: 1c7b adds r3, r7, #1
8001550: 781b ldrb r3, [r3, #0]
8001552: 2b00 cmp r3, #0
8001554: d004 beq.n 8001560 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001556: 1cbb adds r3, r7, #2
8001558: 881a ldrh r2, [r3, #0]
800155a: 687b ldr r3, [r7, #4]
800155c: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
800155e: e003 b.n 8001568 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001560: 1cbb adds r3, r7, #2
8001562: 881a ldrh r2, [r3, #0]
8001564: 687b ldr r3, [r7, #4]
8001566: 629a str r2, [r3, #40] ; 0x28
}
8001568: 46c0 nop ; (mov r8, r8)
800156a: 46bd mov sp, r7
800156c: b002 add sp, #8
800156e: bd80 pop {r7, pc}
08001570 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001570: b580 push {r7, lr}
8001572: b088 sub sp, #32
8001574: af00 add r7, sp, #0
8001576: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001578: 687b ldr r3, [r7, #4]
800157a: 2b00 cmp r3, #0
800157c: d101 bne.n 8001582 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800157e: 2301 movs r3, #1
8001580: e301 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001582: 687b ldr r3, [r7, #4]
8001584: 681b ldr r3, [r3, #0]
8001586: 2201 movs r2, #1
8001588: 4013 ands r3, r2
800158a: d100 bne.n 800158e <HAL_RCC_OscConfig+0x1e>
800158c: e08d b.n 80016aa <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
800158e: 4bc3 ldr r3, [pc, #780] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001590: 685b ldr r3, [r3, #4]
8001592: 220c movs r2, #12
8001594: 4013 ands r3, r2
8001596: 2b04 cmp r3, #4
8001598: d00e beq.n 80015b8 <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
800159a: 4bc0 ldr r3, [pc, #768] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800159c: 685b ldr r3, [r3, #4]
800159e: 220c movs r2, #12
80015a0: 4013 ands r3, r2
80015a2: 2b08 cmp r3, #8
80015a4: d116 bne.n 80015d4 <HAL_RCC_OscConfig+0x64>
80015a6: 4bbd ldr r3, [pc, #756] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80015a8: 685a ldr r2, [r3, #4]
80015aa: 2380 movs r3, #128 ; 0x80
80015ac: 025b lsls r3, r3, #9
80015ae: 401a ands r2, r3
80015b0: 2380 movs r3, #128 ; 0x80
80015b2: 025b lsls r3, r3, #9
80015b4: 429a cmp r2, r3
80015b6: d10d bne.n 80015d4 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80015b8: 4bb8 ldr r3, [pc, #736] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80015ba: 681a ldr r2, [r3, #0]
80015bc: 2380 movs r3, #128 ; 0x80
80015be: 029b lsls r3, r3, #10
80015c0: 4013 ands r3, r2
80015c2: d100 bne.n 80015c6 <HAL_RCC_OscConfig+0x56>
80015c4: e070 b.n 80016a8 <HAL_RCC_OscConfig+0x138>
80015c6: 687b ldr r3, [r7, #4]
80015c8: 685b ldr r3, [r3, #4]
80015ca: 2b00 cmp r3, #0
80015cc: d000 beq.n 80015d0 <HAL_RCC_OscConfig+0x60>
80015ce: e06b b.n 80016a8 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
80015d0: 2301 movs r3, #1
80015d2: e2d8 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80015d4: 687b ldr r3, [r7, #4]
80015d6: 685b ldr r3, [r3, #4]
80015d8: 2b01 cmp r3, #1
80015da: d107 bne.n 80015ec <HAL_RCC_OscConfig+0x7c>
80015dc: 4baf ldr r3, [pc, #700] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80015de: 681a ldr r2, [r3, #0]
80015e0: 4bae ldr r3, [pc, #696] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80015e2: 2180 movs r1, #128 ; 0x80
80015e4: 0249 lsls r1, r1, #9
80015e6: 430a orrs r2, r1
80015e8: 601a str r2, [r3, #0]
80015ea: e02f b.n 800164c <HAL_RCC_OscConfig+0xdc>
80015ec: 687b ldr r3, [r7, #4]
80015ee: 685b ldr r3, [r3, #4]
80015f0: 2b00 cmp r3, #0
80015f2: d10c bne.n 800160e <HAL_RCC_OscConfig+0x9e>
80015f4: 4ba9 ldr r3, [pc, #676] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80015f6: 681a ldr r2, [r3, #0]
80015f8: 4ba8 ldr r3, [pc, #672] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80015fa: 49a9 ldr r1, [pc, #676] ; (80018a0 <HAL_RCC_OscConfig+0x330>)
80015fc: 400a ands r2, r1
80015fe: 601a str r2, [r3, #0]
8001600: 4ba6 ldr r3, [pc, #664] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001602: 681a ldr r2, [r3, #0]
8001604: 4ba5 ldr r3, [pc, #660] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001606: 49a7 ldr r1, [pc, #668] ; (80018a4 <HAL_RCC_OscConfig+0x334>)
8001608: 400a ands r2, r1
800160a: 601a str r2, [r3, #0]
800160c: e01e b.n 800164c <HAL_RCC_OscConfig+0xdc>
800160e: 687b ldr r3, [r7, #4]
8001610: 685b ldr r3, [r3, #4]
8001612: 2b05 cmp r3, #5
8001614: d10e bne.n 8001634 <HAL_RCC_OscConfig+0xc4>
8001616: 4ba1 ldr r3, [pc, #644] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001618: 681a ldr r2, [r3, #0]
800161a: 4ba0 ldr r3, [pc, #640] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800161c: 2180 movs r1, #128 ; 0x80
800161e: 02c9 lsls r1, r1, #11
8001620: 430a orrs r2, r1
8001622: 601a str r2, [r3, #0]
8001624: 4b9d ldr r3, [pc, #628] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001626: 681a ldr r2, [r3, #0]
8001628: 4b9c ldr r3, [pc, #624] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800162a: 2180 movs r1, #128 ; 0x80
800162c: 0249 lsls r1, r1, #9
800162e: 430a orrs r2, r1
8001630: 601a str r2, [r3, #0]
8001632: e00b b.n 800164c <HAL_RCC_OscConfig+0xdc>
8001634: 4b99 ldr r3, [pc, #612] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001636: 681a ldr r2, [r3, #0]
8001638: 4b98 ldr r3, [pc, #608] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800163a: 4999 ldr r1, [pc, #612] ; (80018a0 <HAL_RCC_OscConfig+0x330>)
800163c: 400a ands r2, r1
800163e: 601a str r2, [r3, #0]
8001640: 4b96 ldr r3, [pc, #600] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001642: 681a ldr r2, [r3, #0]
8001644: 4b95 ldr r3, [pc, #596] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001646: 4997 ldr r1, [pc, #604] ; (80018a4 <HAL_RCC_OscConfig+0x334>)
8001648: 400a ands r2, r1
800164a: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800164c: 687b ldr r3, [r7, #4]
800164e: 685b ldr r3, [r3, #4]
8001650: 2b00 cmp r3, #0
8001652: d014 beq.n 800167e <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001654: f7ff f90c bl 8000870 <HAL_GetTick>
8001658: 0003 movs r3, r0
800165a: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800165c: e008 b.n 8001670 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800165e: f7ff f907 bl 8000870 <HAL_GetTick>
8001662: 0002 movs r2, r0
8001664: 69bb ldr r3, [r7, #24]
8001666: 1ad3 subs r3, r2, r3
8001668: 2b64 cmp r3, #100 ; 0x64
800166a: d901 bls.n 8001670 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
800166c: 2303 movs r3, #3
800166e: e28a b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001670: 4b8a ldr r3, [pc, #552] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001672: 681a ldr r2, [r3, #0]
8001674: 2380 movs r3, #128 ; 0x80
8001676: 029b lsls r3, r3, #10
8001678: 4013 ands r3, r2
800167a: d0f0 beq.n 800165e <HAL_RCC_OscConfig+0xee>
800167c: e015 b.n 80016aa <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800167e: f7ff f8f7 bl 8000870 <HAL_GetTick>
8001682: 0003 movs r3, r0
8001684: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001686: e008 b.n 800169a <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001688: f7ff f8f2 bl 8000870 <HAL_GetTick>
800168c: 0002 movs r2, r0
800168e: 69bb ldr r3, [r7, #24]
8001690: 1ad3 subs r3, r2, r3
8001692: 2b64 cmp r3, #100 ; 0x64
8001694: d901 bls.n 800169a <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
8001696: 2303 movs r3, #3
8001698: e275 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800169a: 4b80 ldr r3, [pc, #512] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800169c: 681a ldr r2, [r3, #0]
800169e: 2380 movs r3, #128 ; 0x80
80016a0: 029b lsls r3, r3, #10
80016a2: 4013 ands r3, r2
80016a4: d1f0 bne.n 8001688 <HAL_RCC_OscConfig+0x118>
80016a6: e000 b.n 80016aa <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80016a8: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80016aa: 687b ldr r3, [r7, #4]
80016ac: 681b ldr r3, [r3, #0]
80016ae: 2202 movs r2, #2
80016b0: 4013 ands r3, r2
80016b2: d100 bne.n 80016b6 <HAL_RCC_OscConfig+0x146>
80016b4: e069 b.n 800178a <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80016b6: 4b79 ldr r3, [pc, #484] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80016b8: 685b ldr r3, [r3, #4]
80016ba: 220c movs r2, #12
80016bc: 4013 ands r3, r2
80016be: d00b beq.n 80016d8 <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
80016c0: 4b76 ldr r3, [pc, #472] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80016c2: 685b ldr r3, [r3, #4]
80016c4: 220c movs r2, #12
80016c6: 4013 ands r3, r2
80016c8: 2b08 cmp r3, #8
80016ca: d11c bne.n 8001706 <HAL_RCC_OscConfig+0x196>
80016cc: 4b73 ldr r3, [pc, #460] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80016ce: 685a ldr r2, [r3, #4]
80016d0: 2380 movs r3, #128 ; 0x80
80016d2: 025b lsls r3, r3, #9
80016d4: 4013 ands r3, r2
80016d6: d116 bne.n 8001706 <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80016d8: 4b70 ldr r3, [pc, #448] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80016da: 681b ldr r3, [r3, #0]
80016dc: 2202 movs r2, #2
80016de: 4013 ands r3, r2
80016e0: d005 beq.n 80016ee <HAL_RCC_OscConfig+0x17e>
80016e2: 687b ldr r3, [r7, #4]
80016e4: 68db ldr r3, [r3, #12]
80016e6: 2b01 cmp r3, #1
80016e8: d001 beq.n 80016ee <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
80016ea: 2301 movs r3, #1
80016ec: e24b b.n 8001b86 <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80016ee: 4b6b ldr r3, [pc, #428] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80016f0: 681b ldr r3, [r3, #0]
80016f2: 22f8 movs r2, #248 ; 0xf8
80016f4: 4393 bics r3, r2
80016f6: 0019 movs r1, r3
80016f8: 687b ldr r3, [r7, #4]
80016fa: 691b ldr r3, [r3, #16]
80016fc: 00da lsls r2, r3, #3
80016fe: 4b67 ldr r3, [pc, #412] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001700: 430a orrs r2, r1
8001702: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001704: e041 b.n 800178a <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8001706: 687b ldr r3, [r7, #4]
8001708: 68db ldr r3, [r3, #12]
800170a: 2b00 cmp r3, #0
800170c: d024 beq.n 8001758 <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800170e: 4b63 ldr r3, [pc, #396] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001710: 681a ldr r2, [r3, #0]
8001712: 4b62 ldr r3, [pc, #392] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001714: 2101 movs r1, #1
8001716: 430a orrs r2, r1
8001718: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800171a: f7ff f8a9 bl 8000870 <HAL_GetTick>
800171e: 0003 movs r3, r0
8001720: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001722: e008 b.n 8001736 <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001724: f7ff f8a4 bl 8000870 <HAL_GetTick>
8001728: 0002 movs r2, r0
800172a: 69bb ldr r3, [r7, #24]
800172c: 1ad3 subs r3, r2, r3
800172e: 2b02 cmp r3, #2
8001730: d901 bls.n 8001736 <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
8001732: 2303 movs r3, #3
8001734: e227 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001736: 4b59 ldr r3, [pc, #356] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001738: 681b ldr r3, [r3, #0]
800173a: 2202 movs r2, #2
800173c: 4013 ands r3, r2
800173e: d0f1 beq.n 8001724 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001740: 4b56 ldr r3, [pc, #344] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001742: 681b ldr r3, [r3, #0]
8001744: 22f8 movs r2, #248 ; 0xf8
8001746: 4393 bics r3, r2
8001748: 0019 movs r1, r3
800174a: 687b ldr r3, [r7, #4]
800174c: 691b ldr r3, [r3, #16]
800174e: 00da lsls r2, r3, #3
8001750: 4b52 ldr r3, [pc, #328] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001752: 430a orrs r2, r1
8001754: 601a str r2, [r3, #0]
8001756: e018 b.n 800178a <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001758: 4b50 ldr r3, [pc, #320] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800175a: 681a ldr r2, [r3, #0]
800175c: 4b4f ldr r3, [pc, #316] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800175e: 2101 movs r1, #1
8001760: 438a bics r2, r1
8001762: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001764: f7ff f884 bl 8000870 <HAL_GetTick>
8001768: 0003 movs r3, r0
800176a: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800176c: e008 b.n 8001780 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800176e: f7ff f87f bl 8000870 <HAL_GetTick>
8001772: 0002 movs r2, r0
8001774: 69bb ldr r3, [r7, #24]
8001776: 1ad3 subs r3, r2, r3
8001778: 2b02 cmp r3, #2
800177a: d901 bls.n 8001780 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
800177c: 2303 movs r3, #3
800177e: e202 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001780: 4b46 ldr r3, [pc, #280] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001782: 681b ldr r3, [r3, #0]
8001784: 2202 movs r2, #2
8001786: 4013 ands r3, r2
8001788: d1f1 bne.n 800176e <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800178a: 687b ldr r3, [r7, #4]
800178c: 681b ldr r3, [r3, #0]
800178e: 2208 movs r2, #8
8001790: 4013 ands r3, r2
8001792: d036 beq.n 8001802 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001794: 687b ldr r3, [r7, #4]
8001796: 69db ldr r3, [r3, #28]
8001798: 2b00 cmp r3, #0
800179a: d019 beq.n 80017d0 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800179c: 4b3f ldr r3, [pc, #252] ; (800189c <HAL_RCC_OscConfig+0x32c>)
800179e: 6a5a ldr r2, [r3, #36] ; 0x24
80017a0: 4b3e ldr r3, [pc, #248] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80017a2: 2101 movs r1, #1
80017a4: 430a orrs r2, r1
80017a6: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
80017a8: f7ff f862 bl 8000870 <HAL_GetTick>
80017ac: 0003 movs r3, r0
80017ae: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80017b0: e008 b.n 80017c4 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80017b2: f7ff f85d bl 8000870 <HAL_GetTick>
80017b6: 0002 movs r2, r0
80017b8: 69bb ldr r3, [r7, #24]
80017ba: 1ad3 subs r3, r2, r3
80017bc: 2b02 cmp r3, #2
80017be: d901 bls.n 80017c4 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
80017c0: 2303 movs r3, #3
80017c2: e1e0 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80017c4: 4b35 ldr r3, [pc, #212] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80017c6: 6a5b ldr r3, [r3, #36] ; 0x24
80017c8: 2202 movs r2, #2
80017ca: 4013 ands r3, r2
80017cc: d0f1 beq.n 80017b2 <HAL_RCC_OscConfig+0x242>
80017ce: e018 b.n 8001802 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80017d0: 4b32 ldr r3, [pc, #200] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80017d2: 6a5a ldr r2, [r3, #36] ; 0x24
80017d4: 4b31 ldr r3, [pc, #196] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80017d6: 2101 movs r1, #1
80017d8: 438a bics r2, r1
80017da: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
80017dc: f7ff f848 bl 8000870 <HAL_GetTick>
80017e0: 0003 movs r3, r0
80017e2: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80017e4: e008 b.n 80017f8 <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80017e6: f7ff f843 bl 8000870 <HAL_GetTick>
80017ea: 0002 movs r2, r0
80017ec: 69bb ldr r3, [r7, #24]
80017ee: 1ad3 subs r3, r2, r3
80017f0: 2b02 cmp r3, #2
80017f2: d901 bls.n 80017f8 <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
80017f4: 2303 movs r3, #3
80017f6: e1c6 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80017f8: 4b28 ldr r3, [pc, #160] ; (800189c <HAL_RCC_OscConfig+0x32c>)
80017fa: 6a5b ldr r3, [r3, #36] ; 0x24
80017fc: 2202 movs r2, #2
80017fe: 4013 ands r3, r2
8001800: d1f1 bne.n 80017e6 <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001802: 687b ldr r3, [r7, #4]
8001804: 681b ldr r3, [r3, #0]
8001806: 2204 movs r2, #4
8001808: 4013 ands r3, r2
800180a: d100 bne.n 800180e <HAL_RCC_OscConfig+0x29e>
800180c: e0b4 b.n 8001978 <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
800180e: 201f movs r0, #31
8001810: 183b adds r3, r7, r0
8001812: 2200 movs r2, #0
8001814: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001816: 4b21 ldr r3, [pc, #132] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001818: 69da ldr r2, [r3, #28]
800181a: 2380 movs r3, #128 ; 0x80
800181c: 055b lsls r3, r3, #21
800181e: 4013 ands r3, r2
8001820: d110 bne.n 8001844 <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001822: 4b1e ldr r3, [pc, #120] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001824: 69da ldr r2, [r3, #28]
8001826: 4b1d ldr r3, [pc, #116] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001828: 2180 movs r1, #128 ; 0x80
800182a: 0549 lsls r1, r1, #21
800182c: 430a orrs r2, r1
800182e: 61da str r2, [r3, #28]
8001830: 4b1a ldr r3, [pc, #104] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001832: 69da ldr r2, [r3, #28]
8001834: 2380 movs r3, #128 ; 0x80
8001836: 055b lsls r3, r3, #21
8001838: 4013 ands r3, r2
800183a: 60fb str r3, [r7, #12]
800183c: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
800183e: 183b adds r3, r7, r0
8001840: 2201 movs r2, #1
8001842: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001844: 4b18 ldr r3, [pc, #96] ; (80018a8 <HAL_RCC_OscConfig+0x338>)
8001846: 681a ldr r2, [r3, #0]
8001848: 2380 movs r3, #128 ; 0x80
800184a: 005b lsls r3, r3, #1
800184c: 4013 ands r3, r2
800184e: d11a bne.n 8001886 <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001850: 4b15 ldr r3, [pc, #84] ; (80018a8 <HAL_RCC_OscConfig+0x338>)
8001852: 681a ldr r2, [r3, #0]
8001854: 4b14 ldr r3, [pc, #80] ; (80018a8 <HAL_RCC_OscConfig+0x338>)
8001856: 2180 movs r1, #128 ; 0x80
8001858: 0049 lsls r1, r1, #1
800185a: 430a orrs r2, r1
800185c: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800185e: f7ff f807 bl 8000870 <HAL_GetTick>
8001862: 0003 movs r3, r0
8001864: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001866: e008 b.n 800187a <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001868: f7ff f802 bl 8000870 <HAL_GetTick>
800186c: 0002 movs r2, r0
800186e: 69bb ldr r3, [r7, #24]
8001870: 1ad3 subs r3, r2, r3
8001872: 2b64 cmp r3, #100 ; 0x64
8001874: d901 bls.n 800187a <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8001876: 2303 movs r3, #3
8001878: e185 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800187a: 4b0b ldr r3, [pc, #44] ; (80018a8 <HAL_RCC_OscConfig+0x338>)
800187c: 681a ldr r2, [r3, #0]
800187e: 2380 movs r3, #128 ; 0x80
8001880: 005b lsls r3, r3, #1
8001882: 4013 ands r3, r2
8001884: d0f0 beq.n 8001868 <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001886: 687b ldr r3, [r7, #4]
8001888: 689b ldr r3, [r3, #8]
800188a: 2b01 cmp r3, #1
800188c: d10e bne.n 80018ac <HAL_RCC_OscConfig+0x33c>
800188e: 4b03 ldr r3, [pc, #12] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001890: 6a1a ldr r2, [r3, #32]
8001892: 4b02 ldr r3, [pc, #8] ; (800189c <HAL_RCC_OscConfig+0x32c>)
8001894: 2101 movs r1, #1
8001896: 430a orrs r2, r1
8001898: 621a str r2, [r3, #32]
800189a: e035 b.n 8001908 <HAL_RCC_OscConfig+0x398>
800189c: 40021000 .word 0x40021000
80018a0: fffeffff .word 0xfffeffff
80018a4: fffbffff .word 0xfffbffff
80018a8: 40007000 .word 0x40007000
80018ac: 687b ldr r3, [r7, #4]
80018ae: 689b ldr r3, [r3, #8]
80018b0: 2b00 cmp r3, #0
80018b2: d10c bne.n 80018ce <HAL_RCC_OscConfig+0x35e>
80018b4: 4bb6 ldr r3, [pc, #728] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018b6: 6a1a ldr r2, [r3, #32]
80018b8: 4bb5 ldr r3, [pc, #724] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018ba: 2101 movs r1, #1
80018bc: 438a bics r2, r1
80018be: 621a str r2, [r3, #32]
80018c0: 4bb3 ldr r3, [pc, #716] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018c2: 6a1a ldr r2, [r3, #32]
80018c4: 4bb2 ldr r3, [pc, #712] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018c6: 2104 movs r1, #4
80018c8: 438a bics r2, r1
80018ca: 621a str r2, [r3, #32]
80018cc: e01c b.n 8001908 <HAL_RCC_OscConfig+0x398>
80018ce: 687b ldr r3, [r7, #4]
80018d0: 689b ldr r3, [r3, #8]
80018d2: 2b05 cmp r3, #5
80018d4: d10c bne.n 80018f0 <HAL_RCC_OscConfig+0x380>
80018d6: 4bae ldr r3, [pc, #696] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018d8: 6a1a ldr r2, [r3, #32]
80018da: 4bad ldr r3, [pc, #692] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018dc: 2104 movs r1, #4
80018de: 430a orrs r2, r1
80018e0: 621a str r2, [r3, #32]
80018e2: 4bab ldr r3, [pc, #684] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018e4: 6a1a ldr r2, [r3, #32]
80018e6: 4baa ldr r3, [pc, #680] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018e8: 2101 movs r1, #1
80018ea: 430a orrs r2, r1
80018ec: 621a str r2, [r3, #32]
80018ee: e00b b.n 8001908 <HAL_RCC_OscConfig+0x398>
80018f0: 4ba7 ldr r3, [pc, #668] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018f2: 6a1a ldr r2, [r3, #32]
80018f4: 4ba6 ldr r3, [pc, #664] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018f6: 2101 movs r1, #1
80018f8: 438a bics r2, r1
80018fa: 621a str r2, [r3, #32]
80018fc: 4ba4 ldr r3, [pc, #656] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80018fe: 6a1a ldr r2, [r3, #32]
8001900: 4ba3 ldr r3, [pc, #652] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001902: 2104 movs r1, #4
8001904: 438a bics r2, r1
8001906: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001908: 687b ldr r3, [r7, #4]
800190a: 689b ldr r3, [r3, #8]
800190c: 2b00 cmp r3, #0
800190e: d014 beq.n 800193a <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001910: f7fe ffae bl 8000870 <HAL_GetTick>
8001914: 0003 movs r3, r0
8001916: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001918: e009 b.n 800192e <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
800191a: f7fe ffa9 bl 8000870 <HAL_GetTick>
800191e: 0002 movs r2, r0
8001920: 69bb ldr r3, [r7, #24]
8001922: 1ad3 subs r3, r2, r3
8001924: 4a9b ldr r2, [pc, #620] ; (8001b94 <HAL_RCC_OscConfig+0x624>)
8001926: 4293 cmp r3, r2
8001928: d901 bls.n 800192e <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
800192a: 2303 movs r3, #3
800192c: e12b b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800192e: 4b98 ldr r3, [pc, #608] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001930: 6a1b ldr r3, [r3, #32]
8001932: 2202 movs r2, #2
8001934: 4013 ands r3, r2
8001936: d0f0 beq.n 800191a <HAL_RCC_OscConfig+0x3aa>
8001938: e013 b.n 8001962 <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800193a: f7fe ff99 bl 8000870 <HAL_GetTick>
800193e: 0003 movs r3, r0
8001940: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001942: e009 b.n 8001958 <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001944: f7fe ff94 bl 8000870 <HAL_GetTick>
8001948: 0002 movs r2, r0
800194a: 69bb ldr r3, [r7, #24]
800194c: 1ad3 subs r3, r2, r3
800194e: 4a91 ldr r2, [pc, #580] ; (8001b94 <HAL_RCC_OscConfig+0x624>)
8001950: 4293 cmp r3, r2
8001952: d901 bls.n 8001958 <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
8001954: 2303 movs r3, #3
8001956: e116 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001958: 4b8d ldr r3, [pc, #564] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
800195a: 6a1b ldr r3, [r3, #32]
800195c: 2202 movs r2, #2
800195e: 4013 ands r3, r2
8001960: d1f0 bne.n 8001944 <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8001962: 231f movs r3, #31
8001964: 18fb adds r3, r7, r3
8001966: 781b ldrb r3, [r3, #0]
8001968: 2b01 cmp r3, #1
800196a: d105 bne.n 8001978 <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
800196c: 4b88 ldr r3, [pc, #544] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
800196e: 69da ldr r2, [r3, #28]
8001970: 4b87 ldr r3, [pc, #540] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001972: 4989 ldr r1, [pc, #548] ; (8001b98 <HAL_RCC_OscConfig+0x628>)
8001974: 400a ands r2, r1
8001976: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8001978: 687b ldr r3, [r7, #4]
800197a: 681b ldr r3, [r3, #0]
800197c: 2210 movs r2, #16
800197e: 4013 ands r3, r2
8001980: d063 beq.n 8001a4a <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8001982: 687b ldr r3, [r7, #4]
8001984: 695b ldr r3, [r3, #20]
8001986: 2b01 cmp r3, #1
8001988: d12a bne.n 80019e0 <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
800198a: 4b81 ldr r3, [pc, #516] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
800198c: 6b5a ldr r2, [r3, #52] ; 0x34
800198e: 4b80 ldr r3, [pc, #512] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001990: 2104 movs r1, #4
8001992: 430a orrs r2, r1
8001994: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8001996: 4b7e ldr r3, [pc, #504] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001998: 6b5a ldr r2, [r3, #52] ; 0x34
800199a: 4b7d ldr r3, [pc, #500] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
800199c: 2101 movs r1, #1
800199e: 430a orrs r2, r1
80019a0: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
80019a2: f7fe ff65 bl 8000870 <HAL_GetTick>
80019a6: 0003 movs r3, r0
80019a8: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
80019aa: e008 b.n 80019be <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
80019ac: f7fe ff60 bl 8000870 <HAL_GetTick>
80019b0: 0002 movs r2, r0
80019b2: 69bb ldr r3, [r7, #24]
80019b4: 1ad3 subs r3, r2, r3
80019b6: 2b02 cmp r3, #2
80019b8: d901 bls.n 80019be <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
80019ba: 2303 movs r3, #3
80019bc: e0e3 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
80019be: 4b74 ldr r3, [pc, #464] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80019c0: 6b5b ldr r3, [r3, #52] ; 0x34
80019c2: 2202 movs r2, #2
80019c4: 4013 ands r3, r2
80019c6: d0f1 beq.n 80019ac <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
80019c8: 4b71 ldr r3, [pc, #452] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80019ca: 6b5b ldr r3, [r3, #52] ; 0x34
80019cc: 22f8 movs r2, #248 ; 0xf8
80019ce: 4393 bics r3, r2
80019d0: 0019 movs r1, r3
80019d2: 687b ldr r3, [r7, #4]
80019d4: 699b ldr r3, [r3, #24]
80019d6: 00da lsls r2, r3, #3
80019d8: 4b6d ldr r3, [pc, #436] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80019da: 430a orrs r2, r1
80019dc: 635a str r2, [r3, #52] ; 0x34
80019de: e034 b.n 8001a4a <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
80019e0: 687b ldr r3, [r7, #4]
80019e2: 695b ldr r3, [r3, #20]
80019e4: 3305 adds r3, #5
80019e6: d111 bne.n 8001a0c <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
80019e8: 4b69 ldr r3, [pc, #420] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80019ea: 6b5a ldr r2, [r3, #52] ; 0x34
80019ec: 4b68 ldr r3, [pc, #416] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80019ee: 2104 movs r1, #4
80019f0: 438a bics r2, r1
80019f2: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
80019f4: 4b66 ldr r3, [pc, #408] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
80019f6: 6b5b ldr r3, [r3, #52] ; 0x34
80019f8: 22f8 movs r2, #248 ; 0xf8
80019fa: 4393 bics r3, r2
80019fc: 0019 movs r1, r3
80019fe: 687b ldr r3, [r7, #4]
8001a00: 699b ldr r3, [r3, #24]
8001a02: 00da lsls r2, r3, #3
8001a04: 4b62 ldr r3, [pc, #392] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a06: 430a orrs r2, r1
8001a08: 635a str r2, [r3, #52] ; 0x34
8001a0a: e01e b.n 8001a4a <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001a0c: 4b60 ldr r3, [pc, #384] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a0e: 6b5a ldr r2, [r3, #52] ; 0x34
8001a10: 4b5f ldr r3, [pc, #380] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a12: 2104 movs r1, #4
8001a14: 430a orrs r2, r1
8001a16: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8001a18: 4b5d ldr r3, [pc, #372] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a1a: 6b5a ldr r2, [r3, #52] ; 0x34
8001a1c: 4b5c ldr r3, [pc, #368] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a1e: 2101 movs r1, #1
8001a20: 438a bics r2, r1
8001a22: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a24: f7fe ff24 bl 8000870 <HAL_GetTick>
8001a28: 0003 movs r3, r0
8001a2a: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001a2c: e008 b.n 8001a40 <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001a2e: f7fe ff1f bl 8000870 <HAL_GetTick>
8001a32: 0002 movs r2, r0
8001a34: 69bb ldr r3, [r7, #24]
8001a36: 1ad3 subs r3, r2, r3
8001a38: 2b02 cmp r3, #2
8001a3a: d901 bls.n 8001a40 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
8001a3c: 2303 movs r3, #3
8001a3e: e0a2 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001a40: 4b53 ldr r3, [pc, #332] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a42: 6b5b ldr r3, [r3, #52] ; 0x34
8001a44: 2202 movs r2, #2
8001a46: 4013 ands r3, r2
8001a48: d1f1 bne.n 8001a2e <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001a4a: 687b ldr r3, [r7, #4]
8001a4c: 6a1b ldr r3, [r3, #32]
8001a4e: 2b00 cmp r3, #0
8001a50: d100 bne.n 8001a54 <HAL_RCC_OscConfig+0x4e4>
8001a52: e097 b.n 8001b84 <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001a54: 4b4e ldr r3, [pc, #312] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a56: 685b ldr r3, [r3, #4]
8001a58: 220c movs r2, #12
8001a5a: 4013 ands r3, r2
8001a5c: 2b08 cmp r3, #8
8001a5e: d100 bne.n 8001a62 <HAL_RCC_OscConfig+0x4f2>
8001a60: e06b b.n 8001b3a <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001a62: 687b ldr r3, [r7, #4]
8001a64: 6a1b ldr r3, [r3, #32]
8001a66: 2b02 cmp r3, #2
8001a68: d14c bne.n 8001b04 <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001a6a: 4b49 ldr r3, [pc, #292] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a6c: 681a ldr r2, [r3, #0]
8001a6e: 4b48 ldr r3, [pc, #288] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a70: 494a ldr r1, [pc, #296] ; (8001b9c <HAL_RCC_OscConfig+0x62c>)
8001a72: 400a ands r2, r1
8001a74: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a76: f7fe fefb bl 8000870 <HAL_GetTick>
8001a7a: 0003 movs r3, r0
8001a7c: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001a7e: e008 b.n 8001a92 <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001a80: f7fe fef6 bl 8000870 <HAL_GetTick>
8001a84: 0002 movs r2, r0
8001a86: 69bb ldr r3, [r7, #24]
8001a88: 1ad3 subs r3, r2, r3
8001a8a: 2b02 cmp r3, #2
8001a8c: d901 bls.n 8001a92 <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
8001a8e: 2303 movs r3, #3
8001a90: e079 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001a92: 4b3f ldr r3, [pc, #252] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001a94: 681a ldr r2, [r3, #0]
8001a96: 2380 movs r3, #128 ; 0x80
8001a98: 049b lsls r3, r3, #18
8001a9a: 4013 ands r3, r2
8001a9c: d1f0 bne.n 8001a80 <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001a9e: 4b3c ldr r3, [pc, #240] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001aa0: 6adb ldr r3, [r3, #44] ; 0x2c
8001aa2: 220f movs r2, #15
8001aa4: 4393 bics r3, r2
8001aa6: 0019 movs r1, r3
8001aa8: 687b ldr r3, [r7, #4]
8001aaa: 6ada ldr r2, [r3, #44] ; 0x2c
8001aac: 4b38 ldr r3, [pc, #224] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001aae: 430a orrs r2, r1
8001ab0: 62da str r2, [r3, #44] ; 0x2c
8001ab2: 4b37 ldr r3, [pc, #220] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001ab4: 685b ldr r3, [r3, #4]
8001ab6: 4a3a ldr r2, [pc, #232] ; (8001ba0 <HAL_RCC_OscConfig+0x630>)
8001ab8: 4013 ands r3, r2
8001aba: 0019 movs r1, r3
8001abc: 687b ldr r3, [r7, #4]
8001abe: 6a9a ldr r2, [r3, #40] ; 0x28
8001ac0: 687b ldr r3, [r7, #4]
8001ac2: 6a5b ldr r3, [r3, #36] ; 0x24
8001ac4: 431a orrs r2, r3
8001ac6: 4b32 ldr r3, [pc, #200] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001ac8: 430a orrs r2, r1
8001aca: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001acc: 4b30 ldr r3, [pc, #192] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001ace: 681a ldr r2, [r3, #0]
8001ad0: 4b2f ldr r3, [pc, #188] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001ad2: 2180 movs r1, #128 ; 0x80
8001ad4: 0449 lsls r1, r1, #17
8001ad6: 430a orrs r2, r1
8001ad8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ada: f7fe fec9 bl 8000870 <HAL_GetTick>
8001ade: 0003 movs r3, r0
8001ae0: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001ae2: e008 b.n 8001af6 <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001ae4: f7fe fec4 bl 8000870 <HAL_GetTick>
8001ae8: 0002 movs r2, r0
8001aea: 69bb ldr r3, [r7, #24]
8001aec: 1ad3 subs r3, r2, r3
8001aee: 2b02 cmp r3, #2
8001af0: d901 bls.n 8001af6 <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001af2: 2303 movs r3, #3
8001af4: e047 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001af6: 4b26 ldr r3, [pc, #152] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001af8: 681a ldr r2, [r3, #0]
8001afa: 2380 movs r3, #128 ; 0x80
8001afc: 049b lsls r3, r3, #18
8001afe: 4013 ands r3, r2
8001b00: d0f0 beq.n 8001ae4 <HAL_RCC_OscConfig+0x574>
8001b02: e03f b.n 8001b84 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001b04: 4b22 ldr r3, [pc, #136] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001b06: 681a ldr r2, [r3, #0]
8001b08: 4b21 ldr r3, [pc, #132] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001b0a: 4924 ldr r1, [pc, #144] ; (8001b9c <HAL_RCC_OscConfig+0x62c>)
8001b0c: 400a ands r2, r1
8001b0e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b10: f7fe feae bl 8000870 <HAL_GetTick>
8001b14: 0003 movs r3, r0
8001b16: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001b18: e008 b.n 8001b2c <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001b1a: f7fe fea9 bl 8000870 <HAL_GetTick>
8001b1e: 0002 movs r2, r0
8001b20: 69bb ldr r3, [r7, #24]
8001b22: 1ad3 subs r3, r2, r3
8001b24: 2b02 cmp r3, #2
8001b26: d901 bls.n 8001b2c <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
8001b28: 2303 movs r3, #3
8001b2a: e02c b.n 8001b86 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001b2c: 4b18 ldr r3, [pc, #96] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001b2e: 681a ldr r2, [r3, #0]
8001b30: 2380 movs r3, #128 ; 0x80
8001b32: 049b lsls r3, r3, #18
8001b34: 4013 ands r3, r2
8001b36: d1f0 bne.n 8001b1a <HAL_RCC_OscConfig+0x5aa>
8001b38: e024 b.n 8001b84 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001b3a: 687b ldr r3, [r7, #4]
8001b3c: 6a1b ldr r3, [r3, #32]
8001b3e: 2b01 cmp r3, #1
8001b40: d101 bne.n 8001b46 <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
8001b42: 2301 movs r3, #1
8001b44: e01f b.n 8001b86 <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8001b46: 4b12 ldr r3, [pc, #72] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001b48: 685b ldr r3, [r3, #4]
8001b4a: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8001b4c: 4b10 ldr r3, [pc, #64] ; (8001b90 <HAL_RCC_OscConfig+0x620>)
8001b4e: 6adb ldr r3, [r3, #44] ; 0x2c
8001b50: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001b52: 697a ldr r2, [r7, #20]
8001b54: 2380 movs r3, #128 ; 0x80
8001b56: 025b lsls r3, r3, #9
8001b58: 401a ands r2, r3
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 6a5b ldr r3, [r3, #36] ; 0x24
8001b5e: 429a cmp r2, r3
8001b60: d10e bne.n 8001b80 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001b62: 693b ldr r3, [r7, #16]
8001b64: 220f movs r2, #15
8001b66: 401a ands r2, r3
8001b68: 687b ldr r3, [r7, #4]
8001b6a: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001b6c: 429a cmp r2, r3
8001b6e: d107 bne.n 8001b80 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8001b70: 697a ldr r2, [r7, #20]
8001b72: 23f0 movs r3, #240 ; 0xf0
8001b74: 039b lsls r3, r3, #14
8001b76: 401a ands r2, r3
8001b78: 687b ldr r3, [r7, #4]
8001b7a: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001b7c: 429a cmp r2, r3
8001b7e: d001 beq.n 8001b84 <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
8001b80: 2301 movs r3, #1
8001b82: e000 b.n 8001b86 <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
8001b84: 2300 movs r3, #0
}
8001b86: 0018 movs r0, r3
8001b88: 46bd mov sp, r7
8001b8a: b008 add sp, #32
8001b8c: bd80 pop {r7, pc}
8001b8e: 46c0 nop ; (mov r8, r8)
8001b90: 40021000 .word 0x40021000
8001b94: 00001388 .word 0x00001388
8001b98: efffffff .word 0xefffffff
8001b9c: feffffff .word 0xfeffffff
8001ba0: ffc2ffff .word 0xffc2ffff
08001ba4 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001ba4: b580 push {r7, lr}
8001ba6: b084 sub sp, #16
8001ba8: af00 add r7, sp, #0
8001baa: 6078 str r0, [r7, #4]
8001bac: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001bae: 687b ldr r3, [r7, #4]
8001bb0: 2b00 cmp r3, #0
8001bb2: d101 bne.n 8001bb8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001bb4: 2301 movs r3, #1
8001bb6: e0b3 b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001bb8: 4b5b ldr r3, [pc, #364] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001bba: 681b ldr r3, [r3, #0]
8001bbc: 2201 movs r2, #1
8001bbe: 4013 ands r3, r2
8001bc0: 683a ldr r2, [r7, #0]
8001bc2: 429a cmp r2, r3
8001bc4: d911 bls.n 8001bea <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001bc6: 4b58 ldr r3, [pc, #352] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001bc8: 681b ldr r3, [r3, #0]
8001bca: 2201 movs r2, #1
8001bcc: 4393 bics r3, r2
8001bce: 0019 movs r1, r3
8001bd0: 4b55 ldr r3, [pc, #340] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001bd2: 683a ldr r2, [r7, #0]
8001bd4: 430a orrs r2, r1
8001bd6: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001bd8: 4b53 ldr r3, [pc, #332] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001bda: 681b ldr r3, [r3, #0]
8001bdc: 2201 movs r2, #1
8001bde: 4013 ands r3, r2
8001be0: 683a ldr r2, [r7, #0]
8001be2: 429a cmp r2, r3
8001be4: d001 beq.n 8001bea <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
8001be6: 2301 movs r3, #1
8001be8: e09a b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001bea: 687b ldr r3, [r7, #4]
8001bec: 681b ldr r3, [r3, #0]
8001bee: 2202 movs r2, #2
8001bf0: 4013 ands r3, r2
8001bf2: d015 beq.n 8001c20 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001bf4: 687b ldr r3, [r7, #4]
8001bf6: 681b ldr r3, [r3, #0]
8001bf8: 2204 movs r2, #4
8001bfa: 4013 ands r3, r2
8001bfc: d006 beq.n 8001c0c <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8001bfe: 4b4b ldr r3, [pc, #300] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c00: 685a ldr r2, [r3, #4]
8001c02: 4b4a ldr r3, [pc, #296] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c04: 21e0 movs r1, #224 ; 0xe0
8001c06: 00c9 lsls r1, r1, #3
8001c08: 430a orrs r2, r1
8001c0a: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001c0c: 4b47 ldr r3, [pc, #284] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c0e: 685b ldr r3, [r3, #4]
8001c10: 22f0 movs r2, #240 ; 0xf0
8001c12: 4393 bics r3, r2
8001c14: 0019 movs r1, r3
8001c16: 687b ldr r3, [r7, #4]
8001c18: 689a ldr r2, [r3, #8]
8001c1a: 4b44 ldr r3, [pc, #272] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c1c: 430a orrs r2, r1
8001c1e: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001c20: 687b ldr r3, [r7, #4]
8001c22: 681b ldr r3, [r3, #0]
8001c24: 2201 movs r2, #1
8001c26: 4013 ands r3, r2
8001c28: d040 beq.n 8001cac <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001c2a: 687b ldr r3, [r7, #4]
8001c2c: 685b ldr r3, [r3, #4]
8001c2e: 2b01 cmp r3, #1
8001c30: d107 bne.n 8001c42 <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001c32: 4b3e ldr r3, [pc, #248] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c34: 681a ldr r2, [r3, #0]
8001c36: 2380 movs r3, #128 ; 0x80
8001c38: 029b lsls r3, r3, #10
8001c3a: 4013 ands r3, r2
8001c3c: d114 bne.n 8001c68 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001c3e: 2301 movs r3, #1
8001c40: e06e b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001c42: 687b ldr r3, [r7, #4]
8001c44: 685b ldr r3, [r3, #4]
8001c46: 2b02 cmp r3, #2
8001c48: d107 bne.n 8001c5a <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001c4a: 4b38 ldr r3, [pc, #224] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c4c: 681a ldr r2, [r3, #0]
8001c4e: 2380 movs r3, #128 ; 0x80
8001c50: 049b lsls r3, r3, #18
8001c52: 4013 ands r3, r2
8001c54: d108 bne.n 8001c68 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001c56: 2301 movs r3, #1
8001c58: e062 b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001c5a: 4b34 ldr r3, [pc, #208] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c5c: 681b ldr r3, [r3, #0]
8001c5e: 2202 movs r2, #2
8001c60: 4013 ands r3, r2
8001c62: d101 bne.n 8001c68 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001c64: 2301 movs r3, #1
8001c66: e05b b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001c68: 4b30 ldr r3, [pc, #192] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c6a: 685b ldr r3, [r3, #4]
8001c6c: 2203 movs r2, #3
8001c6e: 4393 bics r3, r2
8001c70: 0019 movs r1, r3
8001c72: 687b ldr r3, [r7, #4]
8001c74: 685a ldr r2, [r3, #4]
8001c76: 4b2d ldr r3, [pc, #180] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c78: 430a orrs r2, r1
8001c7a: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001c7c: f7fe fdf8 bl 8000870 <HAL_GetTick>
8001c80: 0003 movs r3, r0
8001c82: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001c84: e009 b.n 8001c9a <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001c86: f7fe fdf3 bl 8000870 <HAL_GetTick>
8001c8a: 0002 movs r2, r0
8001c8c: 68fb ldr r3, [r7, #12]
8001c8e: 1ad3 subs r3, r2, r3
8001c90: 4a27 ldr r2, [pc, #156] ; (8001d30 <HAL_RCC_ClockConfig+0x18c>)
8001c92: 4293 cmp r3, r2
8001c94: d901 bls.n 8001c9a <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
8001c96: 2303 movs r3, #3
8001c98: e042 b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001c9a: 4b24 ldr r3, [pc, #144] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001c9c: 685b ldr r3, [r3, #4]
8001c9e: 220c movs r2, #12
8001ca0: 401a ands r2, r3
8001ca2: 687b ldr r3, [r7, #4]
8001ca4: 685b ldr r3, [r3, #4]
8001ca6: 009b lsls r3, r3, #2
8001ca8: 429a cmp r2, r3
8001caa: d1ec bne.n 8001c86 <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001cac: 4b1e ldr r3, [pc, #120] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001cae: 681b ldr r3, [r3, #0]
8001cb0: 2201 movs r2, #1
8001cb2: 4013 ands r3, r2
8001cb4: 683a ldr r2, [r7, #0]
8001cb6: 429a cmp r2, r3
8001cb8: d211 bcs.n 8001cde <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001cba: 4b1b ldr r3, [pc, #108] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001cbc: 681b ldr r3, [r3, #0]
8001cbe: 2201 movs r2, #1
8001cc0: 4393 bics r3, r2
8001cc2: 0019 movs r1, r3
8001cc4: 4b18 ldr r3, [pc, #96] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001cc6: 683a ldr r2, [r7, #0]
8001cc8: 430a orrs r2, r1
8001cca: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001ccc: 4b16 ldr r3, [pc, #88] ; (8001d28 <HAL_RCC_ClockConfig+0x184>)
8001cce: 681b ldr r3, [r3, #0]
8001cd0: 2201 movs r2, #1
8001cd2: 4013 ands r3, r2
8001cd4: 683a ldr r2, [r7, #0]
8001cd6: 429a cmp r2, r3
8001cd8: d001 beq.n 8001cde <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
8001cda: 2301 movs r3, #1
8001cdc: e020 b.n 8001d20 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 681b ldr r3, [r3, #0]
8001ce2: 2204 movs r2, #4
8001ce4: 4013 ands r3, r2
8001ce6: d009 beq.n 8001cfc <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8001ce8: 4b10 ldr r3, [pc, #64] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001cea: 685b ldr r3, [r3, #4]
8001cec: 4a11 ldr r2, [pc, #68] ; (8001d34 <HAL_RCC_ClockConfig+0x190>)
8001cee: 4013 ands r3, r2
8001cf0: 0019 movs r1, r3
8001cf2: 687b ldr r3, [r7, #4]
8001cf4: 68da ldr r2, [r3, #12]
8001cf6: 4b0d ldr r3, [pc, #52] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001cf8: 430a orrs r2, r1
8001cfa: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8001cfc: f000 f820 bl 8001d40 <HAL_RCC_GetSysClockFreq>
8001d00: 0001 movs r1, r0
8001d02: 4b0a ldr r3, [pc, #40] ; (8001d2c <HAL_RCC_ClockConfig+0x188>)
8001d04: 685b ldr r3, [r3, #4]
8001d06: 091b lsrs r3, r3, #4
8001d08: 220f movs r2, #15
8001d0a: 4013 ands r3, r2
8001d0c: 4a0a ldr r2, [pc, #40] ; (8001d38 <HAL_RCC_ClockConfig+0x194>)
8001d0e: 5cd3 ldrb r3, [r2, r3]
8001d10: 000a movs r2, r1
8001d12: 40da lsrs r2, r3
8001d14: 4b09 ldr r3, [pc, #36] ; (8001d3c <HAL_RCC_ClockConfig+0x198>)
8001d16: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
8001d18: 2003 movs r0, #3
8001d1a: f7fe fd63 bl 80007e4 <HAL_InitTick>
return HAL_OK;
8001d1e: 2300 movs r3, #0
}
8001d20: 0018 movs r0, r3
8001d22: 46bd mov sp, r7
8001d24: b004 add sp, #16
8001d26: bd80 pop {r7, pc}
8001d28: 40022000 .word 0x40022000
8001d2c: 40021000 .word 0x40021000
8001d30: 00001388 .word 0x00001388
8001d34: fffff8ff .word 0xfffff8ff
8001d38: 08002c5c .word 0x08002c5c
8001d3c: 20000000 .word 0x20000000
08001d40 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001d40: b590 push {r4, r7, lr}
8001d42: b08f sub sp, #60 ; 0x3c
8001d44: af00 add r7, sp, #0
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
8001d46: 2314 movs r3, #20
8001d48: 18fb adds r3, r7, r3
8001d4a: 4a2b ldr r2, [pc, #172] ; (8001df8 <HAL_RCC_GetSysClockFreq+0xb8>)
8001d4c: ca13 ldmia r2!, {r0, r1, r4}
8001d4e: c313 stmia r3!, {r0, r1, r4}
8001d50: 6812 ldr r2, [r2, #0]
8001d52: 601a str r2, [r3, #0]
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
8001d54: 1d3b adds r3, r7, #4
8001d56: 4a29 ldr r2, [pc, #164] ; (8001dfc <HAL_RCC_GetSysClockFreq+0xbc>)
8001d58: ca13 ldmia r2!, {r0, r1, r4}
8001d5a: c313 stmia r3!, {r0, r1, r4}
8001d5c: 6812 ldr r2, [r2, #0]
8001d5e: 601a str r2, [r3, #0]
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8001d60: 2300 movs r3, #0
8001d62: 62fb str r3, [r7, #44] ; 0x2c
8001d64: 2300 movs r3, #0
8001d66: 62bb str r3, [r7, #40] ; 0x28
8001d68: 2300 movs r3, #0
8001d6a: 637b str r3, [r7, #52] ; 0x34
8001d6c: 2300 movs r3, #0
8001d6e: 627b str r3, [r7, #36] ; 0x24
uint32_t sysclockfreq = 0U;
8001d70: 2300 movs r3, #0
8001d72: 633b str r3, [r7, #48] ; 0x30
tmpreg = RCC->CFGR;
8001d74: 4b22 ldr r3, [pc, #136] ; (8001e00 <HAL_RCC_GetSysClockFreq+0xc0>)
8001d76: 685b ldr r3, [r3, #4]
8001d78: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8001d7a: 6afb ldr r3, [r7, #44] ; 0x2c
8001d7c: 220c movs r2, #12
8001d7e: 4013 ands r3, r2
8001d80: 2b04 cmp r3, #4
8001d82: d002 beq.n 8001d8a <HAL_RCC_GetSysClockFreq+0x4a>
8001d84: 2b08 cmp r3, #8
8001d86: d003 beq.n 8001d90 <HAL_RCC_GetSysClockFreq+0x50>
8001d88: e02d b.n 8001de6 <HAL_RCC_GetSysClockFreq+0xa6>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8001d8a: 4b1e ldr r3, [pc, #120] ; (8001e04 <HAL_RCC_GetSysClockFreq+0xc4>)
8001d8c: 633b str r3, [r7, #48] ; 0x30
break;
8001d8e: e02d b.n 8001dec <HAL_RCC_GetSysClockFreq+0xac>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
8001d90: 6afb ldr r3, [r7, #44] ; 0x2c
8001d92: 0c9b lsrs r3, r3, #18
8001d94: 220f movs r2, #15
8001d96: 4013 ands r3, r2
8001d98: 2214 movs r2, #20
8001d9a: 18ba adds r2, r7, r2
8001d9c: 5cd3 ldrb r3, [r2, r3]
8001d9e: 627b str r3, [r7, #36] ; 0x24
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
8001da0: 4b17 ldr r3, [pc, #92] ; (8001e00 <HAL_RCC_GetSysClockFreq+0xc0>)
8001da2: 6adb ldr r3, [r3, #44] ; 0x2c
8001da4: 220f movs r2, #15
8001da6: 4013 ands r3, r2
8001da8: 1d3a adds r2, r7, #4
8001daa: 5cd3 ldrb r3, [r2, r3]
8001dac: 62bb str r3, [r7, #40] ; 0x28
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
8001dae: 6afa ldr r2, [r7, #44] ; 0x2c
8001db0: 2380 movs r3, #128 ; 0x80
8001db2: 025b lsls r3, r3, #9
8001db4: 4013 ands r3, r2
8001db6: d009 beq.n 8001dcc <HAL_RCC_GetSysClockFreq+0x8c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8001db8: 6ab9 ldr r1, [r7, #40] ; 0x28
8001dba: 4812 ldr r0, [pc, #72] ; (8001e04 <HAL_RCC_GetSysClockFreq+0xc4>)
8001dbc: f7fe f9a4 bl 8000108 <__udivsi3>
8001dc0: 0003 movs r3, r0
8001dc2: 001a movs r2, r3
8001dc4: 6a7b ldr r3, [r7, #36] ; 0x24
8001dc6: 4353 muls r3, r2
8001dc8: 637b str r3, [r7, #52] ; 0x34
8001dca: e009 b.n 8001de0 <HAL_RCC_GetSysClockFreq+0xa0>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8001dcc: 6a79 ldr r1, [r7, #36] ; 0x24
8001dce: 000a movs r2, r1
8001dd0: 0152 lsls r2, r2, #5
8001dd2: 1a52 subs r2, r2, r1
8001dd4: 0193 lsls r3, r2, #6
8001dd6: 1a9b subs r3, r3, r2
8001dd8: 00db lsls r3, r3, #3
8001dda: 185b adds r3, r3, r1
8001ddc: 021b lsls r3, r3, #8
8001dde: 637b str r3, [r7, #52] ; 0x34
#endif
}
sysclockfreq = pllclk;
8001de0: 6b7b ldr r3, [r7, #52] ; 0x34
8001de2: 633b str r3, [r7, #48] ; 0x30
break;
8001de4: e002 b.n 8001dec <HAL_RCC_GetSysClockFreq+0xac>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8001de6: 4b07 ldr r3, [pc, #28] ; (8001e04 <HAL_RCC_GetSysClockFreq+0xc4>)
8001de8: 633b str r3, [r7, #48] ; 0x30
break;
8001dea: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
8001dec: 6b3b ldr r3, [r7, #48] ; 0x30
}
8001dee: 0018 movs r0, r3
8001df0: 46bd mov sp, r7
8001df2: b00f add sp, #60 ; 0x3c
8001df4: bd90 pop {r4, r7, pc}
8001df6: 46c0 nop ; (mov r8, r8)
8001df8: 08002c3c .word 0x08002c3c
8001dfc: 08002c4c .word 0x08002c4c
8001e00: 40021000 .word 0x40021000
8001e04: 007a1200 .word 0x007a1200
08001e08 <GEI_BUTTON_CODE>:
*/
#include "button.h"
void GEI_BUTTON_CODE(struct button *bt,uint8_t in)
{
8001e08: b580 push {r7, lr}
8001e0a: b082 sub sp, #8
8001e0c: af00 add r7, sp, #0
8001e0e: 6078 str r0, [r7, #4]
8001e10: 000a movs r2, r1
8001e12: 1cfb adds r3, r7, #3
8001e14: 701a strb r2, [r3, #0]
#define t 250
bt->code=0;
8001e16: 687b ldr r3, [r7, #4]
8001e18: 2200 movs r2, #0
8001e1a: 601a str r2, [r3, #0]
if(in==1)
8001e1c: 1cfb adds r3, r7, #3
8001e1e: 781b ldrb r3, [r3, #0]
8001e20: 2b01 cmp r3, #1
8001e22: d138 bne.n 8001e96 <GEI_BUTTON_CODE+0x8e>
{
if(bt->lock==0)
8001e24: 687b ldr r3, [r7, #4]
8001e26: 791b ldrb r3, [r3, #4]
8001e28: 2b00 cmp r3, #0
8001e2a: d120 bne.n 8001e6e <GEI_BUTTON_CODE+0x66>
{
if(HAL_GetTick()<bt->time+t)
8001e2c: f7fe fd20 bl 8000870 <HAL_GetTick>
8001e30: 0002 movs r2, r0
8001e32: 687b ldr r3, [r7, #4]
8001e34: 689b ldr r3, [r3, #8]
8001e36: 33fa adds r3, #250 ; 0xfa
8001e38: 429a cmp r2, r3
8001e3a: d20d bcs.n 8001e58 <GEI_BUTTON_CODE+0x50>
{
bt->times++;
8001e3c: 687b ldr r3, [r7, #4]
8001e3e: 68db ldr r3, [r3, #12]
8001e40: 1c5a adds r2, r3, #1
8001e42: 687b ldr r3, [r7, #4]
8001e44: 60da str r2, [r3, #12]
bt->time=HAL_GetTick();
8001e46: f7fe fd13 bl 8000870 <HAL_GetTick>
8001e4a: 0002 movs r2, r0
8001e4c: 687b ldr r3, [r7, #4]
8001e4e: 609a str r2, [r3, #8]
bt->lock=1;
8001e50: 687b ldr r3, [r7, #4]
8001e52: 2201 movs r2, #1
8001e54: 711a strb r2, [r3, #4]
8001e56: e00a b.n 8001e6e <GEI_BUTTON_CODE+0x66>
}else
{
bt->times=1;
8001e58: 687b ldr r3, [r7, #4]
8001e5a: 2201 movs r2, #1
8001e5c: 60da str r2, [r3, #12]
bt->time=HAL_GetTick();
8001e5e: f7fe fd07 bl 8000870 <HAL_GetTick>
8001e62: 0002 movs r2, r0
8001e64: 687b ldr r3, [r7, #4]
8001e66: 609a str r2, [r3, #8]
bt->lock=1;
8001e68: 687b ldr r3, [r7, #4]
8001e6a: 2201 movs r2, #1
8001e6c: 711a strb r2, [r3, #4]
}
}
if(bt->lock==1)
8001e6e: 687b ldr r3, [r7, #4]
8001e70: 791b ldrb r3, [r3, #4]
8001e72: 2b01 cmp r3, #1
8001e74: d10f bne.n 8001e96 <GEI_BUTTON_CODE+0x8e>
{
if(HAL_GetTick()>bt->time+t)
8001e76: f7fe fcfb bl 8000870 <HAL_GetTick>
8001e7a: 0002 movs r2, r0
8001e7c: 687b ldr r3, [r7, #4]
8001e7e: 689b ldr r3, [r3, #8]
8001e80: 33fa adds r3, #250 ; 0xfa
8001e82: 429a cmp r2, r3
8001e84: d907 bls.n 8001e96 <GEI_BUTTON_CODE+0x8e>
{
bt->code=-1;
8001e86: 687b ldr r3, [r7, #4]
8001e88: 2201 movs r2, #1
8001e8a: 4252 negs r2, r2
8001e8c: 601a str r2, [r3, #0]
bt->times=-1;
8001e8e: 687b ldr r3, [r7, #4]
8001e90: 2201 movs r2, #1
8001e92: 4252 negs r2, r2
8001e94: 60da str r2, [r3, #12]
}
}
}
if(in==0)
8001e96: 1cfb adds r3, r7, #3
8001e98: 781b ldrb r3, [r3, #0]
8001e9a: 2b00 cmp r3, #0
8001e9c: d10e bne.n 8001ebc <GEI_BUTTON_CODE+0xb4>
{
if(bt->lock==1)
8001e9e: 687b ldr r3, [r7, #4]
8001ea0: 791b ldrb r3, [r3, #4]
8001ea2: 2b01 cmp r3, #1
8001ea4: d10a bne.n 8001ebc <GEI_BUTTON_CODE+0xb4>
{
if(bt->code==-1)
8001ea6: 687b ldr r3, [r7, #4]
8001ea8: 681b ldr r3, [r3, #0]
8001eaa: 3301 adds r3, #1
8001eac: d003 beq.n 8001eb6 <GEI_BUTTON_CODE+0xae>
{
}else
{
bt->code=bt->times;
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 68da ldr r2, [r3, #12]
8001eb2: 687b ldr r3, [r7, #4]
8001eb4: 601a str r2, [r3, #0]
}
bt->lock=0;
8001eb6: 687b ldr r3, [r7, #4]
8001eb8: 2200 movs r2, #0
8001eba: 711a strb r2, [r3, #4]
}
}
}
8001ebc: 46c0 nop ; (mov r8, r8)
8001ebe: 46bd mov sp, r7
8001ec0: b002 add sp, #8
8001ec2: bd80 pop {r7, pc}
08001ec4 <Send_to_595>:
char led_n:1;
char led_err:1;
}dis_buff;
void Send_to_595(char h,char l)
{
8001ec4: b580 push {r7, lr}
8001ec6: b084 sub sp, #16
8001ec8: af00 add r7, sp, #0
8001eca: 0002 movs r2, r0
8001ecc: 1dfb adds r3, r7, #7
8001ece: 701a strb r2, [r3, #0]
8001ed0: 1dbb adds r3, r7, #6
8001ed2: 1c0a adds r2, r1, #0
8001ed4: 701a strb r2, [r3, #0]
for(int a=0;a<8;a++)
8001ed6: 2300 movs r3, #0
8001ed8: 60fb str r3, [r7, #12]
8001eda: e027 b.n 8001f2c <Send_to_595+0x68>
{
if((h<<a)&0x80)
8001edc: 1dfb adds r3, r7, #7
8001ede: 781a ldrb r2, [r3, #0]
8001ee0: 68fb ldr r3, [r7, #12]
8001ee2: 409a lsls r2, r3
8001ee4: 0013 movs r3, r2
8001ee6: 2280 movs r2, #128 ; 0x80
8001ee8: 4013 ands r3, r2
8001eea: d007 beq.n 8001efc <Send_to_595+0x38>
{
HC595_DCK(1);
8001eec: 2390 movs r3, #144 ; 0x90
8001eee: 05db lsls r3, r3, #23
8001ef0: 2201 movs r2, #1
8001ef2: 2108 movs r1, #8
8001ef4: 0018 movs r0, r3
8001ef6: f7ff fb1e bl 8001536 <HAL_GPIO_WritePin>
8001efa: e006 b.n 8001f0a <Send_to_595+0x46>
}else
{
HC595_DCK(0);
8001efc: 2390 movs r3, #144 ; 0x90
8001efe: 05db lsls r3, r3, #23
8001f00: 2200 movs r2, #0
8001f02: 2108 movs r1, #8
8001f04: 0018 movs r0, r3
8001f06: f7ff fb16 bl 8001536 <HAL_GPIO_WritePin>
}
HC595_SCK(1);
8001f0a: 2390 movs r3, #144 ; 0x90
8001f0c: 05db lsls r3, r3, #23
8001f0e: 2201 movs r2, #1
8001f10: 2120 movs r1, #32
8001f12: 0018 movs r0, r3
8001f14: f7ff fb0f bl 8001536 <HAL_GPIO_WritePin>
HC595_SCK(0);
8001f18: 2390 movs r3, #144 ; 0x90
8001f1a: 05db lsls r3, r3, #23
8001f1c: 2200 movs r2, #0
8001f1e: 2120 movs r1, #32
8001f20: 0018 movs r0, r3
8001f22: f7ff fb08 bl 8001536 <HAL_GPIO_WritePin>
for(int a=0;a<8;a++)
8001f26: 68fb ldr r3, [r7, #12]
8001f28: 3301 adds r3, #1
8001f2a: 60fb str r3, [r7, #12]
8001f2c: 68fb ldr r3, [r7, #12]
8001f2e: 2b07 cmp r3, #7
8001f30: ddd4 ble.n 8001edc <Send_to_595+0x18>
}
for(int a=0;a<8;a++)
8001f32: 2300 movs r3, #0
8001f34: 60bb str r3, [r7, #8]
8001f36: e027 b.n 8001f88 <Send_to_595+0xc4>
{
if((l<<a)&0x80)
8001f38: 1dbb adds r3, r7, #6
8001f3a: 781a ldrb r2, [r3, #0]
8001f3c: 68bb ldr r3, [r7, #8]
8001f3e: 409a lsls r2, r3
8001f40: 0013 movs r3, r2
8001f42: 2280 movs r2, #128 ; 0x80
8001f44: 4013 ands r3, r2
8001f46: d007 beq.n 8001f58 <Send_to_595+0x94>
{
HC595_DCK(1);
8001f48: 2390 movs r3, #144 ; 0x90
8001f4a: 05db lsls r3, r3, #23
8001f4c: 2201 movs r2, #1
8001f4e: 2108 movs r1, #8
8001f50: 0018 movs r0, r3
8001f52: f7ff faf0 bl 8001536 <HAL_GPIO_WritePin>
8001f56: e006 b.n 8001f66 <Send_to_595+0xa2>
}else
{
HC595_DCK(0);
8001f58: 2390 movs r3, #144 ; 0x90
8001f5a: 05db lsls r3, r3, #23
8001f5c: 2200 movs r2, #0
8001f5e: 2108 movs r1, #8
8001f60: 0018 movs r0, r3
8001f62: f7ff fae8 bl 8001536 <HAL_GPIO_WritePin>
}
HC595_SCK(1);
8001f66: 2390 movs r3, #144 ; 0x90
8001f68: 05db lsls r3, r3, #23
8001f6a: 2201 movs r2, #1
8001f6c: 2120 movs r1, #32
8001f6e: 0018 movs r0, r3
8001f70: f7ff fae1 bl 8001536 <HAL_GPIO_WritePin>
HC595_SCK(0);
8001f74: 2390 movs r3, #144 ; 0x90
8001f76: 05db lsls r3, r3, #23
8001f78: 2200 movs r2, #0
8001f7a: 2120 movs r1, #32
8001f7c: 0018 movs r0, r3
8001f7e: f7ff fada bl 8001536 <HAL_GPIO_WritePin>
for(int a=0;a<8;a++)
8001f82: 68bb ldr r3, [r7, #8]
8001f84: 3301 adds r3, #1
8001f86: 60bb str r3, [r7, #8]
8001f88: 68bb ldr r3, [r7, #8]
8001f8a: 2b07 cmp r3, #7
8001f8c: ddd4 ble.n 8001f38 <Send_to_595+0x74>
}
HC595_RCK(1);
8001f8e: 2390 movs r3, #144 ; 0x90
8001f90: 05db lsls r3, r3, #23
8001f92: 2201 movs r2, #1
8001f94: 2110 movs r1, #16
8001f96: 0018 movs r0, r3
8001f98: f7ff facd bl 8001536 <HAL_GPIO_WritePin>
HC595_RCK(0);
8001f9c: 2390 movs r3, #144 ; 0x90
8001f9e: 05db lsls r3, r3, #23
8001fa0: 2200 movs r2, #0
8001fa2: 2110 movs r1, #16
8001fa4: 0018 movs r0, r3
8001fa6: f7ff fac6 bl 8001536 <HAL_GPIO_WritePin>
}
8001faa: 46c0 nop ; (mov r8, r8)
8001fac: 46bd mov sp, r7
8001fae: b004 add sp, #16
8001fb0: bd80 pop {r7, pc}
...
08001fb4 <display>:
void display()
{
8001fb4: b580 push {r7, lr}
8001fb6: b082 sub sp, #8
8001fb8: af00 add r7, sp, #0
char h_buff=0,l_buff=0;
8001fba: 1dfb adds r3, r7, #7
8001fbc: 2200 movs r2, #0
8001fbe: 701a strb r2, [r3, #0]
8001fc0: 1dbb adds r3, r7, #6
8001fc2: 2200 movs r2, #0
8001fc4: 701a strb r2, [r3, #0]
h_buff=0,l_buff=0;
8001fc6: 1dfb adds r3, r7, #7
8001fc8: 2200 movs r2, #0
8001fca: 701a strb r2, [r3, #0]
8001fcc: 1dbb adds r3, r7, #6
8001fce: 2200 movs r2, #0
8001fd0: 701a strb r2, [r3, #0]
Send_to_595(h_buff,l_buff);
8001fd2: 1dbb adds r3, r7, #6
8001fd4: 781a ldrb r2, [r3, #0]
8001fd6: 1dfb adds r3, r7, #7
8001fd8: 781b ldrb r3, [r3, #0]
8001fda: 0011 movs r1, r2
8001fdc: 0018 movs r0, r3
8001fde: f7ff ff71 bl 8001ec4 <Send_to_595>
h_buff=~0x01;
8001fe2: 1dfb adds r3, r7, #7
8001fe4: 22fe movs r2, #254 ; 0xfe
8001fe6: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[0]>=10?0:d_num_data[0][dis_buff.d_num[0]];
8001fe8: 4b7b ldr r3, [pc, #492] ; (80021d8 <display+0x224>)
8001fea: 781b ldrb r3, [r3, #0]
8001fec: 2b09 cmp r3, #9
8001fee: d805 bhi.n 8001ffc <display+0x48>
8001ff0: 4b79 ldr r3, [pc, #484] ; (80021d8 <display+0x224>)
8001ff2: 781b ldrb r3, [r3, #0]
8001ff4: 001a movs r2, r3
8001ff6: 4b79 ldr r3, [pc, #484] ; (80021dc <display+0x228>)
8001ff8: 5c9a ldrb r2, [r3, r2]
8001ffa: e000 b.n 8001ffe <display+0x4a>
8001ffc: 2200 movs r2, #0
8001ffe: 1dbb adds r3, r7, #6
8002000: 701a strb r2, [r3, #0]
if(dis_buff.dot1==1)
8002002: 4b75 ldr r3, [pc, #468] ; (80021d8 <display+0x224>)
8002004: 791b ldrb r3, [r3, #4]
8002006: 2201 movs r2, #1
8002008: 4013 ands r3, r2
800200a: b2db uxtb r3, r3
800200c: 2b00 cmp r3, #0
800200e: d006 beq.n 800201e <display+0x6a>
{
l_buff|=0x80;
8002010: 1dbb adds r3, r7, #6
8002012: 1dba adds r2, r7, #6
8002014: 7812 ldrb r2, [r2, #0]
8002016: 2180 movs r1, #128 ; 0x80
8002018: 4249 negs r1, r1
800201a: 430a orrs r2, r1
800201c: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
800201e: 1dbb adds r3, r7, #6
8002020: 781a ldrb r2, [r3, #0]
8002022: 1dfb adds r3, r7, #7
8002024: 781b ldrb r3, [r3, #0]
8002026: 0011 movs r1, r2
8002028: 0018 movs r0, r3
800202a: f7ff ff4b bl 8001ec4 <Send_to_595>
h_buff=0,l_buff=0;
800202e: 1dfb adds r3, r7, #7
8002030: 2200 movs r2, #0
8002032: 701a strb r2, [r3, #0]
8002034: 1dbb adds r3, r7, #6
8002036: 2200 movs r2, #0
8002038: 701a strb r2, [r3, #0]
Send_to_595(h_buff,l_buff);
800203a: 1dbb adds r3, r7, #6
800203c: 781a ldrb r2, [r3, #0]
800203e: 1dfb adds r3, r7, #7
8002040: 781b ldrb r3, [r3, #0]
8002042: 0011 movs r1, r2
8002044: 0018 movs r0, r3
8002046: f7ff ff3d bl 8001ec4 <Send_to_595>
h_buff=~0x80;
800204a: 1dfb adds r3, r7, #7
800204c: 227f movs r2, #127 ; 0x7f
800204e: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[1]>=10?0:d_num_data[1][dis_buff.d_num[1]];
8002050: 4b61 ldr r3, [pc, #388] ; (80021d8 <display+0x224>)
8002052: 785b ldrb r3, [r3, #1]
8002054: 2b09 cmp r3, #9
8002056: d806 bhi.n 8002066 <display+0xb2>
8002058: 4b5f ldr r3, [pc, #380] ; (80021d8 <display+0x224>)
800205a: 785b ldrb r3, [r3, #1]
800205c: 001a movs r2, r3
800205e: 4b5f ldr r3, [pc, #380] ; (80021dc <display+0x228>)
8002060: 189b adds r3, r3, r2
8002062: 7a9a ldrb r2, [r3, #10]
8002064: e000 b.n 8002068 <display+0xb4>
8002066: 2200 movs r2, #0
8002068: 1dbb adds r3, r7, #6
800206a: 701a strb r2, [r3, #0]
if(dis_buff.dot2==1)
800206c: 4b5a ldr r3, [pc, #360] ; (80021d8 <display+0x224>)
800206e: 791b ldrb r3, [r3, #4]
8002070: 2202 movs r2, #2
8002072: 4013 ands r3, r2
8002074: b2db uxtb r3, r3
8002076: 2b00 cmp r3, #0
8002078: d005 beq.n 8002086 <display+0xd2>
{
l_buff|=0x10;
800207a: 1dbb adds r3, r7, #6
800207c: 1dba adds r2, r7, #6
800207e: 7812 ldrb r2, [r2, #0]
8002080: 2110 movs r1, #16
8002082: 430a orrs r2, r1
8002084: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8002086: 1dbb adds r3, r7, #6
8002088: 781a ldrb r2, [r3, #0]
800208a: 1dfb adds r3, r7, #7
800208c: 781b ldrb r3, [r3, #0]
800208e: 0011 movs r1, r2
8002090: 0018 movs r0, r3
8002092: f7ff ff17 bl 8001ec4 <Send_to_595>
h_buff=0,l_buff=0;
8002096: 1dfb adds r3, r7, #7
8002098: 2200 movs r2, #0
800209a: 701a strb r2, [r3, #0]
800209c: 1dbb adds r3, r7, #6
800209e: 2200 movs r2, #0
80020a0: 701a strb r2, [r3, #0]
Send_to_595(h_buff,l_buff);
80020a2: 1dbb adds r3, r7, #6
80020a4: 781a ldrb r2, [r3, #0]
80020a6: 1dfb adds r3, r7, #7
80020a8: 781b ldrb r3, [r3, #0]
80020aa: 0011 movs r1, r2
80020ac: 0018 movs r0, r3
80020ae: f7ff ff09 bl 8001ec4 <Send_to_595>
h_buff=~0x40;
80020b2: 1dfb adds r3, r7, #7
80020b4: 22bf movs r2, #191 ; 0xbf
80020b6: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[2]>=10?0:d_num_data[0][dis_buff.d_num[2]];
80020b8: 4b47 ldr r3, [pc, #284] ; (80021d8 <display+0x224>)
80020ba: 789b ldrb r3, [r3, #2]
80020bc: 2b09 cmp r3, #9
80020be: d805 bhi.n 80020cc <display+0x118>
80020c0: 4b45 ldr r3, [pc, #276] ; (80021d8 <display+0x224>)
80020c2: 789b ldrb r3, [r3, #2]
80020c4: 001a movs r2, r3
80020c6: 4b45 ldr r3, [pc, #276] ; (80021dc <display+0x228>)
80020c8: 5c9a ldrb r2, [r3, r2]
80020ca: e000 b.n 80020ce <display+0x11a>
80020cc: 2200 movs r2, #0
80020ce: 1dbb adds r3, r7, #6
80020d0: 701a strb r2, [r3, #0]
if(dis_buff.dot3==1)
80020d2: 4b41 ldr r3, [pc, #260] ; (80021d8 <display+0x224>)
80020d4: 791b ldrb r3, [r3, #4]
80020d6: 2204 movs r2, #4
80020d8: 4013 ands r3, r2
80020da: b2db uxtb r3, r3
80020dc: 2b00 cmp r3, #0
80020de: d006 beq.n 80020ee <display+0x13a>
{
l_buff|=0x80;
80020e0: 1dbb adds r3, r7, #6
80020e2: 1dba adds r2, r7, #6
80020e4: 7812 ldrb r2, [r2, #0]
80020e6: 2180 movs r1, #128 ; 0x80
80020e8: 4249 negs r1, r1
80020ea: 430a orrs r2, r1
80020ec: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
80020ee: 1dbb adds r3, r7, #6
80020f0: 781a ldrb r2, [r3, #0]
80020f2: 1dfb adds r3, r7, #7
80020f4: 781b ldrb r3, [r3, #0]
80020f6: 0011 movs r1, r2
80020f8: 0018 movs r0, r3
80020fa: f7ff fee3 bl 8001ec4 <Send_to_595>
h_buff=0,l_buff=0;
80020fe: 1dfb adds r3, r7, #7
8002100: 2200 movs r2, #0
8002102: 701a strb r2, [r3, #0]
8002104: 1dbb adds r3, r7, #6
8002106: 2200 movs r2, #0
8002108: 701a strb r2, [r3, #0]
Send_to_595(h_buff,l_buff);
800210a: 1dbb adds r3, r7, #6
800210c: 781a ldrb r2, [r3, #0]
800210e: 1dfb adds r3, r7, #7
8002110: 781b ldrb r3, [r3, #0]
8002112: 0011 movs r1, r2
8002114: 0018 movs r0, r3
8002116: f7ff fed5 bl 8001ec4 <Send_to_595>
h_buff=0xC1;
800211a: 1dfb adds r3, r7, #7
800211c: 22c1 movs r2, #193 ; 0xc1
800211e: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[3]>=10?0:d_num_data[1][dis_buff.d_num[3]];
8002120: 4b2d ldr r3, [pc, #180] ; (80021d8 <display+0x224>)
8002122: 78db ldrb r3, [r3, #3]
8002124: 2b09 cmp r3, #9
8002126: d806 bhi.n 8002136 <display+0x182>
8002128: 4b2b ldr r3, [pc, #172] ; (80021d8 <display+0x224>)
800212a: 78db ldrb r3, [r3, #3]
800212c: 001a movs r2, r3
800212e: 4b2b ldr r3, [pc, #172] ; (80021dc <display+0x228>)
8002130: 189b adds r3, r3, r2
8002132: 7a9a ldrb r2, [r3, #10]
8002134: e000 b.n 8002138 <display+0x184>
8002136: 2200 movs r2, #0
8002138: 1dbb adds r3, r7, #6
800213a: 701a strb r2, [r3, #0]
if(dis_buff.dot4==1)
800213c: 4b26 ldr r3, [pc, #152] ; (80021d8 <display+0x224>)
800213e: 791b ldrb r3, [r3, #4]
8002140: 2208 movs r2, #8
8002142: 4013 ands r3, r2
8002144: b2db uxtb r3, r3
8002146: 2b00 cmp r3, #0
8002148: d005 beq.n 8002156 <display+0x1a2>
{
l_buff|=0x10;
800214a: 1dbb adds r3, r7, #6
800214c: 1dba adds r2, r7, #6
800214e: 7812 ldrb r2, [r2, #0]
8002150: 2110 movs r1, #16
8002152: 430a orrs r2, r1
8002154: 701a strb r2, [r3, #0]
}
if(dis_buff.led_run==1)
8002156: 4b20 ldr r3, [pc, #128] ; (80021d8 <display+0x224>)
8002158: 791b ldrb r3, [r3, #4]
800215a: 2210 movs r2, #16
800215c: 4013 ands r3, r2
800215e: b2db uxtb r3, r3
8002160: 2b00 cmp r3, #0
8002162: d005 beq.n 8002170 <display+0x1bc>
{
h_buff|=0x10;
8002164: 1dfb adds r3, r7, #7
8002166: 1dfa adds r2, r7, #7
8002168: 7812 ldrb r2, [r2, #0]
800216a: 2110 movs r1, #16
800216c: 430a orrs r2, r1
800216e: 701a strb r2, [r3, #0]
}
if(dis_buff.led_err==1)
8002170: 4b19 ldr r3, [pc, #100] ; (80021d8 <display+0x224>)
8002172: 791b ldrb r3, [r3, #4]
8002174: 227f movs r2, #127 ; 0x7f
8002176: 4393 bics r3, r2
8002178: b2db uxtb r3, r3
800217a: 2b00 cmp r3, #0
800217c: d005 beq.n 800218a <display+0x1d6>
{
h_buff|=0x08;
800217e: 1dfb adds r3, r7, #7
8002180: 1dfa adds r2, r7, #7
8002182: 7812 ldrb r2, [r2, #0]
8002184: 2108 movs r1, #8
8002186: 430a orrs r2, r1
8002188: 701a strb r2, [r3, #0]
}
if(dis_buff.led_n==1)
800218a: 4b13 ldr r3, [pc, #76] ; (80021d8 <display+0x224>)
800218c: 791b ldrb r3, [r3, #4]
800218e: 2240 movs r2, #64 ; 0x40
8002190: 4013 ands r3, r2
8002192: b2db uxtb r3, r3
8002194: 2b00 cmp r3, #0
8002196: d005 beq.n 80021a4 <display+0x1f0>
{
h_buff|=0x04;
8002198: 1dfb adds r3, r7, #7
800219a: 1dfa adds r2, r7, #7
800219c: 7812 ldrb r2, [r2, #0]
800219e: 2104 movs r1, #4
80021a0: 430a orrs r2, r1
80021a2: 701a strb r2, [r3, #0]
}
if(dis_buff.led_p==1)
80021a4: 4b0c ldr r3, [pc, #48] ; (80021d8 <display+0x224>)
80021a6: 791b ldrb r3, [r3, #4]
80021a8: 2220 movs r2, #32
80021aa: 4013 ands r3, r2
80021ac: b2db uxtb r3, r3
80021ae: 2b00 cmp r3, #0
80021b0: d005 beq.n 80021be <display+0x20a>
{
h_buff|=0x02;
80021b2: 1dfb adds r3, r7, #7
80021b4: 1dfa adds r2, r7, #7
80021b6: 7812 ldrb r2, [r2, #0]
80021b8: 2102 movs r1, #2
80021ba: 430a orrs r2, r1
80021bc: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
80021be: 1dbb adds r3, r7, #6
80021c0: 781a ldrb r2, [r3, #0]
80021c2: 1dfb adds r3, r7, #7
80021c4: 781b ldrb r3, [r3, #0]
80021c6: 0011 movs r1, r2
80021c8: 0018 movs r0, r3
80021ca: f7ff fe7b bl 8001ec4 <Send_to_595>
}
80021ce: 46c0 nop ; (mov r8, r8)
80021d0: 46bd mov sp, r7
80021d2: b002 add sp, #8
80021d4: bd80 pop {r7, pc}
80021d6: 46c0 nop ; (mov r8, r8)
80021d8: 20000084 .word 0x20000084
80021dc: 08002c6c .word 0x08002c6c
080021e0 <mymain>:
long countdown=0;
long countdown_set=15000;
void mymain()
{
80021e0: b590 push {r4, r7, lr}
80021e2: b087 sub sp, #28
80021e4: af00 add r7, sp, #0
uint32_t runtime=0,move=0;
80021e6: 2300 movs r3, #0
80021e8: 617b str r3, [r7, #20]
80021ea: 2300 movs r3, #0
80021ec: 613b str r3, [r7, #16]
uint8_t mode=0,overload_mode=0;
80021ee: 230f movs r3, #15
80021f0: 18fb adds r3, r7, r3
80021f2: 2200 movs r2, #0
80021f4: 701a strb r2, [r3, #0]
80021f6: 230e movs r3, #14
80021f8: 18fb adds r3, r7, r3
80021fa: 2200 movs r2, #0
80021fc: 701a strb r2, [r3, #0]
uint16_t adc,adc_times=0;
80021fe: 230a movs r3, #10
8002200: 18fb adds r3, r7, r3
8002202: 2200 movs r2, #0
8002204: 801a strh r2, [r3, #0]
uint32_t adc_l;
uint16_t overload_times=0;
8002206: 1cbb adds r3, r7, #2
8002208: 2200 movs r2, #0
800220a: 801a strh r2, [r3, #0]
MOTA(0);
800220c: 4bd1 ldr r3, [pc, #836] ; (8002554 <mymain+0x374>)
800220e: 2200 movs r2, #0
8002210: 2101 movs r1, #1
8002212: 0018 movs r0, r3
8002214: f7ff f98f bl 8001536 <HAL_GPIO_WritePin>
MOTB(0);
8002218: 4bce ldr r3, [pc, #824] ; (8002554 <mymain+0x374>)
800221a: 2200 movs r2, #0
800221c: 2102 movs r1, #2
800221e: 0018 movs r0, r3
8002220: f7ff f989 bl 8001536 <HAL_GPIO_WritePin>
HC595_DCK(0);
8002224: 2390 movs r3, #144 ; 0x90
8002226: 05db lsls r3, r3, #23
8002228: 2200 movs r2, #0
800222a: 2108 movs r1, #8
800222c: 0018 movs r0, r3
800222e: f7ff f982 bl 8001536 <HAL_GPIO_WritePin>
HC595_RCK(0);
8002232: 2390 movs r3, #144 ; 0x90
8002234: 05db lsls r3, r3, #23
8002236: 2200 movs r2, #0
8002238: 2110 movs r1, #16
800223a: 0018 movs r0, r3
800223c: f7ff f97b bl 8001536 <HAL_GPIO_WritePin>
HC595_SCK(0);
8002240: 2390 movs r3, #144 ; 0x90
8002242: 05db lsls r3, r3, #23
8002244: 2200 movs r2, #0
8002246: 2120 movs r1, #32
8002248: 0018 movs r0, r3
800224a: f7ff f974 bl 8001536 <HAL_GPIO_WritePin>
dis_buff.d_num[0]=0xff;
800224e: 4bc2 ldr r3, [pc, #776] ; (8002558 <mymain+0x378>)
8002250: 22ff movs r2, #255 ; 0xff
8002252: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=0xff;
8002254: 4bc0 ldr r3, [pc, #768] ; (8002558 <mymain+0x378>)
8002256: 22ff movs r2, #255 ; 0xff
8002258: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=0xff;
800225a: 4bbf ldr r3, [pc, #764] ; (8002558 <mymain+0x378>)
800225c: 22ff movs r2, #255 ; 0xff
800225e: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=0xff;
8002260: 4bbd ldr r3, [pc, #756] ; (8002558 <mymain+0x378>)
8002262: 22ff movs r2, #255 ; 0xff
8002264: 70da strb r2, [r3, #3]
countdown=1000;
8002266: 4bbd ldr r3, [pc, #756] ; (800255c <mymain+0x37c>)
8002268: 22fa movs r2, #250 ; 0xfa
800226a: 0092 lsls r2, r2, #2
800226c: 601a str r2, [r3, #0]
while(1)
{
switch(mode)
800226e: 230f movs r3, #15
8002270: 18fb adds r3, r7, r3
8002272: 781b ldrb r3, [r3, #0]
8002274: 2b05 cmp r3, #5
8002276: d901 bls.n 800227c <mymain+0x9c>
8002278: f000 fbfd bl 8002a76 <mymain+0x896>
800227c: 009a lsls r2, r3, #2
800227e: 4bb8 ldr r3, [pc, #736] ; (8002560 <mymain+0x380>)
8002280: 18d3 adds r3, r2, r3
8002282: 681b ldr r3, [r3, #0]
8002284: 469f mov pc, r3
{
case 0:
//Startup
if(HAL_GetTick()>move)
8002286: f7fe faf3 bl 8000870 <HAL_GetTick>
800228a: 0002 movs r2, r0
800228c: 693b ldr r3, [r7, #16]
800228e: 4293 cmp r3, r2
8002290: d301 bcc.n 8002296 <mymain+0xb6>
8002292: f000 fbe7 bl 8002a64 <mymain+0x884>
{
move=HAL_GetTick()+100;
8002296: f7fe faeb bl 8000870 <HAL_GetTick>
800229a: 0003 movs r3, r0
800229c: 3364 adds r3, #100 ; 0x64
800229e: 613b str r3, [r7, #16]
countdown-=100;
80022a0: 4bae ldr r3, [pc, #696] ; (800255c <mymain+0x37c>)
80022a2: 681b ldr r3, [r3, #0]
80022a4: 3b64 subs r3, #100 ; 0x64
80022a6: 001a movs r2, r3
80022a8: 4bac ldr r3, [pc, #688] ; (800255c <mymain+0x37c>)
80022aa: 601a str r2, [r3, #0]
if(countdown<0)
80022ac: 4bab ldr r3, [pc, #684] ; (800255c <mymain+0x37c>)
80022ae: 681b ldr r3, [r3, #0]
80022b0: 2b00 cmp r3, #0
80022b2: da03 bge.n 80022bc <mymain+0xdc>
{
mode=1;
80022b4: 230f movs r3, #15
80022b6: 18fb adds r3, r7, r3
80022b8: 2201 movs r2, #1
80022ba: 701a strb r2, [r3, #0]
}
HAL_ADC_Start(&hadc);
80022bc: 4ba9 ldr r3, [pc, #676] ; (8002564 <mymain+0x384>)
80022be: 0018 movs r0, r3
80022c0: f7fe fc20 bl 8000b04 <HAL_ADC_Start>
HAL_ADC_GetValue(&hadc);
80022c4: 4ba7 ldr r3, [pc, #668] ; (8002564 <mymain+0x384>)
80022c6: 0018 movs r0, r3
80022c8: f7fe fcb0 bl 8000c2c <HAL_ADC_GetValue>
HAL_ADC_Stop(&hadc);
80022cc: 4ba5 ldr r3, [pc, #660] ; (8002564 <mymain+0x384>)
80022ce: 0018 movs r0, r3
80022d0: f7fe fc6c bl 8000bac <HAL_ADC_Stop>
dis_buff.d_num[0]=((countdown/100)%10);
80022d4: 4ba1 ldr r3, [pc, #644] ; (800255c <mymain+0x37c>)
80022d6: 681b ldr r3, [r3, #0]
80022d8: 2164 movs r1, #100 ; 0x64
80022da: 0018 movs r0, r3
80022dc: f7fd ff9e bl 800021c <__divsi3>
80022e0: 0003 movs r3, r0
80022e2: 210a movs r1, #10
80022e4: 0018 movs r0, r3
80022e6: f7fe f87f bl 80003e8 <__aeabi_idivmod>
80022ea: 000b movs r3, r1
80022ec: b2da uxtb r2, r3
80022ee: 4b9a ldr r3, [pc, #616] ; (8002558 <mymain+0x378>)
80022f0: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=((countdown/100)%10);
80022f2: 4b9a ldr r3, [pc, #616] ; (800255c <mymain+0x37c>)
80022f4: 681b ldr r3, [r3, #0]
80022f6: 2164 movs r1, #100 ; 0x64
80022f8: 0018 movs r0, r3
80022fa: f7fd ff8f bl 800021c <__divsi3>
80022fe: 0003 movs r3, r0
8002300: 210a movs r1, #10
8002302: 0018 movs r0, r3
8002304: f7fe f870 bl 80003e8 <__aeabi_idivmod>
8002308: 000b movs r3, r1
800230a: b2da uxtb r2, r3
800230c: 4b92 ldr r3, [pc, #584] ; (8002558 <mymain+0x378>)
800230e: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=((countdown/100)%10);
8002310: 4b92 ldr r3, [pc, #584] ; (800255c <mymain+0x37c>)
8002312: 681b ldr r3, [r3, #0]
8002314: 2164 movs r1, #100 ; 0x64
8002316: 0018 movs r0, r3
8002318: f7fd ff80 bl 800021c <__divsi3>
800231c: 0003 movs r3, r0
800231e: 210a movs r1, #10
8002320: 0018 movs r0, r3
8002322: f7fe f861 bl 80003e8 <__aeabi_idivmod>
8002326: 000b movs r3, r1
8002328: b2da uxtb r2, r3
800232a: 4b8b ldr r3, [pc, #556] ; (8002558 <mymain+0x378>)
800232c: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=((countdown/100)%10);
800232e: 4b8b ldr r3, [pc, #556] ; (800255c <mymain+0x37c>)
8002330: 681b ldr r3, [r3, #0]
8002332: 2164 movs r1, #100 ; 0x64
8002334: 0018 movs r0, r3
8002336: f7fd ff71 bl 800021c <__divsi3>
800233a: 0003 movs r3, r0
800233c: 210a movs r1, #10
800233e: 0018 movs r0, r3
8002340: f7fe f852 bl 80003e8 <__aeabi_idivmod>
8002344: 000b movs r3, r1
8002346: b2da uxtb r2, r3
8002348: 4b83 ldr r3, [pc, #524] ; (8002558 <mymain+0x378>)
800234a: 70da strb r2, [r3, #3]
dis_buff.led_err=countdown>>0;
800234c: 4b83 ldr r3, [pc, #524] ; (800255c <mymain+0x37c>)
800234e: 681b ldr r3, [r3, #0]
8002350: 1c1a adds r2, r3, #0
8002352: 2301 movs r3, #1
8002354: 4013 ands r3, r2
8002356: b2da uxtb r2, r3
8002358: 4b7f ldr r3, [pc, #508] ; (8002558 <mymain+0x378>)
800235a: 01d0 lsls r0, r2, #7
800235c: 791a ldrb r2, [r3, #4]
800235e: 217f movs r1, #127 ; 0x7f
8002360: 400a ands r2, r1
8002362: 1c11 adds r1, r2, #0
8002364: 1c02 adds r2, r0, #0
8002366: 430a orrs r2, r1
8002368: 711a strb r2, [r3, #4]
dis_buff.led_p=countdown>>1;
800236a: 4b7c ldr r3, [pc, #496] ; (800255c <mymain+0x37c>)
800236c: 681b ldr r3, [r3, #0]
800236e: 105b asrs r3, r3, #1
8002370: 1c1a adds r2, r3, #0
8002372: 2301 movs r3, #1
8002374: 4013 ands r3, r2
8002376: b2da uxtb r2, r3
8002378: 4b77 ldr r3, [pc, #476] ; (8002558 <mymain+0x378>)
800237a: 2101 movs r1, #1
800237c: 400a ands r2, r1
800237e: 0150 lsls r0, r2, #5
8002380: 791a ldrb r2, [r3, #4]
8002382: 2120 movs r1, #32
8002384: 438a bics r2, r1
8002386: 1c11 adds r1, r2, #0
8002388: 1c02 adds r2, r0, #0
800238a: 430a orrs r2, r1
800238c: 711a strb r2, [r3, #4]
dis_buff.led_n=countdown>>2;
800238e: 4b73 ldr r3, [pc, #460] ; (800255c <mymain+0x37c>)
8002390: 681b ldr r3, [r3, #0]
8002392: 109b asrs r3, r3, #2
8002394: 1c1a adds r2, r3, #0
8002396: 2301 movs r3, #1
8002398: 4013 ands r3, r2
800239a: b2da uxtb r2, r3
800239c: 4b6e ldr r3, [pc, #440] ; (8002558 <mymain+0x378>)
800239e: 2101 movs r1, #1
80023a0: 400a ands r2, r1
80023a2: 0190 lsls r0, r2, #6
80023a4: 791a ldrb r2, [r3, #4]
80023a6: 2140 movs r1, #64 ; 0x40
80023a8: 438a bics r2, r1
80023aa: 1c11 adds r1, r2, #0
80023ac: 1c02 adds r2, r0, #0
80023ae: 430a orrs r2, r1
80023b0: 711a strb r2, [r3, #4]
dis_buff.dot1=countdown>>3;
80023b2: 4b6a ldr r3, [pc, #424] ; (800255c <mymain+0x37c>)
80023b4: 681b ldr r3, [r3, #0]
80023b6: 10db asrs r3, r3, #3
80023b8: 1c1a adds r2, r3, #0
80023ba: 2301 movs r3, #1
80023bc: 4013 ands r3, r2
80023be: b2da uxtb r2, r3
80023c0: 4b65 ldr r3, [pc, #404] ; (8002558 <mymain+0x378>)
80023c2: 2101 movs r1, #1
80023c4: 400a ands r2, r1
80023c6: 0010 movs r0, r2
80023c8: 791a ldrb r2, [r3, #4]
80023ca: 2101 movs r1, #1
80023cc: 438a bics r2, r1
80023ce: 1c11 adds r1, r2, #0
80023d0: 1c02 adds r2, r0, #0
80023d2: 430a orrs r2, r1
80023d4: 711a strb r2, [r3, #4]
dis_buff.dot2=countdown>>4;
80023d6: 4b61 ldr r3, [pc, #388] ; (800255c <mymain+0x37c>)
80023d8: 681b ldr r3, [r3, #0]
80023da: 111b asrs r3, r3, #4
80023dc: 1c1a adds r2, r3, #0
80023de: 2301 movs r3, #1
80023e0: 4013 ands r3, r2
80023e2: b2da uxtb r2, r3
80023e4: 4b5c ldr r3, [pc, #368] ; (8002558 <mymain+0x378>)
80023e6: 2101 movs r1, #1
80023e8: 400a ands r2, r1
80023ea: 1890 adds r0, r2, r2
80023ec: 791a ldrb r2, [r3, #4]
80023ee: 2102 movs r1, #2
80023f0: 438a bics r2, r1
80023f2: 1c11 adds r1, r2, #0
80023f4: 1c02 adds r2, r0, #0
80023f6: 430a orrs r2, r1
80023f8: 711a strb r2, [r3, #4]
dis_buff.dot3=countdown>>5;
80023fa: 4b58 ldr r3, [pc, #352] ; (800255c <mymain+0x37c>)
80023fc: 681b ldr r3, [r3, #0]
80023fe: 115b asrs r3, r3, #5
8002400: 1c1a adds r2, r3, #0
8002402: 2301 movs r3, #1
8002404: 4013 ands r3, r2
8002406: b2da uxtb r2, r3
8002408: 4b53 ldr r3, [pc, #332] ; (8002558 <mymain+0x378>)
800240a: 2101 movs r1, #1
800240c: 400a ands r2, r1
800240e: 0090 lsls r0, r2, #2
8002410: 791a ldrb r2, [r3, #4]
8002412: 2104 movs r1, #4
8002414: 438a bics r2, r1
8002416: 1c11 adds r1, r2, #0
8002418: 1c02 adds r2, r0, #0
800241a: 430a orrs r2, r1
800241c: 711a strb r2, [r3, #4]
dis_buff.dot4=countdown>>6;
800241e: 4b4f ldr r3, [pc, #316] ; (800255c <mymain+0x37c>)
8002420: 681b ldr r3, [r3, #0]
8002422: 119b asrs r3, r3, #6
8002424: 1c1a adds r2, r3, #0
8002426: 2301 movs r3, #1
8002428: 4013 ands r3, r2
800242a: b2da uxtb r2, r3
800242c: 4b4a ldr r3, [pc, #296] ; (8002558 <mymain+0x378>)
800242e: 2101 movs r1, #1
8002430: 400a ands r2, r1
8002432: 00d0 lsls r0, r2, #3
8002434: 791a ldrb r2, [r3, #4]
8002436: 2108 movs r1, #8
8002438: 438a bics r2, r1
800243a: 1c11 adds r1, r2, #0
800243c: 1c02 adds r2, r0, #0
800243e: 430a orrs r2, r1
8002440: 711a strb r2, [r3, #4]
}
break;
8002442: e30f b.n 8002a64 <mymain+0x884>
case 1:
//standby
MOTA(0);
8002444: 4b43 ldr r3, [pc, #268] ; (8002554 <mymain+0x374>)
8002446: 2200 movs r2, #0
8002448: 2101 movs r1, #1
800244a: 0018 movs r0, r3
800244c: f7ff f873 bl 8001536 <HAL_GPIO_WritePin>
MOTB(0);
8002450: 4b40 ldr r3, [pc, #256] ; (8002554 <mymain+0x374>)
8002452: 2200 movs r2, #0
8002454: 2102 movs r1, #2
8002456: 0018 movs r0, r3
8002458: f7ff f86d bl 8001536 <HAL_GPIO_WritePin>
dis_buff.d_num[0]=0xff;
800245c: 4b3e ldr r3, [pc, #248] ; (8002558 <mymain+0x378>)
800245e: 22ff movs r2, #255 ; 0xff
8002460: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=0xff;
8002462: 4b3d ldr r3, [pc, #244] ; (8002558 <mymain+0x378>)
8002464: 22ff movs r2, #255 ; 0xff
8002466: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=0xff;
8002468: 4b3b ldr r3, [pc, #236] ; (8002558 <mymain+0x378>)
800246a: 22ff movs r2, #255 ; 0xff
800246c: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=0xff;
800246e: 4b3a ldr r3, [pc, #232] ; (8002558 <mymain+0x378>)
8002470: 22ff movs r2, #255 ; 0xff
8002472: 70da strb r2, [r3, #3]
dis_buff.led_err=0;
8002474: 4b38 ldr r3, [pc, #224] ; (8002558 <mymain+0x378>)
8002476: 791a ldrb r2, [r3, #4]
8002478: 217f movs r1, #127 ; 0x7f
800247a: 400a ands r2, r1
800247c: 711a strb r2, [r3, #4]
dis_buff.led_p=0;
800247e: 4b36 ldr r3, [pc, #216] ; (8002558 <mymain+0x378>)
8002480: 791a ldrb r2, [r3, #4]
8002482: 2120 movs r1, #32
8002484: 438a bics r2, r1
8002486: 711a strb r2, [r3, #4]
dis_buff.led_n=0;
8002488: 4b33 ldr r3, [pc, #204] ; (8002558 <mymain+0x378>)
800248a: 791a ldrb r2, [r3, #4]
800248c: 2140 movs r1, #64 ; 0x40
800248e: 438a bics r2, r1
8002490: 711a strb r2, [r3, #4]
dis_buff.dot1=0;
8002492: 4b31 ldr r3, [pc, #196] ; (8002558 <mymain+0x378>)
8002494: 791a ldrb r2, [r3, #4]
8002496: 2101 movs r1, #1
8002498: 438a bics r2, r1
800249a: 711a strb r2, [r3, #4]
dis_buff.dot2=0;
800249c: 4b2e ldr r3, [pc, #184] ; (8002558 <mymain+0x378>)
800249e: 791a ldrb r2, [r3, #4]
80024a0: 2102 movs r1, #2
80024a2: 438a bics r2, r1
80024a4: 711a strb r2, [r3, #4]
dis_buff.dot3=0;
80024a6: 4b2c ldr r3, [pc, #176] ; (8002558 <mymain+0x378>)
80024a8: 791a ldrb r2, [r3, #4]
80024aa: 2104 movs r1, #4
80024ac: 438a bics r2, r1
80024ae: 711a strb r2, [r3, #4]
dis_buff.dot4=0;
80024b0: 4b29 ldr r3, [pc, #164] ; (8002558 <mymain+0x378>)
80024b2: 791a ldrb r2, [r3, #4]
80024b4: 2108 movs r1, #8
80024b6: 438a bics r2, r1
80024b8: 711a strb r2, [r3, #4]
overload_times=0;
80024ba: 1cbb adds r3, r7, #2
80024bc: 2200 movs r2, #0
80024be: 801a strh r2, [r3, #0]
if(key2.code!=0)
80024c0: 4b29 ldr r3, [pc, #164] ; (8002568 <mymain+0x388>)
80024c2: 681b ldr r3, [r3, #0]
80024c4: 2b00 cmp r3, #0
80024c6: d007 beq.n 80024d8 <mymain+0x2f8>
{
mode=2;
80024c8: 230f movs r3, #15
80024ca: 18fb adds r3, r7, r3
80024cc: 2202 movs r2, #2
80024ce: 701a strb r2, [r3, #0]
countdown=countdown_set;
80024d0: 4b26 ldr r3, [pc, #152] ; (800256c <mymain+0x38c>)
80024d2: 681a ldr r2, [r3, #0]
80024d4: 4b21 ldr r3, [pc, #132] ; (800255c <mymain+0x37c>)
80024d6: 601a str r2, [r3, #0]
}
if(key3.code!=0)
80024d8: 4b25 ldr r3, [pc, #148] ; (8002570 <mymain+0x390>)
80024da: 681b ldr r3, [r3, #0]
80024dc: 2b00 cmp r3, #0
80024de: d007 beq.n 80024f0 <mymain+0x310>
{
mode=3;
80024e0: 230f movs r3, #15
80024e2: 18fb adds r3, r7, r3
80024e4: 2203 movs r2, #3
80024e6: 701a strb r2, [r3, #0]
countdown=countdown_set;
80024e8: 4b20 ldr r3, [pc, #128] ; (800256c <mymain+0x38c>)
80024ea: 681a ldr r2, [r3, #0]
80024ec: 4b1b ldr r3, [pc, #108] ; (800255c <mymain+0x37c>)
80024ee: 601a str r2, [r3, #0]
}
if(key1.code!=0)
80024f0: 4b20 ldr r3, [pc, #128] ; (8002574 <mymain+0x394>)
80024f2: 681b ldr r3, [r3, #0]
80024f4: 2b00 cmp r3, #0
80024f6: d100 bne.n 80024fa <mymain+0x31a>
80024f8: e2b6 b.n 8002a68 <mymain+0x888>
{
mode=4;
80024fa: 230f movs r3, #15
80024fc: 18fb adds r3, r7, r3
80024fe: 2204 movs r2, #4
8002500: 701a strb r2, [r3, #0]
countdown=10000;
8002502: 4b16 ldr r3, [pc, #88] ; (800255c <mymain+0x37c>)
8002504: 4a1c ldr r2, [pc, #112] ; (8002578 <mymain+0x398>)
8002506: 601a str r2, [r3, #0]
}
break;
8002508: e2ae b.n 8002a68 <mymain+0x888>
case 2:
MOTA(0);
800250a: 4b12 ldr r3, [pc, #72] ; (8002554 <mymain+0x374>)
800250c: 2200 movs r2, #0
800250e: 2101 movs r1, #1
8002510: 0018 movs r0, r3
8002512: f7ff f810 bl 8001536 <HAL_GPIO_WritePin>
MOTB(1);
8002516: 4b0f ldr r3, [pc, #60] ; (8002554 <mymain+0x374>)
8002518: 2201 movs r2, #1
800251a: 2102 movs r1, #2
800251c: 0018 movs r0, r3
800251e: f7ff f80a bl 8001536 <HAL_GPIO_WritePin>
if(HAL_GetTick()>move)
8002522: f7fe f9a5 bl 8000870 <HAL_GetTick>
8002526: 0002 movs r2, r0
8002528: 693b ldr r3, [r7, #16]
800252a: 4293 cmp r3, r2
800252c: d239 bcs.n 80025a2 <mymain+0x3c2>
{
move=HAL_GetTick()+100;
800252e: f7fe f99f bl 8000870 <HAL_GetTick>
8002532: 0003 movs r3, r0
8002534: 3364 adds r3, #100 ; 0x64
8002536: 613b str r3, [r7, #16]
if(dis_buff.led_p==1)
8002538: 4b07 ldr r3, [pc, #28] ; (8002558 <mymain+0x378>)
800253a: 791b ldrb r3, [r3, #4]
800253c: 2220 movs r2, #32
800253e: 4013 ands r3, r2
8002540: b2db uxtb r3, r3
8002542: 2b00 cmp r3, #0
8002544: d01a beq.n 800257c <mymain+0x39c>
{
dis_buff.led_p=0;
8002546: 4b04 ldr r3, [pc, #16] ; (8002558 <mymain+0x378>)
8002548: 791a ldrb r2, [r3, #4]
800254a: 2120 movs r1, #32
800254c: 438a bics r2, r1
800254e: 711a strb r2, [r3, #4]
8002550: e019 b.n 8002586 <mymain+0x3a6>
8002552: 46c0 nop ; (mov r8, r8)
8002554: 48001400 .word 0x48001400
8002558: 20000084 .word 0x20000084
800255c: 2000002c .word 0x2000002c
8002560: 08002c80 .word 0x08002c80
8002564: 20000030 .word 0x20000030
8002568: 200000bc .word 0x200000bc
800256c: 2000000c .word 0x2000000c
8002570: 200000ac .word 0x200000ac
8002574: 2000008c .word 0x2000008c
8002578: 00002710 .word 0x00002710
}else
{
dis_buff.led_p=1;
800257c: 4ba0 ldr r3, [pc, #640] ; (8002800 <mymain+0x620>)
800257e: 791a ldrb r2, [r3, #4]
8002580: 2120 movs r1, #32
8002582: 430a orrs r2, r1
8002584: 711a strb r2, [r3, #4]
}
countdown-=100;
8002586: 4b9f ldr r3, [pc, #636] ; (8002804 <mymain+0x624>)
8002588: 681b ldr r3, [r3, #0]
800258a: 3b64 subs r3, #100 ; 0x64
800258c: 001a movs r2, r3
800258e: 4b9d ldr r3, [pc, #628] ; (8002804 <mymain+0x624>)
8002590: 601a str r2, [r3, #0]
if(countdown<0)
8002592: 4b9c ldr r3, [pc, #624] ; (8002804 <mymain+0x624>)
8002594: 681b ldr r3, [r3, #0]
8002596: 2b00 cmp r3, #0
8002598: da03 bge.n 80025a2 <mymain+0x3c2>
{
mode=1;
800259a: 230f movs r3, #15
800259c: 18fb adds r3, r7, r3
800259e: 2201 movs r2, #1
80025a0: 701a strb r2, [r3, #0]
}
}
dis_buff.d_num[3]=(countdown/100)%10;
80025a2: 4b98 ldr r3, [pc, #608] ; (8002804 <mymain+0x624>)
80025a4: 681b ldr r3, [r3, #0]
80025a6: 2164 movs r1, #100 ; 0x64
80025a8: 0018 movs r0, r3
80025aa: f7fd fe37 bl 800021c <__divsi3>
80025ae: 0003 movs r3, r0
80025b0: 210a movs r1, #10
80025b2: 0018 movs r0, r3
80025b4: f7fd ff18 bl 80003e8 <__aeabi_idivmod>
80025b8: 000b movs r3, r1
80025ba: b2da uxtb r2, r3
80025bc: 4b90 ldr r3, [pc, #576] ; (8002800 <mymain+0x620>)
80025be: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown/1000)%10;
80025c0: 4b90 ldr r3, [pc, #576] ; (8002804 <mymain+0x624>)
80025c2: 681b ldr r3, [r3, #0]
80025c4: 22fa movs r2, #250 ; 0xfa
80025c6: 0091 lsls r1, r2, #2
80025c8: 0018 movs r0, r3
80025ca: f7fd fe27 bl 800021c <__divsi3>
80025ce: 0003 movs r3, r0
80025d0: 210a movs r1, #10
80025d2: 0018 movs r0, r3
80025d4: f7fd ff08 bl 80003e8 <__aeabi_idivmod>
80025d8: 000b movs r3, r1
80025da: b2da uxtb r2, r3
80025dc: 4b88 ldr r3, [pc, #544] ; (8002800 <mymain+0x620>)
80025de: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown/10000)%10);
80025e0: 4b88 ldr r3, [pc, #544] ; (8002804 <mymain+0x624>)
80025e2: 681b ldr r3, [r3, #0]
80025e4: 4988 ldr r1, [pc, #544] ; (8002808 <mymain+0x628>)
80025e6: 0018 movs r0, r3
80025e8: f7fd fe18 bl 800021c <__divsi3>
80025ec: 0003 movs r3, r0
80025ee: 210a movs r1, #10
80025f0: 0018 movs r0, r3
80025f2: f7fd fef9 bl 80003e8 <__aeabi_idivmod>
80025f6: 000b movs r3, r1
80025f8: b2da uxtb r2, r3
80025fa: 4b81 ldr r3, [pc, #516] ; (8002800 <mymain+0x620>)
80025fc: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1];
80025fe: 4b80 ldr r3, [pc, #512] ; (8002800 <mymain+0x620>)
8002600: 785b ldrb r3, [r3, #1]
8002602: 2b00 cmp r3, #0
8002604: d002 beq.n 800260c <mymain+0x42c>
8002606: 4b7e ldr r3, [pc, #504] ; (8002800 <mymain+0x620>)
8002608: 785a ldrb r2, [r3, #1]
800260a: e000 b.n 800260e <mymain+0x42e>
800260c: 22ff movs r2, #255 ; 0xff
800260e: 4b7c ldr r3, [pc, #496] ; (8002800 <mymain+0x620>)
8002610: 705a strb r2, [r3, #1]
dis_buff.dot3=1;
8002612: 4b7b ldr r3, [pc, #492] ; (8002800 <mymain+0x620>)
8002614: 791a ldrb r2, [r3, #4]
8002616: 2104 movs r1, #4
8002618: 430a orrs r2, r1
800261a: 711a strb r2, [r3, #4]
dis_buff.led_n=0;
800261c: 4b78 ldr r3, [pc, #480] ; (8002800 <mymain+0x620>)
800261e: 791a ldrb r2, [r3, #4]
8002620: 2140 movs r1, #64 ; 0x40
8002622: 438a bics r2, r1
8002624: 711a strb r2, [r3, #4]
if(key3.code!=0)
8002626: 4b79 ldr r3, [pc, #484] ; (800280c <mymain+0x62c>)
8002628: 681b ldr r3, [r3, #0]
800262a: 2b00 cmp r3, #0
800262c: d00a beq.n 8002644 <mymain+0x464>
{
mode=3;
800262e: 230f movs r3, #15
8002630: 18fb adds r3, r7, r3
8002632: 2203 movs r2, #3
8002634: 701a strb r2, [r3, #0]
countdown=countdown_set-countdown;
8002636: 4b76 ldr r3, [pc, #472] ; (8002810 <mymain+0x630>)
8002638: 681a ldr r2, [r3, #0]
800263a: 4b72 ldr r3, [pc, #456] ; (8002804 <mymain+0x624>)
800263c: 681b ldr r3, [r3, #0]
800263e: 1ad2 subs r2, r2, r3
8002640: 4b70 ldr r3, [pc, #448] ; (8002804 <mymain+0x624>)
8002642: 601a str r2, [r3, #0]
}
if(key4.code<0)
8002644: 4b73 ldr r3, [pc, #460] ; (8002814 <mymain+0x634>)
8002646: 681b ldr r3, [r3, #0]
8002648: 2b00 cmp r3, #0
800264a: da03 bge.n 8002654 <mymain+0x474>
{
mode=1;
800264c: 230f movs r3, #15
800264e: 18fb adds r3, r7, r3
8002650: 2201 movs r2, #1
8002652: 701a strb r2, [r3, #0]
}
if(overload.code!=0)
8002654: 4b70 ldr r3, [pc, #448] ; (8002818 <mymain+0x638>)
8002656: 681b ldr r3, [r3, #0]
8002658: 2b00 cmp r3, #0
800265a: d004 beq.n 8002666 <mymain+0x486>
{
overload_times+=1;
800265c: 1cbb adds r3, r7, #2
800265e: 1cba adds r2, r7, #2
8002660: 8812 ldrh r2, [r2, #0]
8002662: 3201 adds r2, #1
8002664: 801a strh r2, [r3, #0]
}
if(overload_times>2)
8002666: 1cbb adds r3, r7, #2
8002668: 881b ldrh r3, [r3, #0]
800266a: 2b02 cmp r3, #2
800266c: d800 bhi.n 8002670 <mymain+0x490>
800266e: e1fd b.n 8002a6c <mymain+0x88c>
{
overload_mode=2;
8002670: 230e movs r3, #14
8002672: 18fb adds r3, r7, r3
8002674: 2202 movs r2, #2
8002676: 701a strb r2, [r3, #0]
mode=5;
8002678: 230f movs r3, #15
800267a: 18fb adds r3, r7, r3
800267c: 2205 movs r2, #5
800267e: 701a strb r2, [r3, #0]
}
break;
8002680: e1f4 b.n 8002a6c <mymain+0x88c>
case 3:
MOTB(0);
8002682: 4b66 ldr r3, [pc, #408] ; (800281c <mymain+0x63c>)
8002684: 2200 movs r2, #0
8002686: 2102 movs r1, #2
8002688: 0018 movs r0, r3
800268a: f7fe ff54 bl 8001536 <HAL_GPIO_WritePin>
MOTA(1);
800268e: 4b63 ldr r3, [pc, #396] ; (800281c <mymain+0x63c>)
8002690: 2201 movs r2, #1
8002692: 2101 movs r1, #1
8002694: 0018 movs r0, r3
8002696: f7fe ff4e bl 8001536 <HAL_GPIO_WritePin>
if(HAL_GetTick()>move)
800269a: f7fe f8e9 bl 8000870 <HAL_GetTick>
800269e: 0002 movs r2, r0
80026a0: 693b ldr r3, [r7, #16]
80026a2: 4293 cmp r3, r2
80026a4: d224 bcs.n 80026f0 <mymain+0x510>
{
move=HAL_GetTick()+100;
80026a6: f7fe f8e3 bl 8000870 <HAL_GetTick>
80026aa: 0003 movs r3, r0
80026ac: 3364 adds r3, #100 ; 0x64
80026ae: 613b str r3, [r7, #16]
if(dis_buff.led_n==1)
80026b0: 4b53 ldr r3, [pc, #332] ; (8002800 <mymain+0x620>)
80026b2: 791b ldrb r3, [r3, #4]
80026b4: 2240 movs r2, #64 ; 0x40
80026b6: 4013 ands r3, r2
80026b8: b2db uxtb r3, r3
80026ba: 2b00 cmp r3, #0
80026bc: d005 beq.n 80026ca <mymain+0x4ea>
{
dis_buff.led_n=0;
80026be: 4b50 ldr r3, [pc, #320] ; (8002800 <mymain+0x620>)
80026c0: 791a ldrb r2, [r3, #4]
80026c2: 2140 movs r1, #64 ; 0x40
80026c4: 438a bics r2, r1
80026c6: 711a strb r2, [r3, #4]
80026c8: e004 b.n 80026d4 <mymain+0x4f4>
}else
{
dis_buff.led_n=1;
80026ca: 4b4d ldr r3, [pc, #308] ; (8002800 <mymain+0x620>)
80026cc: 791a ldrb r2, [r3, #4]
80026ce: 2140 movs r1, #64 ; 0x40
80026d0: 430a orrs r2, r1
80026d2: 711a strb r2, [r3, #4]
}
countdown-=100;
80026d4: 4b4b ldr r3, [pc, #300] ; (8002804 <mymain+0x624>)
80026d6: 681b ldr r3, [r3, #0]
80026d8: 3b64 subs r3, #100 ; 0x64
80026da: 001a movs r2, r3
80026dc: 4b49 ldr r3, [pc, #292] ; (8002804 <mymain+0x624>)
80026de: 601a str r2, [r3, #0]
if(countdown<0)
80026e0: 4b48 ldr r3, [pc, #288] ; (8002804 <mymain+0x624>)
80026e2: 681b ldr r3, [r3, #0]
80026e4: 2b00 cmp r3, #0
80026e6: da03 bge.n 80026f0 <mymain+0x510>
{
mode=1;
80026e8: 230f movs r3, #15
80026ea: 18fb adds r3, r7, r3
80026ec: 2201 movs r2, #1
80026ee: 701a strb r2, [r3, #0]
}
}
dis_buff.d_num[3]=(countdown/100)%10;
80026f0: 4b44 ldr r3, [pc, #272] ; (8002804 <mymain+0x624>)
80026f2: 681b ldr r3, [r3, #0]
80026f4: 2164 movs r1, #100 ; 0x64
80026f6: 0018 movs r0, r3
80026f8: f7fd fd90 bl 800021c <__divsi3>
80026fc: 0003 movs r3, r0
80026fe: 210a movs r1, #10
8002700: 0018 movs r0, r3
8002702: f7fd fe71 bl 80003e8 <__aeabi_idivmod>
8002706: 000b movs r3, r1
8002708: b2da uxtb r2, r3
800270a: 4b3d ldr r3, [pc, #244] ; (8002800 <mymain+0x620>)
800270c: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown/1000)%10;
800270e: 4b3d ldr r3, [pc, #244] ; (8002804 <mymain+0x624>)
8002710: 681b ldr r3, [r3, #0]
8002712: 22fa movs r2, #250 ; 0xfa
8002714: 0091 lsls r1, r2, #2
8002716: 0018 movs r0, r3
8002718: f7fd fd80 bl 800021c <__divsi3>
800271c: 0003 movs r3, r0
800271e: 210a movs r1, #10
8002720: 0018 movs r0, r3
8002722: f7fd fe61 bl 80003e8 <__aeabi_idivmod>
8002726: 000b movs r3, r1
8002728: b2da uxtb r2, r3
800272a: 4b35 ldr r3, [pc, #212] ; (8002800 <mymain+0x620>)
800272c: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown/10000)%10);
800272e: 4b35 ldr r3, [pc, #212] ; (8002804 <mymain+0x624>)
8002730: 681b ldr r3, [r3, #0]
8002732: 4935 ldr r1, [pc, #212] ; (8002808 <mymain+0x628>)
8002734: 0018 movs r0, r3
8002736: f7fd fd71 bl 800021c <__divsi3>
800273a: 0003 movs r3, r0
800273c: 210a movs r1, #10
800273e: 0018 movs r0, r3
8002740: f7fd fe52 bl 80003e8 <__aeabi_idivmod>
8002744: 000b movs r3, r1
8002746: b2da uxtb r2, r3
8002748: 4b2d ldr r3, [pc, #180] ; (8002800 <mymain+0x620>)
800274a: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1];
800274c: 4b2c ldr r3, [pc, #176] ; (8002800 <mymain+0x620>)
800274e: 785b ldrb r3, [r3, #1]
8002750: 2b00 cmp r3, #0
8002752: d002 beq.n 800275a <mymain+0x57a>
8002754: 4b2a ldr r3, [pc, #168] ; (8002800 <mymain+0x620>)
8002756: 785a ldrb r2, [r3, #1]
8002758: e000 b.n 800275c <mymain+0x57c>
800275a: 22ff movs r2, #255 ; 0xff
800275c: 4b28 ldr r3, [pc, #160] ; (8002800 <mymain+0x620>)
800275e: 705a strb r2, [r3, #1]
dis_buff.dot3=1;
8002760: 4b27 ldr r3, [pc, #156] ; (8002800 <mymain+0x620>)
8002762: 791a ldrb r2, [r3, #4]
8002764: 2104 movs r1, #4
8002766: 430a orrs r2, r1
8002768: 711a strb r2, [r3, #4]
dis_buff.led_p=0;
800276a: 4b25 ldr r3, [pc, #148] ; (8002800 <mymain+0x620>)
800276c: 791a ldrb r2, [r3, #4]
800276e: 2120 movs r1, #32
8002770: 438a bics r2, r1
8002772: 711a strb r2, [r3, #4]
if(key2.code!=0)
8002774: 4b2a ldr r3, [pc, #168] ; (8002820 <mymain+0x640>)
8002776: 681b ldr r3, [r3, #0]
8002778: 2b00 cmp r3, #0
800277a: d00a beq.n 8002792 <mymain+0x5b2>
{
mode=2;
800277c: 230f movs r3, #15
800277e: 18fb adds r3, r7, r3
8002780: 2202 movs r2, #2
8002782: 701a strb r2, [r3, #0]
countdown=countdown_set-countdown;
8002784: 4b22 ldr r3, [pc, #136] ; (8002810 <mymain+0x630>)
8002786: 681a ldr r2, [r3, #0]
8002788: 4b1e ldr r3, [pc, #120] ; (8002804 <mymain+0x624>)
800278a: 681b ldr r3, [r3, #0]
800278c: 1ad2 subs r2, r2, r3
800278e: 4b1d ldr r3, [pc, #116] ; (8002804 <mymain+0x624>)
8002790: 601a str r2, [r3, #0]
}
if(key4.code<0)
8002792: 4b20 ldr r3, [pc, #128] ; (8002814 <mymain+0x634>)
8002794: 681b ldr r3, [r3, #0]
8002796: 2b00 cmp r3, #0
8002798: da03 bge.n 80027a2 <mymain+0x5c2>
{
mode=1;
800279a: 230f movs r3, #15
800279c: 18fb adds r3, r7, r3
800279e: 2201 movs r2, #1
80027a0: 701a strb r2, [r3, #0]
}
if(overload.code!=0)
80027a2: 4b1d ldr r3, [pc, #116] ; (8002818 <mymain+0x638>)
80027a4: 681b ldr r3, [r3, #0]
80027a6: 2b00 cmp r3, #0
80027a8: d004 beq.n 80027b4 <mymain+0x5d4>
{
overload_times+=1;
80027aa: 1cbb adds r3, r7, #2
80027ac: 1cba adds r2, r7, #2
80027ae: 8812 ldrh r2, [r2, #0]
80027b0: 3201 adds r2, #1
80027b2: 801a strh r2, [r3, #0]
}
if(overload_times>2)
80027b4: 1cbb adds r3, r7, #2
80027b6: 881b ldrh r3, [r3, #0]
80027b8: 2b02 cmp r3, #2
80027ba: d800 bhi.n 80027be <mymain+0x5de>
80027bc: e158 b.n 8002a70 <mymain+0x890>
{
overload_mode=3;
80027be: 230e movs r3, #14
80027c0: 18fb adds r3, r7, r3
80027c2: 2203 movs r2, #3
80027c4: 701a strb r2, [r3, #0]
mode=5;
80027c6: 230f movs r3, #15
80027c8: 18fb adds r3, r7, r3
80027ca: 2205 movs r2, #5
80027cc: 701a strb r2, [r3, #0]
}
break;
80027ce: e14f b.n 8002a70 <mymain+0x890>
case 4:
//setting mode
if(HAL_GetTick()>move)
80027d0: f7fe f84e bl 8000870 <HAL_GetTick>
80027d4: 0002 movs r2, r0
80027d6: 693b ldr r3, [r7, #16]
80027d8: 4293 cmp r3, r2
80027da: d251 bcs.n 8002880 <mymain+0x6a0>
{
move=HAL_GetTick()+100;
80027dc: f7fe f848 bl 8000870 <HAL_GetTick>
80027e0: 0003 movs r3, r0
80027e2: 3364 adds r3, #100 ; 0x64
80027e4: 613b str r3, [r7, #16]
if(dis_buff.dot1==1)
80027e6: 4b06 ldr r3, [pc, #24] ; (8002800 <mymain+0x620>)
80027e8: 791b ldrb r3, [r3, #4]
80027ea: 2201 movs r2, #1
80027ec: 4013 ands r3, r2
80027ee: b2db uxtb r3, r3
80027f0: 2b00 cmp r3, #0
80027f2: d017 beq.n 8002824 <mymain+0x644>
{
dis_buff.dot1=0;
80027f4: 4b02 ldr r3, [pc, #8] ; (8002800 <mymain+0x620>)
80027f6: 791a ldrb r2, [r3, #4]
80027f8: 2101 movs r1, #1
80027fa: 438a bics r2, r1
80027fc: 711a strb r2, [r3, #4]
80027fe: e016 b.n 800282e <mymain+0x64e>
8002800: 20000084 .word 0x20000084
8002804: 2000002c .word 0x2000002c
8002808: 00002710 .word 0x00002710
800280c: 200000ac .word 0x200000ac
8002810: 2000000c .word 0x2000000c
8002814: 20000074 .word 0x20000074
8002818: 2000009c .word 0x2000009c
800281c: 48001400 .word 0x48001400
8002820: 200000bc .word 0x200000bc
}else
{
dis_buff.dot1=1;
8002824: 4bdc ldr r3, [pc, #880] ; (8002b98 <mymain+0x9b8>)
8002826: 791a ldrb r2, [r3, #4]
8002828: 2101 movs r1, #1
800282a: 430a orrs r2, r1
800282c: 711a strb r2, [r3, #4]
}
countdown-=100;
800282e: 4bdb ldr r3, [pc, #876] ; (8002b9c <mymain+0x9bc>)
8002830: 681b ldr r3, [r3, #0]
8002832: 3b64 subs r3, #100 ; 0x64
8002834: 001a movs r2, r3
8002836: 4bd9 ldr r3, [pc, #868] ; (8002b9c <mymain+0x9bc>)
8002838: 601a str r2, [r3, #0]
if(countdown<0)
800283a: 4bd8 ldr r3, [pc, #864] ; (8002b9c <mymain+0x9bc>)
800283c: 681b ldr r3, [r3, #0]
800283e: 2b00 cmp r3, #0
8002840: da03 bge.n 800284a <mymain+0x66a>
{
mode=1;
8002842: 230f movs r3, #15
8002844: 18fb adds r3, r7, r3
8002846: 2201 movs r2, #1
8002848: 701a strb r2, [r3, #0]
}
if(key2.code<0){countdown_set+=1000;countdown=10000;}
800284a: 4bd5 ldr r3, [pc, #852] ; (8002ba0 <mymain+0x9c0>)
800284c: 681b ldr r3, [r3, #0]
800284e: 2b00 cmp r3, #0
8002850: da09 bge.n 8002866 <mymain+0x686>
8002852: 4bd4 ldr r3, [pc, #848] ; (8002ba4 <mymain+0x9c4>)
8002854: 681b ldr r3, [r3, #0]
8002856: 22fa movs r2, #250 ; 0xfa
8002858: 0092 lsls r2, r2, #2
800285a: 189a adds r2, r3, r2
800285c: 4bd1 ldr r3, [pc, #836] ; (8002ba4 <mymain+0x9c4>)
800285e: 601a str r2, [r3, #0]
8002860: 4bce ldr r3, [pc, #824] ; (8002b9c <mymain+0x9bc>)
8002862: 4ad1 ldr r2, [pc, #836] ; (8002ba8 <mymain+0x9c8>)
8002864: 601a str r2, [r3, #0]
if(key3.code<0){countdown_set-=1000;countdown=10000;}
8002866: 4bd1 ldr r3, [pc, #836] ; (8002bac <mymain+0x9cc>)
8002868: 681b ldr r3, [r3, #0]
800286a: 2b00 cmp r3, #0
800286c: da08 bge.n 8002880 <mymain+0x6a0>
800286e: 4bcd ldr r3, [pc, #820] ; (8002ba4 <mymain+0x9c4>)
8002870: 681b ldr r3, [r3, #0]
8002872: 4acf ldr r2, [pc, #828] ; (8002bb0 <mymain+0x9d0>)
8002874: 189a adds r2, r3, r2
8002876: 4bcb ldr r3, [pc, #812] ; (8002ba4 <mymain+0x9c4>)
8002878: 601a str r2, [r3, #0]
800287a: 4bc8 ldr r3, [pc, #800] ; (8002b9c <mymain+0x9bc>)
800287c: 4aca ldr r2, [pc, #808] ; (8002ba8 <mymain+0x9c8>)
800287e: 601a str r2, [r3, #0]
}
if(key2.code>0){countdown_set+=100;countdown=10000;}
8002880: 4bc7 ldr r3, [pc, #796] ; (8002ba0 <mymain+0x9c0>)
8002882: 681b ldr r3, [r3, #0]
8002884: 2b00 cmp r3, #0
8002886: dd08 ble.n 800289a <mymain+0x6ba>
8002888: 4bc6 ldr r3, [pc, #792] ; (8002ba4 <mymain+0x9c4>)
800288a: 681b ldr r3, [r3, #0]
800288c: 3364 adds r3, #100 ; 0x64
800288e: 001a movs r2, r3
8002890: 4bc4 ldr r3, [pc, #784] ; (8002ba4 <mymain+0x9c4>)
8002892: 601a str r2, [r3, #0]
8002894: 4bc1 ldr r3, [pc, #772] ; (8002b9c <mymain+0x9bc>)
8002896: 4ac4 ldr r2, [pc, #784] ; (8002ba8 <mymain+0x9c8>)
8002898: 601a str r2, [r3, #0]
if(key3.code>0){countdown_set-=100;countdown=10000;}
800289a: 4bc4 ldr r3, [pc, #784] ; (8002bac <mymain+0x9cc>)
800289c: 681b ldr r3, [r3, #0]
800289e: 2b00 cmp r3, #0
80028a0: dd08 ble.n 80028b4 <mymain+0x6d4>
80028a2: 4bc0 ldr r3, [pc, #768] ; (8002ba4 <mymain+0x9c4>)
80028a4: 681b ldr r3, [r3, #0]
80028a6: 3b64 subs r3, #100 ; 0x64
80028a8: 001a movs r2, r3
80028aa: 4bbe ldr r3, [pc, #760] ; (8002ba4 <mymain+0x9c4>)
80028ac: 601a str r2, [r3, #0]
80028ae: 4bbb ldr r3, [pc, #748] ; (8002b9c <mymain+0x9bc>)
80028b0: 4abd ldr r2, [pc, #756] ; (8002ba8 <mymain+0x9c8>)
80028b2: 601a str r2, [r3, #0]
if(countdown_set<100){countdown_set=100;}
80028b4: 4bbb ldr r3, [pc, #748] ; (8002ba4 <mymain+0x9c4>)
80028b6: 681b ldr r3, [r3, #0]
80028b8: 2b63 cmp r3, #99 ; 0x63
80028ba: dc02 bgt.n 80028c2 <mymain+0x6e2>
80028bc: 4bb9 ldr r3, [pc, #740] ; (8002ba4 <mymain+0x9c4>)
80028be: 2264 movs r2, #100 ; 0x64
80028c0: 601a str r2, [r3, #0]
if(countdown_set>60000){countdown_set=60000;}
80028c2: 4bb8 ldr r3, [pc, #736] ; (8002ba4 <mymain+0x9c4>)
80028c4: 681b ldr r3, [r3, #0]
80028c6: 4abb ldr r2, [pc, #748] ; (8002bb4 <mymain+0x9d4>)
80028c8: 4293 cmp r3, r2
80028ca: dd02 ble.n 80028d2 <mymain+0x6f2>
80028cc: 4bb5 ldr r3, [pc, #724] ; (8002ba4 <mymain+0x9c4>)
80028ce: 4ab9 ldr r2, [pc, #740] ; (8002bb4 <mymain+0x9d4>)
80028d0: 601a str r2, [r3, #0]
if(key1.code!=0){mode=1;}
80028d2: 4bb9 ldr r3, [pc, #740] ; (8002bb8 <mymain+0x9d8>)
80028d4: 681b ldr r3, [r3, #0]
80028d6: 2b00 cmp r3, #0
80028d8: d003 beq.n 80028e2 <mymain+0x702>
80028da: 230f movs r3, #15
80028dc: 18fb adds r3, r7, r3
80028de: 2201 movs r2, #1
80028e0: 701a strb r2, [r3, #0]
dis_buff.d_num[3]=(countdown_set/100)%10;
80028e2: 4bb0 ldr r3, [pc, #704] ; (8002ba4 <mymain+0x9c4>)
80028e4: 681b ldr r3, [r3, #0]
80028e6: 2164 movs r1, #100 ; 0x64
80028e8: 0018 movs r0, r3
80028ea: f7fd fc97 bl 800021c <__divsi3>
80028ee: 0003 movs r3, r0
80028f0: 210a movs r1, #10
80028f2: 0018 movs r0, r3
80028f4: f7fd fd78 bl 80003e8 <__aeabi_idivmod>
80028f8: 000b movs r3, r1
80028fa: b2da uxtb r2, r3
80028fc: 4ba6 ldr r3, [pc, #664] ; (8002b98 <mymain+0x9b8>)
80028fe: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown_set/1000)%10;
8002900: 4ba8 ldr r3, [pc, #672] ; (8002ba4 <mymain+0x9c4>)
8002902: 681b ldr r3, [r3, #0]
8002904: 22fa movs r2, #250 ; 0xfa
8002906: 0091 lsls r1, r2, #2
8002908: 0018 movs r0, r3
800290a: f7fd fc87 bl 800021c <__divsi3>
800290e: 0003 movs r3, r0
8002910: 210a movs r1, #10
8002912: 0018 movs r0, r3
8002914: f7fd fd68 bl 80003e8 <__aeabi_idivmod>
8002918: 000b movs r3, r1
800291a: b2da uxtb r2, r3
800291c: 4b9e ldr r3, [pc, #632] ; (8002b98 <mymain+0x9b8>)
800291e: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown_set/10000)%10);
8002920: 4ba0 ldr r3, [pc, #640] ; (8002ba4 <mymain+0x9c4>)
8002922: 681b ldr r3, [r3, #0]
8002924: 49a0 ldr r1, [pc, #640] ; (8002ba8 <mymain+0x9c8>)
8002926: 0018 movs r0, r3
8002928: f7fd fc78 bl 800021c <__divsi3>
800292c: 0003 movs r3, r0
800292e: 210a movs r1, #10
8002930: 0018 movs r0, r3
8002932: f7fd fd59 bl 80003e8 <__aeabi_idivmod>
8002936: 000b movs r3, r1
8002938: b2da uxtb r2, r3
800293a: 4b97 ldr r3, [pc, #604] ; (8002b98 <mymain+0x9b8>)
800293c: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1];
800293e: 4b96 ldr r3, [pc, #600] ; (8002b98 <mymain+0x9b8>)
8002940: 785b ldrb r3, [r3, #1]
8002942: 2b00 cmp r3, #0
8002944: d002 beq.n 800294c <mymain+0x76c>
8002946: 4b94 ldr r3, [pc, #592] ; (8002b98 <mymain+0x9b8>)
8002948: 785a ldrb r2, [r3, #1]
800294a: e000 b.n 800294e <mymain+0x76e>
800294c: 22ff movs r2, #255 ; 0xff
800294e: 4b92 ldr r3, [pc, #584] ; (8002b98 <mymain+0x9b8>)
8002950: 705a strb r2, [r3, #1]
dis_buff.dot3=1;
8002952: 4b91 ldr r3, [pc, #580] ; (8002b98 <mymain+0x9b8>)
8002954: 791a ldrb r2, [r3, #4]
8002956: 2104 movs r1, #4
8002958: 430a orrs r2, r1
800295a: 711a strb r2, [r3, #4]
break;
800295c: e08b b.n 8002a76 <mymain+0x896>
case 5:
//overload
MOTB(0);
800295e: 4b97 ldr r3, [pc, #604] ; (8002bbc <mymain+0x9dc>)
8002960: 2200 movs r2, #0
8002962: 2102 movs r1, #2
8002964: 0018 movs r0, r3
8002966: f7fe fde6 bl 8001536 <HAL_GPIO_WritePin>
MOTA(0);
800296a: 4b94 ldr r3, [pc, #592] ; (8002bbc <mymain+0x9dc>)
800296c: 2200 movs r2, #0
800296e: 2101 movs r1, #1
8002970: 0018 movs r0, r3
8002972: f7fe fde0 bl 8001536 <HAL_GPIO_WritePin>
overload_times=0;
8002976: 1cbb adds r3, r7, #2
8002978: 2200 movs r2, #0
800297a: 801a strh r2, [r3, #0]
dis_buff.d_num[3]=(countdown/100)%10;
800297c: 4b87 ldr r3, [pc, #540] ; (8002b9c <mymain+0x9bc>)
800297e: 681b ldr r3, [r3, #0]
8002980: 2164 movs r1, #100 ; 0x64
8002982: 0018 movs r0, r3
8002984: f7fd fc4a bl 800021c <__divsi3>
8002988: 0003 movs r3, r0
800298a: 210a movs r1, #10
800298c: 0018 movs r0, r3
800298e: f7fd fd2b bl 80003e8 <__aeabi_idivmod>
8002992: 000b movs r3, r1
8002994: b2da uxtb r2, r3
8002996: 4b80 ldr r3, [pc, #512] ; (8002b98 <mymain+0x9b8>)
8002998: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown/1000)%10;
800299a: 4b80 ldr r3, [pc, #512] ; (8002b9c <mymain+0x9bc>)
800299c: 681b ldr r3, [r3, #0]
800299e: 22fa movs r2, #250 ; 0xfa
80029a0: 0091 lsls r1, r2, #2
80029a2: 0018 movs r0, r3
80029a4: f7fd fc3a bl 800021c <__divsi3>
80029a8: 0003 movs r3, r0
80029aa: 210a movs r1, #10
80029ac: 0018 movs r0, r3
80029ae: f7fd fd1b bl 80003e8 <__aeabi_idivmod>
80029b2: 000b movs r3, r1
80029b4: b2da uxtb r2, r3
80029b6: 4b78 ldr r3, [pc, #480] ; (8002b98 <mymain+0x9b8>)
80029b8: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown/10000)%10);
80029ba: 4b78 ldr r3, [pc, #480] ; (8002b9c <mymain+0x9bc>)
80029bc: 681b ldr r3, [r3, #0]
80029be: 497a ldr r1, [pc, #488] ; (8002ba8 <mymain+0x9c8>)
80029c0: 0018 movs r0, r3
80029c2: f7fd fc2b bl 800021c <__divsi3>
80029c6: 0003 movs r3, r0
80029c8: 210a movs r1, #10
80029ca: 0018 movs r0, r3
80029cc: f7fd fd0c bl 80003e8 <__aeabi_idivmod>
80029d0: 000b movs r3, r1
80029d2: b2da uxtb r2, r3
80029d4: 4b70 ldr r3, [pc, #448] ; (8002b98 <mymain+0x9b8>)
80029d6: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?255:dis_buff.d_num[1];
80029d8: 4b6f ldr r3, [pc, #444] ; (8002b98 <mymain+0x9b8>)
80029da: 785b ldrb r3, [r3, #1]
80029dc: 2b00 cmp r3, #0
80029de: d002 beq.n 80029e6 <mymain+0x806>
80029e0: 4b6d ldr r3, [pc, #436] ; (8002b98 <mymain+0x9b8>)
80029e2: 785a ldrb r2, [r3, #1]
80029e4: e000 b.n 80029e8 <mymain+0x808>
80029e6: 22ff movs r2, #255 ; 0xff
80029e8: 4b6b ldr r3, [pc, #428] ; (8002b98 <mymain+0x9b8>)
80029ea: 705a strb r2, [r3, #1]
dis_buff.dot3=1;
80029ec: 4b6a ldr r3, [pc, #424] ; (8002b98 <mymain+0x9b8>)
80029ee: 791a ldrb r2, [r3, #4]
80029f0: 2104 movs r1, #4
80029f2: 430a orrs r2, r1
80029f4: 711a strb r2, [r3, #4]
dis_buff.led_err=1;
80029f6: 4b68 ldr r3, [pc, #416] ; (8002b98 <mymain+0x9b8>)
80029f8: 791a ldrb r2, [r3, #4]
80029fa: 2180 movs r1, #128 ; 0x80
80029fc: 4249 negs r1, r1
80029fe: 430a orrs r2, r1
8002a00: 711a strb r2, [r3, #4]
if(key4.code!=0){mode=1;}
8002a02: 4b6f ldr r3, [pc, #444] ; (8002bc0 <mymain+0x9e0>)
8002a04: 681b ldr r3, [r3, #0]
8002a06: 2b00 cmp r3, #0
8002a08: d003 beq.n 8002a12 <mymain+0x832>
8002a0a: 230f movs r3, #15
8002a0c: 18fb adds r3, r7, r3
8002a0e: 2201 movs r2, #1
8002a10: 701a strb r2, [r3, #0]
if(key2.code!=0)
8002a12: 4b63 ldr r3, [pc, #396] ; (8002ba0 <mymain+0x9c0>)
8002a14: 681b ldr r3, [r3, #0]
8002a16: 2b00 cmp r3, #0
8002a18: d00f beq.n 8002a3a <mymain+0x85a>
{
mode=2;
8002a1a: 230f movs r3, #15
8002a1c: 18fb adds r3, r7, r3
8002a1e: 2202 movs r2, #2
8002a20: 701a strb r2, [r3, #0]
if(overload_mode==2)
8002a22: 230e movs r3, #14
8002a24: 18fb adds r3, r7, r3
8002a26: 781b ldrb r3, [r3, #0]
8002a28: 2b02 cmp r3, #2
8002a2a: d006 beq.n 8002a3a <mymain+0x85a>
{
}else
{
countdown=countdown_set-countdown;
8002a2c: 4b5d ldr r3, [pc, #372] ; (8002ba4 <mymain+0x9c4>)
8002a2e: 681a ldr r2, [r3, #0]
8002a30: 4b5a ldr r3, [pc, #360] ; (8002b9c <mymain+0x9bc>)
8002a32: 681b ldr r3, [r3, #0]
8002a34: 1ad2 subs r2, r2, r3
8002a36: 4b59 ldr r3, [pc, #356] ; (8002b9c <mymain+0x9bc>)
8002a38: 601a str r2, [r3, #0]
}
}
if(key3.code!=0)
8002a3a: 4b5c ldr r3, [pc, #368] ; (8002bac <mymain+0x9cc>)
8002a3c: 681b ldr r3, [r3, #0]
8002a3e: 2b00 cmp r3, #0
8002a40: d018 beq.n 8002a74 <mymain+0x894>
{
mode=3;
8002a42: 230f movs r3, #15
8002a44: 18fb adds r3, r7, r3
8002a46: 2203 movs r2, #3
8002a48: 701a strb r2, [r3, #0]
if(overload_mode==3)
8002a4a: 230e movs r3, #14
8002a4c: 18fb adds r3, r7, r3
8002a4e: 781b ldrb r3, [r3, #0]
8002a50: 2b03 cmp r3, #3
8002a52: d00f beq.n 8002a74 <mymain+0x894>
{
}else
{
countdown=countdown_set-countdown;
8002a54: 4b53 ldr r3, [pc, #332] ; (8002ba4 <mymain+0x9c4>)
8002a56: 681a ldr r2, [r3, #0]
8002a58: 4b50 ldr r3, [pc, #320] ; (8002b9c <mymain+0x9bc>)
8002a5a: 681b ldr r3, [r3, #0]
8002a5c: 1ad2 subs r2, r2, r3
8002a5e: 4b4f ldr r3, [pc, #316] ; (8002b9c <mymain+0x9bc>)
8002a60: 601a str r2, [r3, #0]
}
}
break;
8002a62: e007 b.n 8002a74 <mymain+0x894>
break;
8002a64: 46c0 nop ; (mov r8, r8)
8002a66: e006 b.n 8002a76 <mymain+0x896>
break;
8002a68: 46c0 nop ; (mov r8, r8)
8002a6a: e004 b.n 8002a76 <mymain+0x896>
break;
8002a6c: 46c0 nop ; (mov r8, r8)
8002a6e: e002 b.n 8002a76 <mymain+0x896>
break;
8002a70: 46c0 nop ; (mov r8, r8)
8002a72: e000 b.n 8002a76 <mymain+0x896>
break;
8002a74: 46c0 nop ; (mov r8, r8)
}
if(HAL_GetTick()>runtime)
8002a76: f7fd fefb bl 8000870 <HAL_GetTick>
8002a7a: 0002 movs r2, r0
8002a7c: 697b ldr r3, [r7, #20]
8002a7e: 4293 cmp r3, r2
8002a80: d217 bcs.n 8002ab2 <mymain+0x8d2>
{
runtime+=1000;
8002a82: 697b ldr r3, [r7, #20]
8002a84: 22fa movs r2, #250 ; 0xfa
8002a86: 0092 lsls r2, r2, #2
8002a88: 4694 mov ip, r2
8002a8a: 4463 add r3, ip
8002a8c: 617b str r3, [r7, #20]
dis_buff.led_err=rand()%2;
dis_buff.led_n=rand()%2;
dis_buff.led_p=rand()%2;
dis_buff.led_run=rand()%2;
*/
if(dis_buff.led_run==1)
8002a8e: 4b42 ldr r3, [pc, #264] ; (8002b98 <mymain+0x9b8>)
8002a90: 791b ldrb r3, [r3, #4]
8002a92: 2210 movs r2, #16
8002a94: 4013 ands r3, r2
8002a96: b2db uxtb r3, r3
8002a98: 2b00 cmp r3, #0
8002a9a: d005 beq.n 8002aa8 <mymain+0x8c8>
{
dis_buff.led_run=0;
8002a9c: 4b3e ldr r3, [pc, #248] ; (8002b98 <mymain+0x9b8>)
8002a9e: 791a ldrb r2, [r3, #4]
8002aa0: 2110 movs r1, #16
8002aa2: 438a bics r2, r1
8002aa4: 711a strb r2, [r3, #4]
8002aa6: e004 b.n 8002ab2 <mymain+0x8d2>
}else
{
dis_buff.led_run=1;
8002aa8: 4b3b ldr r3, [pc, #236] ; (8002b98 <mymain+0x9b8>)
8002aaa: 791a ldrb r2, [r3, #4]
8002aac: 2110 movs r1, #16
8002aae: 430a orrs r2, r1
8002ab0: 711a strb r2, [r3, #4]
}
}
HAL_ADC_Start(&hadc);
8002ab2: 4b44 ldr r3, [pc, #272] ; (8002bc4 <mymain+0x9e4>)
8002ab4: 0018 movs r0, r3
8002ab6: f7fe f825 bl 8000b04 <HAL_ADC_Start>
adc_l+=HAL_ADC_GetValue(&hadc);
8002aba: 4b42 ldr r3, [pc, #264] ; (8002bc4 <mymain+0x9e4>)
8002abc: 0018 movs r0, r3
8002abe: f7fe f8b5 bl 8000c2c <HAL_ADC_GetValue>
8002ac2: 0002 movs r2, r0
8002ac4: 687b ldr r3, [r7, #4]
8002ac6: 189b adds r3, r3, r2
8002ac8: 607b str r3, [r7, #4]
adc_times+=1;
8002aca: 240a movs r4, #10
8002acc: 193b adds r3, r7, r4
8002ace: 193a adds r2, r7, r4
8002ad0: 8812 ldrh r2, [r2, #0]
8002ad2: 3201 adds r2, #1
8002ad4: 801a strh r2, [r3, #0]
HAL_ADC_Stop(&hadc);
8002ad6: 4b3b ldr r3, [pc, #236] ; (8002bc4 <mymain+0x9e4>)
8002ad8: 0018 movs r0, r3
8002ada: f7fe f867 bl 8000bac <HAL_ADC_Stop>
if(adc_times==32)
8002ade: 0021 movs r1, r4
8002ae0: 187b adds r3, r7, r1
8002ae2: 881b ldrh r3, [r3, #0]
8002ae4: 2b20 cmp r3, #32
8002ae6: d109 bne.n 8002afc <mymain+0x91c>
{
adc=adc_l>>5;
8002ae8: 687b ldr r3, [r7, #4]
8002aea: 095a lsrs r2, r3, #5
8002aec: 230c movs r3, #12
8002aee: 18fb adds r3, r7, r3
8002af0: 801a strh r2, [r3, #0]
adc_times=0;
8002af2: 187b adds r3, r7, r1
8002af4: 2200 movs r2, #0
8002af6: 801a strh r2, [r3, #0]
adc_l=0;
8002af8: 2300 movs r3, #0
8002afa: 607b str r3, [r7, #4]
}
if(adc>600)
8002afc: 230c movs r3, #12
8002afe: 18fb adds r3, r7, r3
8002b00: 881a ldrh r2, [r3, #0]
8002b02: 2396 movs r3, #150 ; 0x96
8002b04: 009b lsls r3, r3, #2
8002b06: 429a cmp r2, r3
8002b08: d905 bls.n 8002b16 <mymain+0x936>
{
GEI_BUTTON_CODE(&overload,1);
8002b0a: 4b2f ldr r3, [pc, #188] ; (8002bc8 <mymain+0x9e8>)
8002b0c: 2101 movs r1, #1
8002b0e: 0018 movs r0, r3
8002b10: f7ff f97a bl 8001e08 <GEI_BUTTON_CODE>
8002b14: e004 b.n 8002b20 <mymain+0x940>
}else
{
GEI_BUTTON_CODE(&overload,0);
8002b16: 4b2c ldr r3, [pc, #176] ; (8002bc8 <mymain+0x9e8>)
8002b18: 2100 movs r1, #0
8002b1a: 0018 movs r0, r3
8002b1c: f7ff f974 bl 8001e08 <GEI_BUTTON_CODE>
}
GEI_BUTTON_CODE(&key1,KEY1);
8002b20: 2390 movs r3, #144 ; 0x90
8002b22: 05db lsls r3, r3, #23
8002b24: 2180 movs r1, #128 ; 0x80
8002b26: 0018 movs r0, r3
8002b28: f7fe fce8 bl 80014fc <HAL_GPIO_ReadPin>
8002b2c: 0003 movs r3, r0
8002b2e: 001a movs r2, r3
8002b30: 4b21 ldr r3, [pc, #132] ; (8002bb8 <mymain+0x9d8>)
8002b32: 0011 movs r1, r2
8002b34: 0018 movs r0, r3
8002b36: f7ff f967 bl 8001e08 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key2,KEY2);
8002b3a: 2380 movs r3, #128 ; 0x80
8002b3c: 009a lsls r2, r3, #2
8002b3e: 2390 movs r3, #144 ; 0x90
8002b40: 05db lsls r3, r3, #23
8002b42: 0011 movs r1, r2
8002b44: 0018 movs r0, r3
8002b46: f7fe fcd9 bl 80014fc <HAL_GPIO_ReadPin>
8002b4a: 0003 movs r3, r0
8002b4c: 001a movs r2, r3
8002b4e: 4b14 ldr r3, [pc, #80] ; (8002ba0 <mymain+0x9c0>)
8002b50: 0011 movs r1, r2
8002b52: 0018 movs r0, r3
8002b54: f7ff f958 bl 8001e08 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key3,KEY3);
8002b58: 2380 movs r3, #128 ; 0x80
8002b5a: 00da lsls r2, r3, #3
8002b5c: 2390 movs r3, #144 ; 0x90
8002b5e: 05db lsls r3, r3, #23
8002b60: 0011 movs r1, r2
8002b62: 0018 movs r0, r3
8002b64: f7fe fcca bl 80014fc <HAL_GPIO_ReadPin>
8002b68: 0003 movs r3, r0
8002b6a: 001a movs r2, r3
8002b6c: 4b0f ldr r3, [pc, #60] ; (8002bac <mymain+0x9cc>)
8002b6e: 0011 movs r1, r2
8002b70: 0018 movs r0, r3
8002b72: f7ff f949 bl 8001e08 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key4,KEY4);
8002b76: 2390 movs r3, #144 ; 0x90
8002b78: 05db lsls r3, r3, #23
8002b7a: 2140 movs r1, #64 ; 0x40
8002b7c: 0018 movs r0, r3
8002b7e: f7fe fcbd bl 80014fc <HAL_GPIO_ReadPin>
8002b82: 0003 movs r3, r0
8002b84: 001a movs r2, r3
8002b86: 4b0e ldr r3, [pc, #56] ; (8002bc0 <mymain+0x9e0>)
8002b88: 0011 movs r1, r2
8002b8a: 0018 movs r0, r3
8002b8c: f7ff f93c bl 8001e08 <GEI_BUTTON_CODE>
display();
8002b90: f7ff fa10 bl 8001fb4 <display>
switch(mode)
8002b94: f7ff fb6b bl 800226e <mymain+0x8e>
8002b98: 20000084 .word 0x20000084
8002b9c: 2000002c .word 0x2000002c
8002ba0: 200000bc .word 0x200000bc
8002ba4: 2000000c .word 0x2000000c
8002ba8: 00002710 .word 0x00002710
8002bac: 200000ac .word 0x200000ac
8002bb0: fffffc18 .word 0xfffffc18
8002bb4: 0000ea60 .word 0x0000ea60
8002bb8: 2000008c .word 0x2000008c
8002bbc: 48001400 .word 0x48001400
8002bc0: 20000074 .word 0x20000074
8002bc4: 20000030 .word 0x20000030
8002bc8: 2000009c .word 0x2000009c
08002bcc <__libc_init_array>:
8002bcc: b570 push {r4, r5, r6, lr}
8002bce: 2600 movs r6, #0
8002bd0: 4d0c ldr r5, [pc, #48] ; (8002c04 <__libc_init_array+0x38>)
8002bd2: 4c0d ldr r4, [pc, #52] ; (8002c08 <__libc_init_array+0x3c>)
8002bd4: 1b64 subs r4, r4, r5
8002bd6: 10a4 asrs r4, r4, #2
8002bd8: 42a6 cmp r6, r4
8002bda: d109 bne.n 8002bf0 <__libc_init_array+0x24>
8002bdc: 2600 movs r6, #0
8002bde: f000 f821 bl 8002c24 <_init>
8002be2: 4d0a ldr r5, [pc, #40] ; (8002c0c <__libc_init_array+0x40>)
8002be4: 4c0a ldr r4, [pc, #40] ; (8002c10 <__libc_init_array+0x44>)
8002be6: 1b64 subs r4, r4, r5
8002be8: 10a4 asrs r4, r4, #2
8002bea: 42a6 cmp r6, r4
8002bec: d105 bne.n 8002bfa <__libc_init_array+0x2e>
8002bee: bd70 pop {r4, r5, r6, pc}
8002bf0: 00b3 lsls r3, r6, #2
8002bf2: 58eb ldr r3, [r5, r3]
8002bf4: 4798 blx r3
8002bf6: 3601 adds r6, #1
8002bf8: e7ee b.n 8002bd8 <__libc_init_array+0xc>
8002bfa: 00b3 lsls r3, r6, #2
8002bfc: 58eb ldr r3, [r5, r3]
8002bfe: 4798 blx r3
8002c00: 3601 adds r6, #1
8002c02: e7f2 b.n 8002bea <__libc_init_array+0x1e>
8002c04: 08002c98 .word 0x08002c98
8002c08: 08002c98 .word 0x08002c98
8002c0c: 08002c98 .word 0x08002c98
8002c10: 08002c9c .word 0x08002c9c
08002c14 <memset>:
8002c14: 0003 movs r3, r0
8002c16: 1882 adds r2, r0, r2
8002c18: 4293 cmp r3, r2
8002c1a: d100 bne.n 8002c1e <memset+0xa>
8002c1c: 4770 bx lr
8002c1e: 7019 strb r1, [r3, #0]
8002c20: 3301 adds r3, #1
8002c22: e7f9 b.n 8002c18 <memset+0x4>
08002c24 <_init>:
8002c24: b5f8 push {r3, r4, r5, r6, r7, lr}
8002c26: 46c0 nop ; (mov r8, r8)
8002c28: bcf8 pop {r3, r4, r5, r6, r7}
8002c2a: bc08 pop {r3}
8002c2c: 469e mov lr, r3
8002c2e: 4770 bx lr
08002c30 <_fini>:
8002c30: b5f8 push {r3, r4, r5, r6, r7, lr}
8002c32: 46c0 nop ; (mov r8, r8)
8002c34: bcf8 pop {r3, r4, r5, r6, r7}
8002c36: bc08 pop {r3}
8002c38: 469e mov lr, r3
8002c3a: 4770 bx lr
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