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motor_controller/Debug/Motor_Controller.list
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Motor_Controller.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001cf4 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000044 08001db4 08001db4 00011db4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08001df8 08001df8 0002000c 2**0
CONTENTS
4 .ARM 00000000 08001df8 08001df8 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08001df8 08001df8 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08001df8 08001df8 00011df8 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08001dfc 08001dfc 00011dfc 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08001e00 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000098 2000000c 08001e0c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000804 200000a4 08001e0c 000200a4 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 000048da 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001333 00000000 00000000 0002490e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000004b0 00000000 00000000 00025c48 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 000003f8 00000000 00000000 000260f8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0000e935 00000000 00000000 000264f0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00006b87 00000000 00000000 00034e25 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00056655 00000000 00000000 0003b9ac 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 00092001 2**0
CONTENTS, READONLY
20 .debug_frame 00000e98 00000000 00000000 00092054 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 08001d9c .word 0x08001d9c
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 08001d9c .word 0x08001d9c
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__aeabi_idiv0>:
800021c: 4770 bx lr
800021e: 46c0 nop ; (mov r8, r8)
08000220 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000220: b580 push {r7, lr}
8000222: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000224: f000 f9e0 bl 80005e8 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000228: f000 f807 bl 800023a <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800022c: f000 f8b2 bl 8000394 <MX_GPIO_Init>
MX_ADC_Init();
8000230: f000 f854 bl 80002dc <MX_ADC_Init>
/* USER CODE BEGIN 2 */
mymain();
8000234: f001 fcee bl 8001c14 <mymain>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000238: e7fe b.n 8000238 <main+0x18>
0800023a <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800023a: b590 push {r4, r7, lr}
800023c: b091 sub sp, #68 ; 0x44
800023e: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000240: 2410 movs r4, #16
8000242: 193b adds r3, r7, r4
8000244: 0018 movs r0, r3
8000246: 2330 movs r3, #48 ; 0x30
8000248: 001a movs r2, r3
800024a: 2100 movs r1, #0
800024c: f001 fd9e bl 8001d8c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000250: 003b movs r3, r7
8000252: 0018 movs r0, r3
8000254: 2310 movs r3, #16
8000256: 001a movs r2, r3
8000258: 2100 movs r1, #0
800025a: f001 fd97 bl 8001d8c <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14;
800025e: 0021 movs r1, r4
8000260: 187b adds r3, r7, r1
8000262: 2212 movs r2, #18
8000264: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000266: 187b adds r3, r7, r1
8000268: 2201 movs r2, #1
800026a: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
800026c: 187b adds r3, r7, r1
800026e: 2201 movs r2, #1
8000270: 615a str r2, [r3, #20]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000272: 187b adds r3, r7, r1
8000274: 2210 movs r2, #16
8000276: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSI14CalibrationValue = 16;
8000278: 187b adds r3, r7, r1
800027a: 2210 movs r2, #16
800027c: 619a str r2, [r3, #24]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800027e: 187b adds r3, r7, r1
8000280: 2202 movs r2, #2
8000282: 621a str r2, [r3, #32]
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000284: 187b adds r3, r7, r1
8000286: 2200 movs r2, #0
8000288: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
800028a: 187b adds r3, r7, r1
800028c: 22a0 movs r2, #160 ; 0xa0
800028e: 0392 lsls r2, r2, #14
8000290: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
8000292: 187b adds r3, r7, r1
8000294: 2200 movs r2, #0
8000296: 62da str r2, [r3, #44] ; 0x2c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000298: 187b adds r3, r7, r1
800029a: 0018 movs r0, r3
800029c: f000 fe9c bl 8000fd8 <HAL_RCC_OscConfig>
80002a0: 1e03 subs r3, r0, #0
80002a2: d001 beq.n 80002a8 <SystemClock_Config+0x6e>
{
Error_Handler();
80002a4: f000 f8ea bl 800047c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80002a8: 003b movs r3, r7
80002aa: 2207 movs r2, #7
80002ac: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80002ae: 003b movs r3, r7
80002b0: 2202 movs r2, #2
80002b2: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002b4: 003b movs r3, r7
80002b6: 2200 movs r2, #0
80002b8: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80002ba: 003b movs r3, r7
80002bc: 2200 movs r2, #0
80002be: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
80002c0: 003b movs r3, r7
80002c2: 2101 movs r1, #1
80002c4: 0018 movs r0, r3
80002c6: f001 f9a1 bl 800160c <HAL_RCC_ClockConfig>
80002ca: 1e03 subs r3, r0, #0
80002cc: d001 beq.n 80002d2 <SystemClock_Config+0x98>
{
Error_Handler();
80002ce: f000 f8d5 bl 800047c <Error_Handler>
}
}
80002d2: 46c0 nop ; (mov r8, r8)
80002d4: 46bd mov sp, r7
80002d6: b011 add sp, #68 ; 0x44
80002d8: bd90 pop {r4, r7, pc}
...
080002dc <MX_ADC_Init>:
* @brief ADC Initialization Function
* @param None
* @retval None
*/
static void MX_ADC_Init(void)
{
80002dc: b580 push {r7, lr}
80002de: b084 sub sp, #16
80002e0: af00 add r7, sp, #0
/* USER CODE BEGIN ADC_Init 0 */
/* USER CODE END ADC_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80002e2: 1d3b adds r3, r7, #4
80002e4: 0018 movs r0, r3
80002e6: 230c movs r3, #12
80002e8: 001a movs r2, r3
80002ea: 2100 movs r1, #0
80002ec: f001 fd4e bl 8001d8c <memset>
/* USER CODE BEGIN ADC_Init 1 */
/* USER CODE END ADC_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc.Instance = ADC1;
80002f0: 4b26 ldr r3, [pc, #152] ; (800038c <MX_ADC_Init+0xb0>)
80002f2: 4a27 ldr r2, [pc, #156] ; (8000390 <MX_ADC_Init+0xb4>)
80002f4: 601a str r2, [r3, #0]
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
80002f6: 4b25 ldr r3, [pc, #148] ; (800038c <MX_ADC_Init+0xb0>)
80002f8: 2200 movs r2, #0
80002fa: 605a str r2, [r3, #4]
hadc.Init.Resolution = ADC_RESOLUTION_12B;
80002fc: 4b23 ldr r3, [pc, #140] ; (800038c <MX_ADC_Init+0xb0>)
80002fe: 2200 movs r2, #0
8000300: 609a str r2, [r3, #8]
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000302: 4b22 ldr r3, [pc, #136] ; (800038c <MX_ADC_Init+0xb0>)
8000304: 2200 movs r2, #0
8000306: 60da str r2, [r3, #12]
hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
8000308: 4b20 ldr r3, [pc, #128] ; (800038c <MX_ADC_Init+0xb0>)
800030a: 2201 movs r2, #1
800030c: 611a str r2, [r3, #16]
hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800030e: 4b1f ldr r3, [pc, #124] ; (800038c <MX_ADC_Init+0xb0>)
8000310: 2204 movs r2, #4
8000312: 615a str r2, [r3, #20]
hadc.Init.LowPowerAutoWait = DISABLE;
8000314: 4b1d ldr r3, [pc, #116] ; (800038c <MX_ADC_Init+0xb0>)
8000316: 2200 movs r2, #0
8000318: 761a strb r2, [r3, #24]
hadc.Init.LowPowerAutoPowerOff = DISABLE;
800031a: 4b1c ldr r3, [pc, #112] ; (800038c <MX_ADC_Init+0xb0>)
800031c: 2200 movs r2, #0
800031e: 765a strb r2, [r3, #25]
hadc.Init.ContinuousConvMode = DISABLE;
8000320: 4b1a ldr r3, [pc, #104] ; (800038c <MX_ADC_Init+0xb0>)
8000322: 2200 movs r2, #0
8000324: 769a strb r2, [r3, #26]
hadc.Init.DiscontinuousConvMode = DISABLE;
8000326: 4b19 ldr r3, [pc, #100] ; (800038c <MX_ADC_Init+0xb0>)
8000328: 2200 movs r2, #0
800032a: 76da strb r2, [r3, #27]
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
800032c: 4b17 ldr r3, [pc, #92] ; (800038c <MX_ADC_Init+0xb0>)
800032e: 22c2 movs r2, #194 ; 0xc2
8000330: 32ff adds r2, #255 ; 0xff
8000332: 61da str r2, [r3, #28]
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000334: 4b15 ldr r3, [pc, #84] ; (800038c <MX_ADC_Init+0xb0>)
8000336: 2200 movs r2, #0
8000338: 621a str r2, [r3, #32]
hadc.Init.DMAContinuousRequests = DISABLE;
800033a: 4b14 ldr r3, [pc, #80] ; (800038c <MX_ADC_Init+0xb0>)
800033c: 2224 movs r2, #36 ; 0x24
800033e: 2100 movs r1, #0
8000340: 5499 strb r1, [r3, r2]
hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000342: 4b12 ldr r3, [pc, #72] ; (800038c <MX_ADC_Init+0xb0>)
8000344: 2201 movs r2, #1
8000346: 629a str r2, [r3, #40] ; 0x28
if (HAL_ADC_Init(&hadc) != HAL_OK)
8000348: 4b10 ldr r3, [pc, #64] ; (800038c <MX_ADC_Init+0xb0>)
800034a: 0018 movs r0, r3
800034c: f000 f9b0 bl 80006b0 <HAL_ADC_Init>
8000350: 1e03 subs r3, r0, #0
8000352: d001 beq.n 8000358 <MX_ADC_Init+0x7c>
{
Error_Handler();
8000354: f000 f892 bl 800047c <Error_Handler>
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000358: 1d3b adds r3, r7, #4
800035a: 2200 movs r2, #0
800035c: 601a str r2, [r3, #0]
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
800035e: 1d3b adds r3, r7, #4
8000360: 2280 movs r2, #128 ; 0x80
8000362: 0152 lsls r2, r2, #5
8000364: 605a str r2, [r3, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
8000366: 1d3b adds r3, r7, #4
8000368: 2280 movs r2, #128 ; 0x80
800036a: 0552 lsls r2, r2, #21
800036c: 609a str r2, [r3, #8]
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
800036e: 1d3a adds r2, r7, #4
8000370: 4b06 ldr r3, [pc, #24] ; (800038c <MX_ADC_Init+0xb0>)
8000372: 0011 movs r1, r2
8000374: 0018 movs r0, r3
8000376: f000 fadb bl 8000930 <HAL_ADC_ConfigChannel>
800037a: 1e03 subs r3, r0, #0
800037c: d001 beq.n 8000382 <MX_ADC_Init+0xa6>
{
Error_Handler();
800037e: f000 f87d bl 800047c <Error_Handler>
}
/* USER CODE BEGIN ADC_Init 2 */
/* USER CODE END ADC_Init 2 */
}
8000382: 46c0 nop ; (mov r8, r8)
8000384: 46bd mov sp, r7
8000386: b004 add sp, #16
8000388: bd80 pop {r7, pc}
800038a: 46c0 nop ; (mov r8, r8)
800038c: 20000028 .word 0x20000028
8000390: 40012400 .word 0x40012400
08000394 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000394: b590 push {r4, r7, lr}
8000396: b089 sub sp, #36 ; 0x24
8000398: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800039a: 240c movs r4, #12
800039c: 193b adds r3, r7, r4
800039e: 0018 movs r0, r3
80003a0: 2314 movs r3, #20
80003a2: 001a movs r2, r3
80003a4: 2100 movs r1, #0
80003a6: f001 fcf1 bl 8001d8c <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80003aa: 4b32 ldr r3, [pc, #200] ; (8000474 <MX_GPIO_Init+0xe0>)
80003ac: 695a ldr r2, [r3, #20]
80003ae: 4b31 ldr r3, [pc, #196] ; (8000474 <MX_GPIO_Init+0xe0>)
80003b0: 2180 movs r1, #128 ; 0x80
80003b2: 03c9 lsls r1, r1, #15
80003b4: 430a orrs r2, r1
80003b6: 615a str r2, [r3, #20]
80003b8: 4b2e ldr r3, [pc, #184] ; (8000474 <MX_GPIO_Init+0xe0>)
80003ba: 695a ldr r2, [r3, #20]
80003bc: 2380 movs r3, #128 ; 0x80
80003be: 03db lsls r3, r3, #15
80003c0: 4013 ands r3, r2
80003c2: 60bb str r3, [r7, #8]
80003c4: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80003c6: 4b2b ldr r3, [pc, #172] ; (8000474 <MX_GPIO_Init+0xe0>)
80003c8: 695a ldr r2, [r3, #20]
80003ca: 4b2a ldr r3, [pc, #168] ; (8000474 <MX_GPIO_Init+0xe0>)
80003cc: 2180 movs r1, #128 ; 0x80
80003ce: 0289 lsls r1, r1, #10
80003d0: 430a orrs r2, r1
80003d2: 615a str r2, [r3, #20]
80003d4: 4b27 ldr r3, [pc, #156] ; (8000474 <MX_GPIO_Init+0xe0>)
80003d6: 695a ldr r2, [r3, #20]
80003d8: 2380 movs r3, #128 ; 0x80
80003da: 029b lsls r3, r3, #10
80003dc: 4013 ands r3, r2
80003de: 607b str r3, [r7, #4]
80003e0: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET);
80003e2: 4b25 ldr r3, [pc, #148] ; (8000478 <MX_GPIO_Init+0xe4>)
80003e4: 2200 movs r2, #0
80003e6: 2103 movs r1, #3
80003e8: 0018 movs r0, r3
80003ea: f000 fdd8 bl 8000f9e <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET);
80003ee: 2390 movs r3, #144 ; 0x90
80003f0: 05db lsls r3, r3, #23
80003f2: 2200 movs r2, #0
80003f4: 2138 movs r1, #56 ; 0x38
80003f6: 0018 movs r0, r3
80003f8: f000 fdd1 bl 8000f9e <HAL_GPIO_WritePin>
/*Configure GPIO pins : MOTA_Pin MOTB_Pin */
GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin;
80003fc: 193b adds r3, r7, r4
80003fe: 2203 movs r2, #3
8000400: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000402: 193b adds r3, r7, r4
8000404: 2201 movs r2, #1
8000406: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000408: 193b adds r3, r7, r4
800040a: 2200 movs r2, #0
800040c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800040e: 193b adds r3, r7, r4
8000410: 2203 movs r2, #3
8000412: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000414: 193b adds r3, r7, r4
8000416: 4a18 ldr r2, [pc, #96] ; (8000478 <MX_GPIO_Init+0xe4>)
8000418: 0019 movs r1, r3
800041a: 0010 movs r0, r2
800041c: f000 fc32 bl 8000c84 <HAL_GPIO_Init>
/*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */
GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin;
8000420: 193b adds r3, r7, r4
8000422: 2238 movs r2, #56 ; 0x38
8000424: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000426: 193b adds r3, r7, r4
8000428: 2201 movs r2, #1
800042a: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800042c: 193b adds r3, r7, r4
800042e: 2200 movs r2, #0
8000430: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000432: 193b adds r3, r7, r4
8000434: 2203 movs r2, #3
8000436: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000438: 193a adds r2, r7, r4
800043a: 2390 movs r3, #144 ; 0x90
800043c: 05db lsls r3, r3, #23
800043e: 0011 movs r1, r2
8000440: 0018 movs r0, r3
8000442: f000 fc1f bl 8000c84 <HAL_GPIO_Init>
/*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */
GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin;
8000446: 0021 movs r1, r4
8000448: 187b adds r3, r7, r1
800044a: 22d8 movs r2, #216 ; 0xd8
800044c: 00d2 lsls r2, r2, #3
800044e: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000450: 187b adds r3, r7, r1
8000452: 2200 movs r2, #0
8000454: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000456: 187b adds r3, r7, r1
8000458: 2200 movs r2, #0
800045a: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800045c: 187a adds r2, r7, r1
800045e: 2390 movs r3, #144 ; 0x90
8000460: 05db lsls r3, r3, #23
8000462: 0011 movs r1, r2
8000464: 0018 movs r0, r3
8000466: f000 fc0d bl 8000c84 <HAL_GPIO_Init>
}
800046a: 46c0 nop ; (mov r8, r8)
800046c: 46bd mov sp, r7
800046e: b009 add sp, #36 ; 0x24
8000470: bd90 pop {r4, r7, pc}
8000472: 46c0 nop ; (mov r8, r8)
8000474: 40021000 .word 0x40021000
8000478: 48001400 .word 0x48001400
0800047c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800047c: b580 push {r7, lr}
800047e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000480: b672 cpsid i
}
8000482: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000484: e7fe b.n 8000484 <Error_Handler+0x8>
...
08000488 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000488: b580 push {r7, lr}
800048a: b082 sub sp, #8
800048c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800048e: 4b0f ldr r3, [pc, #60] ; (80004cc <HAL_MspInit+0x44>)
8000490: 699a ldr r2, [r3, #24]
8000492: 4b0e ldr r3, [pc, #56] ; (80004cc <HAL_MspInit+0x44>)
8000494: 2101 movs r1, #1
8000496: 430a orrs r2, r1
8000498: 619a str r2, [r3, #24]
800049a: 4b0c ldr r3, [pc, #48] ; (80004cc <HAL_MspInit+0x44>)
800049c: 699b ldr r3, [r3, #24]
800049e: 2201 movs r2, #1
80004a0: 4013 ands r3, r2
80004a2: 607b str r3, [r7, #4]
80004a4: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80004a6: 4b09 ldr r3, [pc, #36] ; (80004cc <HAL_MspInit+0x44>)
80004a8: 69da ldr r2, [r3, #28]
80004aa: 4b08 ldr r3, [pc, #32] ; (80004cc <HAL_MspInit+0x44>)
80004ac: 2180 movs r1, #128 ; 0x80
80004ae: 0549 lsls r1, r1, #21
80004b0: 430a orrs r2, r1
80004b2: 61da str r2, [r3, #28]
80004b4: 4b05 ldr r3, [pc, #20] ; (80004cc <HAL_MspInit+0x44>)
80004b6: 69da ldr r2, [r3, #28]
80004b8: 2380 movs r3, #128 ; 0x80
80004ba: 055b lsls r3, r3, #21
80004bc: 4013 ands r3, r2
80004be: 603b str r3, [r7, #0]
80004c0: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80004c2: 46c0 nop ; (mov r8, r8)
80004c4: 46bd mov sp, r7
80004c6: b002 add sp, #8
80004c8: bd80 pop {r7, pc}
80004ca: 46c0 nop ; (mov r8, r8)
80004cc: 40021000 .word 0x40021000
080004d0 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
80004d0: b590 push {r4, r7, lr}
80004d2: b08b sub sp, #44 ; 0x2c
80004d4: af00 add r7, sp, #0
80004d6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80004d8: 2414 movs r4, #20
80004da: 193b adds r3, r7, r4
80004dc: 0018 movs r0, r3
80004de: 2314 movs r3, #20
80004e0: 001a movs r2, r3
80004e2: 2100 movs r1, #0
80004e4: f001 fc52 bl 8001d8c <memset>
if(hadc->Instance==ADC1)
80004e8: 687b ldr r3, [r7, #4]
80004ea: 681b ldr r3, [r3, #0]
80004ec: 4a19 ldr r2, [pc, #100] ; (8000554 <HAL_ADC_MspInit+0x84>)
80004ee: 4293 cmp r3, r2
80004f0: d12b bne.n 800054a <HAL_ADC_MspInit+0x7a>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
80004f2: 4b19 ldr r3, [pc, #100] ; (8000558 <HAL_ADC_MspInit+0x88>)
80004f4: 699a ldr r2, [r3, #24]
80004f6: 4b18 ldr r3, [pc, #96] ; (8000558 <HAL_ADC_MspInit+0x88>)
80004f8: 2180 movs r1, #128 ; 0x80
80004fa: 0089 lsls r1, r1, #2
80004fc: 430a orrs r2, r1
80004fe: 619a str r2, [r3, #24]
8000500: 4b15 ldr r3, [pc, #84] ; (8000558 <HAL_ADC_MspInit+0x88>)
8000502: 699a ldr r2, [r3, #24]
8000504: 2380 movs r3, #128 ; 0x80
8000506: 009b lsls r3, r3, #2
8000508: 4013 ands r3, r2
800050a: 613b str r3, [r7, #16]
800050c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800050e: 4b12 ldr r3, [pc, #72] ; (8000558 <HAL_ADC_MspInit+0x88>)
8000510: 695a ldr r2, [r3, #20]
8000512: 4b11 ldr r3, [pc, #68] ; (8000558 <HAL_ADC_MspInit+0x88>)
8000514: 2180 movs r1, #128 ; 0x80
8000516: 0289 lsls r1, r1, #10
8000518: 430a orrs r2, r1
800051a: 615a str r2, [r3, #20]
800051c: 4b0e ldr r3, [pc, #56] ; (8000558 <HAL_ADC_MspInit+0x88>)
800051e: 695a ldr r2, [r3, #20]
8000520: 2380 movs r3, #128 ; 0x80
8000522: 029b lsls r3, r3, #10
8000524: 4013 ands r3, r2
8000526: 60fb str r3, [r7, #12]
8000528: 68fb ldr r3, [r7, #12]
/**ADC GPIO Configuration
PA0 ------> ADC_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
800052a: 193b adds r3, r7, r4
800052c: 2201 movs r2, #1
800052e: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000530: 193b adds r3, r7, r4
8000532: 2203 movs r2, #3
8000534: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000536: 193b adds r3, r7, r4
8000538: 2200 movs r2, #0
800053a: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800053c: 193a adds r2, r7, r4
800053e: 2390 movs r3, #144 ; 0x90
8000540: 05db lsls r3, r3, #23
8000542: 0011 movs r1, r2
8000544: 0018 movs r0, r3
8000546: f000 fb9d bl 8000c84 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
800054a: 46c0 nop ; (mov r8, r8)
800054c: 46bd mov sp, r7
800054e: b00b add sp, #44 ; 0x2c
8000550: bd90 pop {r4, r7, pc}
8000552: 46c0 nop ; (mov r8, r8)
8000554: 40012400 .word 0x40012400
8000558: 40021000 .word 0x40021000
0800055c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800055c: b580 push {r7, lr}
800055e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000560: e7fe b.n 8000560 <NMI_Handler+0x4>
08000562 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000562: b580 push {r7, lr}
8000564: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000566: e7fe b.n 8000566 <HardFault_Handler+0x4>
08000568 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000568: b580 push {r7, lr}
800056a: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
800056c: 46c0 nop ; (mov r8, r8)
800056e: 46bd mov sp, r7
8000570: bd80 pop {r7, pc}
08000572 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000572: b580 push {r7, lr}
8000574: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000576: 46c0 nop ; (mov r8, r8)
8000578: 46bd mov sp, r7
800057a: bd80 pop {r7, pc}
0800057c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800057c: b580 push {r7, lr}
800057e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000580: f000 f87a bl 8000678 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000584: 46c0 nop ; (mov r8, r8)
8000586: 46bd mov sp, r7
8000588: bd80 pop {r7, pc}
0800058a <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
800058a: b580 push {r7, lr}
800058c: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
800058e: 46c0 nop ; (mov r8, r8)
8000590: 46bd mov sp, r7
8000592: bd80 pop {r7, pc}
08000594 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000594: 480d ldr r0, [pc, #52] ; (80005cc <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000596: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000598: 480d ldr r0, [pc, #52] ; (80005d0 <LoopForever+0x6>)
ldr r1, =_edata
800059a: 490e ldr r1, [pc, #56] ; (80005d4 <LoopForever+0xa>)
ldr r2, =_sidata
800059c: 4a0e ldr r2, [pc, #56] ; (80005d8 <LoopForever+0xe>)
movs r3, #0
800059e: 2300 movs r3, #0
b LoopCopyDataInit
80005a0: e002 b.n 80005a8 <LoopCopyDataInit>
080005a2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80005a2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80005a4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80005a6: 3304 adds r3, #4
080005a8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80005a8: 18c4 adds r4, r0, r3
cmp r4, r1
80005aa: 428c cmp r4, r1
bcc CopyDataInit
80005ac: d3f9 bcc.n 80005a2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80005ae: 4a0b ldr r2, [pc, #44] ; (80005dc <LoopForever+0x12>)
ldr r4, =_ebss
80005b0: 4c0b ldr r4, [pc, #44] ; (80005e0 <LoopForever+0x16>)
movs r3, #0
80005b2: 2300 movs r3, #0
b LoopFillZerobss
80005b4: e001 b.n 80005ba <LoopFillZerobss>
080005b6 <FillZerobss>:
FillZerobss:
str r3, [r2]
80005b6: 6013 str r3, [r2, #0]
adds r2, r2, #4
80005b8: 3204 adds r2, #4
080005ba <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80005ba: 42a2 cmp r2, r4
bcc FillZerobss
80005bc: d3fb bcc.n 80005b6 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80005be: f7ff ffe4 bl 800058a <SystemInit>
/* Call static constructors */
bl __libc_init_array
80005c2: f001 fbbf bl 8001d44 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80005c6: f7ff fe2b bl 8000220 <main>
080005ca <LoopForever>:
LoopForever:
b LoopForever
80005ca: e7fe b.n 80005ca <LoopForever>
ldr r0, =_estack
80005cc: 20001000 .word 0x20001000
ldr r0, =_sdata
80005d0: 20000000 .word 0x20000000
ldr r1, =_edata
80005d4: 2000000c .word 0x2000000c
ldr r2, =_sidata
80005d8: 08001e00 .word 0x08001e00
ldr r2, =_sbss
80005dc: 2000000c .word 0x2000000c
ldr r4, =_ebss
80005e0: 200000a4 .word 0x200000a4
080005e4 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80005e4: e7fe b.n 80005e4 <ADC1_IRQHandler>
...
080005e8 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80005e8: b580 push {r7, lr}
80005ea: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80005ec: 4b07 ldr r3, [pc, #28] ; (800060c <HAL_Init+0x24>)
80005ee: 681a ldr r2, [r3, #0]
80005f0: 4b06 ldr r3, [pc, #24] ; (800060c <HAL_Init+0x24>)
80005f2: 2110 movs r1, #16
80005f4: 430a orrs r2, r1
80005f6: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80005f8: 2003 movs r0, #3
80005fa: f000 f809 bl 8000610 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80005fe: f7ff ff43 bl 8000488 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000602: 2300 movs r3, #0
}
8000604: 0018 movs r0, r3
8000606: 46bd mov sp, r7
8000608: bd80 pop {r7, pc}
800060a: 46c0 nop ; (mov r8, r8)
800060c: 40022000 .word 0x40022000
08000610 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000610: b590 push {r4, r7, lr}
8000612: b083 sub sp, #12
8000614: af00 add r7, sp, #0
8000616: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000618: 4b14 ldr r3, [pc, #80] ; (800066c <HAL_InitTick+0x5c>)
800061a: 681c ldr r4, [r3, #0]
800061c: 4b14 ldr r3, [pc, #80] ; (8000670 <HAL_InitTick+0x60>)
800061e: 781b ldrb r3, [r3, #0]
8000620: 0019 movs r1, r3
8000622: 23fa movs r3, #250 ; 0xfa
8000624: 0098 lsls r0, r3, #2
8000626: f7ff fd6f bl 8000108 <__udivsi3>
800062a: 0003 movs r3, r0
800062c: 0019 movs r1, r3
800062e: 0020 movs r0, r4
8000630: f7ff fd6a bl 8000108 <__udivsi3>
8000634: 0003 movs r3, r0
8000636: 0018 movs r0, r3
8000638: f000 fb17 bl 8000c6a <HAL_SYSTICK_Config>
800063c: 1e03 subs r3, r0, #0
800063e: d001 beq.n 8000644 <HAL_InitTick+0x34>
{
return HAL_ERROR;
8000640: 2301 movs r3, #1
8000642: e00f b.n 8000664 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000644: 687b ldr r3, [r7, #4]
8000646: 2b03 cmp r3, #3
8000648: d80b bhi.n 8000662 <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800064a: 6879 ldr r1, [r7, #4]
800064c: 2301 movs r3, #1
800064e: 425b negs r3, r3
8000650: 2200 movs r2, #0
8000652: 0018 movs r0, r3
8000654: f000 faf4 bl 8000c40 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000658: 4b06 ldr r3, [pc, #24] ; (8000674 <HAL_InitTick+0x64>)
800065a: 687a ldr r2, [r7, #4]
800065c: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800065e: 2300 movs r3, #0
8000660: e000 b.n 8000664 <HAL_InitTick+0x54>
return HAL_ERROR;
8000662: 2301 movs r3, #1
}
8000664: 0018 movs r0, r3
8000666: 46bd mov sp, r7
8000668: b003 add sp, #12
800066a: bd90 pop {r4, r7, pc}
800066c: 20000000 .word 0x20000000
8000670: 20000008 .word 0x20000008
8000674: 20000004 .word 0x20000004
08000678 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000678: b580 push {r7, lr}
800067a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800067c: 4b05 ldr r3, [pc, #20] ; (8000694 <HAL_IncTick+0x1c>)
800067e: 781b ldrb r3, [r3, #0]
8000680: 001a movs r2, r3
8000682: 4b05 ldr r3, [pc, #20] ; (8000698 <HAL_IncTick+0x20>)
8000684: 681b ldr r3, [r3, #0]
8000686: 18d2 adds r2, r2, r3
8000688: 4b03 ldr r3, [pc, #12] ; (8000698 <HAL_IncTick+0x20>)
800068a: 601a str r2, [r3, #0]
}
800068c: 46c0 nop ; (mov r8, r8)
800068e: 46bd mov sp, r7
8000690: bd80 pop {r7, pc}
8000692: 46c0 nop ; (mov r8, r8)
8000694: 20000008 .word 0x20000008
8000698: 20000068 .word 0x20000068
0800069c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800069c: b580 push {r7, lr}
800069e: af00 add r7, sp, #0
return uwTick;
80006a0: 4b02 ldr r3, [pc, #8] ; (80006ac <HAL_GetTick+0x10>)
80006a2: 681b ldr r3, [r3, #0]
}
80006a4: 0018 movs r0, r3
80006a6: 46bd mov sp, r7
80006a8: bd80 pop {r7, pc}
80006aa: 46c0 nop ; (mov r8, r8)
80006ac: 20000068 .word 0x20000068
080006b0 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80006b0: b580 push {r7, lr}
80006b2: b084 sub sp, #16
80006b4: af00 add r7, sp, #0
80006b6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80006b8: 230f movs r3, #15
80006ba: 18fb adds r3, r7, r3
80006bc: 2200 movs r2, #0
80006be: 701a strb r2, [r3, #0]
uint32_t tmpCFGR1 = 0U;
80006c0: 2300 movs r3, #0
80006c2: 60bb str r3, [r7, #8]
/* Check ADC handle */
if(hadc == NULL)
80006c4: 687b ldr r3, [r7, #4]
80006c6: 2b00 cmp r3, #0
80006c8: d101 bne.n 80006ce <HAL_ADC_Init+0x1e>
{
return HAL_ERROR;
80006ca: 2301 movs r3, #1
80006cc: e125 b.n 800091a <HAL_ADC_Init+0x26a>
/* Refer to header of this file for more details on clock enabling procedure*/
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
/* - ADC voltage regulator enable */
if (hadc->State == HAL_ADC_STATE_RESET)
80006ce: 687b ldr r3, [r7, #4]
80006d0: 6b9b ldr r3, [r3, #56] ; 0x38
80006d2: 2b00 cmp r3, #0
80006d4: d10a bne.n 80006ec <HAL_ADC_Init+0x3c>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
80006d6: 687b ldr r3, [r7, #4]
80006d8: 2200 movs r2, #0
80006da: 63da str r2, [r3, #60] ; 0x3c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
80006dc: 687b ldr r3, [r7, #4]
80006de: 2234 movs r2, #52 ; 0x34
80006e0: 2100 movs r1, #0
80006e2: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80006e4: 687b ldr r3, [r7, #4]
80006e6: 0018 movs r0, r3
80006e8: f7ff fef2 bl 80004d0 <HAL_ADC_MspInit>
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
/* and if there is no conversion on going on regular group (ADC can be */
/* enabled anyway, in case of call of this function to update a parameter */
/* on the fly). */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
80006ec: 687b ldr r3, [r7, #4]
80006ee: 6b9b ldr r3, [r3, #56] ; 0x38
80006f0: 2210 movs r2, #16
80006f2: 4013 ands r3, r2
80006f4: d000 beq.n 80006f8 <HAL_ADC_Init+0x48>
80006f6: e103 b.n 8000900 <HAL_ADC_Init+0x250>
80006f8: 230f movs r3, #15
80006fa: 18fb adds r3, r7, r3
80006fc: 781b ldrb r3, [r3, #0]
80006fe: 2b00 cmp r3, #0
8000700: d000 beq.n 8000704 <HAL_ADC_Init+0x54>
8000702: e0fd b.n 8000900 <HAL_ADC_Init+0x250>
(tmp_hal_status == HAL_OK) &&
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
8000704: 687b ldr r3, [r7, #4]
8000706: 681b ldr r3, [r3, #0]
8000708: 689b ldr r3, [r3, #8]
800070a: 2204 movs r2, #4
800070c: 4013 ands r3, r2
(tmp_hal_status == HAL_OK) &&
800070e: d000 beq.n 8000712 <HAL_ADC_Init+0x62>
8000710: e0f6 b.n 8000900 <HAL_ADC_Init+0x250>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000712: 687b ldr r3, [r7, #4]
8000714: 6b9b ldr r3, [r3, #56] ; 0x38
8000716: 4a83 ldr r2, [pc, #524] ; (8000924 <HAL_ADC_Init+0x274>)
8000718: 4013 ands r3, r2
800071a: 2202 movs r2, #2
800071c: 431a orrs r2, r3
800071e: 687b ldr r3, [r7, #4]
8000720: 639a str r2, [r3, #56] ; 0x38
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - ADC clock mode */
/* - ADC clock prescaler */
/* - ADC resolution */
if (ADC_IS_ENABLE(hadc) == RESET)
8000722: 687b ldr r3, [r7, #4]
8000724: 681b ldr r3, [r3, #0]
8000726: 689b ldr r3, [r3, #8]
8000728: 2203 movs r2, #3
800072a: 4013 ands r3, r2
800072c: 2b01 cmp r3, #1
800072e: d112 bne.n 8000756 <HAL_ADC_Init+0xa6>
8000730: 687b ldr r3, [r7, #4]
8000732: 681b ldr r3, [r3, #0]
8000734: 681b ldr r3, [r3, #0]
8000736: 2201 movs r2, #1
8000738: 4013 ands r3, r2
800073a: 2b01 cmp r3, #1
800073c: d009 beq.n 8000752 <HAL_ADC_Init+0xa2>
800073e: 687b ldr r3, [r7, #4]
8000740: 681b ldr r3, [r3, #0]
8000742: 68da ldr r2, [r3, #12]
8000744: 2380 movs r3, #128 ; 0x80
8000746: 021b lsls r3, r3, #8
8000748: 401a ands r2, r3
800074a: 2380 movs r3, #128 ; 0x80
800074c: 021b lsls r3, r3, #8
800074e: 429a cmp r2, r3
8000750: d101 bne.n 8000756 <HAL_ADC_Init+0xa6>
8000752: 2301 movs r3, #1
8000754: e000 b.n 8000758 <HAL_ADC_Init+0xa8>
8000756: 2300 movs r3, #0
8000758: 2b00 cmp r3, #0
800075a: d116 bne.n 800078a <HAL_ADC_Init+0xda>
/* parameters): */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() ) */
/* Configuration of ADC resolution */
MODIFY_REG(hadc->Instance->CFGR1,
800075c: 687b ldr r3, [r7, #4]
800075e: 681b ldr r3, [r3, #0]
8000760: 68db ldr r3, [r3, #12]
8000762: 2218 movs r2, #24
8000764: 4393 bics r3, r2
8000766: 0019 movs r1, r3
8000768: 687b ldr r3, [r7, #4]
800076a: 689a ldr r2, [r3, #8]
800076c: 687b ldr r3, [r7, #4]
800076e: 681b ldr r3, [r3, #0]
8000770: 430a orrs r2, r1
8000772: 60da str r2, [r3, #12]
ADC_CFGR1_RES ,
hadc->Init.Resolution );
/* Configuration of ADC clock mode: clock source AHB or HSI with */
/* selectable prescaler */
MODIFY_REG(hadc->Instance->CFGR2 ,
8000774: 687b ldr r3, [r7, #4]
8000776: 681b ldr r3, [r3, #0]
8000778: 691b ldr r3, [r3, #16]
800077a: 009b lsls r3, r3, #2
800077c: 0899 lsrs r1, r3, #2
800077e: 687b ldr r3, [r7, #4]
8000780: 685a ldr r2, [r3, #4]
8000782: 687b ldr r3, [r7, #4]
8000784: 681b ldr r3, [r3, #0]
8000786: 430a orrs r2, r1
8000788: 611a str r2, [r3, #16]
/* - external trigger polarity */
/* - data alignment */
/* - resolution */
/* - scan direction */
/* - DMA continuous request */
hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN |
800078a: 687b ldr r3, [r7, #4]
800078c: 681b ldr r3, [r3, #0]
800078e: 68da ldr r2, [r3, #12]
8000790: 687b ldr r3, [r7, #4]
8000792: 681b ldr r3, [r3, #0]
8000794: 4964 ldr r1, [pc, #400] ; (8000928 <HAL_ADC_Init+0x278>)
8000796: 400a ands r2, r1
8000798: 60da str r2, [r3, #12]
ADC_CFGR1_EXTEN |
ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG );
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800079a: 687b ldr r3, [r7, #4]
800079c: 7e1b ldrb r3, [r3, #24]
800079e: 039a lsls r2, r3, #14
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
80007a0: 687b ldr r3, [r7, #4]
80007a2: 7e5b ldrb r3, [r3, #25]
80007a4: 03db lsls r3, r3, #15
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
80007a6: 431a orrs r2, r3
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80007a8: 687b ldr r3, [r7, #4]
80007aa: 7e9b ldrb r3, [r3, #26]
80007ac: 035b lsls r3, r3, #13
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
80007ae: 431a orrs r2, r3
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
80007b0: 687b ldr r3, [r7, #4]
80007b2: 6a9b ldr r3, [r3, #40] ; 0x28
80007b4: 2b01 cmp r3, #1
80007b6: d002 beq.n 80007be <HAL_ADC_Init+0x10e>
80007b8: 2380 movs r3, #128 ; 0x80
80007ba: 015b lsls r3, r3, #5
80007bc: e000 b.n 80007c0 <HAL_ADC_Init+0x110>
80007be: 2300 movs r3, #0
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80007c0: 431a orrs r2, r3
hadc->Init.DataAlign |
80007c2: 687b ldr r3, [r7, #4]
80007c4: 68db ldr r3, [r3, #12]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
80007c6: 431a orrs r2, r3
ADC_SCANDIR(hadc->Init.ScanConvMode) |
80007c8: 687b ldr r3, [r7, #4]
80007ca: 691b ldr r3, [r3, #16]
80007cc: 2b02 cmp r3, #2
80007ce: d101 bne.n 80007d4 <HAL_ADC_Init+0x124>
80007d0: 2304 movs r3, #4
80007d2: e000 b.n 80007d6 <HAL_ADC_Init+0x126>
80007d4: 2300 movs r3, #0
hadc->Init.DataAlign |
80007d6: 431a orrs r2, r3
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
80007d8: 687b ldr r3, [r7, #4]
80007da: 2124 movs r1, #36 ; 0x24
80007dc: 5c5b ldrb r3, [r3, r1]
80007de: 005b lsls r3, r3, #1
ADC_SCANDIR(hadc->Init.ScanConvMode) |
80007e0: 4313 orrs r3, r2
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
80007e2: 68ba ldr r2, [r7, #8]
80007e4: 4313 orrs r3, r2
80007e6: 60bb str r3, [r7, #8]
/* Enable discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80007e8: 687b ldr r3, [r7, #4]
80007ea: 7edb ldrb r3, [r3, #27]
80007ec: 2b01 cmp r3, #1
80007ee: d115 bne.n 800081c <HAL_ADC_Init+0x16c>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
80007f0: 687b ldr r3, [r7, #4]
80007f2: 7e9b ldrb r3, [r3, #26]
80007f4: 2b00 cmp r3, #0
80007f6: d105 bne.n 8000804 <HAL_ADC_Init+0x154>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
80007f8: 68bb ldr r3, [r7, #8]
80007fa: 2280 movs r2, #128 ; 0x80
80007fc: 0252 lsls r2, r2, #9
80007fe: 4313 orrs r3, r2
8000800: 60bb str r3, [r7, #8]
8000802: e00b b.n 800081c <HAL_ADC_Init+0x16c>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000804: 687b ldr r3, [r7, #4]
8000806: 6b9b ldr r3, [r3, #56] ; 0x38
8000808: 2220 movs r2, #32
800080a: 431a orrs r2, r3
800080c: 687b ldr r3, [r7, #4]
800080e: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000810: 687b ldr r3, [r7, #4]
8000812: 6bdb ldr r3, [r3, #60] ; 0x3c
8000814: 2201 movs r2, #1
8000816: 431a orrs r2, r3
8000818: 687b ldr r3, [r7, #4]
800081a: 63da str r2, [r3, #60] ; 0x3c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
800081c: 687b ldr r3, [r7, #4]
800081e: 69da ldr r2, [r3, #28]
8000820: 23c2 movs r3, #194 ; 0xc2
8000822: 33ff adds r3, #255 ; 0xff
8000824: 429a cmp r2, r3
8000826: d007 beq.n 8000838 <HAL_ADC_Init+0x188>
{
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000828: 687b ldr r3, [r7, #4]
800082a: 69da ldr r2, [r3, #28]
hadc->Init.ExternalTrigConvEdge );
800082c: 687b ldr r3, [r7, #4]
800082e: 6a1b ldr r3, [r3, #32]
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000830: 4313 orrs r3, r2
8000832: 68ba ldr r2, [r7, #8]
8000834: 4313 orrs r3, r2
8000836: 60bb str r3, [r7, #8]
}
/* Update ADC configuration register with previous settings */
hadc->Instance->CFGR1 |= tmpCFGR1;
8000838: 687b ldr r3, [r7, #4]
800083a: 681b ldr r3, [r3, #0]
800083c: 68d9 ldr r1, [r3, #12]
800083e: 687b ldr r3, [r7, #4]
8000840: 681b ldr r3, [r3, #0]
8000842: 68ba ldr r2, [r7, #8]
8000844: 430a orrs r2, r1
8000846: 60da str r2, [r3, #12]
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function if parameter */
/* "SamplingTimeCommon" has been set to a valid sampling time. */
/* Otherwise, sampling time is set into ADC channel initialization */
/* structure with parameter "SamplingTime" (obsolete). */
if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000848: 687b ldr r3, [r7, #4]
800084a: 6ada ldr r2, [r3, #44] ; 0x2c
800084c: 2380 movs r3, #128 ; 0x80
800084e: 055b lsls r3, r3, #21
8000850: 429a cmp r2, r3
8000852: d01b beq.n 800088c <HAL_ADC_Init+0x1dc>
8000854: 687b ldr r3, [r7, #4]
8000856: 6adb ldr r3, [r3, #44] ; 0x2c
8000858: 2b01 cmp r3, #1
800085a: d017 beq.n 800088c <HAL_ADC_Init+0x1dc>
800085c: 687b ldr r3, [r7, #4]
800085e: 6adb ldr r3, [r3, #44] ; 0x2c
8000860: 2b02 cmp r3, #2
8000862: d013 beq.n 800088c <HAL_ADC_Init+0x1dc>
8000864: 687b ldr r3, [r7, #4]
8000866: 6adb ldr r3, [r3, #44] ; 0x2c
8000868: 2b03 cmp r3, #3
800086a: d00f beq.n 800088c <HAL_ADC_Init+0x1dc>
800086c: 687b ldr r3, [r7, #4]
800086e: 6adb ldr r3, [r3, #44] ; 0x2c
8000870: 2b04 cmp r3, #4
8000872: d00b beq.n 800088c <HAL_ADC_Init+0x1dc>
8000874: 687b ldr r3, [r7, #4]
8000876: 6adb ldr r3, [r3, #44] ; 0x2c
8000878: 2b05 cmp r3, #5
800087a: d007 beq.n 800088c <HAL_ADC_Init+0x1dc>
800087c: 687b ldr r3, [r7, #4]
800087e: 6adb ldr r3, [r3, #44] ; 0x2c
8000880: 2b06 cmp r3, #6
8000882: d003 beq.n 800088c <HAL_ADC_Init+0x1dc>
8000884: 687b ldr r3, [r7, #4]
8000886: 6adb ldr r3, [r3, #44] ; 0x2c
8000888: 2b07 cmp r3, #7
800088a: d112 bne.n 80008b2 <HAL_ADC_Init+0x202>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
800088c: 687b ldr r3, [r7, #4]
800088e: 681b ldr r3, [r3, #0]
8000890: 695a ldr r2, [r3, #20]
8000892: 687b ldr r3, [r7, #4]
8000894: 681b ldr r3, [r3, #0]
8000896: 2107 movs r1, #7
8000898: 438a bics r2, r1
800089a: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
800089c: 687b ldr r3, [r7, #4]
800089e: 681b ldr r3, [r3, #0]
80008a0: 6959 ldr r1, [r3, #20]
80008a2: 687b ldr r3, [r7, #4]
80008a4: 6adb ldr r3, [r3, #44] ; 0x2c
80008a6: 2207 movs r2, #7
80008a8: 401a ands r2, r3
80008aa: 687b ldr r3, [r7, #4]
80008ac: 681b ldr r3, [r3, #0]
80008ae: 430a orrs r2, r1
80008b0: 615a str r2, [r3, #20]
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
/* set into separate dedicated function, and bits of ADC resolution set */
/* out of temporary variable 'tmpCFGR1'). */
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
80008b2: 687b ldr r3, [r7, #4]
80008b4: 681b ldr r3, [r3, #0]
80008b6: 68db ldr r3, [r3, #12]
80008b8: 4a1c ldr r2, [pc, #112] ; (800092c <HAL_ADC_Init+0x27c>)
80008ba: 4013 ands r3, r2
80008bc: 68ba ldr r2, [r7, #8]
80008be: 429a cmp r2, r3
80008c0: d10b bne.n 80008da <HAL_ADC_Init+0x22a>
== tmpCFGR1)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
80008c2: 687b ldr r3, [r7, #4]
80008c4: 2200 movs r2, #0
80008c6: 63da str r2, [r3, #60] ; 0x3c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
80008c8: 687b ldr r3, [r7, #4]
80008ca: 6b9b ldr r3, [r3, #56] ; 0x38
80008cc: 2203 movs r2, #3
80008ce: 4393 bics r3, r2
80008d0: 2201 movs r2, #1
80008d2: 431a orrs r2, r3
80008d4: 687b ldr r3, [r7, #4]
80008d6: 639a str r2, [r3, #56] ; 0x38
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
80008d8: e01c b.n 8000914 <HAL_ADC_Init+0x264>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
80008da: 687b ldr r3, [r7, #4]
80008dc: 6b9b ldr r3, [r3, #56] ; 0x38
80008de: 2212 movs r2, #18
80008e0: 4393 bics r3, r2
80008e2: 2210 movs r2, #16
80008e4: 431a orrs r2, r3
80008e6: 687b ldr r3, [r7, #4]
80008e8: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80008ea: 687b ldr r3, [r7, #4]
80008ec: 6bdb ldr r3, [r3, #60] ; 0x3c
80008ee: 2201 movs r2, #1
80008f0: 431a orrs r2, r3
80008f2: 687b ldr r3, [r7, #4]
80008f4: 63da str r2, [r3, #60] ; 0x3c
tmp_hal_status = HAL_ERROR;
80008f6: 230f movs r3, #15
80008f8: 18fb adds r3, r7, r3
80008fa: 2201 movs r2, #1
80008fc: 701a strb r2, [r3, #0]
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
80008fe: e009 b.n 8000914 <HAL_ADC_Init+0x264>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000900: 687b ldr r3, [r7, #4]
8000902: 6b9b ldr r3, [r3, #56] ; 0x38
8000904: 2210 movs r2, #16
8000906: 431a orrs r2, r3
8000908: 687b ldr r3, [r7, #4]
800090a: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
800090c: 230f movs r3, #15
800090e: 18fb adds r3, r7, r3
8000910: 2201 movs r2, #1
8000912: 701a strb r2, [r3, #0]
}
/* Return function status */
return tmp_hal_status;
8000914: 230f movs r3, #15
8000916: 18fb adds r3, r7, r3
8000918: 781b ldrb r3, [r3, #0]
}
800091a: 0018 movs r0, r3
800091c: 46bd mov sp, r7
800091e: b004 add sp, #16
8000920: bd80 pop {r7, pc}
8000922: 46c0 nop ; (mov r8, r8)
8000924: fffffefd .word 0xfffffefd
8000928: fffe0219 .word 0xfffe0219
800092c: 833fffe7 .word 0x833fffe7
08000930 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8000930: b580 push {r7, lr}
8000932: b084 sub sp, #16
8000934: af00 add r7, sp, #0
8000936: 6078 str r0, [r7, #4]
8000938: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800093a: 230f movs r3, #15
800093c: 18fb adds r3, r7, r3
800093e: 2200 movs r2, #0
8000940: 701a strb r2, [r3, #0]
__IO uint32_t wait_loop_index = 0U;
8000942: 2300 movs r3, #0
8000944: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_RANK(sConfig->Rank));
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000946: 687b ldr r3, [r7, #4]
8000948: 6ada ldr r2, [r3, #44] ; 0x2c
800094a: 2380 movs r3, #128 ; 0x80
800094c: 055b lsls r3, r3, #21
800094e: 429a cmp r2, r3
8000950: d011 beq.n 8000976 <HAL_ADC_ConfigChannel+0x46>
8000952: 687b ldr r3, [r7, #4]
8000954: 6adb ldr r3, [r3, #44] ; 0x2c
8000956: 2b01 cmp r3, #1
8000958: d00d beq.n 8000976 <HAL_ADC_ConfigChannel+0x46>
800095a: 687b ldr r3, [r7, #4]
800095c: 6adb ldr r3, [r3, #44] ; 0x2c
800095e: 2b02 cmp r3, #2
8000960: d009 beq.n 8000976 <HAL_ADC_ConfigChannel+0x46>
8000962: 687b ldr r3, [r7, #4]
8000964: 6adb ldr r3, [r3, #44] ; 0x2c
8000966: 2b03 cmp r3, #3
8000968: d005 beq.n 8000976 <HAL_ADC_ConfigChannel+0x46>
800096a: 687b ldr r3, [r7, #4]
800096c: 6adb ldr r3, [r3, #44] ; 0x2c
800096e: 2b04 cmp r3, #4
8000970: d001 beq.n 8000976 <HAL_ADC_ConfigChannel+0x46>
8000972: 687b ldr r3, [r7, #4]
8000974: 6adb ldr r3, [r3, #44] ; 0x2c
{
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
}
/* Process locked */
__HAL_LOCK(hadc);
8000976: 687b ldr r3, [r7, #4]
8000978: 2234 movs r2, #52 ; 0x34
800097a: 5c9b ldrb r3, [r3, r2]
800097c: 2b01 cmp r3, #1
800097e: d101 bne.n 8000984 <HAL_ADC_ConfigChannel+0x54>
8000980: 2302 movs r3, #2
8000982: e0bb b.n 8000afc <HAL_ADC_ConfigChannel+0x1cc>
8000984: 687b ldr r3, [r7, #4]
8000986: 2234 movs r2, #52 ; 0x34
8000988: 2101 movs r1, #1
800098a: 5499 strb r1, [r3, r2]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
800098c: 687b ldr r3, [r7, #4]
800098e: 681b ldr r3, [r3, #0]
8000990: 689b ldr r3, [r3, #8]
8000992: 2204 movs r2, #4
8000994: 4013 ands r3, r2
8000996: d000 beq.n 800099a <HAL_ADC_ConfigChannel+0x6a>
8000998: e09f b.n 8000ada <HAL_ADC_ConfigChannel+0x1aa>
{
/* Configure channel: depending on rank setting, add it or remove it from */
/* ADC conversion sequencer. */
if (sConfig->Rank != ADC_RANK_NONE)
800099a: 683b ldr r3, [r7, #0]
800099c: 685b ldr r3, [r3, #4]
800099e: 4a59 ldr r2, [pc, #356] ; (8000b04 <HAL_ADC_ConfigChannel+0x1d4>)
80009a0: 4293 cmp r3, r2
80009a2: d100 bne.n 80009a6 <HAL_ADC_ConfigChannel+0x76>
80009a4: e077 b.n 8000a96 <HAL_ADC_ConfigChannel+0x166>
{
/* Regular sequence configuration */
/* Set the channel selection register from the selected channel */
hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
80009a6: 687b ldr r3, [r7, #4]
80009a8: 681b ldr r3, [r3, #0]
80009aa: 6a99 ldr r1, [r3, #40] ; 0x28
80009ac: 683b ldr r3, [r7, #0]
80009ae: 681b ldr r3, [r3, #0]
80009b0: 2201 movs r2, #1
80009b2: 409a lsls r2, r3
80009b4: 687b ldr r3, [r7, #4]
80009b6: 681b ldr r3, [r3, #0]
80009b8: 430a orrs r2, r1
80009ba: 629a str r2, [r3, #40] ; 0x28
/* Channel sampling time configuration */
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function with */
/* parameter "SamplingTime" (obsolete) only if not already set into */
/* ADC initialization structure with parameter "SamplingTimeCommon". */
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
80009bc: 687b ldr r3, [r7, #4]
80009be: 6ada ldr r2, [r3, #44] ; 0x2c
80009c0: 2380 movs r3, #128 ; 0x80
80009c2: 055b lsls r3, r3, #21
80009c4: 429a cmp r2, r3
80009c6: d037 beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009c8: 687b ldr r3, [r7, #4]
80009ca: 6adb ldr r3, [r3, #44] ; 0x2c
80009cc: 2b01 cmp r3, #1
80009ce: d033 beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009d0: 687b ldr r3, [r7, #4]
80009d2: 6adb ldr r3, [r3, #44] ; 0x2c
80009d4: 2b02 cmp r3, #2
80009d6: d02f beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009d8: 687b ldr r3, [r7, #4]
80009da: 6adb ldr r3, [r3, #44] ; 0x2c
80009dc: 2b03 cmp r3, #3
80009de: d02b beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009e0: 687b ldr r3, [r7, #4]
80009e2: 6adb ldr r3, [r3, #44] ; 0x2c
80009e4: 2b04 cmp r3, #4
80009e6: d027 beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009e8: 687b ldr r3, [r7, #4]
80009ea: 6adb ldr r3, [r3, #44] ; 0x2c
80009ec: 2b05 cmp r3, #5
80009ee: d023 beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009f0: 687b ldr r3, [r7, #4]
80009f2: 6adb ldr r3, [r3, #44] ; 0x2c
80009f4: 2b06 cmp r3, #6
80009f6: d01f beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
80009f8: 687b ldr r3, [r7, #4]
80009fa: 6adb ldr r3, [r3, #44] ; 0x2c
80009fc: 2b07 cmp r3, #7
80009fe: d01b beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
{
/* Modify sampling time if needed (not needed in case of reoccurrence */
/* for several channels programmed consecutively into the sequencer) */
if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
8000a00: 683b ldr r3, [r7, #0]
8000a02: 689a ldr r2, [r3, #8]
8000a04: 687b ldr r3, [r7, #4]
8000a06: 681b ldr r3, [r3, #0]
8000a08: 695b ldr r3, [r3, #20]
8000a0a: 2107 movs r1, #7
8000a0c: 400b ands r3, r1
8000a0e: 429a cmp r2, r3
8000a10: d012 beq.n 8000a38 <HAL_ADC_ConfigChannel+0x108>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000a12: 687b ldr r3, [r7, #4]
8000a14: 681b ldr r3, [r3, #0]
8000a16: 695a ldr r2, [r3, #20]
8000a18: 687b ldr r3, [r7, #4]
8000a1a: 681b ldr r3, [r3, #0]
8000a1c: 2107 movs r1, #7
8000a1e: 438a bics r2, r1
8000a20: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
8000a22: 687b ldr r3, [r7, #4]
8000a24: 681b ldr r3, [r3, #0]
8000a26: 6959 ldr r1, [r3, #20]
8000a28: 683b ldr r3, [r7, #0]
8000a2a: 689b ldr r3, [r3, #8]
8000a2c: 2207 movs r2, #7
8000a2e: 401a ands r2, r3
8000a30: 687b ldr r3, [r7, #4]
8000a32: 681b ldr r3, [r3, #0]
8000a34: 430a orrs r2, r1
8000a36: 615a str r2, [r3, #20]
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000a38: 683b ldr r3, [r7, #0]
8000a3a: 681b ldr r3, [r3, #0]
8000a3c: 2b10 cmp r3, #16
8000a3e: d003 beq.n 8000a48 <HAL_ADC_ConfigChannel+0x118>
8000a40: 683b ldr r3, [r7, #0]
8000a42: 681b ldr r3, [r3, #0]
8000a44: 2b11 cmp r3, #17
8000a46: d152 bne.n 8000aee <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, enable Temp. sensor measurement path. */
/* If Channel_17 is selected, enable VREFINT measurement path. */
/* If Channel_18 is selected, enable VBAT measurement path. */
ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000a48: 4b2f ldr r3, [pc, #188] ; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
8000a4a: 6819 ldr r1, [r3, #0]
8000a4c: 683b ldr r3, [r7, #0]
8000a4e: 681b ldr r3, [r3, #0]
8000a50: 2b10 cmp r3, #16
8000a52: d102 bne.n 8000a5a <HAL_ADC_ConfigChannel+0x12a>
8000a54: 2380 movs r3, #128 ; 0x80
8000a56: 041b lsls r3, r3, #16
8000a58: e001 b.n 8000a5e <HAL_ADC_ConfigChannel+0x12e>
8000a5a: 2380 movs r3, #128 ; 0x80
8000a5c: 03db lsls r3, r3, #15
8000a5e: 4a2a ldr r2, [pc, #168] ; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
8000a60: 430b orrs r3, r1
8000a62: 6013 str r3, [r2, #0]
/* If Temp. sensor is selected, wait for stabilization delay */
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8000a64: 683b ldr r3, [r7, #0]
8000a66: 681b ldr r3, [r3, #0]
8000a68: 2b10 cmp r3, #16
8000a6a: d140 bne.n 8000aee <HAL_ADC_ConfigChannel+0x1be>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8000a6c: 4b27 ldr r3, [pc, #156] ; (8000b0c <HAL_ADC_ConfigChannel+0x1dc>)
8000a6e: 681b ldr r3, [r3, #0]
8000a70: 4927 ldr r1, [pc, #156] ; (8000b10 <HAL_ADC_ConfigChannel+0x1e0>)
8000a72: 0018 movs r0, r3
8000a74: f7ff fb48 bl 8000108 <__udivsi3>
8000a78: 0003 movs r3, r0
8000a7a: 001a movs r2, r3
8000a7c: 0013 movs r3, r2
8000a7e: 009b lsls r3, r3, #2
8000a80: 189b adds r3, r3, r2
8000a82: 005b lsls r3, r3, #1
8000a84: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000a86: e002 b.n 8000a8e <HAL_ADC_ConfigChannel+0x15e>
{
wait_loop_index--;
8000a88: 68bb ldr r3, [r7, #8]
8000a8a: 3b01 subs r3, #1
8000a8c: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000a8e: 68bb ldr r3, [r7, #8]
8000a90: 2b00 cmp r3, #0
8000a92: d1f9 bne.n 8000a88 <HAL_ADC_ConfigChannel+0x158>
8000a94: e02b b.n 8000aee <HAL_ADC_ConfigChannel+0x1be>
}
else
{
/* Regular sequence configuration */
/* Reset the channel selection register from the selected channel */
hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
8000a96: 687b ldr r3, [r7, #4]
8000a98: 681b ldr r3, [r3, #0]
8000a9a: 6a9a ldr r2, [r3, #40] ; 0x28
8000a9c: 683b ldr r3, [r7, #0]
8000a9e: 681b ldr r3, [r3, #0]
8000aa0: 2101 movs r1, #1
8000aa2: 4099 lsls r1, r3
8000aa4: 000b movs r3, r1
8000aa6: 43d9 mvns r1, r3
8000aa8: 687b ldr r3, [r7, #4]
8000aaa: 681b ldr r3, [r3, #0]
8000aac: 400a ands r2, r1
8000aae: 629a str r2, [r3, #40] ; 0x28
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths disable: If internal channel selected, */
/* disable dedicated internal buffers and path. */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000ab0: 683b ldr r3, [r7, #0]
8000ab2: 681b ldr r3, [r3, #0]
8000ab4: 2b10 cmp r3, #16
8000ab6: d003 beq.n 8000ac0 <HAL_ADC_ConfigChannel+0x190>
8000ab8: 683b ldr r3, [r7, #0]
8000aba: 681b ldr r3, [r3, #0]
8000abc: 2b11 cmp r3, #17
8000abe: d116 bne.n 8000aee <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, disable Temp. sensor measurement path. */
/* If Channel_17 is selected, disable VREFINT measurement path. */
/* If Channel_18 is selected, disable VBAT measurement path. */
ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000ac0: 4b11 ldr r3, [pc, #68] ; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
8000ac2: 6819 ldr r1, [r3, #0]
8000ac4: 683b ldr r3, [r7, #0]
8000ac6: 681b ldr r3, [r3, #0]
8000ac8: 2b10 cmp r3, #16
8000aca: d101 bne.n 8000ad0 <HAL_ADC_ConfigChannel+0x1a0>
8000acc: 4a11 ldr r2, [pc, #68] ; (8000b14 <HAL_ADC_ConfigChannel+0x1e4>)
8000ace: e000 b.n 8000ad2 <HAL_ADC_ConfigChannel+0x1a2>
8000ad0: 4a11 ldr r2, [pc, #68] ; (8000b18 <HAL_ADC_ConfigChannel+0x1e8>)
8000ad2: 4b0d ldr r3, [pc, #52] ; (8000b08 <HAL_ADC_ConfigChannel+0x1d8>)
8000ad4: 400a ands r2, r1
8000ad6: 601a str r2, [r3, #0]
8000ad8: e009 b.n 8000aee <HAL_ADC_ConfigChannel+0x1be>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000ada: 687b ldr r3, [r7, #4]
8000adc: 6b9b ldr r3, [r3, #56] ; 0x38
8000ade: 2220 movs r2, #32
8000ae0: 431a orrs r2, r3
8000ae2: 687b ldr r3, [r7, #4]
8000ae4: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
8000ae6: 230f movs r3, #15
8000ae8: 18fb adds r3, r7, r3
8000aea: 2201 movs r2, #1
8000aec: 701a strb r2, [r3, #0]
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000aee: 687b ldr r3, [r7, #4]
8000af0: 2234 movs r2, #52 ; 0x34
8000af2: 2100 movs r1, #0
8000af4: 5499 strb r1, [r3, r2]
/* Return function status */
return tmp_hal_status;
8000af6: 230f movs r3, #15
8000af8: 18fb adds r3, r7, r3
8000afa: 781b ldrb r3, [r3, #0]
}
8000afc: 0018 movs r0, r3
8000afe: 46bd mov sp, r7
8000b00: b004 add sp, #16
8000b02: bd80 pop {r7, pc}
8000b04: 00001001 .word 0x00001001
8000b08: 40012708 .word 0x40012708
8000b0c: 20000000 .word 0x20000000
8000b10: 000f4240 .word 0x000f4240
8000b14: ff7fffff .word 0xff7fffff
8000b18: ffbfffff .word 0xffbfffff
08000b1c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000b1c: b590 push {r4, r7, lr}
8000b1e: b083 sub sp, #12
8000b20: af00 add r7, sp, #0
8000b22: 0002 movs r2, r0
8000b24: 6039 str r1, [r7, #0]
8000b26: 1dfb adds r3, r7, #7
8000b28: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8000b2a: 1dfb adds r3, r7, #7
8000b2c: 781b ldrb r3, [r3, #0]
8000b2e: 2b7f cmp r3, #127 ; 0x7f
8000b30: d828 bhi.n 8000b84 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000b32: 4a2f ldr r2, [pc, #188] ; (8000bf0 <__NVIC_SetPriority+0xd4>)
8000b34: 1dfb adds r3, r7, #7
8000b36: 781b ldrb r3, [r3, #0]
8000b38: b25b sxtb r3, r3
8000b3a: 089b lsrs r3, r3, #2
8000b3c: 33c0 adds r3, #192 ; 0xc0
8000b3e: 009b lsls r3, r3, #2
8000b40: 589b ldr r3, [r3, r2]
8000b42: 1dfa adds r2, r7, #7
8000b44: 7812 ldrb r2, [r2, #0]
8000b46: 0011 movs r1, r2
8000b48: 2203 movs r2, #3
8000b4a: 400a ands r2, r1
8000b4c: 00d2 lsls r2, r2, #3
8000b4e: 21ff movs r1, #255 ; 0xff
8000b50: 4091 lsls r1, r2
8000b52: 000a movs r2, r1
8000b54: 43d2 mvns r2, r2
8000b56: 401a ands r2, r3
8000b58: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000b5a: 683b ldr r3, [r7, #0]
8000b5c: 019b lsls r3, r3, #6
8000b5e: 22ff movs r2, #255 ; 0xff
8000b60: 401a ands r2, r3
8000b62: 1dfb adds r3, r7, #7
8000b64: 781b ldrb r3, [r3, #0]
8000b66: 0018 movs r0, r3
8000b68: 2303 movs r3, #3
8000b6a: 4003 ands r3, r0
8000b6c: 00db lsls r3, r3, #3
8000b6e: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000b70: 481f ldr r0, [pc, #124] ; (8000bf0 <__NVIC_SetPriority+0xd4>)
8000b72: 1dfb adds r3, r7, #7
8000b74: 781b ldrb r3, [r3, #0]
8000b76: b25b sxtb r3, r3
8000b78: 089b lsrs r3, r3, #2
8000b7a: 430a orrs r2, r1
8000b7c: 33c0 adds r3, #192 ; 0xc0
8000b7e: 009b lsls r3, r3, #2
8000b80: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000b82: e031 b.n 8000be8 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000b84: 4a1b ldr r2, [pc, #108] ; (8000bf4 <__NVIC_SetPriority+0xd8>)
8000b86: 1dfb adds r3, r7, #7
8000b88: 781b ldrb r3, [r3, #0]
8000b8a: 0019 movs r1, r3
8000b8c: 230f movs r3, #15
8000b8e: 400b ands r3, r1
8000b90: 3b08 subs r3, #8
8000b92: 089b lsrs r3, r3, #2
8000b94: 3306 adds r3, #6
8000b96: 009b lsls r3, r3, #2
8000b98: 18d3 adds r3, r2, r3
8000b9a: 3304 adds r3, #4
8000b9c: 681b ldr r3, [r3, #0]
8000b9e: 1dfa adds r2, r7, #7
8000ba0: 7812 ldrb r2, [r2, #0]
8000ba2: 0011 movs r1, r2
8000ba4: 2203 movs r2, #3
8000ba6: 400a ands r2, r1
8000ba8: 00d2 lsls r2, r2, #3
8000baa: 21ff movs r1, #255 ; 0xff
8000bac: 4091 lsls r1, r2
8000bae: 000a movs r2, r1
8000bb0: 43d2 mvns r2, r2
8000bb2: 401a ands r2, r3
8000bb4: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000bb6: 683b ldr r3, [r7, #0]
8000bb8: 019b lsls r3, r3, #6
8000bba: 22ff movs r2, #255 ; 0xff
8000bbc: 401a ands r2, r3
8000bbe: 1dfb adds r3, r7, #7
8000bc0: 781b ldrb r3, [r3, #0]
8000bc2: 0018 movs r0, r3
8000bc4: 2303 movs r3, #3
8000bc6: 4003 ands r3, r0
8000bc8: 00db lsls r3, r3, #3
8000bca: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000bcc: 4809 ldr r0, [pc, #36] ; (8000bf4 <__NVIC_SetPriority+0xd8>)
8000bce: 1dfb adds r3, r7, #7
8000bd0: 781b ldrb r3, [r3, #0]
8000bd2: 001c movs r4, r3
8000bd4: 230f movs r3, #15
8000bd6: 4023 ands r3, r4
8000bd8: 3b08 subs r3, #8
8000bda: 089b lsrs r3, r3, #2
8000bdc: 430a orrs r2, r1
8000bde: 3306 adds r3, #6
8000be0: 009b lsls r3, r3, #2
8000be2: 18c3 adds r3, r0, r3
8000be4: 3304 adds r3, #4
8000be6: 601a str r2, [r3, #0]
}
8000be8: 46c0 nop ; (mov r8, r8)
8000bea: 46bd mov sp, r7
8000bec: b003 add sp, #12
8000bee: bd90 pop {r4, r7, pc}
8000bf0: e000e100 .word 0xe000e100
8000bf4: e000ed00 .word 0xe000ed00
08000bf8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000bf8: b580 push {r7, lr}
8000bfa: b082 sub sp, #8
8000bfc: af00 add r7, sp, #0
8000bfe: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000c00: 687b ldr r3, [r7, #4]
8000c02: 1e5a subs r2, r3, #1
8000c04: 2380 movs r3, #128 ; 0x80
8000c06: 045b lsls r3, r3, #17
8000c08: 429a cmp r2, r3
8000c0a: d301 bcc.n 8000c10 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8000c0c: 2301 movs r3, #1
8000c0e: e010 b.n 8000c32 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000c10: 4b0a ldr r3, [pc, #40] ; (8000c3c <SysTick_Config+0x44>)
8000c12: 687a ldr r2, [r7, #4]
8000c14: 3a01 subs r2, #1
8000c16: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000c18: 2301 movs r3, #1
8000c1a: 425b negs r3, r3
8000c1c: 2103 movs r1, #3
8000c1e: 0018 movs r0, r3
8000c20: f7ff ff7c bl 8000b1c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000c24: 4b05 ldr r3, [pc, #20] ; (8000c3c <SysTick_Config+0x44>)
8000c26: 2200 movs r2, #0
8000c28: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000c2a: 4b04 ldr r3, [pc, #16] ; (8000c3c <SysTick_Config+0x44>)
8000c2c: 2207 movs r2, #7
8000c2e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000c30: 2300 movs r3, #0
}
8000c32: 0018 movs r0, r3
8000c34: 46bd mov sp, r7
8000c36: b002 add sp, #8
8000c38: bd80 pop {r7, pc}
8000c3a: 46c0 nop ; (mov r8, r8)
8000c3c: e000e010 .word 0xe000e010
08000c40 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000c40: b580 push {r7, lr}
8000c42: b084 sub sp, #16
8000c44: af00 add r7, sp, #0
8000c46: 60b9 str r1, [r7, #8]
8000c48: 607a str r2, [r7, #4]
8000c4a: 210f movs r1, #15
8000c4c: 187b adds r3, r7, r1
8000c4e: 1c02 adds r2, r0, #0
8000c50: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
8000c52: 68ba ldr r2, [r7, #8]
8000c54: 187b adds r3, r7, r1
8000c56: 781b ldrb r3, [r3, #0]
8000c58: b25b sxtb r3, r3
8000c5a: 0011 movs r1, r2
8000c5c: 0018 movs r0, r3
8000c5e: f7ff ff5d bl 8000b1c <__NVIC_SetPriority>
}
8000c62: 46c0 nop ; (mov r8, r8)
8000c64: 46bd mov sp, r7
8000c66: b004 add sp, #16
8000c68: bd80 pop {r7, pc}
08000c6a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000c6a: b580 push {r7, lr}
8000c6c: b082 sub sp, #8
8000c6e: af00 add r7, sp, #0
8000c70: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000c72: 687b ldr r3, [r7, #4]
8000c74: 0018 movs r0, r3
8000c76: f7ff ffbf bl 8000bf8 <SysTick_Config>
8000c7a: 0003 movs r3, r0
}
8000c7c: 0018 movs r0, r3
8000c7e: 46bd mov sp, r7
8000c80: b002 add sp, #8
8000c82: bd80 pop {r7, pc}
08000c84 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000c84: b580 push {r7, lr}
8000c86: b086 sub sp, #24
8000c88: af00 add r7, sp, #0
8000c8a: 6078 str r0, [r7, #4]
8000c8c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000c8e: 2300 movs r3, #0
8000c90: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000c92: e14f b.n 8000f34 <HAL_GPIO_Init+0x2b0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8000c94: 683b ldr r3, [r7, #0]
8000c96: 681b ldr r3, [r3, #0]
8000c98: 2101 movs r1, #1
8000c9a: 697a ldr r2, [r7, #20]
8000c9c: 4091 lsls r1, r2
8000c9e: 000a movs r2, r1
8000ca0: 4013 ands r3, r2
8000ca2: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8000ca4: 68fb ldr r3, [r7, #12]
8000ca6: 2b00 cmp r3, #0
8000ca8: d100 bne.n 8000cac <HAL_GPIO_Init+0x28>
8000caa: e140 b.n 8000f2e <HAL_GPIO_Init+0x2aa>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000cac: 683b ldr r3, [r7, #0]
8000cae: 685b ldr r3, [r3, #4]
8000cb0: 2203 movs r2, #3
8000cb2: 4013 ands r3, r2
8000cb4: 2b01 cmp r3, #1
8000cb6: d005 beq.n 8000cc4 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8000cb8: 683b ldr r3, [r7, #0]
8000cba: 685b ldr r3, [r3, #4]
8000cbc: 2203 movs r2, #3
8000cbe: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000cc0: 2b02 cmp r3, #2
8000cc2: d130 bne.n 8000d26 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000cc4: 687b ldr r3, [r7, #4]
8000cc6: 689b ldr r3, [r3, #8]
8000cc8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8000cca: 697b ldr r3, [r7, #20]
8000ccc: 005b lsls r3, r3, #1
8000cce: 2203 movs r2, #3
8000cd0: 409a lsls r2, r3
8000cd2: 0013 movs r3, r2
8000cd4: 43da mvns r2, r3
8000cd6: 693b ldr r3, [r7, #16]
8000cd8: 4013 ands r3, r2
8000cda: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8000cdc: 683b ldr r3, [r7, #0]
8000cde: 68da ldr r2, [r3, #12]
8000ce0: 697b ldr r3, [r7, #20]
8000ce2: 005b lsls r3, r3, #1
8000ce4: 409a lsls r2, r3
8000ce6: 0013 movs r3, r2
8000ce8: 693a ldr r2, [r7, #16]
8000cea: 4313 orrs r3, r2
8000cec: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000cee: 687b ldr r3, [r7, #4]
8000cf0: 693a ldr r2, [r7, #16]
8000cf2: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 685b ldr r3, [r3, #4]
8000cf8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000cfa: 2201 movs r2, #1
8000cfc: 697b ldr r3, [r7, #20]
8000cfe: 409a lsls r2, r3
8000d00: 0013 movs r3, r2
8000d02: 43da mvns r2, r3
8000d04: 693b ldr r3, [r7, #16]
8000d06: 4013 ands r3, r2
8000d08: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000d0a: 683b ldr r3, [r7, #0]
8000d0c: 685b ldr r3, [r3, #4]
8000d0e: 091b lsrs r3, r3, #4
8000d10: 2201 movs r2, #1
8000d12: 401a ands r2, r3
8000d14: 697b ldr r3, [r7, #20]
8000d16: 409a lsls r2, r3
8000d18: 0013 movs r3, r2
8000d1a: 693a ldr r2, [r7, #16]
8000d1c: 4313 orrs r3, r2
8000d1e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000d20: 687b ldr r3, [r7, #4]
8000d22: 693a ldr r2, [r7, #16]
8000d24: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000d26: 683b ldr r3, [r7, #0]
8000d28: 685b ldr r3, [r3, #4]
8000d2a: 2203 movs r2, #3
8000d2c: 4013 ands r3, r2
8000d2e: 2b03 cmp r3, #3
8000d30: d017 beq.n 8000d62 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000d32: 687b ldr r3, [r7, #4]
8000d34: 68db ldr r3, [r3, #12]
8000d36: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8000d38: 697b ldr r3, [r7, #20]
8000d3a: 005b lsls r3, r3, #1
8000d3c: 2203 movs r2, #3
8000d3e: 409a lsls r2, r3
8000d40: 0013 movs r3, r2
8000d42: 43da mvns r2, r3
8000d44: 693b ldr r3, [r7, #16]
8000d46: 4013 ands r3, r2
8000d48: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8000d4a: 683b ldr r3, [r7, #0]
8000d4c: 689a ldr r2, [r3, #8]
8000d4e: 697b ldr r3, [r7, #20]
8000d50: 005b lsls r3, r3, #1
8000d52: 409a lsls r2, r3
8000d54: 0013 movs r3, r2
8000d56: 693a ldr r2, [r7, #16]
8000d58: 4313 orrs r3, r2
8000d5a: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000d5c: 687b ldr r3, [r7, #4]
8000d5e: 693a ldr r2, [r7, #16]
8000d60: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000d62: 683b ldr r3, [r7, #0]
8000d64: 685b ldr r3, [r3, #4]
8000d66: 2203 movs r2, #3
8000d68: 4013 ands r3, r2
8000d6a: 2b02 cmp r3, #2
8000d6c: d123 bne.n 8000db6 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8000d6e: 697b ldr r3, [r7, #20]
8000d70: 08da lsrs r2, r3, #3
8000d72: 687b ldr r3, [r7, #4]
8000d74: 3208 adds r2, #8
8000d76: 0092 lsls r2, r2, #2
8000d78: 58d3 ldr r3, [r2, r3]
8000d7a: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8000d7c: 697b ldr r3, [r7, #20]
8000d7e: 2207 movs r2, #7
8000d80: 4013 ands r3, r2
8000d82: 009b lsls r3, r3, #2
8000d84: 220f movs r2, #15
8000d86: 409a lsls r2, r3
8000d88: 0013 movs r3, r2
8000d8a: 43da mvns r2, r3
8000d8c: 693b ldr r3, [r7, #16]
8000d8e: 4013 ands r3, r2
8000d90: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8000d92: 683b ldr r3, [r7, #0]
8000d94: 691a ldr r2, [r3, #16]
8000d96: 697b ldr r3, [r7, #20]
8000d98: 2107 movs r1, #7
8000d9a: 400b ands r3, r1
8000d9c: 009b lsls r3, r3, #2
8000d9e: 409a lsls r2, r3
8000da0: 0013 movs r3, r2
8000da2: 693a ldr r2, [r7, #16]
8000da4: 4313 orrs r3, r2
8000da6: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8000da8: 697b ldr r3, [r7, #20]
8000daa: 08da lsrs r2, r3, #3
8000dac: 687b ldr r3, [r7, #4]
8000dae: 3208 adds r2, #8
8000db0: 0092 lsls r2, r2, #2
8000db2: 6939 ldr r1, [r7, #16]
8000db4: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000db6: 687b ldr r3, [r7, #4]
8000db8: 681b ldr r3, [r3, #0]
8000dba: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8000dbc: 697b ldr r3, [r7, #20]
8000dbe: 005b lsls r3, r3, #1
8000dc0: 2203 movs r2, #3
8000dc2: 409a lsls r2, r3
8000dc4: 0013 movs r3, r2
8000dc6: 43da mvns r2, r3
8000dc8: 693b ldr r3, [r7, #16]
8000dca: 4013 ands r3, r2
8000dcc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8000dce: 683b ldr r3, [r7, #0]
8000dd0: 685b ldr r3, [r3, #4]
8000dd2: 2203 movs r2, #3
8000dd4: 401a ands r2, r3
8000dd6: 697b ldr r3, [r7, #20]
8000dd8: 005b lsls r3, r3, #1
8000dda: 409a lsls r2, r3
8000ddc: 0013 movs r3, r2
8000dde: 693a ldr r2, [r7, #16]
8000de0: 4313 orrs r3, r2
8000de2: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000de4: 687b ldr r3, [r7, #4]
8000de6: 693a ldr r2, [r7, #16]
8000de8: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8000dea: 683b ldr r3, [r7, #0]
8000dec: 685a ldr r2, [r3, #4]
8000dee: 23c0 movs r3, #192 ; 0xc0
8000df0: 029b lsls r3, r3, #10
8000df2: 4013 ands r3, r2
8000df4: d100 bne.n 8000df8 <HAL_GPIO_Init+0x174>
8000df6: e09a b.n 8000f2e <HAL_GPIO_Init+0x2aa>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000df8: 4b54 ldr r3, [pc, #336] ; (8000f4c <HAL_GPIO_Init+0x2c8>)
8000dfa: 699a ldr r2, [r3, #24]
8000dfc: 4b53 ldr r3, [pc, #332] ; (8000f4c <HAL_GPIO_Init+0x2c8>)
8000dfe: 2101 movs r1, #1
8000e00: 430a orrs r2, r1
8000e02: 619a str r2, [r3, #24]
8000e04: 4b51 ldr r3, [pc, #324] ; (8000f4c <HAL_GPIO_Init+0x2c8>)
8000e06: 699b ldr r3, [r3, #24]
8000e08: 2201 movs r2, #1
8000e0a: 4013 ands r3, r2
8000e0c: 60bb str r3, [r7, #8]
8000e0e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8000e10: 4a4f ldr r2, [pc, #316] ; (8000f50 <HAL_GPIO_Init+0x2cc>)
8000e12: 697b ldr r3, [r7, #20]
8000e14: 089b lsrs r3, r3, #2
8000e16: 3302 adds r3, #2
8000e18: 009b lsls r3, r3, #2
8000e1a: 589b ldr r3, [r3, r2]
8000e1c: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8000e1e: 697b ldr r3, [r7, #20]
8000e20: 2203 movs r2, #3
8000e22: 4013 ands r3, r2
8000e24: 009b lsls r3, r3, #2
8000e26: 220f movs r2, #15
8000e28: 409a lsls r2, r3
8000e2a: 0013 movs r3, r2
8000e2c: 43da mvns r2, r3
8000e2e: 693b ldr r3, [r7, #16]
8000e30: 4013 ands r3, r2
8000e32: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8000e34: 687a ldr r2, [r7, #4]
8000e36: 2390 movs r3, #144 ; 0x90
8000e38: 05db lsls r3, r3, #23
8000e3a: 429a cmp r2, r3
8000e3c: d013 beq.n 8000e66 <HAL_GPIO_Init+0x1e2>
8000e3e: 687b ldr r3, [r7, #4]
8000e40: 4a44 ldr r2, [pc, #272] ; (8000f54 <HAL_GPIO_Init+0x2d0>)
8000e42: 4293 cmp r3, r2
8000e44: d00d beq.n 8000e62 <HAL_GPIO_Init+0x1de>
8000e46: 687b ldr r3, [r7, #4]
8000e48: 4a43 ldr r2, [pc, #268] ; (8000f58 <HAL_GPIO_Init+0x2d4>)
8000e4a: 4293 cmp r3, r2
8000e4c: d007 beq.n 8000e5e <HAL_GPIO_Init+0x1da>
8000e4e: 687b ldr r3, [r7, #4]
8000e50: 4a42 ldr r2, [pc, #264] ; (8000f5c <HAL_GPIO_Init+0x2d8>)
8000e52: 4293 cmp r3, r2
8000e54: d101 bne.n 8000e5a <HAL_GPIO_Init+0x1d6>
8000e56: 2303 movs r3, #3
8000e58: e006 b.n 8000e68 <HAL_GPIO_Init+0x1e4>
8000e5a: 2305 movs r3, #5
8000e5c: e004 b.n 8000e68 <HAL_GPIO_Init+0x1e4>
8000e5e: 2302 movs r3, #2
8000e60: e002 b.n 8000e68 <HAL_GPIO_Init+0x1e4>
8000e62: 2301 movs r3, #1
8000e64: e000 b.n 8000e68 <HAL_GPIO_Init+0x1e4>
8000e66: 2300 movs r3, #0
8000e68: 697a ldr r2, [r7, #20]
8000e6a: 2103 movs r1, #3
8000e6c: 400a ands r2, r1
8000e6e: 0092 lsls r2, r2, #2
8000e70: 4093 lsls r3, r2
8000e72: 693a ldr r2, [r7, #16]
8000e74: 4313 orrs r3, r2
8000e76: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8000e78: 4935 ldr r1, [pc, #212] ; (8000f50 <HAL_GPIO_Init+0x2cc>)
8000e7a: 697b ldr r3, [r7, #20]
8000e7c: 089b lsrs r3, r3, #2
8000e7e: 3302 adds r3, #2
8000e80: 009b lsls r3, r3, #2
8000e82: 693a ldr r2, [r7, #16]
8000e84: 505a str r2, [r3, r1]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8000e86: 4b36 ldr r3, [pc, #216] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000e88: 681b ldr r3, [r3, #0]
8000e8a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000e8c: 68fb ldr r3, [r7, #12]
8000e8e: 43da mvns r2, r3
8000e90: 693b ldr r3, [r7, #16]
8000e92: 4013 ands r3, r2
8000e94: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8000e96: 683b ldr r3, [r7, #0]
8000e98: 685a ldr r2, [r3, #4]
8000e9a: 2380 movs r3, #128 ; 0x80
8000e9c: 025b lsls r3, r3, #9
8000e9e: 4013 ands r3, r2
8000ea0: d003 beq.n 8000eaa <HAL_GPIO_Init+0x226>
{
temp |= iocurrent;
8000ea2: 693a ldr r2, [r7, #16]
8000ea4: 68fb ldr r3, [r7, #12]
8000ea6: 4313 orrs r3, r2
8000ea8: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8000eaa: 4b2d ldr r3, [pc, #180] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000eac: 693a ldr r2, [r7, #16]
8000eae: 601a str r2, [r3, #0]
temp = EXTI->EMR;
8000eb0: 4b2b ldr r3, [pc, #172] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000eb2: 685b ldr r3, [r3, #4]
8000eb4: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000eb6: 68fb ldr r3, [r7, #12]
8000eb8: 43da mvns r2, r3
8000eba: 693b ldr r3, [r7, #16]
8000ebc: 4013 ands r3, r2
8000ebe: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8000ec0: 683b ldr r3, [r7, #0]
8000ec2: 685a ldr r2, [r3, #4]
8000ec4: 2380 movs r3, #128 ; 0x80
8000ec6: 029b lsls r3, r3, #10
8000ec8: 4013 ands r3, r2
8000eca: d003 beq.n 8000ed4 <HAL_GPIO_Init+0x250>
{
temp |= iocurrent;
8000ecc: 693a ldr r2, [r7, #16]
8000ece: 68fb ldr r3, [r7, #12]
8000ed0: 4313 orrs r3, r2
8000ed2: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8000ed4: 4b22 ldr r3, [pc, #136] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000ed6: 693a ldr r2, [r7, #16]
8000ed8: 605a str r2, [r3, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000eda: 4b21 ldr r3, [pc, #132] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000edc: 689b ldr r3, [r3, #8]
8000ede: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000ee0: 68fb ldr r3, [r7, #12]
8000ee2: 43da mvns r2, r3
8000ee4: 693b ldr r3, [r7, #16]
8000ee6: 4013 ands r3, r2
8000ee8: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8000eea: 683b ldr r3, [r7, #0]
8000eec: 685a ldr r2, [r3, #4]
8000eee: 2380 movs r3, #128 ; 0x80
8000ef0: 035b lsls r3, r3, #13
8000ef2: 4013 ands r3, r2
8000ef4: d003 beq.n 8000efe <HAL_GPIO_Init+0x27a>
{
temp |= iocurrent;
8000ef6: 693a ldr r2, [r7, #16]
8000ef8: 68fb ldr r3, [r7, #12]
8000efa: 4313 orrs r3, r2
8000efc: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8000efe: 4b18 ldr r3, [pc, #96] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000f00: 693a ldr r2, [r7, #16]
8000f02: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
8000f04: 4b16 ldr r3, [pc, #88] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000f06: 68db ldr r3, [r3, #12]
8000f08: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000f0a: 68fb ldr r3, [r7, #12]
8000f0c: 43da mvns r2, r3
8000f0e: 693b ldr r3, [r7, #16]
8000f10: 4013 ands r3, r2
8000f12: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8000f14: 683b ldr r3, [r7, #0]
8000f16: 685a ldr r2, [r3, #4]
8000f18: 2380 movs r3, #128 ; 0x80
8000f1a: 039b lsls r3, r3, #14
8000f1c: 4013 ands r3, r2
8000f1e: d003 beq.n 8000f28 <HAL_GPIO_Init+0x2a4>
{
temp |= iocurrent;
8000f20: 693a ldr r2, [r7, #16]
8000f22: 68fb ldr r3, [r7, #12]
8000f24: 4313 orrs r3, r2
8000f26: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8000f28: 4b0d ldr r3, [pc, #52] ; (8000f60 <HAL_GPIO_Init+0x2dc>)
8000f2a: 693a ldr r2, [r7, #16]
8000f2c: 60da str r2, [r3, #12]
}
}
position++;
8000f2e: 697b ldr r3, [r7, #20]
8000f30: 3301 adds r3, #1
8000f32: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000f34: 683b ldr r3, [r7, #0]
8000f36: 681a ldr r2, [r3, #0]
8000f38: 697b ldr r3, [r7, #20]
8000f3a: 40da lsrs r2, r3
8000f3c: 1e13 subs r3, r2, #0
8000f3e: d000 beq.n 8000f42 <HAL_GPIO_Init+0x2be>
8000f40: e6a8 b.n 8000c94 <HAL_GPIO_Init+0x10>
}
}
8000f42: 46c0 nop ; (mov r8, r8)
8000f44: 46c0 nop ; (mov r8, r8)
8000f46: 46bd mov sp, r7
8000f48: b006 add sp, #24
8000f4a: bd80 pop {r7, pc}
8000f4c: 40021000 .word 0x40021000
8000f50: 40010000 .word 0x40010000
8000f54: 48000400 .word 0x48000400
8000f58: 48000800 .word 0x48000800
8000f5c: 48000c00 .word 0x48000c00
8000f60: 40010400 .word 0x40010400
08000f64 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8000f64: b580 push {r7, lr}
8000f66: b084 sub sp, #16
8000f68: af00 add r7, sp, #0
8000f6a: 6078 str r0, [r7, #4]
8000f6c: 000a movs r2, r1
8000f6e: 1cbb adds r3, r7, #2
8000f70: 801a strh r2, [r3, #0]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8000f72: 687b ldr r3, [r7, #4]
8000f74: 691b ldr r3, [r3, #16]
8000f76: 1cba adds r2, r7, #2
8000f78: 8812 ldrh r2, [r2, #0]
8000f7a: 4013 ands r3, r2
8000f7c: d004 beq.n 8000f88 <HAL_GPIO_ReadPin+0x24>
{
bitstatus = GPIO_PIN_SET;
8000f7e: 230f movs r3, #15
8000f80: 18fb adds r3, r7, r3
8000f82: 2201 movs r2, #1
8000f84: 701a strb r2, [r3, #0]
8000f86: e003 b.n 8000f90 <HAL_GPIO_ReadPin+0x2c>
}
else
{
bitstatus = GPIO_PIN_RESET;
8000f88: 230f movs r3, #15
8000f8a: 18fb adds r3, r7, r3
8000f8c: 2200 movs r2, #0
8000f8e: 701a strb r2, [r3, #0]
}
return bitstatus;
8000f90: 230f movs r3, #15
8000f92: 18fb adds r3, r7, r3
8000f94: 781b ldrb r3, [r3, #0]
}
8000f96: 0018 movs r0, r3
8000f98: 46bd mov sp, r7
8000f9a: b004 add sp, #16
8000f9c: bd80 pop {r7, pc}
08000f9e <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000f9e: b580 push {r7, lr}
8000fa0: b082 sub sp, #8
8000fa2: af00 add r7, sp, #0
8000fa4: 6078 str r0, [r7, #4]
8000fa6: 0008 movs r0, r1
8000fa8: 0011 movs r1, r2
8000faa: 1cbb adds r3, r7, #2
8000fac: 1c02 adds r2, r0, #0
8000fae: 801a strh r2, [r3, #0]
8000fb0: 1c7b adds r3, r7, #1
8000fb2: 1c0a adds r2, r1, #0
8000fb4: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8000fb6: 1c7b adds r3, r7, #1
8000fb8: 781b ldrb r3, [r3, #0]
8000fba: 2b00 cmp r3, #0
8000fbc: d004 beq.n 8000fc8 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8000fbe: 1cbb adds r3, r7, #2
8000fc0: 881a ldrh r2, [r3, #0]
8000fc2: 687b ldr r3, [r7, #4]
8000fc4: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8000fc6: e003 b.n 8000fd0 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8000fc8: 1cbb adds r3, r7, #2
8000fca: 881a ldrh r2, [r3, #0]
8000fcc: 687b ldr r3, [r7, #4]
8000fce: 629a str r2, [r3, #40] ; 0x28
}
8000fd0: 46c0 nop ; (mov r8, r8)
8000fd2: 46bd mov sp, r7
8000fd4: b002 add sp, #8
8000fd6: bd80 pop {r7, pc}
08000fd8 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000fd8: b580 push {r7, lr}
8000fda: b088 sub sp, #32
8000fdc: af00 add r7, sp, #0
8000fde: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000fe0: 687b ldr r3, [r7, #4]
8000fe2: 2b00 cmp r3, #0
8000fe4: d101 bne.n 8000fea <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000fe6: 2301 movs r3, #1
8000fe8: e301 b.n 80015ee <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000fea: 687b ldr r3, [r7, #4]
8000fec: 681b ldr r3, [r3, #0]
8000fee: 2201 movs r2, #1
8000ff0: 4013 ands r3, r2
8000ff2: d100 bne.n 8000ff6 <HAL_RCC_OscConfig+0x1e>
8000ff4: e08d b.n 8001112 <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000ff6: 4bc3 ldr r3, [pc, #780] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8000ff8: 685b ldr r3, [r3, #4]
8000ffa: 220c movs r2, #12
8000ffc: 4013 ands r3, r2
8000ffe: 2b04 cmp r3, #4
8001000: d00e beq.n 8001020 <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8001002: 4bc0 ldr r3, [pc, #768] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001004: 685b ldr r3, [r3, #4]
8001006: 220c movs r2, #12
8001008: 4013 ands r3, r2
800100a: 2b08 cmp r3, #8
800100c: d116 bne.n 800103c <HAL_RCC_OscConfig+0x64>
800100e: 4bbd ldr r3, [pc, #756] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001010: 685a ldr r2, [r3, #4]
8001012: 2380 movs r3, #128 ; 0x80
8001014: 025b lsls r3, r3, #9
8001016: 401a ands r2, r3
8001018: 2380 movs r3, #128 ; 0x80
800101a: 025b lsls r3, r3, #9
800101c: 429a cmp r2, r3
800101e: d10d bne.n 800103c <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001020: 4bb8 ldr r3, [pc, #736] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001022: 681a ldr r2, [r3, #0]
8001024: 2380 movs r3, #128 ; 0x80
8001026: 029b lsls r3, r3, #10
8001028: 4013 ands r3, r2
800102a: d100 bne.n 800102e <HAL_RCC_OscConfig+0x56>
800102c: e070 b.n 8001110 <HAL_RCC_OscConfig+0x138>
800102e: 687b ldr r3, [r7, #4]
8001030: 685b ldr r3, [r3, #4]
8001032: 2b00 cmp r3, #0
8001034: d000 beq.n 8001038 <HAL_RCC_OscConfig+0x60>
8001036: e06b b.n 8001110 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
8001038: 2301 movs r3, #1
800103a: e2d8 b.n 80015ee <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800103c: 687b ldr r3, [r7, #4]
800103e: 685b ldr r3, [r3, #4]
8001040: 2b01 cmp r3, #1
8001042: d107 bne.n 8001054 <HAL_RCC_OscConfig+0x7c>
8001044: 4baf ldr r3, [pc, #700] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001046: 681a ldr r2, [r3, #0]
8001048: 4bae ldr r3, [pc, #696] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800104a: 2180 movs r1, #128 ; 0x80
800104c: 0249 lsls r1, r1, #9
800104e: 430a orrs r2, r1
8001050: 601a str r2, [r3, #0]
8001052: e02f b.n 80010b4 <HAL_RCC_OscConfig+0xdc>
8001054: 687b ldr r3, [r7, #4]
8001056: 685b ldr r3, [r3, #4]
8001058: 2b00 cmp r3, #0
800105a: d10c bne.n 8001076 <HAL_RCC_OscConfig+0x9e>
800105c: 4ba9 ldr r3, [pc, #676] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800105e: 681a ldr r2, [r3, #0]
8001060: 4ba8 ldr r3, [pc, #672] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001062: 49a9 ldr r1, [pc, #676] ; (8001308 <HAL_RCC_OscConfig+0x330>)
8001064: 400a ands r2, r1
8001066: 601a str r2, [r3, #0]
8001068: 4ba6 ldr r3, [pc, #664] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800106a: 681a ldr r2, [r3, #0]
800106c: 4ba5 ldr r3, [pc, #660] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800106e: 49a7 ldr r1, [pc, #668] ; (800130c <HAL_RCC_OscConfig+0x334>)
8001070: 400a ands r2, r1
8001072: 601a str r2, [r3, #0]
8001074: e01e b.n 80010b4 <HAL_RCC_OscConfig+0xdc>
8001076: 687b ldr r3, [r7, #4]
8001078: 685b ldr r3, [r3, #4]
800107a: 2b05 cmp r3, #5
800107c: d10e bne.n 800109c <HAL_RCC_OscConfig+0xc4>
800107e: 4ba1 ldr r3, [pc, #644] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001080: 681a ldr r2, [r3, #0]
8001082: 4ba0 ldr r3, [pc, #640] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001084: 2180 movs r1, #128 ; 0x80
8001086: 02c9 lsls r1, r1, #11
8001088: 430a orrs r2, r1
800108a: 601a str r2, [r3, #0]
800108c: 4b9d ldr r3, [pc, #628] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800108e: 681a ldr r2, [r3, #0]
8001090: 4b9c ldr r3, [pc, #624] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001092: 2180 movs r1, #128 ; 0x80
8001094: 0249 lsls r1, r1, #9
8001096: 430a orrs r2, r1
8001098: 601a str r2, [r3, #0]
800109a: e00b b.n 80010b4 <HAL_RCC_OscConfig+0xdc>
800109c: 4b99 ldr r3, [pc, #612] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800109e: 681a ldr r2, [r3, #0]
80010a0: 4b98 ldr r3, [pc, #608] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80010a2: 4999 ldr r1, [pc, #612] ; (8001308 <HAL_RCC_OscConfig+0x330>)
80010a4: 400a ands r2, r1
80010a6: 601a str r2, [r3, #0]
80010a8: 4b96 ldr r3, [pc, #600] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80010aa: 681a ldr r2, [r3, #0]
80010ac: 4b95 ldr r3, [pc, #596] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80010ae: 4997 ldr r1, [pc, #604] ; (800130c <HAL_RCC_OscConfig+0x334>)
80010b0: 400a ands r2, r1
80010b2: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80010b4: 687b ldr r3, [r7, #4]
80010b6: 685b ldr r3, [r3, #4]
80010b8: 2b00 cmp r3, #0
80010ba: d014 beq.n 80010e6 <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80010bc: f7ff faee bl 800069c <HAL_GetTick>
80010c0: 0003 movs r3, r0
80010c2: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80010c4: e008 b.n 80010d8 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80010c6: f7ff fae9 bl 800069c <HAL_GetTick>
80010ca: 0002 movs r2, r0
80010cc: 69bb ldr r3, [r7, #24]
80010ce: 1ad3 subs r3, r2, r3
80010d0: 2b64 cmp r3, #100 ; 0x64
80010d2: d901 bls.n 80010d8 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
80010d4: 2303 movs r3, #3
80010d6: e28a b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80010d8: 4b8a ldr r3, [pc, #552] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80010da: 681a ldr r2, [r3, #0]
80010dc: 2380 movs r3, #128 ; 0x80
80010de: 029b lsls r3, r3, #10
80010e0: 4013 ands r3, r2
80010e2: d0f0 beq.n 80010c6 <HAL_RCC_OscConfig+0xee>
80010e4: e015 b.n 8001112 <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80010e6: f7ff fad9 bl 800069c <HAL_GetTick>
80010ea: 0003 movs r3, r0
80010ec: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80010ee: e008 b.n 8001102 <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80010f0: f7ff fad4 bl 800069c <HAL_GetTick>
80010f4: 0002 movs r2, r0
80010f6: 69bb ldr r3, [r7, #24]
80010f8: 1ad3 subs r3, r2, r3
80010fa: 2b64 cmp r3, #100 ; 0x64
80010fc: d901 bls.n 8001102 <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
80010fe: 2303 movs r3, #3
8001100: e275 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001102: 4b80 ldr r3, [pc, #512] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001104: 681a ldr r2, [r3, #0]
8001106: 2380 movs r3, #128 ; 0x80
8001108: 029b lsls r3, r3, #10
800110a: 4013 ands r3, r2
800110c: d1f0 bne.n 80010f0 <HAL_RCC_OscConfig+0x118>
800110e: e000 b.n 8001112 <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001110: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001112: 687b ldr r3, [r7, #4]
8001114: 681b ldr r3, [r3, #0]
8001116: 2202 movs r2, #2
8001118: 4013 ands r3, r2
800111a: d100 bne.n 800111e <HAL_RCC_OscConfig+0x146>
800111c: e069 b.n 80011f2 <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800111e: 4b79 ldr r3, [pc, #484] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001120: 685b ldr r3, [r3, #4]
8001122: 220c movs r2, #12
8001124: 4013 ands r3, r2
8001126: d00b beq.n 8001140 <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8001128: 4b76 ldr r3, [pc, #472] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800112a: 685b ldr r3, [r3, #4]
800112c: 220c movs r2, #12
800112e: 4013 ands r3, r2
8001130: 2b08 cmp r3, #8
8001132: d11c bne.n 800116e <HAL_RCC_OscConfig+0x196>
8001134: 4b73 ldr r3, [pc, #460] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001136: 685a ldr r2, [r3, #4]
8001138: 2380 movs r3, #128 ; 0x80
800113a: 025b lsls r3, r3, #9
800113c: 4013 ands r3, r2
800113e: d116 bne.n 800116e <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001140: 4b70 ldr r3, [pc, #448] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001142: 681b ldr r3, [r3, #0]
8001144: 2202 movs r2, #2
8001146: 4013 ands r3, r2
8001148: d005 beq.n 8001156 <HAL_RCC_OscConfig+0x17e>
800114a: 687b ldr r3, [r7, #4]
800114c: 68db ldr r3, [r3, #12]
800114e: 2b01 cmp r3, #1
8001150: d001 beq.n 8001156 <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
8001152: 2301 movs r3, #1
8001154: e24b b.n 80015ee <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001156: 4b6b ldr r3, [pc, #428] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001158: 681b ldr r3, [r3, #0]
800115a: 22f8 movs r2, #248 ; 0xf8
800115c: 4393 bics r3, r2
800115e: 0019 movs r1, r3
8001160: 687b ldr r3, [r7, #4]
8001162: 691b ldr r3, [r3, #16]
8001164: 00da lsls r2, r3, #3
8001166: 4b67 ldr r3, [pc, #412] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001168: 430a orrs r2, r1
800116a: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800116c: e041 b.n 80011f2 <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800116e: 687b ldr r3, [r7, #4]
8001170: 68db ldr r3, [r3, #12]
8001172: 2b00 cmp r3, #0
8001174: d024 beq.n 80011c0 <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001176: 4b63 ldr r3, [pc, #396] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001178: 681a ldr r2, [r3, #0]
800117a: 4b62 ldr r3, [pc, #392] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800117c: 2101 movs r1, #1
800117e: 430a orrs r2, r1
8001180: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001182: f7ff fa8b bl 800069c <HAL_GetTick>
8001186: 0003 movs r3, r0
8001188: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800118a: e008 b.n 800119e <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800118c: f7ff fa86 bl 800069c <HAL_GetTick>
8001190: 0002 movs r2, r0
8001192: 69bb ldr r3, [r7, #24]
8001194: 1ad3 subs r3, r2, r3
8001196: 2b02 cmp r3, #2
8001198: d901 bls.n 800119e <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
800119a: 2303 movs r3, #3
800119c: e227 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800119e: 4b59 ldr r3, [pc, #356] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80011a0: 681b ldr r3, [r3, #0]
80011a2: 2202 movs r2, #2
80011a4: 4013 ands r3, r2
80011a6: d0f1 beq.n 800118c <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80011a8: 4b56 ldr r3, [pc, #344] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80011aa: 681b ldr r3, [r3, #0]
80011ac: 22f8 movs r2, #248 ; 0xf8
80011ae: 4393 bics r3, r2
80011b0: 0019 movs r1, r3
80011b2: 687b ldr r3, [r7, #4]
80011b4: 691b ldr r3, [r3, #16]
80011b6: 00da lsls r2, r3, #3
80011b8: 4b52 ldr r3, [pc, #328] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80011ba: 430a orrs r2, r1
80011bc: 601a str r2, [r3, #0]
80011be: e018 b.n 80011f2 <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80011c0: 4b50 ldr r3, [pc, #320] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80011c2: 681a ldr r2, [r3, #0]
80011c4: 4b4f ldr r3, [pc, #316] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80011c6: 2101 movs r1, #1
80011c8: 438a bics r2, r1
80011ca: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011cc: f7ff fa66 bl 800069c <HAL_GetTick>
80011d0: 0003 movs r3, r0
80011d2: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80011d4: e008 b.n 80011e8 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80011d6: f7ff fa61 bl 800069c <HAL_GetTick>
80011da: 0002 movs r2, r0
80011dc: 69bb ldr r3, [r7, #24]
80011de: 1ad3 subs r3, r2, r3
80011e0: 2b02 cmp r3, #2
80011e2: d901 bls.n 80011e8 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
80011e4: 2303 movs r3, #3
80011e6: e202 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80011e8: 4b46 ldr r3, [pc, #280] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80011ea: 681b ldr r3, [r3, #0]
80011ec: 2202 movs r2, #2
80011ee: 4013 ands r3, r2
80011f0: d1f1 bne.n 80011d6 <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80011f2: 687b ldr r3, [r7, #4]
80011f4: 681b ldr r3, [r3, #0]
80011f6: 2208 movs r2, #8
80011f8: 4013 ands r3, r2
80011fa: d036 beq.n 800126a <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80011fc: 687b ldr r3, [r7, #4]
80011fe: 69db ldr r3, [r3, #28]
8001200: 2b00 cmp r3, #0
8001202: d019 beq.n 8001238 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001204: 4b3f ldr r3, [pc, #252] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001206: 6a5a ldr r2, [r3, #36] ; 0x24
8001208: 4b3e ldr r3, [pc, #248] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800120a: 2101 movs r1, #1
800120c: 430a orrs r2, r1
800120e: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8001210: f7ff fa44 bl 800069c <HAL_GetTick>
8001214: 0003 movs r3, r0
8001216: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001218: e008 b.n 800122c <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800121a: f7ff fa3f bl 800069c <HAL_GetTick>
800121e: 0002 movs r2, r0
8001220: 69bb ldr r3, [r7, #24]
8001222: 1ad3 subs r3, r2, r3
8001224: 2b02 cmp r3, #2
8001226: d901 bls.n 800122c <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
8001228: 2303 movs r3, #3
800122a: e1e0 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800122c: 4b35 ldr r3, [pc, #212] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800122e: 6a5b ldr r3, [r3, #36] ; 0x24
8001230: 2202 movs r2, #2
8001232: 4013 ands r3, r2
8001234: d0f1 beq.n 800121a <HAL_RCC_OscConfig+0x242>
8001236: e018 b.n 800126a <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001238: 4b32 ldr r3, [pc, #200] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800123a: 6a5a ldr r2, [r3, #36] ; 0x24
800123c: 4b31 ldr r3, [pc, #196] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800123e: 2101 movs r1, #1
8001240: 438a bics r2, r1
8001242: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8001244: f7ff fa2a bl 800069c <HAL_GetTick>
8001248: 0003 movs r3, r0
800124a: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800124c: e008 b.n 8001260 <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800124e: f7ff fa25 bl 800069c <HAL_GetTick>
8001252: 0002 movs r2, r0
8001254: 69bb ldr r3, [r7, #24]
8001256: 1ad3 subs r3, r2, r3
8001258: 2b02 cmp r3, #2
800125a: d901 bls.n 8001260 <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
800125c: 2303 movs r3, #3
800125e: e1c6 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001260: 4b28 ldr r3, [pc, #160] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001262: 6a5b ldr r3, [r3, #36] ; 0x24
8001264: 2202 movs r2, #2
8001266: 4013 ands r3, r2
8001268: d1f1 bne.n 800124e <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800126a: 687b ldr r3, [r7, #4]
800126c: 681b ldr r3, [r3, #0]
800126e: 2204 movs r2, #4
8001270: 4013 ands r3, r2
8001272: d100 bne.n 8001276 <HAL_RCC_OscConfig+0x29e>
8001274: e0b4 b.n 80013e0 <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
8001276: 201f movs r0, #31
8001278: 183b adds r3, r7, r0
800127a: 2200 movs r2, #0
800127c: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800127e: 4b21 ldr r3, [pc, #132] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001280: 69da ldr r2, [r3, #28]
8001282: 2380 movs r3, #128 ; 0x80
8001284: 055b lsls r3, r3, #21
8001286: 4013 ands r3, r2
8001288: d110 bne.n 80012ac <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
800128a: 4b1e ldr r3, [pc, #120] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800128c: 69da ldr r2, [r3, #28]
800128e: 4b1d ldr r3, [pc, #116] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
8001290: 2180 movs r1, #128 ; 0x80
8001292: 0549 lsls r1, r1, #21
8001294: 430a orrs r2, r1
8001296: 61da str r2, [r3, #28]
8001298: 4b1a ldr r3, [pc, #104] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
800129a: 69da ldr r2, [r3, #28]
800129c: 2380 movs r3, #128 ; 0x80
800129e: 055b lsls r3, r3, #21
80012a0: 4013 ands r3, r2
80012a2: 60fb str r3, [r7, #12]
80012a4: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
80012a6: 183b adds r3, r7, r0
80012a8: 2201 movs r2, #1
80012aa: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80012ac: 4b18 ldr r3, [pc, #96] ; (8001310 <HAL_RCC_OscConfig+0x338>)
80012ae: 681a ldr r2, [r3, #0]
80012b0: 2380 movs r3, #128 ; 0x80
80012b2: 005b lsls r3, r3, #1
80012b4: 4013 ands r3, r2
80012b6: d11a bne.n 80012ee <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80012b8: 4b15 ldr r3, [pc, #84] ; (8001310 <HAL_RCC_OscConfig+0x338>)
80012ba: 681a ldr r2, [r3, #0]
80012bc: 4b14 ldr r3, [pc, #80] ; (8001310 <HAL_RCC_OscConfig+0x338>)
80012be: 2180 movs r1, #128 ; 0x80
80012c0: 0049 lsls r1, r1, #1
80012c2: 430a orrs r2, r1
80012c4: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80012c6: f7ff f9e9 bl 800069c <HAL_GetTick>
80012ca: 0003 movs r3, r0
80012cc: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80012ce: e008 b.n 80012e2 <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80012d0: f7ff f9e4 bl 800069c <HAL_GetTick>
80012d4: 0002 movs r2, r0
80012d6: 69bb ldr r3, [r7, #24]
80012d8: 1ad3 subs r3, r2, r3
80012da: 2b64 cmp r3, #100 ; 0x64
80012dc: d901 bls.n 80012e2 <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
80012de: 2303 movs r3, #3
80012e0: e185 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80012e2: 4b0b ldr r3, [pc, #44] ; (8001310 <HAL_RCC_OscConfig+0x338>)
80012e4: 681a ldr r2, [r3, #0]
80012e6: 2380 movs r3, #128 ; 0x80
80012e8: 005b lsls r3, r3, #1
80012ea: 4013 ands r3, r2
80012ec: d0f0 beq.n 80012d0 <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80012ee: 687b ldr r3, [r7, #4]
80012f0: 689b ldr r3, [r3, #8]
80012f2: 2b01 cmp r3, #1
80012f4: d10e bne.n 8001314 <HAL_RCC_OscConfig+0x33c>
80012f6: 4b03 ldr r3, [pc, #12] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80012f8: 6a1a ldr r2, [r3, #32]
80012fa: 4b02 ldr r3, [pc, #8] ; (8001304 <HAL_RCC_OscConfig+0x32c>)
80012fc: 2101 movs r1, #1
80012fe: 430a orrs r2, r1
8001300: 621a str r2, [r3, #32]
8001302: e035 b.n 8001370 <HAL_RCC_OscConfig+0x398>
8001304: 40021000 .word 0x40021000
8001308: fffeffff .word 0xfffeffff
800130c: fffbffff .word 0xfffbffff
8001310: 40007000 .word 0x40007000
8001314: 687b ldr r3, [r7, #4]
8001316: 689b ldr r3, [r3, #8]
8001318: 2b00 cmp r3, #0
800131a: d10c bne.n 8001336 <HAL_RCC_OscConfig+0x35e>
800131c: 4bb6 ldr r3, [pc, #728] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800131e: 6a1a ldr r2, [r3, #32]
8001320: 4bb5 ldr r3, [pc, #724] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001322: 2101 movs r1, #1
8001324: 438a bics r2, r1
8001326: 621a str r2, [r3, #32]
8001328: 4bb3 ldr r3, [pc, #716] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800132a: 6a1a ldr r2, [r3, #32]
800132c: 4bb2 ldr r3, [pc, #712] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800132e: 2104 movs r1, #4
8001330: 438a bics r2, r1
8001332: 621a str r2, [r3, #32]
8001334: e01c b.n 8001370 <HAL_RCC_OscConfig+0x398>
8001336: 687b ldr r3, [r7, #4]
8001338: 689b ldr r3, [r3, #8]
800133a: 2b05 cmp r3, #5
800133c: d10c bne.n 8001358 <HAL_RCC_OscConfig+0x380>
800133e: 4bae ldr r3, [pc, #696] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001340: 6a1a ldr r2, [r3, #32]
8001342: 4bad ldr r3, [pc, #692] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001344: 2104 movs r1, #4
8001346: 430a orrs r2, r1
8001348: 621a str r2, [r3, #32]
800134a: 4bab ldr r3, [pc, #684] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800134c: 6a1a ldr r2, [r3, #32]
800134e: 4baa ldr r3, [pc, #680] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001350: 2101 movs r1, #1
8001352: 430a orrs r2, r1
8001354: 621a str r2, [r3, #32]
8001356: e00b b.n 8001370 <HAL_RCC_OscConfig+0x398>
8001358: 4ba7 ldr r3, [pc, #668] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800135a: 6a1a ldr r2, [r3, #32]
800135c: 4ba6 ldr r3, [pc, #664] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800135e: 2101 movs r1, #1
8001360: 438a bics r2, r1
8001362: 621a str r2, [r3, #32]
8001364: 4ba4 ldr r3, [pc, #656] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001366: 6a1a ldr r2, [r3, #32]
8001368: 4ba3 ldr r3, [pc, #652] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800136a: 2104 movs r1, #4
800136c: 438a bics r2, r1
800136e: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001370: 687b ldr r3, [r7, #4]
8001372: 689b ldr r3, [r3, #8]
8001374: 2b00 cmp r3, #0
8001376: d014 beq.n 80013a2 <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001378: f7ff f990 bl 800069c <HAL_GetTick>
800137c: 0003 movs r3, r0
800137e: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001380: e009 b.n 8001396 <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001382: f7ff f98b bl 800069c <HAL_GetTick>
8001386: 0002 movs r2, r0
8001388: 69bb ldr r3, [r7, #24]
800138a: 1ad3 subs r3, r2, r3
800138c: 4a9b ldr r2, [pc, #620] ; (80015fc <HAL_RCC_OscConfig+0x624>)
800138e: 4293 cmp r3, r2
8001390: d901 bls.n 8001396 <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
8001392: 2303 movs r3, #3
8001394: e12b b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001396: 4b98 ldr r3, [pc, #608] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001398: 6a1b ldr r3, [r3, #32]
800139a: 2202 movs r2, #2
800139c: 4013 ands r3, r2
800139e: d0f0 beq.n 8001382 <HAL_RCC_OscConfig+0x3aa>
80013a0: e013 b.n 80013ca <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80013a2: f7ff f97b bl 800069c <HAL_GetTick>
80013a6: 0003 movs r3, r0
80013a8: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80013aa: e009 b.n 80013c0 <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80013ac: f7ff f976 bl 800069c <HAL_GetTick>
80013b0: 0002 movs r2, r0
80013b2: 69bb ldr r3, [r7, #24]
80013b4: 1ad3 subs r3, r2, r3
80013b6: 4a91 ldr r2, [pc, #580] ; (80015fc <HAL_RCC_OscConfig+0x624>)
80013b8: 4293 cmp r3, r2
80013ba: d901 bls.n 80013c0 <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
80013bc: 2303 movs r3, #3
80013be: e116 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80013c0: 4b8d ldr r3, [pc, #564] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80013c2: 6a1b ldr r3, [r3, #32]
80013c4: 2202 movs r2, #2
80013c6: 4013 ands r3, r2
80013c8: d1f0 bne.n 80013ac <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80013ca: 231f movs r3, #31
80013cc: 18fb adds r3, r7, r3
80013ce: 781b ldrb r3, [r3, #0]
80013d0: 2b01 cmp r3, #1
80013d2: d105 bne.n 80013e0 <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
80013d4: 4b88 ldr r3, [pc, #544] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80013d6: 69da ldr r2, [r3, #28]
80013d8: 4b87 ldr r3, [pc, #540] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80013da: 4989 ldr r1, [pc, #548] ; (8001600 <HAL_RCC_OscConfig+0x628>)
80013dc: 400a ands r2, r1
80013de: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
80013e0: 687b ldr r3, [r7, #4]
80013e2: 681b ldr r3, [r3, #0]
80013e4: 2210 movs r2, #16
80013e6: 4013 ands r3, r2
80013e8: d063 beq.n 80014b2 <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
80013ea: 687b ldr r3, [r7, #4]
80013ec: 695b ldr r3, [r3, #20]
80013ee: 2b01 cmp r3, #1
80013f0: d12a bne.n 8001448 <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
80013f2: 4b81 ldr r3, [pc, #516] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80013f4: 6b5a ldr r2, [r3, #52] ; 0x34
80013f6: 4b80 ldr r3, [pc, #512] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80013f8: 2104 movs r1, #4
80013fa: 430a orrs r2, r1
80013fc: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
80013fe: 4b7e ldr r3, [pc, #504] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001400: 6b5a ldr r2, [r3, #52] ; 0x34
8001402: 4b7d ldr r3, [pc, #500] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001404: 2101 movs r1, #1
8001406: 430a orrs r2, r1
8001408: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
800140a: f7ff f947 bl 800069c <HAL_GetTick>
800140e: 0003 movs r3, r0
8001410: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001412: e008 b.n 8001426 <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001414: f7ff f942 bl 800069c <HAL_GetTick>
8001418: 0002 movs r2, r0
800141a: 69bb ldr r3, [r7, #24]
800141c: 1ad3 subs r3, r2, r3
800141e: 2b02 cmp r3, #2
8001420: d901 bls.n 8001426 <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
8001422: 2303 movs r3, #3
8001424: e0e3 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001426: 4b74 ldr r3, [pc, #464] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001428: 6b5b ldr r3, [r3, #52] ; 0x34
800142a: 2202 movs r2, #2
800142c: 4013 ands r3, r2
800142e: d0f1 beq.n 8001414 <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8001430: 4b71 ldr r3, [pc, #452] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001432: 6b5b ldr r3, [r3, #52] ; 0x34
8001434: 22f8 movs r2, #248 ; 0xf8
8001436: 4393 bics r3, r2
8001438: 0019 movs r1, r3
800143a: 687b ldr r3, [r7, #4]
800143c: 699b ldr r3, [r3, #24]
800143e: 00da lsls r2, r3, #3
8001440: 4b6d ldr r3, [pc, #436] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001442: 430a orrs r2, r1
8001444: 635a str r2, [r3, #52] ; 0x34
8001446: e034 b.n 80014b2 <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8001448: 687b ldr r3, [r7, #4]
800144a: 695b ldr r3, [r3, #20]
800144c: 3305 adds r3, #5
800144e: d111 bne.n 8001474 <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
8001450: 4b69 ldr r3, [pc, #420] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001452: 6b5a ldr r2, [r3, #52] ; 0x34
8001454: 4b68 ldr r3, [pc, #416] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001456: 2104 movs r1, #4
8001458: 438a bics r2, r1
800145a: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
800145c: 4b66 ldr r3, [pc, #408] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800145e: 6b5b ldr r3, [r3, #52] ; 0x34
8001460: 22f8 movs r2, #248 ; 0xf8
8001462: 4393 bics r3, r2
8001464: 0019 movs r1, r3
8001466: 687b ldr r3, [r7, #4]
8001468: 699b ldr r3, [r3, #24]
800146a: 00da lsls r2, r3, #3
800146c: 4b62 ldr r3, [pc, #392] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800146e: 430a orrs r2, r1
8001470: 635a str r2, [r3, #52] ; 0x34
8001472: e01e b.n 80014b2 <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001474: 4b60 ldr r3, [pc, #384] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001476: 6b5a ldr r2, [r3, #52] ; 0x34
8001478: 4b5f ldr r3, [pc, #380] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800147a: 2104 movs r1, #4
800147c: 430a orrs r2, r1
800147e: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8001480: 4b5d ldr r3, [pc, #372] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001482: 6b5a ldr r2, [r3, #52] ; 0x34
8001484: 4b5c ldr r3, [pc, #368] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001486: 2101 movs r1, #1
8001488: 438a bics r2, r1
800148a: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
800148c: f7ff f906 bl 800069c <HAL_GetTick>
8001490: 0003 movs r3, r0
8001492: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001494: e008 b.n 80014a8 <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001496: f7ff f901 bl 800069c <HAL_GetTick>
800149a: 0002 movs r2, r0
800149c: 69bb ldr r3, [r7, #24]
800149e: 1ad3 subs r3, r2, r3
80014a0: 2b02 cmp r3, #2
80014a2: d901 bls.n 80014a8 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
80014a4: 2303 movs r3, #3
80014a6: e0a2 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
80014a8: 4b53 ldr r3, [pc, #332] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80014aa: 6b5b ldr r3, [r3, #52] ; 0x34
80014ac: 2202 movs r2, #2
80014ae: 4013 ands r3, r2
80014b0: d1f1 bne.n 8001496 <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80014b2: 687b ldr r3, [r7, #4]
80014b4: 6a1b ldr r3, [r3, #32]
80014b6: 2b00 cmp r3, #0
80014b8: d100 bne.n 80014bc <HAL_RCC_OscConfig+0x4e4>
80014ba: e097 b.n 80015ec <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80014bc: 4b4e ldr r3, [pc, #312] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80014be: 685b ldr r3, [r3, #4]
80014c0: 220c movs r2, #12
80014c2: 4013 ands r3, r2
80014c4: 2b08 cmp r3, #8
80014c6: d100 bne.n 80014ca <HAL_RCC_OscConfig+0x4f2>
80014c8: e06b b.n 80015a2 <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80014ca: 687b ldr r3, [r7, #4]
80014cc: 6a1b ldr r3, [r3, #32]
80014ce: 2b02 cmp r3, #2
80014d0: d14c bne.n 800156c <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80014d2: 4b49 ldr r3, [pc, #292] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80014d4: 681a ldr r2, [r3, #0]
80014d6: 4b48 ldr r3, [pc, #288] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80014d8: 494a ldr r1, [pc, #296] ; (8001604 <HAL_RCC_OscConfig+0x62c>)
80014da: 400a ands r2, r1
80014dc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80014de: f7ff f8dd bl 800069c <HAL_GetTick>
80014e2: 0003 movs r3, r0
80014e4: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80014e6: e008 b.n 80014fa <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80014e8: f7ff f8d8 bl 800069c <HAL_GetTick>
80014ec: 0002 movs r2, r0
80014ee: 69bb ldr r3, [r7, #24]
80014f0: 1ad3 subs r3, r2, r3
80014f2: 2b02 cmp r3, #2
80014f4: d901 bls.n 80014fa <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
80014f6: 2303 movs r3, #3
80014f8: e079 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80014fa: 4b3f ldr r3, [pc, #252] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80014fc: 681a ldr r2, [r3, #0]
80014fe: 2380 movs r3, #128 ; 0x80
8001500: 049b lsls r3, r3, #18
8001502: 4013 ands r3, r2
8001504: d1f0 bne.n 80014e8 <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001506: 4b3c ldr r3, [pc, #240] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001508: 6adb ldr r3, [r3, #44] ; 0x2c
800150a: 220f movs r2, #15
800150c: 4393 bics r3, r2
800150e: 0019 movs r1, r3
8001510: 687b ldr r3, [r7, #4]
8001512: 6ada ldr r2, [r3, #44] ; 0x2c
8001514: 4b38 ldr r3, [pc, #224] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001516: 430a orrs r2, r1
8001518: 62da str r2, [r3, #44] ; 0x2c
800151a: 4b37 ldr r3, [pc, #220] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800151c: 685b ldr r3, [r3, #4]
800151e: 4a3a ldr r2, [pc, #232] ; (8001608 <HAL_RCC_OscConfig+0x630>)
8001520: 4013 ands r3, r2
8001522: 0019 movs r1, r3
8001524: 687b ldr r3, [r7, #4]
8001526: 6a9a ldr r2, [r3, #40] ; 0x28
8001528: 687b ldr r3, [r7, #4]
800152a: 6a5b ldr r3, [r3, #36] ; 0x24
800152c: 431a orrs r2, r3
800152e: 4b32 ldr r3, [pc, #200] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001530: 430a orrs r2, r1
8001532: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001534: 4b30 ldr r3, [pc, #192] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001536: 681a ldr r2, [r3, #0]
8001538: 4b2f ldr r3, [pc, #188] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800153a: 2180 movs r1, #128 ; 0x80
800153c: 0449 lsls r1, r1, #17
800153e: 430a orrs r2, r1
8001540: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001542: f7ff f8ab bl 800069c <HAL_GetTick>
8001546: 0003 movs r3, r0
8001548: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800154a: e008 b.n 800155e <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800154c: f7ff f8a6 bl 800069c <HAL_GetTick>
8001550: 0002 movs r2, r0
8001552: 69bb ldr r3, [r7, #24]
8001554: 1ad3 subs r3, r2, r3
8001556: 2b02 cmp r3, #2
8001558: d901 bls.n 800155e <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
800155a: 2303 movs r3, #3
800155c: e047 b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800155e: 4b26 ldr r3, [pc, #152] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001560: 681a ldr r2, [r3, #0]
8001562: 2380 movs r3, #128 ; 0x80
8001564: 049b lsls r3, r3, #18
8001566: 4013 ands r3, r2
8001568: d0f0 beq.n 800154c <HAL_RCC_OscConfig+0x574>
800156a: e03f b.n 80015ec <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800156c: 4b22 ldr r3, [pc, #136] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
800156e: 681a ldr r2, [r3, #0]
8001570: 4b21 ldr r3, [pc, #132] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001572: 4924 ldr r1, [pc, #144] ; (8001604 <HAL_RCC_OscConfig+0x62c>)
8001574: 400a ands r2, r1
8001576: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001578: f7ff f890 bl 800069c <HAL_GetTick>
800157c: 0003 movs r3, r0
800157e: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001580: e008 b.n 8001594 <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001582: f7ff f88b bl 800069c <HAL_GetTick>
8001586: 0002 movs r2, r0
8001588: 69bb ldr r3, [r7, #24]
800158a: 1ad3 subs r3, r2, r3
800158c: 2b02 cmp r3, #2
800158e: d901 bls.n 8001594 <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
8001590: 2303 movs r3, #3
8001592: e02c b.n 80015ee <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001594: 4b18 ldr r3, [pc, #96] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
8001596: 681a ldr r2, [r3, #0]
8001598: 2380 movs r3, #128 ; 0x80
800159a: 049b lsls r3, r3, #18
800159c: 4013 ands r3, r2
800159e: d1f0 bne.n 8001582 <HAL_RCC_OscConfig+0x5aa>
80015a0: e024 b.n 80015ec <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80015a2: 687b ldr r3, [r7, #4]
80015a4: 6a1b ldr r3, [r3, #32]
80015a6: 2b01 cmp r3, #1
80015a8: d101 bne.n 80015ae <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
80015aa: 2301 movs r3, #1
80015ac: e01f b.n 80015ee <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80015ae: 4b12 ldr r3, [pc, #72] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80015b0: 685b ldr r3, [r3, #4]
80015b2: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
80015b4: 4b10 ldr r3, [pc, #64] ; (80015f8 <HAL_RCC_OscConfig+0x620>)
80015b6: 6adb ldr r3, [r3, #44] ; 0x2c
80015b8: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80015ba: 697a ldr r2, [r7, #20]
80015bc: 2380 movs r3, #128 ; 0x80
80015be: 025b lsls r3, r3, #9
80015c0: 401a ands r2, r3
80015c2: 687b ldr r3, [r7, #4]
80015c4: 6a5b ldr r3, [r3, #36] ; 0x24
80015c6: 429a cmp r2, r3
80015c8: d10e bne.n 80015e8 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
80015ca: 693b ldr r3, [r7, #16]
80015cc: 220f movs r2, #15
80015ce: 401a ands r2, r3
80015d0: 687b ldr r3, [r7, #4]
80015d2: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80015d4: 429a cmp r2, r3
80015d6: d107 bne.n 80015e8 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
80015d8: 697a ldr r2, [r7, #20]
80015da: 23f0 movs r3, #240 ; 0xf0
80015dc: 039b lsls r3, r3, #14
80015de: 401a ands r2, r3
80015e0: 687b ldr r3, [r7, #4]
80015e2: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
80015e4: 429a cmp r2, r3
80015e6: d001 beq.n 80015ec <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
80015e8: 2301 movs r3, #1
80015ea: e000 b.n 80015ee <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
80015ec: 2300 movs r3, #0
}
80015ee: 0018 movs r0, r3
80015f0: 46bd mov sp, r7
80015f2: b008 add sp, #32
80015f4: bd80 pop {r7, pc}
80015f6: 46c0 nop ; (mov r8, r8)
80015f8: 40021000 .word 0x40021000
80015fc: 00001388 .word 0x00001388
8001600: efffffff .word 0xefffffff
8001604: feffffff .word 0xfeffffff
8001608: ffc2ffff .word 0xffc2ffff
0800160c <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
800160c: b580 push {r7, lr}
800160e: b084 sub sp, #16
8001610: af00 add r7, sp, #0
8001612: 6078 str r0, [r7, #4]
8001614: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001616: 687b ldr r3, [r7, #4]
8001618: 2b00 cmp r3, #0
800161a: d101 bne.n 8001620 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
800161c: 2301 movs r3, #1
800161e: e0b3 b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001620: 4b5b ldr r3, [pc, #364] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
8001622: 681b ldr r3, [r3, #0]
8001624: 2201 movs r2, #1
8001626: 4013 ands r3, r2
8001628: 683a ldr r2, [r7, #0]
800162a: 429a cmp r2, r3
800162c: d911 bls.n 8001652 <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800162e: 4b58 ldr r3, [pc, #352] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
8001630: 681b ldr r3, [r3, #0]
8001632: 2201 movs r2, #1
8001634: 4393 bics r3, r2
8001636: 0019 movs r1, r3
8001638: 4b55 ldr r3, [pc, #340] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
800163a: 683a ldr r2, [r7, #0]
800163c: 430a orrs r2, r1
800163e: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001640: 4b53 ldr r3, [pc, #332] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
8001642: 681b ldr r3, [r3, #0]
8001644: 2201 movs r2, #1
8001646: 4013 ands r3, r2
8001648: 683a ldr r2, [r7, #0]
800164a: 429a cmp r2, r3
800164c: d001 beq.n 8001652 <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
800164e: 2301 movs r3, #1
8001650: e09a b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001652: 687b ldr r3, [r7, #4]
8001654: 681b ldr r3, [r3, #0]
8001656: 2202 movs r2, #2
8001658: 4013 ands r3, r2
800165a: d015 beq.n 8001688 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800165c: 687b ldr r3, [r7, #4]
800165e: 681b ldr r3, [r3, #0]
8001660: 2204 movs r2, #4
8001662: 4013 ands r3, r2
8001664: d006 beq.n 8001674 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8001666: 4b4b ldr r3, [pc, #300] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
8001668: 685a ldr r2, [r3, #4]
800166a: 4b4a ldr r3, [pc, #296] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
800166c: 21e0 movs r1, #224 ; 0xe0
800166e: 00c9 lsls r1, r1, #3
8001670: 430a orrs r2, r1
8001672: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001674: 4b47 ldr r3, [pc, #284] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
8001676: 685b ldr r3, [r3, #4]
8001678: 22f0 movs r2, #240 ; 0xf0
800167a: 4393 bics r3, r2
800167c: 0019 movs r1, r3
800167e: 687b ldr r3, [r7, #4]
8001680: 689a ldr r2, [r3, #8]
8001682: 4b44 ldr r3, [pc, #272] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
8001684: 430a orrs r2, r1
8001686: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001688: 687b ldr r3, [r7, #4]
800168a: 681b ldr r3, [r3, #0]
800168c: 2201 movs r2, #1
800168e: 4013 ands r3, r2
8001690: d040 beq.n 8001714 <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001692: 687b ldr r3, [r7, #4]
8001694: 685b ldr r3, [r3, #4]
8001696: 2b01 cmp r3, #1
8001698: d107 bne.n 80016aa <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800169a: 4b3e ldr r3, [pc, #248] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
800169c: 681a ldr r2, [r3, #0]
800169e: 2380 movs r3, #128 ; 0x80
80016a0: 029b lsls r3, r3, #10
80016a2: 4013 ands r3, r2
80016a4: d114 bne.n 80016d0 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
80016a6: 2301 movs r3, #1
80016a8: e06e b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80016aa: 687b ldr r3, [r7, #4]
80016ac: 685b ldr r3, [r3, #4]
80016ae: 2b02 cmp r3, #2
80016b0: d107 bne.n 80016c2 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80016b2: 4b38 ldr r3, [pc, #224] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
80016b4: 681a ldr r2, [r3, #0]
80016b6: 2380 movs r3, #128 ; 0x80
80016b8: 049b lsls r3, r3, #18
80016ba: 4013 ands r3, r2
80016bc: d108 bne.n 80016d0 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
80016be: 2301 movs r3, #1
80016c0: e062 b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80016c2: 4b34 ldr r3, [pc, #208] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
80016c4: 681b ldr r3, [r3, #0]
80016c6: 2202 movs r2, #2
80016c8: 4013 ands r3, r2
80016ca: d101 bne.n 80016d0 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
80016cc: 2301 movs r3, #1
80016ce: e05b b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80016d0: 4b30 ldr r3, [pc, #192] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
80016d2: 685b ldr r3, [r3, #4]
80016d4: 2203 movs r2, #3
80016d6: 4393 bics r3, r2
80016d8: 0019 movs r1, r3
80016da: 687b ldr r3, [r7, #4]
80016dc: 685a ldr r2, [r3, #4]
80016de: 4b2d ldr r3, [pc, #180] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
80016e0: 430a orrs r2, r1
80016e2: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80016e4: f7fe ffda bl 800069c <HAL_GetTick>
80016e8: 0003 movs r3, r0
80016ea: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80016ec: e009 b.n 8001702 <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80016ee: f7fe ffd5 bl 800069c <HAL_GetTick>
80016f2: 0002 movs r2, r0
80016f4: 68fb ldr r3, [r7, #12]
80016f6: 1ad3 subs r3, r2, r3
80016f8: 4a27 ldr r2, [pc, #156] ; (8001798 <HAL_RCC_ClockConfig+0x18c>)
80016fa: 4293 cmp r3, r2
80016fc: d901 bls.n 8001702 <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
80016fe: 2303 movs r3, #3
8001700: e042 b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001702: 4b24 ldr r3, [pc, #144] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
8001704: 685b ldr r3, [r3, #4]
8001706: 220c movs r2, #12
8001708: 401a ands r2, r3
800170a: 687b ldr r3, [r7, #4]
800170c: 685b ldr r3, [r3, #4]
800170e: 009b lsls r3, r3, #2
8001710: 429a cmp r2, r3
8001712: d1ec bne.n 80016ee <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001714: 4b1e ldr r3, [pc, #120] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
8001716: 681b ldr r3, [r3, #0]
8001718: 2201 movs r2, #1
800171a: 4013 ands r3, r2
800171c: 683a ldr r2, [r7, #0]
800171e: 429a cmp r2, r3
8001720: d211 bcs.n 8001746 <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001722: 4b1b ldr r3, [pc, #108] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
8001724: 681b ldr r3, [r3, #0]
8001726: 2201 movs r2, #1
8001728: 4393 bics r3, r2
800172a: 0019 movs r1, r3
800172c: 4b18 ldr r3, [pc, #96] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
800172e: 683a ldr r2, [r7, #0]
8001730: 430a orrs r2, r1
8001732: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001734: 4b16 ldr r3, [pc, #88] ; (8001790 <HAL_RCC_ClockConfig+0x184>)
8001736: 681b ldr r3, [r3, #0]
8001738: 2201 movs r2, #1
800173a: 4013 ands r3, r2
800173c: 683a ldr r2, [r7, #0]
800173e: 429a cmp r2, r3
8001740: d001 beq.n 8001746 <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
8001742: 2301 movs r3, #1
8001744: e020 b.n 8001788 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001746: 687b ldr r3, [r7, #4]
8001748: 681b ldr r3, [r3, #0]
800174a: 2204 movs r2, #4
800174c: 4013 ands r3, r2
800174e: d009 beq.n 8001764 <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8001750: 4b10 ldr r3, [pc, #64] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
8001752: 685b ldr r3, [r3, #4]
8001754: 4a11 ldr r2, [pc, #68] ; (800179c <HAL_RCC_ClockConfig+0x190>)
8001756: 4013 ands r3, r2
8001758: 0019 movs r1, r3
800175a: 687b ldr r3, [r7, #4]
800175c: 68da ldr r2, [r3, #12]
800175e: 4b0d ldr r3, [pc, #52] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
8001760: 430a orrs r2, r1
8001762: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8001764: f000 f820 bl 80017a8 <HAL_RCC_GetSysClockFreq>
8001768: 0001 movs r1, r0
800176a: 4b0a ldr r3, [pc, #40] ; (8001794 <HAL_RCC_ClockConfig+0x188>)
800176c: 685b ldr r3, [r3, #4]
800176e: 091b lsrs r3, r3, #4
8001770: 220f movs r2, #15
8001772: 4013 ands r3, r2
8001774: 4a0a ldr r2, [pc, #40] ; (80017a0 <HAL_RCC_ClockConfig+0x194>)
8001776: 5cd3 ldrb r3, [r2, r3]
8001778: 000a movs r2, r1
800177a: 40da lsrs r2, r3
800177c: 4b09 ldr r3, [pc, #36] ; (80017a4 <HAL_RCC_ClockConfig+0x198>)
800177e: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
8001780: 2003 movs r0, #3
8001782: f7fe ff45 bl 8000610 <HAL_InitTick>
return HAL_OK;
8001786: 2300 movs r3, #0
}
8001788: 0018 movs r0, r3
800178a: 46bd mov sp, r7
800178c: b004 add sp, #16
800178e: bd80 pop {r7, pc}
8001790: 40022000 .word 0x40022000
8001794: 40021000 .word 0x40021000
8001798: 00001388 .word 0x00001388
800179c: fffff8ff .word 0xfffff8ff
80017a0: 08001dd4 .word 0x08001dd4
80017a4: 20000000 .word 0x20000000
080017a8 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80017a8: b590 push {r4, r7, lr}
80017aa: b08f sub sp, #60 ; 0x3c
80017ac: af00 add r7, sp, #0
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
80017ae: 2314 movs r3, #20
80017b0: 18fb adds r3, r7, r3
80017b2: 4a2b ldr r2, [pc, #172] ; (8001860 <HAL_RCC_GetSysClockFreq+0xb8>)
80017b4: ca13 ldmia r2!, {r0, r1, r4}
80017b6: c313 stmia r3!, {r0, r1, r4}
80017b8: 6812 ldr r2, [r2, #0]
80017ba: 601a str r2, [r3, #0]
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
80017bc: 1d3b adds r3, r7, #4
80017be: 4a29 ldr r2, [pc, #164] ; (8001864 <HAL_RCC_GetSysClockFreq+0xbc>)
80017c0: ca13 ldmia r2!, {r0, r1, r4}
80017c2: c313 stmia r3!, {r0, r1, r4}
80017c4: 6812 ldr r2, [r2, #0]
80017c6: 601a str r2, [r3, #0]
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80017c8: 2300 movs r3, #0
80017ca: 62fb str r3, [r7, #44] ; 0x2c
80017cc: 2300 movs r3, #0
80017ce: 62bb str r3, [r7, #40] ; 0x28
80017d0: 2300 movs r3, #0
80017d2: 637b str r3, [r7, #52] ; 0x34
80017d4: 2300 movs r3, #0
80017d6: 627b str r3, [r7, #36] ; 0x24
uint32_t sysclockfreq = 0U;
80017d8: 2300 movs r3, #0
80017da: 633b str r3, [r7, #48] ; 0x30
tmpreg = RCC->CFGR;
80017dc: 4b22 ldr r3, [pc, #136] ; (8001868 <HAL_RCC_GetSysClockFreq+0xc0>)
80017de: 685b ldr r3, [r3, #4]
80017e0: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80017e2: 6afb ldr r3, [r7, #44] ; 0x2c
80017e4: 220c movs r2, #12
80017e6: 4013 ands r3, r2
80017e8: 2b04 cmp r3, #4
80017ea: d002 beq.n 80017f2 <HAL_RCC_GetSysClockFreq+0x4a>
80017ec: 2b08 cmp r3, #8
80017ee: d003 beq.n 80017f8 <HAL_RCC_GetSysClockFreq+0x50>
80017f0: e02d b.n 800184e <HAL_RCC_GetSysClockFreq+0xa6>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80017f2: 4b1e ldr r3, [pc, #120] ; (800186c <HAL_RCC_GetSysClockFreq+0xc4>)
80017f4: 633b str r3, [r7, #48] ; 0x30
break;
80017f6: e02d b.n 8001854 <HAL_RCC_GetSysClockFreq+0xac>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
80017f8: 6afb ldr r3, [r7, #44] ; 0x2c
80017fa: 0c9b lsrs r3, r3, #18
80017fc: 220f movs r2, #15
80017fe: 4013 ands r3, r2
8001800: 2214 movs r2, #20
8001802: 18ba adds r2, r7, r2
8001804: 5cd3 ldrb r3, [r2, r3]
8001806: 627b str r3, [r7, #36] ; 0x24
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
8001808: 4b17 ldr r3, [pc, #92] ; (8001868 <HAL_RCC_GetSysClockFreq+0xc0>)
800180a: 6adb ldr r3, [r3, #44] ; 0x2c
800180c: 220f movs r2, #15
800180e: 4013 ands r3, r2
8001810: 1d3a adds r2, r7, #4
8001812: 5cd3 ldrb r3, [r2, r3]
8001814: 62bb str r3, [r7, #40] ; 0x28
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
8001816: 6afa ldr r2, [r7, #44] ; 0x2c
8001818: 2380 movs r3, #128 ; 0x80
800181a: 025b lsls r3, r3, #9
800181c: 4013 ands r3, r2
800181e: d009 beq.n 8001834 <HAL_RCC_GetSysClockFreq+0x8c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8001820: 6ab9 ldr r1, [r7, #40] ; 0x28
8001822: 4812 ldr r0, [pc, #72] ; (800186c <HAL_RCC_GetSysClockFreq+0xc4>)
8001824: f7fe fc70 bl 8000108 <__udivsi3>
8001828: 0003 movs r3, r0
800182a: 001a movs r2, r3
800182c: 6a7b ldr r3, [r7, #36] ; 0x24
800182e: 4353 muls r3, r2
8001830: 637b str r3, [r7, #52] ; 0x34
8001832: e009 b.n 8001848 <HAL_RCC_GetSysClockFreq+0xa0>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8001834: 6a79 ldr r1, [r7, #36] ; 0x24
8001836: 000a movs r2, r1
8001838: 0152 lsls r2, r2, #5
800183a: 1a52 subs r2, r2, r1
800183c: 0193 lsls r3, r2, #6
800183e: 1a9b subs r3, r3, r2
8001840: 00db lsls r3, r3, #3
8001842: 185b adds r3, r3, r1
8001844: 021b lsls r3, r3, #8
8001846: 637b str r3, [r7, #52] ; 0x34
#endif
}
sysclockfreq = pllclk;
8001848: 6b7b ldr r3, [r7, #52] ; 0x34
800184a: 633b str r3, [r7, #48] ; 0x30
break;
800184c: e002 b.n 8001854 <HAL_RCC_GetSysClockFreq+0xac>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800184e: 4b07 ldr r3, [pc, #28] ; (800186c <HAL_RCC_GetSysClockFreq+0xc4>)
8001850: 633b str r3, [r7, #48] ; 0x30
break;
8001852: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
8001854: 6b3b ldr r3, [r7, #48] ; 0x30
}
8001856: 0018 movs r0, r3
8001858: 46bd mov sp, r7
800185a: b00f add sp, #60 ; 0x3c
800185c: bd90 pop {r4, r7, pc}
800185e: 46c0 nop ; (mov r8, r8)
8001860: 08001db4 .word 0x08001db4
8001864: 08001dc4 .word 0x08001dc4
8001868: 40021000 .word 0x40021000
800186c: 007a1200 .word 0x007a1200
08001870 <GEI_BUTTON_CODE>:
*/
#include "button.h"
void GEI_BUTTON_CODE(struct button *bt,uint8_t in)
{
8001870: b580 push {r7, lr}
8001872: b082 sub sp, #8
8001874: af00 add r7, sp, #0
8001876: 6078 str r0, [r7, #4]
8001878: 000a movs r2, r1
800187a: 1cfb adds r3, r7, #3
800187c: 701a strb r2, [r3, #0]
#define t 250
bt->code=0;
800187e: 687b ldr r3, [r7, #4]
8001880: 2200 movs r2, #0
8001882: 801a strh r2, [r3, #0]
if(in==1)
8001884: 1cfb adds r3, r7, #3
8001886: 781b ldrb r3, [r3, #0]
8001888: 2b01 cmp r3, #1
800188a: d137 bne.n 80018fc <GEI_BUTTON_CODE+0x8c>
{
if(bt->lock==0)
800188c: 687b ldr r3, [r7, #4]
800188e: 789b ldrb r3, [r3, #2]
8001890: 2b00 cmp r3, #0
8001892: d121 bne.n 80018d8 <GEI_BUTTON_CODE+0x68>
{
if(HAL_GetTick()<bt->time+t)
8001894: f7fe ff02 bl 800069c <HAL_GetTick>
8001898: 0002 movs r2, r0
800189a: 687b ldr r3, [r7, #4]
800189c: 685b ldr r3, [r3, #4]
800189e: 33fa adds r3, #250 ; 0xfa
80018a0: 429a cmp r2, r3
80018a2: d20e bcs.n 80018c2 <GEI_BUTTON_CODE+0x52>
{
bt->times++;
80018a4: 687b ldr r3, [r7, #4]
80018a6: 891b ldrh r3, [r3, #8]
80018a8: 3301 adds r3, #1
80018aa: b29a uxth r2, r3
80018ac: 687b ldr r3, [r7, #4]
80018ae: 811a strh r2, [r3, #8]
bt->time=HAL_GetTick();
80018b0: f7fe fef4 bl 800069c <HAL_GetTick>
80018b4: 0002 movs r2, r0
80018b6: 687b ldr r3, [r7, #4]
80018b8: 605a str r2, [r3, #4]
bt->lock=1;
80018ba: 687b ldr r3, [r7, #4]
80018bc: 2201 movs r2, #1
80018be: 709a strb r2, [r3, #2]
80018c0: e00a b.n 80018d8 <GEI_BUTTON_CODE+0x68>
}else
{
bt->times=1;
80018c2: 687b ldr r3, [r7, #4]
80018c4: 2201 movs r2, #1
80018c6: 811a strh r2, [r3, #8]
bt->time=HAL_GetTick();
80018c8: f7fe fee8 bl 800069c <HAL_GetTick>
80018cc: 0002 movs r2, r0
80018ce: 687b ldr r3, [r7, #4]
80018d0: 605a str r2, [r3, #4]
bt->lock=1;
80018d2: 687b ldr r3, [r7, #4]
80018d4: 2201 movs r2, #1
80018d6: 709a strb r2, [r3, #2]
}
}
if(bt->lock==1)
80018d8: 687b ldr r3, [r7, #4]
80018da: 789b ldrb r3, [r3, #2]
80018dc: 2b01 cmp r3, #1
80018de: d10d bne.n 80018fc <GEI_BUTTON_CODE+0x8c>
{
if(HAL_GetTick()>bt->time+t)
80018e0: f7fe fedc bl 800069c <HAL_GetTick>
80018e4: 0002 movs r2, r0
80018e6: 687b ldr r3, [r7, #4]
80018e8: 685b ldr r3, [r3, #4]
80018ea: 33fa adds r3, #250 ; 0xfa
80018ec: 429a cmp r2, r3
80018ee: d905 bls.n 80018fc <GEI_BUTTON_CODE+0x8c>
{
bt->code=255;
80018f0: 687b ldr r3, [r7, #4]
80018f2: 22ff movs r2, #255 ; 0xff
80018f4: 801a strh r2, [r3, #0]
bt->times=255;
80018f6: 687b ldr r3, [r7, #4]
80018f8: 22ff movs r2, #255 ; 0xff
80018fa: 811a strh r2, [r3, #8]
}
}
}
if(in==0)
80018fc: 1cfb adds r3, r7, #3
80018fe: 781b ldrb r3, [r3, #0]
8001900: 2b00 cmp r3, #0
8001902: d10e bne.n 8001922 <GEI_BUTTON_CODE+0xb2>
{
if(bt->lock==1)
8001904: 687b ldr r3, [r7, #4]
8001906: 789b ldrb r3, [r3, #2]
8001908: 2b01 cmp r3, #1
800190a: d10a bne.n 8001922 <GEI_BUTTON_CODE+0xb2>
{
if(bt->code==255)
800190c: 687b ldr r3, [r7, #4]
800190e: 881b ldrh r3, [r3, #0]
8001910: 2bff cmp r3, #255 ; 0xff
8001912: d003 beq.n 800191c <GEI_BUTTON_CODE+0xac>
{
}else
{
bt->code=bt->times;
8001914: 687b ldr r3, [r7, #4]
8001916: 891a ldrh r2, [r3, #8]
8001918: 687b ldr r3, [r7, #4]
800191a: 801a strh r2, [r3, #0]
}
bt->lock=0;
800191c: 687b ldr r3, [r7, #4]
800191e: 2200 movs r2, #0
8001920: 709a strb r2, [r3, #2]
}
}
}
8001922: 46c0 nop ; (mov r8, r8)
8001924: 46bd mov sp, r7
8001926: b002 add sp, #8
8001928: bd80 pop {r7, pc}
0800192a <Send_to_595>:
char led_n:1;
char led_err:1;
}dis_buff;
void Send_to_595(char h,char l)
{
800192a: b580 push {r7, lr}
800192c: b084 sub sp, #16
800192e: af00 add r7, sp, #0
8001930: 0002 movs r2, r0
8001932: 1dfb adds r3, r7, #7
8001934: 701a strb r2, [r3, #0]
8001936: 1dbb adds r3, r7, #6
8001938: 1c0a adds r2, r1, #0
800193a: 701a strb r2, [r3, #0]
for(int a=0;a<8;a++)
800193c: 2300 movs r3, #0
800193e: 60fb str r3, [r7, #12]
8001940: e027 b.n 8001992 <Send_to_595+0x68>
{
if((h<<a)&0x80)
8001942: 1dfb adds r3, r7, #7
8001944: 781a ldrb r2, [r3, #0]
8001946: 68fb ldr r3, [r7, #12]
8001948: 409a lsls r2, r3
800194a: 0013 movs r3, r2
800194c: 2280 movs r2, #128 ; 0x80
800194e: 4013 ands r3, r2
8001950: d007 beq.n 8001962 <Send_to_595+0x38>
{
HC595_DCK(1);
8001952: 2390 movs r3, #144 ; 0x90
8001954: 05db lsls r3, r3, #23
8001956: 2201 movs r2, #1
8001958: 2108 movs r1, #8
800195a: 0018 movs r0, r3
800195c: f7ff fb1f bl 8000f9e <HAL_GPIO_WritePin>
8001960: e006 b.n 8001970 <Send_to_595+0x46>
}else
{
HC595_DCK(0);
8001962: 2390 movs r3, #144 ; 0x90
8001964: 05db lsls r3, r3, #23
8001966: 2200 movs r2, #0
8001968: 2108 movs r1, #8
800196a: 0018 movs r0, r3
800196c: f7ff fb17 bl 8000f9e <HAL_GPIO_WritePin>
}
HC595_SCK(1);
8001970: 2390 movs r3, #144 ; 0x90
8001972: 05db lsls r3, r3, #23
8001974: 2201 movs r2, #1
8001976: 2120 movs r1, #32
8001978: 0018 movs r0, r3
800197a: f7ff fb10 bl 8000f9e <HAL_GPIO_WritePin>
HC595_SCK(0);
800197e: 2390 movs r3, #144 ; 0x90
8001980: 05db lsls r3, r3, #23
8001982: 2200 movs r2, #0
8001984: 2120 movs r1, #32
8001986: 0018 movs r0, r3
8001988: f7ff fb09 bl 8000f9e <HAL_GPIO_WritePin>
for(int a=0;a<8;a++)
800198c: 68fb ldr r3, [r7, #12]
800198e: 3301 adds r3, #1
8001990: 60fb str r3, [r7, #12]
8001992: 68fb ldr r3, [r7, #12]
8001994: 2b07 cmp r3, #7
8001996: ddd4 ble.n 8001942 <Send_to_595+0x18>
}
for(int a=0;a<8;a++)
8001998: 2300 movs r3, #0
800199a: 60bb str r3, [r7, #8]
800199c: e027 b.n 80019ee <Send_to_595+0xc4>
{
if((l<<a)&0x80)
800199e: 1dbb adds r3, r7, #6
80019a0: 781a ldrb r2, [r3, #0]
80019a2: 68bb ldr r3, [r7, #8]
80019a4: 409a lsls r2, r3
80019a6: 0013 movs r3, r2
80019a8: 2280 movs r2, #128 ; 0x80
80019aa: 4013 ands r3, r2
80019ac: d007 beq.n 80019be <Send_to_595+0x94>
{
HC595_DCK(1);
80019ae: 2390 movs r3, #144 ; 0x90
80019b0: 05db lsls r3, r3, #23
80019b2: 2201 movs r2, #1
80019b4: 2108 movs r1, #8
80019b6: 0018 movs r0, r3
80019b8: f7ff faf1 bl 8000f9e <HAL_GPIO_WritePin>
80019bc: e006 b.n 80019cc <Send_to_595+0xa2>
}else
{
HC595_DCK(0);
80019be: 2390 movs r3, #144 ; 0x90
80019c0: 05db lsls r3, r3, #23
80019c2: 2200 movs r2, #0
80019c4: 2108 movs r1, #8
80019c6: 0018 movs r0, r3
80019c8: f7ff fae9 bl 8000f9e <HAL_GPIO_WritePin>
}
HC595_SCK(1);
80019cc: 2390 movs r3, #144 ; 0x90
80019ce: 05db lsls r3, r3, #23
80019d0: 2201 movs r2, #1
80019d2: 2120 movs r1, #32
80019d4: 0018 movs r0, r3
80019d6: f7ff fae2 bl 8000f9e <HAL_GPIO_WritePin>
HC595_SCK(0);
80019da: 2390 movs r3, #144 ; 0x90
80019dc: 05db lsls r3, r3, #23
80019de: 2200 movs r2, #0
80019e0: 2120 movs r1, #32
80019e2: 0018 movs r0, r3
80019e4: f7ff fadb bl 8000f9e <HAL_GPIO_WritePin>
for(int a=0;a<8;a++)
80019e8: 68bb ldr r3, [r7, #8]
80019ea: 3301 adds r3, #1
80019ec: 60bb str r3, [r7, #8]
80019ee: 68bb ldr r3, [r7, #8]
80019f0: 2b07 cmp r3, #7
80019f2: ddd4 ble.n 800199e <Send_to_595+0x74>
}
HC595_RCK(1);
80019f4: 2390 movs r3, #144 ; 0x90
80019f6: 05db lsls r3, r3, #23
80019f8: 2201 movs r2, #1
80019fa: 2110 movs r1, #16
80019fc: 0018 movs r0, r3
80019fe: f7ff face bl 8000f9e <HAL_GPIO_WritePin>
HC595_RCK(0);
8001a02: 2390 movs r3, #144 ; 0x90
8001a04: 05db lsls r3, r3, #23
8001a06: 2200 movs r2, #0
8001a08: 2110 movs r1, #16
8001a0a: 0018 movs r0, r3
8001a0c: f7ff fac7 bl 8000f9e <HAL_GPIO_WritePin>
}
8001a10: 46c0 nop ; (mov r8, r8)
8001a12: 46bd mov sp, r7
8001a14: b004 add sp, #16
8001a16: bd80 pop {r7, pc}
08001a18 <display>:
void display()
{
8001a18: b580 push {r7, lr}
8001a1a: b082 sub sp, #8
8001a1c: af00 add r7, sp, #0
char h_buff=0,l_buff=0;
8001a1e: 1dfb adds r3, r7, #7
8001a20: 2200 movs r2, #0
8001a22: 701a strb r2, [r3, #0]
8001a24: 1dbb adds r3, r7, #6
8001a26: 2200 movs r2, #0
8001a28: 701a strb r2, [r3, #0]
Send_to_595(h_buff,l_buff);
8001a2a: 1dbb adds r3, r7, #6
8001a2c: 781a ldrb r2, [r3, #0]
8001a2e: 1dfb adds r3, r7, #7
8001a30: 781b ldrb r3, [r3, #0]
8001a32: 0011 movs r1, r2
8001a34: 0018 movs r0, r3
8001a36: f7ff ff78 bl 800192a <Send_to_595>
h_buff=0,l_buff=0;
8001a3a: 1dfb adds r3, r7, #7
8001a3c: 2200 movs r2, #0
8001a3e: 701a strb r2, [r3, #0]
8001a40: 1dbb adds r3, r7, #6
8001a42: 2200 movs r2, #0
8001a44: 701a strb r2, [r3, #0]
h_buff=~0x01;
8001a46: 1dfb adds r3, r7, #7
8001a48: 22fe movs r2, #254 ; 0xfe
8001a4a: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[0]>=10?0:d_num_data[0][dis_buff.d_num[0]];
8001a4c: 4b6f ldr r3, [pc, #444] ; (8001c0c <display+0x1f4>)
8001a4e: 781b ldrb r3, [r3, #0]
8001a50: 2b09 cmp r3, #9
8001a52: d805 bhi.n 8001a60 <display+0x48>
8001a54: 4b6d ldr r3, [pc, #436] ; (8001c0c <display+0x1f4>)
8001a56: 781b ldrb r3, [r3, #0]
8001a58: 001a movs r2, r3
8001a5a: 4b6d ldr r3, [pc, #436] ; (8001c10 <display+0x1f8>)
8001a5c: 5c9a ldrb r2, [r3, r2]
8001a5e: e000 b.n 8001a62 <display+0x4a>
8001a60: 2200 movs r2, #0
8001a62: 1dbb adds r3, r7, #6
8001a64: 701a strb r2, [r3, #0]
if(dis_buff.dot1==1)
8001a66: 4b69 ldr r3, [pc, #420] ; (8001c0c <display+0x1f4>)
8001a68: 791b ldrb r3, [r3, #4]
8001a6a: 2201 movs r2, #1
8001a6c: 4013 ands r3, r2
8001a6e: b2db uxtb r3, r3
8001a70: 2b00 cmp r3, #0
8001a72: d006 beq.n 8001a82 <display+0x6a>
{
l_buff|=0x80;
8001a74: 1dbb adds r3, r7, #6
8001a76: 1dba adds r2, r7, #6
8001a78: 7812 ldrb r2, [r2, #0]
8001a7a: 2180 movs r1, #128 ; 0x80
8001a7c: 4249 negs r1, r1
8001a7e: 430a orrs r2, r1
8001a80: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001a82: 1dbb adds r3, r7, #6
8001a84: 781a ldrb r2, [r3, #0]
8001a86: 1dfb adds r3, r7, #7
8001a88: 781b ldrb r3, [r3, #0]
8001a8a: 0011 movs r1, r2
8001a8c: 0018 movs r0, r3
8001a8e: f7ff ff4c bl 800192a <Send_to_595>
h_buff=0,l_buff=0;
8001a92: 1dfb adds r3, r7, #7
8001a94: 2200 movs r2, #0
8001a96: 701a strb r2, [r3, #0]
8001a98: 1dbb adds r3, r7, #6
8001a9a: 2200 movs r2, #0
8001a9c: 701a strb r2, [r3, #0]
h_buff=~0x80;
8001a9e: 1dfb adds r3, r7, #7
8001aa0: 227f movs r2, #127 ; 0x7f
8001aa2: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[0]>=10?0:d_num_data[1][dis_buff.d_num[1]];
8001aa4: 4b59 ldr r3, [pc, #356] ; (8001c0c <display+0x1f4>)
8001aa6: 781b ldrb r3, [r3, #0]
8001aa8: 2b09 cmp r3, #9
8001aaa: d806 bhi.n 8001aba <display+0xa2>
8001aac: 4b57 ldr r3, [pc, #348] ; (8001c0c <display+0x1f4>)
8001aae: 785b ldrb r3, [r3, #1]
8001ab0: 001a movs r2, r3
8001ab2: 4b57 ldr r3, [pc, #348] ; (8001c10 <display+0x1f8>)
8001ab4: 189b adds r3, r3, r2
8001ab6: 7a9a ldrb r2, [r3, #10]
8001ab8: e000 b.n 8001abc <display+0xa4>
8001aba: 2200 movs r2, #0
8001abc: 1dbb adds r3, r7, #6
8001abe: 701a strb r2, [r3, #0]
if(dis_buff.dot2==1)
8001ac0: 4b52 ldr r3, [pc, #328] ; (8001c0c <display+0x1f4>)
8001ac2: 791b ldrb r3, [r3, #4]
8001ac4: 2202 movs r2, #2
8001ac6: 4013 ands r3, r2
8001ac8: b2db uxtb r3, r3
8001aca: 2b00 cmp r3, #0
8001acc: d005 beq.n 8001ada <display+0xc2>
{
l_buff|=0x10;
8001ace: 1dbb adds r3, r7, #6
8001ad0: 1dba adds r2, r7, #6
8001ad2: 7812 ldrb r2, [r2, #0]
8001ad4: 2110 movs r1, #16
8001ad6: 430a orrs r2, r1
8001ad8: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001ada: 1dbb adds r3, r7, #6
8001adc: 781a ldrb r2, [r3, #0]
8001ade: 1dfb adds r3, r7, #7
8001ae0: 781b ldrb r3, [r3, #0]
8001ae2: 0011 movs r1, r2
8001ae4: 0018 movs r0, r3
8001ae6: f7ff ff20 bl 800192a <Send_to_595>
h_buff=0,l_buff=0;
8001aea: 1dfb adds r3, r7, #7
8001aec: 2200 movs r2, #0
8001aee: 701a strb r2, [r3, #0]
8001af0: 1dbb adds r3, r7, #6
8001af2: 2200 movs r2, #0
8001af4: 701a strb r2, [r3, #0]
h_buff=~0x40;
8001af6: 1dfb adds r3, r7, #7
8001af8: 22bf movs r2, #191 ; 0xbf
8001afa: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[0]>=10?0:d_num_data[0][dis_buff.d_num[2]];
8001afc: 4b43 ldr r3, [pc, #268] ; (8001c0c <display+0x1f4>)
8001afe: 781b ldrb r3, [r3, #0]
8001b00: 2b09 cmp r3, #9
8001b02: d805 bhi.n 8001b10 <display+0xf8>
8001b04: 4b41 ldr r3, [pc, #260] ; (8001c0c <display+0x1f4>)
8001b06: 789b ldrb r3, [r3, #2]
8001b08: 001a movs r2, r3
8001b0a: 4b41 ldr r3, [pc, #260] ; (8001c10 <display+0x1f8>)
8001b0c: 5c9a ldrb r2, [r3, r2]
8001b0e: e000 b.n 8001b12 <display+0xfa>
8001b10: 2200 movs r2, #0
8001b12: 1dbb adds r3, r7, #6
8001b14: 701a strb r2, [r3, #0]
if(dis_buff.dot3==1)
8001b16: 4b3d ldr r3, [pc, #244] ; (8001c0c <display+0x1f4>)
8001b18: 791b ldrb r3, [r3, #4]
8001b1a: 2204 movs r2, #4
8001b1c: 4013 ands r3, r2
8001b1e: b2db uxtb r3, r3
8001b20: 2b00 cmp r3, #0
8001b22: d006 beq.n 8001b32 <display+0x11a>
{
l_buff|=0x80;
8001b24: 1dbb adds r3, r7, #6
8001b26: 1dba adds r2, r7, #6
8001b28: 7812 ldrb r2, [r2, #0]
8001b2a: 2180 movs r1, #128 ; 0x80
8001b2c: 4249 negs r1, r1
8001b2e: 430a orrs r2, r1
8001b30: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001b32: 1dbb adds r3, r7, #6
8001b34: 781a ldrb r2, [r3, #0]
8001b36: 1dfb adds r3, r7, #7
8001b38: 781b ldrb r3, [r3, #0]
8001b3a: 0011 movs r1, r2
8001b3c: 0018 movs r0, r3
8001b3e: f7ff fef4 bl 800192a <Send_to_595>
h_buff=0,l_buff=0;
8001b42: 1dfb adds r3, r7, #7
8001b44: 2200 movs r2, #0
8001b46: 701a strb r2, [r3, #0]
8001b48: 1dbb adds r3, r7, #6
8001b4a: 2200 movs r2, #0
8001b4c: 701a strb r2, [r3, #0]
h_buff=0xC1;
8001b4e: 1dfb adds r3, r7, #7
8001b50: 22c1 movs r2, #193 ; 0xc1
8001b52: 701a strb r2, [r3, #0]
l_buff=dis_buff.d_num[0]>=10?0:d_num_data[1][dis_buff.d_num[3]];
8001b54: 4b2d ldr r3, [pc, #180] ; (8001c0c <display+0x1f4>)
8001b56: 781b ldrb r3, [r3, #0]
8001b58: 2b09 cmp r3, #9
8001b5a: d806 bhi.n 8001b6a <display+0x152>
8001b5c: 4b2b ldr r3, [pc, #172] ; (8001c0c <display+0x1f4>)
8001b5e: 78db ldrb r3, [r3, #3]
8001b60: 001a movs r2, r3
8001b62: 4b2b ldr r3, [pc, #172] ; (8001c10 <display+0x1f8>)
8001b64: 189b adds r3, r3, r2
8001b66: 7a9a ldrb r2, [r3, #10]
8001b68: e000 b.n 8001b6c <display+0x154>
8001b6a: 2200 movs r2, #0
8001b6c: 1dbb adds r3, r7, #6
8001b6e: 701a strb r2, [r3, #0]
if(dis_buff.dot4==1)
8001b70: 4b26 ldr r3, [pc, #152] ; (8001c0c <display+0x1f4>)
8001b72: 791b ldrb r3, [r3, #4]
8001b74: 2208 movs r2, #8
8001b76: 4013 ands r3, r2
8001b78: b2db uxtb r3, r3
8001b7a: 2b00 cmp r3, #0
8001b7c: d005 beq.n 8001b8a <display+0x172>
{
l_buff|=0x10;
8001b7e: 1dbb adds r3, r7, #6
8001b80: 1dba adds r2, r7, #6
8001b82: 7812 ldrb r2, [r2, #0]
8001b84: 2110 movs r1, #16
8001b86: 430a orrs r2, r1
8001b88: 701a strb r2, [r3, #0]
}
if(dis_buff.led_run==1)
8001b8a: 4b20 ldr r3, [pc, #128] ; (8001c0c <display+0x1f4>)
8001b8c: 791b ldrb r3, [r3, #4]
8001b8e: 2210 movs r2, #16
8001b90: 4013 ands r3, r2
8001b92: b2db uxtb r3, r3
8001b94: 2b00 cmp r3, #0
8001b96: d005 beq.n 8001ba4 <display+0x18c>
{
h_buff|=0x10;
8001b98: 1dfb adds r3, r7, #7
8001b9a: 1dfa adds r2, r7, #7
8001b9c: 7812 ldrb r2, [r2, #0]
8001b9e: 2110 movs r1, #16
8001ba0: 430a orrs r2, r1
8001ba2: 701a strb r2, [r3, #0]
}
if(dis_buff.led_err==1)
8001ba4: 4b19 ldr r3, [pc, #100] ; (8001c0c <display+0x1f4>)
8001ba6: 791b ldrb r3, [r3, #4]
8001ba8: 227f movs r2, #127 ; 0x7f
8001baa: 4393 bics r3, r2
8001bac: b2db uxtb r3, r3
8001bae: 2b00 cmp r3, #0
8001bb0: d005 beq.n 8001bbe <display+0x1a6>
{
h_buff|=0x08;
8001bb2: 1dfb adds r3, r7, #7
8001bb4: 1dfa adds r2, r7, #7
8001bb6: 7812 ldrb r2, [r2, #0]
8001bb8: 2108 movs r1, #8
8001bba: 430a orrs r2, r1
8001bbc: 701a strb r2, [r3, #0]
}
if(dis_buff.led_n==1)
8001bbe: 4b13 ldr r3, [pc, #76] ; (8001c0c <display+0x1f4>)
8001bc0: 791b ldrb r3, [r3, #4]
8001bc2: 2240 movs r2, #64 ; 0x40
8001bc4: 4013 ands r3, r2
8001bc6: b2db uxtb r3, r3
8001bc8: 2b00 cmp r3, #0
8001bca: d005 beq.n 8001bd8 <display+0x1c0>
{
h_buff|=0x04;
8001bcc: 1dfb adds r3, r7, #7
8001bce: 1dfa adds r2, r7, #7
8001bd0: 7812 ldrb r2, [r2, #0]
8001bd2: 2104 movs r1, #4
8001bd4: 430a orrs r2, r1
8001bd6: 701a strb r2, [r3, #0]
}
if(dis_buff.led_p==1)
8001bd8: 4b0c ldr r3, [pc, #48] ; (8001c0c <display+0x1f4>)
8001bda: 791b ldrb r3, [r3, #4]
8001bdc: 2220 movs r2, #32
8001bde: 4013 ands r3, r2
8001be0: b2db uxtb r3, r3
8001be2: 2b00 cmp r3, #0
8001be4: d005 beq.n 8001bf2 <display+0x1da>
{
h_buff|=0x02;
8001be6: 1dfb adds r3, r7, #7
8001be8: 1dfa adds r2, r7, #7
8001bea: 7812 ldrb r2, [r2, #0]
8001bec: 2102 movs r1, #2
8001bee: 430a orrs r2, r1
8001bf0: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001bf2: 1dbb adds r3, r7, #6
8001bf4: 781a ldrb r2, [r3, #0]
8001bf6: 1dfb adds r3, r7, #7
8001bf8: 781b ldrb r3, [r3, #0]
8001bfa: 0011 movs r1, r2
8001bfc: 0018 movs r0, r3
8001bfe: f7ff fe94 bl 800192a <Send_to_595>
}
8001c02: 46c0 nop ; (mov r8, r8)
8001c04: 46bd mov sp, r7
8001c06: b002 add sp, #8
8001c08: bd80 pop {r7, pc}
8001c0a: 46c0 nop ; (mov r8, r8)
8001c0c: 20000078 .word 0x20000078
8001c10: 08001de4 .word 0x08001de4
08001c14 <mymain>:
void mymain()
{
8001c14: b580 push {r7, lr}
8001c16: b082 sub sp, #8
8001c18: af00 add r7, sp, #0
uint32_t runtime=0;
8001c1a: 2300 movs r3, #0
8001c1c: 607b str r3, [r7, #4]
MOTA(0);
8001c1e: 4b43 ldr r3, [pc, #268] ; (8001d2c <mymain+0x118>)
8001c20: 2200 movs r2, #0
8001c22: 2101 movs r1, #1
8001c24: 0018 movs r0, r3
8001c26: f7ff f9ba bl 8000f9e <HAL_GPIO_WritePin>
MOTB(0);
8001c2a: 4b40 ldr r3, [pc, #256] ; (8001d2c <mymain+0x118>)
8001c2c: 2200 movs r2, #0
8001c2e: 2102 movs r1, #2
8001c30: 0018 movs r0, r3
8001c32: f7ff f9b4 bl 8000f9e <HAL_GPIO_WritePin>
HC595_DCK(0);
8001c36: 2390 movs r3, #144 ; 0x90
8001c38: 05db lsls r3, r3, #23
8001c3a: 2200 movs r2, #0
8001c3c: 2108 movs r1, #8
8001c3e: 0018 movs r0, r3
8001c40: f7ff f9ad bl 8000f9e <HAL_GPIO_WritePin>
HC595_RCK(0);
8001c44: 2390 movs r3, #144 ; 0x90
8001c46: 05db lsls r3, r3, #23
8001c48: 2200 movs r2, #0
8001c4a: 2110 movs r1, #16
8001c4c: 0018 movs r0, r3
8001c4e: f7ff f9a6 bl 8000f9e <HAL_GPIO_WritePin>
HC595_SCK(0);
8001c52: 2390 movs r3, #144 ; 0x90
8001c54: 05db lsls r3, r3, #23
8001c56: 2200 movs r2, #0
8001c58: 2120 movs r1, #32
8001c5a: 0018 movs r0, r3
8001c5c: f7ff f99f bl 8000f9e <HAL_GPIO_WritePin>
dis_buff.d_num[0]=0xff;
8001c60: 4b33 ldr r3, [pc, #204] ; (8001d30 <mymain+0x11c>)
8001c62: 22ff movs r2, #255 ; 0xff
8001c64: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=0xff;
8001c66: 4b32 ldr r3, [pc, #200] ; (8001d30 <mymain+0x11c>)
8001c68: 22ff movs r2, #255 ; 0xff
8001c6a: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=0xff;
8001c6c: 4b30 ldr r3, [pc, #192] ; (8001d30 <mymain+0x11c>)
8001c6e: 22ff movs r2, #255 ; 0xff
8001c70: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=0xff;
8001c72: 4b2f ldr r3, [pc, #188] ; (8001d30 <mymain+0x11c>)
8001c74: 22ff movs r2, #255 ; 0xff
8001c76: 70da strb r2, [r3, #3]
while(1)
{
if(HAL_GetTick()>runtime)
8001c78: f7fe fd10 bl 800069c <HAL_GetTick>
8001c7c: 0002 movs r2, r0
8001c7e: 687b ldr r3, [r7, #4]
8001c80: 4293 cmp r3, r2
8001c82: d217 bcs.n 8001cb4 <mymain+0xa0>
{
runtime+=1000;
8001c84: 687b ldr r3, [r7, #4]
8001c86: 22fa movs r2, #250 ; 0xfa
8001c88: 0092 lsls r2, r2, #2
8001c8a: 4694 mov ip, r2
8001c8c: 4463 add r3, ip
8001c8e: 607b str r3, [r7, #4]
dis_buff.led_err=rand()%2;
dis_buff.led_n=rand()%2;
dis_buff.led_p=rand()%2;
dis_buff.led_run=rand()%2;
*/
if(dis_buff.led_run==1)
8001c90: 4b27 ldr r3, [pc, #156] ; (8001d30 <mymain+0x11c>)
8001c92: 791b ldrb r3, [r3, #4]
8001c94: 2210 movs r2, #16
8001c96: 4013 ands r3, r2
8001c98: b2db uxtb r3, r3
8001c9a: 2b00 cmp r3, #0
8001c9c: d005 beq.n 8001caa <mymain+0x96>
{
dis_buff.led_run=0;
8001c9e: 4b24 ldr r3, [pc, #144] ; (8001d30 <mymain+0x11c>)
8001ca0: 791a ldrb r2, [r3, #4]
8001ca2: 2110 movs r1, #16
8001ca4: 438a bics r2, r1
8001ca6: 711a strb r2, [r3, #4]
8001ca8: e004 b.n 8001cb4 <mymain+0xa0>
}else
{
dis_buff.led_run=1;
8001caa: 4b21 ldr r3, [pc, #132] ; (8001d30 <mymain+0x11c>)
8001cac: 791a ldrb r2, [r3, #4]
8001cae: 2110 movs r1, #16
8001cb0: 430a orrs r2, r1
8001cb2: 711a strb r2, [r3, #4]
}
}
GEI_BUTTON_CODE(&key1,KEY1);
8001cb4: 2390 movs r3, #144 ; 0x90
8001cb6: 05db lsls r3, r3, #23
8001cb8: 2140 movs r1, #64 ; 0x40
8001cba: 0018 movs r0, r3
8001cbc: f7ff f952 bl 8000f64 <HAL_GPIO_ReadPin>
8001cc0: 0003 movs r3, r0
8001cc2: 001a movs r2, r3
8001cc4: 4b1b ldr r3, [pc, #108] ; (8001d34 <mymain+0x120>)
8001cc6: 0011 movs r1, r2
8001cc8: 0018 movs r0, r3
8001cca: f7ff fdd1 bl 8001870 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key2,KEY2);
8001cce: 2390 movs r3, #144 ; 0x90
8001cd0: 05db lsls r3, r3, #23
8001cd2: 2180 movs r1, #128 ; 0x80
8001cd4: 0018 movs r0, r3
8001cd6: f7ff f945 bl 8000f64 <HAL_GPIO_ReadPin>
8001cda: 0003 movs r3, r0
8001cdc: 001a movs r2, r3
8001cde: 4b16 ldr r3, [pc, #88] ; (8001d38 <mymain+0x124>)
8001ce0: 0011 movs r1, r2
8001ce2: 0018 movs r0, r3
8001ce4: f7ff fdc4 bl 8001870 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key3,KEY3);
8001ce8: 2380 movs r3, #128 ; 0x80
8001cea: 009a lsls r2, r3, #2
8001cec: 2390 movs r3, #144 ; 0x90
8001cee: 05db lsls r3, r3, #23
8001cf0: 0011 movs r1, r2
8001cf2: 0018 movs r0, r3
8001cf4: f7ff f936 bl 8000f64 <HAL_GPIO_ReadPin>
8001cf8: 0003 movs r3, r0
8001cfa: 001a movs r2, r3
8001cfc: 4b0f ldr r3, [pc, #60] ; (8001d3c <mymain+0x128>)
8001cfe: 0011 movs r1, r2
8001d00: 0018 movs r0, r3
8001d02: f7ff fdb5 bl 8001870 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key4,KEY4);
8001d06: 2380 movs r3, #128 ; 0x80
8001d08: 00da lsls r2, r3, #3
8001d0a: 2390 movs r3, #144 ; 0x90
8001d0c: 05db lsls r3, r3, #23
8001d0e: 0011 movs r1, r2
8001d10: 0018 movs r0, r3
8001d12: f7ff f927 bl 8000f64 <HAL_GPIO_ReadPin>
8001d16: 0003 movs r3, r0
8001d18: 001a movs r2, r3
8001d1a: 4b09 ldr r3, [pc, #36] ; (8001d40 <mymain+0x12c>)
8001d1c: 0011 movs r1, r2
8001d1e: 0018 movs r0, r3
8001d20: f7ff fda6 bl 8001870 <GEI_BUTTON_CODE>
display();
8001d24: f7ff fe78 bl 8001a18 <display>
if(HAL_GetTick()>runtime)
8001d28: e7a6 b.n 8001c78 <mymain+0x64>
8001d2a: 46c0 nop ; (mov r8, r8)
8001d2c: 48001400 .word 0x48001400
8001d30: 20000078 .word 0x20000078
8001d34: 20000080 .word 0x20000080
8001d38: 20000098 .word 0x20000098
8001d3c: 2000008c .word 0x2000008c
8001d40: 2000006c .word 0x2000006c
08001d44 <__libc_init_array>:
8001d44: b570 push {r4, r5, r6, lr}
8001d46: 2600 movs r6, #0
8001d48: 4d0c ldr r5, [pc, #48] ; (8001d7c <__libc_init_array+0x38>)
8001d4a: 4c0d ldr r4, [pc, #52] ; (8001d80 <__libc_init_array+0x3c>)
8001d4c: 1b64 subs r4, r4, r5
8001d4e: 10a4 asrs r4, r4, #2
8001d50: 42a6 cmp r6, r4
8001d52: d109 bne.n 8001d68 <__libc_init_array+0x24>
8001d54: 2600 movs r6, #0
8001d56: f000 f821 bl 8001d9c <_init>
8001d5a: 4d0a ldr r5, [pc, #40] ; (8001d84 <__libc_init_array+0x40>)
8001d5c: 4c0a ldr r4, [pc, #40] ; (8001d88 <__libc_init_array+0x44>)
8001d5e: 1b64 subs r4, r4, r5
8001d60: 10a4 asrs r4, r4, #2
8001d62: 42a6 cmp r6, r4
8001d64: d105 bne.n 8001d72 <__libc_init_array+0x2e>
8001d66: bd70 pop {r4, r5, r6, pc}
8001d68: 00b3 lsls r3, r6, #2
8001d6a: 58eb ldr r3, [r5, r3]
8001d6c: 4798 blx r3
8001d6e: 3601 adds r6, #1
8001d70: e7ee b.n 8001d50 <__libc_init_array+0xc>
8001d72: 00b3 lsls r3, r6, #2
8001d74: 58eb ldr r3, [r5, r3]
8001d76: 4798 blx r3
8001d78: 3601 adds r6, #1
8001d7a: e7f2 b.n 8001d62 <__libc_init_array+0x1e>
8001d7c: 08001df8 .word 0x08001df8
8001d80: 08001df8 .word 0x08001df8
8001d84: 08001df8 .word 0x08001df8
8001d88: 08001dfc .word 0x08001dfc
08001d8c <memset>:
8001d8c: 0003 movs r3, r0
8001d8e: 1882 adds r2, r0, r2
8001d90: 4293 cmp r3, r2
8001d92: d100 bne.n 8001d96 <memset+0xa>
8001d94: 4770 bx lr
8001d96: 7019 strb r1, [r3, #0]
8001d98: 3301 adds r3, #1
8001d9a: e7f9 b.n 8001d90 <memset+0x4>
08001d9c <_init>:
8001d9c: b5f8 push {r3, r4, r5, r6, r7, lr}
8001d9e: 46c0 nop ; (mov r8, r8)
8001da0: bcf8 pop {r3, r4, r5, r6, r7}
8001da2: bc08 pop {r3}
8001da4: 469e mov lr, r3
8001da6: 4770 bx lr
08001da8 <_fini>:
8001da8: b5f8 push {r3, r4, r5, r6, r7, lr}
8001daa: 46c0 nop ; (mov r8, r8)
8001dac: bcf8 pop {r3, r4, r5, r6, r7}
8001dae: bc08 pop {r3}
8001db0: 469e mov lr, r3
8001db2: 4770 bx lr
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