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31f70a306ade8bdca78a3f85c8409887927df68d
motor_controller/Debug/Motor_Controller.list
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kevin 31f70a306a 创建了基本工程
2021-09-17 22:25:54 +08:00

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Motor_Controller.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00000e5c 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 08000f1c 08000f1c 00010f1c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08000f4c 08000f4c 0002000c 2**0
CONTENTS
4 .ARM 00000000 08000f4c 08000f4c 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08000f4c 08000f4c 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08000f4c 08000f4c 00010f4c 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08000f50 08000f50 00010f50 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08000f54 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000020 2000000c 08000f60 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000002c 08000f60 0002002c 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00002395 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00000cb7 00000000 00000000 000223c9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000318 00000000 00000000 00023080 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000290 00000000 00000000 00023398 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0000de81 00000000 00000000 00023628 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000043b1 00000000 00000000 000314a9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0005322e 00000000 00000000 0003585a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 00088a88 2**0
CONTENTS, READONLY
20 .debug_frame 00000914 00000000 00000000 00088adc 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 08000f04 .word 0x08000f04
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 08000f04 .word 0x08000f04
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__aeabi_idiv0>:
800021c: 4770 bx lr
800021e: 46c0 nop ; (mov r8, r8)
08000220 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000220: b580 push {r7, lr}
8000222: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000224: f000 f8da bl 80003dc <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000228: f000 f805 bl 8000236 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800022c: f000 f84e bl 80002cc <MX_GPIO_Init>
/* USER CODE BEGIN 2 */
mymain();
8000230: f000 fe38 bl 8000ea4 <mymain>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000234: e7fe b.n 8000234 <main+0x14>
08000236 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000236: b590 push {r4, r7, lr}
8000238: b091 sub sp, #68 ; 0x44
800023a: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800023c: 2410 movs r4, #16
800023e: 193b adds r3, r7, r4
8000240: 0018 movs r0, r3
8000242: 2330 movs r3, #48 ; 0x30
8000244: 001a movs r2, r3
8000246: 2100 movs r1, #0
8000248: f000 fe54 bl 8000ef4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800024c: 003b movs r3, r7
800024e: 0018 movs r0, r3
8000250: 2310 movs r3, #16
8000252: 001a movs r2, r3
8000254: 2100 movs r1, #0
8000256: f000 fe4d bl 8000ef4 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800025a: 0021 movs r1, r4
800025c: 187b adds r3, r7, r1
800025e: 2202 movs r2, #2
8000260: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000262: 187b adds r3, r7, r1
8000264: 2201 movs r2, #1
8000266: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000268: 187b adds r3, r7, r1
800026a: 2210 movs r2, #16
800026c: 611a str r2, [r3, #16]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800026e: 187b adds r3, r7, r1
8000270: 2202 movs r2, #2
8000272: 621a str r2, [r3, #32]
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000274: 187b adds r3, r7, r1
8000276: 2200 movs r2, #0
8000278: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
800027a: 187b adds r3, r7, r1
800027c: 22a0 movs r2, #160 ; 0xa0
800027e: 0392 lsls r2, r2, #14
8000280: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
8000282: 187b adds r3, r7, r1
8000284: 2200 movs r2, #0
8000286: 62da str r2, [r3, #44] ; 0x2c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000288: 187b adds r3, r7, r1
800028a: 0018 movs r0, r3
800028c: f000 f9be bl 800060c <HAL_RCC_OscConfig>
8000290: 1e03 subs r3, r0, #0
8000292: d001 beq.n 8000298 <SystemClock_Config+0x62>
{
Error_Handler();
8000294: f000 f832 bl 80002fc <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000298: 003b movs r3, r7
800029a: 2207 movs r2, #7
800029c: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800029e: 003b movs r3, r7
80002a0: 2202 movs r2, #2
80002a2: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002a4: 003b movs r3, r7
80002a6: 2200 movs r2, #0
80002a8: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80002aa: 003b movs r3, r7
80002ac: 2200 movs r2, #0
80002ae: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
80002b0: 003b movs r3, r7
80002b2: 2101 movs r1, #1
80002b4: 0018 movs r0, r3
80002b6: f000 fcc3 bl 8000c40 <HAL_RCC_ClockConfig>
80002ba: 1e03 subs r3, r0, #0
80002bc: d001 beq.n 80002c2 <SystemClock_Config+0x8c>
{
Error_Handler();
80002be: f000 f81d bl 80002fc <Error_Handler>
}
}
80002c2: 46c0 nop ; (mov r8, r8)
80002c4: 46bd mov sp, r7
80002c6: b011 add sp, #68 ; 0x44
80002c8: bd90 pop {r4, r7, pc}
...
080002cc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80002cc: b580 push {r7, lr}
80002ce: b082 sub sp, #8
80002d0: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
80002d2: 4b09 ldr r3, [pc, #36] ; (80002f8 <MX_GPIO_Init+0x2c>)
80002d4: 695a ldr r2, [r3, #20]
80002d6: 4b08 ldr r3, [pc, #32] ; (80002f8 <MX_GPIO_Init+0x2c>)
80002d8: 2180 movs r1, #128 ; 0x80
80002da: 0289 lsls r1, r1, #10
80002dc: 430a orrs r2, r1
80002de: 615a str r2, [r3, #20]
80002e0: 4b05 ldr r3, [pc, #20] ; (80002f8 <MX_GPIO_Init+0x2c>)
80002e2: 695a ldr r2, [r3, #20]
80002e4: 2380 movs r3, #128 ; 0x80
80002e6: 029b lsls r3, r3, #10
80002e8: 4013 ands r3, r2
80002ea: 607b str r3, [r7, #4]
80002ec: 687b ldr r3, [r7, #4]
}
80002ee: 46c0 nop ; (mov r8, r8)
80002f0: 46bd mov sp, r7
80002f2: b002 add sp, #8
80002f4: bd80 pop {r7, pc}
80002f6: 46c0 nop ; (mov r8, r8)
80002f8: 40021000 .word 0x40021000
080002fc <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80002fc: b580 push {r7, lr}
80002fe: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000300: b672 cpsid i
}
8000302: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000304: e7fe b.n 8000304 <Error_Handler+0x8>
...
08000308 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000308: b580 push {r7, lr}
800030a: b082 sub sp, #8
800030c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800030e: 4b0f ldr r3, [pc, #60] ; (800034c <HAL_MspInit+0x44>)
8000310: 699a ldr r2, [r3, #24]
8000312: 4b0e ldr r3, [pc, #56] ; (800034c <HAL_MspInit+0x44>)
8000314: 2101 movs r1, #1
8000316: 430a orrs r2, r1
8000318: 619a str r2, [r3, #24]
800031a: 4b0c ldr r3, [pc, #48] ; (800034c <HAL_MspInit+0x44>)
800031c: 699b ldr r3, [r3, #24]
800031e: 2201 movs r2, #1
8000320: 4013 ands r3, r2
8000322: 607b str r3, [r7, #4]
8000324: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000326: 4b09 ldr r3, [pc, #36] ; (800034c <HAL_MspInit+0x44>)
8000328: 69da ldr r2, [r3, #28]
800032a: 4b08 ldr r3, [pc, #32] ; (800034c <HAL_MspInit+0x44>)
800032c: 2180 movs r1, #128 ; 0x80
800032e: 0549 lsls r1, r1, #21
8000330: 430a orrs r2, r1
8000332: 61da str r2, [r3, #28]
8000334: 4b05 ldr r3, [pc, #20] ; (800034c <HAL_MspInit+0x44>)
8000336: 69da ldr r2, [r3, #28]
8000338: 2380 movs r3, #128 ; 0x80
800033a: 055b lsls r3, r3, #21
800033c: 4013 ands r3, r2
800033e: 603b str r3, [r7, #0]
8000340: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000342: 46c0 nop ; (mov r8, r8)
8000344: 46bd mov sp, r7
8000346: b002 add sp, #8
8000348: bd80 pop {r7, pc}
800034a: 46c0 nop ; (mov r8, r8)
800034c: 40021000 .word 0x40021000
08000350 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000350: b580 push {r7, lr}
8000352: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000354: e7fe b.n 8000354 <NMI_Handler+0x4>
08000356 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000356: b580 push {r7, lr}
8000358: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800035a: e7fe b.n 800035a <HardFault_Handler+0x4>
0800035c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800035c: b580 push {r7, lr}
800035e: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000360: 46c0 nop ; (mov r8, r8)
8000362: 46bd mov sp, r7
8000364: bd80 pop {r7, pc}
08000366 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000366: b580 push {r7, lr}
8000368: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800036a: 46c0 nop ; (mov r8, r8)
800036c: 46bd mov sp, r7
800036e: bd80 pop {r7, pc}
08000370 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000370: b580 push {r7, lr}
8000372: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000374: f000 f87a bl 800046c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000378: 46c0 nop ; (mov r8, r8)
800037a: 46bd mov sp, r7
800037c: bd80 pop {r7, pc}
0800037e <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
800037e: b580 push {r7, lr}
8000380: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
8000382: 46c0 nop ; (mov r8, r8)
8000384: 46bd mov sp, r7
8000386: bd80 pop {r7, pc}
08000388 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000388: 480d ldr r0, [pc, #52] ; (80003c0 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
800038a: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800038c: 480d ldr r0, [pc, #52] ; (80003c4 <LoopForever+0x6>)
ldr r1, =_edata
800038e: 490e ldr r1, [pc, #56] ; (80003c8 <LoopForever+0xa>)
ldr r2, =_sidata
8000390: 4a0e ldr r2, [pc, #56] ; (80003cc <LoopForever+0xe>)
movs r3, #0
8000392: 2300 movs r3, #0
b LoopCopyDataInit
8000394: e002 b.n 800039c <LoopCopyDataInit>
08000396 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000396: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000398: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800039a: 3304 adds r3, #4
0800039c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800039c: 18c4 adds r4, r0, r3
cmp r4, r1
800039e: 428c cmp r4, r1
bcc CopyDataInit
80003a0: d3f9 bcc.n 8000396 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80003a2: 4a0b ldr r2, [pc, #44] ; (80003d0 <LoopForever+0x12>)
ldr r4, =_ebss
80003a4: 4c0b ldr r4, [pc, #44] ; (80003d4 <LoopForever+0x16>)
movs r3, #0
80003a6: 2300 movs r3, #0
b LoopFillZerobss
80003a8: e001 b.n 80003ae <LoopFillZerobss>
080003aa <FillZerobss>:
FillZerobss:
str r3, [r2]
80003aa: 6013 str r3, [r2, #0]
adds r2, r2, #4
80003ac: 3204 adds r2, #4
080003ae <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80003ae: 42a2 cmp r2, r4
bcc FillZerobss
80003b0: d3fb bcc.n 80003aa <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80003b2: f7ff ffe4 bl 800037e <SystemInit>
/* Call static constructors */
bl __libc_init_array
80003b6: f000 fd79 bl 8000eac <__libc_init_array>
/* Call the application's entry point.*/
bl main
80003ba: f7ff ff31 bl 8000220 <main>
080003be <LoopForever>:
LoopForever:
b LoopForever
80003be: e7fe b.n 80003be <LoopForever>
ldr r0, =_estack
80003c0: 20001000 .word 0x20001000
ldr r0, =_sdata
80003c4: 20000000 .word 0x20000000
ldr r1, =_edata
80003c8: 2000000c .word 0x2000000c
ldr r2, =_sidata
80003cc: 08000f54 .word 0x08000f54
ldr r2, =_sbss
80003d0: 2000000c .word 0x2000000c
ldr r4, =_ebss
80003d4: 2000002c .word 0x2000002c
080003d8 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80003d8: e7fe b.n 80003d8 <ADC1_IRQHandler>
...
080003dc <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80003dc: b580 push {r7, lr}
80003de: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80003e0: 4b07 ldr r3, [pc, #28] ; (8000400 <HAL_Init+0x24>)
80003e2: 681a ldr r2, [r3, #0]
80003e4: 4b06 ldr r3, [pc, #24] ; (8000400 <HAL_Init+0x24>)
80003e6: 2110 movs r1, #16
80003e8: 430a orrs r2, r1
80003ea: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80003ec: 2003 movs r0, #3
80003ee: f000 f809 bl 8000404 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80003f2: f7ff ff89 bl 8000308 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80003f6: 2300 movs r3, #0
}
80003f8: 0018 movs r0, r3
80003fa: 46bd mov sp, r7
80003fc: bd80 pop {r7, pc}
80003fe: 46c0 nop ; (mov r8, r8)
8000400: 40022000 .word 0x40022000
08000404 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000404: b590 push {r4, r7, lr}
8000406: b083 sub sp, #12
8000408: af00 add r7, sp, #0
800040a: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
800040c: 4b14 ldr r3, [pc, #80] ; (8000460 <HAL_InitTick+0x5c>)
800040e: 681c ldr r4, [r3, #0]
8000410: 4b14 ldr r3, [pc, #80] ; (8000464 <HAL_InitTick+0x60>)
8000412: 781b ldrb r3, [r3, #0]
8000414: 0019 movs r1, r3
8000416: 23fa movs r3, #250 ; 0xfa
8000418: 0098 lsls r0, r3, #2
800041a: f7ff fe75 bl 8000108 <__udivsi3>
800041e: 0003 movs r3, r0
8000420: 0019 movs r1, r3
8000422: 0020 movs r0, r4
8000424: f7ff fe70 bl 8000108 <__udivsi3>
8000428: 0003 movs r3, r0
800042a: 0018 movs r0, r3
800042c: f000 f8e1 bl 80005f2 <HAL_SYSTICK_Config>
8000430: 1e03 subs r3, r0, #0
8000432: d001 beq.n 8000438 <HAL_InitTick+0x34>
{
return HAL_ERROR;
8000434: 2301 movs r3, #1
8000436: e00f b.n 8000458 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000438: 687b ldr r3, [r7, #4]
800043a: 2b03 cmp r3, #3
800043c: d80b bhi.n 8000456 <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800043e: 6879 ldr r1, [r7, #4]
8000440: 2301 movs r3, #1
8000442: 425b negs r3, r3
8000444: 2200 movs r2, #0
8000446: 0018 movs r0, r3
8000448: f000 f8be bl 80005c8 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800044c: 4b06 ldr r3, [pc, #24] ; (8000468 <HAL_InitTick+0x64>)
800044e: 687a ldr r2, [r7, #4]
8000450: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000452: 2300 movs r3, #0
8000454: e000 b.n 8000458 <HAL_InitTick+0x54>
return HAL_ERROR;
8000456: 2301 movs r3, #1
}
8000458: 0018 movs r0, r3
800045a: 46bd mov sp, r7
800045c: b003 add sp, #12
800045e: bd90 pop {r4, r7, pc}
8000460: 20000000 .word 0x20000000
8000464: 20000008 .word 0x20000008
8000468: 20000004 .word 0x20000004
0800046c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800046c: b580 push {r7, lr}
800046e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000470: 4b05 ldr r3, [pc, #20] ; (8000488 <HAL_IncTick+0x1c>)
8000472: 781b ldrb r3, [r3, #0]
8000474: 001a movs r2, r3
8000476: 4b05 ldr r3, [pc, #20] ; (800048c <HAL_IncTick+0x20>)
8000478: 681b ldr r3, [r3, #0]
800047a: 18d2 adds r2, r2, r3
800047c: 4b03 ldr r3, [pc, #12] ; (800048c <HAL_IncTick+0x20>)
800047e: 601a str r2, [r3, #0]
}
8000480: 46c0 nop ; (mov r8, r8)
8000482: 46bd mov sp, r7
8000484: bd80 pop {r7, pc}
8000486: 46c0 nop ; (mov r8, r8)
8000488: 20000008 .word 0x20000008
800048c: 20000028 .word 0x20000028
08000490 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000490: b580 push {r7, lr}
8000492: af00 add r7, sp, #0
return uwTick;
8000494: 4b02 ldr r3, [pc, #8] ; (80004a0 <HAL_GetTick+0x10>)
8000496: 681b ldr r3, [r3, #0]
}
8000498: 0018 movs r0, r3
800049a: 46bd mov sp, r7
800049c: bd80 pop {r7, pc}
800049e: 46c0 nop ; (mov r8, r8)
80004a0: 20000028 .word 0x20000028
080004a4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80004a4: b590 push {r4, r7, lr}
80004a6: b083 sub sp, #12
80004a8: af00 add r7, sp, #0
80004aa: 0002 movs r2, r0
80004ac: 6039 str r1, [r7, #0]
80004ae: 1dfb adds r3, r7, #7
80004b0: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80004b2: 1dfb adds r3, r7, #7
80004b4: 781b ldrb r3, [r3, #0]
80004b6: 2b7f cmp r3, #127 ; 0x7f
80004b8: d828 bhi.n 800050c <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80004ba: 4a2f ldr r2, [pc, #188] ; (8000578 <__NVIC_SetPriority+0xd4>)
80004bc: 1dfb adds r3, r7, #7
80004be: 781b ldrb r3, [r3, #0]
80004c0: b25b sxtb r3, r3
80004c2: 089b lsrs r3, r3, #2
80004c4: 33c0 adds r3, #192 ; 0xc0
80004c6: 009b lsls r3, r3, #2
80004c8: 589b ldr r3, [r3, r2]
80004ca: 1dfa adds r2, r7, #7
80004cc: 7812 ldrb r2, [r2, #0]
80004ce: 0011 movs r1, r2
80004d0: 2203 movs r2, #3
80004d2: 400a ands r2, r1
80004d4: 00d2 lsls r2, r2, #3
80004d6: 21ff movs r1, #255 ; 0xff
80004d8: 4091 lsls r1, r2
80004da: 000a movs r2, r1
80004dc: 43d2 mvns r2, r2
80004de: 401a ands r2, r3
80004e0: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80004e2: 683b ldr r3, [r7, #0]
80004e4: 019b lsls r3, r3, #6
80004e6: 22ff movs r2, #255 ; 0xff
80004e8: 401a ands r2, r3
80004ea: 1dfb adds r3, r7, #7
80004ec: 781b ldrb r3, [r3, #0]
80004ee: 0018 movs r0, r3
80004f0: 2303 movs r3, #3
80004f2: 4003 ands r3, r0
80004f4: 00db lsls r3, r3, #3
80004f6: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80004f8: 481f ldr r0, [pc, #124] ; (8000578 <__NVIC_SetPriority+0xd4>)
80004fa: 1dfb adds r3, r7, #7
80004fc: 781b ldrb r3, [r3, #0]
80004fe: b25b sxtb r3, r3
8000500: 089b lsrs r3, r3, #2
8000502: 430a orrs r2, r1
8000504: 33c0 adds r3, #192 ; 0xc0
8000506: 009b lsls r3, r3, #2
8000508: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
800050a: e031 b.n 8000570 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800050c: 4a1b ldr r2, [pc, #108] ; (800057c <__NVIC_SetPriority+0xd8>)
800050e: 1dfb adds r3, r7, #7
8000510: 781b ldrb r3, [r3, #0]
8000512: 0019 movs r1, r3
8000514: 230f movs r3, #15
8000516: 400b ands r3, r1
8000518: 3b08 subs r3, #8
800051a: 089b lsrs r3, r3, #2
800051c: 3306 adds r3, #6
800051e: 009b lsls r3, r3, #2
8000520: 18d3 adds r3, r2, r3
8000522: 3304 adds r3, #4
8000524: 681b ldr r3, [r3, #0]
8000526: 1dfa adds r2, r7, #7
8000528: 7812 ldrb r2, [r2, #0]
800052a: 0011 movs r1, r2
800052c: 2203 movs r2, #3
800052e: 400a ands r2, r1
8000530: 00d2 lsls r2, r2, #3
8000532: 21ff movs r1, #255 ; 0xff
8000534: 4091 lsls r1, r2
8000536: 000a movs r2, r1
8000538: 43d2 mvns r2, r2
800053a: 401a ands r2, r3
800053c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800053e: 683b ldr r3, [r7, #0]
8000540: 019b lsls r3, r3, #6
8000542: 22ff movs r2, #255 ; 0xff
8000544: 401a ands r2, r3
8000546: 1dfb adds r3, r7, #7
8000548: 781b ldrb r3, [r3, #0]
800054a: 0018 movs r0, r3
800054c: 2303 movs r3, #3
800054e: 4003 ands r3, r0
8000550: 00db lsls r3, r3, #3
8000552: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000554: 4809 ldr r0, [pc, #36] ; (800057c <__NVIC_SetPriority+0xd8>)
8000556: 1dfb adds r3, r7, #7
8000558: 781b ldrb r3, [r3, #0]
800055a: 001c movs r4, r3
800055c: 230f movs r3, #15
800055e: 4023 ands r3, r4
8000560: 3b08 subs r3, #8
8000562: 089b lsrs r3, r3, #2
8000564: 430a orrs r2, r1
8000566: 3306 adds r3, #6
8000568: 009b lsls r3, r3, #2
800056a: 18c3 adds r3, r0, r3
800056c: 3304 adds r3, #4
800056e: 601a str r2, [r3, #0]
}
8000570: 46c0 nop ; (mov r8, r8)
8000572: 46bd mov sp, r7
8000574: b003 add sp, #12
8000576: bd90 pop {r4, r7, pc}
8000578: e000e100 .word 0xe000e100
800057c: e000ed00 .word 0xe000ed00
08000580 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000580: b580 push {r7, lr}
8000582: b082 sub sp, #8
8000584: af00 add r7, sp, #0
8000586: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000588: 687b ldr r3, [r7, #4]
800058a: 1e5a subs r2, r3, #1
800058c: 2380 movs r3, #128 ; 0x80
800058e: 045b lsls r3, r3, #17
8000590: 429a cmp r2, r3
8000592: d301 bcc.n 8000598 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8000594: 2301 movs r3, #1
8000596: e010 b.n 80005ba <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000598: 4b0a ldr r3, [pc, #40] ; (80005c4 <SysTick_Config+0x44>)
800059a: 687a ldr r2, [r7, #4]
800059c: 3a01 subs r2, #1
800059e: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80005a0: 2301 movs r3, #1
80005a2: 425b negs r3, r3
80005a4: 2103 movs r1, #3
80005a6: 0018 movs r0, r3
80005a8: f7ff ff7c bl 80004a4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80005ac: 4b05 ldr r3, [pc, #20] ; (80005c4 <SysTick_Config+0x44>)
80005ae: 2200 movs r2, #0
80005b0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80005b2: 4b04 ldr r3, [pc, #16] ; (80005c4 <SysTick_Config+0x44>)
80005b4: 2207 movs r2, #7
80005b6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80005b8: 2300 movs r3, #0
}
80005ba: 0018 movs r0, r3
80005bc: 46bd mov sp, r7
80005be: b002 add sp, #8
80005c0: bd80 pop {r7, pc}
80005c2: 46c0 nop ; (mov r8, r8)
80005c4: e000e010 .word 0xe000e010
080005c8 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80005c8: b580 push {r7, lr}
80005ca: b084 sub sp, #16
80005cc: af00 add r7, sp, #0
80005ce: 60b9 str r1, [r7, #8]
80005d0: 607a str r2, [r7, #4]
80005d2: 210f movs r1, #15
80005d4: 187b adds r3, r7, r1
80005d6: 1c02 adds r2, r0, #0
80005d8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
80005da: 68ba ldr r2, [r7, #8]
80005dc: 187b adds r3, r7, r1
80005de: 781b ldrb r3, [r3, #0]
80005e0: b25b sxtb r3, r3
80005e2: 0011 movs r1, r2
80005e4: 0018 movs r0, r3
80005e6: f7ff ff5d bl 80004a4 <__NVIC_SetPriority>
}
80005ea: 46c0 nop ; (mov r8, r8)
80005ec: 46bd mov sp, r7
80005ee: b004 add sp, #16
80005f0: bd80 pop {r7, pc}
080005f2 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80005f2: b580 push {r7, lr}
80005f4: b082 sub sp, #8
80005f6: af00 add r7, sp, #0
80005f8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80005fa: 687b ldr r3, [r7, #4]
80005fc: 0018 movs r0, r3
80005fe: f7ff ffbf bl 8000580 <SysTick_Config>
8000602: 0003 movs r3, r0
}
8000604: 0018 movs r0, r3
8000606: 46bd mov sp, r7
8000608: b002 add sp, #8
800060a: bd80 pop {r7, pc}
0800060c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800060c: b580 push {r7, lr}
800060e: b088 sub sp, #32
8000610: af00 add r7, sp, #0
8000612: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000614: 687b ldr r3, [r7, #4]
8000616: 2b00 cmp r3, #0
8000618: d101 bne.n 800061e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800061a: 2301 movs r3, #1
800061c: e301 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800061e: 687b ldr r3, [r7, #4]
8000620: 681b ldr r3, [r3, #0]
8000622: 2201 movs r2, #1
8000624: 4013 ands r3, r2
8000626: d100 bne.n 800062a <HAL_RCC_OscConfig+0x1e>
8000628: e08d b.n 8000746 <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
800062a: 4bc3 ldr r3, [pc, #780] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800062c: 685b ldr r3, [r3, #4]
800062e: 220c movs r2, #12
8000630: 4013 ands r3, r2
8000632: 2b04 cmp r3, #4
8000634: d00e beq.n 8000654 <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000636: 4bc0 ldr r3, [pc, #768] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000638: 685b ldr r3, [r3, #4]
800063a: 220c movs r2, #12
800063c: 4013 ands r3, r2
800063e: 2b08 cmp r3, #8
8000640: d116 bne.n 8000670 <HAL_RCC_OscConfig+0x64>
8000642: 4bbd ldr r3, [pc, #756] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000644: 685a ldr r2, [r3, #4]
8000646: 2380 movs r3, #128 ; 0x80
8000648: 025b lsls r3, r3, #9
800064a: 401a ands r2, r3
800064c: 2380 movs r3, #128 ; 0x80
800064e: 025b lsls r3, r3, #9
8000650: 429a cmp r2, r3
8000652: d10d bne.n 8000670 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000654: 4bb8 ldr r3, [pc, #736] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000656: 681a ldr r2, [r3, #0]
8000658: 2380 movs r3, #128 ; 0x80
800065a: 029b lsls r3, r3, #10
800065c: 4013 ands r3, r2
800065e: d100 bne.n 8000662 <HAL_RCC_OscConfig+0x56>
8000660: e070 b.n 8000744 <HAL_RCC_OscConfig+0x138>
8000662: 687b ldr r3, [r7, #4]
8000664: 685b ldr r3, [r3, #4]
8000666: 2b00 cmp r3, #0
8000668: d000 beq.n 800066c <HAL_RCC_OscConfig+0x60>
800066a: e06b b.n 8000744 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
800066c: 2301 movs r3, #1
800066e: e2d8 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000670: 687b ldr r3, [r7, #4]
8000672: 685b ldr r3, [r3, #4]
8000674: 2b01 cmp r3, #1
8000676: d107 bne.n 8000688 <HAL_RCC_OscConfig+0x7c>
8000678: 4baf ldr r3, [pc, #700] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800067a: 681a ldr r2, [r3, #0]
800067c: 4bae ldr r3, [pc, #696] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800067e: 2180 movs r1, #128 ; 0x80
8000680: 0249 lsls r1, r1, #9
8000682: 430a orrs r2, r1
8000684: 601a str r2, [r3, #0]
8000686: e02f b.n 80006e8 <HAL_RCC_OscConfig+0xdc>
8000688: 687b ldr r3, [r7, #4]
800068a: 685b ldr r3, [r3, #4]
800068c: 2b00 cmp r3, #0
800068e: d10c bne.n 80006aa <HAL_RCC_OscConfig+0x9e>
8000690: 4ba9 ldr r3, [pc, #676] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000692: 681a ldr r2, [r3, #0]
8000694: 4ba8 ldr r3, [pc, #672] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000696: 49a9 ldr r1, [pc, #676] ; (800093c <HAL_RCC_OscConfig+0x330>)
8000698: 400a ands r2, r1
800069a: 601a str r2, [r3, #0]
800069c: 4ba6 ldr r3, [pc, #664] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800069e: 681a ldr r2, [r3, #0]
80006a0: 4ba5 ldr r3, [pc, #660] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006a2: 49a7 ldr r1, [pc, #668] ; (8000940 <HAL_RCC_OscConfig+0x334>)
80006a4: 400a ands r2, r1
80006a6: 601a str r2, [r3, #0]
80006a8: e01e b.n 80006e8 <HAL_RCC_OscConfig+0xdc>
80006aa: 687b ldr r3, [r7, #4]
80006ac: 685b ldr r3, [r3, #4]
80006ae: 2b05 cmp r3, #5
80006b0: d10e bne.n 80006d0 <HAL_RCC_OscConfig+0xc4>
80006b2: 4ba1 ldr r3, [pc, #644] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006b4: 681a ldr r2, [r3, #0]
80006b6: 4ba0 ldr r3, [pc, #640] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006b8: 2180 movs r1, #128 ; 0x80
80006ba: 02c9 lsls r1, r1, #11
80006bc: 430a orrs r2, r1
80006be: 601a str r2, [r3, #0]
80006c0: 4b9d ldr r3, [pc, #628] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006c2: 681a ldr r2, [r3, #0]
80006c4: 4b9c ldr r3, [pc, #624] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006c6: 2180 movs r1, #128 ; 0x80
80006c8: 0249 lsls r1, r1, #9
80006ca: 430a orrs r2, r1
80006cc: 601a str r2, [r3, #0]
80006ce: e00b b.n 80006e8 <HAL_RCC_OscConfig+0xdc>
80006d0: 4b99 ldr r3, [pc, #612] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006d2: 681a ldr r2, [r3, #0]
80006d4: 4b98 ldr r3, [pc, #608] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006d6: 4999 ldr r1, [pc, #612] ; (800093c <HAL_RCC_OscConfig+0x330>)
80006d8: 400a ands r2, r1
80006da: 601a str r2, [r3, #0]
80006dc: 4b96 ldr r3, [pc, #600] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006de: 681a ldr r2, [r3, #0]
80006e0: 4b95 ldr r3, [pc, #596] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80006e2: 4997 ldr r1, [pc, #604] ; (8000940 <HAL_RCC_OscConfig+0x334>)
80006e4: 400a ands r2, r1
80006e6: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80006e8: 687b ldr r3, [r7, #4]
80006ea: 685b ldr r3, [r3, #4]
80006ec: 2b00 cmp r3, #0
80006ee: d014 beq.n 800071a <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80006f0: f7ff fece bl 8000490 <HAL_GetTick>
80006f4: 0003 movs r3, r0
80006f6: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80006f8: e008 b.n 800070c <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80006fa: f7ff fec9 bl 8000490 <HAL_GetTick>
80006fe: 0002 movs r2, r0
8000700: 69bb ldr r3, [r7, #24]
8000702: 1ad3 subs r3, r2, r3
8000704: 2b64 cmp r3, #100 ; 0x64
8000706: d901 bls.n 800070c <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
8000708: 2303 movs r3, #3
800070a: e28a b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800070c: 4b8a ldr r3, [pc, #552] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800070e: 681a ldr r2, [r3, #0]
8000710: 2380 movs r3, #128 ; 0x80
8000712: 029b lsls r3, r3, #10
8000714: 4013 ands r3, r2
8000716: d0f0 beq.n 80006fa <HAL_RCC_OscConfig+0xee>
8000718: e015 b.n 8000746 <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800071a: f7ff feb9 bl 8000490 <HAL_GetTick>
800071e: 0003 movs r3, r0
8000720: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000722: e008 b.n 8000736 <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000724: f7ff feb4 bl 8000490 <HAL_GetTick>
8000728: 0002 movs r2, r0
800072a: 69bb ldr r3, [r7, #24]
800072c: 1ad3 subs r3, r2, r3
800072e: 2b64 cmp r3, #100 ; 0x64
8000730: d901 bls.n 8000736 <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
8000732: 2303 movs r3, #3
8000734: e275 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000736: 4b80 ldr r3, [pc, #512] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000738: 681a ldr r2, [r3, #0]
800073a: 2380 movs r3, #128 ; 0x80
800073c: 029b lsls r3, r3, #10
800073e: 4013 ands r3, r2
8000740: d1f0 bne.n 8000724 <HAL_RCC_OscConfig+0x118>
8000742: e000 b.n 8000746 <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000744: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000746: 687b ldr r3, [r7, #4]
8000748: 681b ldr r3, [r3, #0]
800074a: 2202 movs r2, #2
800074c: 4013 ands r3, r2
800074e: d100 bne.n 8000752 <HAL_RCC_OscConfig+0x146>
8000750: e069 b.n 8000826 <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000752: 4b79 ldr r3, [pc, #484] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000754: 685b ldr r3, [r3, #4]
8000756: 220c movs r2, #12
8000758: 4013 ands r3, r2
800075a: d00b beq.n 8000774 <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
800075c: 4b76 ldr r3, [pc, #472] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800075e: 685b ldr r3, [r3, #4]
8000760: 220c movs r2, #12
8000762: 4013 ands r3, r2
8000764: 2b08 cmp r3, #8
8000766: d11c bne.n 80007a2 <HAL_RCC_OscConfig+0x196>
8000768: 4b73 ldr r3, [pc, #460] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800076a: 685a ldr r2, [r3, #4]
800076c: 2380 movs r3, #128 ; 0x80
800076e: 025b lsls r3, r3, #9
8000770: 4013 ands r3, r2
8000772: d116 bne.n 80007a2 <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000774: 4b70 ldr r3, [pc, #448] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000776: 681b ldr r3, [r3, #0]
8000778: 2202 movs r2, #2
800077a: 4013 ands r3, r2
800077c: d005 beq.n 800078a <HAL_RCC_OscConfig+0x17e>
800077e: 687b ldr r3, [r7, #4]
8000780: 68db ldr r3, [r3, #12]
8000782: 2b01 cmp r3, #1
8000784: d001 beq.n 800078a <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
8000786: 2301 movs r3, #1
8000788: e24b b.n 8000c22 <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800078a: 4b6b ldr r3, [pc, #428] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800078c: 681b ldr r3, [r3, #0]
800078e: 22f8 movs r2, #248 ; 0xf8
8000790: 4393 bics r3, r2
8000792: 0019 movs r1, r3
8000794: 687b ldr r3, [r7, #4]
8000796: 691b ldr r3, [r3, #16]
8000798: 00da lsls r2, r3, #3
800079a: 4b67 ldr r3, [pc, #412] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800079c: 430a orrs r2, r1
800079e: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80007a0: e041 b.n 8000826 <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80007a2: 687b ldr r3, [r7, #4]
80007a4: 68db ldr r3, [r3, #12]
80007a6: 2b00 cmp r3, #0
80007a8: d024 beq.n 80007f4 <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80007aa: 4b63 ldr r3, [pc, #396] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007ac: 681a ldr r2, [r3, #0]
80007ae: 4b62 ldr r3, [pc, #392] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007b0: 2101 movs r1, #1
80007b2: 430a orrs r2, r1
80007b4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80007b6: f7ff fe6b bl 8000490 <HAL_GetTick>
80007ba: 0003 movs r3, r0
80007bc: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80007be: e008 b.n 80007d2 <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80007c0: f7ff fe66 bl 8000490 <HAL_GetTick>
80007c4: 0002 movs r2, r0
80007c6: 69bb ldr r3, [r7, #24]
80007c8: 1ad3 subs r3, r2, r3
80007ca: 2b02 cmp r3, #2
80007cc: d901 bls.n 80007d2 <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
80007ce: 2303 movs r3, #3
80007d0: e227 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80007d2: 4b59 ldr r3, [pc, #356] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007d4: 681b ldr r3, [r3, #0]
80007d6: 2202 movs r2, #2
80007d8: 4013 ands r3, r2
80007da: d0f1 beq.n 80007c0 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80007dc: 4b56 ldr r3, [pc, #344] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007de: 681b ldr r3, [r3, #0]
80007e0: 22f8 movs r2, #248 ; 0xf8
80007e2: 4393 bics r3, r2
80007e4: 0019 movs r1, r3
80007e6: 687b ldr r3, [r7, #4]
80007e8: 691b ldr r3, [r3, #16]
80007ea: 00da lsls r2, r3, #3
80007ec: 4b52 ldr r3, [pc, #328] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007ee: 430a orrs r2, r1
80007f0: 601a str r2, [r3, #0]
80007f2: e018 b.n 8000826 <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80007f4: 4b50 ldr r3, [pc, #320] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007f6: 681a ldr r2, [r3, #0]
80007f8: 4b4f ldr r3, [pc, #316] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80007fa: 2101 movs r1, #1
80007fc: 438a bics r2, r1
80007fe: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000800: f7ff fe46 bl 8000490 <HAL_GetTick>
8000804: 0003 movs r3, r0
8000806: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000808: e008 b.n 800081c <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800080a: f7ff fe41 bl 8000490 <HAL_GetTick>
800080e: 0002 movs r2, r0
8000810: 69bb ldr r3, [r7, #24]
8000812: 1ad3 subs r3, r2, r3
8000814: 2b02 cmp r3, #2
8000816: d901 bls.n 800081c <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
8000818: 2303 movs r3, #3
800081a: e202 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800081c: 4b46 ldr r3, [pc, #280] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800081e: 681b ldr r3, [r3, #0]
8000820: 2202 movs r2, #2
8000822: 4013 ands r3, r2
8000824: d1f1 bne.n 800080a <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000826: 687b ldr r3, [r7, #4]
8000828: 681b ldr r3, [r3, #0]
800082a: 2208 movs r2, #8
800082c: 4013 ands r3, r2
800082e: d036 beq.n 800089e <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000830: 687b ldr r3, [r7, #4]
8000832: 69db ldr r3, [r3, #28]
8000834: 2b00 cmp r3, #0
8000836: d019 beq.n 800086c <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000838: 4b3f ldr r3, [pc, #252] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800083a: 6a5a ldr r2, [r3, #36] ; 0x24
800083c: 4b3e ldr r3, [pc, #248] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800083e: 2101 movs r1, #1
8000840: 430a orrs r2, r1
8000842: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000844: f7ff fe24 bl 8000490 <HAL_GetTick>
8000848: 0003 movs r3, r0
800084a: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800084c: e008 b.n 8000860 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800084e: f7ff fe1f bl 8000490 <HAL_GetTick>
8000852: 0002 movs r2, r0
8000854: 69bb ldr r3, [r7, #24]
8000856: 1ad3 subs r3, r2, r3
8000858: 2b02 cmp r3, #2
800085a: d901 bls.n 8000860 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
800085c: 2303 movs r3, #3
800085e: e1e0 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000860: 4b35 ldr r3, [pc, #212] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000862: 6a5b ldr r3, [r3, #36] ; 0x24
8000864: 2202 movs r2, #2
8000866: 4013 ands r3, r2
8000868: d0f1 beq.n 800084e <HAL_RCC_OscConfig+0x242>
800086a: e018 b.n 800089e <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800086c: 4b32 ldr r3, [pc, #200] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800086e: 6a5a ldr r2, [r3, #36] ; 0x24
8000870: 4b31 ldr r3, [pc, #196] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000872: 2101 movs r1, #1
8000874: 438a bics r2, r1
8000876: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000878: f7ff fe0a bl 8000490 <HAL_GetTick>
800087c: 0003 movs r3, r0
800087e: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000880: e008 b.n 8000894 <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000882: f7ff fe05 bl 8000490 <HAL_GetTick>
8000886: 0002 movs r2, r0
8000888: 69bb ldr r3, [r7, #24]
800088a: 1ad3 subs r3, r2, r3
800088c: 2b02 cmp r3, #2
800088e: d901 bls.n 8000894 <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
8000890: 2303 movs r3, #3
8000892: e1c6 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000894: 4b28 ldr r3, [pc, #160] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000896: 6a5b ldr r3, [r3, #36] ; 0x24
8000898: 2202 movs r2, #2
800089a: 4013 ands r3, r2
800089c: d1f1 bne.n 8000882 <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800089e: 687b ldr r3, [r7, #4]
80008a0: 681b ldr r3, [r3, #0]
80008a2: 2204 movs r2, #4
80008a4: 4013 ands r3, r2
80008a6: d100 bne.n 80008aa <HAL_RCC_OscConfig+0x29e>
80008a8: e0b4 b.n 8000a14 <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
80008aa: 201f movs r0, #31
80008ac: 183b adds r3, r7, r0
80008ae: 2200 movs r2, #0
80008b0: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80008b2: 4b21 ldr r3, [pc, #132] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80008b4: 69da ldr r2, [r3, #28]
80008b6: 2380 movs r3, #128 ; 0x80
80008b8: 055b lsls r3, r3, #21
80008ba: 4013 ands r3, r2
80008bc: d110 bne.n 80008e0 <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
80008be: 4b1e ldr r3, [pc, #120] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80008c0: 69da ldr r2, [r3, #28]
80008c2: 4b1d ldr r3, [pc, #116] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80008c4: 2180 movs r1, #128 ; 0x80
80008c6: 0549 lsls r1, r1, #21
80008c8: 430a orrs r2, r1
80008ca: 61da str r2, [r3, #28]
80008cc: 4b1a ldr r3, [pc, #104] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
80008ce: 69da ldr r2, [r3, #28]
80008d0: 2380 movs r3, #128 ; 0x80
80008d2: 055b lsls r3, r3, #21
80008d4: 4013 ands r3, r2
80008d6: 60fb str r3, [r7, #12]
80008d8: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
80008da: 183b adds r3, r7, r0
80008dc: 2201 movs r2, #1
80008de: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80008e0: 4b18 ldr r3, [pc, #96] ; (8000944 <HAL_RCC_OscConfig+0x338>)
80008e2: 681a ldr r2, [r3, #0]
80008e4: 2380 movs r3, #128 ; 0x80
80008e6: 005b lsls r3, r3, #1
80008e8: 4013 ands r3, r2
80008ea: d11a bne.n 8000922 <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80008ec: 4b15 ldr r3, [pc, #84] ; (8000944 <HAL_RCC_OscConfig+0x338>)
80008ee: 681a ldr r2, [r3, #0]
80008f0: 4b14 ldr r3, [pc, #80] ; (8000944 <HAL_RCC_OscConfig+0x338>)
80008f2: 2180 movs r1, #128 ; 0x80
80008f4: 0049 lsls r1, r1, #1
80008f6: 430a orrs r2, r1
80008f8: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80008fa: f7ff fdc9 bl 8000490 <HAL_GetTick>
80008fe: 0003 movs r3, r0
8000900: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000902: e008 b.n 8000916 <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000904: f7ff fdc4 bl 8000490 <HAL_GetTick>
8000908: 0002 movs r2, r0
800090a: 69bb ldr r3, [r7, #24]
800090c: 1ad3 subs r3, r2, r3
800090e: 2b64 cmp r3, #100 ; 0x64
8000910: d901 bls.n 8000916 <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8000912: 2303 movs r3, #3
8000914: e185 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000916: 4b0b ldr r3, [pc, #44] ; (8000944 <HAL_RCC_OscConfig+0x338>)
8000918: 681a ldr r2, [r3, #0]
800091a: 2380 movs r3, #128 ; 0x80
800091c: 005b lsls r3, r3, #1
800091e: 4013 ands r3, r2
8000920: d0f0 beq.n 8000904 <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000922: 687b ldr r3, [r7, #4]
8000924: 689b ldr r3, [r3, #8]
8000926: 2b01 cmp r3, #1
8000928: d10e bne.n 8000948 <HAL_RCC_OscConfig+0x33c>
800092a: 4b03 ldr r3, [pc, #12] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
800092c: 6a1a ldr r2, [r3, #32]
800092e: 4b02 ldr r3, [pc, #8] ; (8000938 <HAL_RCC_OscConfig+0x32c>)
8000930: 2101 movs r1, #1
8000932: 430a orrs r2, r1
8000934: 621a str r2, [r3, #32]
8000936: e035 b.n 80009a4 <HAL_RCC_OscConfig+0x398>
8000938: 40021000 .word 0x40021000
800093c: fffeffff .word 0xfffeffff
8000940: fffbffff .word 0xfffbffff
8000944: 40007000 .word 0x40007000
8000948: 687b ldr r3, [r7, #4]
800094a: 689b ldr r3, [r3, #8]
800094c: 2b00 cmp r3, #0
800094e: d10c bne.n 800096a <HAL_RCC_OscConfig+0x35e>
8000950: 4bb6 ldr r3, [pc, #728] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000952: 6a1a ldr r2, [r3, #32]
8000954: 4bb5 ldr r3, [pc, #724] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000956: 2101 movs r1, #1
8000958: 438a bics r2, r1
800095a: 621a str r2, [r3, #32]
800095c: 4bb3 ldr r3, [pc, #716] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
800095e: 6a1a ldr r2, [r3, #32]
8000960: 4bb2 ldr r3, [pc, #712] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000962: 2104 movs r1, #4
8000964: 438a bics r2, r1
8000966: 621a str r2, [r3, #32]
8000968: e01c b.n 80009a4 <HAL_RCC_OscConfig+0x398>
800096a: 687b ldr r3, [r7, #4]
800096c: 689b ldr r3, [r3, #8]
800096e: 2b05 cmp r3, #5
8000970: d10c bne.n 800098c <HAL_RCC_OscConfig+0x380>
8000972: 4bae ldr r3, [pc, #696] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000974: 6a1a ldr r2, [r3, #32]
8000976: 4bad ldr r3, [pc, #692] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000978: 2104 movs r1, #4
800097a: 430a orrs r2, r1
800097c: 621a str r2, [r3, #32]
800097e: 4bab ldr r3, [pc, #684] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000980: 6a1a ldr r2, [r3, #32]
8000982: 4baa ldr r3, [pc, #680] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000984: 2101 movs r1, #1
8000986: 430a orrs r2, r1
8000988: 621a str r2, [r3, #32]
800098a: e00b b.n 80009a4 <HAL_RCC_OscConfig+0x398>
800098c: 4ba7 ldr r3, [pc, #668] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
800098e: 6a1a ldr r2, [r3, #32]
8000990: 4ba6 ldr r3, [pc, #664] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000992: 2101 movs r1, #1
8000994: 438a bics r2, r1
8000996: 621a str r2, [r3, #32]
8000998: 4ba4 ldr r3, [pc, #656] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
800099a: 6a1a ldr r2, [r3, #32]
800099c: 4ba3 ldr r3, [pc, #652] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
800099e: 2104 movs r1, #4
80009a0: 438a bics r2, r1
80009a2: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80009a4: 687b ldr r3, [r7, #4]
80009a6: 689b ldr r3, [r3, #8]
80009a8: 2b00 cmp r3, #0
80009aa: d014 beq.n 80009d6 <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80009ac: f7ff fd70 bl 8000490 <HAL_GetTick>
80009b0: 0003 movs r3, r0
80009b2: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80009b4: e009 b.n 80009ca <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80009b6: f7ff fd6b bl 8000490 <HAL_GetTick>
80009ba: 0002 movs r2, r0
80009bc: 69bb ldr r3, [r7, #24]
80009be: 1ad3 subs r3, r2, r3
80009c0: 4a9b ldr r2, [pc, #620] ; (8000c30 <HAL_RCC_OscConfig+0x624>)
80009c2: 4293 cmp r3, r2
80009c4: d901 bls.n 80009ca <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
80009c6: 2303 movs r3, #3
80009c8: e12b b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80009ca: 4b98 ldr r3, [pc, #608] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
80009cc: 6a1b ldr r3, [r3, #32]
80009ce: 2202 movs r2, #2
80009d0: 4013 ands r3, r2
80009d2: d0f0 beq.n 80009b6 <HAL_RCC_OscConfig+0x3aa>
80009d4: e013 b.n 80009fe <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80009d6: f7ff fd5b bl 8000490 <HAL_GetTick>
80009da: 0003 movs r3, r0
80009dc: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80009de: e009 b.n 80009f4 <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80009e0: f7ff fd56 bl 8000490 <HAL_GetTick>
80009e4: 0002 movs r2, r0
80009e6: 69bb ldr r3, [r7, #24]
80009e8: 1ad3 subs r3, r2, r3
80009ea: 4a91 ldr r2, [pc, #580] ; (8000c30 <HAL_RCC_OscConfig+0x624>)
80009ec: 4293 cmp r3, r2
80009ee: d901 bls.n 80009f4 <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
80009f0: 2303 movs r3, #3
80009f2: e116 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80009f4: 4b8d ldr r3, [pc, #564] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
80009f6: 6a1b ldr r3, [r3, #32]
80009f8: 2202 movs r2, #2
80009fa: 4013 ands r3, r2
80009fc: d1f0 bne.n 80009e0 <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80009fe: 231f movs r3, #31
8000a00: 18fb adds r3, r7, r3
8000a02: 781b ldrb r3, [r3, #0]
8000a04: 2b01 cmp r3, #1
8000a06: d105 bne.n 8000a14 <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000a08: 4b88 ldr r3, [pc, #544] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a0a: 69da ldr r2, [r3, #28]
8000a0c: 4b87 ldr r3, [pc, #540] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a0e: 4989 ldr r1, [pc, #548] ; (8000c34 <HAL_RCC_OscConfig+0x628>)
8000a10: 400a ands r2, r1
8000a12: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8000a14: 687b ldr r3, [r7, #4]
8000a16: 681b ldr r3, [r3, #0]
8000a18: 2210 movs r2, #16
8000a1a: 4013 ands r3, r2
8000a1c: d063 beq.n 8000ae6 <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8000a1e: 687b ldr r3, [r7, #4]
8000a20: 695b ldr r3, [r3, #20]
8000a22: 2b01 cmp r3, #1
8000a24: d12a bne.n 8000a7c <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000a26: 4b81 ldr r3, [pc, #516] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a28: 6b5a ldr r2, [r3, #52] ; 0x34
8000a2a: 4b80 ldr r3, [pc, #512] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a2c: 2104 movs r1, #4
8000a2e: 430a orrs r2, r1
8000a30: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8000a32: 4b7e ldr r3, [pc, #504] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a34: 6b5a ldr r2, [r3, #52] ; 0x34
8000a36: 4b7d ldr r3, [pc, #500] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a38: 2101 movs r1, #1
8000a3a: 430a orrs r2, r1
8000a3c: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a3e: f7ff fd27 bl 8000490 <HAL_GetTick>
8000a42: 0003 movs r3, r0
8000a44: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000a46: e008 b.n 8000a5a <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000a48: f7ff fd22 bl 8000490 <HAL_GetTick>
8000a4c: 0002 movs r2, r0
8000a4e: 69bb ldr r3, [r7, #24]
8000a50: 1ad3 subs r3, r2, r3
8000a52: 2b02 cmp r3, #2
8000a54: d901 bls.n 8000a5a <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
8000a56: 2303 movs r3, #3
8000a58: e0e3 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000a5a: 4b74 ldr r3, [pc, #464] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a5c: 6b5b ldr r3, [r3, #52] ; 0x34
8000a5e: 2202 movs r2, #2
8000a60: 4013 ands r3, r2
8000a62: d0f1 beq.n 8000a48 <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8000a64: 4b71 ldr r3, [pc, #452] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a66: 6b5b ldr r3, [r3, #52] ; 0x34
8000a68: 22f8 movs r2, #248 ; 0xf8
8000a6a: 4393 bics r3, r2
8000a6c: 0019 movs r1, r3
8000a6e: 687b ldr r3, [r7, #4]
8000a70: 699b ldr r3, [r3, #24]
8000a72: 00da lsls r2, r3, #3
8000a74: 4b6d ldr r3, [pc, #436] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a76: 430a orrs r2, r1
8000a78: 635a str r2, [r3, #52] ; 0x34
8000a7a: e034 b.n 8000ae6 <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8000a7c: 687b ldr r3, [r7, #4]
8000a7e: 695b ldr r3, [r3, #20]
8000a80: 3305 adds r3, #5
8000a82: d111 bne.n 8000aa8 <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
8000a84: 4b69 ldr r3, [pc, #420] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a86: 6b5a ldr r2, [r3, #52] ; 0x34
8000a88: 4b68 ldr r3, [pc, #416] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a8a: 2104 movs r1, #4
8000a8c: 438a bics r2, r1
8000a8e: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8000a90: 4b66 ldr r3, [pc, #408] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000a92: 6b5b ldr r3, [r3, #52] ; 0x34
8000a94: 22f8 movs r2, #248 ; 0xf8
8000a96: 4393 bics r3, r2
8000a98: 0019 movs r1, r3
8000a9a: 687b ldr r3, [r7, #4]
8000a9c: 699b ldr r3, [r3, #24]
8000a9e: 00da lsls r2, r3, #3
8000aa0: 4b62 ldr r3, [pc, #392] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000aa2: 430a orrs r2, r1
8000aa4: 635a str r2, [r3, #52] ; 0x34
8000aa6: e01e b.n 8000ae6 <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000aa8: 4b60 ldr r3, [pc, #384] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000aaa: 6b5a ldr r2, [r3, #52] ; 0x34
8000aac: 4b5f ldr r3, [pc, #380] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000aae: 2104 movs r1, #4
8000ab0: 430a orrs r2, r1
8000ab2: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8000ab4: 4b5d ldr r3, [pc, #372] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000ab6: 6b5a ldr r2, [r3, #52] ; 0x34
8000ab8: 4b5c ldr r3, [pc, #368] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000aba: 2101 movs r1, #1
8000abc: 438a bics r2, r1
8000abe: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ac0: f7ff fce6 bl 8000490 <HAL_GetTick>
8000ac4: 0003 movs r3, r0
8000ac6: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8000ac8: e008 b.n 8000adc <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000aca: f7ff fce1 bl 8000490 <HAL_GetTick>
8000ace: 0002 movs r2, r0
8000ad0: 69bb ldr r3, [r7, #24]
8000ad2: 1ad3 subs r3, r2, r3
8000ad4: 2b02 cmp r3, #2
8000ad6: d901 bls.n 8000adc <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
8000ad8: 2303 movs r3, #3
8000ada: e0a2 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8000adc: 4b53 ldr r3, [pc, #332] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000ade: 6b5b ldr r3, [r3, #52] ; 0x34
8000ae0: 2202 movs r2, #2
8000ae2: 4013 ands r3, r2
8000ae4: d1f1 bne.n 8000aca <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000ae6: 687b ldr r3, [r7, #4]
8000ae8: 6a1b ldr r3, [r3, #32]
8000aea: 2b00 cmp r3, #0
8000aec: d100 bne.n 8000af0 <HAL_RCC_OscConfig+0x4e4>
8000aee: e097 b.n 8000c20 <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000af0: 4b4e ldr r3, [pc, #312] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000af2: 685b ldr r3, [r3, #4]
8000af4: 220c movs r2, #12
8000af6: 4013 ands r3, r2
8000af8: 2b08 cmp r3, #8
8000afa: d100 bne.n 8000afe <HAL_RCC_OscConfig+0x4f2>
8000afc: e06b b.n 8000bd6 <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000afe: 687b ldr r3, [r7, #4]
8000b00: 6a1b ldr r3, [r3, #32]
8000b02: 2b02 cmp r3, #2
8000b04: d14c bne.n 8000ba0 <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000b06: 4b49 ldr r3, [pc, #292] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b08: 681a ldr r2, [r3, #0]
8000b0a: 4b48 ldr r3, [pc, #288] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b0c: 494a ldr r1, [pc, #296] ; (8000c38 <HAL_RCC_OscConfig+0x62c>)
8000b0e: 400a ands r2, r1
8000b10: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000b12: f7ff fcbd bl 8000490 <HAL_GetTick>
8000b16: 0003 movs r3, r0
8000b18: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000b1a: e008 b.n 8000b2e <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000b1c: f7ff fcb8 bl 8000490 <HAL_GetTick>
8000b20: 0002 movs r2, r0
8000b22: 69bb ldr r3, [r7, #24]
8000b24: 1ad3 subs r3, r2, r3
8000b26: 2b02 cmp r3, #2
8000b28: d901 bls.n 8000b2e <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
8000b2a: 2303 movs r3, #3
8000b2c: e079 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000b2e: 4b3f ldr r3, [pc, #252] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b30: 681a ldr r2, [r3, #0]
8000b32: 2380 movs r3, #128 ; 0x80
8000b34: 049b lsls r3, r3, #18
8000b36: 4013 ands r3, r2
8000b38: d1f0 bne.n 8000b1c <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000b3a: 4b3c ldr r3, [pc, #240] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b3c: 6adb ldr r3, [r3, #44] ; 0x2c
8000b3e: 220f movs r2, #15
8000b40: 4393 bics r3, r2
8000b42: 0019 movs r1, r3
8000b44: 687b ldr r3, [r7, #4]
8000b46: 6ada ldr r2, [r3, #44] ; 0x2c
8000b48: 4b38 ldr r3, [pc, #224] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b4a: 430a orrs r2, r1
8000b4c: 62da str r2, [r3, #44] ; 0x2c
8000b4e: 4b37 ldr r3, [pc, #220] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b50: 685b ldr r3, [r3, #4]
8000b52: 4a3a ldr r2, [pc, #232] ; (8000c3c <HAL_RCC_OscConfig+0x630>)
8000b54: 4013 ands r3, r2
8000b56: 0019 movs r1, r3
8000b58: 687b ldr r3, [r7, #4]
8000b5a: 6a9a ldr r2, [r3, #40] ; 0x28
8000b5c: 687b ldr r3, [r7, #4]
8000b5e: 6a5b ldr r3, [r3, #36] ; 0x24
8000b60: 431a orrs r2, r3
8000b62: 4b32 ldr r3, [pc, #200] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b64: 430a orrs r2, r1
8000b66: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8000b68: 4b30 ldr r3, [pc, #192] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b6a: 681a ldr r2, [r3, #0]
8000b6c: 4b2f ldr r3, [pc, #188] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b6e: 2180 movs r1, #128 ; 0x80
8000b70: 0449 lsls r1, r1, #17
8000b72: 430a orrs r2, r1
8000b74: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000b76: f7ff fc8b bl 8000490 <HAL_GetTick>
8000b7a: 0003 movs r3, r0
8000b7c: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000b7e: e008 b.n 8000b92 <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000b80: f7ff fc86 bl 8000490 <HAL_GetTick>
8000b84: 0002 movs r2, r0
8000b86: 69bb ldr r3, [r7, #24]
8000b88: 1ad3 subs r3, r2, r3
8000b8a: 2b02 cmp r3, #2
8000b8c: d901 bls.n 8000b92 <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8000b8e: 2303 movs r3, #3
8000b90: e047 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000b92: 4b26 ldr r3, [pc, #152] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000b94: 681a ldr r2, [r3, #0]
8000b96: 2380 movs r3, #128 ; 0x80
8000b98: 049b lsls r3, r3, #18
8000b9a: 4013 ands r3, r2
8000b9c: d0f0 beq.n 8000b80 <HAL_RCC_OscConfig+0x574>
8000b9e: e03f b.n 8000c20 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000ba0: 4b22 ldr r3, [pc, #136] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000ba2: 681a ldr r2, [r3, #0]
8000ba4: 4b21 ldr r3, [pc, #132] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000ba6: 4924 ldr r1, [pc, #144] ; (8000c38 <HAL_RCC_OscConfig+0x62c>)
8000ba8: 400a ands r2, r1
8000baa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000bac: f7ff fc70 bl 8000490 <HAL_GetTick>
8000bb0: 0003 movs r3, r0
8000bb2: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000bb4: e008 b.n 8000bc8 <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000bb6: f7ff fc6b bl 8000490 <HAL_GetTick>
8000bba: 0002 movs r2, r0
8000bbc: 69bb ldr r3, [r7, #24]
8000bbe: 1ad3 subs r3, r2, r3
8000bc0: 2b02 cmp r3, #2
8000bc2: d901 bls.n 8000bc8 <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
8000bc4: 2303 movs r3, #3
8000bc6: e02c b.n 8000c22 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000bc8: 4b18 ldr r3, [pc, #96] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000bca: 681a ldr r2, [r3, #0]
8000bcc: 2380 movs r3, #128 ; 0x80
8000bce: 049b lsls r3, r3, #18
8000bd0: 4013 ands r3, r2
8000bd2: d1f0 bne.n 8000bb6 <HAL_RCC_OscConfig+0x5aa>
8000bd4: e024 b.n 8000c20 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8000bd6: 687b ldr r3, [r7, #4]
8000bd8: 6a1b ldr r3, [r3, #32]
8000bda: 2b01 cmp r3, #1
8000bdc: d101 bne.n 8000be2 <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
8000bde: 2301 movs r3, #1
8000be0: e01f b.n 8000c22 <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8000be2: 4b12 ldr r3, [pc, #72] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000be4: 685b ldr r3, [r3, #4]
8000be6: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8000be8: 4b10 ldr r3, [pc, #64] ; (8000c2c <HAL_RCC_OscConfig+0x620>)
8000bea: 6adb ldr r3, [r3, #44] ; 0x2c
8000bec: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000bee: 697a ldr r2, [r7, #20]
8000bf0: 2380 movs r3, #128 ; 0x80
8000bf2: 025b lsls r3, r3, #9
8000bf4: 401a ands r2, r3
8000bf6: 687b ldr r3, [r7, #4]
8000bf8: 6a5b ldr r3, [r3, #36] ; 0x24
8000bfa: 429a cmp r2, r3
8000bfc: d10e bne.n 8000c1c <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8000bfe: 693b ldr r3, [r7, #16]
8000c00: 220f movs r2, #15
8000c02: 401a ands r2, r3
8000c04: 687b ldr r3, [r7, #4]
8000c06: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000c08: 429a cmp r2, r3
8000c0a: d107 bne.n 8000c1c <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8000c0c: 697a ldr r2, [r7, #20]
8000c0e: 23f0 movs r3, #240 ; 0xf0
8000c10: 039b lsls r3, r3, #14
8000c12: 401a ands r2, r3
8000c14: 687b ldr r3, [r7, #4]
8000c16: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8000c18: 429a cmp r2, r3
8000c1a: d001 beq.n 8000c20 <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
8000c1c: 2301 movs r3, #1
8000c1e: e000 b.n 8000c22 <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
8000c20: 2300 movs r3, #0
}
8000c22: 0018 movs r0, r3
8000c24: 46bd mov sp, r7
8000c26: b008 add sp, #32
8000c28: bd80 pop {r7, pc}
8000c2a: 46c0 nop ; (mov r8, r8)
8000c2c: 40021000 .word 0x40021000
8000c30: 00001388 .word 0x00001388
8000c34: efffffff .word 0xefffffff
8000c38: feffffff .word 0xfeffffff
8000c3c: ffc2ffff .word 0xffc2ffff
08000c40 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8000c40: b580 push {r7, lr}
8000c42: b084 sub sp, #16
8000c44: af00 add r7, sp, #0
8000c46: 6078 str r0, [r7, #4]
8000c48: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8000c4a: 687b ldr r3, [r7, #4]
8000c4c: 2b00 cmp r3, #0
8000c4e: d101 bne.n 8000c54 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8000c50: 2301 movs r3, #1
8000c52: e0b3 b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8000c54: 4b5b ldr r3, [pc, #364] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000c56: 681b ldr r3, [r3, #0]
8000c58: 2201 movs r2, #1
8000c5a: 4013 ands r3, r2
8000c5c: 683a ldr r2, [r7, #0]
8000c5e: 429a cmp r2, r3
8000c60: d911 bls.n 8000c86 <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000c62: 4b58 ldr r3, [pc, #352] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000c64: 681b ldr r3, [r3, #0]
8000c66: 2201 movs r2, #1
8000c68: 4393 bics r3, r2
8000c6a: 0019 movs r1, r3
8000c6c: 4b55 ldr r3, [pc, #340] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000c6e: 683a ldr r2, [r7, #0]
8000c70: 430a orrs r2, r1
8000c72: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8000c74: 4b53 ldr r3, [pc, #332] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000c76: 681b ldr r3, [r3, #0]
8000c78: 2201 movs r2, #1
8000c7a: 4013 ands r3, r2
8000c7c: 683a ldr r2, [r7, #0]
8000c7e: 429a cmp r2, r3
8000c80: d001 beq.n 8000c86 <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
8000c82: 2301 movs r3, #1
8000c84: e09a b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8000c86: 687b ldr r3, [r7, #4]
8000c88: 681b ldr r3, [r3, #0]
8000c8a: 2202 movs r2, #2
8000c8c: 4013 ands r3, r2
8000c8e: d015 beq.n 8000cbc <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000c90: 687b ldr r3, [r7, #4]
8000c92: 681b ldr r3, [r3, #0]
8000c94: 2204 movs r2, #4
8000c96: 4013 ands r3, r2
8000c98: d006 beq.n 8000ca8 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8000c9a: 4b4b ldr r3, [pc, #300] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000c9c: 685a ldr r2, [r3, #4]
8000c9e: 4b4a ldr r3, [pc, #296] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000ca0: 21e0 movs r1, #224 ; 0xe0
8000ca2: 00c9 lsls r1, r1, #3
8000ca4: 430a orrs r2, r1
8000ca6: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8000ca8: 4b47 ldr r3, [pc, #284] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000caa: 685b ldr r3, [r3, #4]
8000cac: 22f0 movs r2, #240 ; 0xf0
8000cae: 4393 bics r3, r2
8000cb0: 0019 movs r1, r3
8000cb2: 687b ldr r3, [r7, #4]
8000cb4: 689a ldr r2, [r3, #8]
8000cb6: 4b44 ldr r3, [pc, #272] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000cb8: 430a orrs r2, r1
8000cba: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8000cbc: 687b ldr r3, [r7, #4]
8000cbe: 681b ldr r3, [r3, #0]
8000cc0: 2201 movs r2, #1
8000cc2: 4013 ands r3, r2
8000cc4: d040 beq.n 8000d48 <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8000cc6: 687b ldr r3, [r7, #4]
8000cc8: 685b ldr r3, [r3, #4]
8000cca: 2b01 cmp r3, #1
8000ccc: d107 bne.n 8000cde <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000cce: 4b3e ldr r3, [pc, #248] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000cd0: 681a ldr r2, [r3, #0]
8000cd2: 2380 movs r3, #128 ; 0x80
8000cd4: 029b lsls r3, r3, #10
8000cd6: 4013 ands r3, r2
8000cd8: d114 bne.n 8000d04 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8000cda: 2301 movs r3, #1
8000cdc: e06e b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8000cde: 687b ldr r3, [r7, #4]
8000ce0: 685b ldr r3, [r3, #4]
8000ce2: 2b02 cmp r3, #2
8000ce4: d107 bne.n 8000cf6 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000ce6: 4b38 ldr r3, [pc, #224] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000ce8: 681a ldr r2, [r3, #0]
8000cea: 2380 movs r3, #128 ; 0x80
8000cec: 049b lsls r3, r3, #18
8000cee: 4013 ands r3, r2
8000cf0: d108 bne.n 8000d04 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8000cf2: 2301 movs r3, #1
8000cf4: e062 b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000cf6: 4b34 ldr r3, [pc, #208] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000cf8: 681b ldr r3, [r3, #0]
8000cfa: 2202 movs r2, #2
8000cfc: 4013 ands r3, r2
8000cfe: d101 bne.n 8000d04 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8000d00: 2301 movs r3, #1
8000d02: e05b b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8000d04: 4b30 ldr r3, [pc, #192] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000d06: 685b ldr r3, [r3, #4]
8000d08: 2203 movs r2, #3
8000d0a: 4393 bics r3, r2
8000d0c: 0019 movs r1, r3
8000d0e: 687b ldr r3, [r7, #4]
8000d10: 685a ldr r2, [r3, #4]
8000d12: 4b2d ldr r3, [pc, #180] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000d14: 430a orrs r2, r1
8000d16: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d18: f7ff fbba bl 8000490 <HAL_GetTick>
8000d1c: 0003 movs r3, r0
8000d1e: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8000d20: e009 b.n 8000d36 <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8000d22: f7ff fbb5 bl 8000490 <HAL_GetTick>
8000d26: 0002 movs r2, r0
8000d28: 68fb ldr r3, [r7, #12]
8000d2a: 1ad3 subs r3, r2, r3
8000d2c: 4a27 ldr r2, [pc, #156] ; (8000dcc <HAL_RCC_ClockConfig+0x18c>)
8000d2e: 4293 cmp r3, r2
8000d30: d901 bls.n 8000d36 <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
8000d32: 2303 movs r3, #3
8000d34: e042 b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8000d36: 4b24 ldr r3, [pc, #144] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000d38: 685b ldr r3, [r3, #4]
8000d3a: 220c movs r2, #12
8000d3c: 401a ands r2, r3
8000d3e: 687b ldr r3, [r7, #4]
8000d40: 685b ldr r3, [r3, #4]
8000d42: 009b lsls r3, r3, #2
8000d44: 429a cmp r2, r3
8000d46: d1ec bne.n 8000d22 <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8000d48: 4b1e ldr r3, [pc, #120] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000d4a: 681b ldr r3, [r3, #0]
8000d4c: 2201 movs r2, #1
8000d4e: 4013 ands r3, r2
8000d50: 683a ldr r2, [r7, #0]
8000d52: 429a cmp r2, r3
8000d54: d211 bcs.n 8000d7a <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000d56: 4b1b ldr r3, [pc, #108] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000d58: 681b ldr r3, [r3, #0]
8000d5a: 2201 movs r2, #1
8000d5c: 4393 bics r3, r2
8000d5e: 0019 movs r1, r3
8000d60: 4b18 ldr r3, [pc, #96] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000d62: 683a ldr r2, [r7, #0]
8000d64: 430a orrs r2, r1
8000d66: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8000d68: 4b16 ldr r3, [pc, #88] ; (8000dc4 <HAL_RCC_ClockConfig+0x184>)
8000d6a: 681b ldr r3, [r3, #0]
8000d6c: 2201 movs r2, #1
8000d6e: 4013 ands r3, r2
8000d70: 683a ldr r2, [r7, #0]
8000d72: 429a cmp r2, r3
8000d74: d001 beq.n 8000d7a <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
8000d76: 2301 movs r3, #1
8000d78: e020 b.n 8000dbc <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000d7a: 687b ldr r3, [r7, #4]
8000d7c: 681b ldr r3, [r3, #0]
8000d7e: 2204 movs r2, #4
8000d80: 4013 ands r3, r2
8000d82: d009 beq.n 8000d98 <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8000d84: 4b10 ldr r3, [pc, #64] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000d86: 685b ldr r3, [r3, #4]
8000d88: 4a11 ldr r2, [pc, #68] ; (8000dd0 <HAL_RCC_ClockConfig+0x190>)
8000d8a: 4013 ands r3, r2
8000d8c: 0019 movs r1, r3
8000d8e: 687b ldr r3, [r7, #4]
8000d90: 68da ldr r2, [r3, #12]
8000d92: 4b0d ldr r3, [pc, #52] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000d94: 430a orrs r2, r1
8000d96: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8000d98: f000 f820 bl 8000ddc <HAL_RCC_GetSysClockFreq>
8000d9c: 0001 movs r1, r0
8000d9e: 4b0a ldr r3, [pc, #40] ; (8000dc8 <HAL_RCC_ClockConfig+0x188>)
8000da0: 685b ldr r3, [r3, #4]
8000da2: 091b lsrs r3, r3, #4
8000da4: 220f movs r2, #15
8000da6: 4013 ands r3, r2
8000da8: 4a0a ldr r2, [pc, #40] ; (8000dd4 <HAL_RCC_ClockConfig+0x194>)
8000daa: 5cd3 ldrb r3, [r2, r3]
8000dac: 000a movs r2, r1
8000dae: 40da lsrs r2, r3
8000db0: 4b09 ldr r3, [pc, #36] ; (8000dd8 <HAL_RCC_ClockConfig+0x198>)
8000db2: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
8000db4: 2003 movs r0, #3
8000db6: f7ff fb25 bl 8000404 <HAL_InitTick>
return HAL_OK;
8000dba: 2300 movs r3, #0
}
8000dbc: 0018 movs r0, r3
8000dbe: 46bd mov sp, r7
8000dc0: b004 add sp, #16
8000dc2: bd80 pop {r7, pc}
8000dc4: 40022000 .word 0x40022000
8000dc8: 40021000 .word 0x40021000
8000dcc: 00001388 .word 0x00001388
8000dd0: fffff8ff .word 0xfffff8ff
8000dd4: 08000f3c .word 0x08000f3c
8000dd8: 20000000 .word 0x20000000
08000ddc <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8000ddc: b590 push {r4, r7, lr}
8000dde: b08f sub sp, #60 ; 0x3c
8000de0: af00 add r7, sp, #0
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
8000de2: 2314 movs r3, #20
8000de4: 18fb adds r3, r7, r3
8000de6: 4a2b ldr r2, [pc, #172] ; (8000e94 <HAL_RCC_GetSysClockFreq+0xb8>)
8000de8: ca13 ldmia r2!, {r0, r1, r4}
8000dea: c313 stmia r3!, {r0, r1, r4}
8000dec: 6812 ldr r2, [r2, #0]
8000dee: 601a str r2, [r3, #0]
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
8000df0: 1d3b adds r3, r7, #4
8000df2: 4a29 ldr r2, [pc, #164] ; (8000e98 <HAL_RCC_GetSysClockFreq+0xbc>)
8000df4: ca13 ldmia r2!, {r0, r1, r4}
8000df6: c313 stmia r3!, {r0, r1, r4}
8000df8: 6812 ldr r2, [r2, #0]
8000dfa: 601a str r2, [r3, #0]
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8000dfc: 2300 movs r3, #0
8000dfe: 62fb str r3, [r7, #44] ; 0x2c
8000e00: 2300 movs r3, #0
8000e02: 62bb str r3, [r7, #40] ; 0x28
8000e04: 2300 movs r3, #0
8000e06: 637b str r3, [r7, #52] ; 0x34
8000e08: 2300 movs r3, #0
8000e0a: 627b str r3, [r7, #36] ; 0x24
uint32_t sysclockfreq = 0U;
8000e0c: 2300 movs r3, #0
8000e0e: 633b str r3, [r7, #48] ; 0x30
tmpreg = RCC->CFGR;
8000e10: 4b22 ldr r3, [pc, #136] ; (8000e9c <HAL_RCC_GetSysClockFreq+0xc0>)
8000e12: 685b ldr r3, [r3, #4]
8000e14: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8000e16: 6afb ldr r3, [r7, #44] ; 0x2c
8000e18: 220c movs r2, #12
8000e1a: 4013 ands r3, r2
8000e1c: 2b04 cmp r3, #4
8000e1e: d002 beq.n 8000e26 <HAL_RCC_GetSysClockFreq+0x4a>
8000e20: 2b08 cmp r3, #8
8000e22: d003 beq.n 8000e2c <HAL_RCC_GetSysClockFreq+0x50>
8000e24: e02d b.n 8000e82 <HAL_RCC_GetSysClockFreq+0xa6>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8000e26: 4b1e ldr r3, [pc, #120] ; (8000ea0 <HAL_RCC_GetSysClockFreq+0xc4>)
8000e28: 633b str r3, [r7, #48] ; 0x30
break;
8000e2a: e02d b.n 8000e88 <HAL_RCC_GetSysClockFreq+0xac>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
8000e2c: 6afb ldr r3, [r7, #44] ; 0x2c
8000e2e: 0c9b lsrs r3, r3, #18
8000e30: 220f movs r2, #15
8000e32: 4013 ands r3, r2
8000e34: 2214 movs r2, #20
8000e36: 18ba adds r2, r7, r2
8000e38: 5cd3 ldrb r3, [r2, r3]
8000e3a: 627b str r3, [r7, #36] ; 0x24
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
8000e3c: 4b17 ldr r3, [pc, #92] ; (8000e9c <HAL_RCC_GetSysClockFreq+0xc0>)
8000e3e: 6adb ldr r3, [r3, #44] ; 0x2c
8000e40: 220f movs r2, #15
8000e42: 4013 ands r3, r2
8000e44: 1d3a adds r2, r7, #4
8000e46: 5cd3 ldrb r3, [r2, r3]
8000e48: 62bb str r3, [r7, #40] ; 0x28
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
8000e4a: 6afa ldr r2, [r7, #44] ; 0x2c
8000e4c: 2380 movs r3, #128 ; 0x80
8000e4e: 025b lsls r3, r3, #9
8000e50: 4013 ands r3, r2
8000e52: d009 beq.n 8000e68 <HAL_RCC_GetSysClockFreq+0x8c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8000e54: 6ab9 ldr r1, [r7, #40] ; 0x28
8000e56: 4812 ldr r0, [pc, #72] ; (8000ea0 <HAL_RCC_GetSysClockFreq+0xc4>)
8000e58: f7ff f956 bl 8000108 <__udivsi3>
8000e5c: 0003 movs r3, r0
8000e5e: 001a movs r2, r3
8000e60: 6a7b ldr r3, [r7, #36] ; 0x24
8000e62: 4353 muls r3, r2
8000e64: 637b str r3, [r7, #52] ; 0x34
8000e66: e009 b.n 8000e7c <HAL_RCC_GetSysClockFreq+0xa0>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8000e68: 6a79 ldr r1, [r7, #36] ; 0x24
8000e6a: 000a movs r2, r1
8000e6c: 0152 lsls r2, r2, #5
8000e6e: 1a52 subs r2, r2, r1
8000e70: 0193 lsls r3, r2, #6
8000e72: 1a9b subs r3, r3, r2
8000e74: 00db lsls r3, r3, #3
8000e76: 185b adds r3, r3, r1
8000e78: 021b lsls r3, r3, #8
8000e7a: 637b str r3, [r7, #52] ; 0x34
#endif
}
sysclockfreq = pllclk;
8000e7c: 6b7b ldr r3, [r7, #52] ; 0x34
8000e7e: 633b str r3, [r7, #48] ; 0x30
break;
8000e80: e002 b.n 8000e88 <HAL_RCC_GetSysClockFreq+0xac>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8000e82: 4b07 ldr r3, [pc, #28] ; (8000ea0 <HAL_RCC_GetSysClockFreq+0xc4>)
8000e84: 633b str r3, [r7, #48] ; 0x30
break;
8000e86: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
8000e88: 6b3b ldr r3, [r7, #48] ; 0x30
}
8000e8a: 0018 movs r0, r3
8000e8c: 46bd mov sp, r7
8000e8e: b00f add sp, #60 ; 0x3c
8000e90: bd90 pop {r4, r7, pc}
8000e92: 46c0 nop ; (mov r8, r8)
8000e94: 08000f1c .word 0x08000f1c
8000e98: 08000f2c .word 0x08000f2c
8000e9c: 40021000 .word 0x40021000
8000ea0: 007a1200 .word 0x007a1200
08000ea4 <mymain>:
* Author: wuwenfeng
*/
#include "my_main.h"
void mymain()
{
8000ea4: b580 push {r7, lr}
8000ea6: af00 add r7, sp, #0
while(1)
8000ea8: e7fe b.n 8000ea8 <mymain+0x4>
...
08000eac <__libc_init_array>:
8000eac: b570 push {r4, r5, r6, lr}
8000eae: 2600 movs r6, #0
8000eb0: 4d0c ldr r5, [pc, #48] ; (8000ee4 <__libc_init_array+0x38>)
8000eb2: 4c0d ldr r4, [pc, #52] ; (8000ee8 <__libc_init_array+0x3c>)
8000eb4: 1b64 subs r4, r4, r5
8000eb6: 10a4 asrs r4, r4, #2
8000eb8: 42a6 cmp r6, r4
8000eba: d109 bne.n 8000ed0 <__libc_init_array+0x24>
8000ebc: 2600 movs r6, #0
8000ebe: f000 f821 bl 8000f04 <_init>
8000ec2: 4d0a ldr r5, [pc, #40] ; (8000eec <__libc_init_array+0x40>)
8000ec4: 4c0a ldr r4, [pc, #40] ; (8000ef0 <__libc_init_array+0x44>)
8000ec6: 1b64 subs r4, r4, r5
8000ec8: 10a4 asrs r4, r4, #2
8000eca: 42a6 cmp r6, r4
8000ecc: d105 bne.n 8000eda <__libc_init_array+0x2e>
8000ece: bd70 pop {r4, r5, r6, pc}
8000ed0: 00b3 lsls r3, r6, #2
8000ed2: 58eb ldr r3, [r5, r3]
8000ed4: 4798 blx r3
8000ed6: 3601 adds r6, #1
8000ed8: e7ee b.n 8000eb8 <__libc_init_array+0xc>
8000eda: 00b3 lsls r3, r6, #2
8000edc: 58eb ldr r3, [r5, r3]
8000ede: 4798 blx r3
8000ee0: 3601 adds r6, #1
8000ee2: e7f2 b.n 8000eca <__libc_init_array+0x1e>
8000ee4: 08000f4c .word 0x08000f4c
8000ee8: 08000f4c .word 0x08000f4c
8000eec: 08000f4c .word 0x08000f4c
8000ef0: 08000f50 .word 0x08000f50
08000ef4 <memset>:
8000ef4: 0003 movs r3, r0
8000ef6: 1882 adds r2, r0, r2
8000ef8: 4293 cmp r3, r2
8000efa: d100 bne.n 8000efe <memset+0xa>
8000efc: 4770 bx lr
8000efe: 7019 strb r1, [r3, #0]
8000f00: 3301 adds r3, #1
8000f02: e7f9 b.n 8000ef8 <memset+0x4>
08000f04 <_init>:
8000f04: b5f8 push {r3, r4, r5, r6, r7, lr}
8000f06: 46c0 nop ; (mov r8, r8)
8000f08: bcf8 pop {r3, r4, r5, r6, r7}
8000f0a: bc08 pop {r3}
8000f0c: 469e mov lr, r3
8000f0e: 4770 bx lr
08000f10 <_fini>:
8000f10: b5f8 push {r3, r4, r5, r6, r7, lr}
8000f12: 46c0 nop ; (mov r8, r8)
8000f14: bcf8 pop {r3, r4, r5, r6, r7}
8000f16: bc08 pop {r3}
8000f18: 469e mov lr, r3
8000f1a: 4770 bx lr
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