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adc745e2a7811c242d8a4b4609f63f1a344c6c3c
motor_controller/Debug/Motor_Controller.list
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kevin adc745e2a7 显示部分已驱动
2021-09-18 10:34:38 +08:00

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Motor_Controller.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003168 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000190 08003228 08003228 00013228 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080033b8 080033b8 00020070 2**0
CONTENTS
4 .ARM 00000000 080033b8 080033b8 00020070 2**0
CONTENTS
5 .preinit_array 00000000 080033b8 080033b8 00020070 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080033b8 080033b8 000133b8 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080033bc 080033bc 000133bc 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000070 20000000 080033c0 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000080 20000070 08003430 00020070 2**2
ALLOC
10 ._user_heap_stack 00000600 200000f0 08003430 000200f0 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 00020070 2**0
CONTENTS, READONLY
12 .debug_info 00006049 00000000 00000000 00020098 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001689 00000000 00000000 000260e1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000558 00000000 00000000 00027770 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000490 00000000 00000000 00027cc8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0000feff 00000000 00000000 00028158 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00007173 00000000 00000000 00038057 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0005bd24 00000000 00000000 0003f1ca 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 0009aeee 2**0
CONTENTS, READONLY
20 .debug_frame 00001b10 00000000 00000000 0009af44 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 20000070 .word 0x20000070
80000e0: 00000000 .word 0x00000000
80000e4: 08003210 .word 0x08003210
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000074 .word 0x20000074
8000104: 08003210 .word 0x08003210
08000108 <__gnu_thumb1_case_shi>:
8000108: b403 push {r0, r1}
800010a: 4671 mov r1, lr
800010c: 0849 lsrs r1, r1, #1
800010e: 0040 lsls r0, r0, #1
8000110: 0049 lsls r1, r1, #1
8000112: 5e09 ldrsh r1, [r1, r0]
8000114: 0049 lsls r1, r1, #1
8000116: 448e add lr, r1
8000118: bc03 pop {r0, r1}
800011a: 4770 bx lr
0800011c <__udivsi3>:
800011c: 2200 movs r2, #0
800011e: 0843 lsrs r3, r0, #1
8000120: 428b cmp r3, r1
8000122: d374 bcc.n 800020e <__udivsi3+0xf2>
8000124: 0903 lsrs r3, r0, #4
8000126: 428b cmp r3, r1
8000128: d35f bcc.n 80001ea <__udivsi3+0xce>
800012a: 0a03 lsrs r3, r0, #8
800012c: 428b cmp r3, r1
800012e: d344 bcc.n 80001ba <__udivsi3+0x9e>
8000130: 0b03 lsrs r3, r0, #12
8000132: 428b cmp r3, r1
8000134: d328 bcc.n 8000188 <__udivsi3+0x6c>
8000136: 0c03 lsrs r3, r0, #16
8000138: 428b cmp r3, r1
800013a: d30d bcc.n 8000158 <__udivsi3+0x3c>
800013c: 22ff movs r2, #255 ; 0xff
800013e: 0209 lsls r1, r1, #8
8000140: ba12 rev r2, r2
8000142: 0c03 lsrs r3, r0, #16
8000144: 428b cmp r3, r1
8000146: d302 bcc.n 800014e <__udivsi3+0x32>
8000148: 1212 asrs r2, r2, #8
800014a: 0209 lsls r1, r1, #8
800014c: d065 beq.n 800021a <__udivsi3+0xfe>
800014e: 0b03 lsrs r3, r0, #12
8000150: 428b cmp r3, r1
8000152: d319 bcc.n 8000188 <__udivsi3+0x6c>
8000154: e000 b.n 8000158 <__udivsi3+0x3c>
8000156: 0a09 lsrs r1, r1, #8
8000158: 0bc3 lsrs r3, r0, #15
800015a: 428b cmp r3, r1
800015c: d301 bcc.n 8000162 <__udivsi3+0x46>
800015e: 03cb lsls r3, r1, #15
8000160: 1ac0 subs r0, r0, r3
8000162: 4152 adcs r2, r2
8000164: 0b83 lsrs r3, r0, #14
8000166: 428b cmp r3, r1
8000168: d301 bcc.n 800016e <__udivsi3+0x52>
800016a: 038b lsls r3, r1, #14
800016c: 1ac0 subs r0, r0, r3
800016e: 4152 adcs r2, r2
8000170: 0b43 lsrs r3, r0, #13
8000172: 428b cmp r3, r1
8000174: d301 bcc.n 800017a <__udivsi3+0x5e>
8000176: 034b lsls r3, r1, #13
8000178: 1ac0 subs r0, r0, r3
800017a: 4152 adcs r2, r2
800017c: 0b03 lsrs r3, r0, #12
800017e: 428b cmp r3, r1
8000180: d301 bcc.n 8000186 <__udivsi3+0x6a>
8000182: 030b lsls r3, r1, #12
8000184: 1ac0 subs r0, r0, r3
8000186: 4152 adcs r2, r2
8000188: 0ac3 lsrs r3, r0, #11
800018a: 428b cmp r3, r1
800018c: d301 bcc.n 8000192 <__udivsi3+0x76>
800018e: 02cb lsls r3, r1, #11
8000190: 1ac0 subs r0, r0, r3
8000192: 4152 adcs r2, r2
8000194: 0a83 lsrs r3, r0, #10
8000196: 428b cmp r3, r1
8000198: d301 bcc.n 800019e <__udivsi3+0x82>
800019a: 028b lsls r3, r1, #10
800019c: 1ac0 subs r0, r0, r3
800019e: 4152 adcs r2, r2
80001a0: 0a43 lsrs r3, r0, #9
80001a2: 428b cmp r3, r1
80001a4: d301 bcc.n 80001aa <__udivsi3+0x8e>
80001a6: 024b lsls r3, r1, #9
80001a8: 1ac0 subs r0, r0, r3
80001aa: 4152 adcs r2, r2
80001ac: 0a03 lsrs r3, r0, #8
80001ae: 428b cmp r3, r1
80001b0: d301 bcc.n 80001b6 <__udivsi3+0x9a>
80001b2: 020b lsls r3, r1, #8
80001b4: 1ac0 subs r0, r0, r3
80001b6: 4152 adcs r2, r2
80001b8: d2cd bcs.n 8000156 <__udivsi3+0x3a>
80001ba: 09c3 lsrs r3, r0, #7
80001bc: 428b cmp r3, r1
80001be: d301 bcc.n 80001c4 <__udivsi3+0xa8>
80001c0: 01cb lsls r3, r1, #7
80001c2: 1ac0 subs r0, r0, r3
80001c4: 4152 adcs r2, r2
80001c6: 0983 lsrs r3, r0, #6
80001c8: 428b cmp r3, r1
80001ca: d301 bcc.n 80001d0 <__udivsi3+0xb4>
80001cc: 018b lsls r3, r1, #6
80001ce: 1ac0 subs r0, r0, r3
80001d0: 4152 adcs r2, r2
80001d2: 0943 lsrs r3, r0, #5
80001d4: 428b cmp r3, r1
80001d6: d301 bcc.n 80001dc <__udivsi3+0xc0>
80001d8: 014b lsls r3, r1, #5
80001da: 1ac0 subs r0, r0, r3
80001dc: 4152 adcs r2, r2
80001de: 0903 lsrs r3, r0, #4
80001e0: 428b cmp r3, r1
80001e2: d301 bcc.n 80001e8 <__udivsi3+0xcc>
80001e4: 010b lsls r3, r1, #4
80001e6: 1ac0 subs r0, r0, r3
80001e8: 4152 adcs r2, r2
80001ea: 08c3 lsrs r3, r0, #3
80001ec: 428b cmp r3, r1
80001ee: d301 bcc.n 80001f4 <__udivsi3+0xd8>
80001f0: 00cb lsls r3, r1, #3
80001f2: 1ac0 subs r0, r0, r3
80001f4: 4152 adcs r2, r2
80001f6: 0883 lsrs r3, r0, #2
80001f8: 428b cmp r3, r1
80001fa: d301 bcc.n 8000200 <__udivsi3+0xe4>
80001fc: 008b lsls r3, r1, #2
80001fe: 1ac0 subs r0, r0, r3
8000200: 4152 adcs r2, r2
8000202: 0843 lsrs r3, r0, #1
8000204: 428b cmp r3, r1
8000206: d301 bcc.n 800020c <__udivsi3+0xf0>
8000208: 004b lsls r3, r1, #1
800020a: 1ac0 subs r0, r0, r3
800020c: 4152 adcs r2, r2
800020e: 1a41 subs r1, r0, r1
8000210: d200 bcs.n 8000214 <__udivsi3+0xf8>
8000212: 4601 mov r1, r0
8000214: 4152 adcs r2, r2
8000216: 4610 mov r0, r2
8000218: 4770 bx lr
800021a: e7ff b.n 800021c <__udivsi3+0x100>
800021c: b501 push {r0, lr}
800021e: 2000 movs r0, #0
8000220: f000 f8f0 bl 8000404 <__aeabi_idiv0>
8000224: bd02 pop {r1, pc}
8000226: 46c0 nop ; (mov r8, r8)
08000228 <__aeabi_uidivmod>:
8000228: 2900 cmp r1, #0
800022a: d0f7 beq.n 800021c <__udivsi3+0x100>
800022c: e776 b.n 800011c <__udivsi3>
800022e: 4770 bx lr
08000230 <__divsi3>:
8000230: 4603 mov r3, r0
8000232: 430b orrs r3, r1
8000234: d47f bmi.n 8000336 <__divsi3+0x106>
8000236: 2200 movs r2, #0
8000238: 0843 lsrs r3, r0, #1
800023a: 428b cmp r3, r1
800023c: d374 bcc.n 8000328 <__divsi3+0xf8>
800023e: 0903 lsrs r3, r0, #4
8000240: 428b cmp r3, r1
8000242: d35f bcc.n 8000304 <__divsi3+0xd4>
8000244: 0a03 lsrs r3, r0, #8
8000246: 428b cmp r3, r1
8000248: d344 bcc.n 80002d4 <__divsi3+0xa4>
800024a: 0b03 lsrs r3, r0, #12
800024c: 428b cmp r3, r1
800024e: d328 bcc.n 80002a2 <__divsi3+0x72>
8000250: 0c03 lsrs r3, r0, #16
8000252: 428b cmp r3, r1
8000254: d30d bcc.n 8000272 <__divsi3+0x42>
8000256: 22ff movs r2, #255 ; 0xff
8000258: 0209 lsls r1, r1, #8
800025a: ba12 rev r2, r2
800025c: 0c03 lsrs r3, r0, #16
800025e: 428b cmp r3, r1
8000260: d302 bcc.n 8000268 <__divsi3+0x38>
8000262: 1212 asrs r2, r2, #8
8000264: 0209 lsls r1, r1, #8
8000266: d065 beq.n 8000334 <__divsi3+0x104>
8000268: 0b03 lsrs r3, r0, #12
800026a: 428b cmp r3, r1
800026c: d319 bcc.n 80002a2 <__divsi3+0x72>
800026e: e000 b.n 8000272 <__divsi3+0x42>
8000270: 0a09 lsrs r1, r1, #8
8000272: 0bc3 lsrs r3, r0, #15
8000274: 428b cmp r3, r1
8000276: d301 bcc.n 800027c <__divsi3+0x4c>
8000278: 03cb lsls r3, r1, #15
800027a: 1ac0 subs r0, r0, r3
800027c: 4152 adcs r2, r2
800027e: 0b83 lsrs r3, r0, #14
8000280: 428b cmp r3, r1
8000282: d301 bcc.n 8000288 <__divsi3+0x58>
8000284: 038b lsls r3, r1, #14
8000286: 1ac0 subs r0, r0, r3
8000288: 4152 adcs r2, r2
800028a: 0b43 lsrs r3, r0, #13
800028c: 428b cmp r3, r1
800028e: d301 bcc.n 8000294 <__divsi3+0x64>
8000290: 034b lsls r3, r1, #13
8000292: 1ac0 subs r0, r0, r3
8000294: 4152 adcs r2, r2
8000296: 0b03 lsrs r3, r0, #12
8000298: 428b cmp r3, r1
800029a: d301 bcc.n 80002a0 <__divsi3+0x70>
800029c: 030b lsls r3, r1, #12
800029e: 1ac0 subs r0, r0, r3
80002a0: 4152 adcs r2, r2
80002a2: 0ac3 lsrs r3, r0, #11
80002a4: 428b cmp r3, r1
80002a6: d301 bcc.n 80002ac <__divsi3+0x7c>
80002a8: 02cb lsls r3, r1, #11
80002aa: 1ac0 subs r0, r0, r3
80002ac: 4152 adcs r2, r2
80002ae: 0a83 lsrs r3, r0, #10
80002b0: 428b cmp r3, r1
80002b2: d301 bcc.n 80002b8 <__divsi3+0x88>
80002b4: 028b lsls r3, r1, #10
80002b6: 1ac0 subs r0, r0, r3
80002b8: 4152 adcs r2, r2
80002ba: 0a43 lsrs r3, r0, #9
80002bc: 428b cmp r3, r1
80002be: d301 bcc.n 80002c4 <__divsi3+0x94>
80002c0: 024b lsls r3, r1, #9
80002c2: 1ac0 subs r0, r0, r3
80002c4: 4152 adcs r2, r2
80002c6: 0a03 lsrs r3, r0, #8
80002c8: 428b cmp r3, r1
80002ca: d301 bcc.n 80002d0 <__divsi3+0xa0>
80002cc: 020b lsls r3, r1, #8
80002ce: 1ac0 subs r0, r0, r3
80002d0: 4152 adcs r2, r2
80002d2: d2cd bcs.n 8000270 <__divsi3+0x40>
80002d4: 09c3 lsrs r3, r0, #7
80002d6: 428b cmp r3, r1
80002d8: d301 bcc.n 80002de <__divsi3+0xae>
80002da: 01cb lsls r3, r1, #7
80002dc: 1ac0 subs r0, r0, r3
80002de: 4152 adcs r2, r2
80002e0: 0983 lsrs r3, r0, #6
80002e2: 428b cmp r3, r1
80002e4: d301 bcc.n 80002ea <__divsi3+0xba>
80002e6: 018b lsls r3, r1, #6
80002e8: 1ac0 subs r0, r0, r3
80002ea: 4152 adcs r2, r2
80002ec: 0943 lsrs r3, r0, #5
80002ee: 428b cmp r3, r1
80002f0: d301 bcc.n 80002f6 <__divsi3+0xc6>
80002f2: 014b lsls r3, r1, #5
80002f4: 1ac0 subs r0, r0, r3
80002f6: 4152 adcs r2, r2
80002f8: 0903 lsrs r3, r0, #4
80002fa: 428b cmp r3, r1
80002fc: d301 bcc.n 8000302 <__divsi3+0xd2>
80002fe: 010b lsls r3, r1, #4
8000300: 1ac0 subs r0, r0, r3
8000302: 4152 adcs r2, r2
8000304: 08c3 lsrs r3, r0, #3
8000306: 428b cmp r3, r1
8000308: d301 bcc.n 800030e <__divsi3+0xde>
800030a: 00cb lsls r3, r1, #3
800030c: 1ac0 subs r0, r0, r3
800030e: 4152 adcs r2, r2
8000310: 0883 lsrs r3, r0, #2
8000312: 428b cmp r3, r1
8000314: d301 bcc.n 800031a <__divsi3+0xea>
8000316: 008b lsls r3, r1, #2
8000318: 1ac0 subs r0, r0, r3
800031a: 4152 adcs r2, r2
800031c: 0843 lsrs r3, r0, #1
800031e: 428b cmp r3, r1
8000320: d301 bcc.n 8000326 <__divsi3+0xf6>
8000322: 004b lsls r3, r1, #1
8000324: 1ac0 subs r0, r0, r3
8000326: 4152 adcs r2, r2
8000328: 1a41 subs r1, r0, r1
800032a: d200 bcs.n 800032e <__divsi3+0xfe>
800032c: 4601 mov r1, r0
800032e: 4152 adcs r2, r2
8000330: 4610 mov r0, r2
8000332: 4770 bx lr
8000334: e05d b.n 80003f2 <__divsi3+0x1c2>
8000336: 0fca lsrs r2, r1, #31
8000338: d000 beq.n 800033c <__divsi3+0x10c>
800033a: 4249 negs r1, r1
800033c: 1003 asrs r3, r0, #32
800033e: d300 bcc.n 8000342 <__divsi3+0x112>
8000340: 4240 negs r0, r0
8000342: 4053 eors r3, r2
8000344: 2200 movs r2, #0
8000346: 469c mov ip, r3
8000348: 0903 lsrs r3, r0, #4
800034a: 428b cmp r3, r1
800034c: d32d bcc.n 80003aa <__divsi3+0x17a>
800034e: 0a03 lsrs r3, r0, #8
8000350: 428b cmp r3, r1
8000352: d312 bcc.n 800037a <__divsi3+0x14a>
8000354: 22fc movs r2, #252 ; 0xfc
8000356: 0189 lsls r1, r1, #6
8000358: ba12 rev r2, r2
800035a: 0a03 lsrs r3, r0, #8
800035c: 428b cmp r3, r1
800035e: d30c bcc.n 800037a <__divsi3+0x14a>
8000360: 0189 lsls r1, r1, #6
8000362: 1192 asrs r2, r2, #6
8000364: 428b cmp r3, r1
8000366: d308 bcc.n 800037a <__divsi3+0x14a>
8000368: 0189 lsls r1, r1, #6
800036a: 1192 asrs r2, r2, #6
800036c: 428b cmp r3, r1
800036e: d304 bcc.n 800037a <__divsi3+0x14a>
8000370: 0189 lsls r1, r1, #6
8000372: d03a beq.n 80003ea <__divsi3+0x1ba>
8000374: 1192 asrs r2, r2, #6
8000376: e000 b.n 800037a <__divsi3+0x14a>
8000378: 0989 lsrs r1, r1, #6
800037a: 09c3 lsrs r3, r0, #7
800037c: 428b cmp r3, r1
800037e: d301 bcc.n 8000384 <__divsi3+0x154>
8000380: 01cb lsls r3, r1, #7
8000382: 1ac0 subs r0, r0, r3
8000384: 4152 adcs r2, r2
8000386: 0983 lsrs r3, r0, #6
8000388: 428b cmp r3, r1
800038a: d301 bcc.n 8000390 <__divsi3+0x160>
800038c: 018b lsls r3, r1, #6
800038e: 1ac0 subs r0, r0, r3
8000390: 4152 adcs r2, r2
8000392: 0943 lsrs r3, r0, #5
8000394: 428b cmp r3, r1
8000396: d301 bcc.n 800039c <__divsi3+0x16c>
8000398: 014b lsls r3, r1, #5
800039a: 1ac0 subs r0, r0, r3
800039c: 4152 adcs r2, r2
800039e: 0903 lsrs r3, r0, #4
80003a0: 428b cmp r3, r1
80003a2: d301 bcc.n 80003a8 <__divsi3+0x178>
80003a4: 010b lsls r3, r1, #4
80003a6: 1ac0 subs r0, r0, r3
80003a8: 4152 adcs r2, r2
80003aa: 08c3 lsrs r3, r0, #3
80003ac: 428b cmp r3, r1
80003ae: d301 bcc.n 80003b4 <__divsi3+0x184>
80003b0: 00cb lsls r3, r1, #3
80003b2: 1ac0 subs r0, r0, r3
80003b4: 4152 adcs r2, r2
80003b6: 0883 lsrs r3, r0, #2
80003b8: 428b cmp r3, r1
80003ba: d301 bcc.n 80003c0 <__divsi3+0x190>
80003bc: 008b lsls r3, r1, #2
80003be: 1ac0 subs r0, r0, r3
80003c0: 4152 adcs r2, r2
80003c2: d2d9 bcs.n 8000378 <__divsi3+0x148>
80003c4: 0843 lsrs r3, r0, #1
80003c6: 428b cmp r3, r1
80003c8: d301 bcc.n 80003ce <__divsi3+0x19e>
80003ca: 004b lsls r3, r1, #1
80003cc: 1ac0 subs r0, r0, r3
80003ce: 4152 adcs r2, r2
80003d0: 1a41 subs r1, r0, r1
80003d2: d200 bcs.n 80003d6 <__divsi3+0x1a6>
80003d4: 4601 mov r1, r0
80003d6: 4663 mov r3, ip
80003d8: 4152 adcs r2, r2
80003da: 105b asrs r3, r3, #1
80003dc: 4610 mov r0, r2
80003de: d301 bcc.n 80003e4 <__divsi3+0x1b4>
80003e0: 4240 negs r0, r0
80003e2: 2b00 cmp r3, #0
80003e4: d500 bpl.n 80003e8 <__divsi3+0x1b8>
80003e6: 4249 negs r1, r1
80003e8: 4770 bx lr
80003ea: 4663 mov r3, ip
80003ec: 105b asrs r3, r3, #1
80003ee: d300 bcc.n 80003f2 <__divsi3+0x1c2>
80003f0: 4240 negs r0, r0
80003f2: b501 push {r0, lr}
80003f4: 2000 movs r0, #0
80003f6: f000 f805 bl 8000404 <__aeabi_idiv0>
80003fa: bd02 pop {r1, pc}
080003fc <__aeabi_idivmod>:
80003fc: 2900 cmp r1, #0
80003fe: d0f8 beq.n 80003f2 <__divsi3+0x1c2>
8000400: e716 b.n 8000230 <__divsi3>
8000402: 4770 bx lr
08000404 <__aeabi_idiv0>:
8000404: 4770 bx lr
8000406: 46c0 nop ; (mov r8, r8)
08000408 <__aeabi_lmul>:
8000408: b5f0 push {r4, r5, r6, r7, lr}
800040a: 0415 lsls r5, r2, #16
800040c: 0c2d lsrs r5, r5, #16
800040e: 000f movs r7, r1
8000410: 0001 movs r1, r0
8000412: 002e movs r6, r5
8000414: 46c6 mov lr, r8
8000416: 4684 mov ip, r0
8000418: 0400 lsls r0, r0, #16
800041a: 0c14 lsrs r4, r2, #16
800041c: 0c00 lsrs r0, r0, #16
800041e: 0c09 lsrs r1, r1, #16
8000420: 4346 muls r6, r0
8000422: 434d muls r5, r1
8000424: 4360 muls r0, r4
8000426: 4361 muls r1, r4
8000428: 1940 adds r0, r0, r5
800042a: 0c34 lsrs r4, r6, #16
800042c: 1824 adds r4, r4, r0
800042e: b500 push {lr}
8000430: 42a5 cmp r5, r4
8000432: d903 bls.n 800043c <__aeabi_lmul+0x34>
8000434: 2080 movs r0, #128 ; 0x80
8000436: 0240 lsls r0, r0, #9
8000438: 4680 mov r8, r0
800043a: 4441 add r1, r8
800043c: 0c25 lsrs r5, r4, #16
800043e: 186d adds r5, r5, r1
8000440: 4661 mov r1, ip
8000442: 4359 muls r1, r3
8000444: 437a muls r2, r7
8000446: 0430 lsls r0, r6, #16
8000448: 1949 adds r1, r1, r5
800044a: 0424 lsls r4, r4, #16
800044c: 0c00 lsrs r0, r0, #16
800044e: 1820 adds r0, r4, r0
8000450: 1889 adds r1, r1, r2
8000452: bc80 pop {r7}
8000454: 46b8 mov r8, r7
8000456: bdf0 pop {r4, r5, r6, r7, pc}
08000458 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000458: b580 push {r7, lr}
800045a: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800045c: f000 fa9e bl 800099c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000460: f000 f807 bl 8000472 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000464: f000 f8b2 bl 80005cc <MX_GPIO_Init>
MX_ADC_Init();
8000468: f000 f854 bl 8000514 <MX_ADC_Init>
/* USER CODE BEGIN 2 */
mymain();
800046c: f001 fd1c bl 8001ea8 <mymain>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000470: e7fe b.n 8000470 <main+0x18>
08000472 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000472: b590 push {r4, r7, lr}
8000474: b091 sub sp, #68 ; 0x44
8000476: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000478: 2410 movs r4, #16
800047a: 193b adds r3, r7, r4
800047c: 0018 movs r0, r3
800047e: 2330 movs r3, #48 ; 0x30
8000480: 001a movs r2, r3
8000482: 2100 movs r1, #0
8000484: f001 fe70 bl 8002168 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000488: 003b movs r3, r7
800048a: 0018 movs r0, r3
800048c: 2310 movs r3, #16
800048e: 001a movs r2, r3
8000490: 2100 movs r1, #0
8000492: f001 fe69 bl 8002168 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14;
8000496: 0021 movs r1, r4
8000498: 187b adds r3, r7, r1
800049a: 2212 movs r2, #18
800049c: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800049e: 187b adds r3, r7, r1
80004a0: 2201 movs r2, #1
80004a2: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
80004a4: 187b adds r3, r7, r1
80004a6: 2201 movs r2, #1
80004a8: 615a str r2, [r3, #20]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80004aa: 187b adds r3, r7, r1
80004ac: 2210 movs r2, #16
80004ae: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSI14CalibrationValue = 16;
80004b0: 187b adds r3, r7, r1
80004b2: 2210 movs r2, #16
80004b4: 619a str r2, [r3, #24]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80004b6: 187b adds r3, r7, r1
80004b8: 2202 movs r2, #2
80004ba: 621a str r2, [r3, #32]
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80004bc: 187b adds r3, r7, r1
80004be: 2200 movs r2, #0
80004c0: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
80004c2: 187b adds r3, r7, r1
80004c4: 22a0 movs r2, #160 ; 0xa0
80004c6: 0392 lsls r2, r2, #14
80004c8: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
80004ca: 187b adds r3, r7, r1
80004cc: 2200 movs r2, #0
80004ce: 62da str r2, [r3, #44] ; 0x2c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80004d0: 187b adds r3, r7, r1
80004d2: 0018 movs r0, r3
80004d4: f000 ff3e bl 8001354 <HAL_RCC_OscConfig>
80004d8: 1e03 subs r3, r0, #0
80004da: d001 beq.n 80004e0 <SystemClock_Config+0x6e>
{
Error_Handler();
80004dc: f000 f8ea bl 80006b4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80004e0: 003b movs r3, r7
80004e2: 2207 movs r2, #7
80004e4: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80004e6: 003b movs r3, r7
80004e8: 2202 movs r2, #2
80004ea: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80004ec: 003b movs r3, r7
80004ee: 2200 movs r2, #0
80004f0: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80004f2: 003b movs r3, r7
80004f4: 2200 movs r2, #0
80004f6: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
80004f8: 003b movs r3, r7
80004fa: 2101 movs r1, #1
80004fc: 0018 movs r0, r3
80004fe: f001 fa43 bl 8001988 <HAL_RCC_ClockConfig>
8000502: 1e03 subs r3, r0, #0
8000504: d001 beq.n 800050a <SystemClock_Config+0x98>
{
Error_Handler();
8000506: f000 f8d5 bl 80006b4 <Error_Handler>
}
}
800050a: 46c0 nop ; (mov r8, r8)
800050c: 46bd mov sp, r7
800050e: b011 add sp, #68 ; 0x44
8000510: bd90 pop {r4, r7, pc}
...
08000514 <MX_ADC_Init>:
* @brief ADC Initialization Function
* @param None
* @retval None
*/
static void MX_ADC_Init(void)
{
8000514: b580 push {r7, lr}
8000516: b084 sub sp, #16
8000518: af00 add r7, sp, #0
/* USER CODE BEGIN ADC_Init 0 */
/* USER CODE END ADC_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800051a: 1d3b adds r3, r7, #4
800051c: 0018 movs r0, r3
800051e: 230c movs r3, #12
8000520: 001a movs r2, r3
8000522: 2100 movs r1, #0
8000524: f001 fe20 bl 8002168 <memset>
/* USER CODE BEGIN ADC_Init 1 */
/* USER CODE END ADC_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc.Instance = ADC1;
8000528: 4b26 ldr r3, [pc, #152] ; (80005c4 <MX_ADC_Init+0xb0>)
800052a: 4a27 ldr r2, [pc, #156] ; (80005c8 <MX_ADC_Init+0xb4>)
800052c: 601a str r2, [r3, #0]
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
800052e: 4b25 ldr r3, [pc, #148] ; (80005c4 <MX_ADC_Init+0xb0>)
8000530: 2200 movs r2, #0
8000532: 605a str r2, [r3, #4]
hadc.Init.Resolution = ADC_RESOLUTION_12B;
8000534: 4b23 ldr r3, [pc, #140] ; (80005c4 <MX_ADC_Init+0xb0>)
8000536: 2200 movs r2, #0
8000538: 609a str r2, [r3, #8]
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800053a: 4b22 ldr r3, [pc, #136] ; (80005c4 <MX_ADC_Init+0xb0>)
800053c: 2200 movs r2, #0
800053e: 60da str r2, [r3, #12]
hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
8000540: 4b20 ldr r3, [pc, #128] ; (80005c4 <MX_ADC_Init+0xb0>)
8000542: 2201 movs r2, #1
8000544: 611a str r2, [r3, #16]
hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000546: 4b1f ldr r3, [pc, #124] ; (80005c4 <MX_ADC_Init+0xb0>)
8000548: 2204 movs r2, #4
800054a: 615a str r2, [r3, #20]
hadc.Init.LowPowerAutoWait = DISABLE;
800054c: 4b1d ldr r3, [pc, #116] ; (80005c4 <MX_ADC_Init+0xb0>)
800054e: 2200 movs r2, #0
8000550: 761a strb r2, [r3, #24]
hadc.Init.LowPowerAutoPowerOff = DISABLE;
8000552: 4b1c ldr r3, [pc, #112] ; (80005c4 <MX_ADC_Init+0xb0>)
8000554: 2200 movs r2, #0
8000556: 765a strb r2, [r3, #25]
hadc.Init.ContinuousConvMode = DISABLE;
8000558: 4b1a ldr r3, [pc, #104] ; (80005c4 <MX_ADC_Init+0xb0>)
800055a: 2200 movs r2, #0
800055c: 769a strb r2, [r3, #26]
hadc.Init.DiscontinuousConvMode = DISABLE;
800055e: 4b19 ldr r3, [pc, #100] ; (80005c4 <MX_ADC_Init+0xb0>)
8000560: 2200 movs r2, #0
8000562: 76da strb r2, [r3, #27]
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000564: 4b17 ldr r3, [pc, #92] ; (80005c4 <MX_ADC_Init+0xb0>)
8000566: 22c2 movs r2, #194 ; 0xc2
8000568: 32ff adds r2, #255 ; 0xff
800056a: 61da str r2, [r3, #28]
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800056c: 4b15 ldr r3, [pc, #84] ; (80005c4 <MX_ADC_Init+0xb0>)
800056e: 2200 movs r2, #0
8000570: 621a str r2, [r3, #32]
hadc.Init.DMAContinuousRequests = DISABLE;
8000572: 4b14 ldr r3, [pc, #80] ; (80005c4 <MX_ADC_Init+0xb0>)
8000574: 2224 movs r2, #36 ; 0x24
8000576: 2100 movs r1, #0
8000578: 5499 strb r1, [r3, r2]
hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
800057a: 4b12 ldr r3, [pc, #72] ; (80005c4 <MX_ADC_Init+0xb0>)
800057c: 2201 movs r2, #1
800057e: 629a str r2, [r3, #40] ; 0x28
if (HAL_ADC_Init(&hadc) != HAL_OK)
8000580: 4b10 ldr r3, [pc, #64] ; (80005c4 <MX_ADC_Init+0xb0>)
8000582: 0018 movs r0, r3
8000584: f000 fa6e bl 8000a64 <HAL_ADC_Init>
8000588: 1e03 subs r3, r0, #0
800058a: d001 beq.n 8000590 <MX_ADC_Init+0x7c>
{
Error_Handler();
800058c: f000 f892 bl 80006b4 <Error_Handler>
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000590: 1d3b adds r3, r7, #4
8000592: 2200 movs r2, #0
8000594: 601a str r2, [r3, #0]
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
8000596: 1d3b adds r3, r7, #4
8000598: 2280 movs r2, #128 ; 0x80
800059a: 0152 lsls r2, r2, #5
800059c: 605a str r2, [r3, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
800059e: 1d3b adds r3, r7, #4
80005a0: 2280 movs r2, #128 ; 0x80
80005a2: 0552 lsls r2, r2, #21
80005a4: 609a str r2, [r3, #8]
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
80005a6: 1d3a adds r2, r7, #4
80005a8: 4b06 ldr r3, [pc, #24] ; (80005c4 <MX_ADC_Init+0xb0>)
80005aa: 0011 movs r1, r2
80005ac: 0018 movs r0, r3
80005ae: f000 fb99 bl 8000ce4 <HAL_ADC_ConfigChannel>
80005b2: 1e03 subs r3, r0, #0
80005b4: d001 beq.n 80005ba <MX_ADC_Init+0xa6>
{
Error_Handler();
80005b6: f000 f87d bl 80006b4 <Error_Handler>
}
/* USER CODE BEGIN ADC_Init 2 */
/* USER CODE END ADC_Init 2 */
}
80005ba: 46c0 nop ; (mov r8, r8)
80005bc: 46bd mov sp, r7
80005be: b004 add sp, #16
80005c0: bd80 pop {r7, pc}
80005c2: 46c0 nop ; (mov r8, r8)
80005c4: 20000098 .word 0x20000098
80005c8: 40012400 .word 0x40012400
080005cc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80005cc: b590 push {r4, r7, lr}
80005ce: b089 sub sp, #36 ; 0x24
80005d0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80005d2: 240c movs r4, #12
80005d4: 193b adds r3, r7, r4
80005d6: 0018 movs r0, r3
80005d8: 2314 movs r3, #20
80005da: 001a movs r2, r3
80005dc: 2100 movs r1, #0
80005de: f001 fdc3 bl 8002168 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80005e2: 4b32 ldr r3, [pc, #200] ; (80006ac <MX_GPIO_Init+0xe0>)
80005e4: 695a ldr r2, [r3, #20]
80005e6: 4b31 ldr r3, [pc, #196] ; (80006ac <MX_GPIO_Init+0xe0>)
80005e8: 2180 movs r1, #128 ; 0x80
80005ea: 03c9 lsls r1, r1, #15
80005ec: 430a orrs r2, r1
80005ee: 615a str r2, [r3, #20]
80005f0: 4b2e ldr r3, [pc, #184] ; (80006ac <MX_GPIO_Init+0xe0>)
80005f2: 695a ldr r2, [r3, #20]
80005f4: 2380 movs r3, #128 ; 0x80
80005f6: 03db lsls r3, r3, #15
80005f8: 4013 ands r3, r2
80005fa: 60bb str r3, [r7, #8]
80005fc: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80005fe: 4b2b ldr r3, [pc, #172] ; (80006ac <MX_GPIO_Init+0xe0>)
8000600: 695a ldr r2, [r3, #20]
8000602: 4b2a ldr r3, [pc, #168] ; (80006ac <MX_GPIO_Init+0xe0>)
8000604: 2180 movs r1, #128 ; 0x80
8000606: 0289 lsls r1, r1, #10
8000608: 430a orrs r2, r1
800060a: 615a str r2, [r3, #20]
800060c: 4b27 ldr r3, [pc, #156] ; (80006ac <MX_GPIO_Init+0xe0>)
800060e: 695a ldr r2, [r3, #20]
8000610: 2380 movs r3, #128 ; 0x80
8000612: 029b lsls r3, r3, #10
8000614: 4013 ands r3, r2
8000616: 607b str r3, [r7, #4]
8000618: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, MOTA_Pin|MOTB_Pin, GPIO_PIN_RESET);
800061a: 4b25 ldr r3, [pc, #148] ; (80006b0 <MX_GPIO_Init+0xe4>)
800061c: 2200 movs r2, #0
800061e: 2103 movs r1, #3
8000620: 0018 movs r0, r3
8000622: f000 fe79 bl 8001318 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin, GPIO_PIN_RESET);
8000626: 2390 movs r3, #144 ; 0x90
8000628: 05db lsls r3, r3, #23
800062a: 2200 movs r2, #0
800062c: 2138 movs r1, #56 ; 0x38
800062e: 0018 movs r0, r3
8000630: f000 fe72 bl 8001318 <HAL_GPIO_WritePin>
/*Configure GPIO pins : MOTA_Pin MOTB_Pin */
GPIO_InitStruct.Pin = MOTA_Pin|MOTB_Pin;
8000634: 193b adds r3, r7, r4
8000636: 2203 movs r2, #3
8000638: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800063a: 193b adds r3, r7, r4
800063c: 2201 movs r2, #1
800063e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000640: 193b adds r3, r7, r4
8000642: 2200 movs r2, #0
8000644: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000646: 193b adds r3, r7, r4
8000648: 2203 movs r2, #3
800064a: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
800064c: 193b adds r3, r7, r4
800064e: 4a18 ldr r2, [pc, #96] ; (80006b0 <MX_GPIO_Init+0xe4>)
8000650: 0019 movs r1, r3
8000652: 0010 movs r0, r2
8000654: f000 fcf0 bl 8001038 <HAL_GPIO_Init>
/*Configure GPIO pins : HC595_DCK_Pin HC595_RCK_Pin HC595_SCK_Pin */
GPIO_InitStruct.Pin = HC595_DCK_Pin|HC595_RCK_Pin|HC595_SCK_Pin;
8000658: 193b adds r3, r7, r4
800065a: 2238 movs r2, #56 ; 0x38
800065c: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800065e: 193b adds r3, r7, r4
8000660: 2201 movs r2, #1
8000662: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000664: 193b adds r3, r7, r4
8000666: 2200 movs r2, #0
8000668: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800066a: 193b adds r3, r7, r4
800066c: 2203 movs r2, #3
800066e: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000670: 193a adds r2, r7, r4
8000672: 2390 movs r3, #144 ; 0x90
8000674: 05db lsls r3, r3, #23
8000676: 0011 movs r1, r2
8000678: 0018 movs r0, r3
800067a: f000 fcdd bl 8001038 <HAL_GPIO_Init>
/*Configure GPIO pins : KEY1_Pin KEY2_Pin KEY3_Pin KEY4_Pin */
GPIO_InitStruct.Pin = KEY1_Pin|KEY2_Pin|KEY3_Pin|KEY4_Pin;
800067e: 0021 movs r1, r4
8000680: 187b adds r3, r7, r1
8000682: 22d8 movs r2, #216 ; 0xd8
8000684: 00d2 lsls r2, r2, #3
8000686: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000688: 187b adds r3, r7, r1
800068a: 2200 movs r2, #0
800068c: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800068e: 187b adds r3, r7, r1
8000690: 2200 movs r2, #0
8000692: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000694: 187a adds r2, r7, r1
8000696: 2390 movs r3, #144 ; 0x90
8000698: 05db lsls r3, r3, #23
800069a: 0011 movs r1, r2
800069c: 0018 movs r0, r3
800069e: f000 fccb bl 8001038 <HAL_GPIO_Init>
}
80006a2: 46c0 nop ; (mov r8, r8)
80006a4: 46bd mov sp, r7
80006a6: b009 add sp, #36 ; 0x24
80006a8: bd90 pop {r4, r7, pc}
80006aa: 46c0 nop ; (mov r8, r8)
80006ac: 40021000 .word 0x40021000
80006b0: 48001400 .word 0x48001400
080006b4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80006b4: b580 push {r7, lr}
80006b6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80006b8: b672 cpsid i
}
80006ba: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80006bc: e7fe b.n 80006bc <Error_Handler+0x8>
...
080006c0 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80006c0: b580 push {r7, lr}
80006c2: b082 sub sp, #8
80006c4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80006c6: 4b0f ldr r3, [pc, #60] ; (8000704 <HAL_MspInit+0x44>)
80006c8: 699a ldr r2, [r3, #24]
80006ca: 4b0e ldr r3, [pc, #56] ; (8000704 <HAL_MspInit+0x44>)
80006cc: 2101 movs r1, #1
80006ce: 430a orrs r2, r1
80006d0: 619a str r2, [r3, #24]
80006d2: 4b0c ldr r3, [pc, #48] ; (8000704 <HAL_MspInit+0x44>)
80006d4: 699b ldr r3, [r3, #24]
80006d6: 2201 movs r2, #1
80006d8: 4013 ands r3, r2
80006da: 607b str r3, [r7, #4]
80006dc: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80006de: 4b09 ldr r3, [pc, #36] ; (8000704 <HAL_MspInit+0x44>)
80006e0: 69da ldr r2, [r3, #28]
80006e2: 4b08 ldr r3, [pc, #32] ; (8000704 <HAL_MspInit+0x44>)
80006e4: 2180 movs r1, #128 ; 0x80
80006e6: 0549 lsls r1, r1, #21
80006e8: 430a orrs r2, r1
80006ea: 61da str r2, [r3, #28]
80006ec: 4b05 ldr r3, [pc, #20] ; (8000704 <HAL_MspInit+0x44>)
80006ee: 69da ldr r2, [r3, #28]
80006f0: 2380 movs r3, #128 ; 0x80
80006f2: 055b lsls r3, r3, #21
80006f4: 4013 ands r3, r2
80006f6: 603b str r3, [r7, #0]
80006f8: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80006fa: 46c0 nop ; (mov r8, r8)
80006fc: 46bd mov sp, r7
80006fe: b002 add sp, #8
8000700: bd80 pop {r7, pc}
8000702: 46c0 nop ; (mov r8, r8)
8000704: 40021000 .word 0x40021000
08000708 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8000708: b590 push {r4, r7, lr}
800070a: b08b sub sp, #44 ; 0x2c
800070c: af00 add r7, sp, #0
800070e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000710: 2414 movs r4, #20
8000712: 193b adds r3, r7, r4
8000714: 0018 movs r0, r3
8000716: 2314 movs r3, #20
8000718: 001a movs r2, r3
800071a: 2100 movs r1, #0
800071c: f001 fd24 bl 8002168 <memset>
if(hadc->Instance==ADC1)
8000720: 687b ldr r3, [r7, #4]
8000722: 681b ldr r3, [r3, #0]
8000724: 4a19 ldr r2, [pc, #100] ; (800078c <HAL_ADC_MspInit+0x84>)
8000726: 4293 cmp r3, r2
8000728: d12b bne.n 8000782 <HAL_ADC_MspInit+0x7a>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
800072a: 4b19 ldr r3, [pc, #100] ; (8000790 <HAL_ADC_MspInit+0x88>)
800072c: 699a ldr r2, [r3, #24]
800072e: 4b18 ldr r3, [pc, #96] ; (8000790 <HAL_ADC_MspInit+0x88>)
8000730: 2180 movs r1, #128 ; 0x80
8000732: 0089 lsls r1, r1, #2
8000734: 430a orrs r2, r1
8000736: 619a str r2, [r3, #24]
8000738: 4b15 ldr r3, [pc, #84] ; (8000790 <HAL_ADC_MspInit+0x88>)
800073a: 699a ldr r2, [r3, #24]
800073c: 2380 movs r3, #128 ; 0x80
800073e: 009b lsls r3, r3, #2
8000740: 4013 ands r3, r2
8000742: 613b str r3, [r7, #16]
8000744: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000746: 4b12 ldr r3, [pc, #72] ; (8000790 <HAL_ADC_MspInit+0x88>)
8000748: 695a ldr r2, [r3, #20]
800074a: 4b11 ldr r3, [pc, #68] ; (8000790 <HAL_ADC_MspInit+0x88>)
800074c: 2180 movs r1, #128 ; 0x80
800074e: 0289 lsls r1, r1, #10
8000750: 430a orrs r2, r1
8000752: 615a str r2, [r3, #20]
8000754: 4b0e ldr r3, [pc, #56] ; (8000790 <HAL_ADC_MspInit+0x88>)
8000756: 695a ldr r2, [r3, #20]
8000758: 2380 movs r3, #128 ; 0x80
800075a: 029b lsls r3, r3, #10
800075c: 4013 ands r3, r2
800075e: 60fb str r3, [r7, #12]
8000760: 68fb ldr r3, [r7, #12]
/**ADC GPIO Configuration
PA0 ------> ADC_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000762: 193b adds r3, r7, r4
8000764: 2201 movs r2, #1
8000766: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000768: 193b adds r3, r7, r4
800076a: 2203 movs r2, #3
800076c: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800076e: 193b adds r3, r7, r4
8000770: 2200 movs r2, #0
8000772: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000774: 193a adds r2, r7, r4
8000776: 2390 movs r3, #144 ; 0x90
8000778: 05db lsls r3, r3, #23
800077a: 0011 movs r1, r2
800077c: 0018 movs r0, r3
800077e: f000 fc5b bl 8001038 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
8000782: 46c0 nop ; (mov r8, r8)
8000784: 46bd mov sp, r7
8000786: b00b add sp, #44 ; 0x2c
8000788: bd90 pop {r4, r7, pc}
800078a: 46c0 nop ; (mov r8, r8)
800078c: 40012400 .word 0x40012400
8000790: 40021000 .word 0x40021000
08000794 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000794: b580 push {r7, lr}
8000796: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000798: e7fe b.n 8000798 <NMI_Handler+0x4>
0800079a <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800079a: b580 push {r7, lr}
800079c: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800079e: e7fe b.n 800079e <HardFault_Handler+0x4>
080007a0 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80007a0: b580 push {r7, lr}
80007a2: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
80007a4: 46c0 nop ; (mov r8, r8)
80007a6: 46bd mov sp, r7
80007a8: bd80 pop {r7, pc}
080007aa <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80007aa: b580 push {r7, lr}
80007ac: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80007ae: 46c0 nop ; (mov r8, r8)
80007b0: 46bd mov sp, r7
80007b2: bd80 pop {r7, pc}
080007b4 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80007b4: b580 push {r7, lr}
80007b6: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80007b8: f000 f938 bl 8000a2c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80007bc: 46c0 nop ; (mov r8, r8)
80007be: 46bd mov sp, r7
80007c0: bd80 pop {r7, pc}
080007c2 <_getpid>:
void initialise_monitor_handles()
{
}
int _getpid(void)
{
80007c2: b580 push {r7, lr}
80007c4: af00 add r7, sp, #0
return 1;
80007c6: 2301 movs r3, #1
}
80007c8: 0018 movs r0, r3
80007ca: 46bd mov sp, r7
80007cc: bd80 pop {r7, pc}
080007ce <_kill>:
int _kill(int pid, int sig)
{
80007ce: b580 push {r7, lr}
80007d0: b082 sub sp, #8
80007d2: af00 add r7, sp, #0
80007d4: 6078 str r0, [r7, #4]
80007d6: 6039 str r1, [r7, #0]
errno = EINVAL;
80007d8: f001 fc9c bl 8002114 <__errno>
80007dc: 0003 movs r3, r0
80007de: 2216 movs r2, #22
80007e0: 601a str r2, [r3, #0]
return -1;
80007e2: 2301 movs r3, #1
80007e4: 425b negs r3, r3
}
80007e6: 0018 movs r0, r3
80007e8: 46bd mov sp, r7
80007ea: b002 add sp, #8
80007ec: bd80 pop {r7, pc}
080007ee <_exit>:
void _exit (int status)
{
80007ee: b580 push {r7, lr}
80007f0: b082 sub sp, #8
80007f2: af00 add r7, sp, #0
80007f4: 6078 str r0, [r7, #4]
_kill(status, -1);
80007f6: 2301 movs r3, #1
80007f8: 425a negs r2, r3
80007fa: 687b ldr r3, [r7, #4]
80007fc: 0011 movs r1, r2
80007fe: 0018 movs r0, r3
8000800: f7ff ffe5 bl 80007ce <_kill>
while (1) {} /* Make sure we hang here */
8000804: e7fe b.n 8000804 <_exit+0x16>
08000806 <_read>:
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8000806: b580 push {r7, lr}
8000808: b086 sub sp, #24
800080a: af00 add r7, sp, #0
800080c: 60f8 str r0, [r7, #12]
800080e: 60b9 str r1, [r7, #8]
8000810: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000812: 2300 movs r3, #0
8000814: 617b str r3, [r7, #20]
8000816: e00a b.n 800082e <_read+0x28>
{
*ptr++ = __io_getchar();
8000818: e000 b.n 800081c <_read+0x16>
800081a: bf00 nop
800081c: 0001 movs r1, r0
800081e: 68bb ldr r3, [r7, #8]
8000820: 1c5a adds r2, r3, #1
8000822: 60ba str r2, [r7, #8]
8000824: b2ca uxtb r2, r1
8000826: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000828: 697b ldr r3, [r7, #20]
800082a: 3301 adds r3, #1
800082c: 617b str r3, [r7, #20]
800082e: 697a ldr r2, [r7, #20]
8000830: 687b ldr r3, [r7, #4]
8000832: 429a cmp r2, r3
8000834: dbf0 blt.n 8000818 <_read+0x12>
}
return len;
8000836: 687b ldr r3, [r7, #4]
}
8000838: 0018 movs r0, r3
800083a: 46bd mov sp, r7
800083c: b006 add sp, #24
800083e: bd80 pop {r7, pc}
08000840 <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
8000840: b580 push {r7, lr}
8000842: b086 sub sp, #24
8000844: af00 add r7, sp, #0
8000846: 60f8 str r0, [r7, #12]
8000848: 60b9 str r1, [r7, #8]
800084a: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
800084c: 2300 movs r3, #0
800084e: 617b str r3, [r7, #20]
8000850: e009 b.n 8000866 <_write+0x26>
{
__io_putchar(*ptr++);
8000852: 68bb ldr r3, [r7, #8]
8000854: 1c5a adds r2, r3, #1
8000856: 60ba str r2, [r7, #8]
8000858: 781b ldrb r3, [r3, #0]
800085a: 0018 movs r0, r3
800085c: e000 b.n 8000860 <_write+0x20>
800085e: bf00 nop
for (DataIdx = 0; DataIdx < len; DataIdx++)
8000860: 697b ldr r3, [r7, #20]
8000862: 3301 adds r3, #1
8000864: 617b str r3, [r7, #20]
8000866: 697a ldr r2, [r7, #20]
8000868: 687b ldr r3, [r7, #4]
800086a: 429a cmp r2, r3
800086c: dbf1 blt.n 8000852 <_write+0x12>
}
return len;
800086e: 687b ldr r3, [r7, #4]
}
8000870: 0018 movs r0, r3
8000872: 46bd mov sp, r7
8000874: b006 add sp, #24
8000876: bd80 pop {r7, pc}
08000878 <_close>:
int _close(int file)
{
8000878: b580 push {r7, lr}
800087a: b082 sub sp, #8
800087c: af00 add r7, sp, #0
800087e: 6078 str r0, [r7, #4]
return -1;
8000880: 2301 movs r3, #1
8000882: 425b negs r3, r3
}
8000884: 0018 movs r0, r3
8000886: 46bd mov sp, r7
8000888: b002 add sp, #8
800088a: bd80 pop {r7, pc}
0800088c <_fstat>:
int _fstat(int file, struct stat *st)
{
800088c: b580 push {r7, lr}
800088e: b082 sub sp, #8
8000890: af00 add r7, sp, #0
8000892: 6078 str r0, [r7, #4]
8000894: 6039 str r1, [r7, #0]
st->st_mode = S_IFCHR;
8000896: 683b ldr r3, [r7, #0]
8000898: 2280 movs r2, #128 ; 0x80
800089a: 0192 lsls r2, r2, #6
800089c: 605a str r2, [r3, #4]
return 0;
800089e: 2300 movs r3, #0
}
80008a0: 0018 movs r0, r3
80008a2: 46bd mov sp, r7
80008a4: b002 add sp, #8
80008a6: bd80 pop {r7, pc}
080008a8 <_isatty>:
int _isatty(int file)
{
80008a8: b580 push {r7, lr}
80008aa: b082 sub sp, #8
80008ac: af00 add r7, sp, #0
80008ae: 6078 str r0, [r7, #4]
return 1;
80008b0: 2301 movs r3, #1
}
80008b2: 0018 movs r0, r3
80008b4: 46bd mov sp, r7
80008b6: b002 add sp, #8
80008b8: bd80 pop {r7, pc}
080008ba <_lseek>:
int _lseek(int file, int ptr, int dir)
{
80008ba: b580 push {r7, lr}
80008bc: b084 sub sp, #16
80008be: af00 add r7, sp, #0
80008c0: 60f8 str r0, [r7, #12]
80008c2: 60b9 str r1, [r7, #8]
80008c4: 607a str r2, [r7, #4]
return 0;
80008c6: 2300 movs r3, #0
}
80008c8: 0018 movs r0, r3
80008ca: 46bd mov sp, r7
80008cc: b004 add sp, #16
80008ce: bd80 pop {r7, pc}
080008d0 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
80008d0: b580 push {r7, lr}
80008d2: b086 sub sp, #24
80008d4: af00 add r7, sp, #0
80008d6: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
80008d8: 4a14 ldr r2, [pc, #80] ; (800092c <_sbrk+0x5c>)
80008da: 4b15 ldr r3, [pc, #84] ; (8000930 <_sbrk+0x60>)
80008dc: 1ad3 subs r3, r2, r3
80008de: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
80008e0: 697b ldr r3, [r7, #20]
80008e2: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
80008e4: 4b13 ldr r3, [pc, #76] ; (8000934 <_sbrk+0x64>)
80008e6: 681b ldr r3, [r3, #0]
80008e8: 2b00 cmp r3, #0
80008ea: d102 bne.n 80008f2 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
80008ec: 4b11 ldr r3, [pc, #68] ; (8000934 <_sbrk+0x64>)
80008ee: 4a12 ldr r2, [pc, #72] ; (8000938 <_sbrk+0x68>)
80008f0: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
80008f2: 4b10 ldr r3, [pc, #64] ; (8000934 <_sbrk+0x64>)
80008f4: 681a ldr r2, [r3, #0]
80008f6: 687b ldr r3, [r7, #4]
80008f8: 18d3 adds r3, r2, r3
80008fa: 693a ldr r2, [r7, #16]
80008fc: 429a cmp r2, r3
80008fe: d207 bcs.n 8000910 <_sbrk+0x40>
{
errno = ENOMEM;
8000900: f001 fc08 bl 8002114 <__errno>
8000904: 0003 movs r3, r0
8000906: 220c movs r2, #12
8000908: 601a str r2, [r3, #0]
return (void *)-1;
800090a: 2301 movs r3, #1
800090c: 425b negs r3, r3
800090e: e009 b.n 8000924 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8000910: 4b08 ldr r3, [pc, #32] ; (8000934 <_sbrk+0x64>)
8000912: 681b ldr r3, [r3, #0]
8000914: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8000916: 4b07 ldr r3, [pc, #28] ; (8000934 <_sbrk+0x64>)
8000918: 681a ldr r2, [r3, #0]
800091a: 687b ldr r3, [r7, #4]
800091c: 18d2 adds r2, r2, r3
800091e: 4b05 ldr r3, [pc, #20] ; (8000934 <_sbrk+0x64>)
8000920: 601a str r2, [r3, #0]
return (void *)prev_heap_end;
8000922: 68fb ldr r3, [r7, #12]
}
8000924: 0018 movs r0, r3
8000926: 46bd mov sp, r7
8000928: b006 add sp, #24
800092a: bd80 pop {r7, pc}
800092c: 20001000 .word 0x20001000
8000930: 00000400 .word 0x00000400
8000934: 2000008c .word 0x2000008c
8000938: 200000f0 .word 0x200000f0
0800093c <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
800093c: b580 push {r7, lr}
800093e: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
8000940: 46c0 nop ; (mov r8, r8)
8000942: 46bd mov sp, r7
8000944: bd80 pop {r7, pc}
...
08000948 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000948: 480d ldr r0, [pc, #52] ; (8000980 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
800094a: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800094c: 480d ldr r0, [pc, #52] ; (8000984 <LoopForever+0x6>)
ldr r1, =_edata
800094e: 490e ldr r1, [pc, #56] ; (8000988 <LoopForever+0xa>)
ldr r2, =_sidata
8000950: 4a0e ldr r2, [pc, #56] ; (800098c <LoopForever+0xe>)
movs r3, #0
8000952: 2300 movs r3, #0
b LoopCopyDataInit
8000954: e002 b.n 800095c <LoopCopyDataInit>
08000956 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000956: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000958: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800095a: 3304 adds r3, #4
0800095c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800095c: 18c4 adds r4, r0, r3
cmp r4, r1
800095e: 428c cmp r4, r1
bcc CopyDataInit
8000960: d3f9 bcc.n 8000956 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000962: 4a0b ldr r2, [pc, #44] ; (8000990 <LoopForever+0x12>)
ldr r4, =_ebss
8000964: 4c0b ldr r4, [pc, #44] ; (8000994 <LoopForever+0x16>)
movs r3, #0
8000966: 2300 movs r3, #0
b LoopFillZerobss
8000968: e001 b.n 800096e <LoopFillZerobss>
0800096a <FillZerobss>:
FillZerobss:
str r3, [r2]
800096a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800096c: 3204 adds r2, #4
0800096e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800096e: 42a2 cmp r2, r4
bcc FillZerobss
8000970: d3fb bcc.n 800096a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000972: f7ff ffe3 bl 800093c <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000976: f001 fbd3 bl 8002120 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800097a: f7ff fd6d bl 8000458 <main>
0800097e <LoopForever>:
LoopForever:
b LoopForever
800097e: e7fe b.n 800097e <LoopForever>
ldr r0, =_estack
8000980: 20001000 .word 0x20001000
ldr r0, =_sdata
8000984: 20000000 .word 0x20000000
ldr r1, =_edata
8000988: 20000070 .word 0x20000070
ldr r2, =_sidata
800098c: 080033c0 .word 0x080033c0
ldr r2, =_sbss
8000990: 20000070 .word 0x20000070
ldr r4, =_ebss
8000994: 200000f0 .word 0x200000f0
08000998 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000998: e7fe b.n 8000998 <ADC1_IRQHandler>
...
0800099c <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800099c: b580 push {r7, lr}
800099e: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80009a0: 4b07 ldr r3, [pc, #28] ; (80009c0 <HAL_Init+0x24>)
80009a2: 681a ldr r2, [r3, #0]
80009a4: 4b06 ldr r3, [pc, #24] ; (80009c0 <HAL_Init+0x24>)
80009a6: 2110 movs r1, #16
80009a8: 430a orrs r2, r1
80009aa: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80009ac: 2003 movs r0, #3
80009ae: f000 f809 bl 80009c4 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80009b2: f7ff fe85 bl 80006c0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80009b6: 2300 movs r3, #0
}
80009b8: 0018 movs r0, r3
80009ba: 46bd mov sp, r7
80009bc: bd80 pop {r7, pc}
80009be: 46c0 nop ; (mov r8, r8)
80009c0: 40022000 .word 0x40022000
080009c4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80009c4: b590 push {r4, r7, lr}
80009c6: b083 sub sp, #12
80009c8: af00 add r7, sp, #0
80009ca: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80009cc: 4b14 ldr r3, [pc, #80] ; (8000a20 <HAL_InitTick+0x5c>)
80009ce: 681c ldr r4, [r3, #0]
80009d0: 4b14 ldr r3, [pc, #80] ; (8000a24 <HAL_InitTick+0x60>)
80009d2: 781b ldrb r3, [r3, #0]
80009d4: 0019 movs r1, r3
80009d6: 23fa movs r3, #250 ; 0xfa
80009d8: 0098 lsls r0, r3, #2
80009da: f7ff fb9f bl 800011c <__udivsi3>
80009de: 0003 movs r3, r0
80009e0: 0019 movs r1, r3
80009e2: 0020 movs r0, r4
80009e4: f7ff fb9a bl 800011c <__udivsi3>
80009e8: 0003 movs r3, r0
80009ea: 0018 movs r0, r3
80009ec: f000 fb17 bl 800101e <HAL_SYSTICK_Config>
80009f0: 1e03 subs r3, r0, #0
80009f2: d001 beq.n 80009f8 <HAL_InitTick+0x34>
{
return HAL_ERROR;
80009f4: 2301 movs r3, #1
80009f6: e00f b.n 8000a18 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80009f8: 687b ldr r3, [r7, #4]
80009fa: 2b03 cmp r3, #3
80009fc: d80b bhi.n 8000a16 <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80009fe: 6879 ldr r1, [r7, #4]
8000a00: 2301 movs r3, #1
8000a02: 425b negs r3, r3
8000a04: 2200 movs r2, #0
8000a06: 0018 movs r0, r3
8000a08: f000 faf4 bl 8000ff4 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000a0c: 4b06 ldr r3, [pc, #24] ; (8000a28 <HAL_InitTick+0x64>)
8000a0e: 687a ldr r2, [r7, #4]
8000a10: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000a12: 2300 movs r3, #0
8000a14: e000 b.n 8000a18 <HAL_InitTick+0x54>
return HAL_ERROR;
8000a16: 2301 movs r3, #1
}
8000a18: 0018 movs r0, r3
8000a1a: 46bd mov sp, r7
8000a1c: b003 add sp, #12
8000a1e: bd90 pop {r4, r7, pc}
8000a20: 20000000 .word 0x20000000
8000a24: 20000008 .word 0x20000008
8000a28: 20000004 .word 0x20000004
08000a2c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000a2c: b580 push {r7, lr}
8000a2e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000a30: 4b05 ldr r3, [pc, #20] ; (8000a48 <HAL_IncTick+0x1c>)
8000a32: 781b ldrb r3, [r3, #0]
8000a34: 001a movs r2, r3
8000a36: 4b05 ldr r3, [pc, #20] ; (8000a4c <HAL_IncTick+0x20>)
8000a38: 681b ldr r3, [r3, #0]
8000a3a: 18d2 adds r2, r2, r3
8000a3c: 4b03 ldr r3, [pc, #12] ; (8000a4c <HAL_IncTick+0x20>)
8000a3e: 601a str r2, [r3, #0]
}
8000a40: 46c0 nop ; (mov r8, r8)
8000a42: 46bd mov sp, r7
8000a44: bd80 pop {r7, pc}
8000a46: 46c0 nop ; (mov r8, r8)
8000a48: 20000008 .word 0x20000008
8000a4c: 200000d8 .word 0x200000d8
08000a50 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000a50: b580 push {r7, lr}
8000a52: af00 add r7, sp, #0
return uwTick;
8000a54: 4b02 ldr r3, [pc, #8] ; (8000a60 <HAL_GetTick+0x10>)
8000a56: 681b ldr r3, [r3, #0]
}
8000a58: 0018 movs r0, r3
8000a5a: 46bd mov sp, r7
8000a5c: bd80 pop {r7, pc}
8000a5e: 46c0 nop ; (mov r8, r8)
8000a60: 200000d8 .word 0x200000d8
08000a64 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8000a64: b580 push {r7, lr}
8000a66: b084 sub sp, #16
8000a68: af00 add r7, sp, #0
8000a6a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000a6c: 230f movs r3, #15
8000a6e: 18fb adds r3, r7, r3
8000a70: 2200 movs r2, #0
8000a72: 701a strb r2, [r3, #0]
uint32_t tmpCFGR1 = 0U;
8000a74: 2300 movs r3, #0
8000a76: 60bb str r3, [r7, #8]
/* Check ADC handle */
if(hadc == NULL)
8000a78: 687b ldr r3, [r7, #4]
8000a7a: 2b00 cmp r3, #0
8000a7c: d101 bne.n 8000a82 <HAL_ADC_Init+0x1e>
{
return HAL_ERROR;
8000a7e: 2301 movs r3, #1
8000a80: e125 b.n 8000cce <HAL_ADC_Init+0x26a>
/* Refer to header of this file for more details on clock enabling procedure*/
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
/* - ADC voltage regulator enable */
if (hadc->State == HAL_ADC_STATE_RESET)
8000a82: 687b ldr r3, [r7, #4]
8000a84: 6b9b ldr r3, [r3, #56] ; 0x38
8000a86: 2b00 cmp r3, #0
8000a88: d10a bne.n 8000aa0 <HAL_ADC_Init+0x3c>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8000a8a: 687b ldr r3, [r7, #4]
8000a8c: 2200 movs r2, #0
8000a8e: 63da str r2, [r3, #60] ; 0x3c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8000a90: 687b ldr r3, [r7, #4]
8000a92: 2234 movs r2, #52 ; 0x34
8000a94: 2100 movs r1, #0
8000a96: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8000a98: 687b ldr r3, [r7, #4]
8000a9a: 0018 movs r0, r3
8000a9c: f7ff fe34 bl 8000708 <HAL_ADC_MspInit>
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
/* and if there is no conversion on going on regular group (ADC can be */
/* enabled anyway, in case of call of this function to update a parameter */
/* on the fly). */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8000aa0: 687b ldr r3, [r7, #4]
8000aa2: 6b9b ldr r3, [r3, #56] ; 0x38
8000aa4: 2210 movs r2, #16
8000aa6: 4013 ands r3, r2
8000aa8: d000 beq.n 8000aac <HAL_ADC_Init+0x48>
8000aaa: e103 b.n 8000cb4 <HAL_ADC_Init+0x250>
8000aac: 230f movs r3, #15
8000aae: 18fb adds r3, r7, r3
8000ab0: 781b ldrb r3, [r3, #0]
8000ab2: 2b00 cmp r3, #0
8000ab4: d000 beq.n 8000ab8 <HAL_ADC_Init+0x54>
8000ab6: e0fd b.n 8000cb4 <HAL_ADC_Init+0x250>
(tmp_hal_status == HAL_OK) &&
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
8000ab8: 687b ldr r3, [r7, #4]
8000aba: 681b ldr r3, [r3, #0]
8000abc: 689b ldr r3, [r3, #8]
8000abe: 2204 movs r2, #4
8000ac0: 4013 ands r3, r2
(tmp_hal_status == HAL_OK) &&
8000ac2: d000 beq.n 8000ac6 <HAL_ADC_Init+0x62>
8000ac4: e0f6 b.n 8000cb4 <HAL_ADC_Init+0x250>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000ac6: 687b ldr r3, [r7, #4]
8000ac8: 6b9b ldr r3, [r3, #56] ; 0x38
8000aca: 4a83 ldr r2, [pc, #524] ; (8000cd8 <HAL_ADC_Init+0x274>)
8000acc: 4013 ands r3, r2
8000ace: 2202 movs r2, #2
8000ad0: 431a orrs r2, r3
8000ad2: 687b ldr r3, [r7, #4]
8000ad4: 639a str r2, [r3, #56] ; 0x38
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - ADC clock mode */
/* - ADC clock prescaler */
/* - ADC resolution */
if (ADC_IS_ENABLE(hadc) == RESET)
8000ad6: 687b ldr r3, [r7, #4]
8000ad8: 681b ldr r3, [r3, #0]
8000ada: 689b ldr r3, [r3, #8]
8000adc: 2203 movs r2, #3
8000ade: 4013 ands r3, r2
8000ae0: 2b01 cmp r3, #1
8000ae2: d112 bne.n 8000b0a <HAL_ADC_Init+0xa6>
8000ae4: 687b ldr r3, [r7, #4]
8000ae6: 681b ldr r3, [r3, #0]
8000ae8: 681b ldr r3, [r3, #0]
8000aea: 2201 movs r2, #1
8000aec: 4013 ands r3, r2
8000aee: 2b01 cmp r3, #1
8000af0: d009 beq.n 8000b06 <HAL_ADC_Init+0xa2>
8000af2: 687b ldr r3, [r7, #4]
8000af4: 681b ldr r3, [r3, #0]
8000af6: 68da ldr r2, [r3, #12]
8000af8: 2380 movs r3, #128 ; 0x80
8000afa: 021b lsls r3, r3, #8
8000afc: 401a ands r2, r3
8000afe: 2380 movs r3, #128 ; 0x80
8000b00: 021b lsls r3, r3, #8
8000b02: 429a cmp r2, r3
8000b04: d101 bne.n 8000b0a <HAL_ADC_Init+0xa6>
8000b06: 2301 movs r3, #1
8000b08: e000 b.n 8000b0c <HAL_ADC_Init+0xa8>
8000b0a: 2300 movs r3, #0
8000b0c: 2b00 cmp r3, #0
8000b0e: d116 bne.n 8000b3e <HAL_ADC_Init+0xda>
/* parameters): */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() ) */
/* Configuration of ADC resolution */
MODIFY_REG(hadc->Instance->CFGR1,
8000b10: 687b ldr r3, [r7, #4]
8000b12: 681b ldr r3, [r3, #0]
8000b14: 68db ldr r3, [r3, #12]
8000b16: 2218 movs r2, #24
8000b18: 4393 bics r3, r2
8000b1a: 0019 movs r1, r3
8000b1c: 687b ldr r3, [r7, #4]
8000b1e: 689a ldr r2, [r3, #8]
8000b20: 687b ldr r3, [r7, #4]
8000b22: 681b ldr r3, [r3, #0]
8000b24: 430a orrs r2, r1
8000b26: 60da str r2, [r3, #12]
ADC_CFGR1_RES ,
hadc->Init.Resolution );
/* Configuration of ADC clock mode: clock source AHB or HSI with */
/* selectable prescaler */
MODIFY_REG(hadc->Instance->CFGR2 ,
8000b28: 687b ldr r3, [r7, #4]
8000b2a: 681b ldr r3, [r3, #0]
8000b2c: 691b ldr r3, [r3, #16]
8000b2e: 009b lsls r3, r3, #2
8000b30: 0899 lsrs r1, r3, #2
8000b32: 687b ldr r3, [r7, #4]
8000b34: 685a ldr r2, [r3, #4]
8000b36: 687b ldr r3, [r7, #4]
8000b38: 681b ldr r3, [r3, #0]
8000b3a: 430a orrs r2, r1
8000b3c: 611a str r2, [r3, #16]
/* - external trigger polarity */
/* - data alignment */
/* - resolution */
/* - scan direction */
/* - DMA continuous request */
hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN |
8000b3e: 687b ldr r3, [r7, #4]
8000b40: 681b ldr r3, [r3, #0]
8000b42: 68da ldr r2, [r3, #12]
8000b44: 687b ldr r3, [r7, #4]
8000b46: 681b ldr r3, [r3, #0]
8000b48: 4964 ldr r1, [pc, #400] ; (8000cdc <HAL_ADC_Init+0x278>)
8000b4a: 400a ands r2, r1
8000b4c: 60da str r2, [r3, #12]
ADC_CFGR1_EXTEN |
ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG );
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000b4e: 687b ldr r3, [r7, #4]
8000b50: 7e1b ldrb r3, [r3, #24]
8000b52: 039a lsls r2, r3, #14
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8000b54: 687b ldr r3, [r7, #4]
8000b56: 7e5b ldrb r3, [r3, #25]
8000b58: 03db lsls r3, r3, #15
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000b5a: 431a orrs r2, r3
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000b5c: 687b ldr r3, [r7, #4]
8000b5e: 7e9b ldrb r3, [r3, #26]
8000b60: 035b lsls r3, r3, #13
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8000b62: 431a orrs r2, r3
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8000b64: 687b ldr r3, [r7, #4]
8000b66: 6a9b ldr r3, [r3, #40] ; 0x28
8000b68: 2b01 cmp r3, #1
8000b6a: d002 beq.n 8000b72 <HAL_ADC_Init+0x10e>
8000b6c: 2380 movs r3, #128 ; 0x80
8000b6e: 015b lsls r3, r3, #5
8000b70: e000 b.n 8000b74 <HAL_ADC_Init+0x110>
8000b72: 2300 movs r3, #0
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000b74: 431a orrs r2, r3
hadc->Init.DataAlign |
8000b76: 687b ldr r3, [r7, #4]
8000b78: 68db ldr r3, [r3, #12]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8000b7a: 431a orrs r2, r3
ADC_SCANDIR(hadc->Init.ScanConvMode) |
8000b7c: 687b ldr r3, [r7, #4]
8000b7e: 691b ldr r3, [r3, #16]
8000b80: 2b02 cmp r3, #2
8000b82: d101 bne.n 8000b88 <HAL_ADC_Init+0x124>
8000b84: 2304 movs r3, #4
8000b86: e000 b.n 8000b8a <HAL_ADC_Init+0x126>
8000b88: 2300 movs r3, #0
hadc->Init.DataAlign |
8000b8a: 431a orrs r2, r3
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
8000b8c: 687b ldr r3, [r7, #4]
8000b8e: 2124 movs r1, #36 ; 0x24
8000b90: 5c5b ldrb r3, [r3, r1]
8000b92: 005b lsls r3, r3, #1
ADC_SCANDIR(hadc->Init.ScanConvMode) |
8000b94: 4313 orrs r3, r2
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000b96: 68ba ldr r2, [r7, #8]
8000b98: 4313 orrs r3, r2
8000b9a: 60bb str r3, [r7, #8]
/* Enable discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8000b9c: 687b ldr r3, [r7, #4]
8000b9e: 7edb ldrb r3, [r3, #27]
8000ba0: 2b01 cmp r3, #1
8000ba2: d115 bne.n 8000bd0 <HAL_ADC_Init+0x16c>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8000ba4: 687b ldr r3, [r7, #4]
8000ba6: 7e9b ldrb r3, [r3, #26]
8000ba8: 2b00 cmp r3, #0
8000baa: d105 bne.n 8000bb8 <HAL_ADC_Init+0x154>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
8000bac: 68bb ldr r3, [r7, #8]
8000bae: 2280 movs r2, #128 ; 0x80
8000bb0: 0252 lsls r2, r2, #9
8000bb2: 4313 orrs r3, r2
8000bb4: 60bb str r3, [r7, #8]
8000bb6: e00b b.n 8000bd0 <HAL_ADC_Init+0x16c>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000bb8: 687b ldr r3, [r7, #4]
8000bba: 6b9b ldr r3, [r3, #56] ; 0x38
8000bbc: 2220 movs r2, #32
8000bbe: 431a orrs r2, r3
8000bc0: 687b ldr r3, [r7, #4]
8000bc2: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000bc4: 687b ldr r3, [r7, #4]
8000bc6: 6bdb ldr r3, [r3, #60] ; 0x3c
8000bc8: 2201 movs r2, #1
8000bca: 431a orrs r2, r3
8000bcc: 687b ldr r3, [r7, #4]
8000bce: 63da str r2, [r3, #60] ; 0x3c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8000bd0: 687b ldr r3, [r7, #4]
8000bd2: 69da ldr r2, [r3, #28]
8000bd4: 23c2 movs r3, #194 ; 0xc2
8000bd6: 33ff adds r3, #255 ; 0xff
8000bd8: 429a cmp r2, r3
8000bda: d007 beq.n 8000bec <HAL_ADC_Init+0x188>
{
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000bdc: 687b ldr r3, [r7, #4]
8000bde: 69da ldr r2, [r3, #28]
hadc->Init.ExternalTrigConvEdge );
8000be0: 687b ldr r3, [r7, #4]
8000be2: 6a1b ldr r3, [r3, #32]
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000be4: 4313 orrs r3, r2
8000be6: 68ba ldr r2, [r7, #8]
8000be8: 4313 orrs r3, r2
8000bea: 60bb str r3, [r7, #8]
}
/* Update ADC configuration register with previous settings */
hadc->Instance->CFGR1 |= tmpCFGR1;
8000bec: 687b ldr r3, [r7, #4]
8000bee: 681b ldr r3, [r3, #0]
8000bf0: 68d9 ldr r1, [r3, #12]
8000bf2: 687b ldr r3, [r7, #4]
8000bf4: 681b ldr r3, [r3, #0]
8000bf6: 68ba ldr r2, [r7, #8]
8000bf8: 430a orrs r2, r1
8000bfa: 60da str r2, [r3, #12]
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function if parameter */
/* "SamplingTimeCommon" has been set to a valid sampling time. */
/* Otherwise, sampling time is set into ADC channel initialization */
/* structure with parameter "SamplingTime" (obsolete). */
if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000bfc: 687b ldr r3, [r7, #4]
8000bfe: 6ada ldr r2, [r3, #44] ; 0x2c
8000c00: 2380 movs r3, #128 ; 0x80
8000c02: 055b lsls r3, r3, #21
8000c04: 429a cmp r2, r3
8000c06: d01b beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c08: 687b ldr r3, [r7, #4]
8000c0a: 6adb ldr r3, [r3, #44] ; 0x2c
8000c0c: 2b01 cmp r3, #1
8000c0e: d017 beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c10: 687b ldr r3, [r7, #4]
8000c12: 6adb ldr r3, [r3, #44] ; 0x2c
8000c14: 2b02 cmp r3, #2
8000c16: d013 beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 6adb ldr r3, [r3, #44] ; 0x2c
8000c1c: 2b03 cmp r3, #3
8000c1e: d00f beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c20: 687b ldr r3, [r7, #4]
8000c22: 6adb ldr r3, [r3, #44] ; 0x2c
8000c24: 2b04 cmp r3, #4
8000c26: d00b beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c28: 687b ldr r3, [r7, #4]
8000c2a: 6adb ldr r3, [r3, #44] ; 0x2c
8000c2c: 2b05 cmp r3, #5
8000c2e: d007 beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c30: 687b ldr r3, [r7, #4]
8000c32: 6adb ldr r3, [r3, #44] ; 0x2c
8000c34: 2b06 cmp r3, #6
8000c36: d003 beq.n 8000c40 <HAL_ADC_Init+0x1dc>
8000c38: 687b ldr r3, [r7, #4]
8000c3a: 6adb ldr r3, [r3, #44] ; 0x2c
8000c3c: 2b07 cmp r3, #7
8000c3e: d112 bne.n 8000c66 <HAL_ADC_Init+0x202>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000c40: 687b ldr r3, [r7, #4]
8000c42: 681b ldr r3, [r3, #0]
8000c44: 695a ldr r2, [r3, #20]
8000c46: 687b ldr r3, [r7, #4]
8000c48: 681b ldr r3, [r3, #0]
8000c4a: 2107 movs r1, #7
8000c4c: 438a bics r2, r1
8000c4e: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
8000c50: 687b ldr r3, [r7, #4]
8000c52: 681b ldr r3, [r3, #0]
8000c54: 6959 ldr r1, [r3, #20]
8000c56: 687b ldr r3, [r7, #4]
8000c58: 6adb ldr r3, [r3, #44] ; 0x2c
8000c5a: 2207 movs r2, #7
8000c5c: 401a ands r2, r3
8000c5e: 687b ldr r3, [r7, #4]
8000c60: 681b ldr r3, [r3, #0]
8000c62: 430a orrs r2, r1
8000c64: 615a str r2, [r3, #20]
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
/* set into separate dedicated function, and bits of ADC resolution set */
/* out of temporary variable 'tmpCFGR1'). */
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000c66: 687b ldr r3, [r7, #4]
8000c68: 681b ldr r3, [r3, #0]
8000c6a: 68db ldr r3, [r3, #12]
8000c6c: 4a1c ldr r2, [pc, #112] ; (8000ce0 <HAL_ADC_Init+0x27c>)
8000c6e: 4013 ands r3, r2
8000c70: 68ba ldr r2, [r7, #8]
8000c72: 429a cmp r2, r3
8000c74: d10b bne.n 8000c8e <HAL_ADC_Init+0x22a>
== tmpCFGR1)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8000c76: 687b ldr r3, [r7, #4]
8000c78: 2200 movs r2, #0
8000c7a: 63da str r2, [r3, #60] ; 0x3c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000c7c: 687b ldr r3, [r7, #4]
8000c7e: 6b9b ldr r3, [r3, #56] ; 0x38
8000c80: 2203 movs r2, #3
8000c82: 4393 bics r3, r2
8000c84: 2201 movs r2, #1
8000c86: 431a orrs r2, r3
8000c88: 687b ldr r3, [r7, #4]
8000c8a: 639a str r2, [r3, #56] ; 0x38
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000c8c: e01c b.n 8000cc8 <HAL_ADC_Init+0x264>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8000c8e: 687b ldr r3, [r7, #4]
8000c90: 6b9b ldr r3, [r3, #56] ; 0x38
8000c92: 2212 movs r2, #18
8000c94: 4393 bics r3, r2
8000c96: 2210 movs r2, #16
8000c98: 431a orrs r2, r3
8000c9a: 687b ldr r3, [r7, #4]
8000c9c: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000c9e: 687b ldr r3, [r7, #4]
8000ca0: 6bdb ldr r3, [r3, #60] ; 0x3c
8000ca2: 2201 movs r2, #1
8000ca4: 431a orrs r2, r3
8000ca6: 687b ldr r3, [r7, #4]
8000ca8: 63da str r2, [r3, #60] ; 0x3c
tmp_hal_status = HAL_ERROR;
8000caa: 230f movs r3, #15
8000cac: 18fb adds r3, r7, r3
8000cae: 2201 movs r2, #1
8000cb0: 701a strb r2, [r3, #0]
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000cb2: e009 b.n 8000cc8 <HAL_ADC_Init+0x264>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000cb4: 687b ldr r3, [r7, #4]
8000cb6: 6b9b ldr r3, [r3, #56] ; 0x38
8000cb8: 2210 movs r2, #16
8000cba: 431a orrs r2, r3
8000cbc: 687b ldr r3, [r7, #4]
8000cbe: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
8000cc0: 230f movs r3, #15
8000cc2: 18fb adds r3, r7, r3
8000cc4: 2201 movs r2, #1
8000cc6: 701a strb r2, [r3, #0]
}
/* Return function status */
return tmp_hal_status;
8000cc8: 230f movs r3, #15
8000cca: 18fb adds r3, r7, r3
8000ccc: 781b ldrb r3, [r3, #0]
}
8000cce: 0018 movs r0, r3
8000cd0: 46bd mov sp, r7
8000cd2: b004 add sp, #16
8000cd4: bd80 pop {r7, pc}
8000cd6: 46c0 nop ; (mov r8, r8)
8000cd8: fffffefd .word 0xfffffefd
8000cdc: fffe0219 .word 0xfffe0219
8000ce0: 833fffe7 .word 0x833fffe7
08000ce4 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8000ce4: b580 push {r7, lr}
8000ce6: b084 sub sp, #16
8000ce8: af00 add r7, sp, #0
8000cea: 6078 str r0, [r7, #4]
8000cec: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000cee: 230f movs r3, #15
8000cf0: 18fb adds r3, r7, r3
8000cf2: 2200 movs r2, #0
8000cf4: 701a strb r2, [r3, #0]
__IO uint32_t wait_loop_index = 0U;
8000cf6: 2300 movs r3, #0
8000cf8: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_RANK(sConfig->Rank));
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000cfa: 687b ldr r3, [r7, #4]
8000cfc: 6ada ldr r2, [r3, #44] ; 0x2c
8000cfe: 2380 movs r3, #128 ; 0x80
8000d00: 055b lsls r3, r3, #21
8000d02: 429a cmp r2, r3
8000d04: d011 beq.n 8000d2a <HAL_ADC_ConfigChannel+0x46>
8000d06: 687b ldr r3, [r7, #4]
8000d08: 6adb ldr r3, [r3, #44] ; 0x2c
8000d0a: 2b01 cmp r3, #1
8000d0c: d00d beq.n 8000d2a <HAL_ADC_ConfigChannel+0x46>
8000d0e: 687b ldr r3, [r7, #4]
8000d10: 6adb ldr r3, [r3, #44] ; 0x2c
8000d12: 2b02 cmp r3, #2
8000d14: d009 beq.n 8000d2a <HAL_ADC_ConfigChannel+0x46>
8000d16: 687b ldr r3, [r7, #4]
8000d18: 6adb ldr r3, [r3, #44] ; 0x2c
8000d1a: 2b03 cmp r3, #3
8000d1c: d005 beq.n 8000d2a <HAL_ADC_ConfigChannel+0x46>
8000d1e: 687b ldr r3, [r7, #4]
8000d20: 6adb ldr r3, [r3, #44] ; 0x2c
8000d22: 2b04 cmp r3, #4
8000d24: d001 beq.n 8000d2a <HAL_ADC_ConfigChannel+0x46>
8000d26: 687b ldr r3, [r7, #4]
8000d28: 6adb ldr r3, [r3, #44] ; 0x2c
{
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
}
/* Process locked */
__HAL_LOCK(hadc);
8000d2a: 687b ldr r3, [r7, #4]
8000d2c: 2234 movs r2, #52 ; 0x34
8000d2e: 5c9b ldrb r3, [r3, r2]
8000d30: 2b01 cmp r3, #1
8000d32: d101 bne.n 8000d38 <HAL_ADC_ConfigChannel+0x54>
8000d34: 2302 movs r3, #2
8000d36: e0bb b.n 8000eb0 <HAL_ADC_ConfigChannel+0x1cc>
8000d38: 687b ldr r3, [r7, #4]
8000d3a: 2234 movs r2, #52 ; 0x34
8000d3c: 2101 movs r1, #1
8000d3e: 5499 strb r1, [r3, r2]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8000d40: 687b ldr r3, [r7, #4]
8000d42: 681b ldr r3, [r3, #0]
8000d44: 689b ldr r3, [r3, #8]
8000d46: 2204 movs r2, #4
8000d48: 4013 ands r3, r2
8000d4a: d000 beq.n 8000d4e <HAL_ADC_ConfigChannel+0x6a>
8000d4c: e09f b.n 8000e8e <HAL_ADC_ConfigChannel+0x1aa>
{
/* Configure channel: depending on rank setting, add it or remove it from */
/* ADC conversion sequencer. */
if (sConfig->Rank != ADC_RANK_NONE)
8000d4e: 683b ldr r3, [r7, #0]
8000d50: 685b ldr r3, [r3, #4]
8000d52: 4a59 ldr r2, [pc, #356] ; (8000eb8 <HAL_ADC_ConfigChannel+0x1d4>)
8000d54: 4293 cmp r3, r2
8000d56: d100 bne.n 8000d5a <HAL_ADC_ConfigChannel+0x76>
8000d58: e077 b.n 8000e4a <HAL_ADC_ConfigChannel+0x166>
{
/* Regular sequence configuration */
/* Set the channel selection register from the selected channel */
hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
8000d5a: 687b ldr r3, [r7, #4]
8000d5c: 681b ldr r3, [r3, #0]
8000d5e: 6a99 ldr r1, [r3, #40] ; 0x28
8000d60: 683b ldr r3, [r7, #0]
8000d62: 681b ldr r3, [r3, #0]
8000d64: 2201 movs r2, #1
8000d66: 409a lsls r2, r3
8000d68: 687b ldr r3, [r7, #4]
8000d6a: 681b ldr r3, [r3, #0]
8000d6c: 430a orrs r2, r1
8000d6e: 629a str r2, [r3, #40] ; 0x28
/* Channel sampling time configuration */
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function with */
/* parameter "SamplingTime" (obsolete) only if not already set into */
/* ADC initialization structure with parameter "SamplingTimeCommon". */
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000d70: 687b ldr r3, [r7, #4]
8000d72: 6ada ldr r2, [r3, #44] ; 0x2c
8000d74: 2380 movs r3, #128 ; 0x80
8000d76: 055b lsls r3, r3, #21
8000d78: 429a cmp r2, r3
8000d7a: d037 beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000d7c: 687b ldr r3, [r7, #4]
8000d7e: 6adb ldr r3, [r3, #44] ; 0x2c
8000d80: 2b01 cmp r3, #1
8000d82: d033 beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000d84: 687b ldr r3, [r7, #4]
8000d86: 6adb ldr r3, [r3, #44] ; 0x2c
8000d88: 2b02 cmp r3, #2
8000d8a: d02f beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000d8c: 687b ldr r3, [r7, #4]
8000d8e: 6adb ldr r3, [r3, #44] ; 0x2c
8000d90: 2b03 cmp r3, #3
8000d92: d02b beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000d94: 687b ldr r3, [r7, #4]
8000d96: 6adb ldr r3, [r3, #44] ; 0x2c
8000d98: 2b04 cmp r3, #4
8000d9a: d027 beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000d9c: 687b ldr r3, [r7, #4]
8000d9e: 6adb ldr r3, [r3, #44] ; 0x2c
8000da0: 2b05 cmp r3, #5
8000da2: d023 beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000da4: 687b ldr r3, [r7, #4]
8000da6: 6adb ldr r3, [r3, #44] ; 0x2c
8000da8: 2b06 cmp r3, #6
8000daa: d01f beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
8000dac: 687b ldr r3, [r7, #4]
8000dae: 6adb ldr r3, [r3, #44] ; 0x2c
8000db0: 2b07 cmp r3, #7
8000db2: d01b beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
{
/* Modify sampling time if needed (not needed in case of reoccurrence */
/* for several channels programmed consecutively into the sequencer) */
if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
8000db4: 683b ldr r3, [r7, #0]
8000db6: 689a ldr r2, [r3, #8]
8000db8: 687b ldr r3, [r7, #4]
8000dba: 681b ldr r3, [r3, #0]
8000dbc: 695b ldr r3, [r3, #20]
8000dbe: 2107 movs r1, #7
8000dc0: 400b ands r3, r1
8000dc2: 429a cmp r2, r3
8000dc4: d012 beq.n 8000dec <HAL_ADC_ConfigChannel+0x108>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000dc6: 687b ldr r3, [r7, #4]
8000dc8: 681b ldr r3, [r3, #0]
8000dca: 695a ldr r2, [r3, #20]
8000dcc: 687b ldr r3, [r7, #4]
8000dce: 681b ldr r3, [r3, #0]
8000dd0: 2107 movs r1, #7
8000dd2: 438a bics r2, r1
8000dd4: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 681b ldr r3, [r3, #0]
8000dda: 6959 ldr r1, [r3, #20]
8000ddc: 683b ldr r3, [r7, #0]
8000dde: 689b ldr r3, [r3, #8]
8000de0: 2207 movs r2, #7
8000de2: 401a ands r2, r3
8000de4: 687b ldr r3, [r7, #4]
8000de6: 681b ldr r3, [r3, #0]
8000de8: 430a orrs r2, r1
8000dea: 615a str r2, [r3, #20]
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000dec: 683b ldr r3, [r7, #0]
8000dee: 681b ldr r3, [r3, #0]
8000df0: 2b10 cmp r3, #16
8000df2: d003 beq.n 8000dfc <HAL_ADC_ConfigChannel+0x118>
8000df4: 683b ldr r3, [r7, #0]
8000df6: 681b ldr r3, [r3, #0]
8000df8: 2b11 cmp r3, #17
8000dfa: d152 bne.n 8000ea2 <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, enable Temp. sensor measurement path. */
/* If Channel_17 is selected, enable VREFINT measurement path. */
/* If Channel_18 is selected, enable VBAT measurement path. */
ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000dfc: 4b2f ldr r3, [pc, #188] ; (8000ebc <HAL_ADC_ConfigChannel+0x1d8>)
8000dfe: 6819 ldr r1, [r3, #0]
8000e00: 683b ldr r3, [r7, #0]
8000e02: 681b ldr r3, [r3, #0]
8000e04: 2b10 cmp r3, #16
8000e06: d102 bne.n 8000e0e <HAL_ADC_ConfigChannel+0x12a>
8000e08: 2380 movs r3, #128 ; 0x80
8000e0a: 041b lsls r3, r3, #16
8000e0c: e001 b.n 8000e12 <HAL_ADC_ConfigChannel+0x12e>
8000e0e: 2380 movs r3, #128 ; 0x80
8000e10: 03db lsls r3, r3, #15
8000e12: 4a2a ldr r2, [pc, #168] ; (8000ebc <HAL_ADC_ConfigChannel+0x1d8>)
8000e14: 430b orrs r3, r1
8000e16: 6013 str r3, [r2, #0]
/* If Temp. sensor is selected, wait for stabilization delay */
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8000e18: 683b ldr r3, [r7, #0]
8000e1a: 681b ldr r3, [r3, #0]
8000e1c: 2b10 cmp r3, #16
8000e1e: d140 bne.n 8000ea2 <HAL_ADC_ConfigChannel+0x1be>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8000e20: 4b27 ldr r3, [pc, #156] ; (8000ec0 <HAL_ADC_ConfigChannel+0x1dc>)
8000e22: 681b ldr r3, [r3, #0]
8000e24: 4927 ldr r1, [pc, #156] ; (8000ec4 <HAL_ADC_ConfigChannel+0x1e0>)
8000e26: 0018 movs r0, r3
8000e28: f7ff f978 bl 800011c <__udivsi3>
8000e2c: 0003 movs r3, r0
8000e2e: 001a movs r2, r3
8000e30: 0013 movs r3, r2
8000e32: 009b lsls r3, r3, #2
8000e34: 189b adds r3, r3, r2
8000e36: 005b lsls r3, r3, #1
8000e38: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000e3a: e002 b.n 8000e42 <HAL_ADC_ConfigChannel+0x15e>
{
wait_loop_index--;
8000e3c: 68bb ldr r3, [r7, #8]
8000e3e: 3b01 subs r3, #1
8000e40: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000e42: 68bb ldr r3, [r7, #8]
8000e44: 2b00 cmp r3, #0
8000e46: d1f9 bne.n 8000e3c <HAL_ADC_ConfigChannel+0x158>
8000e48: e02b b.n 8000ea2 <HAL_ADC_ConfigChannel+0x1be>
}
else
{
/* Regular sequence configuration */
/* Reset the channel selection register from the selected channel */
hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
8000e4a: 687b ldr r3, [r7, #4]
8000e4c: 681b ldr r3, [r3, #0]
8000e4e: 6a9a ldr r2, [r3, #40] ; 0x28
8000e50: 683b ldr r3, [r7, #0]
8000e52: 681b ldr r3, [r3, #0]
8000e54: 2101 movs r1, #1
8000e56: 4099 lsls r1, r3
8000e58: 000b movs r3, r1
8000e5a: 43d9 mvns r1, r3
8000e5c: 687b ldr r3, [r7, #4]
8000e5e: 681b ldr r3, [r3, #0]
8000e60: 400a ands r2, r1
8000e62: 629a str r2, [r3, #40] ; 0x28
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths disable: If internal channel selected, */
/* disable dedicated internal buffers and path. */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000e64: 683b ldr r3, [r7, #0]
8000e66: 681b ldr r3, [r3, #0]
8000e68: 2b10 cmp r3, #16
8000e6a: d003 beq.n 8000e74 <HAL_ADC_ConfigChannel+0x190>
8000e6c: 683b ldr r3, [r7, #0]
8000e6e: 681b ldr r3, [r3, #0]
8000e70: 2b11 cmp r3, #17
8000e72: d116 bne.n 8000ea2 <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, disable Temp. sensor measurement path. */
/* If Channel_17 is selected, disable VREFINT measurement path. */
/* If Channel_18 is selected, disable VBAT measurement path. */
ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000e74: 4b11 ldr r3, [pc, #68] ; (8000ebc <HAL_ADC_ConfigChannel+0x1d8>)
8000e76: 6819 ldr r1, [r3, #0]
8000e78: 683b ldr r3, [r7, #0]
8000e7a: 681b ldr r3, [r3, #0]
8000e7c: 2b10 cmp r3, #16
8000e7e: d101 bne.n 8000e84 <HAL_ADC_ConfigChannel+0x1a0>
8000e80: 4a11 ldr r2, [pc, #68] ; (8000ec8 <HAL_ADC_ConfigChannel+0x1e4>)
8000e82: e000 b.n 8000e86 <HAL_ADC_ConfigChannel+0x1a2>
8000e84: 4a11 ldr r2, [pc, #68] ; (8000ecc <HAL_ADC_ConfigChannel+0x1e8>)
8000e86: 4b0d ldr r3, [pc, #52] ; (8000ebc <HAL_ADC_ConfigChannel+0x1d8>)
8000e88: 400a ands r2, r1
8000e8a: 601a str r2, [r3, #0]
8000e8c: e009 b.n 8000ea2 <HAL_ADC_ConfigChannel+0x1be>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000e8e: 687b ldr r3, [r7, #4]
8000e90: 6b9b ldr r3, [r3, #56] ; 0x38
8000e92: 2220 movs r2, #32
8000e94: 431a orrs r2, r3
8000e96: 687b ldr r3, [r7, #4]
8000e98: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
8000e9a: 230f movs r3, #15
8000e9c: 18fb adds r3, r7, r3
8000e9e: 2201 movs r2, #1
8000ea0: 701a strb r2, [r3, #0]
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000ea2: 687b ldr r3, [r7, #4]
8000ea4: 2234 movs r2, #52 ; 0x34
8000ea6: 2100 movs r1, #0
8000ea8: 5499 strb r1, [r3, r2]
/* Return function status */
return tmp_hal_status;
8000eaa: 230f movs r3, #15
8000eac: 18fb adds r3, r7, r3
8000eae: 781b ldrb r3, [r3, #0]
}
8000eb0: 0018 movs r0, r3
8000eb2: 46bd mov sp, r7
8000eb4: b004 add sp, #16
8000eb6: bd80 pop {r7, pc}
8000eb8: 00001001 .word 0x00001001
8000ebc: 40012708 .word 0x40012708
8000ec0: 20000000 .word 0x20000000
8000ec4: 000f4240 .word 0x000f4240
8000ec8: ff7fffff .word 0xff7fffff
8000ecc: ffbfffff .word 0xffbfffff
08000ed0 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000ed0: b590 push {r4, r7, lr}
8000ed2: b083 sub sp, #12
8000ed4: af00 add r7, sp, #0
8000ed6: 0002 movs r2, r0
8000ed8: 6039 str r1, [r7, #0]
8000eda: 1dfb adds r3, r7, #7
8000edc: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8000ede: 1dfb adds r3, r7, #7
8000ee0: 781b ldrb r3, [r3, #0]
8000ee2: 2b7f cmp r3, #127 ; 0x7f
8000ee4: d828 bhi.n 8000f38 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000ee6: 4a2f ldr r2, [pc, #188] ; (8000fa4 <__NVIC_SetPriority+0xd4>)
8000ee8: 1dfb adds r3, r7, #7
8000eea: 781b ldrb r3, [r3, #0]
8000eec: b25b sxtb r3, r3
8000eee: 089b lsrs r3, r3, #2
8000ef0: 33c0 adds r3, #192 ; 0xc0
8000ef2: 009b lsls r3, r3, #2
8000ef4: 589b ldr r3, [r3, r2]
8000ef6: 1dfa adds r2, r7, #7
8000ef8: 7812 ldrb r2, [r2, #0]
8000efa: 0011 movs r1, r2
8000efc: 2203 movs r2, #3
8000efe: 400a ands r2, r1
8000f00: 00d2 lsls r2, r2, #3
8000f02: 21ff movs r1, #255 ; 0xff
8000f04: 4091 lsls r1, r2
8000f06: 000a movs r2, r1
8000f08: 43d2 mvns r2, r2
8000f0a: 401a ands r2, r3
8000f0c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000f0e: 683b ldr r3, [r7, #0]
8000f10: 019b lsls r3, r3, #6
8000f12: 22ff movs r2, #255 ; 0xff
8000f14: 401a ands r2, r3
8000f16: 1dfb adds r3, r7, #7
8000f18: 781b ldrb r3, [r3, #0]
8000f1a: 0018 movs r0, r3
8000f1c: 2303 movs r3, #3
8000f1e: 4003 ands r3, r0
8000f20: 00db lsls r3, r3, #3
8000f22: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000f24: 481f ldr r0, [pc, #124] ; (8000fa4 <__NVIC_SetPriority+0xd4>)
8000f26: 1dfb adds r3, r7, #7
8000f28: 781b ldrb r3, [r3, #0]
8000f2a: b25b sxtb r3, r3
8000f2c: 089b lsrs r3, r3, #2
8000f2e: 430a orrs r2, r1
8000f30: 33c0 adds r3, #192 ; 0xc0
8000f32: 009b lsls r3, r3, #2
8000f34: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000f36: e031 b.n 8000f9c <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000f38: 4a1b ldr r2, [pc, #108] ; (8000fa8 <__NVIC_SetPriority+0xd8>)
8000f3a: 1dfb adds r3, r7, #7
8000f3c: 781b ldrb r3, [r3, #0]
8000f3e: 0019 movs r1, r3
8000f40: 230f movs r3, #15
8000f42: 400b ands r3, r1
8000f44: 3b08 subs r3, #8
8000f46: 089b lsrs r3, r3, #2
8000f48: 3306 adds r3, #6
8000f4a: 009b lsls r3, r3, #2
8000f4c: 18d3 adds r3, r2, r3
8000f4e: 3304 adds r3, #4
8000f50: 681b ldr r3, [r3, #0]
8000f52: 1dfa adds r2, r7, #7
8000f54: 7812 ldrb r2, [r2, #0]
8000f56: 0011 movs r1, r2
8000f58: 2203 movs r2, #3
8000f5a: 400a ands r2, r1
8000f5c: 00d2 lsls r2, r2, #3
8000f5e: 21ff movs r1, #255 ; 0xff
8000f60: 4091 lsls r1, r2
8000f62: 000a movs r2, r1
8000f64: 43d2 mvns r2, r2
8000f66: 401a ands r2, r3
8000f68: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000f6a: 683b ldr r3, [r7, #0]
8000f6c: 019b lsls r3, r3, #6
8000f6e: 22ff movs r2, #255 ; 0xff
8000f70: 401a ands r2, r3
8000f72: 1dfb adds r3, r7, #7
8000f74: 781b ldrb r3, [r3, #0]
8000f76: 0018 movs r0, r3
8000f78: 2303 movs r3, #3
8000f7a: 4003 ands r3, r0
8000f7c: 00db lsls r3, r3, #3
8000f7e: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000f80: 4809 ldr r0, [pc, #36] ; (8000fa8 <__NVIC_SetPriority+0xd8>)
8000f82: 1dfb adds r3, r7, #7
8000f84: 781b ldrb r3, [r3, #0]
8000f86: 001c movs r4, r3
8000f88: 230f movs r3, #15
8000f8a: 4023 ands r3, r4
8000f8c: 3b08 subs r3, #8
8000f8e: 089b lsrs r3, r3, #2
8000f90: 430a orrs r2, r1
8000f92: 3306 adds r3, #6
8000f94: 009b lsls r3, r3, #2
8000f96: 18c3 adds r3, r0, r3
8000f98: 3304 adds r3, #4
8000f9a: 601a str r2, [r3, #0]
}
8000f9c: 46c0 nop ; (mov r8, r8)
8000f9e: 46bd mov sp, r7
8000fa0: b003 add sp, #12
8000fa2: bd90 pop {r4, r7, pc}
8000fa4: e000e100 .word 0xe000e100
8000fa8: e000ed00 .word 0xe000ed00
08000fac <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000fac: b580 push {r7, lr}
8000fae: b082 sub sp, #8
8000fb0: af00 add r7, sp, #0
8000fb2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000fb4: 687b ldr r3, [r7, #4]
8000fb6: 1e5a subs r2, r3, #1
8000fb8: 2380 movs r3, #128 ; 0x80
8000fba: 045b lsls r3, r3, #17
8000fbc: 429a cmp r2, r3
8000fbe: d301 bcc.n 8000fc4 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8000fc0: 2301 movs r3, #1
8000fc2: e010 b.n 8000fe6 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000fc4: 4b0a ldr r3, [pc, #40] ; (8000ff0 <SysTick_Config+0x44>)
8000fc6: 687a ldr r2, [r7, #4]
8000fc8: 3a01 subs r2, #1
8000fca: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000fcc: 2301 movs r3, #1
8000fce: 425b negs r3, r3
8000fd0: 2103 movs r1, #3
8000fd2: 0018 movs r0, r3
8000fd4: f7ff ff7c bl 8000ed0 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000fd8: 4b05 ldr r3, [pc, #20] ; (8000ff0 <SysTick_Config+0x44>)
8000fda: 2200 movs r2, #0
8000fdc: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000fde: 4b04 ldr r3, [pc, #16] ; (8000ff0 <SysTick_Config+0x44>)
8000fe0: 2207 movs r2, #7
8000fe2: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000fe4: 2300 movs r3, #0
}
8000fe6: 0018 movs r0, r3
8000fe8: 46bd mov sp, r7
8000fea: b002 add sp, #8
8000fec: bd80 pop {r7, pc}
8000fee: 46c0 nop ; (mov r8, r8)
8000ff0: e000e010 .word 0xe000e010
08000ff4 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ff4: b580 push {r7, lr}
8000ff6: b084 sub sp, #16
8000ff8: af00 add r7, sp, #0
8000ffa: 60b9 str r1, [r7, #8]
8000ffc: 607a str r2, [r7, #4]
8000ffe: 210f movs r1, #15
8001000: 187b adds r3, r7, r1
8001002: 1c02 adds r2, r0, #0
8001004: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
8001006: 68ba ldr r2, [r7, #8]
8001008: 187b adds r3, r7, r1
800100a: 781b ldrb r3, [r3, #0]
800100c: b25b sxtb r3, r3
800100e: 0011 movs r1, r2
8001010: 0018 movs r0, r3
8001012: f7ff ff5d bl 8000ed0 <__NVIC_SetPriority>
}
8001016: 46c0 nop ; (mov r8, r8)
8001018: 46bd mov sp, r7
800101a: b004 add sp, #16
800101c: bd80 pop {r7, pc}
0800101e <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800101e: b580 push {r7, lr}
8001020: b082 sub sp, #8
8001022: af00 add r7, sp, #0
8001024: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001026: 687b ldr r3, [r7, #4]
8001028: 0018 movs r0, r3
800102a: f7ff ffbf bl 8000fac <SysTick_Config>
800102e: 0003 movs r3, r0
}
8001030: 0018 movs r0, r3
8001032: 46bd mov sp, r7
8001034: b002 add sp, #8
8001036: bd80 pop {r7, pc}
08001038 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001038: b580 push {r7, lr}
800103a: b086 sub sp, #24
800103c: af00 add r7, sp, #0
800103e: 6078 str r0, [r7, #4]
8001040: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001042: 2300 movs r3, #0
8001044: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001046: e14f b.n 80012e8 <HAL_GPIO_Init+0x2b0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001048: 683b ldr r3, [r7, #0]
800104a: 681b ldr r3, [r3, #0]
800104c: 2101 movs r1, #1
800104e: 697a ldr r2, [r7, #20]
8001050: 4091 lsls r1, r2
8001052: 000a movs r2, r1
8001054: 4013 ands r3, r2
8001056: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001058: 68fb ldr r3, [r7, #12]
800105a: 2b00 cmp r3, #0
800105c: d100 bne.n 8001060 <HAL_GPIO_Init+0x28>
800105e: e140 b.n 80012e2 <HAL_GPIO_Init+0x2aa>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001060: 683b ldr r3, [r7, #0]
8001062: 685b ldr r3, [r3, #4]
8001064: 2203 movs r2, #3
8001066: 4013 ands r3, r2
8001068: 2b01 cmp r3, #1
800106a: d005 beq.n 8001078 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
800106c: 683b ldr r3, [r7, #0]
800106e: 685b ldr r3, [r3, #4]
8001070: 2203 movs r2, #3
8001072: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001074: 2b02 cmp r3, #2
8001076: d130 bne.n 80010da <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001078: 687b ldr r3, [r7, #4]
800107a: 689b ldr r3, [r3, #8]
800107c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
800107e: 697b ldr r3, [r7, #20]
8001080: 005b lsls r3, r3, #1
8001082: 2203 movs r2, #3
8001084: 409a lsls r2, r3
8001086: 0013 movs r3, r2
8001088: 43da mvns r2, r3
800108a: 693b ldr r3, [r7, #16]
800108c: 4013 ands r3, r2
800108e: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001090: 683b ldr r3, [r7, #0]
8001092: 68da ldr r2, [r3, #12]
8001094: 697b ldr r3, [r7, #20]
8001096: 005b lsls r3, r3, #1
8001098: 409a lsls r2, r3
800109a: 0013 movs r3, r2
800109c: 693a ldr r2, [r7, #16]
800109e: 4313 orrs r3, r2
80010a0: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
80010a2: 687b ldr r3, [r7, #4]
80010a4: 693a ldr r2, [r7, #16]
80010a6: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80010a8: 687b ldr r3, [r7, #4]
80010aa: 685b ldr r3, [r3, #4]
80010ac: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
80010ae: 2201 movs r2, #1
80010b0: 697b ldr r3, [r7, #20]
80010b2: 409a lsls r2, r3
80010b4: 0013 movs r3, r2
80010b6: 43da mvns r2, r3
80010b8: 693b ldr r3, [r7, #16]
80010ba: 4013 ands r3, r2
80010bc: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80010be: 683b ldr r3, [r7, #0]
80010c0: 685b ldr r3, [r3, #4]
80010c2: 091b lsrs r3, r3, #4
80010c4: 2201 movs r2, #1
80010c6: 401a ands r2, r3
80010c8: 697b ldr r3, [r7, #20]
80010ca: 409a lsls r2, r3
80010cc: 0013 movs r3, r2
80010ce: 693a ldr r2, [r7, #16]
80010d0: 4313 orrs r3, r2
80010d2: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80010d4: 687b ldr r3, [r7, #4]
80010d6: 693a ldr r2, [r7, #16]
80010d8: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80010da: 683b ldr r3, [r7, #0]
80010dc: 685b ldr r3, [r3, #4]
80010de: 2203 movs r2, #3
80010e0: 4013 ands r3, r2
80010e2: 2b03 cmp r3, #3
80010e4: d017 beq.n 8001116 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80010e6: 687b ldr r3, [r7, #4]
80010e8: 68db ldr r3, [r3, #12]
80010ea: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
80010ec: 697b ldr r3, [r7, #20]
80010ee: 005b lsls r3, r3, #1
80010f0: 2203 movs r2, #3
80010f2: 409a lsls r2, r3
80010f4: 0013 movs r3, r2
80010f6: 43da mvns r2, r3
80010f8: 693b ldr r3, [r7, #16]
80010fa: 4013 ands r3, r2
80010fc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80010fe: 683b ldr r3, [r7, #0]
8001100: 689a ldr r2, [r3, #8]
8001102: 697b ldr r3, [r7, #20]
8001104: 005b lsls r3, r3, #1
8001106: 409a lsls r2, r3
8001108: 0013 movs r3, r2
800110a: 693a ldr r2, [r7, #16]
800110c: 4313 orrs r3, r2
800110e: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8001110: 687b ldr r3, [r7, #4]
8001112: 693a ldr r2, [r7, #16]
8001114: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001116: 683b ldr r3, [r7, #0]
8001118: 685b ldr r3, [r3, #4]
800111a: 2203 movs r2, #3
800111c: 4013 ands r3, r2
800111e: 2b02 cmp r3, #2
8001120: d123 bne.n 800116a <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8001122: 697b ldr r3, [r7, #20]
8001124: 08da lsrs r2, r3, #3
8001126: 687b ldr r3, [r7, #4]
8001128: 3208 adds r2, #8
800112a: 0092 lsls r2, r2, #2
800112c: 58d3 ldr r3, [r2, r3]
800112e: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8001130: 697b ldr r3, [r7, #20]
8001132: 2207 movs r2, #7
8001134: 4013 ands r3, r2
8001136: 009b lsls r3, r3, #2
8001138: 220f movs r2, #15
800113a: 409a lsls r2, r3
800113c: 0013 movs r3, r2
800113e: 43da mvns r2, r3
8001140: 693b ldr r3, [r7, #16]
8001142: 4013 ands r3, r2
8001144: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8001146: 683b ldr r3, [r7, #0]
8001148: 691a ldr r2, [r3, #16]
800114a: 697b ldr r3, [r7, #20]
800114c: 2107 movs r1, #7
800114e: 400b ands r3, r1
8001150: 009b lsls r3, r3, #2
8001152: 409a lsls r2, r3
8001154: 0013 movs r3, r2
8001156: 693a ldr r2, [r7, #16]
8001158: 4313 orrs r3, r2
800115a: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
800115c: 697b ldr r3, [r7, #20]
800115e: 08da lsrs r2, r3, #3
8001160: 687b ldr r3, [r7, #4]
8001162: 3208 adds r2, #8
8001164: 0092 lsls r2, r2, #2
8001166: 6939 ldr r1, [r7, #16]
8001168: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800116a: 687b ldr r3, [r7, #4]
800116c: 681b ldr r3, [r3, #0]
800116e: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8001170: 697b ldr r3, [r7, #20]
8001172: 005b lsls r3, r3, #1
8001174: 2203 movs r2, #3
8001176: 409a lsls r2, r3
8001178: 0013 movs r3, r2
800117a: 43da mvns r2, r3
800117c: 693b ldr r3, [r7, #16]
800117e: 4013 ands r3, r2
8001180: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001182: 683b ldr r3, [r7, #0]
8001184: 685b ldr r3, [r3, #4]
8001186: 2203 movs r2, #3
8001188: 401a ands r2, r3
800118a: 697b ldr r3, [r7, #20]
800118c: 005b lsls r3, r3, #1
800118e: 409a lsls r2, r3
8001190: 0013 movs r3, r2
8001192: 693a ldr r2, [r7, #16]
8001194: 4313 orrs r3, r2
8001196: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001198: 687b ldr r3, [r7, #4]
800119a: 693a ldr r2, [r7, #16]
800119c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800119e: 683b ldr r3, [r7, #0]
80011a0: 685a ldr r2, [r3, #4]
80011a2: 23c0 movs r3, #192 ; 0xc0
80011a4: 029b lsls r3, r3, #10
80011a6: 4013 ands r3, r2
80011a8: d100 bne.n 80011ac <HAL_GPIO_Init+0x174>
80011aa: e09a b.n 80012e2 <HAL_GPIO_Init+0x2aa>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80011ac: 4b54 ldr r3, [pc, #336] ; (8001300 <HAL_GPIO_Init+0x2c8>)
80011ae: 699a ldr r2, [r3, #24]
80011b0: 4b53 ldr r3, [pc, #332] ; (8001300 <HAL_GPIO_Init+0x2c8>)
80011b2: 2101 movs r1, #1
80011b4: 430a orrs r2, r1
80011b6: 619a str r2, [r3, #24]
80011b8: 4b51 ldr r3, [pc, #324] ; (8001300 <HAL_GPIO_Init+0x2c8>)
80011ba: 699b ldr r3, [r3, #24]
80011bc: 2201 movs r2, #1
80011be: 4013 ands r3, r2
80011c0: 60bb str r3, [r7, #8]
80011c2: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
80011c4: 4a4f ldr r2, [pc, #316] ; (8001304 <HAL_GPIO_Init+0x2cc>)
80011c6: 697b ldr r3, [r7, #20]
80011c8: 089b lsrs r3, r3, #2
80011ca: 3302 adds r3, #2
80011cc: 009b lsls r3, r3, #2
80011ce: 589b ldr r3, [r3, r2]
80011d0: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
80011d2: 697b ldr r3, [r7, #20]
80011d4: 2203 movs r2, #3
80011d6: 4013 ands r3, r2
80011d8: 009b lsls r3, r3, #2
80011da: 220f movs r2, #15
80011dc: 409a lsls r2, r3
80011de: 0013 movs r3, r2
80011e0: 43da mvns r2, r3
80011e2: 693b ldr r3, [r7, #16]
80011e4: 4013 ands r3, r2
80011e6: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80011e8: 687a ldr r2, [r7, #4]
80011ea: 2390 movs r3, #144 ; 0x90
80011ec: 05db lsls r3, r3, #23
80011ee: 429a cmp r2, r3
80011f0: d013 beq.n 800121a <HAL_GPIO_Init+0x1e2>
80011f2: 687b ldr r3, [r7, #4]
80011f4: 4a44 ldr r2, [pc, #272] ; (8001308 <HAL_GPIO_Init+0x2d0>)
80011f6: 4293 cmp r3, r2
80011f8: d00d beq.n 8001216 <HAL_GPIO_Init+0x1de>
80011fa: 687b ldr r3, [r7, #4]
80011fc: 4a43 ldr r2, [pc, #268] ; (800130c <HAL_GPIO_Init+0x2d4>)
80011fe: 4293 cmp r3, r2
8001200: d007 beq.n 8001212 <HAL_GPIO_Init+0x1da>
8001202: 687b ldr r3, [r7, #4]
8001204: 4a42 ldr r2, [pc, #264] ; (8001310 <HAL_GPIO_Init+0x2d8>)
8001206: 4293 cmp r3, r2
8001208: d101 bne.n 800120e <HAL_GPIO_Init+0x1d6>
800120a: 2303 movs r3, #3
800120c: e006 b.n 800121c <HAL_GPIO_Init+0x1e4>
800120e: 2305 movs r3, #5
8001210: e004 b.n 800121c <HAL_GPIO_Init+0x1e4>
8001212: 2302 movs r3, #2
8001214: e002 b.n 800121c <HAL_GPIO_Init+0x1e4>
8001216: 2301 movs r3, #1
8001218: e000 b.n 800121c <HAL_GPIO_Init+0x1e4>
800121a: 2300 movs r3, #0
800121c: 697a ldr r2, [r7, #20]
800121e: 2103 movs r1, #3
8001220: 400a ands r2, r1
8001222: 0092 lsls r2, r2, #2
8001224: 4093 lsls r3, r2
8001226: 693a ldr r2, [r7, #16]
8001228: 4313 orrs r3, r2
800122a: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
800122c: 4935 ldr r1, [pc, #212] ; (8001304 <HAL_GPIO_Init+0x2cc>)
800122e: 697b ldr r3, [r7, #20]
8001230: 089b lsrs r3, r3, #2
8001232: 3302 adds r3, #2
8001234: 009b lsls r3, r3, #2
8001236: 693a ldr r2, [r7, #16]
8001238: 505a str r2, [r3, r1]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800123a: 4b36 ldr r3, [pc, #216] ; (8001314 <HAL_GPIO_Init+0x2dc>)
800123c: 681b ldr r3, [r3, #0]
800123e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001240: 68fb ldr r3, [r7, #12]
8001242: 43da mvns r2, r3
8001244: 693b ldr r3, [r7, #16]
8001246: 4013 ands r3, r2
8001248: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
800124a: 683b ldr r3, [r7, #0]
800124c: 685a ldr r2, [r3, #4]
800124e: 2380 movs r3, #128 ; 0x80
8001250: 025b lsls r3, r3, #9
8001252: 4013 ands r3, r2
8001254: d003 beq.n 800125e <HAL_GPIO_Init+0x226>
{
temp |= iocurrent;
8001256: 693a ldr r2, [r7, #16]
8001258: 68fb ldr r3, [r7, #12]
800125a: 4313 orrs r3, r2
800125c: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
800125e: 4b2d ldr r3, [pc, #180] ; (8001314 <HAL_GPIO_Init+0x2dc>)
8001260: 693a ldr r2, [r7, #16]
8001262: 601a str r2, [r3, #0]
temp = EXTI->EMR;
8001264: 4b2b ldr r3, [pc, #172] ; (8001314 <HAL_GPIO_Init+0x2dc>)
8001266: 685b ldr r3, [r3, #4]
8001268: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800126a: 68fb ldr r3, [r7, #12]
800126c: 43da mvns r2, r3
800126e: 693b ldr r3, [r7, #16]
8001270: 4013 ands r3, r2
8001272: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001274: 683b ldr r3, [r7, #0]
8001276: 685a ldr r2, [r3, #4]
8001278: 2380 movs r3, #128 ; 0x80
800127a: 029b lsls r3, r3, #10
800127c: 4013 ands r3, r2
800127e: d003 beq.n 8001288 <HAL_GPIO_Init+0x250>
{
temp |= iocurrent;
8001280: 693a ldr r2, [r7, #16]
8001282: 68fb ldr r3, [r7, #12]
8001284: 4313 orrs r3, r2
8001286: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001288: 4b22 ldr r3, [pc, #136] ; (8001314 <HAL_GPIO_Init+0x2dc>)
800128a: 693a ldr r2, [r7, #16]
800128c: 605a str r2, [r3, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
800128e: 4b21 ldr r3, [pc, #132] ; (8001314 <HAL_GPIO_Init+0x2dc>)
8001290: 689b ldr r3, [r3, #8]
8001292: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001294: 68fb ldr r3, [r7, #12]
8001296: 43da mvns r2, r3
8001298: 693b ldr r3, [r7, #16]
800129a: 4013 ands r3, r2
800129c: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
800129e: 683b ldr r3, [r7, #0]
80012a0: 685a ldr r2, [r3, #4]
80012a2: 2380 movs r3, #128 ; 0x80
80012a4: 035b lsls r3, r3, #13
80012a6: 4013 ands r3, r2
80012a8: d003 beq.n 80012b2 <HAL_GPIO_Init+0x27a>
{
temp |= iocurrent;
80012aa: 693a ldr r2, [r7, #16]
80012ac: 68fb ldr r3, [r7, #12]
80012ae: 4313 orrs r3, r2
80012b0: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
80012b2: 4b18 ldr r3, [pc, #96] ; (8001314 <HAL_GPIO_Init+0x2dc>)
80012b4: 693a ldr r2, [r7, #16]
80012b6: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
80012b8: 4b16 ldr r3, [pc, #88] ; (8001314 <HAL_GPIO_Init+0x2dc>)
80012ba: 68db ldr r3, [r3, #12]
80012bc: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80012be: 68fb ldr r3, [r7, #12]
80012c0: 43da mvns r2, r3
80012c2: 693b ldr r3, [r7, #16]
80012c4: 4013 ands r3, r2
80012c6: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
80012c8: 683b ldr r3, [r7, #0]
80012ca: 685a ldr r2, [r3, #4]
80012cc: 2380 movs r3, #128 ; 0x80
80012ce: 039b lsls r3, r3, #14
80012d0: 4013 ands r3, r2
80012d2: d003 beq.n 80012dc <HAL_GPIO_Init+0x2a4>
{
temp |= iocurrent;
80012d4: 693a ldr r2, [r7, #16]
80012d6: 68fb ldr r3, [r7, #12]
80012d8: 4313 orrs r3, r2
80012da: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
80012dc: 4b0d ldr r3, [pc, #52] ; (8001314 <HAL_GPIO_Init+0x2dc>)
80012de: 693a ldr r2, [r7, #16]
80012e0: 60da str r2, [r3, #12]
}
}
position++;
80012e2: 697b ldr r3, [r7, #20]
80012e4: 3301 adds r3, #1
80012e6: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80012e8: 683b ldr r3, [r7, #0]
80012ea: 681a ldr r2, [r3, #0]
80012ec: 697b ldr r3, [r7, #20]
80012ee: 40da lsrs r2, r3
80012f0: 1e13 subs r3, r2, #0
80012f2: d000 beq.n 80012f6 <HAL_GPIO_Init+0x2be>
80012f4: e6a8 b.n 8001048 <HAL_GPIO_Init+0x10>
}
}
80012f6: 46c0 nop ; (mov r8, r8)
80012f8: 46c0 nop ; (mov r8, r8)
80012fa: 46bd mov sp, r7
80012fc: b006 add sp, #24
80012fe: bd80 pop {r7, pc}
8001300: 40021000 .word 0x40021000
8001304: 40010000 .word 0x40010000
8001308: 48000400 .word 0x48000400
800130c: 48000800 .word 0x48000800
8001310: 48000c00 .word 0x48000c00
8001314: 40010400 .word 0x40010400
08001318 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001318: b580 push {r7, lr}
800131a: b082 sub sp, #8
800131c: af00 add r7, sp, #0
800131e: 6078 str r0, [r7, #4]
8001320: 0008 movs r0, r1
8001322: 0011 movs r1, r2
8001324: 1cbb adds r3, r7, #2
8001326: 1c02 adds r2, r0, #0
8001328: 801a strh r2, [r3, #0]
800132a: 1c7b adds r3, r7, #1
800132c: 1c0a adds r2, r1, #0
800132e: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001330: 1c7b adds r3, r7, #1
8001332: 781b ldrb r3, [r3, #0]
8001334: 2b00 cmp r3, #0
8001336: d004 beq.n 8001342 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001338: 1cbb adds r3, r7, #2
800133a: 881a ldrh r2, [r3, #0]
800133c: 687b ldr r3, [r7, #4]
800133e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8001340: e003 b.n 800134a <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001342: 1cbb adds r3, r7, #2
8001344: 881a ldrh r2, [r3, #0]
8001346: 687b ldr r3, [r7, #4]
8001348: 629a str r2, [r3, #40] ; 0x28
}
800134a: 46c0 nop ; (mov r8, r8)
800134c: 46bd mov sp, r7
800134e: b002 add sp, #8
8001350: bd80 pop {r7, pc}
...
08001354 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001354: b580 push {r7, lr}
8001356: b088 sub sp, #32
8001358: af00 add r7, sp, #0
800135a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
800135c: 687b ldr r3, [r7, #4]
800135e: 2b00 cmp r3, #0
8001360: d101 bne.n 8001366 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8001362: 2301 movs r3, #1
8001364: e301 b.n 800196a <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001366: 687b ldr r3, [r7, #4]
8001368: 681b ldr r3, [r3, #0]
800136a: 2201 movs r2, #1
800136c: 4013 ands r3, r2
800136e: d100 bne.n 8001372 <HAL_RCC_OscConfig+0x1e>
8001370: e08d b.n 800148e <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001372: 4bc3 ldr r3, [pc, #780] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001374: 685b ldr r3, [r3, #4]
8001376: 220c movs r2, #12
8001378: 4013 ands r3, r2
800137a: 2b04 cmp r3, #4
800137c: d00e beq.n 800139c <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
800137e: 4bc0 ldr r3, [pc, #768] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001380: 685b ldr r3, [r3, #4]
8001382: 220c movs r2, #12
8001384: 4013 ands r3, r2
8001386: 2b08 cmp r3, #8
8001388: d116 bne.n 80013b8 <HAL_RCC_OscConfig+0x64>
800138a: 4bbd ldr r3, [pc, #756] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800138c: 685a ldr r2, [r3, #4]
800138e: 2380 movs r3, #128 ; 0x80
8001390: 025b lsls r3, r3, #9
8001392: 401a ands r2, r3
8001394: 2380 movs r3, #128 ; 0x80
8001396: 025b lsls r3, r3, #9
8001398: 429a cmp r2, r3
800139a: d10d bne.n 80013b8 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800139c: 4bb8 ldr r3, [pc, #736] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800139e: 681a ldr r2, [r3, #0]
80013a0: 2380 movs r3, #128 ; 0x80
80013a2: 029b lsls r3, r3, #10
80013a4: 4013 ands r3, r2
80013a6: d100 bne.n 80013aa <HAL_RCC_OscConfig+0x56>
80013a8: e070 b.n 800148c <HAL_RCC_OscConfig+0x138>
80013aa: 687b ldr r3, [r7, #4]
80013ac: 685b ldr r3, [r3, #4]
80013ae: 2b00 cmp r3, #0
80013b0: d000 beq.n 80013b4 <HAL_RCC_OscConfig+0x60>
80013b2: e06b b.n 800148c <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
80013b4: 2301 movs r3, #1
80013b6: e2d8 b.n 800196a <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80013b8: 687b ldr r3, [r7, #4]
80013ba: 685b ldr r3, [r3, #4]
80013bc: 2b01 cmp r3, #1
80013be: d107 bne.n 80013d0 <HAL_RCC_OscConfig+0x7c>
80013c0: 4baf ldr r3, [pc, #700] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013c2: 681a ldr r2, [r3, #0]
80013c4: 4bae ldr r3, [pc, #696] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013c6: 2180 movs r1, #128 ; 0x80
80013c8: 0249 lsls r1, r1, #9
80013ca: 430a orrs r2, r1
80013cc: 601a str r2, [r3, #0]
80013ce: e02f b.n 8001430 <HAL_RCC_OscConfig+0xdc>
80013d0: 687b ldr r3, [r7, #4]
80013d2: 685b ldr r3, [r3, #4]
80013d4: 2b00 cmp r3, #0
80013d6: d10c bne.n 80013f2 <HAL_RCC_OscConfig+0x9e>
80013d8: 4ba9 ldr r3, [pc, #676] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013da: 681a ldr r2, [r3, #0]
80013dc: 4ba8 ldr r3, [pc, #672] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013de: 49a9 ldr r1, [pc, #676] ; (8001684 <HAL_RCC_OscConfig+0x330>)
80013e0: 400a ands r2, r1
80013e2: 601a str r2, [r3, #0]
80013e4: 4ba6 ldr r3, [pc, #664] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013e6: 681a ldr r2, [r3, #0]
80013e8: 4ba5 ldr r3, [pc, #660] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013ea: 49a7 ldr r1, [pc, #668] ; (8001688 <HAL_RCC_OscConfig+0x334>)
80013ec: 400a ands r2, r1
80013ee: 601a str r2, [r3, #0]
80013f0: e01e b.n 8001430 <HAL_RCC_OscConfig+0xdc>
80013f2: 687b ldr r3, [r7, #4]
80013f4: 685b ldr r3, [r3, #4]
80013f6: 2b05 cmp r3, #5
80013f8: d10e bne.n 8001418 <HAL_RCC_OscConfig+0xc4>
80013fa: 4ba1 ldr r3, [pc, #644] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80013fc: 681a ldr r2, [r3, #0]
80013fe: 4ba0 ldr r3, [pc, #640] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001400: 2180 movs r1, #128 ; 0x80
8001402: 02c9 lsls r1, r1, #11
8001404: 430a orrs r2, r1
8001406: 601a str r2, [r3, #0]
8001408: 4b9d ldr r3, [pc, #628] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800140a: 681a ldr r2, [r3, #0]
800140c: 4b9c ldr r3, [pc, #624] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800140e: 2180 movs r1, #128 ; 0x80
8001410: 0249 lsls r1, r1, #9
8001412: 430a orrs r2, r1
8001414: 601a str r2, [r3, #0]
8001416: e00b b.n 8001430 <HAL_RCC_OscConfig+0xdc>
8001418: 4b99 ldr r3, [pc, #612] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800141a: 681a ldr r2, [r3, #0]
800141c: 4b98 ldr r3, [pc, #608] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800141e: 4999 ldr r1, [pc, #612] ; (8001684 <HAL_RCC_OscConfig+0x330>)
8001420: 400a ands r2, r1
8001422: 601a str r2, [r3, #0]
8001424: 4b96 ldr r3, [pc, #600] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001426: 681a ldr r2, [r3, #0]
8001428: 4b95 ldr r3, [pc, #596] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800142a: 4997 ldr r1, [pc, #604] ; (8001688 <HAL_RCC_OscConfig+0x334>)
800142c: 400a ands r2, r1
800142e: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001430: 687b ldr r3, [r7, #4]
8001432: 685b ldr r3, [r3, #4]
8001434: 2b00 cmp r3, #0
8001436: d014 beq.n 8001462 <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001438: f7ff fb0a bl 8000a50 <HAL_GetTick>
800143c: 0003 movs r3, r0
800143e: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001440: e008 b.n 8001454 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001442: f7ff fb05 bl 8000a50 <HAL_GetTick>
8001446: 0002 movs r2, r0
8001448: 69bb ldr r3, [r7, #24]
800144a: 1ad3 subs r3, r2, r3
800144c: 2b64 cmp r3, #100 ; 0x64
800144e: d901 bls.n 8001454 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
8001450: 2303 movs r3, #3
8001452: e28a b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001454: 4b8a ldr r3, [pc, #552] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001456: 681a ldr r2, [r3, #0]
8001458: 2380 movs r3, #128 ; 0x80
800145a: 029b lsls r3, r3, #10
800145c: 4013 ands r3, r2
800145e: d0f0 beq.n 8001442 <HAL_RCC_OscConfig+0xee>
8001460: e015 b.n 800148e <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001462: f7ff faf5 bl 8000a50 <HAL_GetTick>
8001466: 0003 movs r3, r0
8001468: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800146a: e008 b.n 800147e <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800146c: f7ff faf0 bl 8000a50 <HAL_GetTick>
8001470: 0002 movs r2, r0
8001472: 69bb ldr r3, [r7, #24]
8001474: 1ad3 subs r3, r2, r3
8001476: 2b64 cmp r3, #100 ; 0x64
8001478: d901 bls.n 800147e <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
800147a: 2303 movs r3, #3
800147c: e275 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800147e: 4b80 ldr r3, [pc, #512] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001480: 681a ldr r2, [r3, #0]
8001482: 2380 movs r3, #128 ; 0x80
8001484: 029b lsls r3, r3, #10
8001486: 4013 ands r3, r2
8001488: d1f0 bne.n 800146c <HAL_RCC_OscConfig+0x118>
800148a: e000 b.n 800148e <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800148c: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800148e: 687b ldr r3, [r7, #4]
8001490: 681b ldr r3, [r3, #0]
8001492: 2202 movs r2, #2
8001494: 4013 ands r3, r2
8001496: d100 bne.n 800149a <HAL_RCC_OscConfig+0x146>
8001498: e069 b.n 800156e <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800149a: 4b79 ldr r3, [pc, #484] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800149c: 685b ldr r3, [r3, #4]
800149e: 220c movs r2, #12
80014a0: 4013 ands r3, r2
80014a2: d00b beq.n 80014bc <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
80014a4: 4b76 ldr r3, [pc, #472] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014a6: 685b ldr r3, [r3, #4]
80014a8: 220c movs r2, #12
80014aa: 4013 ands r3, r2
80014ac: 2b08 cmp r3, #8
80014ae: d11c bne.n 80014ea <HAL_RCC_OscConfig+0x196>
80014b0: 4b73 ldr r3, [pc, #460] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014b2: 685a ldr r2, [r3, #4]
80014b4: 2380 movs r3, #128 ; 0x80
80014b6: 025b lsls r3, r3, #9
80014b8: 4013 ands r3, r2
80014ba: d116 bne.n 80014ea <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80014bc: 4b70 ldr r3, [pc, #448] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014be: 681b ldr r3, [r3, #0]
80014c0: 2202 movs r2, #2
80014c2: 4013 ands r3, r2
80014c4: d005 beq.n 80014d2 <HAL_RCC_OscConfig+0x17e>
80014c6: 687b ldr r3, [r7, #4]
80014c8: 68db ldr r3, [r3, #12]
80014ca: 2b01 cmp r3, #1
80014cc: d001 beq.n 80014d2 <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
80014ce: 2301 movs r3, #1
80014d0: e24b b.n 800196a <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80014d2: 4b6b ldr r3, [pc, #428] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014d4: 681b ldr r3, [r3, #0]
80014d6: 22f8 movs r2, #248 ; 0xf8
80014d8: 4393 bics r3, r2
80014da: 0019 movs r1, r3
80014dc: 687b ldr r3, [r7, #4]
80014de: 691b ldr r3, [r3, #16]
80014e0: 00da lsls r2, r3, #3
80014e2: 4b67 ldr r3, [pc, #412] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014e4: 430a orrs r2, r1
80014e6: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80014e8: e041 b.n 800156e <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80014ea: 687b ldr r3, [r7, #4]
80014ec: 68db ldr r3, [r3, #12]
80014ee: 2b00 cmp r3, #0
80014f0: d024 beq.n 800153c <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80014f2: 4b63 ldr r3, [pc, #396] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014f4: 681a ldr r2, [r3, #0]
80014f6: 4b62 ldr r3, [pc, #392] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80014f8: 2101 movs r1, #1
80014fa: 430a orrs r2, r1
80014fc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80014fe: f7ff faa7 bl 8000a50 <HAL_GetTick>
8001502: 0003 movs r3, r0
8001504: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001506: e008 b.n 800151a <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001508: f7ff faa2 bl 8000a50 <HAL_GetTick>
800150c: 0002 movs r2, r0
800150e: 69bb ldr r3, [r7, #24]
8001510: 1ad3 subs r3, r2, r3
8001512: 2b02 cmp r3, #2
8001514: d901 bls.n 800151a <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
8001516: 2303 movs r3, #3
8001518: e227 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800151a: 4b59 ldr r3, [pc, #356] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800151c: 681b ldr r3, [r3, #0]
800151e: 2202 movs r2, #2
8001520: 4013 ands r3, r2
8001522: d0f1 beq.n 8001508 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001524: 4b56 ldr r3, [pc, #344] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001526: 681b ldr r3, [r3, #0]
8001528: 22f8 movs r2, #248 ; 0xf8
800152a: 4393 bics r3, r2
800152c: 0019 movs r1, r3
800152e: 687b ldr r3, [r7, #4]
8001530: 691b ldr r3, [r3, #16]
8001532: 00da lsls r2, r3, #3
8001534: 4b52 ldr r3, [pc, #328] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001536: 430a orrs r2, r1
8001538: 601a str r2, [r3, #0]
800153a: e018 b.n 800156e <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800153c: 4b50 ldr r3, [pc, #320] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800153e: 681a ldr r2, [r3, #0]
8001540: 4b4f ldr r3, [pc, #316] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001542: 2101 movs r1, #1
8001544: 438a bics r2, r1
8001546: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001548: f7ff fa82 bl 8000a50 <HAL_GetTick>
800154c: 0003 movs r3, r0
800154e: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001550: e008 b.n 8001564 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001552: f7ff fa7d bl 8000a50 <HAL_GetTick>
8001556: 0002 movs r2, r0
8001558: 69bb ldr r3, [r7, #24]
800155a: 1ad3 subs r3, r2, r3
800155c: 2b02 cmp r3, #2
800155e: d901 bls.n 8001564 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
8001560: 2303 movs r3, #3
8001562: e202 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001564: 4b46 ldr r3, [pc, #280] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001566: 681b ldr r3, [r3, #0]
8001568: 2202 movs r2, #2
800156a: 4013 ands r3, r2
800156c: d1f1 bne.n 8001552 <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800156e: 687b ldr r3, [r7, #4]
8001570: 681b ldr r3, [r3, #0]
8001572: 2208 movs r2, #8
8001574: 4013 ands r3, r2
8001576: d036 beq.n 80015e6 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001578: 687b ldr r3, [r7, #4]
800157a: 69db ldr r3, [r3, #28]
800157c: 2b00 cmp r3, #0
800157e: d019 beq.n 80015b4 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001580: 4b3f ldr r3, [pc, #252] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001582: 6a5a ldr r2, [r3, #36] ; 0x24
8001584: 4b3e ldr r3, [pc, #248] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001586: 2101 movs r1, #1
8001588: 430a orrs r2, r1
800158a: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
800158c: f7ff fa60 bl 8000a50 <HAL_GetTick>
8001590: 0003 movs r3, r0
8001592: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001594: e008 b.n 80015a8 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001596: f7ff fa5b bl 8000a50 <HAL_GetTick>
800159a: 0002 movs r2, r0
800159c: 69bb ldr r3, [r7, #24]
800159e: 1ad3 subs r3, r2, r3
80015a0: 2b02 cmp r3, #2
80015a2: d901 bls.n 80015a8 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
80015a4: 2303 movs r3, #3
80015a6: e1e0 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80015a8: 4b35 ldr r3, [pc, #212] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80015aa: 6a5b ldr r3, [r3, #36] ; 0x24
80015ac: 2202 movs r2, #2
80015ae: 4013 ands r3, r2
80015b0: d0f1 beq.n 8001596 <HAL_RCC_OscConfig+0x242>
80015b2: e018 b.n 80015e6 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80015b4: 4b32 ldr r3, [pc, #200] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80015b6: 6a5a ldr r2, [r3, #36] ; 0x24
80015b8: 4b31 ldr r3, [pc, #196] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80015ba: 2101 movs r1, #1
80015bc: 438a bics r2, r1
80015be: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
80015c0: f7ff fa46 bl 8000a50 <HAL_GetTick>
80015c4: 0003 movs r3, r0
80015c6: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80015c8: e008 b.n 80015dc <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80015ca: f7ff fa41 bl 8000a50 <HAL_GetTick>
80015ce: 0002 movs r2, r0
80015d0: 69bb ldr r3, [r7, #24]
80015d2: 1ad3 subs r3, r2, r3
80015d4: 2b02 cmp r3, #2
80015d6: d901 bls.n 80015dc <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
80015d8: 2303 movs r3, #3
80015da: e1c6 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80015dc: 4b28 ldr r3, [pc, #160] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80015de: 6a5b ldr r3, [r3, #36] ; 0x24
80015e0: 2202 movs r2, #2
80015e2: 4013 ands r3, r2
80015e4: d1f1 bne.n 80015ca <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80015e6: 687b ldr r3, [r7, #4]
80015e8: 681b ldr r3, [r3, #0]
80015ea: 2204 movs r2, #4
80015ec: 4013 ands r3, r2
80015ee: d100 bne.n 80015f2 <HAL_RCC_OscConfig+0x29e>
80015f0: e0b4 b.n 800175c <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
80015f2: 201f movs r0, #31
80015f4: 183b adds r3, r7, r0
80015f6: 2200 movs r2, #0
80015f8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80015fa: 4b21 ldr r3, [pc, #132] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
80015fc: 69da ldr r2, [r3, #28]
80015fe: 2380 movs r3, #128 ; 0x80
8001600: 055b lsls r3, r3, #21
8001602: 4013 ands r3, r2
8001604: d110 bne.n 8001628 <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001606: 4b1e ldr r3, [pc, #120] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001608: 69da ldr r2, [r3, #28]
800160a: 4b1d ldr r3, [pc, #116] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
800160c: 2180 movs r1, #128 ; 0x80
800160e: 0549 lsls r1, r1, #21
8001610: 430a orrs r2, r1
8001612: 61da str r2, [r3, #28]
8001614: 4b1a ldr r3, [pc, #104] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001616: 69da ldr r2, [r3, #28]
8001618: 2380 movs r3, #128 ; 0x80
800161a: 055b lsls r3, r3, #21
800161c: 4013 ands r3, r2
800161e: 60fb str r3, [r7, #12]
8001620: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8001622: 183b adds r3, r7, r0
8001624: 2201 movs r2, #1
8001626: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001628: 4b18 ldr r3, [pc, #96] ; (800168c <HAL_RCC_OscConfig+0x338>)
800162a: 681a ldr r2, [r3, #0]
800162c: 2380 movs r3, #128 ; 0x80
800162e: 005b lsls r3, r3, #1
8001630: 4013 ands r3, r2
8001632: d11a bne.n 800166a <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001634: 4b15 ldr r3, [pc, #84] ; (800168c <HAL_RCC_OscConfig+0x338>)
8001636: 681a ldr r2, [r3, #0]
8001638: 4b14 ldr r3, [pc, #80] ; (800168c <HAL_RCC_OscConfig+0x338>)
800163a: 2180 movs r1, #128 ; 0x80
800163c: 0049 lsls r1, r1, #1
800163e: 430a orrs r2, r1
8001640: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001642: f7ff fa05 bl 8000a50 <HAL_GetTick>
8001646: 0003 movs r3, r0
8001648: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800164a: e008 b.n 800165e <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800164c: f7ff fa00 bl 8000a50 <HAL_GetTick>
8001650: 0002 movs r2, r0
8001652: 69bb ldr r3, [r7, #24]
8001654: 1ad3 subs r3, r2, r3
8001656: 2b64 cmp r3, #100 ; 0x64
8001658: d901 bls.n 800165e <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
800165a: 2303 movs r3, #3
800165c: e185 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800165e: 4b0b ldr r3, [pc, #44] ; (800168c <HAL_RCC_OscConfig+0x338>)
8001660: 681a ldr r2, [r3, #0]
8001662: 2380 movs r3, #128 ; 0x80
8001664: 005b lsls r3, r3, #1
8001666: 4013 ands r3, r2
8001668: d0f0 beq.n 800164c <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800166a: 687b ldr r3, [r7, #4]
800166c: 689b ldr r3, [r3, #8]
800166e: 2b01 cmp r3, #1
8001670: d10e bne.n 8001690 <HAL_RCC_OscConfig+0x33c>
8001672: 4b03 ldr r3, [pc, #12] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001674: 6a1a ldr r2, [r3, #32]
8001676: 4b02 ldr r3, [pc, #8] ; (8001680 <HAL_RCC_OscConfig+0x32c>)
8001678: 2101 movs r1, #1
800167a: 430a orrs r2, r1
800167c: 621a str r2, [r3, #32]
800167e: e035 b.n 80016ec <HAL_RCC_OscConfig+0x398>
8001680: 40021000 .word 0x40021000
8001684: fffeffff .word 0xfffeffff
8001688: fffbffff .word 0xfffbffff
800168c: 40007000 .word 0x40007000
8001690: 687b ldr r3, [r7, #4]
8001692: 689b ldr r3, [r3, #8]
8001694: 2b00 cmp r3, #0
8001696: d10c bne.n 80016b2 <HAL_RCC_OscConfig+0x35e>
8001698: 4bb6 ldr r3, [pc, #728] ; (8001974 <HAL_RCC_OscConfig+0x620>)
800169a: 6a1a ldr r2, [r3, #32]
800169c: 4bb5 ldr r3, [pc, #724] ; (8001974 <HAL_RCC_OscConfig+0x620>)
800169e: 2101 movs r1, #1
80016a0: 438a bics r2, r1
80016a2: 621a str r2, [r3, #32]
80016a4: 4bb3 ldr r3, [pc, #716] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016a6: 6a1a ldr r2, [r3, #32]
80016a8: 4bb2 ldr r3, [pc, #712] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016aa: 2104 movs r1, #4
80016ac: 438a bics r2, r1
80016ae: 621a str r2, [r3, #32]
80016b0: e01c b.n 80016ec <HAL_RCC_OscConfig+0x398>
80016b2: 687b ldr r3, [r7, #4]
80016b4: 689b ldr r3, [r3, #8]
80016b6: 2b05 cmp r3, #5
80016b8: d10c bne.n 80016d4 <HAL_RCC_OscConfig+0x380>
80016ba: 4bae ldr r3, [pc, #696] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016bc: 6a1a ldr r2, [r3, #32]
80016be: 4bad ldr r3, [pc, #692] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016c0: 2104 movs r1, #4
80016c2: 430a orrs r2, r1
80016c4: 621a str r2, [r3, #32]
80016c6: 4bab ldr r3, [pc, #684] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016c8: 6a1a ldr r2, [r3, #32]
80016ca: 4baa ldr r3, [pc, #680] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016cc: 2101 movs r1, #1
80016ce: 430a orrs r2, r1
80016d0: 621a str r2, [r3, #32]
80016d2: e00b b.n 80016ec <HAL_RCC_OscConfig+0x398>
80016d4: 4ba7 ldr r3, [pc, #668] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016d6: 6a1a ldr r2, [r3, #32]
80016d8: 4ba6 ldr r3, [pc, #664] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016da: 2101 movs r1, #1
80016dc: 438a bics r2, r1
80016de: 621a str r2, [r3, #32]
80016e0: 4ba4 ldr r3, [pc, #656] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016e2: 6a1a ldr r2, [r3, #32]
80016e4: 4ba3 ldr r3, [pc, #652] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80016e6: 2104 movs r1, #4
80016e8: 438a bics r2, r1
80016ea: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80016ec: 687b ldr r3, [r7, #4]
80016ee: 689b ldr r3, [r3, #8]
80016f0: 2b00 cmp r3, #0
80016f2: d014 beq.n 800171e <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80016f4: f7ff f9ac bl 8000a50 <HAL_GetTick>
80016f8: 0003 movs r3, r0
80016fa: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80016fc: e009 b.n 8001712 <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80016fe: f7ff f9a7 bl 8000a50 <HAL_GetTick>
8001702: 0002 movs r2, r0
8001704: 69bb ldr r3, [r7, #24]
8001706: 1ad3 subs r3, r2, r3
8001708: 4a9b ldr r2, [pc, #620] ; (8001978 <HAL_RCC_OscConfig+0x624>)
800170a: 4293 cmp r3, r2
800170c: d901 bls.n 8001712 <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
800170e: 2303 movs r3, #3
8001710: e12b b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001712: 4b98 ldr r3, [pc, #608] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001714: 6a1b ldr r3, [r3, #32]
8001716: 2202 movs r2, #2
8001718: 4013 ands r3, r2
800171a: d0f0 beq.n 80016fe <HAL_RCC_OscConfig+0x3aa>
800171c: e013 b.n 8001746 <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800171e: f7ff f997 bl 8000a50 <HAL_GetTick>
8001722: 0003 movs r3, r0
8001724: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001726: e009 b.n 800173c <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001728: f7ff f992 bl 8000a50 <HAL_GetTick>
800172c: 0002 movs r2, r0
800172e: 69bb ldr r3, [r7, #24]
8001730: 1ad3 subs r3, r2, r3
8001732: 4a91 ldr r2, [pc, #580] ; (8001978 <HAL_RCC_OscConfig+0x624>)
8001734: 4293 cmp r3, r2
8001736: d901 bls.n 800173c <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
8001738: 2303 movs r3, #3
800173a: e116 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800173c: 4b8d ldr r3, [pc, #564] ; (8001974 <HAL_RCC_OscConfig+0x620>)
800173e: 6a1b ldr r3, [r3, #32]
8001740: 2202 movs r2, #2
8001742: 4013 ands r3, r2
8001744: d1f0 bne.n 8001728 <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8001746: 231f movs r3, #31
8001748: 18fb adds r3, r7, r3
800174a: 781b ldrb r3, [r3, #0]
800174c: 2b01 cmp r3, #1
800174e: d105 bne.n 800175c <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001750: 4b88 ldr r3, [pc, #544] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001752: 69da ldr r2, [r3, #28]
8001754: 4b87 ldr r3, [pc, #540] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001756: 4989 ldr r1, [pc, #548] ; (800197c <HAL_RCC_OscConfig+0x628>)
8001758: 400a ands r2, r1
800175a: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
800175c: 687b ldr r3, [r7, #4]
800175e: 681b ldr r3, [r3, #0]
8001760: 2210 movs r2, #16
8001762: 4013 ands r3, r2
8001764: d063 beq.n 800182e <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8001766: 687b ldr r3, [r7, #4]
8001768: 695b ldr r3, [r3, #20]
800176a: 2b01 cmp r3, #1
800176c: d12a bne.n 80017c4 <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
800176e: 4b81 ldr r3, [pc, #516] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001770: 6b5a ldr r2, [r3, #52] ; 0x34
8001772: 4b80 ldr r3, [pc, #512] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001774: 2104 movs r1, #4
8001776: 430a orrs r2, r1
8001778: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
800177a: 4b7e ldr r3, [pc, #504] ; (8001974 <HAL_RCC_OscConfig+0x620>)
800177c: 6b5a ldr r2, [r3, #52] ; 0x34
800177e: 4b7d ldr r3, [pc, #500] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001780: 2101 movs r1, #1
8001782: 430a orrs r2, r1
8001784: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001786: f7ff f963 bl 8000a50 <HAL_GetTick>
800178a: 0003 movs r3, r0
800178c: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
800178e: e008 b.n 80017a2 <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001790: f7ff f95e bl 8000a50 <HAL_GetTick>
8001794: 0002 movs r2, r0
8001796: 69bb ldr r3, [r7, #24]
8001798: 1ad3 subs r3, r2, r3
800179a: 2b02 cmp r3, #2
800179c: d901 bls.n 80017a2 <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
800179e: 2303 movs r3, #3
80017a0: e0e3 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
80017a2: 4b74 ldr r3, [pc, #464] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017a4: 6b5b ldr r3, [r3, #52] ; 0x34
80017a6: 2202 movs r2, #2
80017a8: 4013 ands r3, r2
80017aa: d0f1 beq.n 8001790 <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
80017ac: 4b71 ldr r3, [pc, #452] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017ae: 6b5b ldr r3, [r3, #52] ; 0x34
80017b0: 22f8 movs r2, #248 ; 0xf8
80017b2: 4393 bics r3, r2
80017b4: 0019 movs r1, r3
80017b6: 687b ldr r3, [r7, #4]
80017b8: 699b ldr r3, [r3, #24]
80017ba: 00da lsls r2, r3, #3
80017bc: 4b6d ldr r3, [pc, #436] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017be: 430a orrs r2, r1
80017c0: 635a str r2, [r3, #52] ; 0x34
80017c2: e034 b.n 800182e <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
80017c4: 687b ldr r3, [r7, #4]
80017c6: 695b ldr r3, [r3, #20]
80017c8: 3305 adds r3, #5
80017ca: d111 bne.n 80017f0 <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
80017cc: 4b69 ldr r3, [pc, #420] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017ce: 6b5a ldr r2, [r3, #52] ; 0x34
80017d0: 4b68 ldr r3, [pc, #416] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017d2: 2104 movs r1, #4
80017d4: 438a bics r2, r1
80017d6: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
80017d8: 4b66 ldr r3, [pc, #408] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017da: 6b5b ldr r3, [r3, #52] ; 0x34
80017dc: 22f8 movs r2, #248 ; 0xf8
80017de: 4393 bics r3, r2
80017e0: 0019 movs r1, r3
80017e2: 687b ldr r3, [r7, #4]
80017e4: 699b ldr r3, [r3, #24]
80017e6: 00da lsls r2, r3, #3
80017e8: 4b62 ldr r3, [pc, #392] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017ea: 430a orrs r2, r1
80017ec: 635a str r2, [r3, #52] ; 0x34
80017ee: e01e b.n 800182e <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
80017f0: 4b60 ldr r3, [pc, #384] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017f2: 6b5a ldr r2, [r3, #52] ; 0x34
80017f4: 4b5f ldr r3, [pc, #380] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017f6: 2104 movs r1, #4
80017f8: 430a orrs r2, r1
80017fa: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
80017fc: 4b5d ldr r3, [pc, #372] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80017fe: 6b5a ldr r2, [r3, #52] ; 0x34
8001800: 4b5c ldr r3, [pc, #368] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001802: 2101 movs r1, #1
8001804: 438a bics r2, r1
8001806: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001808: f7ff f922 bl 8000a50 <HAL_GetTick>
800180c: 0003 movs r3, r0
800180e: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001810: e008 b.n 8001824 <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001812: f7ff f91d bl 8000a50 <HAL_GetTick>
8001816: 0002 movs r2, r0
8001818: 69bb ldr r3, [r7, #24]
800181a: 1ad3 subs r3, r2, r3
800181c: 2b02 cmp r3, #2
800181e: d901 bls.n 8001824 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
8001820: 2303 movs r3, #3
8001822: e0a2 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001824: 4b53 ldr r3, [pc, #332] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001826: 6b5b ldr r3, [r3, #52] ; 0x34
8001828: 2202 movs r2, #2
800182a: 4013 ands r3, r2
800182c: d1f1 bne.n 8001812 <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
800182e: 687b ldr r3, [r7, #4]
8001830: 6a1b ldr r3, [r3, #32]
8001832: 2b00 cmp r3, #0
8001834: d100 bne.n 8001838 <HAL_RCC_OscConfig+0x4e4>
8001836: e097 b.n 8001968 <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001838: 4b4e ldr r3, [pc, #312] ; (8001974 <HAL_RCC_OscConfig+0x620>)
800183a: 685b ldr r3, [r3, #4]
800183c: 220c movs r2, #12
800183e: 4013 ands r3, r2
8001840: 2b08 cmp r3, #8
8001842: d100 bne.n 8001846 <HAL_RCC_OscConfig+0x4f2>
8001844: e06b b.n 800191e <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001846: 687b ldr r3, [r7, #4]
8001848: 6a1b ldr r3, [r3, #32]
800184a: 2b02 cmp r3, #2
800184c: d14c bne.n 80018e8 <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800184e: 4b49 ldr r3, [pc, #292] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001850: 681a ldr r2, [r3, #0]
8001852: 4b48 ldr r3, [pc, #288] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001854: 494a ldr r1, [pc, #296] ; (8001980 <HAL_RCC_OscConfig+0x62c>)
8001856: 400a ands r2, r1
8001858: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800185a: f7ff f8f9 bl 8000a50 <HAL_GetTick>
800185e: 0003 movs r3, r0
8001860: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001862: e008 b.n 8001876 <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001864: f7ff f8f4 bl 8000a50 <HAL_GetTick>
8001868: 0002 movs r2, r0
800186a: 69bb ldr r3, [r7, #24]
800186c: 1ad3 subs r3, r2, r3
800186e: 2b02 cmp r3, #2
8001870: d901 bls.n 8001876 <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
8001872: 2303 movs r3, #3
8001874: e079 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001876: 4b3f ldr r3, [pc, #252] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001878: 681a ldr r2, [r3, #0]
800187a: 2380 movs r3, #128 ; 0x80
800187c: 049b lsls r3, r3, #18
800187e: 4013 ands r3, r2
8001880: d1f0 bne.n 8001864 <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001882: 4b3c ldr r3, [pc, #240] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001884: 6adb ldr r3, [r3, #44] ; 0x2c
8001886: 220f movs r2, #15
8001888: 4393 bics r3, r2
800188a: 0019 movs r1, r3
800188c: 687b ldr r3, [r7, #4]
800188e: 6ada ldr r2, [r3, #44] ; 0x2c
8001890: 4b38 ldr r3, [pc, #224] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001892: 430a orrs r2, r1
8001894: 62da str r2, [r3, #44] ; 0x2c
8001896: 4b37 ldr r3, [pc, #220] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001898: 685b ldr r3, [r3, #4]
800189a: 4a3a ldr r2, [pc, #232] ; (8001984 <HAL_RCC_OscConfig+0x630>)
800189c: 4013 ands r3, r2
800189e: 0019 movs r1, r3
80018a0: 687b ldr r3, [r7, #4]
80018a2: 6a9a ldr r2, [r3, #40] ; 0x28
80018a4: 687b ldr r3, [r7, #4]
80018a6: 6a5b ldr r3, [r3, #36] ; 0x24
80018a8: 431a orrs r2, r3
80018aa: 4b32 ldr r3, [pc, #200] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80018ac: 430a orrs r2, r1
80018ae: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80018b0: 4b30 ldr r3, [pc, #192] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80018b2: 681a ldr r2, [r3, #0]
80018b4: 4b2f ldr r3, [pc, #188] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80018b6: 2180 movs r1, #128 ; 0x80
80018b8: 0449 lsls r1, r1, #17
80018ba: 430a orrs r2, r1
80018bc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80018be: f7ff f8c7 bl 8000a50 <HAL_GetTick>
80018c2: 0003 movs r3, r0
80018c4: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80018c6: e008 b.n 80018da <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80018c8: f7ff f8c2 bl 8000a50 <HAL_GetTick>
80018cc: 0002 movs r2, r0
80018ce: 69bb ldr r3, [r7, #24]
80018d0: 1ad3 subs r3, r2, r3
80018d2: 2b02 cmp r3, #2
80018d4: d901 bls.n 80018da <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
80018d6: 2303 movs r3, #3
80018d8: e047 b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80018da: 4b26 ldr r3, [pc, #152] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80018dc: 681a ldr r2, [r3, #0]
80018de: 2380 movs r3, #128 ; 0x80
80018e0: 049b lsls r3, r3, #18
80018e2: 4013 ands r3, r2
80018e4: d0f0 beq.n 80018c8 <HAL_RCC_OscConfig+0x574>
80018e6: e03f b.n 8001968 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80018e8: 4b22 ldr r3, [pc, #136] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80018ea: 681a ldr r2, [r3, #0]
80018ec: 4b21 ldr r3, [pc, #132] ; (8001974 <HAL_RCC_OscConfig+0x620>)
80018ee: 4924 ldr r1, [pc, #144] ; (8001980 <HAL_RCC_OscConfig+0x62c>)
80018f0: 400a ands r2, r1
80018f2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80018f4: f7ff f8ac bl 8000a50 <HAL_GetTick>
80018f8: 0003 movs r3, r0
80018fa: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80018fc: e008 b.n 8001910 <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80018fe: f7ff f8a7 bl 8000a50 <HAL_GetTick>
8001902: 0002 movs r2, r0
8001904: 69bb ldr r3, [r7, #24]
8001906: 1ad3 subs r3, r2, r3
8001908: 2b02 cmp r3, #2
800190a: d901 bls.n 8001910 <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
800190c: 2303 movs r3, #3
800190e: e02c b.n 800196a <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001910: 4b18 ldr r3, [pc, #96] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001912: 681a ldr r2, [r3, #0]
8001914: 2380 movs r3, #128 ; 0x80
8001916: 049b lsls r3, r3, #18
8001918: 4013 ands r3, r2
800191a: d1f0 bne.n 80018fe <HAL_RCC_OscConfig+0x5aa>
800191c: e024 b.n 8001968 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800191e: 687b ldr r3, [r7, #4]
8001920: 6a1b ldr r3, [r3, #32]
8001922: 2b01 cmp r3, #1
8001924: d101 bne.n 800192a <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
8001926: 2301 movs r3, #1
8001928: e01f b.n 800196a <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800192a: 4b12 ldr r3, [pc, #72] ; (8001974 <HAL_RCC_OscConfig+0x620>)
800192c: 685b ldr r3, [r3, #4]
800192e: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8001930: 4b10 ldr r3, [pc, #64] ; (8001974 <HAL_RCC_OscConfig+0x620>)
8001932: 6adb ldr r3, [r3, #44] ; 0x2c
8001934: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001936: 697a ldr r2, [r7, #20]
8001938: 2380 movs r3, #128 ; 0x80
800193a: 025b lsls r3, r3, #9
800193c: 401a ands r2, r3
800193e: 687b ldr r3, [r7, #4]
8001940: 6a5b ldr r3, [r3, #36] ; 0x24
8001942: 429a cmp r2, r3
8001944: d10e bne.n 8001964 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001946: 693b ldr r3, [r7, #16]
8001948: 220f movs r2, #15
800194a: 401a ands r2, r3
800194c: 687b ldr r3, [r7, #4]
800194e: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001950: 429a cmp r2, r3
8001952: d107 bne.n 8001964 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8001954: 697a ldr r2, [r7, #20]
8001956: 23f0 movs r3, #240 ; 0xf0
8001958: 039b lsls r3, r3, #14
800195a: 401a ands r2, r3
800195c: 687b ldr r3, [r7, #4]
800195e: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001960: 429a cmp r2, r3
8001962: d001 beq.n 8001968 <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
8001964: 2301 movs r3, #1
8001966: e000 b.n 800196a <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
8001968: 2300 movs r3, #0
}
800196a: 0018 movs r0, r3
800196c: 46bd mov sp, r7
800196e: b008 add sp, #32
8001970: bd80 pop {r7, pc}
8001972: 46c0 nop ; (mov r8, r8)
8001974: 40021000 .word 0x40021000
8001978: 00001388 .word 0x00001388
800197c: efffffff .word 0xefffffff
8001980: feffffff .word 0xfeffffff
8001984: ffc2ffff .word 0xffc2ffff
08001988 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001988: b580 push {r7, lr}
800198a: b084 sub sp, #16
800198c: af00 add r7, sp, #0
800198e: 6078 str r0, [r7, #4]
8001990: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001992: 687b ldr r3, [r7, #4]
8001994: 2b00 cmp r3, #0
8001996: d101 bne.n 800199c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001998: 2301 movs r3, #1
800199a: e0b3 b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
800199c: 4b5b ldr r3, [pc, #364] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
800199e: 681b ldr r3, [r3, #0]
80019a0: 2201 movs r2, #1
80019a2: 4013 ands r3, r2
80019a4: 683a ldr r2, [r7, #0]
80019a6: 429a cmp r2, r3
80019a8: d911 bls.n 80019ce <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80019aa: 4b58 ldr r3, [pc, #352] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
80019ac: 681b ldr r3, [r3, #0]
80019ae: 2201 movs r2, #1
80019b0: 4393 bics r3, r2
80019b2: 0019 movs r1, r3
80019b4: 4b55 ldr r3, [pc, #340] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
80019b6: 683a ldr r2, [r7, #0]
80019b8: 430a orrs r2, r1
80019ba: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80019bc: 4b53 ldr r3, [pc, #332] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
80019be: 681b ldr r3, [r3, #0]
80019c0: 2201 movs r2, #1
80019c2: 4013 ands r3, r2
80019c4: 683a ldr r2, [r7, #0]
80019c6: 429a cmp r2, r3
80019c8: d001 beq.n 80019ce <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
80019ca: 2301 movs r3, #1
80019cc: e09a b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80019ce: 687b ldr r3, [r7, #4]
80019d0: 681b ldr r3, [r3, #0]
80019d2: 2202 movs r2, #2
80019d4: 4013 ands r3, r2
80019d6: d015 beq.n 8001a04 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80019d8: 687b ldr r3, [r7, #4]
80019da: 681b ldr r3, [r3, #0]
80019dc: 2204 movs r2, #4
80019de: 4013 ands r3, r2
80019e0: d006 beq.n 80019f0 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
80019e2: 4b4b ldr r3, [pc, #300] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
80019e4: 685a ldr r2, [r3, #4]
80019e6: 4b4a ldr r3, [pc, #296] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
80019e8: 21e0 movs r1, #224 ; 0xe0
80019ea: 00c9 lsls r1, r1, #3
80019ec: 430a orrs r2, r1
80019ee: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80019f0: 4b47 ldr r3, [pc, #284] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
80019f2: 685b ldr r3, [r3, #4]
80019f4: 22f0 movs r2, #240 ; 0xf0
80019f6: 4393 bics r3, r2
80019f8: 0019 movs r1, r3
80019fa: 687b ldr r3, [r7, #4]
80019fc: 689a ldr r2, [r3, #8]
80019fe: 4b44 ldr r3, [pc, #272] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a00: 430a orrs r2, r1
8001a02: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001a04: 687b ldr r3, [r7, #4]
8001a06: 681b ldr r3, [r3, #0]
8001a08: 2201 movs r2, #1
8001a0a: 4013 ands r3, r2
8001a0c: d040 beq.n 8001a90 <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001a0e: 687b ldr r3, [r7, #4]
8001a10: 685b ldr r3, [r3, #4]
8001a12: 2b01 cmp r3, #1
8001a14: d107 bne.n 8001a26 <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001a16: 4b3e ldr r3, [pc, #248] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a18: 681a ldr r2, [r3, #0]
8001a1a: 2380 movs r3, #128 ; 0x80
8001a1c: 029b lsls r3, r3, #10
8001a1e: 4013 ands r3, r2
8001a20: d114 bne.n 8001a4c <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001a22: 2301 movs r3, #1
8001a24: e06e b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001a26: 687b ldr r3, [r7, #4]
8001a28: 685b ldr r3, [r3, #4]
8001a2a: 2b02 cmp r3, #2
8001a2c: d107 bne.n 8001a3e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001a2e: 4b38 ldr r3, [pc, #224] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a30: 681a ldr r2, [r3, #0]
8001a32: 2380 movs r3, #128 ; 0x80
8001a34: 049b lsls r3, r3, #18
8001a36: 4013 ands r3, r2
8001a38: d108 bne.n 8001a4c <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001a3a: 2301 movs r3, #1
8001a3c: e062 b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001a3e: 4b34 ldr r3, [pc, #208] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a40: 681b ldr r3, [r3, #0]
8001a42: 2202 movs r2, #2
8001a44: 4013 ands r3, r2
8001a46: d101 bne.n 8001a4c <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001a48: 2301 movs r3, #1
8001a4a: e05b b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001a4c: 4b30 ldr r3, [pc, #192] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a4e: 685b ldr r3, [r3, #4]
8001a50: 2203 movs r2, #3
8001a52: 4393 bics r3, r2
8001a54: 0019 movs r1, r3
8001a56: 687b ldr r3, [r7, #4]
8001a58: 685a ldr r2, [r3, #4]
8001a5a: 4b2d ldr r3, [pc, #180] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a5c: 430a orrs r2, r1
8001a5e: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a60: f7fe fff6 bl 8000a50 <HAL_GetTick>
8001a64: 0003 movs r3, r0
8001a66: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001a68: e009 b.n 8001a7e <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001a6a: f7fe fff1 bl 8000a50 <HAL_GetTick>
8001a6e: 0002 movs r2, r0
8001a70: 68fb ldr r3, [r7, #12]
8001a72: 1ad3 subs r3, r2, r3
8001a74: 4a27 ldr r2, [pc, #156] ; (8001b14 <HAL_RCC_ClockConfig+0x18c>)
8001a76: 4293 cmp r3, r2
8001a78: d901 bls.n 8001a7e <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
8001a7a: 2303 movs r3, #3
8001a7c: e042 b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001a7e: 4b24 ldr r3, [pc, #144] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001a80: 685b ldr r3, [r3, #4]
8001a82: 220c movs r2, #12
8001a84: 401a ands r2, r3
8001a86: 687b ldr r3, [r7, #4]
8001a88: 685b ldr r3, [r3, #4]
8001a8a: 009b lsls r3, r3, #2
8001a8c: 429a cmp r2, r3
8001a8e: d1ec bne.n 8001a6a <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001a90: 4b1e ldr r3, [pc, #120] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
8001a92: 681b ldr r3, [r3, #0]
8001a94: 2201 movs r2, #1
8001a96: 4013 ands r3, r2
8001a98: 683a ldr r2, [r7, #0]
8001a9a: 429a cmp r2, r3
8001a9c: d211 bcs.n 8001ac2 <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001a9e: 4b1b ldr r3, [pc, #108] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
8001aa0: 681b ldr r3, [r3, #0]
8001aa2: 2201 movs r2, #1
8001aa4: 4393 bics r3, r2
8001aa6: 0019 movs r1, r3
8001aa8: 4b18 ldr r3, [pc, #96] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
8001aaa: 683a ldr r2, [r7, #0]
8001aac: 430a orrs r2, r1
8001aae: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001ab0: 4b16 ldr r3, [pc, #88] ; (8001b0c <HAL_RCC_ClockConfig+0x184>)
8001ab2: 681b ldr r3, [r3, #0]
8001ab4: 2201 movs r2, #1
8001ab6: 4013 ands r3, r2
8001ab8: 683a ldr r2, [r7, #0]
8001aba: 429a cmp r2, r3
8001abc: d001 beq.n 8001ac2 <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
8001abe: 2301 movs r3, #1
8001ac0: e020 b.n 8001b04 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001ac2: 687b ldr r3, [r7, #4]
8001ac4: 681b ldr r3, [r3, #0]
8001ac6: 2204 movs r2, #4
8001ac8: 4013 ands r3, r2
8001aca: d009 beq.n 8001ae0 <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8001acc: 4b10 ldr r3, [pc, #64] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001ace: 685b ldr r3, [r3, #4]
8001ad0: 4a11 ldr r2, [pc, #68] ; (8001b18 <HAL_RCC_ClockConfig+0x190>)
8001ad2: 4013 ands r3, r2
8001ad4: 0019 movs r1, r3
8001ad6: 687b ldr r3, [r7, #4]
8001ad8: 68da ldr r2, [r3, #12]
8001ada: 4b0d ldr r3, [pc, #52] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001adc: 430a orrs r2, r1
8001ade: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8001ae0: f000 f820 bl 8001b24 <HAL_RCC_GetSysClockFreq>
8001ae4: 0001 movs r1, r0
8001ae6: 4b0a ldr r3, [pc, #40] ; (8001b10 <HAL_RCC_ClockConfig+0x188>)
8001ae8: 685b ldr r3, [r3, #4]
8001aea: 091b lsrs r3, r3, #4
8001aec: 220f movs r2, #15
8001aee: 4013 ands r3, r2
8001af0: 4a0a ldr r2, [pc, #40] ; (8001b1c <HAL_RCC_ClockConfig+0x194>)
8001af2: 5cd3 ldrb r3, [r2, r3]
8001af4: 000a movs r2, r1
8001af6: 40da lsrs r2, r3
8001af8: 4b09 ldr r3, [pc, #36] ; (8001b20 <HAL_RCC_ClockConfig+0x198>)
8001afa: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
8001afc: 2003 movs r0, #3
8001afe: f7fe ff61 bl 80009c4 <HAL_InitTick>
return HAL_OK;
8001b02: 2300 movs r3, #0
}
8001b04: 0018 movs r0, r3
8001b06: 46bd mov sp, r7
8001b08: b004 add sp, #16
8001b0a: bd80 pop {r7, pc}
8001b0c: 40022000 .word 0x40022000
8001b10: 40021000 .word 0x40021000
8001b14: 00001388 .word 0x00001388
8001b18: fffff8ff .word 0xfffff8ff
8001b1c: 08003248 .word 0x08003248
8001b20: 20000000 .word 0x20000000
08001b24 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001b24: b590 push {r4, r7, lr}
8001b26: b08f sub sp, #60 ; 0x3c
8001b28: af00 add r7, sp, #0
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
8001b2a: 2314 movs r3, #20
8001b2c: 18fb adds r3, r7, r3
8001b2e: 4a2b ldr r2, [pc, #172] ; (8001bdc <HAL_RCC_GetSysClockFreq+0xb8>)
8001b30: ca13 ldmia r2!, {r0, r1, r4}
8001b32: c313 stmia r3!, {r0, r1, r4}
8001b34: 6812 ldr r2, [r2, #0]
8001b36: 601a str r2, [r3, #0]
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
8001b38: 1d3b adds r3, r7, #4
8001b3a: 4a29 ldr r2, [pc, #164] ; (8001be0 <HAL_RCC_GetSysClockFreq+0xbc>)
8001b3c: ca13 ldmia r2!, {r0, r1, r4}
8001b3e: c313 stmia r3!, {r0, r1, r4}
8001b40: 6812 ldr r2, [r2, #0]
8001b42: 601a str r2, [r3, #0]
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8001b44: 2300 movs r3, #0
8001b46: 62fb str r3, [r7, #44] ; 0x2c
8001b48: 2300 movs r3, #0
8001b4a: 62bb str r3, [r7, #40] ; 0x28
8001b4c: 2300 movs r3, #0
8001b4e: 637b str r3, [r7, #52] ; 0x34
8001b50: 2300 movs r3, #0
8001b52: 627b str r3, [r7, #36] ; 0x24
uint32_t sysclockfreq = 0U;
8001b54: 2300 movs r3, #0
8001b56: 633b str r3, [r7, #48] ; 0x30
tmpreg = RCC->CFGR;
8001b58: 4b22 ldr r3, [pc, #136] ; (8001be4 <HAL_RCC_GetSysClockFreq+0xc0>)
8001b5a: 685b ldr r3, [r3, #4]
8001b5c: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8001b5e: 6afb ldr r3, [r7, #44] ; 0x2c
8001b60: 220c movs r2, #12
8001b62: 4013 ands r3, r2
8001b64: 2b04 cmp r3, #4
8001b66: d002 beq.n 8001b6e <HAL_RCC_GetSysClockFreq+0x4a>
8001b68: 2b08 cmp r3, #8
8001b6a: d003 beq.n 8001b74 <HAL_RCC_GetSysClockFreq+0x50>
8001b6c: e02d b.n 8001bca <HAL_RCC_GetSysClockFreq+0xa6>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8001b6e: 4b1e ldr r3, [pc, #120] ; (8001be8 <HAL_RCC_GetSysClockFreq+0xc4>)
8001b70: 633b str r3, [r7, #48] ; 0x30
break;
8001b72: e02d b.n 8001bd0 <HAL_RCC_GetSysClockFreq+0xac>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
8001b74: 6afb ldr r3, [r7, #44] ; 0x2c
8001b76: 0c9b lsrs r3, r3, #18
8001b78: 220f movs r2, #15
8001b7a: 4013 ands r3, r2
8001b7c: 2214 movs r2, #20
8001b7e: 18ba adds r2, r7, r2
8001b80: 5cd3 ldrb r3, [r2, r3]
8001b82: 627b str r3, [r7, #36] ; 0x24
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
8001b84: 4b17 ldr r3, [pc, #92] ; (8001be4 <HAL_RCC_GetSysClockFreq+0xc0>)
8001b86: 6adb ldr r3, [r3, #44] ; 0x2c
8001b88: 220f movs r2, #15
8001b8a: 4013 ands r3, r2
8001b8c: 1d3a adds r2, r7, #4
8001b8e: 5cd3 ldrb r3, [r2, r3]
8001b90: 62bb str r3, [r7, #40] ; 0x28
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
8001b92: 6afa ldr r2, [r7, #44] ; 0x2c
8001b94: 2380 movs r3, #128 ; 0x80
8001b96: 025b lsls r3, r3, #9
8001b98: 4013 ands r3, r2
8001b9a: d009 beq.n 8001bb0 <HAL_RCC_GetSysClockFreq+0x8c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8001b9c: 6ab9 ldr r1, [r7, #40] ; 0x28
8001b9e: 4812 ldr r0, [pc, #72] ; (8001be8 <HAL_RCC_GetSysClockFreq+0xc4>)
8001ba0: f7fe fabc bl 800011c <__udivsi3>
8001ba4: 0003 movs r3, r0
8001ba6: 001a movs r2, r3
8001ba8: 6a7b ldr r3, [r7, #36] ; 0x24
8001baa: 4353 muls r3, r2
8001bac: 637b str r3, [r7, #52] ; 0x34
8001bae: e009 b.n 8001bc4 <HAL_RCC_GetSysClockFreq+0xa0>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8001bb0: 6a79 ldr r1, [r7, #36] ; 0x24
8001bb2: 000a movs r2, r1
8001bb4: 0152 lsls r2, r2, #5
8001bb6: 1a52 subs r2, r2, r1
8001bb8: 0193 lsls r3, r2, #6
8001bba: 1a9b subs r3, r3, r2
8001bbc: 00db lsls r3, r3, #3
8001bbe: 185b adds r3, r3, r1
8001bc0: 021b lsls r3, r3, #8
8001bc2: 637b str r3, [r7, #52] ; 0x34
#endif
}
sysclockfreq = pllclk;
8001bc4: 6b7b ldr r3, [r7, #52] ; 0x34
8001bc6: 633b str r3, [r7, #48] ; 0x30
break;
8001bc8: e002 b.n 8001bd0 <HAL_RCC_GetSysClockFreq+0xac>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8001bca: 4b07 ldr r3, [pc, #28] ; (8001be8 <HAL_RCC_GetSysClockFreq+0xc4>)
8001bcc: 633b str r3, [r7, #48] ; 0x30
break;
8001bce: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
8001bd0: 6b3b ldr r3, [r7, #48] ; 0x30
}
8001bd2: 0018 movs r0, r3
8001bd4: 46bd mov sp, r7
8001bd6: b00f add sp, #60 ; 0x3c
8001bd8: bd90 pop {r4, r7, pc}
8001bda: 46c0 nop ; (mov r8, r8)
8001bdc: 08003228 .word 0x08003228
8001be0: 08003238 .word 0x08003238
8001be4: 40021000 .word 0x40021000
8001be8: 007a1200 .word 0x007a1200
08001bec <Send_to_595>:
char led_n:1;
char led_err:1;
}dis_buff;
void Send_to_595(char h,char l)
{
8001bec: b580 push {r7, lr}
8001bee: b084 sub sp, #16
8001bf0: af00 add r7, sp, #0
8001bf2: 0002 movs r2, r0
8001bf4: 1dfb adds r3, r7, #7
8001bf6: 701a strb r2, [r3, #0]
8001bf8: 1dbb adds r3, r7, #6
8001bfa: 1c0a adds r2, r1, #0
8001bfc: 701a strb r2, [r3, #0]
for(int a=0;a<8;a++)
8001bfe: 2300 movs r3, #0
8001c00: 60fb str r3, [r7, #12]
8001c02: e027 b.n 8001c54 <Send_to_595+0x68>
{
if((h<<a)&0x80)
8001c04: 1dfb adds r3, r7, #7
8001c06: 781a ldrb r2, [r3, #0]
8001c08: 68fb ldr r3, [r7, #12]
8001c0a: 409a lsls r2, r3
8001c0c: 0013 movs r3, r2
8001c0e: 2280 movs r2, #128 ; 0x80
8001c10: 4013 ands r3, r2
8001c12: d007 beq.n 8001c24 <Send_to_595+0x38>
{
HC595_DCK(1);
8001c14: 2390 movs r3, #144 ; 0x90
8001c16: 05db lsls r3, r3, #23
8001c18: 2201 movs r2, #1
8001c1a: 2108 movs r1, #8
8001c1c: 0018 movs r0, r3
8001c1e: f7ff fb7b bl 8001318 <HAL_GPIO_WritePin>
8001c22: e006 b.n 8001c32 <Send_to_595+0x46>
}else
{
HC595_DCK(0);
8001c24: 2390 movs r3, #144 ; 0x90
8001c26: 05db lsls r3, r3, #23
8001c28: 2200 movs r2, #0
8001c2a: 2108 movs r1, #8
8001c2c: 0018 movs r0, r3
8001c2e: f7ff fb73 bl 8001318 <HAL_GPIO_WritePin>
}
HC595_SCK(1);
8001c32: 2390 movs r3, #144 ; 0x90
8001c34: 05db lsls r3, r3, #23
8001c36: 2201 movs r2, #1
8001c38: 2120 movs r1, #32
8001c3a: 0018 movs r0, r3
8001c3c: f7ff fb6c bl 8001318 <HAL_GPIO_WritePin>
HC595_SCK(0);
8001c40: 2390 movs r3, #144 ; 0x90
8001c42: 05db lsls r3, r3, #23
8001c44: 2200 movs r2, #0
8001c46: 2120 movs r1, #32
8001c48: 0018 movs r0, r3
8001c4a: f7ff fb65 bl 8001318 <HAL_GPIO_WritePin>
for(int a=0;a<8;a++)
8001c4e: 68fb ldr r3, [r7, #12]
8001c50: 3301 adds r3, #1
8001c52: 60fb str r3, [r7, #12]
8001c54: 68fb ldr r3, [r7, #12]
8001c56: 2b07 cmp r3, #7
8001c58: ddd4 ble.n 8001c04 <Send_to_595+0x18>
}
for(int a=0;a<8;a++)
8001c5a: 2300 movs r3, #0
8001c5c: 60bb str r3, [r7, #8]
8001c5e: e027 b.n 8001cb0 <Send_to_595+0xc4>
{
if((l<<a)&0x80)
8001c60: 1dbb adds r3, r7, #6
8001c62: 781a ldrb r2, [r3, #0]
8001c64: 68bb ldr r3, [r7, #8]
8001c66: 409a lsls r2, r3
8001c68: 0013 movs r3, r2
8001c6a: 2280 movs r2, #128 ; 0x80
8001c6c: 4013 ands r3, r2
8001c6e: d007 beq.n 8001c80 <Send_to_595+0x94>
{
HC595_DCK(1);
8001c70: 2390 movs r3, #144 ; 0x90
8001c72: 05db lsls r3, r3, #23
8001c74: 2201 movs r2, #1
8001c76: 2108 movs r1, #8
8001c78: 0018 movs r0, r3
8001c7a: f7ff fb4d bl 8001318 <HAL_GPIO_WritePin>
8001c7e: e006 b.n 8001c8e <Send_to_595+0xa2>
}else
{
HC595_DCK(0);
8001c80: 2390 movs r3, #144 ; 0x90
8001c82: 05db lsls r3, r3, #23
8001c84: 2200 movs r2, #0
8001c86: 2108 movs r1, #8
8001c88: 0018 movs r0, r3
8001c8a: f7ff fb45 bl 8001318 <HAL_GPIO_WritePin>
}
HC595_SCK(1);
8001c8e: 2390 movs r3, #144 ; 0x90
8001c90: 05db lsls r3, r3, #23
8001c92: 2201 movs r2, #1
8001c94: 2120 movs r1, #32
8001c96: 0018 movs r0, r3
8001c98: f7ff fb3e bl 8001318 <HAL_GPIO_WritePin>
HC595_SCK(0);
8001c9c: 2390 movs r3, #144 ; 0x90
8001c9e: 05db lsls r3, r3, #23
8001ca0: 2200 movs r2, #0
8001ca2: 2120 movs r1, #32
8001ca4: 0018 movs r0, r3
8001ca6: f7ff fb37 bl 8001318 <HAL_GPIO_WritePin>
for(int a=0;a<8;a++)
8001caa: 68bb ldr r3, [r7, #8]
8001cac: 3301 adds r3, #1
8001cae: 60bb str r3, [r7, #8]
8001cb0: 68bb ldr r3, [r7, #8]
8001cb2: 2b07 cmp r3, #7
8001cb4: ddd4 ble.n 8001c60 <Send_to_595+0x74>
}
HC595_RCK(1);
8001cb6: 2390 movs r3, #144 ; 0x90
8001cb8: 05db lsls r3, r3, #23
8001cba: 2201 movs r2, #1
8001cbc: 2110 movs r1, #16
8001cbe: 0018 movs r0, r3
8001cc0: f7ff fb2a bl 8001318 <HAL_GPIO_WritePin>
HC595_RCK(0);
8001cc4: 2390 movs r3, #144 ; 0x90
8001cc6: 05db lsls r3, r3, #23
8001cc8: 2200 movs r2, #0
8001cca: 2110 movs r1, #16
8001ccc: 0018 movs r0, r3
8001cce: f7ff fb23 bl 8001318 <HAL_GPIO_WritePin>
}
8001cd2: 46c0 nop ; (mov r8, r8)
8001cd4: 46bd mov sp, r7
8001cd6: b004 add sp, #16
8001cd8: bd80 pop {r7, pc}
...
08001cdc <display>:
void display()
{
8001cdc: b580 push {r7, lr}
8001cde: b082 sub sp, #8
8001ce0: af00 add r7, sp, #0
char h_buff=0,l_buff=0;
8001ce2: 1dfb adds r3, r7, #7
8001ce4: 2200 movs r2, #0
8001ce6: 701a strb r2, [r3, #0]
8001ce8: 1dbb adds r3, r7, #6
8001cea: 2200 movs r2, #0
8001cec: 701a strb r2, [r3, #0]
Send_to_595(h_buff,l_buff);
8001cee: 1dbb adds r3, r7, #6
8001cf0: 781a ldrb r2, [r3, #0]
8001cf2: 1dfb adds r3, r7, #7
8001cf4: 781b ldrb r3, [r3, #0]
8001cf6: 0011 movs r1, r2
8001cf8: 0018 movs r0, r3
8001cfa: f7ff ff77 bl 8001bec <Send_to_595>
h_buff=0,l_buff=0;
8001cfe: 1dfb adds r3, r7, #7
8001d00: 2200 movs r2, #0
8001d02: 701a strb r2, [r3, #0]
8001d04: 1dbb adds r3, r7, #6
8001d06: 2200 movs r2, #0
8001d08: 701a strb r2, [r3, #0]
h_buff=~0x01;
8001d0a: 1dfb adds r3, r7, #7
8001d0c: 22fe movs r2, #254 ; 0xfe
8001d0e: 701a strb r2, [r3, #0]
l_buff=d_num_data[0][dis_buff.d_num[0]];
8001d10: 4b63 ldr r3, [pc, #396] ; (8001ea0 <display+0x1c4>)
8001d12: 781b ldrb r3, [r3, #0]
8001d14: 0019 movs r1, r3
8001d16: 1dbb adds r3, r7, #6
8001d18: 4a62 ldr r2, [pc, #392] ; (8001ea4 <display+0x1c8>)
8001d1a: 5c52 ldrb r2, [r2, r1]
8001d1c: 701a strb r2, [r3, #0]
if(dis_buff.dot1==1)
8001d1e: 4b60 ldr r3, [pc, #384] ; (8001ea0 <display+0x1c4>)
8001d20: 791b ldrb r3, [r3, #4]
8001d22: 2201 movs r2, #1
8001d24: 4013 ands r3, r2
8001d26: b2db uxtb r3, r3
8001d28: 2b00 cmp r3, #0
8001d2a: d006 beq.n 8001d3a <display+0x5e>
{
l_buff|=0x80;
8001d2c: 1dbb adds r3, r7, #6
8001d2e: 1dba adds r2, r7, #6
8001d30: 7812 ldrb r2, [r2, #0]
8001d32: 2180 movs r1, #128 ; 0x80
8001d34: 4249 negs r1, r1
8001d36: 430a orrs r2, r1
8001d38: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001d3a: 1dbb adds r3, r7, #6
8001d3c: 781a ldrb r2, [r3, #0]
8001d3e: 1dfb adds r3, r7, #7
8001d40: 781b ldrb r3, [r3, #0]
8001d42: 0011 movs r1, r2
8001d44: 0018 movs r0, r3
8001d46: f7ff ff51 bl 8001bec <Send_to_595>
h_buff=0,l_buff=0;
8001d4a: 1dfb adds r3, r7, #7
8001d4c: 2200 movs r2, #0
8001d4e: 701a strb r2, [r3, #0]
8001d50: 1dbb adds r3, r7, #6
8001d52: 2200 movs r2, #0
8001d54: 701a strb r2, [r3, #0]
h_buff=~0x80;
8001d56: 1dfb adds r3, r7, #7
8001d58: 227f movs r2, #127 ; 0x7f
8001d5a: 701a strb r2, [r3, #0]
l_buff=d_num_data[1][dis_buff.d_num[1]];
8001d5c: 4b50 ldr r3, [pc, #320] ; (8001ea0 <display+0x1c4>)
8001d5e: 785b ldrb r3, [r3, #1]
8001d60: 0019 movs r1, r3
8001d62: 1dbb adds r3, r7, #6
8001d64: 4a4f ldr r2, [pc, #316] ; (8001ea4 <display+0x1c8>)
8001d66: 1852 adds r2, r2, r1
8001d68: 7a92 ldrb r2, [r2, #10]
8001d6a: 701a strb r2, [r3, #0]
if(dis_buff.dot2==1)
8001d6c: 4b4c ldr r3, [pc, #304] ; (8001ea0 <display+0x1c4>)
8001d6e: 791b ldrb r3, [r3, #4]
8001d70: 2202 movs r2, #2
8001d72: 4013 ands r3, r2
8001d74: b2db uxtb r3, r3
8001d76: 2b00 cmp r3, #0
8001d78: d005 beq.n 8001d86 <display+0xaa>
{
l_buff|=0x10;
8001d7a: 1dbb adds r3, r7, #6
8001d7c: 1dba adds r2, r7, #6
8001d7e: 7812 ldrb r2, [r2, #0]
8001d80: 2110 movs r1, #16
8001d82: 430a orrs r2, r1
8001d84: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001d86: 1dbb adds r3, r7, #6
8001d88: 781a ldrb r2, [r3, #0]
8001d8a: 1dfb adds r3, r7, #7
8001d8c: 781b ldrb r3, [r3, #0]
8001d8e: 0011 movs r1, r2
8001d90: 0018 movs r0, r3
8001d92: f7ff ff2b bl 8001bec <Send_to_595>
h_buff=0,l_buff=0;
8001d96: 1dfb adds r3, r7, #7
8001d98: 2200 movs r2, #0
8001d9a: 701a strb r2, [r3, #0]
8001d9c: 1dbb adds r3, r7, #6
8001d9e: 2200 movs r2, #0
8001da0: 701a strb r2, [r3, #0]
h_buff=~0x40;
8001da2: 1dfb adds r3, r7, #7
8001da4: 22bf movs r2, #191 ; 0xbf
8001da6: 701a strb r2, [r3, #0]
l_buff=d_num_data[0][dis_buff.d_num[2]];
8001da8: 4b3d ldr r3, [pc, #244] ; (8001ea0 <display+0x1c4>)
8001daa: 789b ldrb r3, [r3, #2]
8001dac: 0019 movs r1, r3
8001dae: 1dbb adds r3, r7, #6
8001db0: 4a3c ldr r2, [pc, #240] ; (8001ea4 <display+0x1c8>)
8001db2: 5c52 ldrb r2, [r2, r1]
8001db4: 701a strb r2, [r3, #0]
if(dis_buff.dot3==1)
8001db6: 4b3a ldr r3, [pc, #232] ; (8001ea0 <display+0x1c4>)
8001db8: 791b ldrb r3, [r3, #4]
8001dba: 2204 movs r2, #4
8001dbc: 4013 ands r3, r2
8001dbe: b2db uxtb r3, r3
8001dc0: 2b00 cmp r3, #0
8001dc2: d006 beq.n 8001dd2 <display+0xf6>
{
l_buff|=0x80;
8001dc4: 1dbb adds r3, r7, #6
8001dc6: 1dba adds r2, r7, #6
8001dc8: 7812 ldrb r2, [r2, #0]
8001dca: 2180 movs r1, #128 ; 0x80
8001dcc: 4249 negs r1, r1
8001dce: 430a orrs r2, r1
8001dd0: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001dd2: 1dbb adds r3, r7, #6
8001dd4: 781a ldrb r2, [r3, #0]
8001dd6: 1dfb adds r3, r7, #7
8001dd8: 781b ldrb r3, [r3, #0]
8001dda: 0011 movs r1, r2
8001ddc: 0018 movs r0, r3
8001dde: f7ff ff05 bl 8001bec <Send_to_595>
h_buff=0,l_buff=0;
8001de2: 1dfb adds r3, r7, #7
8001de4: 2200 movs r2, #0
8001de6: 701a strb r2, [r3, #0]
8001de8: 1dbb adds r3, r7, #6
8001dea: 2200 movs r2, #0
8001dec: 701a strb r2, [r3, #0]
h_buff=0xC1;
8001dee: 1dfb adds r3, r7, #7
8001df0: 22c1 movs r2, #193 ; 0xc1
8001df2: 701a strb r2, [r3, #0]
l_buff=d_num_data[1][dis_buff.d_num[3]];
8001df4: 4b2a ldr r3, [pc, #168] ; (8001ea0 <display+0x1c4>)
8001df6: 78db ldrb r3, [r3, #3]
8001df8: 0019 movs r1, r3
8001dfa: 1dbb adds r3, r7, #6
8001dfc: 4a29 ldr r2, [pc, #164] ; (8001ea4 <display+0x1c8>)
8001dfe: 1852 adds r2, r2, r1
8001e00: 7a92 ldrb r2, [r2, #10]
8001e02: 701a strb r2, [r3, #0]
if(dis_buff.dot4==1)
8001e04: 4b26 ldr r3, [pc, #152] ; (8001ea0 <display+0x1c4>)
8001e06: 791b ldrb r3, [r3, #4]
8001e08: 2208 movs r2, #8
8001e0a: 4013 ands r3, r2
8001e0c: b2db uxtb r3, r3
8001e0e: 2b00 cmp r3, #0
8001e10: d005 beq.n 8001e1e <display+0x142>
{
l_buff|=0x10;
8001e12: 1dbb adds r3, r7, #6
8001e14: 1dba adds r2, r7, #6
8001e16: 7812 ldrb r2, [r2, #0]
8001e18: 2110 movs r1, #16
8001e1a: 430a orrs r2, r1
8001e1c: 701a strb r2, [r3, #0]
}
if(dis_buff.led_run==1)
8001e1e: 4b20 ldr r3, [pc, #128] ; (8001ea0 <display+0x1c4>)
8001e20: 791b ldrb r3, [r3, #4]
8001e22: 2210 movs r2, #16
8001e24: 4013 ands r3, r2
8001e26: b2db uxtb r3, r3
8001e28: 2b00 cmp r3, #0
8001e2a: d005 beq.n 8001e38 <display+0x15c>
{
h_buff|=0x10;
8001e2c: 1dfb adds r3, r7, #7
8001e2e: 1dfa adds r2, r7, #7
8001e30: 7812 ldrb r2, [r2, #0]
8001e32: 2110 movs r1, #16
8001e34: 430a orrs r2, r1
8001e36: 701a strb r2, [r3, #0]
}
if(dis_buff.led_err==1)
8001e38: 4b19 ldr r3, [pc, #100] ; (8001ea0 <display+0x1c4>)
8001e3a: 791b ldrb r3, [r3, #4]
8001e3c: 227f movs r2, #127 ; 0x7f
8001e3e: 4393 bics r3, r2
8001e40: b2db uxtb r3, r3
8001e42: 2b00 cmp r3, #0
8001e44: d005 beq.n 8001e52 <display+0x176>
{
h_buff|=0x08;
8001e46: 1dfb adds r3, r7, #7
8001e48: 1dfa adds r2, r7, #7
8001e4a: 7812 ldrb r2, [r2, #0]
8001e4c: 2108 movs r1, #8
8001e4e: 430a orrs r2, r1
8001e50: 701a strb r2, [r3, #0]
}
if(dis_buff.led_n==1)
8001e52: 4b13 ldr r3, [pc, #76] ; (8001ea0 <display+0x1c4>)
8001e54: 791b ldrb r3, [r3, #4]
8001e56: 2240 movs r2, #64 ; 0x40
8001e58: 4013 ands r3, r2
8001e5a: b2db uxtb r3, r3
8001e5c: 2b00 cmp r3, #0
8001e5e: d005 beq.n 8001e6c <display+0x190>
{
h_buff|=0x04;
8001e60: 1dfb adds r3, r7, #7
8001e62: 1dfa adds r2, r7, #7
8001e64: 7812 ldrb r2, [r2, #0]
8001e66: 2104 movs r1, #4
8001e68: 430a orrs r2, r1
8001e6a: 701a strb r2, [r3, #0]
}
if(dis_buff.led_p==1)
8001e6c: 4b0c ldr r3, [pc, #48] ; (8001ea0 <display+0x1c4>)
8001e6e: 791b ldrb r3, [r3, #4]
8001e70: 2220 movs r2, #32
8001e72: 4013 ands r3, r2
8001e74: b2db uxtb r3, r3
8001e76: 2b00 cmp r3, #0
8001e78: d005 beq.n 8001e86 <display+0x1aa>
{
h_buff|=0x02;
8001e7a: 1dfb adds r3, r7, #7
8001e7c: 1dfa adds r2, r7, #7
8001e7e: 7812 ldrb r2, [r2, #0]
8001e80: 2102 movs r1, #2
8001e82: 430a orrs r2, r1
8001e84: 701a strb r2, [r3, #0]
}
Send_to_595(h_buff,l_buff);
8001e86: 1dbb adds r3, r7, #6
8001e88: 781a ldrb r2, [r3, #0]
8001e8a: 1dfb adds r3, r7, #7
8001e8c: 781b ldrb r3, [r3, #0]
8001e8e: 0011 movs r1, r2
8001e90: 0018 movs r0, r3
8001e92: f7ff feab bl 8001bec <Send_to_595>
}
8001e96: 46c0 nop ; (mov r8, r8)
8001e98: 46bd mov sp, r7
8001e9a: b002 add sp, #8
8001e9c: bd80 pop {r7, pc}
8001e9e: 46c0 nop ; (mov r8, r8)
8001ea0: 200000dc .word 0x200000dc
8001ea4: 08003258 .word 0x08003258
08001ea8 <mymain>:
void mymain()
{
8001ea8: b580 push {r7, lr}
8001eaa: b082 sub sp, #8
8001eac: af00 add r7, sp, #0
uint32_t runtime=0;
8001eae: 2300 movs r3, #0
8001eb0: 607b str r3, [r7, #4]
MOTA(0);
8001eb2: 4b95 ldr r3, [pc, #596] ; (8002108 <mymain+0x260>)
8001eb4: 2200 movs r2, #0
8001eb6: 2101 movs r1, #1
8001eb8: 0018 movs r0, r3
8001eba: f7ff fa2d bl 8001318 <HAL_GPIO_WritePin>
MOTB(0);
8001ebe: 4b92 ldr r3, [pc, #584] ; (8002108 <mymain+0x260>)
8001ec0: 2200 movs r2, #0
8001ec2: 2102 movs r1, #2
8001ec4: 0018 movs r0, r3
8001ec6: f7ff fa27 bl 8001318 <HAL_GPIO_WritePin>
HC595_DCK(0);
8001eca: 2390 movs r3, #144 ; 0x90
8001ecc: 05db lsls r3, r3, #23
8001ece: 2200 movs r2, #0
8001ed0: 2108 movs r1, #8
8001ed2: 0018 movs r0, r3
8001ed4: f7ff fa20 bl 8001318 <HAL_GPIO_WritePin>
HC595_RCK(0);
8001ed8: 2390 movs r3, #144 ; 0x90
8001eda: 05db lsls r3, r3, #23
8001edc: 2200 movs r2, #0
8001ede: 2110 movs r1, #16
8001ee0: 0018 movs r0, r3
8001ee2: f7ff fa19 bl 8001318 <HAL_GPIO_WritePin>
HC595_SCK(0);
8001ee6: 2390 movs r3, #144 ; 0x90
8001ee8: 05db lsls r3, r3, #23
8001eea: 2200 movs r2, #0
8001eec: 2120 movs r1, #32
8001eee: 0018 movs r0, r3
8001ef0: f7ff fa12 bl 8001318 <HAL_GPIO_WritePin>
while(1)
{
if(HAL_GetTick()>runtime)
8001ef4: f7fe fdac bl 8000a50 <HAL_GetTick>
8001ef8: 0002 movs r2, r0
8001efa: 687b ldr r3, [r7, #4]
8001efc: 4293 cmp r3, r2
8001efe: d300 bcc.n 8001f02 <mymain+0x5a>
8001f00: e0ff b.n 8002102 <mymain+0x25a>
{
runtime+=1000;
8001f02: 687b ldr r3, [r7, #4]
8001f04: 22fa movs r2, #250 ; 0xfa
8001f06: 0092 lsls r2, r2, #2
8001f08: 4694 mov ip, r2
8001f0a: 4463 add r3, ip
8001f0c: 607b str r3, [r7, #4]
dis_buff.d_num[0]=rand()%10;
8001f0e: f000 f933 bl 8002178 <rand>
8001f12: 0003 movs r3, r0
8001f14: 210a movs r1, #10
8001f16: 0018 movs r0, r3
8001f18: f7fe fa70 bl 80003fc <__aeabi_idivmod>
8001f1c: 000b movs r3, r1
8001f1e: b2da uxtb r2, r3
8001f20: 4b7a ldr r3, [pc, #488] ; (800210c <mymain+0x264>)
8001f22: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=rand()%10;
8001f24: f000 f928 bl 8002178 <rand>
8001f28: 0003 movs r3, r0
8001f2a: 210a movs r1, #10
8001f2c: 0018 movs r0, r3
8001f2e: f7fe fa65 bl 80003fc <__aeabi_idivmod>
8001f32: 000b movs r3, r1
8001f34: b2da uxtb r2, r3
8001f36: 4b75 ldr r3, [pc, #468] ; (800210c <mymain+0x264>)
8001f38: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=rand()%10;
8001f3a: f000 f91d bl 8002178 <rand>
8001f3e: 0003 movs r3, r0
8001f40: 210a movs r1, #10
8001f42: 0018 movs r0, r3
8001f44: f7fe fa5a bl 80003fc <__aeabi_idivmod>
8001f48: 000b movs r3, r1
8001f4a: b2da uxtb r2, r3
8001f4c: 4b6f ldr r3, [pc, #444] ; (800210c <mymain+0x264>)
8001f4e: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=rand()%10;
8001f50: f000 f912 bl 8002178 <rand>
8001f54: 0003 movs r3, r0
8001f56: 210a movs r1, #10
8001f58: 0018 movs r0, r3
8001f5a: f7fe fa4f bl 80003fc <__aeabi_idivmod>
8001f5e: 000b movs r3, r1
8001f60: b2da uxtb r2, r3
8001f62: 4b6a ldr r3, [pc, #424] ; (800210c <mymain+0x264>)
8001f64: 70da strb r2, [r3, #3]
dis_buff.dot1=rand()%2;
8001f66: f000 f907 bl 8002178 <rand>
8001f6a: 0003 movs r3, r0
8001f6c: 4a68 ldr r2, [pc, #416] ; (8002110 <mymain+0x268>)
8001f6e: 4013 ands r3, r2
8001f70: d504 bpl.n 8001f7c <mymain+0xd4>
8001f72: 3b01 subs r3, #1
8001f74: 2202 movs r2, #2
8001f76: 4252 negs r2, r2
8001f78: 4313 orrs r3, r2
8001f7a: 3301 adds r3, #1
8001f7c: 1c1a adds r2, r3, #0
8001f7e: 2301 movs r3, #1
8001f80: 4013 ands r3, r2
8001f82: b2da uxtb r2, r3
8001f84: 4b61 ldr r3, [pc, #388] ; (800210c <mymain+0x264>)
8001f86: 2101 movs r1, #1
8001f88: 400a ands r2, r1
8001f8a: 0010 movs r0, r2
8001f8c: 791a ldrb r2, [r3, #4]
8001f8e: 2101 movs r1, #1
8001f90: 438a bics r2, r1
8001f92: 1c11 adds r1, r2, #0
8001f94: 1c02 adds r2, r0, #0
8001f96: 430a orrs r2, r1
8001f98: 711a strb r2, [r3, #4]
dis_buff.dot2=rand()%2;
8001f9a: f000 f8ed bl 8002178 <rand>
8001f9e: 0003 movs r3, r0
8001fa0: 4a5b ldr r2, [pc, #364] ; (8002110 <mymain+0x268>)
8001fa2: 4013 ands r3, r2
8001fa4: d504 bpl.n 8001fb0 <mymain+0x108>
8001fa6: 3b01 subs r3, #1
8001fa8: 2202 movs r2, #2
8001faa: 4252 negs r2, r2
8001fac: 4313 orrs r3, r2
8001fae: 3301 adds r3, #1
8001fb0: 1c1a adds r2, r3, #0
8001fb2: 2301 movs r3, #1
8001fb4: 4013 ands r3, r2
8001fb6: b2da uxtb r2, r3
8001fb8: 4b54 ldr r3, [pc, #336] ; (800210c <mymain+0x264>)
8001fba: 2101 movs r1, #1
8001fbc: 400a ands r2, r1
8001fbe: 1890 adds r0, r2, r2
8001fc0: 791a ldrb r2, [r3, #4]
8001fc2: 2102 movs r1, #2
8001fc4: 438a bics r2, r1
8001fc6: 1c11 adds r1, r2, #0
8001fc8: 1c02 adds r2, r0, #0
8001fca: 430a orrs r2, r1
8001fcc: 711a strb r2, [r3, #4]
dis_buff.dot3=rand()%2;
8001fce: f000 f8d3 bl 8002178 <rand>
8001fd2: 0003 movs r3, r0
8001fd4: 4a4e ldr r2, [pc, #312] ; (8002110 <mymain+0x268>)
8001fd6: 4013 ands r3, r2
8001fd8: d504 bpl.n 8001fe4 <mymain+0x13c>
8001fda: 3b01 subs r3, #1
8001fdc: 2202 movs r2, #2
8001fde: 4252 negs r2, r2
8001fe0: 4313 orrs r3, r2
8001fe2: 3301 adds r3, #1
8001fe4: 1c1a adds r2, r3, #0
8001fe6: 2301 movs r3, #1
8001fe8: 4013 ands r3, r2
8001fea: b2da uxtb r2, r3
8001fec: 4b47 ldr r3, [pc, #284] ; (800210c <mymain+0x264>)
8001fee: 2101 movs r1, #1
8001ff0: 400a ands r2, r1
8001ff2: 0090 lsls r0, r2, #2
8001ff4: 791a ldrb r2, [r3, #4]
8001ff6: 2104 movs r1, #4
8001ff8: 438a bics r2, r1
8001ffa: 1c11 adds r1, r2, #0
8001ffc: 1c02 adds r2, r0, #0
8001ffe: 430a orrs r2, r1
8002000: 711a strb r2, [r3, #4]
dis_buff.dot4=rand()%2;
8002002: f000 f8b9 bl 8002178 <rand>
8002006: 0003 movs r3, r0
8002008: 4a41 ldr r2, [pc, #260] ; (8002110 <mymain+0x268>)
800200a: 4013 ands r3, r2
800200c: d504 bpl.n 8002018 <mymain+0x170>
800200e: 3b01 subs r3, #1
8002010: 2202 movs r2, #2
8002012: 4252 negs r2, r2
8002014: 4313 orrs r3, r2
8002016: 3301 adds r3, #1
8002018: 1c1a adds r2, r3, #0
800201a: 2301 movs r3, #1
800201c: 4013 ands r3, r2
800201e: b2da uxtb r2, r3
8002020: 4b3a ldr r3, [pc, #232] ; (800210c <mymain+0x264>)
8002022: 2101 movs r1, #1
8002024: 400a ands r2, r1
8002026: 00d0 lsls r0, r2, #3
8002028: 791a ldrb r2, [r3, #4]
800202a: 2108 movs r1, #8
800202c: 438a bics r2, r1
800202e: 1c11 adds r1, r2, #0
8002030: 1c02 adds r2, r0, #0
8002032: 430a orrs r2, r1
8002034: 711a strb r2, [r3, #4]
dis_buff.led_err=rand()%2;
8002036: f000 f89f bl 8002178 <rand>
800203a: 0003 movs r3, r0
800203c: 4a34 ldr r2, [pc, #208] ; (8002110 <mymain+0x268>)
800203e: 4013 ands r3, r2
8002040: d504 bpl.n 800204c <mymain+0x1a4>
8002042: 3b01 subs r3, #1
8002044: 2202 movs r2, #2
8002046: 4252 negs r2, r2
8002048: 4313 orrs r3, r2
800204a: 3301 adds r3, #1
800204c: 1c1a adds r2, r3, #0
800204e: 2301 movs r3, #1
8002050: 4013 ands r3, r2
8002052: b2da uxtb r2, r3
8002054: 4b2d ldr r3, [pc, #180] ; (800210c <mymain+0x264>)
8002056: 01d0 lsls r0, r2, #7
8002058: 791a ldrb r2, [r3, #4]
800205a: 217f movs r1, #127 ; 0x7f
800205c: 400a ands r2, r1
800205e: 1c11 adds r1, r2, #0
8002060: 1c02 adds r2, r0, #0
8002062: 430a orrs r2, r1
8002064: 711a strb r2, [r3, #4]
dis_buff.led_n=rand()%2;
8002066: f000 f887 bl 8002178 <rand>
800206a: 0003 movs r3, r0
800206c: 4a28 ldr r2, [pc, #160] ; (8002110 <mymain+0x268>)
800206e: 4013 ands r3, r2
8002070: d504 bpl.n 800207c <mymain+0x1d4>
8002072: 3b01 subs r3, #1
8002074: 2202 movs r2, #2
8002076: 4252 negs r2, r2
8002078: 4313 orrs r3, r2
800207a: 3301 adds r3, #1
800207c: 1c1a adds r2, r3, #0
800207e: 2301 movs r3, #1
8002080: 4013 ands r3, r2
8002082: b2da uxtb r2, r3
8002084: 4b21 ldr r3, [pc, #132] ; (800210c <mymain+0x264>)
8002086: 2101 movs r1, #1
8002088: 400a ands r2, r1
800208a: 0190 lsls r0, r2, #6
800208c: 791a ldrb r2, [r3, #4]
800208e: 2140 movs r1, #64 ; 0x40
8002090: 438a bics r2, r1
8002092: 1c11 adds r1, r2, #0
8002094: 1c02 adds r2, r0, #0
8002096: 430a orrs r2, r1
8002098: 711a strb r2, [r3, #4]
dis_buff.led_p=rand()%2;
800209a: f000 f86d bl 8002178 <rand>
800209e: 0003 movs r3, r0
80020a0: 4a1b ldr r2, [pc, #108] ; (8002110 <mymain+0x268>)
80020a2: 4013 ands r3, r2
80020a4: d504 bpl.n 80020b0 <mymain+0x208>
80020a6: 3b01 subs r3, #1
80020a8: 2202 movs r2, #2
80020aa: 4252 negs r2, r2
80020ac: 4313 orrs r3, r2
80020ae: 3301 adds r3, #1
80020b0: 1c1a adds r2, r3, #0
80020b2: 2301 movs r3, #1
80020b4: 4013 ands r3, r2
80020b6: b2da uxtb r2, r3
80020b8: 4b14 ldr r3, [pc, #80] ; (800210c <mymain+0x264>)
80020ba: 2101 movs r1, #1
80020bc: 400a ands r2, r1
80020be: 0150 lsls r0, r2, #5
80020c0: 791a ldrb r2, [r3, #4]
80020c2: 2120 movs r1, #32
80020c4: 438a bics r2, r1
80020c6: 1c11 adds r1, r2, #0
80020c8: 1c02 adds r2, r0, #0
80020ca: 430a orrs r2, r1
80020cc: 711a strb r2, [r3, #4]
dis_buff.led_run=rand()%2;
80020ce: f000 f853 bl 8002178 <rand>
80020d2: 0003 movs r3, r0
80020d4: 4a0e ldr r2, [pc, #56] ; (8002110 <mymain+0x268>)
80020d6: 4013 ands r3, r2
80020d8: d504 bpl.n 80020e4 <mymain+0x23c>
80020da: 3b01 subs r3, #1
80020dc: 2202 movs r2, #2
80020de: 4252 negs r2, r2
80020e0: 4313 orrs r3, r2
80020e2: 3301 adds r3, #1
80020e4: 1c1a adds r2, r3, #0
80020e6: 2301 movs r3, #1
80020e8: 4013 ands r3, r2
80020ea: b2da uxtb r2, r3
80020ec: 4b07 ldr r3, [pc, #28] ; (800210c <mymain+0x264>)
80020ee: 2101 movs r1, #1
80020f0: 400a ands r2, r1
80020f2: 0110 lsls r0, r2, #4
80020f4: 791a ldrb r2, [r3, #4]
80020f6: 2110 movs r1, #16
80020f8: 438a bics r2, r1
80020fa: 1c11 adds r1, r2, #0
80020fc: 1c02 adds r2, r0, #0
80020fe: 430a orrs r2, r1
8002100: 711a strb r2, [r3, #4]
}
display();
8002102: f7ff fdeb bl 8001cdc <display>
if(HAL_GetTick()>runtime)
8002106: e6f5 b.n 8001ef4 <mymain+0x4c>
8002108: 48001400 .word 0x48001400
800210c: 200000dc .word 0x200000dc
8002110: 80000001 .word 0x80000001
08002114 <__errno>:
8002114: 4b01 ldr r3, [pc, #4] ; (800211c <__errno+0x8>)
8002116: 6818 ldr r0, [r3, #0]
8002118: 4770 bx lr
800211a: 46c0 nop ; (mov r8, r8)
800211c: 2000000c .word 0x2000000c
08002120 <__libc_init_array>:
8002120: b570 push {r4, r5, r6, lr}
8002122: 2600 movs r6, #0
8002124: 4d0c ldr r5, [pc, #48] ; (8002158 <__libc_init_array+0x38>)
8002126: 4c0d ldr r4, [pc, #52] ; (800215c <__libc_init_array+0x3c>)
8002128: 1b64 subs r4, r4, r5
800212a: 10a4 asrs r4, r4, #2
800212c: 42a6 cmp r6, r4
800212e: d109 bne.n 8002144 <__libc_init_array+0x24>
8002130: 2600 movs r6, #0
8002132: f001 f86d bl 8003210 <_init>
8002136: 4d0a ldr r5, [pc, #40] ; (8002160 <__libc_init_array+0x40>)
8002138: 4c0a ldr r4, [pc, #40] ; (8002164 <__libc_init_array+0x44>)
800213a: 1b64 subs r4, r4, r5
800213c: 10a4 asrs r4, r4, #2
800213e: 42a6 cmp r6, r4
8002140: d105 bne.n 800214e <__libc_init_array+0x2e>
8002142: bd70 pop {r4, r5, r6, pc}
8002144: 00b3 lsls r3, r6, #2
8002146: 58eb ldr r3, [r5, r3]
8002148: 4798 blx r3
800214a: 3601 adds r6, #1
800214c: e7ee b.n 800212c <__libc_init_array+0xc>
800214e: 00b3 lsls r3, r6, #2
8002150: 58eb ldr r3, [r5, r3]
8002152: 4798 blx r3
8002154: 3601 adds r6, #1
8002156: e7f2 b.n 800213e <__libc_init_array+0x1e>
8002158: 080033b8 .word 0x080033b8
800215c: 080033b8 .word 0x080033b8
8002160: 080033b8 .word 0x080033b8
8002164: 080033bc .word 0x080033bc
08002168 <memset>:
8002168: 0003 movs r3, r0
800216a: 1882 adds r2, r0, r2
800216c: 4293 cmp r3, r2
800216e: d100 bne.n 8002172 <memset+0xa>
8002170: 4770 bx lr
8002172: 7019 strb r1, [r3, #0]
8002174: 3301 adds r3, #1
8002176: e7f9 b.n 800216c <memset+0x4>
08002178 <rand>:
8002178: 4b16 ldr r3, [pc, #88] ; (80021d4 <rand+0x5c>)
800217a: b510 push {r4, lr}
800217c: 681c ldr r4, [r3, #0]
800217e: 6ba3 ldr r3, [r4, #56] ; 0x38
8002180: 2b00 cmp r3, #0
8002182: d116 bne.n 80021b2 <rand+0x3a>
8002184: 2018 movs r0, #24
8002186: f000 f863 bl 8002250 <malloc>
800218a: 1e02 subs r2, r0, #0
800218c: 63a0 str r0, [r4, #56] ; 0x38
800218e: d104 bne.n 800219a <rand+0x22>
8002190: 214e movs r1, #78 ; 0x4e
8002192: 4b11 ldr r3, [pc, #68] ; (80021d8 <rand+0x60>)
8002194: 4811 ldr r0, [pc, #68] ; (80021dc <rand+0x64>)
8002196: f000 f82d bl 80021f4 <__assert_func>
800219a: 4b11 ldr r3, [pc, #68] ; (80021e0 <rand+0x68>)
800219c: 2100 movs r1, #0
800219e: 6003 str r3, [r0, #0]
80021a0: 4b10 ldr r3, [pc, #64] ; (80021e4 <rand+0x6c>)
80021a2: 6043 str r3, [r0, #4]
80021a4: 4b10 ldr r3, [pc, #64] ; (80021e8 <rand+0x70>)
80021a6: 6083 str r3, [r0, #8]
80021a8: 230b movs r3, #11
80021aa: 8183 strh r3, [r0, #12]
80021ac: 2001 movs r0, #1
80021ae: 6110 str r0, [r2, #16]
80021b0: 6151 str r1, [r2, #20]
80021b2: 6ba4 ldr r4, [r4, #56] ; 0x38
80021b4: 4a0d ldr r2, [pc, #52] ; (80021ec <rand+0x74>)
80021b6: 6920 ldr r0, [r4, #16]
80021b8: 6961 ldr r1, [r4, #20]
80021ba: 4b0d ldr r3, [pc, #52] ; (80021f0 <rand+0x78>)
80021bc: f7fe f924 bl 8000408 <__aeabi_lmul>
80021c0: 2201 movs r2, #1
80021c2: 2300 movs r3, #0
80021c4: 1880 adds r0, r0, r2
80021c6: 4159 adcs r1, r3
80021c8: 6120 str r0, [r4, #16]
80021ca: 6161 str r1, [r4, #20]
80021cc: 0048 lsls r0, r1, #1
80021ce: 0840 lsrs r0, r0, #1
80021d0: bd10 pop {r4, pc}
80021d2: 46c0 nop ; (mov r8, r8)
80021d4: 2000000c .word 0x2000000c
80021d8: 08003270 .word 0x08003270
80021dc: 08003287 .word 0x08003287
80021e0: abcd330e .word 0xabcd330e
80021e4: e66d1234 .word 0xe66d1234
80021e8: 0005deec .word 0x0005deec
80021ec: 4c957f2d .word 0x4c957f2d
80021f0: 5851f42d .word 0x5851f42d
080021f4 <__assert_func>:
80021f4: b530 push {r4, r5, lr}
80021f6: 0014 movs r4, r2
80021f8: 001a movs r2, r3
80021fa: 4b09 ldr r3, [pc, #36] ; (8002220 <__assert_func+0x2c>)
80021fc: 0005 movs r5, r0
80021fe: 681b ldr r3, [r3, #0]
8002200: b085 sub sp, #20
8002202: 68d8 ldr r0, [r3, #12]
8002204: 4b07 ldr r3, [pc, #28] ; (8002224 <__assert_func+0x30>)
8002206: 2c00 cmp r4, #0
8002208: d101 bne.n 800220e <__assert_func+0x1a>
800220a: 4b07 ldr r3, [pc, #28] ; (8002228 <__assert_func+0x34>)
800220c: 001c movs r4, r3
800220e: 9301 str r3, [sp, #4]
8002210: 9100 str r1, [sp, #0]
8002212: 002b movs r3, r5
8002214: 4905 ldr r1, [pc, #20] ; (800222c <__assert_func+0x38>)
8002216: 9402 str r4, [sp, #8]
8002218: f000 f80a bl 8002230 <fiprintf>
800221c: f000 fc8e bl 8002b3c <abort>
8002220: 2000000c .word 0x2000000c
8002224: 080032e6 .word 0x080032e6
8002228: 08003321 .word 0x08003321
800222c: 080032f3 .word 0x080032f3
08002230 <fiprintf>:
8002230: b40e push {r1, r2, r3}
8002232: b503 push {r0, r1, lr}
8002234: 0001 movs r1, r0
8002236: ab03 add r3, sp, #12
8002238: 4804 ldr r0, [pc, #16] ; (800224c <fiprintf+0x1c>)
800223a: cb04 ldmia r3!, {r2}
800223c: 6800 ldr r0, [r0, #0]
800223e: 9301 str r3, [sp, #4]
8002240: f000 f8e0 bl 8002404 <_vfiprintf_r>
8002244: b002 add sp, #8
8002246: bc08 pop {r3}
8002248: b003 add sp, #12
800224a: 4718 bx r3
800224c: 2000000c .word 0x2000000c
08002250 <malloc>:
8002250: b510 push {r4, lr}
8002252: 4b03 ldr r3, [pc, #12] ; (8002260 <malloc+0x10>)
8002254: 0001 movs r1, r0
8002256: 6818 ldr r0, [r3, #0]
8002258: f000 f84e bl 80022f8 <_malloc_r>
800225c: bd10 pop {r4, pc}
800225e: 46c0 nop ; (mov r8, r8)
8002260: 2000000c .word 0x2000000c
08002264 <_free_r>:
8002264: b570 push {r4, r5, r6, lr}
8002266: 0005 movs r5, r0
8002268: 2900 cmp r1, #0
800226a: d010 beq.n 800228e <_free_r+0x2a>
800226c: 1f0c subs r4, r1, #4
800226e: 6823 ldr r3, [r4, #0]
8002270: 2b00 cmp r3, #0
8002272: da00 bge.n 8002276 <_free_r+0x12>
8002274: 18e4 adds r4, r4, r3
8002276: 0028 movs r0, r5
8002278: f000 feb2 bl 8002fe0 <__malloc_lock>
800227c: 4a1d ldr r2, [pc, #116] ; (80022f4 <_free_r+0x90>)
800227e: 6813 ldr r3, [r2, #0]
8002280: 2b00 cmp r3, #0
8002282: d105 bne.n 8002290 <_free_r+0x2c>
8002284: 6063 str r3, [r4, #4]
8002286: 6014 str r4, [r2, #0]
8002288: 0028 movs r0, r5
800228a: f000 feb1 bl 8002ff0 <__malloc_unlock>
800228e: bd70 pop {r4, r5, r6, pc}
8002290: 42a3 cmp r3, r4
8002292: d908 bls.n 80022a6 <_free_r+0x42>
8002294: 6821 ldr r1, [r4, #0]
8002296: 1860 adds r0, r4, r1
8002298: 4283 cmp r3, r0
800229a: d1f3 bne.n 8002284 <_free_r+0x20>
800229c: 6818 ldr r0, [r3, #0]
800229e: 685b ldr r3, [r3, #4]
80022a0: 1841 adds r1, r0, r1
80022a2: 6021 str r1, [r4, #0]
80022a4: e7ee b.n 8002284 <_free_r+0x20>
80022a6: 001a movs r2, r3
80022a8: 685b ldr r3, [r3, #4]
80022aa: 2b00 cmp r3, #0
80022ac: d001 beq.n 80022b2 <_free_r+0x4e>
80022ae: 42a3 cmp r3, r4
80022b0: d9f9 bls.n 80022a6 <_free_r+0x42>
80022b2: 6811 ldr r1, [r2, #0]
80022b4: 1850 adds r0, r2, r1
80022b6: 42a0 cmp r0, r4
80022b8: d10b bne.n 80022d2 <_free_r+0x6e>
80022ba: 6820 ldr r0, [r4, #0]
80022bc: 1809 adds r1, r1, r0
80022be: 1850 adds r0, r2, r1
80022c0: 6011 str r1, [r2, #0]
80022c2: 4283 cmp r3, r0
80022c4: d1e0 bne.n 8002288 <_free_r+0x24>
80022c6: 6818 ldr r0, [r3, #0]
80022c8: 685b ldr r3, [r3, #4]
80022ca: 1841 adds r1, r0, r1
80022cc: 6011 str r1, [r2, #0]
80022ce: 6053 str r3, [r2, #4]
80022d0: e7da b.n 8002288 <_free_r+0x24>
80022d2: 42a0 cmp r0, r4
80022d4: d902 bls.n 80022dc <_free_r+0x78>
80022d6: 230c movs r3, #12
80022d8: 602b str r3, [r5, #0]
80022da: e7d5 b.n 8002288 <_free_r+0x24>
80022dc: 6821 ldr r1, [r4, #0]
80022de: 1860 adds r0, r4, r1
80022e0: 4283 cmp r3, r0
80022e2: d103 bne.n 80022ec <_free_r+0x88>
80022e4: 6818 ldr r0, [r3, #0]
80022e6: 685b ldr r3, [r3, #4]
80022e8: 1841 adds r1, r0, r1
80022ea: 6021 str r1, [r4, #0]
80022ec: 6063 str r3, [r4, #4]
80022ee: 6054 str r4, [r2, #4]
80022f0: e7ca b.n 8002288 <_free_r+0x24>
80022f2: 46c0 nop ; (mov r8, r8)
80022f4: 20000090 .word 0x20000090
080022f8 <_malloc_r>:
80022f8: b5f8 push {r3, r4, r5, r6, r7, lr}
80022fa: 2303 movs r3, #3
80022fc: 1ccd adds r5, r1, #3
80022fe: 439d bics r5, r3
8002300: 3508 adds r5, #8
8002302: 0006 movs r6, r0
8002304: 2d0c cmp r5, #12
8002306: d21f bcs.n 8002348 <_malloc_r+0x50>
8002308: 250c movs r5, #12
800230a: 42a9 cmp r1, r5
800230c: d81e bhi.n 800234c <_malloc_r+0x54>
800230e: 0030 movs r0, r6
8002310: f000 fe66 bl 8002fe0 <__malloc_lock>
8002314: 4925 ldr r1, [pc, #148] ; (80023ac <_malloc_r+0xb4>)
8002316: 680a ldr r2, [r1, #0]
8002318: 0014 movs r4, r2
800231a: 2c00 cmp r4, #0
800231c: d11a bne.n 8002354 <_malloc_r+0x5c>
800231e: 4f24 ldr r7, [pc, #144] ; (80023b0 <_malloc_r+0xb8>)
8002320: 683b ldr r3, [r7, #0]
8002322: 2b00 cmp r3, #0
8002324: d104 bne.n 8002330 <_malloc_r+0x38>
8002326: 0021 movs r1, r4
8002328: 0030 movs r0, r6
800232a: f000 fb27 bl 800297c <_sbrk_r>
800232e: 6038 str r0, [r7, #0]
8002330: 0029 movs r1, r5
8002332: 0030 movs r0, r6
8002334: f000 fb22 bl 800297c <_sbrk_r>
8002338: 1c43 adds r3, r0, #1
800233a: d12b bne.n 8002394 <_malloc_r+0x9c>
800233c: 230c movs r3, #12
800233e: 0030 movs r0, r6
8002340: 6033 str r3, [r6, #0]
8002342: f000 fe55 bl 8002ff0 <__malloc_unlock>
8002346: e003 b.n 8002350 <_malloc_r+0x58>
8002348: 2d00 cmp r5, #0
800234a: dade bge.n 800230a <_malloc_r+0x12>
800234c: 230c movs r3, #12
800234e: 6033 str r3, [r6, #0]
8002350: 2000 movs r0, #0
8002352: bdf8 pop {r3, r4, r5, r6, r7, pc}
8002354: 6823 ldr r3, [r4, #0]
8002356: 1b5b subs r3, r3, r5
8002358: d419 bmi.n 800238e <_malloc_r+0x96>
800235a: 2b0b cmp r3, #11
800235c: d903 bls.n 8002366 <_malloc_r+0x6e>
800235e: 6023 str r3, [r4, #0]
8002360: 18e4 adds r4, r4, r3
8002362: 6025 str r5, [r4, #0]
8002364: e003 b.n 800236e <_malloc_r+0x76>
8002366: 6863 ldr r3, [r4, #4]
8002368: 42a2 cmp r2, r4
800236a: d10e bne.n 800238a <_malloc_r+0x92>
800236c: 600b str r3, [r1, #0]
800236e: 0030 movs r0, r6
8002370: f000 fe3e bl 8002ff0 <__malloc_unlock>
8002374: 0020 movs r0, r4
8002376: 2207 movs r2, #7
8002378: 300b adds r0, #11
800237a: 1d23 adds r3, r4, #4
800237c: 4390 bics r0, r2
800237e: 1ac2 subs r2, r0, r3
8002380: 4298 cmp r0, r3
8002382: d0e6 beq.n 8002352 <_malloc_r+0x5a>
8002384: 1a1b subs r3, r3, r0
8002386: 50a3 str r3, [r4, r2]
8002388: e7e3 b.n 8002352 <_malloc_r+0x5a>
800238a: 6053 str r3, [r2, #4]
800238c: e7ef b.n 800236e <_malloc_r+0x76>
800238e: 0022 movs r2, r4
8002390: 6864 ldr r4, [r4, #4]
8002392: e7c2 b.n 800231a <_malloc_r+0x22>
8002394: 2303 movs r3, #3
8002396: 1cc4 adds r4, r0, #3
8002398: 439c bics r4, r3
800239a: 42a0 cmp r0, r4
800239c: d0e1 beq.n 8002362 <_malloc_r+0x6a>
800239e: 1a21 subs r1, r4, r0
80023a0: 0030 movs r0, r6
80023a2: f000 faeb bl 800297c <_sbrk_r>
80023a6: 1c43 adds r3, r0, #1
80023a8: d1db bne.n 8002362 <_malloc_r+0x6a>
80023aa: e7c7 b.n 800233c <_malloc_r+0x44>
80023ac: 20000090 .word 0x20000090
80023b0: 20000094 .word 0x20000094
080023b4 <__sfputc_r>:
80023b4: 6893 ldr r3, [r2, #8]
80023b6: b510 push {r4, lr}
80023b8: 3b01 subs r3, #1
80023ba: 6093 str r3, [r2, #8]
80023bc: 2b00 cmp r3, #0
80023be: da04 bge.n 80023ca <__sfputc_r+0x16>
80023c0: 6994 ldr r4, [r2, #24]
80023c2: 42a3 cmp r3, r4
80023c4: db07 blt.n 80023d6 <__sfputc_r+0x22>
80023c6: 290a cmp r1, #10
80023c8: d005 beq.n 80023d6 <__sfputc_r+0x22>
80023ca: 6813 ldr r3, [r2, #0]
80023cc: 1c58 adds r0, r3, #1
80023ce: 6010 str r0, [r2, #0]
80023d0: 7019 strb r1, [r3, #0]
80023d2: 0008 movs r0, r1
80023d4: bd10 pop {r4, pc}
80023d6: f000 fae3 bl 80029a0 <__swbuf_r>
80023da: 0001 movs r1, r0
80023dc: e7f9 b.n 80023d2 <__sfputc_r+0x1e>
080023de <__sfputs_r>:
80023de: b5f8 push {r3, r4, r5, r6, r7, lr}
80023e0: 0006 movs r6, r0
80023e2: 000f movs r7, r1
80023e4: 0014 movs r4, r2
80023e6: 18d5 adds r5, r2, r3
80023e8: 42ac cmp r4, r5
80023ea: d101 bne.n 80023f0 <__sfputs_r+0x12>
80023ec: 2000 movs r0, #0
80023ee: e007 b.n 8002400 <__sfputs_r+0x22>
80023f0: 7821 ldrb r1, [r4, #0]
80023f2: 003a movs r2, r7
80023f4: 0030 movs r0, r6
80023f6: f7ff ffdd bl 80023b4 <__sfputc_r>
80023fa: 3401 adds r4, #1
80023fc: 1c43 adds r3, r0, #1
80023fe: d1f3 bne.n 80023e8 <__sfputs_r+0xa>
8002400: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
08002404 <_vfiprintf_r>:
8002404: b5f0 push {r4, r5, r6, r7, lr}
8002406: b0a1 sub sp, #132 ; 0x84
8002408: 0006 movs r6, r0
800240a: 000c movs r4, r1
800240c: 001f movs r7, r3
800240e: 9203 str r2, [sp, #12]
8002410: 2800 cmp r0, #0
8002412: d004 beq.n 800241e <_vfiprintf_r+0x1a>
8002414: 6983 ldr r3, [r0, #24]
8002416: 2b00 cmp r3, #0
8002418: d101 bne.n 800241e <_vfiprintf_r+0x1a>
800241a: f000 fcc5 bl 8002da8 <__sinit>
800241e: 4b8e ldr r3, [pc, #568] ; (8002658 <_vfiprintf_r+0x254>)
8002420: 429c cmp r4, r3
8002422: d11c bne.n 800245e <_vfiprintf_r+0x5a>
8002424: 6874 ldr r4, [r6, #4]
8002426: 6e63 ldr r3, [r4, #100] ; 0x64
8002428: 07db lsls r3, r3, #31
800242a: d405 bmi.n 8002438 <_vfiprintf_r+0x34>
800242c: 89a3 ldrh r3, [r4, #12]
800242e: 059b lsls r3, r3, #22
8002430: d402 bmi.n 8002438 <_vfiprintf_r+0x34>
8002432: 6da0 ldr r0, [r4, #88] ; 0x58
8002434: f000 fd59 bl 8002eea <__retarget_lock_acquire_recursive>
8002438: 89a3 ldrh r3, [r4, #12]
800243a: 071b lsls r3, r3, #28
800243c: d502 bpl.n 8002444 <_vfiprintf_r+0x40>
800243e: 6923 ldr r3, [r4, #16]
8002440: 2b00 cmp r3, #0
8002442: d11d bne.n 8002480 <_vfiprintf_r+0x7c>
8002444: 0021 movs r1, r4
8002446: 0030 movs r0, r6
8002448: f000 fb00 bl 8002a4c <__swsetup_r>
800244c: 2800 cmp r0, #0
800244e: d017 beq.n 8002480 <_vfiprintf_r+0x7c>
8002450: 6e63 ldr r3, [r4, #100] ; 0x64
8002452: 07db lsls r3, r3, #31
8002454: d50d bpl.n 8002472 <_vfiprintf_r+0x6e>
8002456: 2001 movs r0, #1
8002458: 4240 negs r0, r0
800245a: b021 add sp, #132 ; 0x84
800245c: bdf0 pop {r4, r5, r6, r7, pc}
800245e: 4b7f ldr r3, [pc, #508] ; (800265c <_vfiprintf_r+0x258>)
8002460: 429c cmp r4, r3
8002462: d101 bne.n 8002468 <_vfiprintf_r+0x64>
8002464: 68b4 ldr r4, [r6, #8]
8002466: e7de b.n 8002426 <_vfiprintf_r+0x22>
8002468: 4b7d ldr r3, [pc, #500] ; (8002660 <_vfiprintf_r+0x25c>)
800246a: 429c cmp r4, r3
800246c: d1db bne.n 8002426 <_vfiprintf_r+0x22>
800246e: 68f4 ldr r4, [r6, #12]
8002470: e7d9 b.n 8002426 <_vfiprintf_r+0x22>
8002472: 89a3 ldrh r3, [r4, #12]
8002474: 059b lsls r3, r3, #22
8002476: d4ee bmi.n 8002456 <_vfiprintf_r+0x52>
8002478: 6da0 ldr r0, [r4, #88] ; 0x58
800247a: f000 fd37 bl 8002eec <__retarget_lock_release_recursive>
800247e: e7ea b.n 8002456 <_vfiprintf_r+0x52>
8002480: 2300 movs r3, #0
8002482: ad08 add r5, sp, #32
8002484: 616b str r3, [r5, #20]
8002486: 3320 adds r3, #32
8002488: 766b strb r3, [r5, #25]
800248a: 3310 adds r3, #16
800248c: 76ab strb r3, [r5, #26]
800248e: 9707 str r7, [sp, #28]
8002490: 9f03 ldr r7, [sp, #12]
8002492: 783b ldrb r3, [r7, #0]
8002494: 2b00 cmp r3, #0
8002496: d001 beq.n 800249c <_vfiprintf_r+0x98>
8002498: 2b25 cmp r3, #37 ; 0x25
800249a: d14e bne.n 800253a <_vfiprintf_r+0x136>
800249c: 9b03 ldr r3, [sp, #12]
800249e: 1afb subs r3, r7, r3
80024a0: 9305 str r3, [sp, #20]
80024a2: 9b03 ldr r3, [sp, #12]
80024a4: 429f cmp r7, r3
80024a6: d00d beq.n 80024c4 <_vfiprintf_r+0xc0>
80024a8: 9b05 ldr r3, [sp, #20]
80024aa: 0021 movs r1, r4
80024ac: 0030 movs r0, r6
80024ae: 9a03 ldr r2, [sp, #12]
80024b0: f7ff ff95 bl 80023de <__sfputs_r>
80024b4: 1c43 adds r3, r0, #1
80024b6: d100 bne.n 80024ba <_vfiprintf_r+0xb6>
80024b8: e0b5 b.n 8002626 <_vfiprintf_r+0x222>
80024ba: 696a ldr r2, [r5, #20]
80024bc: 9b05 ldr r3, [sp, #20]
80024be: 4694 mov ip, r2
80024c0: 4463 add r3, ip
80024c2: 616b str r3, [r5, #20]
80024c4: 783b ldrb r3, [r7, #0]
80024c6: 2b00 cmp r3, #0
80024c8: d100 bne.n 80024cc <_vfiprintf_r+0xc8>
80024ca: e0ac b.n 8002626 <_vfiprintf_r+0x222>
80024cc: 2201 movs r2, #1
80024ce: 1c7b adds r3, r7, #1
80024d0: 9303 str r3, [sp, #12]
80024d2: 2300 movs r3, #0
80024d4: 4252 negs r2, r2
80024d6: 606a str r2, [r5, #4]
80024d8: a904 add r1, sp, #16
80024da: 3254 adds r2, #84 ; 0x54
80024dc: 1852 adds r2, r2, r1
80024de: 602b str r3, [r5, #0]
80024e0: 60eb str r3, [r5, #12]
80024e2: 60ab str r3, [r5, #8]
80024e4: 7013 strb r3, [r2, #0]
80024e6: 65ab str r3, [r5, #88] ; 0x58
80024e8: 9b03 ldr r3, [sp, #12]
80024ea: 2205 movs r2, #5
80024ec: 7819 ldrb r1, [r3, #0]
80024ee: 485d ldr r0, [pc, #372] ; (8002664 <_vfiprintf_r+0x260>)
80024f0: f000 fd6a bl 8002fc8 <memchr>
80024f4: 9b03 ldr r3, [sp, #12]
80024f6: 1c5f adds r7, r3, #1
80024f8: 2800 cmp r0, #0
80024fa: d120 bne.n 800253e <_vfiprintf_r+0x13a>
80024fc: 682a ldr r2, [r5, #0]
80024fe: 06d3 lsls r3, r2, #27
8002500: d504 bpl.n 800250c <_vfiprintf_r+0x108>
8002502: 2353 movs r3, #83 ; 0x53
8002504: a904 add r1, sp, #16
8002506: 185b adds r3, r3, r1
8002508: 2120 movs r1, #32
800250a: 7019 strb r1, [r3, #0]
800250c: 0713 lsls r3, r2, #28
800250e: d504 bpl.n 800251a <_vfiprintf_r+0x116>
8002510: 2353 movs r3, #83 ; 0x53
8002512: a904 add r1, sp, #16
8002514: 185b adds r3, r3, r1
8002516: 212b movs r1, #43 ; 0x2b
8002518: 7019 strb r1, [r3, #0]
800251a: 9b03 ldr r3, [sp, #12]
800251c: 781b ldrb r3, [r3, #0]
800251e: 2b2a cmp r3, #42 ; 0x2a
8002520: d016 beq.n 8002550 <_vfiprintf_r+0x14c>
8002522: 2100 movs r1, #0
8002524: 68eb ldr r3, [r5, #12]
8002526: 9f03 ldr r7, [sp, #12]
8002528: 783a ldrb r2, [r7, #0]
800252a: 1c78 adds r0, r7, #1
800252c: 3a30 subs r2, #48 ; 0x30
800252e: 4684 mov ip, r0
8002530: 2a09 cmp r2, #9
8002532: d94f bls.n 80025d4 <_vfiprintf_r+0x1d0>
8002534: 2900 cmp r1, #0
8002536: d111 bne.n 800255c <_vfiprintf_r+0x158>
8002538: e017 b.n 800256a <_vfiprintf_r+0x166>
800253a: 3701 adds r7, #1
800253c: e7a9 b.n 8002492 <_vfiprintf_r+0x8e>
800253e: 4b49 ldr r3, [pc, #292] ; (8002664 <_vfiprintf_r+0x260>)
8002540: 682a ldr r2, [r5, #0]
8002542: 1ac0 subs r0, r0, r3
8002544: 2301 movs r3, #1
8002546: 4083 lsls r3, r0
8002548: 4313 orrs r3, r2
800254a: 602b str r3, [r5, #0]
800254c: 9703 str r7, [sp, #12]
800254e: e7cb b.n 80024e8 <_vfiprintf_r+0xe4>
8002550: 9b07 ldr r3, [sp, #28]
8002552: 1d19 adds r1, r3, #4
8002554: 681b ldr r3, [r3, #0]
8002556: 9107 str r1, [sp, #28]
8002558: 2b00 cmp r3, #0
800255a: db01 blt.n 8002560 <_vfiprintf_r+0x15c>
800255c: 930b str r3, [sp, #44] ; 0x2c
800255e: e004 b.n 800256a <_vfiprintf_r+0x166>
8002560: 425b negs r3, r3
8002562: 60eb str r3, [r5, #12]
8002564: 2302 movs r3, #2
8002566: 4313 orrs r3, r2
8002568: 602b str r3, [r5, #0]
800256a: 783b ldrb r3, [r7, #0]
800256c: 2b2e cmp r3, #46 ; 0x2e
800256e: d10a bne.n 8002586 <_vfiprintf_r+0x182>
8002570: 787b ldrb r3, [r7, #1]
8002572: 2b2a cmp r3, #42 ; 0x2a
8002574: d137 bne.n 80025e6 <_vfiprintf_r+0x1e2>
8002576: 9b07 ldr r3, [sp, #28]
8002578: 3702 adds r7, #2
800257a: 1d1a adds r2, r3, #4
800257c: 681b ldr r3, [r3, #0]
800257e: 9207 str r2, [sp, #28]
8002580: 2b00 cmp r3, #0
8002582: db2d blt.n 80025e0 <_vfiprintf_r+0x1dc>
8002584: 9309 str r3, [sp, #36] ; 0x24
8002586: 2203 movs r2, #3
8002588: 7839 ldrb r1, [r7, #0]
800258a: 4837 ldr r0, [pc, #220] ; (8002668 <_vfiprintf_r+0x264>)
800258c: f000 fd1c bl 8002fc8 <memchr>
8002590: 2800 cmp r0, #0
8002592: d007 beq.n 80025a4 <_vfiprintf_r+0x1a0>
8002594: 4b34 ldr r3, [pc, #208] ; (8002668 <_vfiprintf_r+0x264>)
8002596: 682a ldr r2, [r5, #0]
8002598: 1ac0 subs r0, r0, r3
800259a: 2340 movs r3, #64 ; 0x40
800259c: 4083 lsls r3, r0
800259e: 4313 orrs r3, r2
80025a0: 3701 adds r7, #1
80025a2: 602b str r3, [r5, #0]
80025a4: 7839 ldrb r1, [r7, #0]
80025a6: 1c7b adds r3, r7, #1
80025a8: 2206 movs r2, #6
80025aa: 4830 ldr r0, [pc, #192] ; (800266c <_vfiprintf_r+0x268>)
80025ac: 9303 str r3, [sp, #12]
80025ae: 7629 strb r1, [r5, #24]
80025b0: f000 fd0a bl 8002fc8 <memchr>
80025b4: 2800 cmp r0, #0
80025b6: d045 beq.n 8002644 <_vfiprintf_r+0x240>
80025b8: 4b2d ldr r3, [pc, #180] ; (8002670 <_vfiprintf_r+0x26c>)
80025ba: 2b00 cmp r3, #0
80025bc: d127 bne.n 800260e <_vfiprintf_r+0x20a>
80025be: 2207 movs r2, #7
80025c0: 9b07 ldr r3, [sp, #28]
80025c2: 3307 adds r3, #7
80025c4: 4393 bics r3, r2
80025c6: 3308 adds r3, #8
80025c8: 9307 str r3, [sp, #28]
80025ca: 696b ldr r3, [r5, #20]
80025cc: 9a04 ldr r2, [sp, #16]
80025ce: 189b adds r3, r3, r2
80025d0: 616b str r3, [r5, #20]
80025d2: e75d b.n 8002490 <_vfiprintf_r+0x8c>
80025d4: 210a movs r1, #10
80025d6: 434b muls r3, r1
80025d8: 4667 mov r7, ip
80025da: 189b adds r3, r3, r2
80025dc: 3909 subs r1, #9
80025de: e7a3 b.n 8002528 <_vfiprintf_r+0x124>
80025e0: 2301 movs r3, #1
80025e2: 425b negs r3, r3
80025e4: e7ce b.n 8002584 <_vfiprintf_r+0x180>
80025e6: 2300 movs r3, #0
80025e8: 001a movs r2, r3
80025ea: 3701 adds r7, #1
80025ec: 606b str r3, [r5, #4]
80025ee: 7839 ldrb r1, [r7, #0]
80025f0: 1c78 adds r0, r7, #1
80025f2: 3930 subs r1, #48 ; 0x30
80025f4: 4684 mov ip, r0
80025f6: 2909 cmp r1, #9
80025f8: d903 bls.n 8002602 <_vfiprintf_r+0x1fe>
80025fa: 2b00 cmp r3, #0
80025fc: d0c3 beq.n 8002586 <_vfiprintf_r+0x182>
80025fe: 9209 str r2, [sp, #36] ; 0x24
8002600: e7c1 b.n 8002586 <_vfiprintf_r+0x182>
8002602: 230a movs r3, #10
8002604: 435a muls r2, r3
8002606: 4667 mov r7, ip
8002608: 1852 adds r2, r2, r1
800260a: 3b09 subs r3, #9
800260c: e7ef b.n 80025ee <_vfiprintf_r+0x1ea>
800260e: ab07 add r3, sp, #28
8002610: 9300 str r3, [sp, #0]
8002612: 0022 movs r2, r4
8002614: 0029 movs r1, r5
8002616: 0030 movs r0, r6
8002618: 4b16 ldr r3, [pc, #88] ; (8002674 <_vfiprintf_r+0x270>)
800261a: e000 b.n 800261e <_vfiprintf_r+0x21a>
800261c: bf00 nop
800261e: 9004 str r0, [sp, #16]
8002620: 9b04 ldr r3, [sp, #16]
8002622: 3301 adds r3, #1
8002624: d1d1 bne.n 80025ca <_vfiprintf_r+0x1c6>
8002626: 6e63 ldr r3, [r4, #100] ; 0x64
8002628: 07db lsls r3, r3, #31
800262a: d405 bmi.n 8002638 <_vfiprintf_r+0x234>
800262c: 89a3 ldrh r3, [r4, #12]
800262e: 059b lsls r3, r3, #22
8002630: d402 bmi.n 8002638 <_vfiprintf_r+0x234>
8002632: 6da0 ldr r0, [r4, #88] ; 0x58
8002634: f000 fc5a bl 8002eec <__retarget_lock_release_recursive>
8002638: 89a3 ldrh r3, [r4, #12]
800263a: 065b lsls r3, r3, #25
800263c: d500 bpl.n 8002640 <_vfiprintf_r+0x23c>
800263e: e70a b.n 8002456 <_vfiprintf_r+0x52>
8002640: 980d ldr r0, [sp, #52] ; 0x34
8002642: e70a b.n 800245a <_vfiprintf_r+0x56>
8002644: ab07 add r3, sp, #28
8002646: 9300 str r3, [sp, #0]
8002648: 0022 movs r2, r4
800264a: 0029 movs r1, r5
800264c: 0030 movs r0, r6
800264e: 4b09 ldr r3, [pc, #36] ; (8002674 <_vfiprintf_r+0x270>)
8002650: f000 f882 bl 8002758 <_printf_i>
8002654: e7e3 b.n 800261e <_vfiprintf_r+0x21a>
8002656: 46c0 nop ; (mov r8, r8)
8002658: 08003378 .word 0x08003378
800265c: 08003398 .word 0x08003398
8002660: 08003358 .word 0x08003358
8002664: 08003322 .word 0x08003322
8002668: 08003328 .word 0x08003328
800266c: 0800332c .word 0x0800332c
8002670: 00000000 .word 0x00000000
8002674: 080023df .word 0x080023df
08002678 <_printf_common>:
8002678: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
800267a: 0015 movs r5, r2
800267c: 9301 str r3, [sp, #4]
800267e: 688a ldr r2, [r1, #8]
8002680: 690b ldr r3, [r1, #16]
8002682: 000c movs r4, r1
8002684: 9000 str r0, [sp, #0]
8002686: 4293 cmp r3, r2
8002688: da00 bge.n 800268c <_printf_common+0x14>
800268a: 0013 movs r3, r2
800268c: 0022 movs r2, r4
800268e: 602b str r3, [r5, #0]
8002690: 3243 adds r2, #67 ; 0x43
8002692: 7812 ldrb r2, [r2, #0]
8002694: 2a00 cmp r2, #0
8002696: d001 beq.n 800269c <_printf_common+0x24>
8002698: 3301 adds r3, #1
800269a: 602b str r3, [r5, #0]
800269c: 6823 ldr r3, [r4, #0]
800269e: 069b lsls r3, r3, #26
80026a0: d502 bpl.n 80026a8 <_printf_common+0x30>
80026a2: 682b ldr r3, [r5, #0]
80026a4: 3302 adds r3, #2
80026a6: 602b str r3, [r5, #0]
80026a8: 6822 ldr r2, [r4, #0]
80026aa: 2306 movs r3, #6
80026ac: 0017 movs r7, r2
80026ae: 401f ands r7, r3
80026b0: 421a tst r2, r3
80026b2: d027 beq.n 8002704 <_printf_common+0x8c>
80026b4: 0023 movs r3, r4
80026b6: 3343 adds r3, #67 ; 0x43
80026b8: 781b ldrb r3, [r3, #0]
80026ba: 1e5a subs r2, r3, #1
80026bc: 4193 sbcs r3, r2
80026be: 6822 ldr r2, [r4, #0]
80026c0: 0692 lsls r2, r2, #26
80026c2: d430 bmi.n 8002726 <_printf_common+0xae>
80026c4: 0022 movs r2, r4
80026c6: 9901 ldr r1, [sp, #4]
80026c8: 9800 ldr r0, [sp, #0]
80026ca: 9e08 ldr r6, [sp, #32]
80026cc: 3243 adds r2, #67 ; 0x43
80026ce: 47b0 blx r6
80026d0: 1c43 adds r3, r0, #1
80026d2: d025 beq.n 8002720 <_printf_common+0xa8>
80026d4: 2306 movs r3, #6
80026d6: 6820 ldr r0, [r4, #0]
80026d8: 682a ldr r2, [r5, #0]
80026da: 68e1 ldr r1, [r4, #12]
80026dc: 2500 movs r5, #0
80026de: 4003 ands r3, r0
80026e0: 2b04 cmp r3, #4
80026e2: d103 bne.n 80026ec <_printf_common+0x74>
80026e4: 1a8d subs r5, r1, r2
80026e6: 43eb mvns r3, r5
80026e8: 17db asrs r3, r3, #31
80026ea: 401d ands r5, r3
80026ec: 68a3 ldr r3, [r4, #8]
80026ee: 6922 ldr r2, [r4, #16]
80026f0: 4293 cmp r3, r2
80026f2: dd01 ble.n 80026f8 <_printf_common+0x80>
80026f4: 1a9b subs r3, r3, r2
80026f6: 18ed adds r5, r5, r3
80026f8: 2700 movs r7, #0
80026fa: 42bd cmp r5, r7
80026fc: d120 bne.n 8002740 <_printf_common+0xc8>
80026fe: 2000 movs r0, #0
8002700: e010 b.n 8002724 <_printf_common+0xac>
8002702: 3701 adds r7, #1
8002704: 68e3 ldr r3, [r4, #12]
8002706: 682a ldr r2, [r5, #0]
8002708: 1a9b subs r3, r3, r2
800270a: 42bb cmp r3, r7
800270c: ddd2 ble.n 80026b4 <_printf_common+0x3c>
800270e: 0022 movs r2, r4
8002710: 2301 movs r3, #1
8002712: 9901 ldr r1, [sp, #4]
8002714: 9800 ldr r0, [sp, #0]
8002716: 9e08 ldr r6, [sp, #32]
8002718: 3219 adds r2, #25
800271a: 47b0 blx r6
800271c: 1c43 adds r3, r0, #1
800271e: d1f0 bne.n 8002702 <_printf_common+0x8a>
8002720: 2001 movs r0, #1
8002722: 4240 negs r0, r0
8002724: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
8002726: 2030 movs r0, #48 ; 0x30
8002728: 18e1 adds r1, r4, r3
800272a: 3143 adds r1, #67 ; 0x43
800272c: 7008 strb r0, [r1, #0]
800272e: 0021 movs r1, r4
8002730: 1c5a adds r2, r3, #1
8002732: 3145 adds r1, #69 ; 0x45
8002734: 7809 ldrb r1, [r1, #0]
8002736: 18a2 adds r2, r4, r2
8002738: 3243 adds r2, #67 ; 0x43
800273a: 3302 adds r3, #2
800273c: 7011 strb r1, [r2, #0]
800273e: e7c1 b.n 80026c4 <_printf_common+0x4c>
8002740: 0022 movs r2, r4
8002742: 2301 movs r3, #1
8002744: 9901 ldr r1, [sp, #4]
8002746: 9800 ldr r0, [sp, #0]
8002748: 9e08 ldr r6, [sp, #32]
800274a: 321a adds r2, #26
800274c: 47b0 blx r6
800274e: 1c43 adds r3, r0, #1
8002750: d0e6 beq.n 8002720 <_printf_common+0xa8>
8002752: 3701 adds r7, #1
8002754: e7d1 b.n 80026fa <_printf_common+0x82>
...
08002758 <_printf_i>:
8002758: b5f0 push {r4, r5, r6, r7, lr}
800275a: b08b sub sp, #44 ; 0x2c
800275c: 9206 str r2, [sp, #24]
800275e: 000a movs r2, r1
8002760: 3243 adds r2, #67 ; 0x43
8002762: 9307 str r3, [sp, #28]
8002764: 9005 str r0, [sp, #20]
8002766: 9204 str r2, [sp, #16]
8002768: 7e0a ldrb r2, [r1, #24]
800276a: 000c movs r4, r1
800276c: 9b10 ldr r3, [sp, #64] ; 0x40
800276e: 2a78 cmp r2, #120 ; 0x78
8002770: d806 bhi.n 8002780 <_printf_i+0x28>
8002772: 2a62 cmp r2, #98 ; 0x62
8002774: d808 bhi.n 8002788 <_printf_i+0x30>
8002776: 2a00 cmp r2, #0
8002778: d100 bne.n 800277c <_printf_i+0x24>
800277a: e0c0 b.n 80028fe <_printf_i+0x1a6>
800277c: 2a58 cmp r2, #88 ; 0x58
800277e: d052 beq.n 8002826 <_printf_i+0xce>
8002780: 0026 movs r6, r4
8002782: 3642 adds r6, #66 ; 0x42
8002784: 7032 strb r2, [r6, #0]
8002786: e022 b.n 80027ce <_printf_i+0x76>
8002788: 0010 movs r0, r2
800278a: 3863 subs r0, #99 ; 0x63
800278c: 2815 cmp r0, #21
800278e: d8f7 bhi.n 8002780 <_printf_i+0x28>
8002790: f7fd fcba bl 8000108 <__gnu_thumb1_case_shi>
8002794: 001f0016 .word 0x001f0016
8002798: fff6fff6 .word 0xfff6fff6
800279c: fff6fff6 .word 0xfff6fff6
80027a0: fff6001f .word 0xfff6001f
80027a4: fff6fff6 .word 0xfff6fff6
80027a8: 00a8fff6 .word 0x00a8fff6
80027ac: 009a0036 .word 0x009a0036
80027b0: fff6fff6 .word 0xfff6fff6
80027b4: fff600b9 .word 0xfff600b9
80027b8: fff60036 .word 0xfff60036
80027bc: 009efff6 .word 0x009efff6
80027c0: 0026 movs r6, r4
80027c2: 681a ldr r2, [r3, #0]
80027c4: 3642 adds r6, #66 ; 0x42
80027c6: 1d11 adds r1, r2, #4
80027c8: 6019 str r1, [r3, #0]
80027ca: 6813 ldr r3, [r2, #0]
80027cc: 7033 strb r3, [r6, #0]
80027ce: 2301 movs r3, #1
80027d0: e0a7 b.n 8002922 <_printf_i+0x1ca>
80027d2: 6808 ldr r0, [r1, #0]
80027d4: 6819 ldr r1, [r3, #0]
80027d6: 1d0a adds r2, r1, #4
80027d8: 0605 lsls r5, r0, #24
80027da: d50b bpl.n 80027f4 <_printf_i+0x9c>
80027dc: 680d ldr r5, [r1, #0]
80027de: 601a str r2, [r3, #0]
80027e0: 2d00 cmp r5, #0
80027e2: da03 bge.n 80027ec <_printf_i+0x94>
80027e4: 232d movs r3, #45 ; 0x2d
80027e6: 9a04 ldr r2, [sp, #16]
80027e8: 426d negs r5, r5
80027ea: 7013 strb r3, [r2, #0]
80027ec: 4b61 ldr r3, [pc, #388] ; (8002974 <_printf_i+0x21c>)
80027ee: 270a movs r7, #10
80027f0: 9303 str r3, [sp, #12]
80027f2: e032 b.n 800285a <_printf_i+0x102>
80027f4: 680d ldr r5, [r1, #0]
80027f6: 601a str r2, [r3, #0]
80027f8: 0641 lsls r1, r0, #25
80027fa: d5f1 bpl.n 80027e0 <_printf_i+0x88>
80027fc: b22d sxth r5, r5
80027fe: e7ef b.n 80027e0 <_printf_i+0x88>
8002800: 680d ldr r5, [r1, #0]
8002802: 6819 ldr r1, [r3, #0]
8002804: 1d08 adds r0, r1, #4
8002806: 6018 str r0, [r3, #0]
8002808: 062e lsls r6, r5, #24
800280a: d501 bpl.n 8002810 <_printf_i+0xb8>
800280c: 680d ldr r5, [r1, #0]
800280e: e003 b.n 8002818 <_printf_i+0xc0>
8002810: 066d lsls r5, r5, #25
8002812: d5fb bpl.n 800280c <_printf_i+0xb4>
8002814: 680d ldr r5, [r1, #0]
8002816: b2ad uxth r5, r5
8002818: 4b56 ldr r3, [pc, #344] ; (8002974 <_printf_i+0x21c>)
800281a: 270a movs r7, #10
800281c: 9303 str r3, [sp, #12]
800281e: 2a6f cmp r2, #111 ; 0x6f
8002820: d117 bne.n 8002852 <_printf_i+0xfa>
8002822: 2708 movs r7, #8
8002824: e015 b.n 8002852 <_printf_i+0xfa>
8002826: 3145 adds r1, #69 ; 0x45
8002828: 700a strb r2, [r1, #0]
800282a: 4a52 ldr r2, [pc, #328] ; (8002974 <_printf_i+0x21c>)
800282c: 9203 str r2, [sp, #12]
800282e: 681a ldr r2, [r3, #0]
8002830: 6821 ldr r1, [r4, #0]
8002832: ca20 ldmia r2!, {r5}
8002834: 601a str r2, [r3, #0]
8002836: 0608 lsls r0, r1, #24
8002838: d550 bpl.n 80028dc <_printf_i+0x184>
800283a: 07cb lsls r3, r1, #31
800283c: d502 bpl.n 8002844 <_printf_i+0xec>
800283e: 2320 movs r3, #32
8002840: 4319 orrs r1, r3
8002842: 6021 str r1, [r4, #0]
8002844: 2710 movs r7, #16
8002846: 2d00 cmp r5, #0
8002848: d103 bne.n 8002852 <_printf_i+0xfa>
800284a: 2320 movs r3, #32
800284c: 6822 ldr r2, [r4, #0]
800284e: 439a bics r2, r3
8002850: 6022 str r2, [r4, #0]
8002852: 0023 movs r3, r4
8002854: 2200 movs r2, #0
8002856: 3343 adds r3, #67 ; 0x43
8002858: 701a strb r2, [r3, #0]
800285a: 6863 ldr r3, [r4, #4]
800285c: 60a3 str r3, [r4, #8]
800285e: 2b00 cmp r3, #0
8002860: db03 blt.n 800286a <_printf_i+0x112>
8002862: 2204 movs r2, #4
8002864: 6821 ldr r1, [r4, #0]
8002866: 4391 bics r1, r2
8002868: 6021 str r1, [r4, #0]
800286a: 2d00 cmp r5, #0
800286c: d102 bne.n 8002874 <_printf_i+0x11c>
800286e: 9e04 ldr r6, [sp, #16]
8002870: 2b00 cmp r3, #0
8002872: d00c beq.n 800288e <_printf_i+0x136>
8002874: 9e04 ldr r6, [sp, #16]
8002876: 0028 movs r0, r5
8002878: 0039 movs r1, r7
800287a: f7fd fcd5 bl 8000228 <__aeabi_uidivmod>
800287e: 9b03 ldr r3, [sp, #12]
8002880: 3e01 subs r6, #1
8002882: 5c5b ldrb r3, [r3, r1]
8002884: 7033 strb r3, [r6, #0]
8002886: 002b movs r3, r5
8002888: 0005 movs r5, r0
800288a: 429f cmp r7, r3
800288c: d9f3 bls.n 8002876 <_printf_i+0x11e>
800288e: 2f08 cmp r7, #8
8002890: d109 bne.n 80028a6 <_printf_i+0x14e>
8002892: 6823 ldr r3, [r4, #0]
8002894: 07db lsls r3, r3, #31
8002896: d506 bpl.n 80028a6 <_printf_i+0x14e>
8002898: 6863 ldr r3, [r4, #4]
800289a: 6922 ldr r2, [r4, #16]
800289c: 4293 cmp r3, r2
800289e: dc02 bgt.n 80028a6 <_printf_i+0x14e>
80028a0: 2330 movs r3, #48 ; 0x30
80028a2: 3e01 subs r6, #1
80028a4: 7033 strb r3, [r6, #0]
80028a6: 9b04 ldr r3, [sp, #16]
80028a8: 1b9b subs r3, r3, r6
80028aa: 6123 str r3, [r4, #16]
80028ac: 9b07 ldr r3, [sp, #28]
80028ae: 0021 movs r1, r4
80028b0: 9300 str r3, [sp, #0]
80028b2: 9805 ldr r0, [sp, #20]
80028b4: 9b06 ldr r3, [sp, #24]
80028b6: aa09 add r2, sp, #36 ; 0x24
80028b8: f7ff fede bl 8002678 <_printf_common>
80028bc: 1c43 adds r3, r0, #1
80028be: d135 bne.n 800292c <_printf_i+0x1d4>
80028c0: 2001 movs r0, #1
80028c2: 4240 negs r0, r0
80028c4: b00b add sp, #44 ; 0x2c
80028c6: bdf0 pop {r4, r5, r6, r7, pc}
80028c8: 2220 movs r2, #32
80028ca: 6809 ldr r1, [r1, #0]
80028cc: 430a orrs r2, r1
80028ce: 6022 str r2, [r4, #0]
80028d0: 0022 movs r2, r4
80028d2: 2178 movs r1, #120 ; 0x78
80028d4: 3245 adds r2, #69 ; 0x45
80028d6: 7011 strb r1, [r2, #0]
80028d8: 4a27 ldr r2, [pc, #156] ; (8002978 <_printf_i+0x220>)
80028da: e7a7 b.n 800282c <_printf_i+0xd4>
80028dc: 0648 lsls r0, r1, #25
80028de: d5ac bpl.n 800283a <_printf_i+0xe2>
80028e0: b2ad uxth r5, r5
80028e2: e7aa b.n 800283a <_printf_i+0xe2>
80028e4: 681a ldr r2, [r3, #0]
80028e6: 680d ldr r5, [r1, #0]
80028e8: 1d10 adds r0, r2, #4
80028ea: 6949 ldr r1, [r1, #20]
80028ec: 6018 str r0, [r3, #0]
80028ee: 6813 ldr r3, [r2, #0]
80028f0: 062e lsls r6, r5, #24
80028f2: d501 bpl.n 80028f8 <_printf_i+0x1a0>
80028f4: 6019 str r1, [r3, #0]
80028f6: e002 b.n 80028fe <_printf_i+0x1a6>
80028f8: 066d lsls r5, r5, #25
80028fa: d5fb bpl.n 80028f4 <_printf_i+0x19c>
80028fc: 8019 strh r1, [r3, #0]
80028fe: 2300 movs r3, #0
8002900: 9e04 ldr r6, [sp, #16]
8002902: 6123 str r3, [r4, #16]
8002904: e7d2 b.n 80028ac <_printf_i+0x154>
8002906: 681a ldr r2, [r3, #0]
8002908: 1d11 adds r1, r2, #4
800290a: 6019 str r1, [r3, #0]
800290c: 6816 ldr r6, [r2, #0]
800290e: 2100 movs r1, #0
8002910: 0030 movs r0, r6
8002912: 6862 ldr r2, [r4, #4]
8002914: f000 fb58 bl 8002fc8 <memchr>
8002918: 2800 cmp r0, #0
800291a: d001 beq.n 8002920 <_printf_i+0x1c8>
800291c: 1b80 subs r0, r0, r6
800291e: 6060 str r0, [r4, #4]
8002920: 6863 ldr r3, [r4, #4]
8002922: 6123 str r3, [r4, #16]
8002924: 2300 movs r3, #0
8002926: 9a04 ldr r2, [sp, #16]
8002928: 7013 strb r3, [r2, #0]
800292a: e7bf b.n 80028ac <_printf_i+0x154>
800292c: 6923 ldr r3, [r4, #16]
800292e: 0032 movs r2, r6
8002930: 9906 ldr r1, [sp, #24]
8002932: 9805 ldr r0, [sp, #20]
8002934: 9d07 ldr r5, [sp, #28]
8002936: 47a8 blx r5
8002938: 1c43 adds r3, r0, #1
800293a: d0c1 beq.n 80028c0 <_printf_i+0x168>
800293c: 6823 ldr r3, [r4, #0]
800293e: 079b lsls r3, r3, #30
8002940: d415 bmi.n 800296e <_printf_i+0x216>
8002942: 9b09 ldr r3, [sp, #36] ; 0x24
8002944: 68e0 ldr r0, [r4, #12]
8002946: 4298 cmp r0, r3
8002948: dabc bge.n 80028c4 <_printf_i+0x16c>
800294a: 0018 movs r0, r3
800294c: e7ba b.n 80028c4 <_printf_i+0x16c>
800294e: 0022 movs r2, r4
8002950: 2301 movs r3, #1
8002952: 9906 ldr r1, [sp, #24]
8002954: 9805 ldr r0, [sp, #20]
8002956: 9e07 ldr r6, [sp, #28]
8002958: 3219 adds r2, #25
800295a: 47b0 blx r6
800295c: 1c43 adds r3, r0, #1
800295e: d0af beq.n 80028c0 <_printf_i+0x168>
8002960: 3501 adds r5, #1
8002962: 68e3 ldr r3, [r4, #12]
8002964: 9a09 ldr r2, [sp, #36] ; 0x24
8002966: 1a9b subs r3, r3, r2
8002968: 42ab cmp r3, r5
800296a: dcf0 bgt.n 800294e <_printf_i+0x1f6>
800296c: e7e9 b.n 8002942 <_printf_i+0x1ea>
800296e: 2500 movs r5, #0
8002970: e7f7 b.n 8002962 <_printf_i+0x20a>
8002972: 46c0 nop ; (mov r8, r8)
8002974: 08003333 .word 0x08003333
8002978: 08003344 .word 0x08003344
0800297c <_sbrk_r>:
800297c: 2300 movs r3, #0
800297e: b570 push {r4, r5, r6, lr}
8002980: 4d06 ldr r5, [pc, #24] ; (800299c <_sbrk_r+0x20>)
8002982: 0004 movs r4, r0
8002984: 0008 movs r0, r1
8002986: 602b str r3, [r5, #0]
8002988: f7fd ffa2 bl 80008d0 <_sbrk>
800298c: 1c43 adds r3, r0, #1
800298e: d103 bne.n 8002998 <_sbrk_r+0x1c>
8002990: 682b ldr r3, [r5, #0]
8002992: 2b00 cmp r3, #0
8002994: d000 beq.n 8002998 <_sbrk_r+0x1c>
8002996: 6023 str r3, [r4, #0]
8002998: bd70 pop {r4, r5, r6, pc}
800299a: 46c0 nop ; (mov r8, r8)
800299c: 200000ec .word 0x200000ec
080029a0 <__swbuf_r>:
80029a0: b5f8 push {r3, r4, r5, r6, r7, lr}
80029a2: 0005 movs r5, r0
80029a4: 000e movs r6, r1
80029a6: 0014 movs r4, r2
80029a8: 2800 cmp r0, #0
80029aa: d004 beq.n 80029b6 <__swbuf_r+0x16>
80029ac: 6983 ldr r3, [r0, #24]
80029ae: 2b00 cmp r3, #0
80029b0: d101 bne.n 80029b6 <__swbuf_r+0x16>
80029b2: f000 f9f9 bl 8002da8 <__sinit>
80029b6: 4b22 ldr r3, [pc, #136] ; (8002a40 <__swbuf_r+0xa0>)
80029b8: 429c cmp r4, r3
80029ba: d12e bne.n 8002a1a <__swbuf_r+0x7a>
80029bc: 686c ldr r4, [r5, #4]
80029be: 69a3 ldr r3, [r4, #24]
80029c0: 60a3 str r3, [r4, #8]
80029c2: 89a3 ldrh r3, [r4, #12]
80029c4: 071b lsls r3, r3, #28
80029c6: d532 bpl.n 8002a2e <__swbuf_r+0x8e>
80029c8: 6923 ldr r3, [r4, #16]
80029ca: 2b00 cmp r3, #0
80029cc: d02f beq.n 8002a2e <__swbuf_r+0x8e>
80029ce: 6823 ldr r3, [r4, #0]
80029d0: 6922 ldr r2, [r4, #16]
80029d2: b2f7 uxtb r7, r6
80029d4: 1a98 subs r0, r3, r2
80029d6: 6963 ldr r3, [r4, #20]
80029d8: b2f6 uxtb r6, r6
80029da: 4283 cmp r3, r0
80029dc: dc05 bgt.n 80029ea <__swbuf_r+0x4a>
80029de: 0021 movs r1, r4
80029e0: 0028 movs r0, r5
80029e2: f000 f93f bl 8002c64 <_fflush_r>
80029e6: 2800 cmp r0, #0
80029e8: d127 bne.n 8002a3a <__swbuf_r+0x9a>
80029ea: 68a3 ldr r3, [r4, #8]
80029ec: 3001 adds r0, #1
80029ee: 3b01 subs r3, #1
80029f0: 60a3 str r3, [r4, #8]
80029f2: 6823 ldr r3, [r4, #0]
80029f4: 1c5a adds r2, r3, #1
80029f6: 6022 str r2, [r4, #0]
80029f8: 701f strb r7, [r3, #0]
80029fa: 6963 ldr r3, [r4, #20]
80029fc: 4283 cmp r3, r0
80029fe: d004 beq.n 8002a0a <__swbuf_r+0x6a>
8002a00: 89a3 ldrh r3, [r4, #12]
8002a02: 07db lsls r3, r3, #31
8002a04: d507 bpl.n 8002a16 <__swbuf_r+0x76>
8002a06: 2e0a cmp r6, #10
8002a08: d105 bne.n 8002a16 <__swbuf_r+0x76>
8002a0a: 0021 movs r1, r4
8002a0c: 0028 movs r0, r5
8002a0e: f000 f929 bl 8002c64 <_fflush_r>
8002a12: 2800 cmp r0, #0
8002a14: d111 bne.n 8002a3a <__swbuf_r+0x9a>
8002a16: 0030 movs r0, r6
8002a18: bdf8 pop {r3, r4, r5, r6, r7, pc}
8002a1a: 4b0a ldr r3, [pc, #40] ; (8002a44 <__swbuf_r+0xa4>)
8002a1c: 429c cmp r4, r3
8002a1e: d101 bne.n 8002a24 <__swbuf_r+0x84>
8002a20: 68ac ldr r4, [r5, #8]
8002a22: e7cc b.n 80029be <__swbuf_r+0x1e>
8002a24: 4b08 ldr r3, [pc, #32] ; (8002a48 <__swbuf_r+0xa8>)
8002a26: 429c cmp r4, r3
8002a28: d1c9 bne.n 80029be <__swbuf_r+0x1e>
8002a2a: 68ec ldr r4, [r5, #12]
8002a2c: e7c7 b.n 80029be <__swbuf_r+0x1e>
8002a2e: 0021 movs r1, r4
8002a30: 0028 movs r0, r5
8002a32: f000 f80b bl 8002a4c <__swsetup_r>
8002a36: 2800 cmp r0, #0
8002a38: d0c9 beq.n 80029ce <__swbuf_r+0x2e>
8002a3a: 2601 movs r6, #1
8002a3c: 4276 negs r6, r6
8002a3e: e7ea b.n 8002a16 <__swbuf_r+0x76>
8002a40: 08003378 .word 0x08003378
8002a44: 08003398 .word 0x08003398
8002a48: 08003358 .word 0x08003358
08002a4c <__swsetup_r>:
8002a4c: 4b37 ldr r3, [pc, #220] ; (8002b2c <__swsetup_r+0xe0>)
8002a4e: b570 push {r4, r5, r6, lr}
8002a50: 681d ldr r5, [r3, #0]
8002a52: 0006 movs r6, r0
8002a54: 000c movs r4, r1
8002a56: 2d00 cmp r5, #0
8002a58: d005 beq.n 8002a66 <__swsetup_r+0x1a>
8002a5a: 69ab ldr r3, [r5, #24]
8002a5c: 2b00 cmp r3, #0
8002a5e: d102 bne.n 8002a66 <__swsetup_r+0x1a>
8002a60: 0028 movs r0, r5
8002a62: f000 f9a1 bl 8002da8 <__sinit>
8002a66: 4b32 ldr r3, [pc, #200] ; (8002b30 <__swsetup_r+0xe4>)
8002a68: 429c cmp r4, r3
8002a6a: d10f bne.n 8002a8c <__swsetup_r+0x40>
8002a6c: 686c ldr r4, [r5, #4]
8002a6e: 230c movs r3, #12
8002a70: 5ee2 ldrsh r2, [r4, r3]
8002a72: b293 uxth r3, r2
8002a74: 0711 lsls r1, r2, #28
8002a76: d42d bmi.n 8002ad4 <__swsetup_r+0x88>
8002a78: 06d9 lsls r1, r3, #27
8002a7a: d411 bmi.n 8002aa0 <__swsetup_r+0x54>
8002a7c: 2309 movs r3, #9
8002a7e: 2001 movs r0, #1
8002a80: 6033 str r3, [r6, #0]
8002a82: 3337 adds r3, #55 ; 0x37
8002a84: 4313 orrs r3, r2
8002a86: 81a3 strh r3, [r4, #12]
8002a88: 4240 negs r0, r0
8002a8a: bd70 pop {r4, r5, r6, pc}
8002a8c: 4b29 ldr r3, [pc, #164] ; (8002b34 <__swsetup_r+0xe8>)
8002a8e: 429c cmp r4, r3
8002a90: d101 bne.n 8002a96 <__swsetup_r+0x4a>
8002a92: 68ac ldr r4, [r5, #8]
8002a94: e7eb b.n 8002a6e <__swsetup_r+0x22>
8002a96: 4b28 ldr r3, [pc, #160] ; (8002b38 <__swsetup_r+0xec>)
8002a98: 429c cmp r4, r3
8002a9a: d1e8 bne.n 8002a6e <__swsetup_r+0x22>
8002a9c: 68ec ldr r4, [r5, #12]
8002a9e: e7e6 b.n 8002a6e <__swsetup_r+0x22>
8002aa0: 075b lsls r3, r3, #29
8002aa2: d513 bpl.n 8002acc <__swsetup_r+0x80>
8002aa4: 6b61 ldr r1, [r4, #52] ; 0x34
8002aa6: 2900 cmp r1, #0
8002aa8: d008 beq.n 8002abc <__swsetup_r+0x70>
8002aaa: 0023 movs r3, r4
8002aac: 3344 adds r3, #68 ; 0x44
8002aae: 4299 cmp r1, r3
8002ab0: d002 beq.n 8002ab8 <__swsetup_r+0x6c>
8002ab2: 0030 movs r0, r6
8002ab4: f7ff fbd6 bl 8002264 <_free_r>
8002ab8: 2300 movs r3, #0
8002aba: 6363 str r3, [r4, #52] ; 0x34
8002abc: 2224 movs r2, #36 ; 0x24
8002abe: 89a3 ldrh r3, [r4, #12]
8002ac0: 4393 bics r3, r2
8002ac2: 81a3 strh r3, [r4, #12]
8002ac4: 2300 movs r3, #0
8002ac6: 6063 str r3, [r4, #4]
8002ac8: 6923 ldr r3, [r4, #16]
8002aca: 6023 str r3, [r4, #0]
8002acc: 2308 movs r3, #8
8002ace: 89a2 ldrh r2, [r4, #12]
8002ad0: 4313 orrs r3, r2
8002ad2: 81a3 strh r3, [r4, #12]
8002ad4: 6923 ldr r3, [r4, #16]
8002ad6: 2b00 cmp r3, #0
8002ad8: d10b bne.n 8002af2 <__swsetup_r+0xa6>
8002ada: 21a0 movs r1, #160 ; 0xa0
8002adc: 2280 movs r2, #128 ; 0x80
8002ade: 89a3 ldrh r3, [r4, #12]
8002ae0: 0089 lsls r1, r1, #2
8002ae2: 0092 lsls r2, r2, #2
8002ae4: 400b ands r3, r1
8002ae6: 4293 cmp r3, r2
8002ae8: d003 beq.n 8002af2 <__swsetup_r+0xa6>
8002aea: 0021 movs r1, r4
8002aec: 0030 movs r0, r6
8002aee: f000 fa27 bl 8002f40 <__smakebuf_r>
8002af2: 220c movs r2, #12
8002af4: 5ea3 ldrsh r3, [r4, r2]
8002af6: 2001 movs r0, #1
8002af8: 001a movs r2, r3
8002afa: b299 uxth r1, r3
8002afc: 4002 ands r2, r0
8002afe: 4203 tst r3, r0
8002b00: d00f beq.n 8002b22 <__swsetup_r+0xd6>
8002b02: 2200 movs r2, #0
8002b04: 60a2 str r2, [r4, #8]
8002b06: 6962 ldr r2, [r4, #20]
8002b08: 4252 negs r2, r2
8002b0a: 61a2 str r2, [r4, #24]
8002b0c: 2000 movs r0, #0
8002b0e: 6922 ldr r2, [r4, #16]
8002b10: 4282 cmp r2, r0
8002b12: d1ba bne.n 8002a8a <__swsetup_r+0x3e>
8002b14: 060a lsls r2, r1, #24
8002b16: d5b8 bpl.n 8002a8a <__swsetup_r+0x3e>
8002b18: 2240 movs r2, #64 ; 0x40
8002b1a: 4313 orrs r3, r2
8002b1c: 81a3 strh r3, [r4, #12]
8002b1e: 3801 subs r0, #1
8002b20: e7b3 b.n 8002a8a <__swsetup_r+0x3e>
8002b22: 0788 lsls r0, r1, #30
8002b24: d400 bmi.n 8002b28 <__swsetup_r+0xdc>
8002b26: 6962 ldr r2, [r4, #20]
8002b28: 60a2 str r2, [r4, #8]
8002b2a: e7ef b.n 8002b0c <__swsetup_r+0xc0>
8002b2c: 2000000c .word 0x2000000c
8002b30: 08003378 .word 0x08003378
8002b34: 08003398 .word 0x08003398
8002b38: 08003358 .word 0x08003358
08002b3c <abort>:
8002b3c: 2006 movs r0, #6
8002b3e: b510 push {r4, lr}
8002b40: f000 fa88 bl 8003054 <raise>
8002b44: 2001 movs r0, #1
8002b46: f7fd fe52 bl 80007ee <_exit>
...
08002b4c <__sflush_r>:
8002b4c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8002b4e: 898b ldrh r3, [r1, #12]
8002b50: 0005 movs r5, r0
8002b52: 000c movs r4, r1
8002b54: 071a lsls r2, r3, #28
8002b56: d45f bmi.n 8002c18 <__sflush_r+0xcc>
8002b58: 684a ldr r2, [r1, #4]
8002b5a: 2a00 cmp r2, #0
8002b5c: dc04 bgt.n 8002b68 <__sflush_r+0x1c>
8002b5e: 6c0a ldr r2, [r1, #64] ; 0x40
8002b60: 2a00 cmp r2, #0
8002b62: dc01 bgt.n 8002b68 <__sflush_r+0x1c>
8002b64: 2000 movs r0, #0
8002b66: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
8002b68: 6ae7 ldr r7, [r4, #44] ; 0x2c
8002b6a: 2f00 cmp r7, #0
8002b6c: d0fa beq.n 8002b64 <__sflush_r+0x18>
8002b6e: 2200 movs r2, #0
8002b70: 2180 movs r1, #128 ; 0x80
8002b72: 682e ldr r6, [r5, #0]
8002b74: 602a str r2, [r5, #0]
8002b76: 001a movs r2, r3
8002b78: 0149 lsls r1, r1, #5
8002b7a: 400a ands r2, r1
8002b7c: 420b tst r3, r1
8002b7e: d034 beq.n 8002bea <__sflush_r+0x9e>
8002b80: 6d60 ldr r0, [r4, #84] ; 0x54
8002b82: 89a3 ldrh r3, [r4, #12]
8002b84: 075b lsls r3, r3, #29
8002b86: d506 bpl.n 8002b96 <__sflush_r+0x4a>
8002b88: 6863 ldr r3, [r4, #4]
8002b8a: 1ac0 subs r0, r0, r3
8002b8c: 6b63 ldr r3, [r4, #52] ; 0x34
8002b8e: 2b00 cmp r3, #0
8002b90: d001 beq.n 8002b96 <__sflush_r+0x4a>
8002b92: 6c23 ldr r3, [r4, #64] ; 0x40
8002b94: 1ac0 subs r0, r0, r3
8002b96: 0002 movs r2, r0
8002b98: 6a21 ldr r1, [r4, #32]
8002b9a: 2300 movs r3, #0
8002b9c: 0028 movs r0, r5
8002b9e: 6ae7 ldr r7, [r4, #44] ; 0x2c
8002ba0: 47b8 blx r7
8002ba2: 89a1 ldrh r1, [r4, #12]
8002ba4: 1c43 adds r3, r0, #1
8002ba6: d106 bne.n 8002bb6 <__sflush_r+0x6a>
8002ba8: 682b ldr r3, [r5, #0]
8002baa: 2b1d cmp r3, #29
8002bac: d831 bhi.n 8002c12 <__sflush_r+0xc6>
8002bae: 4a2c ldr r2, [pc, #176] ; (8002c60 <__sflush_r+0x114>)
8002bb0: 40da lsrs r2, r3
8002bb2: 07d3 lsls r3, r2, #31
8002bb4: d52d bpl.n 8002c12 <__sflush_r+0xc6>
8002bb6: 2300 movs r3, #0
8002bb8: 6063 str r3, [r4, #4]
8002bba: 6923 ldr r3, [r4, #16]
8002bbc: 6023 str r3, [r4, #0]
8002bbe: 04cb lsls r3, r1, #19
8002bc0: d505 bpl.n 8002bce <__sflush_r+0x82>
8002bc2: 1c43 adds r3, r0, #1
8002bc4: d102 bne.n 8002bcc <__sflush_r+0x80>
8002bc6: 682b ldr r3, [r5, #0]
8002bc8: 2b00 cmp r3, #0
8002bca: d100 bne.n 8002bce <__sflush_r+0x82>
8002bcc: 6560 str r0, [r4, #84] ; 0x54
8002bce: 6b61 ldr r1, [r4, #52] ; 0x34
8002bd0: 602e str r6, [r5, #0]
8002bd2: 2900 cmp r1, #0
8002bd4: d0c6 beq.n 8002b64 <__sflush_r+0x18>
8002bd6: 0023 movs r3, r4
8002bd8: 3344 adds r3, #68 ; 0x44
8002bda: 4299 cmp r1, r3
8002bdc: d002 beq.n 8002be4 <__sflush_r+0x98>
8002bde: 0028 movs r0, r5
8002be0: f7ff fb40 bl 8002264 <_free_r>
8002be4: 2000 movs r0, #0
8002be6: 6360 str r0, [r4, #52] ; 0x34
8002be8: e7bd b.n 8002b66 <__sflush_r+0x1a>
8002bea: 2301 movs r3, #1
8002bec: 0028 movs r0, r5
8002bee: 6a21 ldr r1, [r4, #32]
8002bf0: 47b8 blx r7
8002bf2: 1c43 adds r3, r0, #1
8002bf4: d1c5 bne.n 8002b82 <__sflush_r+0x36>
8002bf6: 682b ldr r3, [r5, #0]
8002bf8: 2b00 cmp r3, #0
8002bfa: d0c2 beq.n 8002b82 <__sflush_r+0x36>
8002bfc: 2b1d cmp r3, #29
8002bfe: d001 beq.n 8002c04 <__sflush_r+0xb8>
8002c00: 2b16 cmp r3, #22
8002c02: d101 bne.n 8002c08 <__sflush_r+0xbc>
8002c04: 602e str r6, [r5, #0]
8002c06: e7ad b.n 8002b64 <__sflush_r+0x18>
8002c08: 2340 movs r3, #64 ; 0x40
8002c0a: 89a2 ldrh r2, [r4, #12]
8002c0c: 4313 orrs r3, r2
8002c0e: 81a3 strh r3, [r4, #12]
8002c10: e7a9 b.n 8002b66 <__sflush_r+0x1a>
8002c12: 2340 movs r3, #64 ; 0x40
8002c14: 430b orrs r3, r1
8002c16: e7fa b.n 8002c0e <__sflush_r+0xc2>
8002c18: 690f ldr r7, [r1, #16]
8002c1a: 2f00 cmp r7, #0
8002c1c: d0a2 beq.n 8002b64 <__sflush_r+0x18>
8002c1e: 680a ldr r2, [r1, #0]
8002c20: 600f str r7, [r1, #0]
8002c22: 1bd2 subs r2, r2, r7
8002c24: 9201 str r2, [sp, #4]
8002c26: 2200 movs r2, #0
8002c28: 079b lsls r3, r3, #30
8002c2a: d100 bne.n 8002c2e <__sflush_r+0xe2>
8002c2c: 694a ldr r2, [r1, #20]
8002c2e: 60a2 str r2, [r4, #8]
8002c30: 9b01 ldr r3, [sp, #4]
8002c32: 2b00 cmp r3, #0
8002c34: dc00 bgt.n 8002c38 <__sflush_r+0xec>
8002c36: e795 b.n 8002b64 <__sflush_r+0x18>
8002c38: 003a movs r2, r7
8002c3a: 0028 movs r0, r5
8002c3c: 9b01 ldr r3, [sp, #4]
8002c3e: 6a21 ldr r1, [r4, #32]
8002c40: 6aa6 ldr r6, [r4, #40] ; 0x28
8002c42: 47b0 blx r6
8002c44: 2800 cmp r0, #0
8002c46: dc06 bgt.n 8002c56 <__sflush_r+0x10a>
8002c48: 2340 movs r3, #64 ; 0x40
8002c4a: 2001 movs r0, #1
8002c4c: 89a2 ldrh r2, [r4, #12]
8002c4e: 4240 negs r0, r0
8002c50: 4313 orrs r3, r2
8002c52: 81a3 strh r3, [r4, #12]
8002c54: e787 b.n 8002b66 <__sflush_r+0x1a>
8002c56: 9b01 ldr r3, [sp, #4]
8002c58: 183f adds r7, r7, r0
8002c5a: 1a1b subs r3, r3, r0
8002c5c: 9301 str r3, [sp, #4]
8002c5e: e7e7 b.n 8002c30 <__sflush_r+0xe4>
8002c60: 20400001 .word 0x20400001
08002c64 <_fflush_r>:
8002c64: 690b ldr r3, [r1, #16]
8002c66: b570 push {r4, r5, r6, lr}
8002c68: 0005 movs r5, r0
8002c6a: 000c movs r4, r1
8002c6c: 2b00 cmp r3, #0
8002c6e: d102 bne.n 8002c76 <_fflush_r+0x12>
8002c70: 2500 movs r5, #0
8002c72: 0028 movs r0, r5
8002c74: bd70 pop {r4, r5, r6, pc}
8002c76: 2800 cmp r0, #0
8002c78: d004 beq.n 8002c84 <_fflush_r+0x20>
8002c7a: 6983 ldr r3, [r0, #24]
8002c7c: 2b00 cmp r3, #0
8002c7e: d101 bne.n 8002c84 <_fflush_r+0x20>
8002c80: f000 f892 bl 8002da8 <__sinit>
8002c84: 4b14 ldr r3, [pc, #80] ; (8002cd8 <_fflush_r+0x74>)
8002c86: 429c cmp r4, r3
8002c88: d11b bne.n 8002cc2 <_fflush_r+0x5e>
8002c8a: 686c ldr r4, [r5, #4]
8002c8c: 220c movs r2, #12
8002c8e: 5ea3 ldrsh r3, [r4, r2]
8002c90: 2b00 cmp r3, #0
8002c92: d0ed beq.n 8002c70 <_fflush_r+0xc>
8002c94: 6e62 ldr r2, [r4, #100] ; 0x64
8002c96: 07d2 lsls r2, r2, #31
8002c98: d404 bmi.n 8002ca4 <_fflush_r+0x40>
8002c9a: 059b lsls r3, r3, #22
8002c9c: d402 bmi.n 8002ca4 <_fflush_r+0x40>
8002c9e: 6da0 ldr r0, [r4, #88] ; 0x58
8002ca0: f000 f923 bl 8002eea <__retarget_lock_acquire_recursive>
8002ca4: 0028 movs r0, r5
8002ca6: 0021 movs r1, r4
8002ca8: f7ff ff50 bl 8002b4c <__sflush_r>
8002cac: 6e63 ldr r3, [r4, #100] ; 0x64
8002cae: 0005 movs r5, r0
8002cb0: 07db lsls r3, r3, #31
8002cb2: d4de bmi.n 8002c72 <_fflush_r+0xe>
8002cb4: 89a3 ldrh r3, [r4, #12]
8002cb6: 059b lsls r3, r3, #22
8002cb8: d4db bmi.n 8002c72 <_fflush_r+0xe>
8002cba: 6da0 ldr r0, [r4, #88] ; 0x58
8002cbc: f000 f916 bl 8002eec <__retarget_lock_release_recursive>
8002cc0: e7d7 b.n 8002c72 <_fflush_r+0xe>
8002cc2: 4b06 ldr r3, [pc, #24] ; (8002cdc <_fflush_r+0x78>)
8002cc4: 429c cmp r4, r3
8002cc6: d101 bne.n 8002ccc <_fflush_r+0x68>
8002cc8: 68ac ldr r4, [r5, #8]
8002cca: e7df b.n 8002c8c <_fflush_r+0x28>
8002ccc: 4b04 ldr r3, [pc, #16] ; (8002ce0 <_fflush_r+0x7c>)
8002cce: 429c cmp r4, r3
8002cd0: d1dc bne.n 8002c8c <_fflush_r+0x28>
8002cd2: 68ec ldr r4, [r5, #12]
8002cd4: e7da b.n 8002c8c <_fflush_r+0x28>
8002cd6: 46c0 nop ; (mov r8, r8)
8002cd8: 08003378 .word 0x08003378
8002cdc: 08003398 .word 0x08003398
8002ce0: 08003358 .word 0x08003358
08002ce4 <std>:
8002ce4: 2300 movs r3, #0
8002ce6: b510 push {r4, lr}
8002ce8: 0004 movs r4, r0
8002cea: 6003 str r3, [r0, #0]
8002cec: 6043 str r3, [r0, #4]
8002cee: 6083 str r3, [r0, #8]
8002cf0: 8181 strh r1, [r0, #12]
8002cf2: 6643 str r3, [r0, #100] ; 0x64
8002cf4: 0019 movs r1, r3
8002cf6: 81c2 strh r2, [r0, #14]
8002cf8: 6103 str r3, [r0, #16]
8002cfa: 6143 str r3, [r0, #20]
8002cfc: 6183 str r3, [r0, #24]
8002cfe: 2208 movs r2, #8
8002d00: 305c adds r0, #92 ; 0x5c
8002d02: f7ff fa31 bl 8002168 <memset>
8002d06: 4b05 ldr r3, [pc, #20] ; (8002d1c <std+0x38>)
8002d08: 6263 str r3, [r4, #36] ; 0x24
8002d0a: 4b05 ldr r3, [pc, #20] ; (8002d20 <std+0x3c>)
8002d0c: 6224 str r4, [r4, #32]
8002d0e: 62a3 str r3, [r4, #40] ; 0x28
8002d10: 4b04 ldr r3, [pc, #16] ; (8002d24 <std+0x40>)
8002d12: 62e3 str r3, [r4, #44] ; 0x2c
8002d14: 4b04 ldr r3, [pc, #16] ; (8002d28 <std+0x44>)
8002d16: 6323 str r3, [r4, #48] ; 0x30
8002d18: bd10 pop {r4, pc}
8002d1a: 46c0 nop ; (mov r8, r8)
8002d1c: 08003095 .word 0x08003095
8002d20: 080030bd .word 0x080030bd
8002d24: 080030f5 .word 0x080030f5
8002d28: 08003121 .word 0x08003121
08002d2c <_cleanup_r>:
8002d2c: b510 push {r4, lr}
8002d2e: 4902 ldr r1, [pc, #8] ; (8002d38 <_cleanup_r+0xc>)
8002d30: f000 f8ba bl 8002ea8 <_fwalk_reent>
8002d34: bd10 pop {r4, pc}
8002d36: 46c0 nop ; (mov r8, r8)
8002d38: 08002c65 .word 0x08002c65
08002d3c <__sfmoreglue>:
8002d3c: b570 push {r4, r5, r6, lr}
8002d3e: 2568 movs r5, #104 ; 0x68
8002d40: 1e4a subs r2, r1, #1
8002d42: 4355 muls r5, r2
8002d44: 000e movs r6, r1
8002d46: 0029 movs r1, r5
8002d48: 3174 adds r1, #116 ; 0x74
8002d4a: f7ff fad5 bl 80022f8 <_malloc_r>
8002d4e: 1e04 subs r4, r0, #0
8002d50: d008 beq.n 8002d64 <__sfmoreglue+0x28>
8002d52: 2100 movs r1, #0
8002d54: 002a movs r2, r5
8002d56: 6001 str r1, [r0, #0]
8002d58: 6046 str r6, [r0, #4]
8002d5a: 300c adds r0, #12
8002d5c: 60a0 str r0, [r4, #8]
8002d5e: 3268 adds r2, #104 ; 0x68
8002d60: f7ff fa02 bl 8002168 <memset>
8002d64: 0020 movs r0, r4
8002d66: bd70 pop {r4, r5, r6, pc}
08002d68 <__sfp_lock_acquire>:
8002d68: b510 push {r4, lr}
8002d6a: 4802 ldr r0, [pc, #8] ; (8002d74 <__sfp_lock_acquire+0xc>)
8002d6c: f000 f8bd bl 8002eea <__retarget_lock_acquire_recursive>
8002d70: bd10 pop {r4, pc}
8002d72: 46c0 nop ; (mov r8, r8)
8002d74: 200000e9 .word 0x200000e9
08002d78 <__sfp_lock_release>:
8002d78: b510 push {r4, lr}
8002d7a: 4802 ldr r0, [pc, #8] ; (8002d84 <__sfp_lock_release+0xc>)
8002d7c: f000 f8b6 bl 8002eec <__retarget_lock_release_recursive>
8002d80: bd10 pop {r4, pc}
8002d82: 46c0 nop ; (mov r8, r8)
8002d84: 200000e9 .word 0x200000e9
08002d88 <__sinit_lock_acquire>:
8002d88: b510 push {r4, lr}
8002d8a: 4802 ldr r0, [pc, #8] ; (8002d94 <__sinit_lock_acquire+0xc>)
8002d8c: f000 f8ad bl 8002eea <__retarget_lock_acquire_recursive>
8002d90: bd10 pop {r4, pc}
8002d92: 46c0 nop ; (mov r8, r8)
8002d94: 200000e4 .word 0x200000e4
08002d98 <__sinit_lock_release>:
8002d98: b510 push {r4, lr}
8002d9a: 4802 ldr r0, [pc, #8] ; (8002da4 <__sinit_lock_release+0xc>)
8002d9c: f000 f8a6 bl 8002eec <__retarget_lock_release_recursive>
8002da0: bd10 pop {r4, pc}
8002da2: 46c0 nop ; (mov r8, r8)
8002da4: 200000e4 .word 0x200000e4
08002da8 <__sinit>:
8002da8: b513 push {r0, r1, r4, lr}
8002daa: 0004 movs r4, r0
8002dac: f7ff ffec bl 8002d88 <__sinit_lock_acquire>
8002db0: 69a3 ldr r3, [r4, #24]
8002db2: 2b00 cmp r3, #0
8002db4: d002 beq.n 8002dbc <__sinit+0x14>
8002db6: f7ff ffef bl 8002d98 <__sinit_lock_release>
8002dba: bd13 pop {r0, r1, r4, pc}
8002dbc: 64a3 str r3, [r4, #72] ; 0x48
8002dbe: 64e3 str r3, [r4, #76] ; 0x4c
8002dc0: 6523 str r3, [r4, #80] ; 0x50
8002dc2: 4b13 ldr r3, [pc, #76] ; (8002e10 <__sinit+0x68>)
8002dc4: 4a13 ldr r2, [pc, #76] ; (8002e14 <__sinit+0x6c>)
8002dc6: 681b ldr r3, [r3, #0]
8002dc8: 62a2 str r2, [r4, #40] ; 0x28
8002dca: 9301 str r3, [sp, #4]
8002dcc: 42a3 cmp r3, r4
8002dce: d101 bne.n 8002dd4 <__sinit+0x2c>
8002dd0: 2301 movs r3, #1
8002dd2: 61a3 str r3, [r4, #24]
8002dd4: 0020 movs r0, r4
8002dd6: f000 f81f bl 8002e18 <__sfp>
8002dda: 6060 str r0, [r4, #4]
8002ddc: 0020 movs r0, r4
8002dde: f000 f81b bl 8002e18 <__sfp>
8002de2: 60a0 str r0, [r4, #8]
8002de4: 0020 movs r0, r4
8002de6: f000 f817 bl 8002e18 <__sfp>
8002dea: 2200 movs r2, #0
8002dec: 2104 movs r1, #4
8002dee: 60e0 str r0, [r4, #12]
8002df0: 6860 ldr r0, [r4, #4]
8002df2: f7ff ff77 bl 8002ce4 <std>
8002df6: 2201 movs r2, #1
8002df8: 2109 movs r1, #9
8002dfa: 68a0 ldr r0, [r4, #8]
8002dfc: f7ff ff72 bl 8002ce4 <std>
8002e00: 2202 movs r2, #2
8002e02: 2112 movs r1, #18
8002e04: 68e0 ldr r0, [r4, #12]
8002e06: f7ff ff6d bl 8002ce4 <std>
8002e0a: 2301 movs r3, #1
8002e0c: 61a3 str r3, [r4, #24]
8002e0e: e7d2 b.n 8002db6 <__sinit+0xe>
8002e10: 0800326c .word 0x0800326c
8002e14: 08002d2d .word 0x08002d2d
08002e18 <__sfp>:
8002e18: b5f8 push {r3, r4, r5, r6, r7, lr}
8002e1a: 0007 movs r7, r0
8002e1c: f7ff ffa4 bl 8002d68 <__sfp_lock_acquire>
8002e20: 4b1f ldr r3, [pc, #124] ; (8002ea0 <__sfp+0x88>)
8002e22: 681e ldr r6, [r3, #0]
8002e24: 69b3 ldr r3, [r6, #24]
8002e26: 2b00 cmp r3, #0
8002e28: d102 bne.n 8002e30 <__sfp+0x18>
8002e2a: 0030 movs r0, r6
8002e2c: f7ff ffbc bl 8002da8 <__sinit>
8002e30: 3648 adds r6, #72 ; 0x48
8002e32: 68b4 ldr r4, [r6, #8]
8002e34: 6873 ldr r3, [r6, #4]
8002e36: 3b01 subs r3, #1
8002e38: d504 bpl.n 8002e44 <__sfp+0x2c>
8002e3a: 6833 ldr r3, [r6, #0]
8002e3c: 2b00 cmp r3, #0
8002e3e: d022 beq.n 8002e86 <__sfp+0x6e>
8002e40: 6836 ldr r6, [r6, #0]
8002e42: e7f6 b.n 8002e32 <__sfp+0x1a>
8002e44: 220c movs r2, #12
8002e46: 5ea5 ldrsh r5, [r4, r2]
8002e48: 2d00 cmp r5, #0
8002e4a: d11a bne.n 8002e82 <__sfp+0x6a>
8002e4c: 0020 movs r0, r4
8002e4e: 4b15 ldr r3, [pc, #84] ; (8002ea4 <__sfp+0x8c>)
8002e50: 3058 adds r0, #88 ; 0x58
8002e52: 60e3 str r3, [r4, #12]
8002e54: 6665 str r5, [r4, #100] ; 0x64
8002e56: f000 f847 bl 8002ee8 <__retarget_lock_init_recursive>
8002e5a: f7ff ff8d bl 8002d78 <__sfp_lock_release>
8002e5e: 0020 movs r0, r4
8002e60: 2208 movs r2, #8
8002e62: 0029 movs r1, r5
8002e64: 6025 str r5, [r4, #0]
8002e66: 60a5 str r5, [r4, #8]
8002e68: 6065 str r5, [r4, #4]
8002e6a: 6125 str r5, [r4, #16]
8002e6c: 6165 str r5, [r4, #20]
8002e6e: 61a5 str r5, [r4, #24]
8002e70: 305c adds r0, #92 ; 0x5c
8002e72: f7ff f979 bl 8002168 <memset>
8002e76: 6365 str r5, [r4, #52] ; 0x34
8002e78: 63a5 str r5, [r4, #56] ; 0x38
8002e7a: 64a5 str r5, [r4, #72] ; 0x48
8002e7c: 64e5 str r5, [r4, #76] ; 0x4c
8002e7e: 0020 movs r0, r4
8002e80: bdf8 pop {r3, r4, r5, r6, r7, pc}
8002e82: 3468 adds r4, #104 ; 0x68
8002e84: e7d7 b.n 8002e36 <__sfp+0x1e>
8002e86: 2104 movs r1, #4
8002e88: 0038 movs r0, r7
8002e8a: f7ff ff57 bl 8002d3c <__sfmoreglue>
8002e8e: 1e04 subs r4, r0, #0
8002e90: 6030 str r0, [r6, #0]
8002e92: d1d5 bne.n 8002e40 <__sfp+0x28>
8002e94: f7ff ff70 bl 8002d78 <__sfp_lock_release>
8002e98: 230c movs r3, #12
8002e9a: 603b str r3, [r7, #0]
8002e9c: e7ef b.n 8002e7e <__sfp+0x66>
8002e9e: 46c0 nop ; (mov r8, r8)
8002ea0: 0800326c .word 0x0800326c
8002ea4: ffff0001 .word 0xffff0001
08002ea8 <_fwalk_reent>:
8002ea8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8002eaa: 0004 movs r4, r0
8002eac: 0006 movs r6, r0
8002eae: 2700 movs r7, #0
8002eb0: 9101 str r1, [sp, #4]
8002eb2: 3448 adds r4, #72 ; 0x48
8002eb4: 6863 ldr r3, [r4, #4]
8002eb6: 68a5 ldr r5, [r4, #8]
8002eb8: 9300 str r3, [sp, #0]
8002eba: 9b00 ldr r3, [sp, #0]
8002ebc: 3b01 subs r3, #1
8002ebe: 9300 str r3, [sp, #0]
8002ec0: d504 bpl.n 8002ecc <_fwalk_reent+0x24>
8002ec2: 6824 ldr r4, [r4, #0]
8002ec4: 2c00 cmp r4, #0
8002ec6: d1f5 bne.n 8002eb4 <_fwalk_reent+0xc>
8002ec8: 0038 movs r0, r7
8002eca: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
8002ecc: 89ab ldrh r3, [r5, #12]
8002ece: 2b01 cmp r3, #1
8002ed0: d908 bls.n 8002ee4 <_fwalk_reent+0x3c>
8002ed2: 220e movs r2, #14
8002ed4: 5eab ldrsh r3, [r5, r2]
8002ed6: 3301 adds r3, #1
8002ed8: d004 beq.n 8002ee4 <_fwalk_reent+0x3c>
8002eda: 0029 movs r1, r5
8002edc: 0030 movs r0, r6
8002ede: 9b01 ldr r3, [sp, #4]
8002ee0: 4798 blx r3
8002ee2: 4307 orrs r7, r0
8002ee4: 3568 adds r5, #104 ; 0x68
8002ee6: e7e8 b.n 8002eba <_fwalk_reent+0x12>
08002ee8 <__retarget_lock_init_recursive>:
8002ee8: 4770 bx lr
08002eea <__retarget_lock_acquire_recursive>:
8002eea: 4770 bx lr
08002eec <__retarget_lock_release_recursive>:
8002eec: 4770 bx lr
...
08002ef0 <__swhatbuf_r>:
8002ef0: b570 push {r4, r5, r6, lr}
8002ef2: 000e movs r6, r1
8002ef4: 001d movs r5, r3
8002ef6: 230e movs r3, #14
8002ef8: 5ec9 ldrsh r1, [r1, r3]
8002efa: 0014 movs r4, r2
8002efc: b096 sub sp, #88 ; 0x58
8002efe: 2900 cmp r1, #0
8002f00: da07 bge.n 8002f12 <__swhatbuf_r+0x22>
8002f02: 2300 movs r3, #0
8002f04: 602b str r3, [r5, #0]
8002f06: 89b3 ldrh r3, [r6, #12]
8002f08: 061b lsls r3, r3, #24
8002f0a: d411 bmi.n 8002f30 <__swhatbuf_r+0x40>
8002f0c: 2380 movs r3, #128 ; 0x80
8002f0e: 00db lsls r3, r3, #3
8002f10: e00f b.n 8002f32 <__swhatbuf_r+0x42>
8002f12: 466a mov r2, sp
8002f14: f000 f930 bl 8003178 <_fstat_r>
8002f18: 2800 cmp r0, #0
8002f1a: dbf2 blt.n 8002f02 <__swhatbuf_r+0x12>
8002f1c: 23f0 movs r3, #240 ; 0xf0
8002f1e: 9901 ldr r1, [sp, #4]
8002f20: 021b lsls r3, r3, #8
8002f22: 4019 ands r1, r3
8002f24: 4b05 ldr r3, [pc, #20] ; (8002f3c <__swhatbuf_r+0x4c>)
8002f26: 18c9 adds r1, r1, r3
8002f28: 424b negs r3, r1
8002f2a: 4159 adcs r1, r3
8002f2c: 6029 str r1, [r5, #0]
8002f2e: e7ed b.n 8002f0c <__swhatbuf_r+0x1c>
8002f30: 2340 movs r3, #64 ; 0x40
8002f32: 2000 movs r0, #0
8002f34: 6023 str r3, [r4, #0]
8002f36: b016 add sp, #88 ; 0x58
8002f38: bd70 pop {r4, r5, r6, pc}
8002f3a: 46c0 nop ; (mov r8, r8)
8002f3c: ffffe000 .word 0xffffe000
08002f40 <__smakebuf_r>:
8002f40: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8002f42: 2602 movs r6, #2
8002f44: 898b ldrh r3, [r1, #12]
8002f46: 0005 movs r5, r0
8002f48: 000c movs r4, r1
8002f4a: 4233 tst r3, r6
8002f4c: d006 beq.n 8002f5c <__smakebuf_r+0x1c>
8002f4e: 0023 movs r3, r4
8002f50: 3347 adds r3, #71 ; 0x47
8002f52: 6023 str r3, [r4, #0]
8002f54: 6123 str r3, [r4, #16]
8002f56: 2301 movs r3, #1
8002f58: 6163 str r3, [r4, #20]
8002f5a: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
8002f5c: 466a mov r2, sp
8002f5e: ab01 add r3, sp, #4
8002f60: f7ff ffc6 bl 8002ef0 <__swhatbuf_r>
8002f64: 9900 ldr r1, [sp, #0]
8002f66: 0007 movs r7, r0
8002f68: 0028 movs r0, r5
8002f6a: f7ff f9c5 bl 80022f8 <_malloc_r>
8002f6e: 2800 cmp r0, #0
8002f70: d108 bne.n 8002f84 <__smakebuf_r+0x44>
8002f72: 220c movs r2, #12
8002f74: 5ea3 ldrsh r3, [r4, r2]
8002f76: 059a lsls r2, r3, #22
8002f78: d4ef bmi.n 8002f5a <__smakebuf_r+0x1a>
8002f7a: 2203 movs r2, #3
8002f7c: 4393 bics r3, r2
8002f7e: 431e orrs r6, r3
8002f80: 81a6 strh r6, [r4, #12]
8002f82: e7e4 b.n 8002f4e <__smakebuf_r+0xe>
8002f84: 4b0f ldr r3, [pc, #60] ; (8002fc4 <__smakebuf_r+0x84>)
8002f86: 62ab str r3, [r5, #40] ; 0x28
8002f88: 2380 movs r3, #128 ; 0x80
8002f8a: 89a2 ldrh r2, [r4, #12]
8002f8c: 6020 str r0, [r4, #0]
8002f8e: 4313 orrs r3, r2
8002f90: 81a3 strh r3, [r4, #12]
8002f92: 9b00 ldr r3, [sp, #0]
8002f94: 6120 str r0, [r4, #16]
8002f96: 6163 str r3, [r4, #20]
8002f98: 9b01 ldr r3, [sp, #4]
8002f9a: 2b00 cmp r3, #0
8002f9c: d00d beq.n 8002fba <__smakebuf_r+0x7a>
8002f9e: 0028 movs r0, r5
8002fa0: 230e movs r3, #14
8002fa2: 5ee1 ldrsh r1, [r4, r3]
8002fa4: f000 f8fa bl 800319c <_isatty_r>
8002fa8: 2800 cmp r0, #0
8002faa: d006 beq.n 8002fba <__smakebuf_r+0x7a>
8002fac: 2203 movs r2, #3
8002fae: 89a3 ldrh r3, [r4, #12]
8002fb0: 4393 bics r3, r2
8002fb2: 001a movs r2, r3
8002fb4: 2301 movs r3, #1
8002fb6: 4313 orrs r3, r2
8002fb8: 81a3 strh r3, [r4, #12]
8002fba: 89a0 ldrh r0, [r4, #12]
8002fbc: 4307 orrs r7, r0
8002fbe: 81a7 strh r7, [r4, #12]
8002fc0: e7cb b.n 8002f5a <__smakebuf_r+0x1a>
8002fc2: 46c0 nop ; (mov r8, r8)
8002fc4: 08002d2d .word 0x08002d2d
08002fc8 <memchr>:
8002fc8: b2c9 uxtb r1, r1
8002fca: 1882 adds r2, r0, r2
8002fcc: 4290 cmp r0, r2
8002fce: d101 bne.n 8002fd4 <memchr+0xc>
8002fd0: 2000 movs r0, #0
8002fd2: 4770 bx lr
8002fd4: 7803 ldrb r3, [r0, #0]
8002fd6: 428b cmp r3, r1
8002fd8: d0fb beq.n 8002fd2 <memchr+0xa>
8002fda: 3001 adds r0, #1
8002fdc: e7f6 b.n 8002fcc <memchr+0x4>
...
08002fe0 <__malloc_lock>:
8002fe0: b510 push {r4, lr}
8002fe2: 4802 ldr r0, [pc, #8] ; (8002fec <__malloc_lock+0xc>)
8002fe4: f7ff ff81 bl 8002eea <__retarget_lock_acquire_recursive>
8002fe8: bd10 pop {r4, pc}
8002fea: 46c0 nop ; (mov r8, r8)
8002fec: 200000e5 .word 0x200000e5
08002ff0 <__malloc_unlock>:
8002ff0: b510 push {r4, lr}
8002ff2: 4802 ldr r0, [pc, #8] ; (8002ffc <__malloc_unlock+0xc>)
8002ff4: f7ff ff7a bl 8002eec <__retarget_lock_release_recursive>
8002ff8: bd10 pop {r4, pc}
8002ffa: 46c0 nop ; (mov r8, r8)
8002ffc: 200000e5 .word 0x200000e5
08003000 <_raise_r>:
8003000: b570 push {r4, r5, r6, lr}
8003002: 0004 movs r4, r0
8003004: 000d movs r5, r1
8003006: 291f cmp r1, #31
8003008: d904 bls.n 8003014 <_raise_r+0x14>
800300a: 2316 movs r3, #22
800300c: 6003 str r3, [r0, #0]
800300e: 2001 movs r0, #1
8003010: 4240 negs r0, r0
8003012: bd70 pop {r4, r5, r6, pc}
8003014: 6c43 ldr r3, [r0, #68] ; 0x44
8003016: 2b00 cmp r3, #0
8003018: d004 beq.n 8003024 <_raise_r+0x24>
800301a: 008a lsls r2, r1, #2
800301c: 189b adds r3, r3, r2
800301e: 681a ldr r2, [r3, #0]
8003020: 2a00 cmp r2, #0
8003022: d108 bne.n 8003036 <_raise_r+0x36>
8003024: 0020 movs r0, r4
8003026: f000 f831 bl 800308c <_getpid_r>
800302a: 002a movs r2, r5
800302c: 0001 movs r1, r0
800302e: 0020 movs r0, r4
8003030: f000 f81a bl 8003068 <_kill_r>
8003034: e7ed b.n 8003012 <_raise_r+0x12>
8003036: 2000 movs r0, #0
8003038: 2a01 cmp r2, #1
800303a: d0ea beq.n 8003012 <_raise_r+0x12>
800303c: 1c51 adds r1, r2, #1
800303e: d103 bne.n 8003048 <_raise_r+0x48>
8003040: 2316 movs r3, #22
8003042: 3001 adds r0, #1
8003044: 6023 str r3, [r4, #0]
8003046: e7e4 b.n 8003012 <_raise_r+0x12>
8003048: 2400 movs r4, #0
800304a: 0028 movs r0, r5
800304c: 601c str r4, [r3, #0]
800304e: 4790 blx r2
8003050: 0020 movs r0, r4
8003052: e7de b.n 8003012 <_raise_r+0x12>
08003054 <raise>:
8003054: b510 push {r4, lr}
8003056: 4b03 ldr r3, [pc, #12] ; (8003064 <raise+0x10>)
8003058: 0001 movs r1, r0
800305a: 6818 ldr r0, [r3, #0]
800305c: f7ff ffd0 bl 8003000 <_raise_r>
8003060: bd10 pop {r4, pc}
8003062: 46c0 nop ; (mov r8, r8)
8003064: 2000000c .word 0x2000000c
08003068 <_kill_r>:
8003068: 2300 movs r3, #0
800306a: b570 push {r4, r5, r6, lr}
800306c: 4d06 ldr r5, [pc, #24] ; (8003088 <_kill_r+0x20>)
800306e: 0004 movs r4, r0
8003070: 0008 movs r0, r1
8003072: 0011 movs r1, r2
8003074: 602b str r3, [r5, #0]
8003076: f7fd fbaa bl 80007ce <_kill>
800307a: 1c43 adds r3, r0, #1
800307c: d103 bne.n 8003086 <_kill_r+0x1e>
800307e: 682b ldr r3, [r5, #0]
8003080: 2b00 cmp r3, #0
8003082: d000 beq.n 8003086 <_kill_r+0x1e>
8003084: 6023 str r3, [r4, #0]
8003086: bd70 pop {r4, r5, r6, pc}
8003088: 200000ec .word 0x200000ec
0800308c <_getpid_r>:
800308c: b510 push {r4, lr}
800308e: f7fd fb98 bl 80007c2 <_getpid>
8003092: bd10 pop {r4, pc}
08003094 <__sread>:
8003094: b570 push {r4, r5, r6, lr}
8003096: 000c movs r4, r1
8003098: 250e movs r5, #14
800309a: 5f49 ldrsh r1, [r1, r5]
800309c: f000 f8a4 bl 80031e8 <_read_r>
80030a0: 2800 cmp r0, #0
80030a2: db03 blt.n 80030ac <__sread+0x18>
80030a4: 6d63 ldr r3, [r4, #84] ; 0x54
80030a6: 181b adds r3, r3, r0
80030a8: 6563 str r3, [r4, #84] ; 0x54
80030aa: bd70 pop {r4, r5, r6, pc}
80030ac: 89a3 ldrh r3, [r4, #12]
80030ae: 4a02 ldr r2, [pc, #8] ; (80030b8 <__sread+0x24>)
80030b0: 4013 ands r3, r2
80030b2: 81a3 strh r3, [r4, #12]
80030b4: e7f9 b.n 80030aa <__sread+0x16>
80030b6: 46c0 nop ; (mov r8, r8)
80030b8: ffffefff .word 0xffffefff
080030bc <__swrite>:
80030bc: b5f8 push {r3, r4, r5, r6, r7, lr}
80030be: 001f movs r7, r3
80030c0: 898b ldrh r3, [r1, #12]
80030c2: 0005 movs r5, r0
80030c4: 000c movs r4, r1
80030c6: 0016 movs r6, r2
80030c8: 05db lsls r3, r3, #23
80030ca: d505 bpl.n 80030d8 <__swrite+0x1c>
80030cc: 230e movs r3, #14
80030ce: 5ec9 ldrsh r1, [r1, r3]
80030d0: 2200 movs r2, #0
80030d2: 2302 movs r3, #2
80030d4: f000 f874 bl 80031c0 <_lseek_r>
80030d8: 89a3 ldrh r3, [r4, #12]
80030da: 4a05 ldr r2, [pc, #20] ; (80030f0 <__swrite+0x34>)
80030dc: 0028 movs r0, r5
80030de: 4013 ands r3, r2
80030e0: 81a3 strh r3, [r4, #12]
80030e2: 0032 movs r2, r6
80030e4: 230e movs r3, #14
80030e6: 5ee1 ldrsh r1, [r4, r3]
80030e8: 003b movs r3, r7
80030ea: f000 f81f bl 800312c <_write_r>
80030ee: bdf8 pop {r3, r4, r5, r6, r7, pc}
80030f0: ffffefff .word 0xffffefff
080030f4 <__sseek>:
80030f4: b570 push {r4, r5, r6, lr}
80030f6: 000c movs r4, r1
80030f8: 250e movs r5, #14
80030fa: 5f49 ldrsh r1, [r1, r5]
80030fc: f000 f860 bl 80031c0 <_lseek_r>
8003100: 89a3 ldrh r3, [r4, #12]
8003102: 1c42 adds r2, r0, #1
8003104: d103 bne.n 800310e <__sseek+0x1a>
8003106: 4a05 ldr r2, [pc, #20] ; (800311c <__sseek+0x28>)
8003108: 4013 ands r3, r2
800310a: 81a3 strh r3, [r4, #12]
800310c: bd70 pop {r4, r5, r6, pc}
800310e: 2280 movs r2, #128 ; 0x80
8003110: 0152 lsls r2, r2, #5
8003112: 4313 orrs r3, r2
8003114: 81a3 strh r3, [r4, #12]
8003116: 6560 str r0, [r4, #84] ; 0x54
8003118: e7f8 b.n 800310c <__sseek+0x18>
800311a: 46c0 nop ; (mov r8, r8)
800311c: ffffefff .word 0xffffefff
08003120 <__sclose>:
8003120: b510 push {r4, lr}
8003122: 230e movs r3, #14
8003124: 5ec9 ldrsh r1, [r1, r3]
8003126: f000 f815 bl 8003154 <_close_r>
800312a: bd10 pop {r4, pc}
0800312c <_write_r>:
800312c: b570 push {r4, r5, r6, lr}
800312e: 0004 movs r4, r0
8003130: 0008 movs r0, r1
8003132: 0011 movs r1, r2
8003134: 001a movs r2, r3
8003136: 2300 movs r3, #0
8003138: 4d05 ldr r5, [pc, #20] ; (8003150 <_write_r+0x24>)
800313a: 602b str r3, [r5, #0]
800313c: f7fd fb80 bl 8000840 <_write>
8003140: 1c43 adds r3, r0, #1
8003142: d103 bne.n 800314c <_write_r+0x20>
8003144: 682b ldr r3, [r5, #0]
8003146: 2b00 cmp r3, #0
8003148: d000 beq.n 800314c <_write_r+0x20>
800314a: 6023 str r3, [r4, #0]
800314c: bd70 pop {r4, r5, r6, pc}
800314e: 46c0 nop ; (mov r8, r8)
8003150: 200000ec .word 0x200000ec
08003154 <_close_r>:
8003154: 2300 movs r3, #0
8003156: b570 push {r4, r5, r6, lr}
8003158: 4d06 ldr r5, [pc, #24] ; (8003174 <_close_r+0x20>)
800315a: 0004 movs r4, r0
800315c: 0008 movs r0, r1
800315e: 602b str r3, [r5, #0]
8003160: f7fd fb8a bl 8000878 <_close>
8003164: 1c43 adds r3, r0, #1
8003166: d103 bne.n 8003170 <_close_r+0x1c>
8003168: 682b ldr r3, [r5, #0]
800316a: 2b00 cmp r3, #0
800316c: d000 beq.n 8003170 <_close_r+0x1c>
800316e: 6023 str r3, [r4, #0]
8003170: bd70 pop {r4, r5, r6, pc}
8003172: 46c0 nop ; (mov r8, r8)
8003174: 200000ec .word 0x200000ec
08003178 <_fstat_r>:
8003178: 2300 movs r3, #0
800317a: b570 push {r4, r5, r6, lr}
800317c: 4d06 ldr r5, [pc, #24] ; (8003198 <_fstat_r+0x20>)
800317e: 0004 movs r4, r0
8003180: 0008 movs r0, r1
8003182: 0011 movs r1, r2
8003184: 602b str r3, [r5, #0]
8003186: f7fd fb81 bl 800088c <_fstat>
800318a: 1c43 adds r3, r0, #1
800318c: d103 bne.n 8003196 <_fstat_r+0x1e>
800318e: 682b ldr r3, [r5, #0]
8003190: 2b00 cmp r3, #0
8003192: d000 beq.n 8003196 <_fstat_r+0x1e>
8003194: 6023 str r3, [r4, #0]
8003196: bd70 pop {r4, r5, r6, pc}
8003198: 200000ec .word 0x200000ec
0800319c <_isatty_r>:
800319c: 2300 movs r3, #0
800319e: b570 push {r4, r5, r6, lr}
80031a0: 4d06 ldr r5, [pc, #24] ; (80031bc <_isatty_r+0x20>)
80031a2: 0004 movs r4, r0
80031a4: 0008 movs r0, r1
80031a6: 602b str r3, [r5, #0]
80031a8: f7fd fb7e bl 80008a8 <_isatty>
80031ac: 1c43 adds r3, r0, #1
80031ae: d103 bne.n 80031b8 <_isatty_r+0x1c>
80031b0: 682b ldr r3, [r5, #0]
80031b2: 2b00 cmp r3, #0
80031b4: d000 beq.n 80031b8 <_isatty_r+0x1c>
80031b6: 6023 str r3, [r4, #0]
80031b8: bd70 pop {r4, r5, r6, pc}
80031ba: 46c0 nop ; (mov r8, r8)
80031bc: 200000ec .word 0x200000ec
080031c0 <_lseek_r>:
80031c0: b570 push {r4, r5, r6, lr}
80031c2: 0004 movs r4, r0
80031c4: 0008 movs r0, r1
80031c6: 0011 movs r1, r2
80031c8: 001a movs r2, r3
80031ca: 2300 movs r3, #0
80031cc: 4d05 ldr r5, [pc, #20] ; (80031e4 <_lseek_r+0x24>)
80031ce: 602b str r3, [r5, #0]
80031d0: f7fd fb73 bl 80008ba <_lseek>
80031d4: 1c43 adds r3, r0, #1
80031d6: d103 bne.n 80031e0 <_lseek_r+0x20>
80031d8: 682b ldr r3, [r5, #0]
80031da: 2b00 cmp r3, #0
80031dc: d000 beq.n 80031e0 <_lseek_r+0x20>
80031de: 6023 str r3, [r4, #0]
80031e0: bd70 pop {r4, r5, r6, pc}
80031e2: 46c0 nop ; (mov r8, r8)
80031e4: 200000ec .word 0x200000ec
080031e8 <_read_r>:
80031e8: b570 push {r4, r5, r6, lr}
80031ea: 0004 movs r4, r0
80031ec: 0008 movs r0, r1
80031ee: 0011 movs r1, r2
80031f0: 001a movs r2, r3
80031f2: 2300 movs r3, #0
80031f4: 4d05 ldr r5, [pc, #20] ; (800320c <_read_r+0x24>)
80031f6: 602b str r3, [r5, #0]
80031f8: f7fd fb05 bl 8000806 <_read>
80031fc: 1c43 adds r3, r0, #1
80031fe: d103 bne.n 8003208 <_read_r+0x20>
8003200: 682b ldr r3, [r5, #0]
8003202: 2b00 cmp r3, #0
8003204: d000 beq.n 8003208 <_read_r+0x20>
8003206: 6023 str r3, [r4, #0]
8003208: bd70 pop {r4, r5, r6, pc}
800320a: 46c0 nop ; (mov r8, r8)
800320c: 200000ec .word 0x200000ec
08003210 <_init>:
8003210: b5f8 push {r3, r4, r5, r6, r7, lr}
8003212: 46c0 nop ; (mov r8, r8)
8003214: bcf8 pop {r3, r4, r5, r6, r7}
8003216: bc08 pop {r3}
8003218: 469e mov lr, r3
800321a: 4770 bx lr
0800321c <_fini>:
800321c: b5f8 push {r3, r4, r5, r6, r7, lr}
800321e: 46c0 nop ; (mov r8, r8)
8003220: bcf8 pop {r3, r4, r5, r6, r7}
8003222: bc08 pop {r3}
8003224: 469e mov lr, r3
8003226: 4770 bx lr
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