diff --git a/.cproject b/.cproject
index 76ffce4..c487de5 100644
--- a/.cproject
+++ b/.cproject
@@ -41,6 +41,7 @@
 								</option>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1878550455" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/my_software}&quot;"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32F0xx_HAL_Driver/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F0xx/Include"/>
@@ -73,6 +74,7 @@
 					<sourceEntries>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="my_software"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -94,25 +96,25 @@
 				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.459940613" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
 					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.459940613." name="/" resourcePath="">
 						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1407775258" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.228153008" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F030F4Px" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.828480546" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1426371198" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.411819854" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1226525547" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F030F4Px || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/STM32F0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F0xx/Include ||  ||  || USE_HAL_DRIVER | STM32F030x6 ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.228153008" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F030F4Px" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.828480546" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1426371198" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.411819854" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1226525547" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F030F4Px || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/STM32F0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F0xx/Include ||  ||  || USE_HAL_DRIVER | STM32F030x6 ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1370458443" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/Motor_Controller2}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.53671476" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<builder buildPath="${workspace_loc:/Motor_Controller2}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.53671476" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.499532382" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.747473442" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.747473442" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1072510588" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.663139893" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.60795894" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1422908823" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1820480621" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.60795894" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1422908823" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1820480621" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32F030x6"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1109162893" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1109162893" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32F0xx_HAL_Driver/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy"/>
@@ -122,11 +124,11 @@
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1091234256" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.572768492" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1529844604" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1524067260" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1529844604" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1524067260" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1541490766" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.985442494" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld}" valueType="string"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.985442494" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F030F4PX_FLASH.ld}" valueType="string"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.742975389" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -146,6 +148,7 @@
 					<sourceEntries>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="my_software"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -167,4 +170,12 @@
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
 	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/Motor_Controller2"/>
+		</configuration>
+		<configuration configurationName="Release">
+			<resource resourceType="PROJECT" workspacePath="/Motor_Controller2"/>
+		</configuration>
+	</storageModule>
 </cproject>
\ No newline at end of file
diff --git a/.settings/org.eclipse.cdt.core.prefs b/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000..c8ec5df
--- /dev/null
+++ b/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,6 @@
+doxygen/doxygen_new_line_after_brief=true
+doxygen/doxygen_use_brief_tag=false
+doxygen/doxygen_use_javadoc_tags=true
+doxygen/doxygen_use_pre_tag=false
+doxygen/doxygen_use_structural_commands=false
+eclipse.preferences.version=1
diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs
index df1a229..82b5ba3 100644
--- a/.settings/stm32cubeide.project.prefs
+++ b/.settings/stm32cubeide.project.prefs
@@ -1,3 +1,4 @@
 66BE74F758C12D739921AEA421D593D3=0
+8DF89ED150041C4CBC7CB9A9CAA90856=4CEDEAF73CDABB08FD3583A2D7D4A47A
 DC22A860405A8BF2F2C095E5B6529F12=4CEDEAF73CDABB08FD3583A2D7D4A47A
 eclipse.preferences.version=1
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 991a015..75f8ad4 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -22,7 +22,7 @@
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
-
+#include "my_code.h"
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -87,6 +87,7 @@ int main(void)
   MX_GPIO_Init();
   /* USER CODE BEGIN 2 */
 
+  my_code();
   /* USER CODE END 2 */
 
   /* Infinite loop */
diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d
new file mode 100644
index 0000000..bf63e3c
--- /dev/null
+++ b/Debug/Core/Src/main.d
@@ -0,0 +1,81 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \
+ /Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/my_software/my_code.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
+
+/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/my_software/my_code.h:
diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su
new file mode 100644
index 0000000..e94e55a
--- /dev/null
+++ b/Debug/Core/Src/main.su
@@ -0,0 +1,4 @@
+main.c:64:5:main	8	static
+main.c:108:6:SystemClock_Config	80	static
+main.c:146:13:MX_GPIO_Init	48	static
+main.c:195:6:Error_Handler	8	static,ignoring_inline_asm
diff --git a/Debug/Core/Src/stm32f0xx_hal_msp.d b/Debug/Core/Src/stm32f0xx_hal_msp.d
new file mode 100644
index 0000000..62a4406
--- /dev/null
+++ b/Debug/Core/Src/stm32f0xx_hal_msp.d
@@ -0,0 +1,78 @@
+Core/Src/stm32f0xx_hal_msp.o: ../Core/Src/stm32f0xx_hal_msp.c \
+ ../Core/Inc/main.h ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Core/Src/stm32f0xx_hal_msp.su b/Debug/Core/Src/stm32f0xx_hal_msp.su
new file mode 100644
index 0000000..994fa07
--- /dev/null
+++ b/Debug/Core/Src/stm32f0xx_hal_msp.su
@@ -0,0 +1 @@
+stm32f0xx_hal_msp.c:64:6:HAL_MspInit	16	static
diff --git a/Debug/Core/Src/stm32f0xx_it.d b/Debug/Core/Src/stm32f0xx_it.d
new file mode 100644
index 0000000..d841325
--- /dev/null
+++ b/Debug/Core/Src/stm32f0xx_it.d
@@ -0,0 +1,81 @@
+Core/Src/stm32f0xx_it.o: ../Core/Src/stm32f0xx_it.c ../Core/Inc/main.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \
+ ../Core/Inc/stm32f0xx_it.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
+
+../Core/Inc/stm32f0xx_it.h:
diff --git a/Debug/Core/Src/stm32f0xx_it.su b/Debug/Core/Src/stm32f0xx_it.su
new file mode 100644
index 0000000..105da51
--- /dev/null
+++ b/Debug/Core/Src/stm32f0xx_it.su
@@ -0,0 +1,5 @@
+stm32f0xx_it.c:70:6:NMI_Handler	8	static
+stm32f0xx_it.c:85:6:HardFault_Handler	8	static
+stm32f0xx_it.c:100:6:SVC_Handler	8	static
+stm32f0xx_it.c:113:6:PendSV_Handler	8	static
+stm32f0xx_it.c:126:6:SysTick_Handler	8	static
diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk
new file mode 100644
index 0000000..736535a
--- /dev/null
+++ b/Debug/Core/Src/subdir.mk
@@ -0,0 +1,35 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/Src/main.c \
+../Core/Src/stm32f0xx_hal_msp.c \
+../Core/Src/stm32f0xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32f0xx.c 
+
+OBJS += \
+./Core/Src/main.o \
+./Core/Src/stm32f0xx_hal_msp.o \
+./Core/Src/stm32f0xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32f0xx.o 
+
+C_DEPS += \
+./Core/Src/main.d \
+./Core/Src/stm32f0xx_hal_msp.d \
+./Core/Src/stm32f0xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32f0xx.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F030x6 -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/my_software" -I../Drivers/STM32F0xx_HAL_Driver/Inc -I../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d
new file mode 100644
index 0000000..8667c70
--- /dev/null
+++ b/Debug/Core/Src/syscalls.d
@@ -0,0 +1 @@
+Core/Src/syscalls.o: ../Core/Src/syscalls.c
diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su
new file mode 100644
index 0000000..2661431
--- /dev/null
+++ b/Debug/Core/Src/syscalls.su
@@ -0,0 +1,18 @@
+syscalls.c:45:6:initialise_monitor_handles	8	static
+syscalls.c:49:5:_getpid	8	static
+syscalls.c:54:5:_kill	16	static
+syscalls.c:60:6:_exit	16	static
+syscalls.c:66:27:_read	32	static
+syscalls.c:78:27:_write	32	static
+syscalls.c:89:5:_close	16	static
+syscalls.c:95:5:_fstat	16	static
+syscalls.c:101:5:_isatty	16	static
+syscalls.c:106:5:_lseek	24	static
+syscalls.c:111:5:_open	20	static
+syscalls.c:117:5:_wait	16	static
+syscalls.c:123:5:_unlink	16	static
+syscalls.c:129:5:_times	16	static
+syscalls.c:134:5:_stat	16	static
+syscalls.c:140:5:_link	16	static
+syscalls.c:146:5:_fork	8	static
+syscalls.c:152:5:_execve	24	static
diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d
new file mode 100644
index 0000000..74fecf9
--- /dev/null
+++ b/Debug/Core/Src/sysmem.d
@@ -0,0 +1 @@
+Core/Src/sysmem.o: ../Core/Src/sysmem.c
diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su
new file mode 100644
index 0000000..4474c68
--- /dev/null
+++ b/Debug/Core/Src/sysmem.su
@@ -0,0 +1 @@
+sysmem.c:54:7:_sbrk	32	static
diff --git a/Debug/Core/Src/system_stm32f0xx.d b/Debug/Core/Src/system_stm32f0xx.d
new file mode 100644
index 0000000..e20f9a2
--- /dev/null
+++ b/Debug/Core/Src/system_stm32f0xx.d
@@ -0,0 +1,76 @@
+Core/Src/system_stm32f0xx.o: ../Core/Src/system_stm32f0xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Core/Src/system_stm32f0xx.su b/Debug/Core/Src/system_stm32f0xx.su
new file mode 100644
index 0000000..2304684
--- /dev/null
+++ b/Debug/Core/Src/system_stm32f0xx.su
@@ -0,0 +1,2 @@
+system_stm32f0xx.c:128:6:SystemInit	8	static
+system_stm32f0xx.c:174:6:SystemCoreClockUpdate	24	static
diff --git a/Debug/Core/Startup/startup_stm32f030f4px.d b/Debug/Core/Startup/startup_stm32f030f4px.d
new file mode 100644
index 0000000..fbe3d71
--- /dev/null
+++ b/Debug/Core/Startup/startup_stm32f030f4px.d
@@ -0,0 +1,2 @@
+Core/Startup/startup_stm32f030f4px.o: \
+ ../Core/Startup/startup_stm32f030f4px.s
diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk
new file mode 100644
index 0000000..641b476
--- /dev/null
+++ b/Debug/Core/Startup/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+S_SRCS += \
+../Core/Startup/startup_stm32f030f4px.s 
+
+OBJS += \
+./Core/Startup/startup_stm32f030f4px.o 
+
+S_DEPS += \
+./Core/Startup/startup_stm32f030f4px.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
+	arm-none-eabi-gcc -mcpu=cortex-m0 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<"
+
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d
new file mode 100644
index 0000000..9b32d12
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su
new file mode 100644
index 0000000..7c31d5c
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su
@@ -0,0 +1,23 @@
+stm32f0xx_hal.c:141:19:HAL_Init	8	static
+stm32f0xx_hal.c:165:19:HAL_DeInit	8	static
+stm32f0xx_hal.c:188:13:HAL_MspInit	8	static
+stm32f0xx_hal.c:199:13:HAL_MspDeInit	8	static
+stm32f0xx_hal.c:222:26:HAL_InitTick	24	static
+stm32f0xx_hal.c:281:13:HAL_IncTick	8	static
+stm32f0xx_hal.c:292:17:HAL_GetTick	8	static
+stm32f0xx_hal.c:301:10:HAL_GetTickPrio	8	static
+stm32f0xx_hal.c:310:19:HAL_SetTickFreq	40	static
+stm32f0xx_hal.c:342:21:HAL_GetTickFreq	8	static
+stm32f0xx_hal.c:358:13:HAL_Delay	24	static
+stm32f0xx_hal.c:384:13:HAL_SuspendTick	8	static
+stm32f0xx_hal.c:401:13:HAL_ResumeTick	8	static
+stm32f0xx_hal.c:411:10:HAL_GetHalVersion	8	static
+stm32f0xx_hal.c:420:10:HAL_GetREVID	8	static
+stm32f0xx_hal.c:429:10:HAL_GetDEVID	8	static
+stm32f0xx_hal.c:438:10:HAL_GetUIDw0	8	static
+stm32f0xx_hal.c:447:10:HAL_GetUIDw1	8	static
+stm32f0xx_hal.c:456:10:HAL_GetUIDw2	8	static
+stm32f0xx_hal.c:465:6:HAL_DBGMCU_EnableDBGStopMode	8	static
+stm32f0xx_hal.c:474:6:HAL_DBGMCU_DisableDBGStopMode	8	static
+stm32f0xx_hal.c:483:6:HAL_DBGMCU_EnableDBGStandbyMode	8	static
+stm32f0xx_hal.c:492:6:HAL_DBGMCU_DisableDBGStandbyMode	8	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d
new file mode 100644
index 0000000..750c6ff
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su
new file mode 100644
index 0000000..9fe77bd
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su
@@ -0,0 +1,21 @@
+core_cm0.h:623:22:__NVIC_EnableIRQ	16	static
+core_cm0.h:659:22:__NVIC_DisableIRQ	16	static,ignoring_inline_asm
+core_cm0.h:678:26:__NVIC_GetPendingIRQ	16	static
+core_cm0.h:697:22:__NVIC_SetPendingIRQ	16	static
+core_cm0.h:712:22:__NVIC_ClearPendingIRQ	16	static
+core_cm0.h:730:22:__NVIC_SetPriority	24	static
+core_cm0.h:754:26:__NVIC_GetPriority	16	static
+core_cm0.h:856:34:__NVIC_SystemReset	8	static,ignoring_inline_asm
+core_cm0.h:920:26:SysTick_Config	16	static
+stm32f0xx_hal_cortex.c:136:6:HAL_NVIC_SetPriority	24	static
+stm32f0xx_hal_cortex.c:152:6:HAL_NVIC_EnableIRQ	16	static
+stm32f0xx_hal_cortex.c:168:6:HAL_NVIC_DisableIRQ	16	static
+stm32f0xx_hal_cortex.c:181:6:HAL_NVIC_SystemReset	8	static
+stm32f0xx_hal_cortex.c:194:10:HAL_SYSTICK_Config	16	static
+stm32f0xx_hal_cortex.c:226:10:HAL_NVIC_GetPriority	16	static
+stm32f0xx_hal_cortex.c:239:6:HAL_NVIC_SetPendingIRQ	16	static
+stm32f0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ	16	static
+stm32f0xx_hal_cortex.c:273:6:HAL_NVIC_ClearPendingIRQ	16	static
+stm32f0xx_hal_cortex.c:290:6:HAL_SYSTICK_CLKSourceConfig	16	static
+stm32f0xx_hal_cortex.c:308:6:HAL_SYSTICK_IRQHandler	8	static
+stm32f0xx_hal_cortex.c:317:13:HAL_SYSTICK_Callback	8	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d
new file mode 100644
index 0000000..6158fa4
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su
new file mode 100644
index 0000000..c1baa6b
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su
@@ -0,0 +1,14 @@
+stm32f0xx_hal_dma.c:138:19:HAL_DMA_Init	24	static
+stm32f0xx_hal_dma.c:200:19:HAL_DMA_DeInit	16	static
+stm32f0xx_hal_dma.c:282:19:HAL_DMA_Start	32	static
+stm32f0xx_hal_dma.c:329:19:HAL_DMA_Start_IT	32	static
+stm32f0xx_hal_dma.c:385:19:HAL_DMA_Abort	16	static
+stm32f0xx_hal_dma.c:423:19:HAL_DMA_Abort_IT	24	static
+stm32f0xx_hal_dma.c:469:19:HAL_DMA_PollForTransfer	32	static
+stm32f0xx_hal_dma.c:570:6:HAL_DMA_IRQHandler	24	static
+stm32f0xx_hal_dma.c:662:19:HAL_DMA_RegisterCallback	32	static
+stm32f0xx_hal_dma.c:713:19:HAL_DMA_UnRegisterCallback	24	static
+stm32f0xx_hal_dma.c:789:22:HAL_DMA_GetState	16	static
+stm32f0xx_hal_dma.c:800:10:HAL_DMA_GetError	16	static
+stm32f0xx_hal_dma.c:826:13:DMA_SetConfig	24	static
+stm32f0xx_hal_dma.c:860:13:DMA_CalcBaseAndBitshift	16	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d
new file mode 100644
index 0000000..76b58f3
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su
new file mode 100644
index 0000000..06dba86
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su
@@ -0,0 +1,9 @@
+stm32f0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine	32	static
+stm32f0xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine	32	static
+stm32f0xx_hal_exti.c:317:19:HAL_EXTI_ClearConfigLine	32	static
+stm32f0xx_hal_exti.c:370:19:HAL_EXTI_RegisterCallback	32	static
+stm32f0xx_hal_exti.c:395:19:HAL_EXTI_GetHandle	16	static
+stm32f0xx_hal_exti.c:435:6:HAL_EXTI_IRQHandler	24	static
+stm32f0xx_hal_exti.c:467:10:HAL_EXTI_GetPending	32	static
+stm32f0xx_hal_exti.c:496:6:HAL_EXTI_ClearPending	24	static
+stm32f0xx_hal_exti.c:517:6:HAL_EXTI_GenerateSWI	24	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d
new file mode 100644
index 0000000..2eb18d4
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su
new file mode 100644
index 0000000..5fb5979
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su
@@ -0,0 +1,14 @@
+stm32f0xx_hal_flash.c:167:19:HAL_FLASH_Program	48	static
+stm32f0xx_hal_flash.c:239:19:HAL_FLASH_Program_IT	32	static
+stm32f0xx_hal_flash.c:285:6:HAL_FLASH_IRQHandler	24	static
+stm32f0xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback	16	static
+stm32f0xx_hal_flash.c:446:13:HAL_FLASH_OperationErrorCallback	16	static
+stm32f0xx_hal_flash.c:479:19:HAL_FLASH_Unlock	16	static
+stm32f0xx_hal_flash.c:503:19:HAL_FLASH_Lock	8	static
+stm32f0xx_hal_flash.c:515:19:HAL_FLASH_OB_Unlock	8	static
+stm32f0xx_hal_flash.c:535:19:HAL_FLASH_OB_Lock	8	static
+stm32f0xx_hal_flash.c:548:19:HAL_FLASH_OB_Launch	8	static
+stm32f0xx_hal_flash.c:580:10:HAL_FLASH_GetError	8	static
+stm32f0xx_hal_flash.c:603:13:FLASH_Program_HalfWord	16	static
+stm32f0xx_hal_flash.c:620:19:FLASH_WaitForLastOperation	24	static
+stm32f0xx_hal_flash.c:663:13:FLASH_SetErrorCode	16	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d
new file mode 100644
index 0000000..f2b6d4a
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su
new file mode 100644
index 0000000..fcf9366
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su
@@ -0,0 +1,16 @@
+stm32f0xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase	32	static
+stm32f0xx_hal_flash_ex.c:240:19:HAL_FLASHEx_Erase_IT	24	static
+stm32f0xx_hal_flash_ex.c:313:19:HAL_FLASHEx_OBErase	24	static
+stm32f0xx_hal_flash_ex.c:362:19:HAL_FLASHEx_OBProgram	32	static
+stm32f0xx_hal_flash_ex.c:443:6:HAL_FLASHEx_OBGetConfig	16	static
+stm32f0xx_hal_flash_ex.c:465:10:HAL_FLASHEx_OBGetUserData	24	static
+stm32f0xx_hal_flash_ex.c:500:13:FLASH_MassErase	8	static
+stm32f0xx_hal_flash_ex.c:521:26:FLASH_OB_EnableWRP	40	static
+stm32f0xx_hal_flash_ex.c:637:26:FLASH_OB_DisableWRP	40	static
+stm32f0xx_hal_flash_ex.c:751:26:FLASH_OB_RDP_LevelConfig	32	static
+stm32f0xx_hal_flash_ex.c:802:26:FLASH_OB_UserConfig	32	static
+stm32f0xx_hal_flash_ex.c:857:26:FLASH_OB_ProgramData	32	static
+stm32f0xx_hal_flash_ex.c:890:17:FLASH_OB_GetWRP	8	static
+stm32f0xx_hal_flash_ex.c:904:17:FLASH_OB_GetRDP	16	static
+stm32f0xx_hal_flash_ex.c:931:16:FLASH_OB_GetUser	8	static
+stm32f0xx_hal_flash_ex.c:960:6:FLASH_PageErase	16	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d
new file mode 100644
index 0000000..0cd7cbf
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su
new file mode 100644
index 0000000..d548c01
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su
@@ -0,0 +1,8 @@
+stm32f0xx_hal_gpio.c:169:6:HAL_GPIO_Init	32	static
+stm32f0xx_hal_gpio.c:299:6:HAL_GPIO_DeInit	32	static
+stm32f0xx_hal_gpio.c:382:15:HAL_GPIO_ReadPin	24	static
+stm32f0xx_hal_gpio.c:415:6:HAL_GPIO_WritePin	16	static
+stm32f0xx_hal_gpio.c:437:6:HAL_GPIO_TogglePin	24	static
+stm32f0xx_hal_gpio.c:462:19:HAL_GPIO_LockPin	24	static
+stm32f0xx_hal_gpio.c:497:6:HAL_GPIO_EXTI_IRQHandler	16	static
+stm32f0xx_hal_gpio.c:512:13:HAL_GPIO_EXTI_Callback	16	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d
new file mode 100644
index 0000000..57698d8
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su
new file mode 100644
index 0000000..c7eea82
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su
@@ -0,0 +1,79 @@
+stm32f0xx_hal_i2c.c:522:19:HAL_I2C_Init	16	static
+stm32f0xx_hal_i2c.c:632:19:HAL_I2C_DeInit	16	static
+stm32f0xx_hal_i2c.c:678:13:HAL_I2C_MspInit	16	static
+stm32f0xx_hal_i2c.c:694:13:HAL_I2C_MspDeInit	16	static
+stm32f0xx_hal_i2c.c:1115:19:HAL_I2C_Master_Transmit	48	static
+stm32f0xx_hal_i2c.c:1234:19:HAL_I2C_Master_Receive	48	static
+stm32f0xx_hal_i2c.c:1352:19:HAL_I2C_Slave_Transmit	40	static
+stm32f0xx_hal_i2c.c:1490:19:HAL_I2C_Slave_Receive	40	static
+stm32f0xx_hal_i2c.c:1617:19:HAL_I2C_Master_Transmit_IT	48	static
+stm32f0xx_hal_i2c.c:1688:19:HAL_I2C_Master_Receive_IT	48	static
+stm32f0xx_hal_i2c.c:1757:19:HAL_I2C_Slave_Transmit_IT	24	static
+stm32f0xx_hal_i2c.c:1807:19:HAL_I2C_Slave_Receive_IT	24	static
+stm32f0xx_hal_i2c.c:1859:19:HAL_I2C_Master_Transmit_DMA	48	static
+stm32f0xx_hal_i2c.c:2006:19:HAL_I2C_Master_Receive_DMA	48	static
+stm32f0xx_hal_i2c.c:2151:19:HAL_I2C_Slave_Transmit_DMA	40	static
+stm32f0xx_hal_i2c.c:2255:19:HAL_I2C_Slave_Receive_DMA	40	static
+stm32f0xx_hal_i2c.c:2363:19:HAL_I2C_Mem_Write	48	static
+stm32f0xx_hal_i2c.c:2500:19:HAL_I2C_Mem_Read	48	static
+stm32f0xx_hal_i2c.c:2637:19:HAL_I2C_Mem_Write_IT	48	static
+stm32f0xx_hal_i2c.c:2731:19:HAL_I2C_Mem_Read_IT	48	static
+stm32f0xx_hal_i2c.c:2823:19:HAL_I2C_Mem_Write_DMA	56	static
+stm32f0xx_hal_i2c.c:2970:19:HAL_I2C_Mem_Read_DMA	56	static
+stm32f0xx_hal_i2c.c:3113:19:HAL_I2C_IsDeviceReady	48	static
+stm32f0xx_hal_i2c.c:3255:19:HAL_I2C_Master_Seq_Transmit_IT	48	static
+stm32f0xx_hal_i2c.c:3342:19:HAL_I2C_Master_Seq_Transmit_DMA	56	static
+stm32f0xx_hal_i2c.c:3510:19:HAL_I2C_Master_Seq_Receive_IT	48	static
+stm32f0xx_hal_i2c.c:3597:19:HAL_I2C_Master_Seq_Receive_DMA	56	static
+stm32f0xx_hal_i2c.c:3763:19:HAL_I2C_Slave_Seq_Transmit_IT	24	static
+stm32f0xx_hal_i2c.c:3859:19:HAL_I2C_Slave_Seq_Transmit_DMA	40	static
+stm32f0xx_hal_i2c.c:4040:19:HAL_I2C_Slave_Seq_Receive_IT	24	static
+stm32f0xx_hal_i2c.c:4136:19:HAL_I2C_Slave_Seq_Receive_DMA	40	static
+stm32f0xx_hal_i2c.c:4313:19:HAL_I2C_EnableListen_IT	16	static
+stm32f0xx_hal_i2c.c:4337:19:HAL_I2C_DisableListen_IT	24	static
+stm32f0xx_hal_i2c.c:4370:19:HAL_I2C_Master_Abort_IT	24	static
+stm32f0xx_hal_i2c.c:4432:6:HAL_I2C_EV_IRQHandler	24	static
+stm32f0xx_hal_i2c.c:4451:6:HAL_I2C_ER_IRQHandler	32	static
+stm32f0xx_hal_i2c.c:4503:13:HAL_I2C_MasterTxCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4519:13:HAL_I2C_MasterRxCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4534:13:HAL_I2C_SlaveTxCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4550:13:HAL_I2C_SlaveRxCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4568:13:HAL_I2C_AddrCallback	16	static
+stm32f0xx_hal_i2c.c:4586:13:HAL_I2C_ListenCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4602:13:HAL_I2C_MemTxCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4618:13:HAL_I2C_MemRxCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4634:13:HAL_I2C_ErrorCallback	16	static
+stm32f0xx_hal_i2c.c:4650:13:HAL_I2C_AbortCpltCallback	16	static
+stm32f0xx_hal_i2c.c:4685:22:HAL_I2C_GetState	16	static
+stm32f0xx_hal_i2c.c:4697:21:HAL_I2C_GetMode	16	static
+stm32f0xx_hal_i2c.c:4708:10:HAL_I2C_GetError	16	static
+stm32f0xx_hal_i2c.c:4733:26:I2C_Master_ISR_IT	48	static
+stm32f0xx_hal_i2c.c:4879:26:I2C_Slave_ISR_IT	32	static
+stm32f0xx_hal_i2c.c:5020:26:I2C_Master_ISR_DMA	48	static
+stm32f0xx_hal_i2c.c:5160:26:I2C_Slave_ISR_DMA	40	static
+stm32f0xx_hal_i2c.c:5305:26:I2C_RequestMemoryWrite	40	static
+stm32f0xx_hal_i2c.c:5360:26:I2C_RequestMemoryRead	40	static
+stm32f0xx_hal_i2c.c:5409:13:I2C_ITAddrCplt	32	static
+stm32f0xx_hal_i2c.c:5504:13:I2C_ITMasterSeqCplt	16	static
+stm32f0xx_hal_i2c.c:5557:13:I2C_ITSlaveSeqCplt	24	static
+stm32f0xx_hal_i2c.c:5631:13:I2C_ITMasterCplt	32	static
+stm32f0xx_hal_i2c.c:5774:13:I2C_ITSlaveCplt	32	static
+stm32f0xx_hal_i2c.c:5933:13:I2C_ITListenCplt	16	static
+stm32f0xx_hal_i2c.c:5984:13:I2C_ITError	24	static
+stm32f0xx_hal_i2c.c:6096:13:I2C_TreatErrorCallback	16	static
+stm32f0xx_hal_i2c.c:6134:13:I2C_Flush_TXDR	16	static
+stm32f0xx_hal_i2c.c:6155:13:I2C_DMAMasterTransmitCplt	24	static
+stm32f0xx_hal_i2c.c:6205:13:I2C_DMASlaveTransmitCplt	24	static
+stm32f0xx_hal_i2c.c:6233:13:I2C_DMAMasterReceiveCplt	24	static
+stm32f0xx_hal_i2c.c:6283:13:I2C_DMASlaveReceiveCplt	24	static
+stm32f0xx_hal_i2c.c:6311:13:I2C_DMAError	24	static
+stm32f0xx_hal_i2c.c:6329:13:I2C_DMAAbort	24	static
+stm32f0xx_hal_i2c.c:6357:26:I2C_WaitOnFlagUntilTimeout	24	static
+stm32f0xx_hal_i2c.c:6388:26:I2C_WaitOnTXISFlagUntilTimeout	24	static
+stm32f0xx_hal_i2c.c:6426:26:I2C_WaitOnSTOPFlagUntilTimeout	24	static
+stm32f0xx_hal_i2c.c:6461:26:I2C_WaitOnRXNEFlagUntilTimeout	24	static
+stm32f0xx_hal_i2c.c:6525:26:I2C_IsAcknowledgeFailed	24	static
+stm32f0xx_hal_i2c.c:6599:13:I2C_TransferConfig	32	static
+stm32f0xx_hal_i2c.c:6624:13:I2C_Enable_IRQ	24	static
+stm32f0xx_hal_i2c.c:6695:13:I2C_Disable_IRQ	24	static
+stm32f0xx_hal_i2c.c:6758:13:I2C_ConvertOtherXferOptions	16	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d
new file mode 100644
index 0000000..9737ab8
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su
new file mode 100644
index 0000000..8a90ef8
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su
@@ -0,0 +1,4 @@
+stm32f0xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter	16	static
+stm32f0xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter	24	static
+stm32f0xx_hal_i2c_ex.c:313:6:HAL_I2CEx_EnableFastModePlus	24	static
+stm32f0xx_hal_i2c_ex.c:338:6:HAL_I2CEx_DisableFastModePlus	24	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d
new file mode 100644
index 0000000..c8e0cad
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su
new file mode 100644
index 0000000..6bc0263
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su
@@ -0,0 +1,12 @@
+stm32f0xx_hal_pwr.c:75:6:HAL_PWR_DeInit	8	static
+stm32f0xx_hal_pwr.c:88:6:HAL_PWR_EnableBkUpAccess	8	static
+stm32f0xx_hal_pwr.c:100:6:HAL_PWR_DisableBkUpAccess	8	static
+stm32f0xx_hal_pwr.c:231:6:HAL_PWR_EnableWakeUpPin	16	static
+stm32f0xx_hal_pwr.c:246:6:HAL_PWR_DisableWakeUpPin	16	static
+stm32f0xx_hal_pwr.c:269:6:HAL_PWR_EnterSLEEPMode	16	static,ignoring_inline_asm
+stm32f0xx_hal_pwr.c:312:6:HAL_PWR_EnterSTOPMode	24	static,ignoring_inline_asm
+stm32f0xx_hal_pwr.c:367:6:HAL_PWR_EnterSTANDBYMode	8	static,ignoring_inline_asm
+stm32f0xx_hal_pwr.c:391:6:HAL_PWR_EnableSleepOnExit	8	static
+stm32f0xx_hal_pwr.c:404:6:HAL_PWR_DisableSleepOnExit	8	static
+stm32f0xx_hal_pwr.c:418:6:HAL_PWR_EnableSEVOnPend	8	static
+stm32f0xx_hal_pwr.c:431:6:HAL_PWR_DisableSEVOnPend	8	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d
new file mode 100644
index 0000000..1f7f41d
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d
new file mode 100644
index 0000000..a7478f5
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su
new file mode 100644
index 0000000..b42db45
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su
@@ -0,0 +1,13 @@
+stm32f0xx_hal_rcc.c:210:19:HAL_RCC_DeInit	16	static
+stm32f0xx_hal_rcc.c:300:19:HAL_RCC_OscConfig	40	static
+stm32f0xx_hal_rcc.c:779:19:HAL_RCC_ClockConfig	24	static
+stm32f0xx_hal_rcc.c:1018:6:HAL_RCC_MCOConfig	48	static
+stm32f0xx_hal_rcc.c:1052:6:HAL_RCC_EnableCSS	8	static
+stm32f0xx_hal_rcc.c:1061:6:HAL_RCC_DisableCSS	8	static
+stm32f0xx_hal_rcc.c:1097:10:HAL_RCC_GetSysClockFreq	72	static
+stm32f0xx_hal_rcc.c:1172:10:HAL_RCC_GetHCLKFreq	8	static
+stm32f0xx_hal_rcc.c:1183:10:HAL_RCC_GetPCLK1Freq	8	static
+stm32f0xx_hal_rcc.c:1196:6:HAL_RCC_GetOscConfig	16	static
+stm32f0xx_hal_rcc.c:1298:6:HAL_RCC_GetClockConfig	16	static
+stm32f0xx_hal_rcc.c:1324:6:HAL_RCC_NMI_IRQHandler	8	static
+stm32f0xx_hal_rcc.c:1341:13:HAL_RCC_CSSCallback	8	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d
new file mode 100644
index 0000000..b2234db
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su
new file mode 100644
index 0000000..e199abe
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su
@@ -0,0 +1,3 @@
+stm32f0xx_hal_rcc_ex.c:104:19:HAL_RCCEx_PeriphCLKConfig	32	static
+stm32f0xx_hal_rcc_ex.c:270:6:HAL_RCCEx_GetPeriphCLKConfig	16	static
+stm32f0xx_hal_rcc_ex.c:370:10:HAL_RCCEx_GetPeriphCLKFreq	24	static
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d
new file mode 100644
index 0000000..2949cd6
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d
new file mode 100644
index 0000000..2ccb2ad
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d
@@ -0,0 +1,77 @@
+Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o: \
+ ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.su b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..522ef73
--- /dev/null
+++ b/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,62 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c \
+../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c 
+
+OBJS += \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o 
+
+C_DEPS += \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d \
+./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32F0xx_HAL_Driver/Src/%.o: ../Drivers/STM32F0xx_HAL_Driver/Src/%.c Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F030x6 -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/my_software" -I../Drivers/STM32F0xx_HAL_Driver/Inc -I../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Debug/Motor_Controller2.bin b/Debug/Motor_Controller2.bin
new file mode 100755
index 0000000..23bf88a
Binary files /dev/null and b/Debug/Motor_Controller2.bin differ
diff --git a/Debug/Motor_Controller2.list b/Debug/Motor_Controller2.list
new file mode 100644
index 0000000..ef17b77
--- /dev/null
+++ b/Debug/Motor_Controller2.list
@@ -0,0 +1,4025 @@
+
+Motor_Controller2.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .isr_vector   000000c0  08000000  08000000  00010000  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  1 .text         000015b0  080000c0  080000c0  000100c0  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .rodata       00000040  08001670  08001670  00011670  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .ARM.extab    00000000  080016b0  080016b0  0002000c  2**0
+                  CONTENTS
+  4 .ARM          00000000  080016b0  080016b0  0002000c  2**0
+                  CONTENTS
+  5 .preinit_array 00000000  080016b0  080016b0  0002000c  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  6 .init_array   00000004  080016b0  080016b0  000116b0  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  7 .fini_array   00000004  080016b4  080016b4  000116b4  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  8 .data         0000000c  20000000  080016b8  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  9 .bss          00000028  2000000c  080016c4  0002000c  2**2
+                  ALLOC
+ 10 ._user_heap_stack 00000604  20000034  080016c4  00020034  2**0
+                  ALLOC
+ 11 .ARM.attributes 00000028  00000000  00000000  0002000c  2**0
+                  CONTENTS, READONLY
+ 12 .debug_info   00002f23  00000000  00000000  00020034  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 00000fb6  00000000  00000000  00022f57  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00000390  00000000  00000000  00023f10  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_ranges 000002f8  00000000  00000000  000242a0  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_macro  0000e10b  00000000  00000000  00024598  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_line   0000505a  00000000  00000000  000326a3  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_str    000537f2  00000000  00000000  000376fd  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 19 .comment      00000053  00000000  00000000  0008aeef  2**0
+                  CONTENTS, READONLY
+ 20 .debug_frame  00000aa0  00000000  00000000  0008af44  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080000c0 <__do_global_dtors_aux>:
+ 80000c0:	b510      	push	{r4, lr}
+ 80000c2:	4c06      	ldr	r4, [pc, #24]	; (80000dc <__do_global_dtors_aux+0x1c>)
+ 80000c4:	7823      	ldrb	r3, [r4, #0]
+ 80000c6:	2b00      	cmp	r3, #0
+ 80000c8:	d107      	bne.n	80000da <__do_global_dtors_aux+0x1a>
+ 80000ca:	4b05      	ldr	r3, [pc, #20]	; (80000e0 <__do_global_dtors_aux+0x20>)
+ 80000cc:	2b00      	cmp	r3, #0
+ 80000ce:	d002      	beq.n	80000d6 <__do_global_dtors_aux+0x16>
+ 80000d0:	4804      	ldr	r0, [pc, #16]	; (80000e4 <__do_global_dtors_aux+0x24>)
+ 80000d2:	e000      	b.n	80000d6 <__do_global_dtors_aux+0x16>
+ 80000d4:	bf00      	nop
+ 80000d6:	2301      	movs	r3, #1
+ 80000d8:	7023      	strb	r3, [r4, #0]
+ 80000da:	bd10      	pop	{r4, pc}
+ 80000dc:	2000000c 	.word	0x2000000c
+ 80000e0:	00000000 	.word	0x00000000
+ 80000e4:	08001658 	.word	0x08001658
+
+080000e8 <frame_dummy>:
+ 80000e8:	4b04      	ldr	r3, [pc, #16]	; (80000fc <frame_dummy+0x14>)
+ 80000ea:	b510      	push	{r4, lr}
+ 80000ec:	2b00      	cmp	r3, #0
+ 80000ee:	d003      	beq.n	80000f8 <frame_dummy+0x10>
+ 80000f0:	4903      	ldr	r1, [pc, #12]	; (8000100 <frame_dummy+0x18>)
+ 80000f2:	4804      	ldr	r0, [pc, #16]	; (8000104 <frame_dummy+0x1c>)
+ 80000f4:	e000      	b.n	80000f8 <frame_dummy+0x10>
+ 80000f6:	bf00      	nop
+ 80000f8:	bd10      	pop	{r4, pc}
+ 80000fa:	46c0      	nop			; (mov r8, r8)
+ 80000fc:	00000000 	.word	0x00000000
+ 8000100:	20000010 	.word	0x20000010
+ 8000104:	08001658 	.word	0x08001658
+
+08000108 <__udivsi3>:
+ 8000108:	2200      	movs	r2, #0
+ 800010a:	0843      	lsrs	r3, r0, #1
+ 800010c:	428b      	cmp	r3, r1
+ 800010e:	d374      	bcc.n	80001fa <__udivsi3+0xf2>
+ 8000110:	0903      	lsrs	r3, r0, #4
+ 8000112:	428b      	cmp	r3, r1
+ 8000114:	d35f      	bcc.n	80001d6 <__udivsi3+0xce>
+ 8000116:	0a03      	lsrs	r3, r0, #8
+ 8000118:	428b      	cmp	r3, r1
+ 800011a:	d344      	bcc.n	80001a6 <__udivsi3+0x9e>
+ 800011c:	0b03      	lsrs	r3, r0, #12
+ 800011e:	428b      	cmp	r3, r1
+ 8000120:	d328      	bcc.n	8000174 <__udivsi3+0x6c>
+ 8000122:	0c03      	lsrs	r3, r0, #16
+ 8000124:	428b      	cmp	r3, r1
+ 8000126:	d30d      	bcc.n	8000144 <__udivsi3+0x3c>
+ 8000128:	22ff      	movs	r2, #255	; 0xff
+ 800012a:	0209      	lsls	r1, r1, #8
+ 800012c:	ba12      	rev	r2, r2
+ 800012e:	0c03      	lsrs	r3, r0, #16
+ 8000130:	428b      	cmp	r3, r1
+ 8000132:	d302      	bcc.n	800013a <__udivsi3+0x32>
+ 8000134:	1212      	asrs	r2, r2, #8
+ 8000136:	0209      	lsls	r1, r1, #8
+ 8000138:	d065      	beq.n	8000206 <__udivsi3+0xfe>
+ 800013a:	0b03      	lsrs	r3, r0, #12
+ 800013c:	428b      	cmp	r3, r1
+ 800013e:	d319      	bcc.n	8000174 <__udivsi3+0x6c>
+ 8000140:	e000      	b.n	8000144 <__udivsi3+0x3c>
+ 8000142:	0a09      	lsrs	r1, r1, #8
+ 8000144:	0bc3      	lsrs	r3, r0, #15
+ 8000146:	428b      	cmp	r3, r1
+ 8000148:	d301      	bcc.n	800014e <__udivsi3+0x46>
+ 800014a:	03cb      	lsls	r3, r1, #15
+ 800014c:	1ac0      	subs	r0, r0, r3
+ 800014e:	4152      	adcs	r2, r2
+ 8000150:	0b83      	lsrs	r3, r0, #14
+ 8000152:	428b      	cmp	r3, r1
+ 8000154:	d301      	bcc.n	800015a <__udivsi3+0x52>
+ 8000156:	038b      	lsls	r3, r1, #14
+ 8000158:	1ac0      	subs	r0, r0, r3
+ 800015a:	4152      	adcs	r2, r2
+ 800015c:	0b43      	lsrs	r3, r0, #13
+ 800015e:	428b      	cmp	r3, r1
+ 8000160:	d301      	bcc.n	8000166 <__udivsi3+0x5e>
+ 8000162:	034b      	lsls	r3, r1, #13
+ 8000164:	1ac0      	subs	r0, r0, r3
+ 8000166:	4152      	adcs	r2, r2
+ 8000168:	0b03      	lsrs	r3, r0, #12
+ 800016a:	428b      	cmp	r3, r1
+ 800016c:	d301      	bcc.n	8000172 <__udivsi3+0x6a>
+ 800016e:	030b      	lsls	r3, r1, #12
+ 8000170:	1ac0      	subs	r0, r0, r3
+ 8000172:	4152      	adcs	r2, r2
+ 8000174:	0ac3      	lsrs	r3, r0, #11
+ 8000176:	428b      	cmp	r3, r1
+ 8000178:	d301      	bcc.n	800017e <__udivsi3+0x76>
+ 800017a:	02cb      	lsls	r3, r1, #11
+ 800017c:	1ac0      	subs	r0, r0, r3
+ 800017e:	4152      	adcs	r2, r2
+ 8000180:	0a83      	lsrs	r3, r0, #10
+ 8000182:	428b      	cmp	r3, r1
+ 8000184:	d301      	bcc.n	800018a <__udivsi3+0x82>
+ 8000186:	028b      	lsls	r3, r1, #10
+ 8000188:	1ac0      	subs	r0, r0, r3
+ 800018a:	4152      	adcs	r2, r2
+ 800018c:	0a43      	lsrs	r3, r0, #9
+ 800018e:	428b      	cmp	r3, r1
+ 8000190:	d301      	bcc.n	8000196 <__udivsi3+0x8e>
+ 8000192:	024b      	lsls	r3, r1, #9
+ 8000194:	1ac0      	subs	r0, r0, r3
+ 8000196:	4152      	adcs	r2, r2
+ 8000198:	0a03      	lsrs	r3, r0, #8
+ 800019a:	428b      	cmp	r3, r1
+ 800019c:	d301      	bcc.n	80001a2 <__udivsi3+0x9a>
+ 800019e:	020b      	lsls	r3, r1, #8
+ 80001a0:	1ac0      	subs	r0, r0, r3
+ 80001a2:	4152      	adcs	r2, r2
+ 80001a4:	d2cd      	bcs.n	8000142 <__udivsi3+0x3a>
+ 80001a6:	09c3      	lsrs	r3, r0, #7
+ 80001a8:	428b      	cmp	r3, r1
+ 80001aa:	d301      	bcc.n	80001b0 <__udivsi3+0xa8>
+ 80001ac:	01cb      	lsls	r3, r1, #7
+ 80001ae:	1ac0      	subs	r0, r0, r3
+ 80001b0:	4152      	adcs	r2, r2
+ 80001b2:	0983      	lsrs	r3, r0, #6
+ 80001b4:	428b      	cmp	r3, r1
+ 80001b6:	d301      	bcc.n	80001bc <__udivsi3+0xb4>
+ 80001b8:	018b      	lsls	r3, r1, #6
+ 80001ba:	1ac0      	subs	r0, r0, r3
+ 80001bc:	4152      	adcs	r2, r2
+ 80001be:	0943      	lsrs	r3, r0, #5
+ 80001c0:	428b      	cmp	r3, r1
+ 80001c2:	d301      	bcc.n	80001c8 <__udivsi3+0xc0>
+ 80001c4:	014b      	lsls	r3, r1, #5
+ 80001c6:	1ac0      	subs	r0, r0, r3
+ 80001c8:	4152      	adcs	r2, r2
+ 80001ca:	0903      	lsrs	r3, r0, #4
+ 80001cc:	428b      	cmp	r3, r1
+ 80001ce:	d301      	bcc.n	80001d4 <__udivsi3+0xcc>
+ 80001d0:	010b      	lsls	r3, r1, #4
+ 80001d2:	1ac0      	subs	r0, r0, r3
+ 80001d4:	4152      	adcs	r2, r2
+ 80001d6:	08c3      	lsrs	r3, r0, #3
+ 80001d8:	428b      	cmp	r3, r1
+ 80001da:	d301      	bcc.n	80001e0 <__udivsi3+0xd8>
+ 80001dc:	00cb      	lsls	r3, r1, #3
+ 80001de:	1ac0      	subs	r0, r0, r3
+ 80001e0:	4152      	adcs	r2, r2
+ 80001e2:	0883      	lsrs	r3, r0, #2
+ 80001e4:	428b      	cmp	r3, r1
+ 80001e6:	d301      	bcc.n	80001ec <__udivsi3+0xe4>
+ 80001e8:	008b      	lsls	r3, r1, #2
+ 80001ea:	1ac0      	subs	r0, r0, r3
+ 80001ec:	4152      	adcs	r2, r2
+ 80001ee:	0843      	lsrs	r3, r0, #1
+ 80001f0:	428b      	cmp	r3, r1
+ 80001f2:	d301      	bcc.n	80001f8 <__udivsi3+0xf0>
+ 80001f4:	004b      	lsls	r3, r1, #1
+ 80001f6:	1ac0      	subs	r0, r0, r3
+ 80001f8:	4152      	adcs	r2, r2
+ 80001fa:	1a41      	subs	r1, r0, r1
+ 80001fc:	d200      	bcs.n	8000200 <__udivsi3+0xf8>
+ 80001fe:	4601      	mov	r1, r0
+ 8000200:	4152      	adcs	r2, r2
+ 8000202:	4610      	mov	r0, r2
+ 8000204:	4770      	bx	lr
+ 8000206:	e7ff      	b.n	8000208 <__udivsi3+0x100>
+ 8000208:	b501      	push	{r0, lr}
+ 800020a:	2000      	movs	r0, #0
+ 800020c:	f000 f806 	bl	800021c <__aeabi_idiv0>
+ 8000210:	bd02      	pop	{r1, pc}
+ 8000212:	46c0      	nop			; (mov r8, r8)
+
+08000214 <__aeabi_uidivmod>:
+ 8000214:	2900      	cmp	r1, #0
+ 8000216:	d0f7      	beq.n	8000208 <__udivsi3+0x100>
+ 8000218:	e776      	b.n	8000108 <__udivsi3>
+ 800021a:	4770      	bx	lr
+
+0800021c <__aeabi_idiv0>:
+ 800021c:	4770      	bx	lr
+ 800021e:	46c0      	nop			; (mov r8, r8)
+
+08000220 <main>:
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+ 8000220:	b580      	push	{r7, lr}
+ 8000222:	af00      	add	r7, sp, #0
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+ 8000224:	f000 f93e 	bl	80004a4 <HAL_Init>
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+ 8000228:	f000 f805 	bl	8000236 <SystemClock_Config>
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+ 800022c:	f000 f84e 	bl	80002cc <MX_GPIO_Init>
+  /* USER CODE BEGIN 2 */
+
+  my_code();
+ 8000230:	f001 f9d2 	bl	80015d8 <my_code>
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+ 8000234:	e7fe      	b.n	8000234 <main+0x14>
+
+08000236 <SystemClock_Config>:
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+ 8000236:	b590      	push	{r4, r7, lr}
+ 8000238:	b091      	sub	sp, #68	; 0x44
+ 800023a:	af00      	add	r7, sp, #0
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 800023c:	2410      	movs	r4, #16
+ 800023e:	193b      	adds	r3, r7, r4
+ 8000240:	0018      	movs	r0, r3
+ 8000242:	2330      	movs	r3, #48	; 0x30
+ 8000244:	001a      	movs	r2, r3
+ 8000246:	2100      	movs	r1, #0
+ 8000248:	f001 f9fe 	bl	8001648 <memset>
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 800024c:	003b      	movs	r3, r7
+ 800024e:	0018      	movs	r0, r3
+ 8000250:	2310      	movs	r3, #16
+ 8000252:	001a      	movs	r2, r3
+ 8000254:	2100      	movs	r1, #0
+ 8000256:	f001 f9f7 	bl	8001648 <memset>
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 800025a:	0021      	movs	r1, r4
+ 800025c:	187b      	adds	r3, r7, r1
+ 800025e:	2202      	movs	r2, #2
+ 8000260:	601a      	str	r2, [r3, #0]
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ 8000262:	187b      	adds	r3, r7, r1
+ 8000264:	2201      	movs	r2, #1
+ 8000266:	60da      	str	r2, [r3, #12]
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ 8000268:	187b      	adds	r3, r7, r1
+ 800026a:	2210      	movs	r2, #16
+ 800026c:	611a      	str	r2, [r3, #16]
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 800026e:	187b      	adds	r3, r7, r1
+ 8000270:	2202      	movs	r2, #2
+ 8000272:	621a      	str	r2, [r3, #32]
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ 8000274:	187b      	adds	r3, r7, r1
+ 8000276:	2200      	movs	r2, #0
+ 8000278:	625a      	str	r2, [r3, #36]	; 0x24
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ 800027a:	187b      	adds	r3, r7, r1
+ 800027c:	22a0      	movs	r2, #160	; 0xa0
+ 800027e:	0392      	lsls	r2, r2, #14
+ 8000280:	629a      	str	r2, [r3, #40]	; 0x28
+  RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ 8000282:	187b      	adds	r3, r7, r1
+ 8000284:	2200      	movs	r2, #0
+ 8000286:	62da      	str	r2, [r3, #44]	; 0x2c
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 8000288:	187b      	adds	r3, r7, r1
+ 800028a:	0018      	movs	r0, r3
+ 800028c:	f000 fbb0 	bl	80009f0 <HAL_RCC_OscConfig>
+ 8000290:	1e03      	subs	r3, r0, #0
+ 8000292:	d001      	beq.n	8000298 <SystemClock_Config+0x62>
+  {
+    Error_Handler();
+ 8000294:	f000 f896 	bl	80003c4 <Error_Handler>
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 8000298:	003b      	movs	r3, r7
+ 800029a:	2207      	movs	r2, #7
+ 800029c:	601a      	str	r2, [r3, #0]
+                              |RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 800029e:	003b      	movs	r3, r7
+ 80002a0:	2202      	movs	r2, #2
+ 80002a2:	605a      	str	r2, [r3, #4]
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 80002a4:	003b      	movs	r3, r7
+ 80002a6:	2200      	movs	r2, #0
+ 80002a8:	609a      	str	r2, [r3, #8]
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 80002aa:	003b      	movs	r3, r7
+ 80002ac:	2200      	movs	r2, #0
+ 80002ae:	60da      	str	r2, [r3, #12]
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ 80002b0:	003b      	movs	r3, r7
+ 80002b2:	2101      	movs	r1, #1
+ 80002b4:	0018      	movs	r0, r3
+ 80002b6:	f000 feb5 	bl	8001024 <HAL_RCC_ClockConfig>
+ 80002ba:	1e03      	subs	r3, r0, #0
+ 80002bc:	d001      	beq.n	80002c2 <SystemClock_Config+0x8c>
+  {
+    Error_Handler();
+ 80002be:	f000 f881 	bl	80003c4 <Error_Handler>
+  }
+}
+ 80002c2:	46c0      	nop			; (mov r8, r8)
+ 80002c4:	46bd      	mov	sp, r7
+ 80002c6:	b011      	add	sp, #68	; 0x44
+ 80002c8:	bd90      	pop	{r4, r7, pc}
+	...
+
+080002cc <MX_GPIO_Init>:
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+ 80002cc:	b590      	push	{r4, r7, lr}
+ 80002ce:	b089      	sub	sp, #36	; 0x24
+ 80002d0:	af00      	add	r7, sp, #0
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80002d2:	240c      	movs	r4, #12
+ 80002d4:	193b      	adds	r3, r7, r4
+ 80002d6:	0018      	movs	r0, r3
+ 80002d8:	2314      	movs	r3, #20
+ 80002da:	001a      	movs	r2, r3
+ 80002dc:	2100      	movs	r1, #0
+ 80002de:	f001 f9b3 	bl	8001648 <memset>
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 80002e2:	4b36      	ldr	r3, [pc, #216]	; (80003bc <MX_GPIO_Init+0xf0>)
+ 80002e4:	695a      	ldr	r2, [r3, #20]
+ 80002e6:	4b35      	ldr	r3, [pc, #212]	; (80003bc <MX_GPIO_Init+0xf0>)
+ 80002e8:	2180      	movs	r1, #128	; 0x80
+ 80002ea:	03c9      	lsls	r1, r1, #15
+ 80002ec:	430a      	orrs	r2, r1
+ 80002ee:	615a      	str	r2, [r3, #20]
+ 80002f0:	4b32      	ldr	r3, [pc, #200]	; (80003bc <MX_GPIO_Init+0xf0>)
+ 80002f2:	695a      	ldr	r2, [r3, #20]
+ 80002f4:	2380      	movs	r3, #128	; 0x80
+ 80002f6:	03db      	lsls	r3, r3, #15
+ 80002f8:	4013      	ands	r3, r2
+ 80002fa:	60bb      	str	r3, [r7, #8]
+ 80002fc:	68bb      	ldr	r3, [r7, #8]
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80002fe:	4b2f      	ldr	r3, [pc, #188]	; (80003bc <MX_GPIO_Init+0xf0>)
+ 8000300:	695a      	ldr	r2, [r3, #20]
+ 8000302:	4b2e      	ldr	r3, [pc, #184]	; (80003bc <MX_GPIO_Init+0xf0>)
+ 8000304:	2180      	movs	r1, #128	; 0x80
+ 8000306:	0289      	lsls	r1, r1, #10
+ 8000308:	430a      	orrs	r2, r1
+ 800030a:	615a      	str	r2, [r3, #20]
+ 800030c:	4b2b      	ldr	r3, [pc, #172]	; (80003bc <MX_GPIO_Init+0xf0>)
+ 800030e:	695a      	ldr	r2, [r3, #20]
+ 8000310:	2380      	movs	r3, #128	; 0x80
+ 8000312:	029b      	lsls	r3, r3, #10
+ 8000314:	4013      	ands	r3, r2
+ 8000316:	607b      	str	r3, [r7, #4]
+ 8000318:	687b      	ldr	r3, [r7, #4]
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin
+ 800031a:	23b9      	movs	r3, #185	; 0xb9
+ 800031c:	0099      	lsls	r1, r3, #2
+ 800031e:	2390      	movs	r3, #144	; 0x90
+ 8000320:	05db      	lsls	r3, r3, #23
+ 8000322:	2200      	movs	r2, #0
+ 8000324:	0018      	movs	r0, r3
+ 8000326:	f000 fb45 	bl	80009b4 <HAL_GPIO_WritePin>
+                          |HC595_SLK2_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : MOT_IN1_Pin MOT_IN2_Pin */
+  GPIO_InitStruct.Pin = MOT_IN1_Pin|MOT_IN2_Pin;
+ 800032a:	193b      	adds	r3, r7, r4
+ 800032c:	2203      	movs	r2, #3
+ 800032e:	601a      	str	r2, [r3, #0]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8000330:	193b      	adds	r3, r7, r4
+ 8000332:	2200      	movs	r2, #0
+ 8000334:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ 8000336:	193b      	adds	r3, r7, r4
+ 8000338:	2202      	movs	r2, #2
+ 800033a:	609a      	str	r2, [r3, #8]
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 800033c:	193b      	adds	r3, r7, r4
+ 800033e:	4a20      	ldr	r2, [pc, #128]	; (80003c0 <MX_GPIO_Init+0xf4>)
+ 8000340:	0019      	movs	r1, r3
+ 8000342:	0010      	movs	r0, r2
+ 8000344:	f000 f9c6 	bl	80006d4 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : ADC_CH0_Pin ADC_CH1_Pin */
+  GPIO_InitStruct.Pin = ADC_CH0_Pin|ADC_CH1_Pin;
+ 8000348:	193b      	adds	r3, r7, r4
+ 800034a:	2203      	movs	r2, #3
+ 800034c:	601a      	str	r2, [r3, #0]
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 800034e:	193b      	adds	r3, r7, r4
+ 8000350:	2203      	movs	r2, #3
+ 8000352:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000354:	193b      	adds	r3, r7, r4
+ 8000356:	2200      	movs	r2, #0
+ 8000358:	609a      	str	r2, [r3, #8]
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800035a:	193a      	adds	r2, r7, r4
+ 800035c:	2390      	movs	r3, #144	; 0x90
+ 800035e:	05db      	lsls	r3, r3, #23
+ 8000360:	0011      	movs	r1, r2
+ 8000362:	0018      	movs	r0, r3
+ 8000364:	f000 f9b6 	bl	80006d4 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : U_T_Pin HC595_DLK_Pin HC595_SLK_Pin HC595_RLK_Pin
+                           HC595_SLK2_Pin */
+  GPIO_InitStruct.Pin = U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin
+ 8000368:	0021      	movs	r1, r4
+ 800036a:	187b      	adds	r3, r7, r1
+ 800036c:	22b9      	movs	r2, #185	; 0xb9
+ 800036e:	0092      	lsls	r2, r2, #2
+ 8000370:	601a      	str	r2, [r3, #0]
+                          |HC595_SLK2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8000372:	000c      	movs	r4, r1
+ 8000374:	193b      	adds	r3, r7, r4
+ 8000376:	2201      	movs	r2, #1
+ 8000378:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ 800037a:	193b      	adds	r3, r7, r4
+ 800037c:	2202      	movs	r2, #2
+ 800037e:	609a      	str	r2, [r3, #8]
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ 8000380:	193b      	adds	r3, r7, r4
+ 8000382:	2203      	movs	r2, #3
+ 8000384:	60da      	str	r2, [r3, #12]
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000386:	193a      	adds	r2, r7, r4
+ 8000388:	2390      	movs	r3, #144	; 0x90
+ 800038a:	05db      	lsls	r3, r3, #23
+ 800038c:	0011      	movs	r1, r2
+ 800038e:	0018      	movs	r0, r3
+ 8000390:	f000 f9a0 	bl	80006d4 <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : U_R_Pin I_R_Pin */
+  GPIO_InitStruct.Pin = U_R_Pin|I_R_Pin;
+ 8000394:	193b      	adds	r3, r7, r4
+ 8000396:	2218      	movs	r2, #24
+ 8000398:	601a      	str	r2, [r3, #0]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 800039a:	193b      	adds	r3, r7, r4
+ 800039c:	2200      	movs	r2, #0
+ 800039e:	605a      	str	r2, [r3, #4]
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ 80003a0:	193b      	adds	r3, r7, r4
+ 80003a2:	2202      	movs	r2, #2
+ 80003a4:	609a      	str	r2, [r3, #8]
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80003a6:	193a      	adds	r2, r7, r4
+ 80003a8:	2390      	movs	r3, #144	; 0x90
+ 80003aa:	05db      	lsls	r3, r3, #23
+ 80003ac:	0011      	movs	r1, r2
+ 80003ae:	0018      	movs	r0, r3
+ 80003b0:	f000 f990 	bl	80006d4 <HAL_GPIO_Init>
+
+}
+ 80003b4:	46c0      	nop			; (mov r8, r8)
+ 80003b6:	46bd      	mov	sp, r7
+ 80003b8:	b009      	add	sp, #36	; 0x24
+ 80003ba:	bd90      	pop	{r4, r7, pc}
+ 80003bc:	40021000 	.word	0x40021000
+ 80003c0:	48001400 	.word	0x48001400
+
+080003c4 <Error_Handler>:
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+ 80003c4:	b580      	push	{r7, lr}
+ 80003c6:	af00      	add	r7, sp, #0
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+ 80003c8:	b672      	cpsid	i
+}
+ 80003ca:	46c0      	nop			; (mov r8, r8)
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+ 80003cc:	e7fe      	b.n	80003cc <Error_Handler+0x8>
+	...
+
+080003d0 <HAL_MspInit>:
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+ 80003d0:	b580      	push	{r7, lr}
+ 80003d2:	b082      	sub	sp, #8
+ 80003d4:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 80003d6:	4b0f      	ldr	r3, [pc, #60]	; (8000414 <HAL_MspInit+0x44>)
+ 80003d8:	699a      	ldr	r2, [r3, #24]
+ 80003da:	4b0e      	ldr	r3, [pc, #56]	; (8000414 <HAL_MspInit+0x44>)
+ 80003dc:	2101      	movs	r1, #1
+ 80003de:	430a      	orrs	r2, r1
+ 80003e0:	619a      	str	r2, [r3, #24]
+ 80003e2:	4b0c      	ldr	r3, [pc, #48]	; (8000414 <HAL_MspInit+0x44>)
+ 80003e4:	699b      	ldr	r3, [r3, #24]
+ 80003e6:	2201      	movs	r2, #1
+ 80003e8:	4013      	ands	r3, r2
+ 80003ea:	607b      	str	r3, [r7, #4]
+ 80003ec:	687b      	ldr	r3, [r7, #4]
+  __HAL_RCC_PWR_CLK_ENABLE();
+ 80003ee:	4b09      	ldr	r3, [pc, #36]	; (8000414 <HAL_MspInit+0x44>)
+ 80003f0:	69da      	ldr	r2, [r3, #28]
+ 80003f2:	4b08      	ldr	r3, [pc, #32]	; (8000414 <HAL_MspInit+0x44>)
+ 80003f4:	2180      	movs	r1, #128	; 0x80
+ 80003f6:	0549      	lsls	r1, r1, #21
+ 80003f8:	430a      	orrs	r2, r1
+ 80003fa:	61da      	str	r2, [r3, #28]
+ 80003fc:	4b05      	ldr	r3, [pc, #20]	; (8000414 <HAL_MspInit+0x44>)
+ 80003fe:	69da      	ldr	r2, [r3, #28]
+ 8000400:	2380      	movs	r3, #128	; 0x80
+ 8000402:	055b      	lsls	r3, r3, #21
+ 8000404:	4013      	ands	r3, r2
+ 8000406:	603b      	str	r3, [r7, #0]
+ 8000408:	683b      	ldr	r3, [r7, #0]
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+ 800040a:	46c0      	nop			; (mov r8, r8)
+ 800040c:	46bd      	mov	sp, r7
+ 800040e:	b002      	add	sp, #8
+ 8000410:	bd80      	pop	{r7, pc}
+ 8000412:	46c0      	nop			; (mov r8, r8)
+ 8000414:	40021000 	.word	0x40021000
+
+08000418 <NMI_Handler>:
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+ 8000418:	b580      	push	{r7, lr}
+ 800041a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+ 800041c:	e7fe      	b.n	800041c <NMI_Handler+0x4>
+
+0800041e <HardFault_Handler>:
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+ 800041e:	b580      	push	{r7, lr}
+ 8000420:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+ 8000422:	e7fe      	b.n	8000422 <HardFault_Handler+0x4>
+
+08000424 <SVC_Handler>:
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+ 8000424:	b580      	push	{r7, lr}
+ 8000426:	af00      	add	r7, sp, #0
+
+  /* USER CODE END SVC_IRQn 0 */
+  /* USER CODE BEGIN SVC_IRQn 1 */
+
+  /* USER CODE END SVC_IRQn 1 */
+}
+ 8000428:	46c0      	nop			; (mov r8, r8)
+ 800042a:	46bd      	mov	sp, r7
+ 800042c:	bd80      	pop	{r7, pc}
+
+0800042e <PendSV_Handler>:
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+ 800042e:	b580      	push	{r7, lr}
+ 8000430:	af00      	add	r7, sp, #0
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+ 8000432:	46c0      	nop			; (mov r8, r8)
+ 8000434:	46bd      	mov	sp, r7
+ 8000436:	bd80      	pop	{r7, pc}
+
+08000438 <SysTick_Handler>:
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+ 8000438:	b580      	push	{r7, lr}
+ 800043a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+ 800043c:	f000 f87a 	bl	8000534 <HAL_IncTick>
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+ 8000440:	46c0      	nop			; (mov r8, r8)
+ 8000442:	46bd      	mov	sp, r7
+ 8000444:	bd80      	pop	{r7, pc}
+
+08000446 <SystemInit>:
+  * @brief  Setup the microcontroller system
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+ 8000446:	b580      	push	{r7, lr}
+ 8000448:	af00      	add	r7, sp, #0
+                         before branch to main program. This call is made inside
+                         the "startup_stm32f0xx.s" file.
+                         User can setups the default system clock (System clock source, PLL Multiplier
+                         and Divider factors, AHB/APBx prescalers and Flash settings).
+   */
+}
+ 800044a:	46c0      	nop			; (mov r8, r8)
+ 800044c:	46bd      	mov	sp, r7
+ 800044e:	bd80      	pop	{r7, pc}
+
+08000450 <Reset_Handler>:
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+ 8000450:	480d      	ldr	r0, [pc, #52]	; (8000488 <LoopForever+0x2>)
+  mov   sp, r0          /* set stack pointer */
+ 8000452:	4685      	mov	sp, r0
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+ 8000454:	480d      	ldr	r0, [pc, #52]	; (800048c <LoopForever+0x6>)
+  ldr r1, =_edata
+ 8000456:	490e      	ldr	r1, [pc, #56]	; (8000490 <LoopForever+0xa>)
+  ldr r2, =_sidata
+ 8000458:	4a0e      	ldr	r2, [pc, #56]	; (8000494 <LoopForever+0xe>)
+  movs r3, #0
+ 800045a:	2300      	movs	r3, #0
+  b LoopCopyDataInit
+ 800045c:	e002      	b.n	8000464 <LoopCopyDataInit>
+
+0800045e <CopyDataInit>:
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+ 800045e:	58d4      	ldr	r4, [r2, r3]
+  str r4, [r0, r3]
+ 8000460:	50c4      	str	r4, [r0, r3]
+  adds r3, r3, #4
+ 8000462:	3304      	adds	r3, #4
+
+08000464 <LoopCopyDataInit>:
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+ 8000464:	18c4      	adds	r4, r0, r3
+  cmp r4, r1
+ 8000466:	428c      	cmp	r4, r1
+  bcc CopyDataInit
+ 8000468:	d3f9      	bcc.n	800045e <CopyDataInit>
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+ 800046a:	4a0b      	ldr	r2, [pc, #44]	; (8000498 <LoopForever+0x12>)
+  ldr r4, =_ebss
+ 800046c:	4c0b      	ldr	r4, [pc, #44]	; (800049c <LoopForever+0x16>)
+  movs r3, #0
+ 800046e:	2300      	movs	r3, #0
+  b LoopFillZerobss
+ 8000470:	e001      	b.n	8000476 <LoopFillZerobss>
+
+08000472 <FillZerobss>:
+
+FillZerobss:
+  str  r3, [r2]
+ 8000472:	6013      	str	r3, [r2, #0]
+  adds r2, r2, #4
+ 8000474:	3204      	adds	r2, #4
+
+08000476 <LoopFillZerobss>:
+
+LoopFillZerobss:
+  cmp r2, r4
+ 8000476:	42a2      	cmp	r2, r4
+  bcc FillZerobss
+ 8000478:	d3fb      	bcc.n	8000472 <FillZerobss>
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+ 800047a:	f7ff ffe4 	bl	8000446 <SystemInit>
+/* Call static constructors */
+  bl __libc_init_array
+ 800047e:	f001 f8bf 	bl	8001600 <__libc_init_array>
+/* Call the application's entry point.*/
+  bl main
+ 8000482:	f7ff fecd 	bl	8000220 <main>
+
+08000486 <LoopForever>:
+
+LoopForever:
+    b LoopForever
+ 8000486:	e7fe      	b.n	8000486 <LoopForever>
+  ldr   r0, =_estack
+ 8000488:	20001000 	.word	0x20001000
+  ldr r0, =_sdata
+ 800048c:	20000000 	.word	0x20000000
+  ldr r1, =_edata
+ 8000490:	2000000c 	.word	0x2000000c
+  ldr r2, =_sidata
+ 8000494:	080016b8 	.word	0x080016b8
+  ldr r2, =_sbss
+ 8000498:	2000000c 	.word	0x2000000c
+  ldr r4, =_ebss
+ 800049c:	20000034 	.word	0x20000034
+
+080004a0 <ADC1_IRQHandler>:
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+ 80004a0:	e7fe      	b.n	80004a0 <ADC1_IRQHandler>
+	...
+
+080004a4 <HAL_Init>:
+  *       In the default implementation,Systick is used as source of time base.
+  *       The tick variable is incremented each 1ms in its ISR.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 80004a4:	b580      	push	{r7, lr}
+ 80004a6:	af00      	add	r7, sp, #0
+  /* Configure Flash prefetch */ 
+#if (PREFETCH_ENABLE != 0)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ 80004a8:	4b07      	ldr	r3, [pc, #28]	; (80004c8 <HAL_Init+0x24>)
+ 80004aa:	681a      	ldr	r2, [r3, #0]
+ 80004ac:	4b06      	ldr	r3, [pc, #24]	; (80004c8 <HAL_Init+0x24>)
+ 80004ae:	2110      	movs	r1, #16
+ 80004b0:	430a      	orrs	r2, r1
+ 80004b2:	601a      	str	r2, [r3, #0]
+#endif /* PREFETCH_ENABLE */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+
+  HAL_InitTick(TICK_INT_PRIORITY);
+ 80004b4:	2003      	movs	r0, #3
+ 80004b6:	f000 f809 	bl	80004cc <HAL_InitTick>
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+ 80004ba:	f7ff ff89 	bl	80003d0 <HAL_MspInit>
+
+  /* Return function status */
+  return HAL_OK;
+ 80004be:	2300      	movs	r3, #0
+}
+ 80004c0:	0018      	movs	r0, r3
+ 80004c2:	46bd      	mov	sp, r7
+ 80004c4:	bd80      	pop	{r7, pc}
+ 80004c6:	46c0      	nop			; (mov r8, r8)
+ 80004c8:	40022000 	.word	0x40022000
+
+080004cc <HAL_InitTick>:
+  *       implementation  in user file.
+  * @param TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 80004cc:	b590      	push	{r4, r7, lr}
+ 80004ce:	b083      	sub	sp, #12
+ 80004d0:	af00      	add	r7, sp, #0
+ 80004d2:	6078      	str	r0, [r7, #4]
+  /*Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 80004d4:	4b14      	ldr	r3, [pc, #80]	; (8000528 <HAL_InitTick+0x5c>)
+ 80004d6:	681c      	ldr	r4, [r3, #0]
+ 80004d8:	4b14      	ldr	r3, [pc, #80]	; (800052c <HAL_InitTick+0x60>)
+ 80004da:	781b      	ldrb	r3, [r3, #0]
+ 80004dc:	0019      	movs	r1, r3
+ 80004de:	23fa      	movs	r3, #250	; 0xfa
+ 80004e0:	0098      	lsls	r0, r3, #2
+ 80004e2:	f7ff fe11 	bl	8000108 <__udivsi3>
+ 80004e6:	0003      	movs	r3, r0
+ 80004e8:	0019      	movs	r1, r3
+ 80004ea:	0020      	movs	r0, r4
+ 80004ec:	f7ff fe0c 	bl	8000108 <__udivsi3>
+ 80004f0:	0003      	movs	r3, r0
+ 80004f2:	0018      	movs	r0, r3
+ 80004f4:	f000 f8e1 	bl	80006ba <HAL_SYSTICK_Config>
+ 80004f8:	1e03      	subs	r3, r0, #0
+ 80004fa:	d001      	beq.n	8000500 <HAL_InitTick+0x34>
+  {
+    return HAL_ERROR;
+ 80004fc:	2301      	movs	r3, #1
+ 80004fe:	e00f      	b.n	8000520 <HAL_InitTick+0x54>
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 8000500:	687b      	ldr	r3, [r7, #4]
+ 8000502:	2b03      	cmp	r3, #3
+ 8000504:	d80b      	bhi.n	800051e <HAL_InitTick+0x52>
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 8000506:	6879      	ldr	r1, [r7, #4]
+ 8000508:	2301      	movs	r3, #1
+ 800050a:	425b      	negs	r3, r3
+ 800050c:	2200      	movs	r2, #0
+ 800050e:	0018      	movs	r0, r3
+ 8000510:	f000 f8be 	bl	8000690 <HAL_NVIC_SetPriority>
+    uwTickPrio = TickPriority;
+ 8000514:	4b06      	ldr	r3, [pc, #24]	; (8000530 <HAL_InitTick+0x64>)
+ 8000516:	687a      	ldr	r2, [r7, #4]
+ 8000518:	601a      	str	r2, [r3, #0]
+  {
+    return HAL_ERROR;
+  }
+
+   /* Return function status */
+  return HAL_OK;
+ 800051a:	2300      	movs	r3, #0
+ 800051c:	e000      	b.n	8000520 <HAL_InitTick+0x54>
+    return HAL_ERROR;
+ 800051e:	2301      	movs	r3, #1
+}
+ 8000520:	0018      	movs	r0, r3
+ 8000522:	46bd      	mov	sp, r7
+ 8000524:	b003      	add	sp, #12
+ 8000526:	bd90      	pop	{r4, r7, pc}
+ 8000528:	20000000 	.word	0x20000000
+ 800052c:	20000008 	.word	0x20000008
+ 8000530:	20000004 	.word	0x20000004
+
+08000534 <HAL_IncTick>:
+  * @note This function is declared as __weak to be overwritten in case of other 
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+ 8000534:	b580      	push	{r7, lr}
+ 8000536:	af00      	add	r7, sp, #0
+  uwTick += uwTickFreq;
+ 8000538:	4b05      	ldr	r3, [pc, #20]	; (8000550 <HAL_IncTick+0x1c>)
+ 800053a:	781b      	ldrb	r3, [r3, #0]
+ 800053c:	001a      	movs	r2, r3
+ 800053e:	4b05      	ldr	r3, [pc, #20]	; (8000554 <HAL_IncTick+0x20>)
+ 8000540:	681b      	ldr	r3, [r3, #0]
+ 8000542:	18d2      	adds	r2, r2, r3
+ 8000544:	4b03      	ldr	r3, [pc, #12]	; (8000554 <HAL_IncTick+0x20>)
+ 8000546:	601a      	str	r2, [r3, #0]
+}
+ 8000548:	46c0      	nop			; (mov r8, r8)
+ 800054a:	46bd      	mov	sp, r7
+ 800054c:	bd80      	pop	{r7, pc}
+ 800054e:	46c0      	nop			; (mov r8, r8)
+ 8000550:	20000008 	.word	0x20000008
+ 8000554:	20000028 	.word	0x20000028
+
+08000558 <HAL_GetTick>:
+  * @note   This function is declared as __weak  to be overwritten  in case of other 
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8000558:	b580      	push	{r7, lr}
+ 800055a:	af00      	add	r7, sp, #0
+  return uwTick;
+ 800055c:	4b02      	ldr	r3, [pc, #8]	; (8000568 <HAL_GetTick+0x10>)
+ 800055e:	681b      	ldr	r3, [r3, #0]
+}
+ 8000560:	0018      	movs	r0, r3
+ 8000562:	46bd      	mov	sp, r7
+ 8000564:	bd80      	pop	{r7, pc}
+ 8000566:	46c0      	nop			; (mov r8, r8)
+ 8000568:	20000028 	.word	0x20000028
+
+0800056c <__NVIC_SetPriority>:
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 800056c:	b590      	push	{r4, r7, lr}
+ 800056e:	b083      	sub	sp, #12
+ 8000570:	af00      	add	r7, sp, #0
+ 8000572:	0002      	movs	r2, r0
+ 8000574:	6039      	str	r1, [r7, #0]
+ 8000576:	1dfb      	adds	r3, r7, #7
+ 8000578:	701a      	strb	r2, [r3, #0]
+  if ((int32_t)(IRQn) >= 0)
+ 800057a:	1dfb      	adds	r3, r7, #7
+ 800057c:	781b      	ldrb	r3, [r3, #0]
+ 800057e:	2b7f      	cmp	r3, #127	; 0x7f
+ 8000580:	d828      	bhi.n	80005d4 <__NVIC_SetPriority+0x68>
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8000582:	4a2f      	ldr	r2, [pc, #188]	; (8000640 <__NVIC_SetPriority+0xd4>)
+ 8000584:	1dfb      	adds	r3, r7, #7
+ 8000586:	781b      	ldrb	r3, [r3, #0]
+ 8000588:	b25b      	sxtb	r3, r3
+ 800058a:	089b      	lsrs	r3, r3, #2
+ 800058c:	33c0      	adds	r3, #192	; 0xc0
+ 800058e:	009b      	lsls	r3, r3, #2
+ 8000590:	589b      	ldr	r3, [r3, r2]
+ 8000592:	1dfa      	adds	r2, r7, #7
+ 8000594:	7812      	ldrb	r2, [r2, #0]
+ 8000596:	0011      	movs	r1, r2
+ 8000598:	2203      	movs	r2, #3
+ 800059a:	400a      	ands	r2, r1
+ 800059c:	00d2      	lsls	r2, r2, #3
+ 800059e:	21ff      	movs	r1, #255	; 0xff
+ 80005a0:	4091      	lsls	r1, r2
+ 80005a2:	000a      	movs	r2, r1
+ 80005a4:	43d2      	mvns	r2, r2
+ 80005a6:	401a      	ands	r2, r3
+ 80005a8:	0011      	movs	r1, r2
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 80005aa:	683b      	ldr	r3, [r7, #0]
+ 80005ac:	019b      	lsls	r3, r3, #6
+ 80005ae:	22ff      	movs	r2, #255	; 0xff
+ 80005b0:	401a      	ands	r2, r3
+ 80005b2:	1dfb      	adds	r3, r7, #7
+ 80005b4:	781b      	ldrb	r3, [r3, #0]
+ 80005b6:	0018      	movs	r0, r3
+ 80005b8:	2303      	movs	r3, #3
+ 80005ba:	4003      	ands	r3, r0
+ 80005bc:	00db      	lsls	r3, r3, #3
+ 80005be:	409a      	lsls	r2, r3
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80005c0:	481f      	ldr	r0, [pc, #124]	; (8000640 <__NVIC_SetPriority+0xd4>)
+ 80005c2:	1dfb      	adds	r3, r7, #7
+ 80005c4:	781b      	ldrb	r3, [r3, #0]
+ 80005c6:	b25b      	sxtb	r3, r3
+ 80005c8:	089b      	lsrs	r3, r3, #2
+ 80005ca:	430a      	orrs	r2, r1
+ 80005cc:	33c0      	adds	r3, #192	; 0xc0
+ 80005ce:	009b      	lsls	r3, r3, #2
+ 80005d0:	501a      	str	r2, [r3, r0]
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+ 80005d2:	e031      	b.n	8000638 <__NVIC_SetPriority+0xcc>
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80005d4:	4a1b      	ldr	r2, [pc, #108]	; (8000644 <__NVIC_SetPriority+0xd8>)
+ 80005d6:	1dfb      	adds	r3, r7, #7
+ 80005d8:	781b      	ldrb	r3, [r3, #0]
+ 80005da:	0019      	movs	r1, r3
+ 80005dc:	230f      	movs	r3, #15
+ 80005de:	400b      	ands	r3, r1
+ 80005e0:	3b08      	subs	r3, #8
+ 80005e2:	089b      	lsrs	r3, r3, #2
+ 80005e4:	3306      	adds	r3, #6
+ 80005e6:	009b      	lsls	r3, r3, #2
+ 80005e8:	18d3      	adds	r3, r2, r3
+ 80005ea:	3304      	adds	r3, #4
+ 80005ec:	681b      	ldr	r3, [r3, #0]
+ 80005ee:	1dfa      	adds	r2, r7, #7
+ 80005f0:	7812      	ldrb	r2, [r2, #0]
+ 80005f2:	0011      	movs	r1, r2
+ 80005f4:	2203      	movs	r2, #3
+ 80005f6:	400a      	ands	r2, r1
+ 80005f8:	00d2      	lsls	r2, r2, #3
+ 80005fa:	21ff      	movs	r1, #255	; 0xff
+ 80005fc:	4091      	lsls	r1, r2
+ 80005fe:	000a      	movs	r2, r1
+ 8000600:	43d2      	mvns	r2, r2
+ 8000602:	401a      	ands	r2, r3
+ 8000604:	0011      	movs	r1, r2
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8000606:	683b      	ldr	r3, [r7, #0]
+ 8000608:	019b      	lsls	r3, r3, #6
+ 800060a:	22ff      	movs	r2, #255	; 0xff
+ 800060c:	401a      	ands	r2, r3
+ 800060e:	1dfb      	adds	r3, r7, #7
+ 8000610:	781b      	ldrb	r3, [r3, #0]
+ 8000612:	0018      	movs	r0, r3
+ 8000614:	2303      	movs	r3, #3
+ 8000616:	4003      	ands	r3, r0
+ 8000618:	00db      	lsls	r3, r3, #3
+ 800061a:	409a      	lsls	r2, r3
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 800061c:	4809      	ldr	r0, [pc, #36]	; (8000644 <__NVIC_SetPriority+0xd8>)
+ 800061e:	1dfb      	adds	r3, r7, #7
+ 8000620:	781b      	ldrb	r3, [r3, #0]
+ 8000622:	001c      	movs	r4, r3
+ 8000624:	230f      	movs	r3, #15
+ 8000626:	4023      	ands	r3, r4
+ 8000628:	3b08      	subs	r3, #8
+ 800062a:	089b      	lsrs	r3, r3, #2
+ 800062c:	430a      	orrs	r2, r1
+ 800062e:	3306      	adds	r3, #6
+ 8000630:	009b      	lsls	r3, r3, #2
+ 8000632:	18c3      	adds	r3, r0, r3
+ 8000634:	3304      	adds	r3, #4
+ 8000636:	601a      	str	r2, [r3, #0]
+}
+ 8000638:	46c0      	nop			; (mov r8, r8)
+ 800063a:	46bd      	mov	sp, r7
+ 800063c:	b003      	add	sp, #12
+ 800063e:	bd90      	pop	{r4, r7, pc}
+ 8000640:	e000e100 	.word	0xe000e100
+ 8000644:	e000ed00 	.word	0xe000ed00
+
+08000648 <SysTick_Config>:
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8000648:	b580      	push	{r7, lr}
+ 800064a:	b082      	sub	sp, #8
+ 800064c:	af00      	add	r7, sp, #0
+ 800064e:	6078      	str	r0, [r7, #4]
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8000650:	687b      	ldr	r3, [r7, #4]
+ 8000652:	1e5a      	subs	r2, r3, #1
+ 8000654:	2380      	movs	r3, #128	; 0x80
+ 8000656:	045b      	lsls	r3, r3, #17
+ 8000658:	429a      	cmp	r2, r3
+ 800065a:	d301      	bcc.n	8000660 <SysTick_Config+0x18>
+  {
+    return (1UL);                                                   /* Reload value impossible */
+ 800065c:	2301      	movs	r3, #1
+ 800065e:	e010      	b.n	8000682 <SysTick_Config+0x3a>
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 8000660:	4b0a      	ldr	r3, [pc, #40]	; (800068c <SysTick_Config+0x44>)
+ 8000662:	687a      	ldr	r2, [r7, #4]
+ 8000664:	3a01      	subs	r2, #1
+ 8000666:	605a      	str	r2, [r3, #4]
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8000668:	2301      	movs	r3, #1
+ 800066a:	425b      	negs	r3, r3
+ 800066c:	2103      	movs	r1, #3
+ 800066e:	0018      	movs	r0, r3
+ 8000670:	f7ff ff7c 	bl	800056c <__NVIC_SetPriority>
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+ 8000674:	4b05      	ldr	r3, [pc, #20]	; (800068c <SysTick_Config+0x44>)
+ 8000676:	2200      	movs	r2, #0
+ 8000678:	609a      	str	r2, [r3, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 800067a:	4b04      	ldr	r3, [pc, #16]	; (800068c <SysTick_Config+0x44>)
+ 800067c:	2207      	movs	r2, #7
+ 800067e:	601a      	str	r2, [r3, #0]
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+ 8000680:	2300      	movs	r3, #0
+}
+ 8000682:	0018      	movs	r0, r3
+ 8000684:	46bd      	mov	sp, r7
+ 8000686:	b002      	add	sp, #8
+ 8000688:	bd80      	pop	{r7, pc}
+ 800068a:	46c0      	nop			; (mov r8, r8)
+ 800068c:	e000e010 	.word	0xe000e010
+
+08000690 <HAL_NVIC_SetPriority>:
+  *         with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 
+  *         no subpriority supported in Cortex M0 based products.   
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+ 8000690:	b580      	push	{r7, lr}
+ 8000692:	b084      	sub	sp, #16
+ 8000694:	af00      	add	r7, sp, #0
+ 8000696:	60b9      	str	r1, [r7, #8]
+ 8000698:	607a      	str	r2, [r7, #4]
+ 800069a:	210f      	movs	r1, #15
+ 800069c:	187b      	adds	r3, r7, r1
+ 800069e:	1c02      	adds	r2, r0, #0
+ 80006a0:	701a      	strb	r2, [r3, #0]
+  /* Check the parameters */
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  NVIC_SetPriority(IRQn,PreemptPriority);
+ 80006a2:	68ba      	ldr	r2, [r7, #8]
+ 80006a4:	187b      	adds	r3, r7, r1
+ 80006a6:	781b      	ldrb	r3, [r3, #0]
+ 80006a8:	b25b      	sxtb	r3, r3
+ 80006aa:	0011      	movs	r1, r2
+ 80006ac:	0018      	movs	r0, r3
+ 80006ae:	f7ff ff5d 	bl	800056c <__NVIC_SetPriority>
+}
+ 80006b2:	46c0      	nop			; (mov r8, r8)
+ 80006b4:	46bd      	mov	sp, r7
+ 80006b6:	b004      	add	sp, #16
+ 80006b8:	bd80      	pop	{r7, pc}
+
+080006ba <HAL_SYSTICK_Config>:
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 80006ba:	b580      	push	{r7, lr}
+ 80006bc:	b082      	sub	sp, #8
+ 80006be:	af00      	add	r7, sp, #0
+ 80006c0:	6078      	str	r0, [r7, #4]
+   return SysTick_Config(TicksNumb);
+ 80006c2:	687b      	ldr	r3, [r7, #4]
+ 80006c4:	0018      	movs	r0, r3
+ 80006c6:	f7ff ffbf 	bl	8000648 <SysTick_Config>
+ 80006ca:	0003      	movs	r3, r0
+}
+ 80006cc:	0018      	movs	r0, r3
+ 80006ce:	46bd      	mov	sp, r7
+ 80006d0:	b002      	add	sp, #8
+ 80006d2:	bd80      	pop	{r7, pc}
+
+080006d4 <HAL_GPIO_Init>:
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 80006d4:	b580      	push	{r7, lr}
+ 80006d6:	b086      	sub	sp, #24
+ 80006d8:	af00      	add	r7, sp, #0
+ 80006da:	6078      	str	r0, [r7, #4]
+ 80006dc:	6039      	str	r1, [r7, #0]
+  uint32_t position = 0x00u;
+ 80006de:	2300      	movs	r3, #0
+ 80006e0:	617b      	str	r3, [r7, #20]
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+ 80006e2:	e14f      	b.n	8000984 <HAL_GPIO_Init+0x2b0>
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1uL << position);
+ 80006e4:	683b      	ldr	r3, [r7, #0]
+ 80006e6:	681b      	ldr	r3, [r3, #0]
+ 80006e8:	2101      	movs	r1, #1
+ 80006ea:	697a      	ldr	r2, [r7, #20]
+ 80006ec:	4091      	lsls	r1, r2
+ 80006ee:	000a      	movs	r2, r1
+ 80006f0:	4013      	ands	r3, r2
+ 80006f2:	60fb      	str	r3, [r7, #12]
+
+    if (iocurrent != 0x00u)
+ 80006f4:	68fb      	ldr	r3, [r7, #12]
+ 80006f6:	2b00      	cmp	r3, #0
+ 80006f8:	d100      	bne.n	80006fc <HAL_GPIO_Init+0x28>
+ 80006fa:	e140      	b.n	800097e <HAL_GPIO_Init+0x2aa>
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 80006fc:	683b      	ldr	r3, [r7, #0]
+ 80006fe:	685b      	ldr	r3, [r3, #4]
+ 8000700:	2203      	movs	r2, #3
+ 8000702:	4013      	ands	r3, r2
+ 8000704:	2b01      	cmp	r3, #1
+ 8000706:	d005      	beq.n	8000714 <HAL_GPIO_Init+0x40>
+         ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 8000708:	683b      	ldr	r3, [r7, #0]
+ 800070a:	685b      	ldr	r3, [r3, #4]
+ 800070c:	2203      	movs	r2, #3
+ 800070e:	4013      	ands	r3, r2
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
+ 8000710:	2b02      	cmp	r3, #2
+ 8000712:	d130      	bne.n	8000776 <HAL_GPIO_Init+0xa2>
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+ 8000714:	687b      	ldr	r3, [r7, #4]
+ 8000716:	689b      	ldr	r3, [r3, #8]
+ 8000718:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
+ 800071a:	697b      	ldr	r3, [r7, #20]
+ 800071c:	005b      	lsls	r3, r3, #1
+ 800071e:	2203      	movs	r2, #3
+ 8000720:	409a      	lsls	r2, r3
+ 8000722:	0013      	movs	r3, r2
+ 8000724:	43da      	mvns	r2, r3
+ 8000726:	693b      	ldr	r3, [r7, #16]
+ 8000728:	4013      	ands	r3, r2
+ 800072a:	613b      	str	r3, [r7, #16]
+        temp |= (GPIO_Init->Speed << (position * 2u));
+ 800072c:	683b      	ldr	r3, [r7, #0]
+ 800072e:	68da      	ldr	r2, [r3, #12]
+ 8000730:	697b      	ldr	r3, [r7, #20]
+ 8000732:	005b      	lsls	r3, r3, #1
+ 8000734:	409a      	lsls	r2, r3
+ 8000736:	0013      	movs	r3, r2
+ 8000738:	693a      	ldr	r2, [r7, #16]
+ 800073a:	4313      	orrs	r3, r2
+ 800073c:	613b      	str	r3, [r7, #16]
+        GPIOx->OSPEEDR = temp;
+ 800073e:	687b      	ldr	r3, [r7, #4]
+ 8000740:	693a      	ldr	r2, [r7, #16]
+ 8000742:	609a      	str	r2, [r3, #8]
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+ 8000744:	687b      	ldr	r3, [r7, #4]
+ 8000746:	685b      	ldr	r3, [r3, #4]
+ 8000748:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 800074a:	2201      	movs	r2, #1
+ 800074c:	697b      	ldr	r3, [r7, #20]
+ 800074e:	409a      	lsls	r2, r3
+ 8000750:	0013      	movs	r3, r2
+ 8000752:	43da      	mvns	r2, r3
+ 8000754:	693b      	ldr	r3, [r7, #16]
+ 8000756:	4013      	ands	r3, r2
+ 8000758:	613b      	str	r3, [r7, #16]
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ 800075a:	683b      	ldr	r3, [r7, #0]
+ 800075c:	685b      	ldr	r3, [r3, #4]
+ 800075e:	091b      	lsrs	r3, r3, #4
+ 8000760:	2201      	movs	r2, #1
+ 8000762:	401a      	ands	r2, r3
+ 8000764:	697b      	ldr	r3, [r7, #20]
+ 8000766:	409a      	lsls	r2, r3
+ 8000768:	0013      	movs	r3, r2
+ 800076a:	693a      	ldr	r2, [r7, #16]
+ 800076c:	4313      	orrs	r3, r2
+ 800076e:	613b      	str	r3, [r7, #16]
+        GPIOx->OTYPER = temp;
+ 8000770:	687b      	ldr	r3, [r7, #4]
+ 8000772:	693a      	ldr	r2, [r7, #16]
+ 8000774:	605a      	str	r2, [r3, #4]
+      }
+      
+      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 8000776:	683b      	ldr	r3, [r7, #0]
+ 8000778:	685b      	ldr	r3, [r3, #4]
+ 800077a:	2203      	movs	r2, #3
+ 800077c:	4013      	ands	r3, r2
+ 800077e:	2b03      	cmp	r3, #3
+ 8000780:	d017      	beq.n	80007b2 <HAL_GPIO_Init+0xde>
+      {
+        /* Check the Pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+ 8000782:	687b      	ldr	r3, [r7, #4]
+ 8000784:	68db      	ldr	r3, [r3, #12]
+ 8000786:	613b      	str	r3, [r7, #16]
+        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
+ 8000788:	697b      	ldr	r3, [r7, #20]
+ 800078a:	005b      	lsls	r3, r3, #1
+ 800078c:	2203      	movs	r2, #3
+ 800078e:	409a      	lsls	r2, r3
+ 8000790:	0013      	movs	r3, r2
+ 8000792:	43da      	mvns	r2, r3
+ 8000794:	693b      	ldr	r3, [r7, #16]
+ 8000796:	4013      	ands	r3, r2
+ 8000798:	613b      	str	r3, [r7, #16]
+        temp |= ((GPIO_Init->Pull) << (position * 2u));
+ 800079a:	683b      	ldr	r3, [r7, #0]
+ 800079c:	689a      	ldr	r2, [r3, #8]
+ 800079e:	697b      	ldr	r3, [r7, #20]
+ 80007a0:	005b      	lsls	r3, r3, #1
+ 80007a2:	409a      	lsls	r2, r3
+ 80007a4:	0013      	movs	r3, r2
+ 80007a6:	693a      	ldr	r2, [r7, #16]
+ 80007a8:	4313      	orrs	r3, r2
+ 80007aa:	613b      	str	r3, [r7, #16]
+        GPIOx->PUPDR = temp;
+ 80007ac:	687b      	ldr	r3, [r7, #4]
+ 80007ae:	693a      	ldr	r2, [r7, #16]
+ 80007b0:	60da      	str	r2, [r3, #12]
+      }
+
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 80007b2:	683b      	ldr	r3, [r7, #0]
+ 80007b4:	685b      	ldr	r3, [r3, #4]
+ 80007b6:	2203      	movs	r2, #3
+ 80007b8:	4013      	ands	r3, r2
+ 80007ba:	2b02      	cmp	r3, #2
+ 80007bc:	d123      	bne.n	8000806 <HAL_GPIO_Init+0x132>
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3u];
+ 80007be:	697b      	ldr	r3, [r7, #20]
+ 80007c0:	08da      	lsrs	r2, r3, #3
+ 80007c2:	687b      	ldr	r3, [r7, #4]
+ 80007c4:	3208      	adds	r2, #8
+ 80007c6:	0092      	lsls	r2, r2, #2
+ 80007c8:	58d3      	ldr	r3, [r2, r3]
+ 80007ca:	613b      	str	r3, [r7, #16]
+        temp &= ~(0xFu << ((position & 0x07u) * 4u));
+ 80007cc:	697b      	ldr	r3, [r7, #20]
+ 80007ce:	2207      	movs	r2, #7
+ 80007d0:	4013      	ands	r3, r2
+ 80007d2:	009b      	lsls	r3, r3, #2
+ 80007d4:	220f      	movs	r2, #15
+ 80007d6:	409a      	lsls	r2, r3
+ 80007d8:	0013      	movs	r3, r2
+ 80007da:	43da      	mvns	r2, r3
+ 80007dc:	693b      	ldr	r3, [r7, #16]
+ 80007de:	4013      	ands	r3, r2
+ 80007e0:	613b      	str	r3, [r7, #16]
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+ 80007e2:	683b      	ldr	r3, [r7, #0]
+ 80007e4:	691a      	ldr	r2, [r3, #16]
+ 80007e6:	697b      	ldr	r3, [r7, #20]
+ 80007e8:	2107      	movs	r1, #7
+ 80007ea:	400b      	ands	r3, r1
+ 80007ec:	009b      	lsls	r3, r3, #2
+ 80007ee:	409a      	lsls	r2, r3
+ 80007f0:	0013      	movs	r3, r2
+ 80007f2:	693a      	ldr	r2, [r7, #16]
+ 80007f4:	4313      	orrs	r3, r2
+ 80007f6:	613b      	str	r3, [r7, #16]
+        GPIOx->AFR[position >> 3u] = temp;
+ 80007f8:	697b      	ldr	r3, [r7, #20]
+ 80007fa:	08da      	lsrs	r2, r3, #3
+ 80007fc:	687b      	ldr	r3, [r7, #4]
+ 80007fe:	3208      	adds	r2, #8
+ 8000800:	0092      	lsls	r2, r2, #2
+ 8000802:	6939      	ldr	r1, [r7, #16]
+ 8000804:	50d1      	str	r1, [r2, r3]
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+ 8000806:	687b      	ldr	r3, [r7, #4]
+ 8000808:	681b      	ldr	r3, [r3, #0]
+ 800080a:	613b      	str	r3, [r7, #16]
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
+ 800080c:	697b      	ldr	r3, [r7, #20]
+ 800080e:	005b      	lsls	r3, r3, #1
+ 8000810:	2203      	movs	r2, #3
+ 8000812:	409a      	lsls	r2, r3
+ 8000814:	0013      	movs	r3, r2
+ 8000816:	43da      	mvns	r2, r3
+ 8000818:	693b      	ldr	r3, [r7, #16]
+ 800081a:	4013      	ands	r3, r2
+ 800081c:	613b      	str	r3, [r7, #16]
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
+ 800081e:	683b      	ldr	r3, [r7, #0]
+ 8000820:	685b      	ldr	r3, [r3, #4]
+ 8000822:	2203      	movs	r2, #3
+ 8000824:	401a      	ands	r2, r3
+ 8000826:	697b      	ldr	r3, [r7, #20]
+ 8000828:	005b      	lsls	r3, r3, #1
+ 800082a:	409a      	lsls	r2, r3
+ 800082c:	0013      	movs	r3, r2
+ 800082e:	693a      	ldr	r2, [r7, #16]
+ 8000830:	4313      	orrs	r3, r2
+ 8000832:	613b      	str	r3, [r7, #16]
+      GPIOx->MODER = temp;
+ 8000834:	687b      	ldr	r3, [r7, #4]
+ 8000836:	693a      	ldr	r2, [r7, #16]
+ 8000838:	601a      	str	r2, [r3, #0]
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+ 800083a:	683b      	ldr	r3, [r7, #0]
+ 800083c:	685a      	ldr	r2, [r3, #4]
+ 800083e:	23c0      	movs	r3, #192	; 0xc0
+ 8000840:	029b      	lsls	r3, r3, #10
+ 8000842:	4013      	ands	r3, r2
+ 8000844:	d100      	bne.n	8000848 <HAL_GPIO_Init+0x174>
+ 8000846:	e09a      	b.n	800097e <HAL_GPIO_Init+0x2aa>
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8000848:	4b54      	ldr	r3, [pc, #336]	; (800099c <HAL_GPIO_Init+0x2c8>)
+ 800084a:	699a      	ldr	r2, [r3, #24]
+ 800084c:	4b53      	ldr	r3, [pc, #332]	; (800099c <HAL_GPIO_Init+0x2c8>)
+ 800084e:	2101      	movs	r1, #1
+ 8000850:	430a      	orrs	r2, r1
+ 8000852:	619a      	str	r2, [r3, #24]
+ 8000854:	4b51      	ldr	r3, [pc, #324]	; (800099c <HAL_GPIO_Init+0x2c8>)
+ 8000856:	699b      	ldr	r3, [r3, #24]
+ 8000858:	2201      	movs	r2, #1
+ 800085a:	4013      	ands	r3, r2
+ 800085c:	60bb      	str	r3, [r7, #8]
+ 800085e:	68bb      	ldr	r3, [r7, #8]
+
+        temp = SYSCFG->EXTICR[position >> 2u];
+ 8000860:	4a4f      	ldr	r2, [pc, #316]	; (80009a0 <HAL_GPIO_Init+0x2cc>)
+ 8000862:	697b      	ldr	r3, [r7, #20]
+ 8000864:	089b      	lsrs	r3, r3, #2
+ 8000866:	3302      	adds	r3, #2
+ 8000868:	009b      	lsls	r3, r3, #2
+ 800086a:	589b      	ldr	r3, [r3, r2]
+ 800086c:	613b      	str	r3, [r7, #16]
+        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
+ 800086e:	697b      	ldr	r3, [r7, #20]
+ 8000870:	2203      	movs	r2, #3
+ 8000872:	4013      	ands	r3, r2
+ 8000874:	009b      	lsls	r3, r3, #2
+ 8000876:	220f      	movs	r2, #15
+ 8000878:	409a      	lsls	r2, r3
+ 800087a:	0013      	movs	r3, r2
+ 800087c:	43da      	mvns	r2, r3
+ 800087e:	693b      	ldr	r3, [r7, #16]
+ 8000880:	4013      	ands	r3, r2
+ 8000882:	613b      	str	r3, [r7, #16]
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
+ 8000884:	687a      	ldr	r2, [r7, #4]
+ 8000886:	2390      	movs	r3, #144	; 0x90
+ 8000888:	05db      	lsls	r3, r3, #23
+ 800088a:	429a      	cmp	r2, r3
+ 800088c:	d013      	beq.n	80008b6 <HAL_GPIO_Init+0x1e2>
+ 800088e:	687b      	ldr	r3, [r7, #4]
+ 8000890:	4a44      	ldr	r2, [pc, #272]	; (80009a4 <HAL_GPIO_Init+0x2d0>)
+ 8000892:	4293      	cmp	r3, r2
+ 8000894:	d00d      	beq.n	80008b2 <HAL_GPIO_Init+0x1de>
+ 8000896:	687b      	ldr	r3, [r7, #4]
+ 8000898:	4a43      	ldr	r2, [pc, #268]	; (80009a8 <HAL_GPIO_Init+0x2d4>)
+ 800089a:	4293      	cmp	r3, r2
+ 800089c:	d007      	beq.n	80008ae <HAL_GPIO_Init+0x1da>
+ 800089e:	687b      	ldr	r3, [r7, #4]
+ 80008a0:	4a42      	ldr	r2, [pc, #264]	; (80009ac <HAL_GPIO_Init+0x2d8>)
+ 80008a2:	4293      	cmp	r3, r2
+ 80008a4:	d101      	bne.n	80008aa <HAL_GPIO_Init+0x1d6>
+ 80008a6:	2303      	movs	r3, #3
+ 80008a8:	e006      	b.n	80008b8 <HAL_GPIO_Init+0x1e4>
+ 80008aa:	2305      	movs	r3, #5
+ 80008ac:	e004      	b.n	80008b8 <HAL_GPIO_Init+0x1e4>
+ 80008ae:	2302      	movs	r3, #2
+ 80008b0:	e002      	b.n	80008b8 <HAL_GPIO_Init+0x1e4>
+ 80008b2:	2301      	movs	r3, #1
+ 80008b4:	e000      	b.n	80008b8 <HAL_GPIO_Init+0x1e4>
+ 80008b6:	2300      	movs	r3, #0
+ 80008b8:	697a      	ldr	r2, [r7, #20]
+ 80008ba:	2103      	movs	r1, #3
+ 80008bc:	400a      	ands	r2, r1
+ 80008be:	0092      	lsls	r2, r2, #2
+ 80008c0:	4093      	lsls	r3, r2
+ 80008c2:	693a      	ldr	r2, [r7, #16]
+ 80008c4:	4313      	orrs	r3, r2
+ 80008c6:	613b      	str	r3, [r7, #16]
+        SYSCFG->EXTICR[position >> 2u] = temp;
+ 80008c8:	4935      	ldr	r1, [pc, #212]	; (80009a0 <HAL_GPIO_Init+0x2cc>)
+ 80008ca:	697b      	ldr	r3, [r7, #20]
+ 80008cc:	089b      	lsrs	r3, r3, #2
+ 80008ce:	3302      	adds	r3, #2
+ 80008d0:	009b      	lsls	r3, r3, #2
+ 80008d2:	693a      	ldr	r2, [r7, #16]
+ 80008d4:	505a      	str	r2, [r3, r1]
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+ 80008d6:	4b36      	ldr	r3, [pc, #216]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 80008d8:	681b      	ldr	r3, [r3, #0]
+ 80008da:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 80008dc:	68fb      	ldr	r3, [r7, #12]
+ 80008de:	43da      	mvns	r2, r3
+ 80008e0:	693b      	ldr	r3, [r7, #16]
+ 80008e2:	4013      	ands	r3, r2
+ 80008e4:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+ 80008e6:	683b      	ldr	r3, [r7, #0]
+ 80008e8:	685a      	ldr	r2, [r3, #4]
+ 80008ea:	2380      	movs	r3, #128	; 0x80
+ 80008ec:	025b      	lsls	r3, r3, #9
+ 80008ee:	4013      	ands	r3, r2
+ 80008f0:	d003      	beq.n	80008fa <HAL_GPIO_Init+0x226>
+        {
+          temp |= iocurrent;
+ 80008f2:	693a      	ldr	r2, [r7, #16]
+ 80008f4:	68fb      	ldr	r3, [r7, #12]
+ 80008f6:	4313      	orrs	r3, r2
+ 80008f8:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->IMR = temp;
+ 80008fa:	4b2d      	ldr	r3, [pc, #180]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 80008fc:	693a      	ldr	r2, [r7, #16]
+ 80008fe:	601a      	str	r2, [r3, #0]
+
+        temp = EXTI->EMR;
+ 8000900:	4b2b      	ldr	r3, [pc, #172]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 8000902:	685b      	ldr	r3, [r3, #4]
+ 8000904:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 8000906:	68fb      	ldr	r3, [r7, #12]
+ 8000908:	43da      	mvns	r2, r3
+ 800090a:	693b      	ldr	r3, [r7, #16]
+ 800090c:	4013      	ands	r3, r2
+ 800090e:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+ 8000910:	683b      	ldr	r3, [r7, #0]
+ 8000912:	685a      	ldr	r2, [r3, #4]
+ 8000914:	2380      	movs	r3, #128	; 0x80
+ 8000916:	029b      	lsls	r3, r3, #10
+ 8000918:	4013      	ands	r3, r2
+ 800091a:	d003      	beq.n	8000924 <HAL_GPIO_Init+0x250>
+        {
+          temp |= iocurrent;
+ 800091c:	693a      	ldr	r2, [r7, #16]
+ 800091e:	68fb      	ldr	r3, [r7, #12]
+ 8000920:	4313      	orrs	r3, r2
+ 8000922:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->EMR = temp;
+ 8000924:	4b22      	ldr	r3, [pc, #136]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 8000926:	693a      	ldr	r2, [r7, #16]
+ 8000928:	605a      	str	r2, [r3, #4]
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+ 800092a:	4b21      	ldr	r3, [pc, #132]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 800092c:	689b      	ldr	r3, [r3, #8]
+ 800092e:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 8000930:	68fb      	ldr	r3, [r7, #12]
+ 8000932:	43da      	mvns	r2, r3
+ 8000934:	693b      	ldr	r3, [r7, #16]
+ 8000936:	4013      	ands	r3, r2
+ 8000938:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
+ 800093a:	683b      	ldr	r3, [r7, #0]
+ 800093c:	685a      	ldr	r2, [r3, #4]
+ 800093e:	2380      	movs	r3, #128	; 0x80
+ 8000940:	035b      	lsls	r3, r3, #13
+ 8000942:	4013      	ands	r3, r2
+ 8000944:	d003      	beq.n	800094e <HAL_GPIO_Init+0x27a>
+        {
+          temp |= iocurrent;
+ 8000946:	693a      	ldr	r2, [r7, #16]
+ 8000948:	68fb      	ldr	r3, [r7, #12]
+ 800094a:	4313      	orrs	r3, r2
+ 800094c:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->RTSR = temp;
+ 800094e:	4b18      	ldr	r3, [pc, #96]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 8000950:	693a      	ldr	r2, [r7, #16]
+ 8000952:	609a      	str	r2, [r3, #8]
+
+        temp = EXTI->FTSR;
+ 8000954:	4b16      	ldr	r3, [pc, #88]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 8000956:	68db      	ldr	r3, [r3, #12]
+ 8000958:	613b      	str	r3, [r7, #16]
+        temp &= ~(iocurrent);
+ 800095a:	68fb      	ldr	r3, [r7, #12]
+ 800095c:	43da      	mvns	r2, r3
+ 800095e:	693b      	ldr	r3, [r7, #16]
+ 8000960:	4013      	ands	r3, r2
+ 8000962:	613b      	str	r3, [r7, #16]
+        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
+ 8000964:	683b      	ldr	r3, [r7, #0]
+ 8000966:	685a      	ldr	r2, [r3, #4]
+ 8000968:	2380      	movs	r3, #128	; 0x80
+ 800096a:	039b      	lsls	r3, r3, #14
+ 800096c:	4013      	ands	r3, r2
+ 800096e:	d003      	beq.n	8000978 <HAL_GPIO_Init+0x2a4>
+        {
+          temp |= iocurrent;
+ 8000970:	693a      	ldr	r2, [r7, #16]
+ 8000972:	68fb      	ldr	r3, [r7, #12]
+ 8000974:	4313      	orrs	r3, r2
+ 8000976:	613b      	str	r3, [r7, #16]
+        }
+        EXTI->FTSR = temp;
+ 8000978:	4b0d      	ldr	r3, [pc, #52]	; (80009b0 <HAL_GPIO_Init+0x2dc>)
+ 800097a:	693a      	ldr	r2, [r7, #16]
+ 800097c:	60da      	str	r2, [r3, #12]
+      }
+    }
+
+    position++;
+ 800097e:	697b      	ldr	r3, [r7, #20]
+ 8000980:	3301      	adds	r3, #1
+ 8000982:	617b      	str	r3, [r7, #20]
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+ 8000984:	683b      	ldr	r3, [r7, #0]
+ 8000986:	681a      	ldr	r2, [r3, #0]
+ 8000988:	697b      	ldr	r3, [r7, #20]
+ 800098a:	40da      	lsrs	r2, r3
+ 800098c:	1e13      	subs	r3, r2, #0
+ 800098e:	d000      	beq.n	8000992 <HAL_GPIO_Init+0x2be>
+ 8000990:	e6a8      	b.n	80006e4 <HAL_GPIO_Init+0x10>
+  } 
+}
+ 8000992:	46c0      	nop			; (mov r8, r8)
+ 8000994:	46c0      	nop			; (mov r8, r8)
+ 8000996:	46bd      	mov	sp, r7
+ 8000998:	b006      	add	sp, #24
+ 800099a:	bd80      	pop	{r7, pc}
+ 800099c:	40021000 	.word	0x40021000
+ 80009a0:	40010000 	.word	0x40010000
+ 80009a4:	48000400 	.word	0x48000400
+ 80009a8:	48000800 	.word	0x48000800
+ 80009ac:	48000c00 	.word	0x48000c00
+ 80009b0:	40010400 	.word	0x40010400
+
+080009b4 <HAL_GPIO_WritePin>:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 80009b4:	b580      	push	{r7, lr}
+ 80009b6:	b082      	sub	sp, #8
+ 80009b8:	af00      	add	r7, sp, #0
+ 80009ba:	6078      	str	r0, [r7, #4]
+ 80009bc:	0008      	movs	r0, r1
+ 80009be:	0011      	movs	r1, r2
+ 80009c0:	1cbb      	adds	r3, r7, #2
+ 80009c2:	1c02      	adds	r2, r0, #0
+ 80009c4:	801a      	strh	r2, [r3, #0]
+ 80009c6:	1c7b      	adds	r3, r7, #1
+ 80009c8:	1c0a      	adds	r2, r1, #0
+ 80009ca:	701a      	strb	r2, [r3, #0]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+ 80009cc:	1c7b      	adds	r3, r7, #1
+ 80009ce:	781b      	ldrb	r3, [r3, #0]
+ 80009d0:	2b00      	cmp	r3, #0
+ 80009d2:	d004      	beq.n	80009de <HAL_GPIO_WritePin+0x2a>
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ 80009d4:	1cbb      	adds	r3, r7, #2
+ 80009d6:	881a      	ldrh	r2, [r3, #0]
+ 80009d8:	687b      	ldr	r3, [r7, #4]
+ 80009da:	619a      	str	r2, [r3, #24]
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+ 80009dc:	e003      	b.n	80009e6 <HAL_GPIO_WritePin+0x32>
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+ 80009de:	1cbb      	adds	r3, r7, #2
+ 80009e0:	881a      	ldrh	r2, [r3, #0]
+ 80009e2:	687b      	ldr	r3, [r7, #4]
+ 80009e4:	629a      	str	r2, [r3, #40]	; 0x28
+}
+ 80009e6:	46c0      	nop			; (mov r8, r8)
+ 80009e8:	46bd      	mov	sp, r7
+ 80009ea:	b002      	add	sp, #8
+ 80009ec:	bd80      	pop	{r7, pc}
+	...
+
+080009f0 <HAL_RCC_OscConfig>:
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+ 80009f0:	b580      	push	{r7, lr}
+ 80009f2:	b088      	sub	sp, #32
+ 80009f4:	af00      	add	r7, sp, #0
+ 80009f6:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+  uint32_t pll_config;
+  uint32_t pll_config2;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+ 80009f8:	687b      	ldr	r3, [r7, #4]
+ 80009fa:	2b00      	cmp	r3, #0
+ 80009fc:	d101      	bne.n	8000a02 <HAL_RCC_OscConfig+0x12>
+  {
+    return HAL_ERROR;
+ 80009fe:	2301      	movs	r3, #1
+ 8000a00:	e301      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+  /*------------------------------- HSE Configuration ------------------------*/ 
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 8000a02:	687b      	ldr	r3, [r7, #4]
+ 8000a04:	681b      	ldr	r3, [r3, #0]
+ 8000a06:	2201      	movs	r2, #1
+ 8000a08:	4013      	ands	r3, r2
+ 8000a0a:	d100      	bne.n	8000a0e <HAL_RCC_OscConfig+0x1e>
+ 8000a0c:	e08d      	b.n	8000b2a <HAL_RCC_OscConfig+0x13a>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
+ 8000a0e:	4bc3      	ldr	r3, [pc, #780]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a10:	685b      	ldr	r3, [r3, #4]
+ 8000a12:	220c      	movs	r2, #12
+ 8000a14:	4013      	ands	r3, r2
+ 8000a16:	2b04      	cmp	r3, #4
+ 8000a18:	d00e      	beq.n	8000a38 <HAL_RCC_OscConfig+0x48>
+       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ 8000a1a:	4bc0      	ldr	r3, [pc, #768]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a1c:	685b      	ldr	r3, [r3, #4]
+ 8000a1e:	220c      	movs	r2, #12
+ 8000a20:	4013      	ands	r3, r2
+ 8000a22:	2b08      	cmp	r3, #8
+ 8000a24:	d116      	bne.n	8000a54 <HAL_RCC_OscConfig+0x64>
+ 8000a26:	4bbd      	ldr	r3, [pc, #756]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a28:	685a      	ldr	r2, [r3, #4]
+ 8000a2a:	2380      	movs	r3, #128	; 0x80
+ 8000a2c:	025b      	lsls	r3, r3, #9
+ 8000a2e:	401a      	ands	r2, r3
+ 8000a30:	2380      	movs	r3, #128	; 0x80
+ 8000a32:	025b      	lsls	r3, r3, #9
+ 8000a34:	429a      	cmp	r2, r3
+ 8000a36:	d10d      	bne.n	8000a54 <HAL_RCC_OscConfig+0x64>
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8000a38:	4bb8      	ldr	r3, [pc, #736]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a3a:	681a      	ldr	r2, [r3, #0]
+ 8000a3c:	2380      	movs	r3, #128	; 0x80
+ 8000a3e:	029b      	lsls	r3, r3, #10
+ 8000a40:	4013      	ands	r3, r2
+ 8000a42:	d100      	bne.n	8000a46 <HAL_RCC_OscConfig+0x56>
+ 8000a44:	e070      	b.n	8000b28 <HAL_RCC_OscConfig+0x138>
+ 8000a46:	687b      	ldr	r3, [r7, #4]
+ 8000a48:	685b      	ldr	r3, [r3, #4]
+ 8000a4a:	2b00      	cmp	r3, #0
+ 8000a4c:	d000      	beq.n	8000a50 <HAL_RCC_OscConfig+0x60>
+ 8000a4e:	e06b      	b.n	8000b28 <HAL_RCC_OscConfig+0x138>
+      {
+        return HAL_ERROR;
+ 8000a50:	2301      	movs	r3, #1
+ 8000a52:	e2d8      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 8000a54:	687b      	ldr	r3, [r7, #4]
+ 8000a56:	685b      	ldr	r3, [r3, #4]
+ 8000a58:	2b01      	cmp	r3, #1
+ 8000a5a:	d107      	bne.n	8000a6c <HAL_RCC_OscConfig+0x7c>
+ 8000a5c:	4baf      	ldr	r3, [pc, #700]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a5e:	681a      	ldr	r2, [r3, #0]
+ 8000a60:	4bae      	ldr	r3, [pc, #696]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a62:	2180      	movs	r1, #128	; 0x80
+ 8000a64:	0249      	lsls	r1, r1, #9
+ 8000a66:	430a      	orrs	r2, r1
+ 8000a68:	601a      	str	r2, [r3, #0]
+ 8000a6a:	e02f      	b.n	8000acc <HAL_RCC_OscConfig+0xdc>
+ 8000a6c:	687b      	ldr	r3, [r7, #4]
+ 8000a6e:	685b      	ldr	r3, [r3, #4]
+ 8000a70:	2b00      	cmp	r3, #0
+ 8000a72:	d10c      	bne.n	8000a8e <HAL_RCC_OscConfig+0x9e>
+ 8000a74:	4ba9      	ldr	r3, [pc, #676]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a76:	681a      	ldr	r2, [r3, #0]
+ 8000a78:	4ba8      	ldr	r3, [pc, #672]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a7a:	49a9      	ldr	r1, [pc, #676]	; (8000d20 <HAL_RCC_OscConfig+0x330>)
+ 8000a7c:	400a      	ands	r2, r1
+ 8000a7e:	601a      	str	r2, [r3, #0]
+ 8000a80:	4ba6      	ldr	r3, [pc, #664]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a82:	681a      	ldr	r2, [r3, #0]
+ 8000a84:	4ba5      	ldr	r3, [pc, #660]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a86:	49a7      	ldr	r1, [pc, #668]	; (8000d24 <HAL_RCC_OscConfig+0x334>)
+ 8000a88:	400a      	ands	r2, r1
+ 8000a8a:	601a      	str	r2, [r3, #0]
+ 8000a8c:	e01e      	b.n	8000acc <HAL_RCC_OscConfig+0xdc>
+ 8000a8e:	687b      	ldr	r3, [r7, #4]
+ 8000a90:	685b      	ldr	r3, [r3, #4]
+ 8000a92:	2b05      	cmp	r3, #5
+ 8000a94:	d10e      	bne.n	8000ab4 <HAL_RCC_OscConfig+0xc4>
+ 8000a96:	4ba1      	ldr	r3, [pc, #644]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a98:	681a      	ldr	r2, [r3, #0]
+ 8000a9a:	4ba0      	ldr	r3, [pc, #640]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000a9c:	2180      	movs	r1, #128	; 0x80
+ 8000a9e:	02c9      	lsls	r1, r1, #11
+ 8000aa0:	430a      	orrs	r2, r1
+ 8000aa2:	601a      	str	r2, [r3, #0]
+ 8000aa4:	4b9d      	ldr	r3, [pc, #628]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000aa6:	681a      	ldr	r2, [r3, #0]
+ 8000aa8:	4b9c      	ldr	r3, [pc, #624]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000aaa:	2180      	movs	r1, #128	; 0x80
+ 8000aac:	0249      	lsls	r1, r1, #9
+ 8000aae:	430a      	orrs	r2, r1
+ 8000ab0:	601a      	str	r2, [r3, #0]
+ 8000ab2:	e00b      	b.n	8000acc <HAL_RCC_OscConfig+0xdc>
+ 8000ab4:	4b99      	ldr	r3, [pc, #612]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000ab6:	681a      	ldr	r2, [r3, #0]
+ 8000ab8:	4b98      	ldr	r3, [pc, #608]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000aba:	4999      	ldr	r1, [pc, #612]	; (8000d20 <HAL_RCC_OscConfig+0x330>)
+ 8000abc:	400a      	ands	r2, r1
+ 8000abe:	601a      	str	r2, [r3, #0]
+ 8000ac0:	4b96      	ldr	r3, [pc, #600]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000ac2:	681a      	ldr	r2, [r3, #0]
+ 8000ac4:	4b95      	ldr	r3, [pc, #596]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000ac6:	4997      	ldr	r1, [pc, #604]	; (8000d24 <HAL_RCC_OscConfig+0x334>)
+ 8000ac8:	400a      	ands	r2, r1
+ 8000aca:	601a      	str	r2, [r3, #0]
+      
+
+       /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 8000acc:	687b      	ldr	r3, [r7, #4]
+ 8000ace:	685b      	ldr	r3, [r3, #4]
+ 8000ad0:	2b00      	cmp	r3, #0
+ 8000ad2:	d014      	beq.n	8000afe <HAL_RCC_OscConfig+0x10e>
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000ad4:	f7ff fd40 	bl	8000558 <HAL_GetTick>
+ 8000ad8:	0003      	movs	r3, r0
+ 8000ada:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 8000adc:	e008      	b.n	8000af0 <HAL_RCC_OscConfig+0x100>
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8000ade:	f7ff fd3b 	bl	8000558 <HAL_GetTick>
+ 8000ae2:	0002      	movs	r2, r0
+ 8000ae4:	69bb      	ldr	r3, [r7, #24]
+ 8000ae6:	1ad3      	subs	r3, r2, r3
+ 8000ae8:	2b64      	cmp	r3, #100	; 0x64
+ 8000aea:	d901      	bls.n	8000af0 <HAL_RCC_OscConfig+0x100>
+          {
+            return HAL_TIMEOUT;
+ 8000aec:	2303      	movs	r3, #3
+ 8000aee:	e28a      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 8000af0:	4b8a      	ldr	r3, [pc, #552]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000af2:	681a      	ldr	r2, [r3, #0]
+ 8000af4:	2380      	movs	r3, #128	; 0x80
+ 8000af6:	029b      	lsls	r3, r3, #10
+ 8000af8:	4013      	ands	r3, r2
+ 8000afa:	d0f0      	beq.n	8000ade <HAL_RCC_OscConfig+0xee>
+ 8000afc:	e015      	b.n	8000b2a <HAL_RCC_OscConfig+0x13a>
+        }
+      }
+      else
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000afe:	f7ff fd2b 	bl	8000558 <HAL_GetTick>
+ 8000b02:	0003      	movs	r3, r0
+ 8000b04:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till HSE is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 8000b06:	e008      	b.n	8000b1a <HAL_RCC_OscConfig+0x12a>
+        {
+           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8000b08:	f7ff fd26 	bl	8000558 <HAL_GetTick>
+ 8000b0c:	0002      	movs	r2, r0
+ 8000b0e:	69bb      	ldr	r3, [r7, #24]
+ 8000b10:	1ad3      	subs	r3, r2, r3
+ 8000b12:	2b64      	cmp	r3, #100	; 0x64
+ 8000b14:	d901      	bls.n	8000b1a <HAL_RCC_OscConfig+0x12a>
+          {
+            return HAL_TIMEOUT;
+ 8000b16:	2303      	movs	r3, #3
+ 8000b18:	e275      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 8000b1a:	4b80      	ldr	r3, [pc, #512]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b1c:	681a      	ldr	r2, [r3, #0]
+ 8000b1e:	2380      	movs	r3, #128	; 0x80
+ 8000b20:	029b      	lsls	r3, r3, #10
+ 8000b22:	4013      	ands	r3, r2
+ 8000b24:	d1f0      	bne.n	8000b08 <HAL_RCC_OscConfig+0x118>
+ 8000b26:	e000      	b.n	8000b2a <HAL_RCC_OscConfig+0x13a>
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8000b28:	46c0      	nop			; (mov r8, r8)
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/ 
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 8000b2a:	687b      	ldr	r3, [r7, #4]
+ 8000b2c:	681b      	ldr	r3, [r3, #0]
+ 8000b2e:	2202      	movs	r2, #2
+ 8000b30:	4013      	ands	r3, r2
+ 8000b32:	d100      	bne.n	8000b36 <HAL_RCC_OscConfig+0x146>
+ 8000b34:	e069      	b.n	8000c0a <HAL_RCC_OscConfig+0x21a>
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+    
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
+ 8000b36:	4b79      	ldr	r3, [pc, #484]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b38:	685b      	ldr	r3, [r3, #4]
+ 8000b3a:	220c      	movs	r2, #12
+ 8000b3c:	4013      	ands	r3, r2
+ 8000b3e:	d00b      	beq.n	8000b58 <HAL_RCC_OscConfig+0x168>
+       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
+ 8000b40:	4b76      	ldr	r3, [pc, #472]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b42:	685b      	ldr	r3, [r3, #4]
+ 8000b44:	220c      	movs	r2, #12
+ 8000b46:	4013      	ands	r3, r2
+ 8000b48:	2b08      	cmp	r3, #8
+ 8000b4a:	d11c      	bne.n	8000b86 <HAL_RCC_OscConfig+0x196>
+ 8000b4c:	4b73      	ldr	r3, [pc, #460]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b4e:	685a      	ldr	r2, [r3, #4]
+ 8000b50:	2380      	movs	r3, #128	; 0x80
+ 8000b52:	025b      	lsls	r3, r3, #9
+ 8000b54:	4013      	ands	r3, r2
+ 8000b56:	d116      	bne.n	8000b86 <HAL_RCC_OscConfig+0x196>
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 8000b58:	4b70      	ldr	r3, [pc, #448]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b5a:	681b      	ldr	r3, [r3, #0]
+ 8000b5c:	2202      	movs	r2, #2
+ 8000b5e:	4013      	ands	r3, r2
+ 8000b60:	d005      	beq.n	8000b6e <HAL_RCC_OscConfig+0x17e>
+ 8000b62:	687b      	ldr	r3, [r7, #4]
+ 8000b64:	68db      	ldr	r3, [r3, #12]
+ 8000b66:	2b01      	cmp	r3, #1
+ 8000b68:	d001      	beq.n	8000b6e <HAL_RCC_OscConfig+0x17e>
+      {
+        return HAL_ERROR;
+ 8000b6a:	2301      	movs	r3, #1
+ 8000b6c:	e24b      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8000b6e:	4b6b      	ldr	r3, [pc, #428]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b70:	681b      	ldr	r3, [r3, #0]
+ 8000b72:	22f8      	movs	r2, #248	; 0xf8
+ 8000b74:	4393      	bics	r3, r2
+ 8000b76:	0019      	movs	r1, r3
+ 8000b78:	687b      	ldr	r3, [r7, #4]
+ 8000b7a:	691b      	ldr	r3, [r3, #16]
+ 8000b7c:	00da      	lsls	r2, r3, #3
+ 8000b7e:	4b67      	ldr	r3, [pc, #412]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b80:	430a      	orrs	r2, r1
+ 8000b82:	601a      	str	r2, [r3, #0]
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 8000b84:	e041      	b.n	8000c0a <HAL_RCC_OscConfig+0x21a>
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ 8000b86:	687b      	ldr	r3, [r7, #4]
+ 8000b88:	68db      	ldr	r3, [r3, #12]
+ 8000b8a:	2b00      	cmp	r3, #0
+ 8000b8c:	d024      	beq.n	8000bd8 <HAL_RCC_OscConfig+0x1e8>
+      {
+       /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+ 8000b8e:	4b63      	ldr	r3, [pc, #396]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b90:	681a      	ldr	r2, [r3, #0]
+ 8000b92:	4b62      	ldr	r3, [pc, #392]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000b94:	2101      	movs	r1, #1
+ 8000b96:	430a      	orrs	r2, r1
+ 8000b98:	601a      	str	r2, [r3, #0]
+        
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000b9a:	f7ff fcdd 	bl	8000558 <HAL_GetTick>
+ 8000b9e:	0003      	movs	r3, r0
+ 8000ba0:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000ba2:	e008      	b.n	8000bb6 <HAL_RCC_OscConfig+0x1c6>
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 8000ba4:	f7ff fcd8 	bl	8000558 <HAL_GetTick>
+ 8000ba8:	0002      	movs	r2, r0
+ 8000baa:	69bb      	ldr	r3, [r7, #24]
+ 8000bac:	1ad3      	subs	r3, r2, r3
+ 8000bae:	2b02      	cmp	r3, #2
+ 8000bb0:	d901      	bls.n	8000bb6 <HAL_RCC_OscConfig+0x1c6>
+          {
+            return HAL_TIMEOUT;
+ 8000bb2:	2303      	movs	r3, #3
+ 8000bb4:	e227      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000bb6:	4b59      	ldr	r3, [pc, #356]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000bb8:	681b      	ldr	r3, [r3, #0]
+ 8000bba:	2202      	movs	r2, #2
+ 8000bbc:	4013      	ands	r3, r2
+ 8000bbe:	d0f1      	beq.n	8000ba4 <HAL_RCC_OscConfig+0x1b4>
+          }
+        }
+                
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8000bc0:	4b56      	ldr	r3, [pc, #344]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000bc2:	681b      	ldr	r3, [r3, #0]
+ 8000bc4:	22f8      	movs	r2, #248	; 0xf8
+ 8000bc6:	4393      	bics	r3, r2
+ 8000bc8:	0019      	movs	r1, r3
+ 8000bca:	687b      	ldr	r3, [r7, #4]
+ 8000bcc:	691b      	ldr	r3, [r3, #16]
+ 8000bce:	00da      	lsls	r2, r3, #3
+ 8000bd0:	4b52      	ldr	r3, [pc, #328]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000bd2:	430a      	orrs	r2, r1
+ 8000bd4:	601a      	str	r2, [r3, #0]
+ 8000bd6:	e018      	b.n	8000c0a <HAL_RCC_OscConfig+0x21a>
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+ 8000bd8:	4b50      	ldr	r3, [pc, #320]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000bda:	681a      	ldr	r2, [r3, #0]
+ 8000bdc:	4b4f      	ldr	r3, [pc, #316]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000bde:	2101      	movs	r1, #1
+ 8000be0:	438a      	bics	r2, r1
+ 8000be2:	601a      	str	r2, [r3, #0]
+        
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000be4:	f7ff fcb8 	bl	8000558 <HAL_GetTick>
+ 8000be8:	0003      	movs	r3, r0
+ 8000bea:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till HSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 8000bec:	e008      	b.n	8000c00 <HAL_RCC_OscConfig+0x210>
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 8000bee:	f7ff fcb3 	bl	8000558 <HAL_GetTick>
+ 8000bf2:	0002      	movs	r2, r0
+ 8000bf4:	69bb      	ldr	r3, [r7, #24]
+ 8000bf6:	1ad3      	subs	r3, r2, r3
+ 8000bf8:	2b02      	cmp	r3, #2
+ 8000bfa:	d901      	bls.n	8000c00 <HAL_RCC_OscConfig+0x210>
+          {
+            return HAL_TIMEOUT;
+ 8000bfc:	2303      	movs	r3, #3
+ 8000bfe:	e202      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 8000c00:	4b46      	ldr	r3, [pc, #280]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c02:	681b      	ldr	r3, [r3, #0]
+ 8000c04:	2202      	movs	r2, #2
+ 8000c06:	4013      	ands	r3, r2
+ 8000c08:	d1f1      	bne.n	8000bee <HAL_RCC_OscConfig+0x1fe>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/ 
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 8000c0a:	687b      	ldr	r3, [r7, #4]
+ 8000c0c:	681b      	ldr	r3, [r3, #0]
+ 8000c0e:	2208      	movs	r2, #8
+ 8000c10:	4013      	ands	r3, r2
+ 8000c12:	d036      	beq.n	8000c82 <HAL_RCC_OscConfig+0x292>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+    
+    /* Check the LSI State */
+    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 8000c14:	687b      	ldr	r3, [r7, #4]
+ 8000c16:	69db      	ldr	r3, [r3, #28]
+ 8000c18:	2b00      	cmp	r3, #0
+ 8000c1a:	d019      	beq.n	8000c50 <HAL_RCC_OscConfig+0x260>
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+ 8000c1c:	4b3f      	ldr	r3, [pc, #252]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c1e:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 8000c20:	4b3e      	ldr	r3, [pc, #248]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c22:	2101      	movs	r1, #1
+ 8000c24:	430a      	orrs	r2, r1
+ 8000c26:	625a      	str	r2, [r3, #36]	; 0x24
+      
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8000c28:	f7ff fc96 	bl	8000558 <HAL_GetTick>
+ 8000c2c:	0003      	movs	r3, r0
+ 8000c2e:	61bb      	str	r3, [r7, #24]
+      
+      /* Wait till LSI is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 8000c30:	e008      	b.n	8000c44 <HAL_RCC_OscConfig+0x254>
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8000c32:	f7ff fc91 	bl	8000558 <HAL_GetTick>
+ 8000c36:	0002      	movs	r2, r0
+ 8000c38:	69bb      	ldr	r3, [r7, #24]
+ 8000c3a:	1ad3      	subs	r3, r2, r3
+ 8000c3c:	2b02      	cmp	r3, #2
+ 8000c3e:	d901      	bls.n	8000c44 <HAL_RCC_OscConfig+0x254>
+        {
+          return HAL_TIMEOUT;
+ 8000c40:	2303      	movs	r3, #3
+ 8000c42:	e1e0      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 8000c44:	4b35      	ldr	r3, [pc, #212]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c46:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8000c48:	2202      	movs	r2, #2
+ 8000c4a:	4013      	ands	r3, r2
+ 8000c4c:	d0f1      	beq.n	8000c32 <HAL_RCC_OscConfig+0x242>
+ 8000c4e:	e018      	b.n	8000c82 <HAL_RCC_OscConfig+0x292>
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+ 8000c50:	4b32      	ldr	r3, [pc, #200]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c52:	6a5a      	ldr	r2, [r3, #36]	; 0x24
+ 8000c54:	4b31      	ldr	r3, [pc, #196]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c56:	2101      	movs	r1, #1
+ 8000c58:	438a      	bics	r2, r1
+ 8000c5a:	625a      	str	r2, [r3, #36]	; 0x24
+      
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8000c5c:	f7ff fc7c 	bl	8000558 <HAL_GetTick>
+ 8000c60:	0003      	movs	r3, r0
+ 8000c62:	61bb      	str	r3, [r7, #24]
+      
+      /* Wait till LSI is disabled */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 8000c64:	e008      	b.n	8000c78 <HAL_RCC_OscConfig+0x288>
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8000c66:	f7ff fc77 	bl	8000558 <HAL_GetTick>
+ 8000c6a:	0002      	movs	r2, r0
+ 8000c6c:	69bb      	ldr	r3, [r7, #24]
+ 8000c6e:	1ad3      	subs	r3, r2, r3
+ 8000c70:	2b02      	cmp	r3, #2
+ 8000c72:	d901      	bls.n	8000c78 <HAL_RCC_OscConfig+0x288>
+        {
+          return HAL_TIMEOUT;
+ 8000c74:	2303      	movs	r3, #3
+ 8000c76:	e1c6      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 8000c78:	4b28      	ldr	r3, [pc, #160]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c7a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8000c7c:	2202      	movs	r2, #2
+ 8000c7e:	4013      	ands	r3, r2
+ 8000c80:	d1f1      	bne.n	8000c66 <HAL_RCC_OscConfig+0x276>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/ 
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 8000c82:	687b      	ldr	r3, [r7, #4]
+ 8000c84:	681b      	ldr	r3, [r3, #0]
+ 8000c86:	2204      	movs	r2, #4
+ 8000c88:	4013      	ands	r3, r2
+ 8000c8a:	d100      	bne.n	8000c8e <HAL_RCC_OscConfig+0x29e>
+ 8000c8c:	e0b4      	b.n	8000df8 <HAL_RCC_OscConfig+0x408>
+  {
+    FlagStatus       pwrclkchanged = RESET;
+ 8000c8e:	201f      	movs	r0, #31
+ 8000c90:	183b      	adds	r3, r7, r0
+ 8000c92:	2200      	movs	r2, #0
+ 8000c94:	701a      	strb	r2, [r3, #0]
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 8000c96:	4b21      	ldr	r3, [pc, #132]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000c98:	69da      	ldr	r2, [r3, #28]
+ 8000c9a:	2380      	movs	r3, #128	; 0x80
+ 8000c9c:	055b      	lsls	r3, r3, #21
+ 8000c9e:	4013      	ands	r3, r2
+ 8000ca0:	d110      	bne.n	8000cc4 <HAL_RCC_OscConfig+0x2d4>
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+ 8000ca2:	4b1e      	ldr	r3, [pc, #120]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000ca4:	69da      	ldr	r2, [r3, #28]
+ 8000ca6:	4b1d      	ldr	r3, [pc, #116]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000ca8:	2180      	movs	r1, #128	; 0x80
+ 8000caa:	0549      	lsls	r1, r1, #21
+ 8000cac:	430a      	orrs	r2, r1
+ 8000cae:	61da      	str	r2, [r3, #28]
+ 8000cb0:	4b1a      	ldr	r3, [pc, #104]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000cb2:	69da      	ldr	r2, [r3, #28]
+ 8000cb4:	2380      	movs	r3, #128	; 0x80
+ 8000cb6:	055b      	lsls	r3, r3, #21
+ 8000cb8:	4013      	ands	r3, r2
+ 8000cba:	60fb      	str	r3, [r7, #12]
+ 8000cbc:	68fb      	ldr	r3, [r7, #12]
+      pwrclkchanged = SET;
+ 8000cbe:	183b      	adds	r3, r7, r0
+ 8000cc0:	2201      	movs	r2, #1
+ 8000cc2:	701a      	strb	r2, [r3, #0]
+    }
+    
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8000cc4:	4b18      	ldr	r3, [pc, #96]	; (8000d28 <HAL_RCC_OscConfig+0x338>)
+ 8000cc6:	681a      	ldr	r2, [r3, #0]
+ 8000cc8:	2380      	movs	r3, #128	; 0x80
+ 8000cca:	005b      	lsls	r3, r3, #1
+ 8000ccc:	4013      	ands	r3, r2
+ 8000cce:	d11a      	bne.n	8000d06 <HAL_RCC_OscConfig+0x316>
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+ 8000cd0:	4b15      	ldr	r3, [pc, #84]	; (8000d28 <HAL_RCC_OscConfig+0x338>)
+ 8000cd2:	681a      	ldr	r2, [r3, #0]
+ 8000cd4:	4b14      	ldr	r3, [pc, #80]	; (8000d28 <HAL_RCC_OscConfig+0x338>)
+ 8000cd6:	2180      	movs	r1, #128	; 0x80
+ 8000cd8:	0049      	lsls	r1, r1, #1
+ 8000cda:	430a      	orrs	r2, r1
+ 8000cdc:	601a      	str	r2, [r3, #0]
+      
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+ 8000cde:	f7ff fc3b 	bl	8000558 <HAL_GetTick>
+ 8000ce2:	0003      	movs	r3, r0
+ 8000ce4:	61bb      	str	r3, [r7, #24]
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8000ce6:	e008      	b.n	8000cfa <HAL_RCC_OscConfig+0x30a>
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 8000ce8:	f7ff fc36 	bl	8000558 <HAL_GetTick>
+ 8000cec:	0002      	movs	r2, r0
+ 8000cee:	69bb      	ldr	r3, [r7, #24]
+ 8000cf0:	1ad3      	subs	r3, r2, r3
+ 8000cf2:	2b64      	cmp	r3, #100	; 0x64
+ 8000cf4:	d901      	bls.n	8000cfa <HAL_RCC_OscConfig+0x30a>
+        {
+          return HAL_TIMEOUT;
+ 8000cf6:	2303      	movs	r3, #3
+ 8000cf8:	e185      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 8000cfa:	4b0b      	ldr	r3, [pc, #44]	; (8000d28 <HAL_RCC_OscConfig+0x338>)
+ 8000cfc:	681a      	ldr	r2, [r3, #0]
+ 8000cfe:	2380      	movs	r3, #128	; 0x80
+ 8000d00:	005b      	lsls	r3, r3, #1
+ 8000d02:	4013      	ands	r3, r2
+ 8000d04:	d0f0      	beq.n	8000ce8 <HAL_RCC_OscConfig+0x2f8>
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 8000d06:	687b      	ldr	r3, [r7, #4]
+ 8000d08:	689b      	ldr	r3, [r3, #8]
+ 8000d0a:	2b01      	cmp	r3, #1
+ 8000d0c:	d10e      	bne.n	8000d2c <HAL_RCC_OscConfig+0x33c>
+ 8000d0e:	4b03      	ldr	r3, [pc, #12]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000d10:	6a1a      	ldr	r2, [r3, #32]
+ 8000d12:	4b02      	ldr	r3, [pc, #8]	; (8000d1c <HAL_RCC_OscConfig+0x32c>)
+ 8000d14:	2101      	movs	r1, #1
+ 8000d16:	430a      	orrs	r2, r1
+ 8000d18:	621a      	str	r2, [r3, #32]
+ 8000d1a:	e035      	b.n	8000d88 <HAL_RCC_OscConfig+0x398>
+ 8000d1c:	40021000 	.word	0x40021000
+ 8000d20:	fffeffff 	.word	0xfffeffff
+ 8000d24:	fffbffff 	.word	0xfffbffff
+ 8000d28:	40007000 	.word	0x40007000
+ 8000d2c:	687b      	ldr	r3, [r7, #4]
+ 8000d2e:	689b      	ldr	r3, [r3, #8]
+ 8000d30:	2b00      	cmp	r3, #0
+ 8000d32:	d10c      	bne.n	8000d4e <HAL_RCC_OscConfig+0x35e>
+ 8000d34:	4bb6      	ldr	r3, [pc, #728]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d36:	6a1a      	ldr	r2, [r3, #32]
+ 8000d38:	4bb5      	ldr	r3, [pc, #724]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d3a:	2101      	movs	r1, #1
+ 8000d3c:	438a      	bics	r2, r1
+ 8000d3e:	621a      	str	r2, [r3, #32]
+ 8000d40:	4bb3      	ldr	r3, [pc, #716]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d42:	6a1a      	ldr	r2, [r3, #32]
+ 8000d44:	4bb2      	ldr	r3, [pc, #712]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d46:	2104      	movs	r1, #4
+ 8000d48:	438a      	bics	r2, r1
+ 8000d4a:	621a      	str	r2, [r3, #32]
+ 8000d4c:	e01c      	b.n	8000d88 <HAL_RCC_OscConfig+0x398>
+ 8000d4e:	687b      	ldr	r3, [r7, #4]
+ 8000d50:	689b      	ldr	r3, [r3, #8]
+ 8000d52:	2b05      	cmp	r3, #5
+ 8000d54:	d10c      	bne.n	8000d70 <HAL_RCC_OscConfig+0x380>
+ 8000d56:	4bae      	ldr	r3, [pc, #696]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d58:	6a1a      	ldr	r2, [r3, #32]
+ 8000d5a:	4bad      	ldr	r3, [pc, #692]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d5c:	2104      	movs	r1, #4
+ 8000d5e:	430a      	orrs	r2, r1
+ 8000d60:	621a      	str	r2, [r3, #32]
+ 8000d62:	4bab      	ldr	r3, [pc, #684]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d64:	6a1a      	ldr	r2, [r3, #32]
+ 8000d66:	4baa      	ldr	r3, [pc, #680]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d68:	2101      	movs	r1, #1
+ 8000d6a:	430a      	orrs	r2, r1
+ 8000d6c:	621a      	str	r2, [r3, #32]
+ 8000d6e:	e00b      	b.n	8000d88 <HAL_RCC_OscConfig+0x398>
+ 8000d70:	4ba7      	ldr	r3, [pc, #668]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d72:	6a1a      	ldr	r2, [r3, #32]
+ 8000d74:	4ba6      	ldr	r3, [pc, #664]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d76:	2101      	movs	r1, #1
+ 8000d78:	438a      	bics	r2, r1
+ 8000d7a:	621a      	str	r2, [r3, #32]
+ 8000d7c:	4ba4      	ldr	r3, [pc, #656]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d7e:	6a1a      	ldr	r2, [r3, #32]
+ 8000d80:	4ba3      	ldr	r3, [pc, #652]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000d82:	2104      	movs	r1, #4
+ 8000d84:	438a      	bics	r2, r1
+ 8000d86:	621a      	str	r2, [r3, #32]
+    /* Check the LSE State */
+    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ 8000d88:	687b      	ldr	r3, [r7, #4]
+ 8000d8a:	689b      	ldr	r3, [r3, #8]
+ 8000d8c:	2b00      	cmp	r3, #0
+ 8000d8e:	d014      	beq.n	8000dba <HAL_RCC_OscConfig+0x3ca>
+    {
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8000d90:	f7ff fbe2 	bl	8000558 <HAL_GetTick>
+ 8000d94:	0003      	movs	r3, r0
+ 8000d96:	61bb      	str	r3, [r7, #24]
+      
+      /* Wait till LSE is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 8000d98:	e009      	b.n	8000dae <HAL_RCC_OscConfig+0x3be>
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8000d9a:	f7ff fbdd 	bl	8000558 <HAL_GetTick>
+ 8000d9e:	0002      	movs	r2, r0
+ 8000da0:	69bb      	ldr	r3, [r7, #24]
+ 8000da2:	1ad3      	subs	r3, r2, r3
+ 8000da4:	4a9b      	ldr	r2, [pc, #620]	; (8001014 <HAL_RCC_OscConfig+0x624>)
+ 8000da6:	4293      	cmp	r3, r2
+ 8000da8:	d901      	bls.n	8000dae <HAL_RCC_OscConfig+0x3be>
+        {
+          return HAL_TIMEOUT;
+ 8000daa:	2303      	movs	r3, #3
+ 8000dac:	e12b      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 8000dae:	4b98      	ldr	r3, [pc, #608]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000db0:	6a1b      	ldr	r3, [r3, #32]
+ 8000db2:	2202      	movs	r2, #2
+ 8000db4:	4013      	ands	r3, r2
+ 8000db6:	d0f0      	beq.n	8000d9a <HAL_RCC_OscConfig+0x3aa>
+ 8000db8:	e013      	b.n	8000de2 <HAL_RCC_OscConfig+0x3f2>
+      }
+    }
+    else
+    {
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8000dba:	f7ff fbcd 	bl	8000558 <HAL_GetTick>
+ 8000dbe:	0003      	movs	r3, r0
+ 8000dc0:	61bb      	str	r3, [r7, #24]
+      
+      /* Wait till LSE is disabled */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 8000dc2:	e009      	b.n	8000dd8 <HAL_RCC_OscConfig+0x3e8>
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8000dc4:	f7ff fbc8 	bl	8000558 <HAL_GetTick>
+ 8000dc8:	0002      	movs	r2, r0
+ 8000dca:	69bb      	ldr	r3, [r7, #24]
+ 8000dcc:	1ad3      	subs	r3, r2, r3
+ 8000dce:	4a91      	ldr	r2, [pc, #580]	; (8001014 <HAL_RCC_OscConfig+0x624>)
+ 8000dd0:	4293      	cmp	r3, r2
+ 8000dd2:	d901      	bls.n	8000dd8 <HAL_RCC_OscConfig+0x3e8>
+        {
+          return HAL_TIMEOUT;
+ 8000dd4:	2303      	movs	r3, #3
+ 8000dd6:	e116      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 8000dd8:	4b8d      	ldr	r3, [pc, #564]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000dda:	6a1b      	ldr	r3, [r3, #32]
+ 8000ddc:	2202      	movs	r2, #2
+ 8000dde:	4013      	ands	r3, r2
+ 8000de0:	d1f0      	bne.n	8000dc4 <HAL_RCC_OscConfig+0x3d4>
+        }
+      }
+    }
+
+    /* Require to disable power clock if necessary */
+    if(pwrclkchanged == SET)
+ 8000de2:	231f      	movs	r3, #31
+ 8000de4:	18fb      	adds	r3, r7, r3
+ 8000de6:	781b      	ldrb	r3, [r3, #0]
+ 8000de8:	2b01      	cmp	r3, #1
+ 8000dea:	d105      	bne.n	8000df8 <HAL_RCC_OscConfig+0x408>
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+ 8000dec:	4b88      	ldr	r3, [pc, #544]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000dee:	69da      	ldr	r2, [r3, #28]
+ 8000df0:	4b87      	ldr	r3, [pc, #540]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000df2:	4989      	ldr	r1, [pc, #548]	; (8001018 <HAL_RCC_OscConfig+0x628>)
+ 8000df4:	400a      	ands	r2, r1
+ 8000df6:	61da      	str	r2, [r3, #28]
+    }
+  }
+
+  /*----------------------------- HSI14 Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
+ 8000df8:	687b      	ldr	r3, [r7, #4]
+ 8000dfa:	681b      	ldr	r3, [r3, #0]
+ 8000dfc:	2210      	movs	r2, #16
+ 8000dfe:	4013      	ands	r3, r2
+ 8000e00:	d063      	beq.n	8000eca <HAL_RCC_OscConfig+0x4da>
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
+
+    /* Check the HSI14 State */
+    if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
+ 8000e02:	687b      	ldr	r3, [r7, #4]
+ 8000e04:	695b      	ldr	r3, [r3, #20]
+ 8000e06:	2b01      	cmp	r3, #1
+ 8000e08:	d12a      	bne.n	8000e60 <HAL_RCC_OscConfig+0x470>
+    {
+      /* Disable ADC control of the Internal High Speed oscillator HSI14 */
+      __HAL_RCC_HSI14ADC_DISABLE();
+ 8000e0a:	4b81      	ldr	r3, [pc, #516]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e0c:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8000e0e:	4b80      	ldr	r3, [pc, #512]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e10:	2104      	movs	r1, #4
+ 8000e12:	430a      	orrs	r2, r1
+ 8000e14:	635a      	str	r2, [r3, #52]	; 0x34
+
+      /* Enable the Internal High Speed oscillator (HSI). */
+      __HAL_RCC_HSI14_ENABLE();
+ 8000e16:	4b7e      	ldr	r3, [pc, #504]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e18:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8000e1a:	4b7d      	ldr	r3, [pc, #500]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e1c:	2101      	movs	r1, #1
+ 8000e1e:	430a      	orrs	r2, r1
+ 8000e20:	635a      	str	r2, [r3, #52]	; 0x34
+
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8000e22:	f7ff fb99 	bl	8000558 <HAL_GetTick>
+ 8000e26:	0003      	movs	r3, r0
+ 8000e28:	61bb      	str	r3, [r7, #24]
+      
+      /* Wait till HSI is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
+ 8000e2a:	e008      	b.n	8000e3e <HAL_RCC_OscConfig+0x44e>
+      {
+        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
+ 8000e2c:	f7ff fb94 	bl	8000558 <HAL_GetTick>
+ 8000e30:	0002      	movs	r2, r0
+ 8000e32:	69bb      	ldr	r3, [r7, #24]
+ 8000e34:	1ad3      	subs	r3, r2, r3
+ 8000e36:	2b02      	cmp	r3, #2
+ 8000e38:	d901      	bls.n	8000e3e <HAL_RCC_OscConfig+0x44e>
+        {
+          return HAL_TIMEOUT;
+ 8000e3a:	2303      	movs	r3, #3
+ 8000e3c:	e0e3      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
+ 8000e3e:	4b74      	ldr	r3, [pc, #464]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e40:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8000e42:	2202      	movs	r2, #2
+ 8000e44:	4013      	ands	r3, r2
+ 8000e46:	d0f1      	beq.n	8000e2c <HAL_RCC_OscConfig+0x43c>
+        }      
+      } 
+
+      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
+      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
+ 8000e48:	4b71      	ldr	r3, [pc, #452]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e4a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8000e4c:	22f8      	movs	r2, #248	; 0xf8
+ 8000e4e:	4393      	bics	r3, r2
+ 8000e50:	0019      	movs	r1, r3
+ 8000e52:	687b      	ldr	r3, [r7, #4]
+ 8000e54:	699b      	ldr	r3, [r3, #24]
+ 8000e56:	00da      	lsls	r2, r3, #3
+ 8000e58:	4b6d      	ldr	r3, [pc, #436]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e5a:	430a      	orrs	r2, r1
+ 8000e5c:	635a      	str	r2, [r3, #52]	; 0x34
+ 8000e5e:	e034      	b.n	8000eca <HAL_RCC_OscConfig+0x4da>
+    }
+    else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
+ 8000e60:	687b      	ldr	r3, [r7, #4]
+ 8000e62:	695b      	ldr	r3, [r3, #20]
+ 8000e64:	3305      	adds	r3, #5
+ 8000e66:	d111      	bne.n	8000e8c <HAL_RCC_OscConfig+0x49c>
+    {
+      /* Enable ADC control of the Internal High Speed oscillator HSI14 */
+      __HAL_RCC_HSI14ADC_ENABLE();
+ 8000e68:	4b69      	ldr	r3, [pc, #420]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e6a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8000e6c:	4b68      	ldr	r3, [pc, #416]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e6e:	2104      	movs	r1, #4
+ 8000e70:	438a      	bics	r2, r1
+ 8000e72:	635a      	str	r2, [r3, #52]	; 0x34
+
+      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
+      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
+ 8000e74:	4b66      	ldr	r3, [pc, #408]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e76:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8000e78:	22f8      	movs	r2, #248	; 0xf8
+ 8000e7a:	4393      	bics	r3, r2
+ 8000e7c:	0019      	movs	r1, r3
+ 8000e7e:	687b      	ldr	r3, [r7, #4]
+ 8000e80:	699b      	ldr	r3, [r3, #24]
+ 8000e82:	00da      	lsls	r2, r3, #3
+ 8000e84:	4b62      	ldr	r3, [pc, #392]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e86:	430a      	orrs	r2, r1
+ 8000e88:	635a      	str	r2, [r3, #52]	; 0x34
+ 8000e8a:	e01e      	b.n	8000eca <HAL_RCC_OscConfig+0x4da>
+    }
+    else
+    {
+      /* Disable ADC control of the Internal High Speed oscillator HSI14 */
+      __HAL_RCC_HSI14ADC_DISABLE();
+ 8000e8c:	4b60      	ldr	r3, [pc, #384]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e8e:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8000e90:	4b5f      	ldr	r3, [pc, #380]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e92:	2104      	movs	r1, #4
+ 8000e94:	430a      	orrs	r2, r1
+ 8000e96:	635a      	str	r2, [r3, #52]	; 0x34
+
+      /* Disable the Internal High Speed oscillator (HSI). */
+      __HAL_RCC_HSI14_DISABLE();
+ 8000e98:	4b5d      	ldr	r3, [pc, #372]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e9a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8000e9c:	4b5c      	ldr	r3, [pc, #368]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000e9e:	2101      	movs	r1, #1
+ 8000ea0:	438a      	bics	r2, r1
+ 8000ea2:	635a      	str	r2, [r3, #52]	; 0x34
+
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+ 8000ea4:	f7ff fb58 	bl	8000558 <HAL_GetTick>
+ 8000ea8:	0003      	movs	r3, r0
+ 8000eaa:	61bb      	str	r3, [r7, #24]
+      
+      /* Wait till HSI is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
+ 8000eac:	e008      	b.n	8000ec0 <HAL_RCC_OscConfig+0x4d0>
+      {
+        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
+ 8000eae:	f7ff fb53 	bl	8000558 <HAL_GetTick>
+ 8000eb2:	0002      	movs	r2, r0
+ 8000eb4:	69bb      	ldr	r3, [r7, #24]
+ 8000eb6:	1ad3      	subs	r3, r2, r3
+ 8000eb8:	2b02      	cmp	r3, #2
+ 8000eba:	d901      	bls.n	8000ec0 <HAL_RCC_OscConfig+0x4d0>
+        {
+          return HAL_TIMEOUT;
+ 8000ebc:	2303      	movs	r3, #3
+ 8000ebe:	e0a2      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
+ 8000ec0:	4b53      	ldr	r3, [pc, #332]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000ec2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8000ec4:	2202      	movs	r2, #2
+ 8000ec6:	4013      	ands	r3, r2
+ 8000ec8:	d1f1      	bne.n	8000eae <HAL_RCC_OscConfig+0x4be>
+#endif /* RCC_HSI48_SUPPORT */
+       
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 8000eca:	687b      	ldr	r3, [r7, #4]
+ 8000ecc:	6a1b      	ldr	r3, [r3, #32]
+ 8000ece:	2b00      	cmp	r3, #0
+ 8000ed0:	d100      	bne.n	8000ed4 <HAL_RCC_OscConfig+0x4e4>
+ 8000ed2:	e097      	b.n	8001004 <HAL_RCC_OscConfig+0x614>
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 8000ed4:	4b4e      	ldr	r3, [pc, #312]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000ed6:	685b      	ldr	r3, [r3, #4]
+ 8000ed8:	220c      	movs	r2, #12
+ 8000eda:	4013      	ands	r3, r2
+ 8000edc:	2b08      	cmp	r3, #8
+ 8000ede:	d100      	bne.n	8000ee2 <HAL_RCC_OscConfig+0x4f2>
+ 8000ee0:	e06b      	b.n	8000fba <HAL_RCC_OscConfig+0x5ca>
+    { 
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 8000ee2:	687b      	ldr	r3, [r7, #4]
+ 8000ee4:	6a1b      	ldr	r3, [r3, #32]
+ 8000ee6:	2b02      	cmp	r3, #2
+ 8000ee8:	d14c      	bne.n	8000f84 <HAL_RCC_OscConfig+0x594>
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+        assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+  
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 8000eea:	4b49      	ldr	r3, [pc, #292]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000eec:	681a      	ldr	r2, [r3, #0]
+ 8000eee:	4b48      	ldr	r3, [pc, #288]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000ef0:	494a      	ldr	r1, [pc, #296]	; (800101c <HAL_RCC_OscConfig+0x62c>)
+ 8000ef2:	400a      	ands	r2, r1
+ 8000ef4:	601a      	str	r2, [r3, #0]
+        
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000ef6:	f7ff fb2f 	bl	8000558 <HAL_GetTick>
+ 8000efa:	0003      	movs	r3, r0
+ 8000efc:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 8000efe:	e008      	b.n	8000f12 <HAL_RCC_OscConfig+0x522>
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8000f00:	f7ff fb2a 	bl	8000558 <HAL_GetTick>
+ 8000f04:	0002      	movs	r2, r0
+ 8000f06:	69bb      	ldr	r3, [r7, #24]
+ 8000f08:	1ad3      	subs	r3, r2, r3
+ 8000f0a:	2b02      	cmp	r3, #2
+ 8000f0c:	d901      	bls.n	8000f12 <HAL_RCC_OscConfig+0x522>
+          {
+            return HAL_TIMEOUT;
+ 8000f0e:	2303      	movs	r3, #3
+ 8000f10:	e079      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 8000f12:	4b3f      	ldr	r3, [pc, #252]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f14:	681a      	ldr	r2, [r3, #0]
+ 8000f16:	2380      	movs	r3, #128	; 0x80
+ 8000f18:	049b      	lsls	r3, r3, #18
+ 8000f1a:	4013      	ands	r3, r2
+ 8000f1c:	d1f0      	bne.n	8000f00 <HAL_RCC_OscConfig+0x510>
+          }
+        }
+
+        /* Configure the main PLL clock source, predivider and multiplication factor. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 8000f1e:	4b3c      	ldr	r3, [pc, #240]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f20:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000f22:	220f      	movs	r2, #15
+ 8000f24:	4393      	bics	r3, r2
+ 8000f26:	0019      	movs	r1, r3
+ 8000f28:	687b      	ldr	r3, [r7, #4]
+ 8000f2a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8000f2c:	4b38      	ldr	r3, [pc, #224]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f2e:	430a      	orrs	r2, r1
+ 8000f30:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8000f32:	4b37      	ldr	r3, [pc, #220]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f34:	685b      	ldr	r3, [r3, #4]
+ 8000f36:	4a3a      	ldr	r2, [pc, #232]	; (8001020 <HAL_RCC_OscConfig+0x630>)
+ 8000f38:	4013      	ands	r3, r2
+ 8000f3a:	0019      	movs	r1, r3
+ 8000f3c:	687b      	ldr	r3, [r7, #4]
+ 8000f3e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8000f40:	687b      	ldr	r3, [r7, #4]
+ 8000f42:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8000f44:	431a      	orrs	r2, r3
+ 8000f46:	4b32      	ldr	r3, [pc, #200]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f48:	430a      	orrs	r2, r1
+ 8000f4a:	605a      	str	r2, [r3, #4]
+                             RCC_OscInitStruct->PLL.PREDIV,
+                             RCC_OscInitStruct->PLL.PLLMUL);
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+ 8000f4c:	4b30      	ldr	r3, [pc, #192]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f4e:	681a      	ldr	r2, [r3, #0]
+ 8000f50:	4b2f      	ldr	r3, [pc, #188]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f52:	2180      	movs	r1, #128	; 0x80
+ 8000f54:	0449      	lsls	r1, r1, #17
+ 8000f56:	430a      	orrs	r2, r1
+ 8000f58:	601a      	str	r2, [r3, #0]
+        
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000f5a:	f7ff fafd 	bl	8000558 <HAL_GetTick>
+ 8000f5e:	0003      	movs	r3, r0
+ 8000f60:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
+ 8000f62:	e008      	b.n	8000f76 <HAL_RCC_OscConfig+0x586>
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8000f64:	f7ff faf8 	bl	8000558 <HAL_GetTick>
+ 8000f68:	0002      	movs	r2, r0
+ 8000f6a:	69bb      	ldr	r3, [r7, #24]
+ 8000f6c:	1ad3      	subs	r3, r2, r3
+ 8000f6e:	2b02      	cmp	r3, #2
+ 8000f70:	d901      	bls.n	8000f76 <HAL_RCC_OscConfig+0x586>
+          {
+            return HAL_TIMEOUT;
+ 8000f72:	2303      	movs	r3, #3
+ 8000f74:	e047      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
+ 8000f76:	4b26      	ldr	r3, [pc, #152]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f78:	681a      	ldr	r2, [r3, #0]
+ 8000f7a:	2380      	movs	r3, #128	; 0x80
+ 8000f7c:	049b      	lsls	r3, r3, #18
+ 8000f7e:	4013      	ands	r3, r2
+ 8000f80:	d0f0      	beq.n	8000f64 <HAL_RCC_OscConfig+0x574>
+ 8000f82:	e03f      	b.n	8001004 <HAL_RCC_OscConfig+0x614>
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 8000f84:	4b22      	ldr	r3, [pc, #136]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f86:	681a      	ldr	r2, [r3, #0]
+ 8000f88:	4b21      	ldr	r3, [pc, #132]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000f8a:	4924      	ldr	r1, [pc, #144]	; (800101c <HAL_RCC_OscConfig+0x62c>)
+ 8000f8c:	400a      	ands	r2, r1
+ 8000f8e:	601a      	str	r2, [r3, #0]
+ 
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+ 8000f90:	f7ff fae2 	bl	8000558 <HAL_GetTick>
+ 8000f94:	0003      	movs	r3, r0
+ 8000f96:	61bb      	str	r3, [r7, #24]
+        
+        /* Wait till PLL is disabled */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 8000f98:	e008      	b.n	8000fac <HAL_RCC_OscConfig+0x5bc>
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8000f9a:	f7ff fadd 	bl	8000558 <HAL_GetTick>
+ 8000f9e:	0002      	movs	r2, r0
+ 8000fa0:	69bb      	ldr	r3, [r7, #24]
+ 8000fa2:	1ad3      	subs	r3, r2, r3
+ 8000fa4:	2b02      	cmp	r3, #2
+ 8000fa6:	d901      	bls.n	8000fac <HAL_RCC_OscConfig+0x5bc>
+          {
+            return HAL_TIMEOUT;
+ 8000fa8:	2303      	movs	r3, #3
+ 8000faa:	e02c      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 8000fac:	4b18      	ldr	r3, [pc, #96]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000fae:	681a      	ldr	r2, [r3, #0]
+ 8000fb0:	2380      	movs	r3, #128	; 0x80
+ 8000fb2:	049b      	lsls	r3, r3, #18
+ 8000fb4:	4013      	ands	r3, r2
+ 8000fb6:	d1f0      	bne.n	8000f9a <HAL_RCC_OscConfig+0x5aa>
+ 8000fb8:	e024      	b.n	8001004 <HAL_RCC_OscConfig+0x614>
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+ 8000fba:	687b      	ldr	r3, [r7, #4]
+ 8000fbc:	6a1b      	ldr	r3, [r3, #32]
+ 8000fbe:	2b01      	cmp	r3, #1
+ 8000fc0:	d101      	bne.n	8000fc6 <HAL_RCC_OscConfig+0x5d6>
+      {
+        return HAL_ERROR;
+ 8000fc2:	2301      	movs	r3, #1
+ 8000fc4:	e01f      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        pll_config  = RCC->CFGR;
+ 8000fc6:	4b12      	ldr	r3, [pc, #72]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000fc8:	685b      	ldr	r3, [r3, #4]
+ 8000fca:	617b      	str	r3, [r7, #20]
+        pll_config2 = RCC->CFGR2;
+ 8000fcc:	4b10      	ldr	r3, [pc, #64]	; (8001010 <HAL_RCC_OscConfig+0x620>)
+ 8000fce:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8000fd0:	613b      	str	r3, [r7, #16]
+        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
+ 8000fd2:	697a      	ldr	r2, [r7, #20]
+ 8000fd4:	2380      	movs	r3, #128	; 0x80
+ 8000fd6:	025b      	lsls	r3, r3, #9
+ 8000fd8:	401a      	ands	r2, r3
+ 8000fda:	687b      	ldr	r3, [r7, #4]
+ 8000fdc:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8000fde:	429a      	cmp	r2, r3
+ 8000fe0:	d10e      	bne.n	8001000 <HAL_RCC_OscConfig+0x610>
+           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
+ 8000fe2:	693b      	ldr	r3, [r7, #16]
+ 8000fe4:	220f      	movs	r2, #15
+ 8000fe6:	401a      	ands	r2, r3
+ 8000fe8:	687b      	ldr	r3, [r7, #4]
+ 8000fea:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
+ 8000fec:	429a      	cmp	r2, r3
+ 8000fee:	d107      	bne.n	8001000 <HAL_RCC_OscConfig+0x610>
+           (READ_BIT(pll_config,  RCC_CFGR_PLLMUL)  != RCC_OscInitStruct->PLL.PLLMUL))
+ 8000ff0:	697a      	ldr	r2, [r7, #20]
+ 8000ff2:	23f0      	movs	r3, #240	; 0xf0
+ 8000ff4:	039b      	lsls	r3, r3, #14
+ 8000ff6:	401a      	ands	r2, r3
+ 8000ff8:	687b      	ldr	r3, [r7, #4]
+ 8000ffa:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
+ 8000ffc:	429a      	cmp	r2, r3
+ 8000ffe:	d001      	beq.n	8001004 <HAL_RCC_OscConfig+0x614>
+        {
+          return HAL_ERROR;
+ 8001000:	2301      	movs	r3, #1
+ 8001002:	e000      	b.n	8001006 <HAL_RCC_OscConfig+0x616>
+        }
+      }
+    }
+  }
+
+  return HAL_OK;
+ 8001004:	2300      	movs	r3, #0
+}
+ 8001006:	0018      	movs	r0, r3
+ 8001008:	46bd      	mov	sp, r7
+ 800100a:	b008      	add	sp, #32
+ 800100c:	bd80      	pop	{r7, pc}
+ 800100e:	46c0      	nop			; (mov r8, r8)
+ 8001010:	40021000 	.word	0x40021000
+ 8001014:	00001388 	.word	0x00001388
+ 8001018:	efffffff 	.word	0xefffffff
+ 800101c:	feffffff 	.word	0xfeffffff
+ 8001020:	ffc2ffff 	.word	0xffc2ffff
+
+08001024 <HAL_RCC_ClockConfig>:
+  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 8001024:	b580      	push	{r7, lr}
+ 8001026:	b084      	sub	sp, #16
+ 8001028:	af00      	add	r7, sp, #0
+ 800102a:	6078      	str	r0, [r7, #4]
+ 800102c:	6039      	str	r1, [r7, #0]
+  uint32_t tickstart;
+
+  /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+ 800102e:	687b      	ldr	r3, [r7, #4]
+ 8001030:	2b00      	cmp	r3, #0
+ 8001032:	d101      	bne.n	8001038 <HAL_RCC_ClockConfig+0x14>
+  {
+    return HAL_ERROR;
+ 8001034:	2301      	movs	r3, #1
+ 8001036:	e0b3      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+  must be correctly programmed according to the frequency of the CPU clock 
+    (HCLK) of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+ 8001038:	4b5b      	ldr	r3, [pc, #364]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 800103a:	681b      	ldr	r3, [r3, #0]
+ 800103c:	2201      	movs	r2, #1
+ 800103e:	4013      	ands	r3, r2
+ 8001040:	683a      	ldr	r2, [r7, #0]
+ 8001042:	429a      	cmp	r2, r3
+ 8001044:	d911      	bls.n	800106a <HAL_RCC_ClockConfig+0x46>
+  {    
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8001046:	4b58      	ldr	r3, [pc, #352]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 8001048:	681b      	ldr	r3, [r3, #0]
+ 800104a:	2201      	movs	r2, #1
+ 800104c:	4393      	bics	r3, r2
+ 800104e:	0019      	movs	r1, r3
+ 8001050:	4b55      	ldr	r3, [pc, #340]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 8001052:	683a      	ldr	r2, [r7, #0]
+ 8001054:	430a      	orrs	r2, r1
+ 8001056:	601a      	str	r2, [r3, #0]
+    
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8001058:	4b53      	ldr	r3, [pc, #332]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 800105a:	681b      	ldr	r3, [r3, #0]
+ 800105c:	2201      	movs	r2, #1
+ 800105e:	4013      	ands	r3, r2
+ 8001060:	683a      	ldr	r2, [r7, #0]
+ 8001062:	429a      	cmp	r2, r3
+ 8001064:	d001      	beq.n	800106a <HAL_RCC_ClockConfig+0x46>
+    {
+      return HAL_ERROR;
+ 8001066:	2301      	movs	r3, #1
+ 8001068:	e09a      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 800106a:	687b      	ldr	r3, [r7, #4]
+ 800106c:	681b      	ldr	r3, [r3, #0]
+ 800106e:	2202      	movs	r2, #2
+ 8001070:	4013      	ands	r3, r2
+ 8001072:	d015      	beq.n	80010a0 <HAL_RCC_ClockConfig+0x7c>
+  {
+    /* Set the highest APB divider in order to ensure that we do not go through
+       a non-spec phase whatever we decrease or increase HCLK. */
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8001074:	687b      	ldr	r3, [r7, #4]
+ 8001076:	681b      	ldr	r3, [r3, #0]
+ 8001078:	2204      	movs	r2, #4
+ 800107a:	4013      	ands	r3, r2
+ 800107c:	d006      	beq.n	800108c <HAL_RCC_ClockConfig+0x68>
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
+ 800107e:	4b4b      	ldr	r3, [pc, #300]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 8001080:	685a      	ldr	r2, [r3, #4]
+ 8001082:	4b4a      	ldr	r3, [pc, #296]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 8001084:	21e0      	movs	r1, #224	; 0xe0
+ 8001086:	00c9      	lsls	r1, r1, #3
+ 8001088:	430a      	orrs	r2, r1
+ 800108a:	605a      	str	r2, [r3, #4]
+    }
+
+    /* Set the new HCLK clock divider */
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 800108c:	4b47      	ldr	r3, [pc, #284]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 800108e:	685b      	ldr	r3, [r3, #4]
+ 8001090:	22f0      	movs	r2, #240	; 0xf0
+ 8001092:	4393      	bics	r3, r2
+ 8001094:	0019      	movs	r1, r3
+ 8001096:	687b      	ldr	r3, [r7, #4]
+ 8001098:	689a      	ldr	r2, [r3, #8]
+ 800109a:	4b44      	ldr	r3, [pc, #272]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 800109c:	430a      	orrs	r2, r1
+ 800109e:	605a      	str	r2, [r3, #4]
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/ 
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 80010a0:	687b      	ldr	r3, [r7, #4]
+ 80010a2:	681b      	ldr	r3, [r3, #0]
+ 80010a4:	2201      	movs	r2, #1
+ 80010a6:	4013      	ands	r3, r2
+ 80010a8:	d040      	beq.n	800112c <HAL_RCC_ClockConfig+0x108>
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+    
+    /* HSE is selected as System Clock Source */
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 80010aa:	687b      	ldr	r3, [r7, #4]
+ 80010ac:	685b      	ldr	r3, [r3, #4]
+ 80010ae:	2b01      	cmp	r3, #1
+ 80010b0:	d107      	bne.n	80010c2 <HAL_RCC_ClockConfig+0x9e>
+    {
+      /* Check the HSE ready flag */  
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 80010b2:	4b3e      	ldr	r3, [pc, #248]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 80010b4:	681a      	ldr	r2, [r3, #0]
+ 80010b6:	2380      	movs	r3, #128	; 0x80
+ 80010b8:	029b      	lsls	r3, r3, #10
+ 80010ba:	4013      	ands	r3, r2
+ 80010bc:	d114      	bne.n	80010e8 <HAL_RCC_ClockConfig+0xc4>
+      {
+        return HAL_ERROR;
+ 80010be:	2301      	movs	r3, #1
+ 80010c0:	e06e      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 80010c2:	687b      	ldr	r3, [r7, #4]
+ 80010c4:	685b      	ldr	r3, [r3, #4]
+ 80010c6:	2b02      	cmp	r3, #2
+ 80010c8:	d107      	bne.n	80010da <HAL_RCC_ClockConfig+0xb6>
+    {
+      /* Check the PLL ready flag */  
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 80010ca:	4b38      	ldr	r3, [pc, #224]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 80010cc:	681a      	ldr	r2, [r3, #0]
+ 80010ce:	2380      	movs	r3, #128	; 0x80
+ 80010d0:	049b      	lsls	r3, r3, #18
+ 80010d2:	4013      	ands	r3, r2
+ 80010d4:	d108      	bne.n	80010e8 <HAL_RCC_ClockConfig+0xc4>
+      {
+        return HAL_ERROR;
+ 80010d6:	2301      	movs	r3, #1
+ 80010d8:	e062      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+#endif /* RCC_CFGR_SWS_HSI48 */
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */  
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 80010da:	4b34      	ldr	r3, [pc, #208]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 80010dc:	681b      	ldr	r3, [r3, #0]
+ 80010de:	2202      	movs	r2, #2
+ 80010e0:	4013      	ands	r3, r2
+ 80010e2:	d101      	bne.n	80010e8 <HAL_RCC_ClockConfig+0xc4>
+      {
+        return HAL_ERROR;
+ 80010e4:	2301      	movs	r3, #1
+ 80010e6:	e05b      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+      }
+    }
+    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 80010e8:	4b30      	ldr	r3, [pc, #192]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 80010ea:	685b      	ldr	r3, [r3, #4]
+ 80010ec:	2203      	movs	r2, #3
+ 80010ee:	4393      	bics	r3, r2
+ 80010f0:	0019      	movs	r1, r3
+ 80010f2:	687b      	ldr	r3, [r7, #4]
+ 80010f4:	685a      	ldr	r2, [r3, #4]
+ 80010f6:	4b2d      	ldr	r3, [pc, #180]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 80010f8:	430a      	orrs	r2, r1
+ 80010fa:	605a      	str	r2, [r3, #4]
+
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+ 80010fc:	f7ff fa2c 	bl	8000558 <HAL_GetTick>
+ 8001100:	0003      	movs	r3, r0
+ 8001102:	60fb      	str	r3, [r7, #12]
+    
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8001104:	e009      	b.n	800111a <HAL_RCC_ClockConfig+0xf6>
+    {
+      if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8001106:	f7ff fa27 	bl	8000558 <HAL_GetTick>
+ 800110a:	0002      	movs	r2, r0
+ 800110c:	68fb      	ldr	r3, [r7, #12]
+ 800110e:	1ad3      	subs	r3, r2, r3
+ 8001110:	4a27      	ldr	r2, [pc, #156]	; (80011b0 <HAL_RCC_ClockConfig+0x18c>)
+ 8001112:	4293      	cmp	r3, r2
+ 8001114:	d901      	bls.n	800111a <HAL_RCC_ClockConfig+0xf6>
+      {
+        return HAL_TIMEOUT;
+ 8001116:	2303      	movs	r3, #3
+ 8001118:	e042      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 800111a:	4b24      	ldr	r3, [pc, #144]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 800111c:	685b      	ldr	r3, [r3, #4]
+ 800111e:	220c      	movs	r2, #12
+ 8001120:	401a      	ands	r2, r3
+ 8001122:	687b      	ldr	r3, [r7, #4]
+ 8001124:	685b      	ldr	r3, [r3, #4]
+ 8001126:	009b      	lsls	r3, r3, #2
+ 8001128:	429a      	cmp	r2, r3
+ 800112a:	d1ec      	bne.n	8001106 <HAL_RCC_ClockConfig+0xe2>
+      }
+    }
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+ 800112c:	4b1e      	ldr	r3, [pc, #120]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 800112e:	681b      	ldr	r3, [r3, #0]
+ 8001130:	2201      	movs	r2, #1
+ 8001132:	4013      	ands	r3, r2
+ 8001134:	683a      	ldr	r2, [r7, #0]
+ 8001136:	429a      	cmp	r2, r3
+ 8001138:	d211      	bcs.n	800115e <HAL_RCC_ClockConfig+0x13a>
+  {    
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 800113a:	4b1b      	ldr	r3, [pc, #108]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 800113c:	681b      	ldr	r3, [r3, #0]
+ 800113e:	2201      	movs	r2, #1
+ 8001140:	4393      	bics	r3, r2
+ 8001142:	0019      	movs	r1, r3
+ 8001144:	4b18      	ldr	r3, [pc, #96]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 8001146:	683a      	ldr	r2, [r7, #0]
+ 8001148:	430a      	orrs	r2, r1
+ 800114a:	601a      	str	r2, [r3, #0]
+    
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 800114c:	4b16      	ldr	r3, [pc, #88]	; (80011a8 <HAL_RCC_ClockConfig+0x184>)
+ 800114e:	681b      	ldr	r3, [r3, #0]
+ 8001150:	2201      	movs	r2, #1
+ 8001152:	4013      	ands	r3, r2
+ 8001154:	683a      	ldr	r2, [r7, #0]
+ 8001156:	429a      	cmp	r2, r3
+ 8001158:	d001      	beq.n	800115e <HAL_RCC_ClockConfig+0x13a>
+    {
+      return HAL_ERROR;
+ 800115a:	2301      	movs	r3, #1
+ 800115c:	e020      	b.n	80011a0 <HAL_RCC_ClockConfig+0x17c>
+    }
+  }    
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/ 
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 800115e:	687b      	ldr	r3, [r7, #4]
+ 8001160:	681b      	ldr	r3, [r3, #0]
+ 8001162:	2204      	movs	r2, #4
+ 8001164:	4013      	ands	r3, r2
+ 8001166:	d009      	beq.n	800117c <HAL_RCC_ClockConfig+0x158>
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
+ 8001168:	4b10      	ldr	r3, [pc, #64]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 800116a:	685b      	ldr	r3, [r3, #4]
+ 800116c:	4a11      	ldr	r2, [pc, #68]	; (80011b4 <HAL_RCC_ClockConfig+0x190>)
+ 800116e:	4013      	ands	r3, r2
+ 8001170:	0019      	movs	r1, r3
+ 8001172:	687b      	ldr	r3, [r7, #4]
+ 8001174:	68da      	ldr	r2, [r3, #12]
+ 8001176:	4b0d      	ldr	r3, [pc, #52]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 8001178:	430a      	orrs	r2, r1
+ 800117a:	605a      	str	r2, [r3, #4]
+  }
+  
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+ 800117c:	f000 f820 	bl	80011c0 <HAL_RCC_GetSysClockFreq>
+ 8001180:	0001      	movs	r1, r0
+ 8001182:	4b0a      	ldr	r3, [pc, #40]	; (80011ac <HAL_RCC_ClockConfig+0x188>)
+ 8001184:	685b      	ldr	r3, [r3, #4]
+ 8001186:	091b      	lsrs	r3, r3, #4
+ 8001188:	220f      	movs	r2, #15
+ 800118a:	4013      	ands	r3, r2
+ 800118c:	4a0a      	ldr	r2, [pc, #40]	; (80011b8 <HAL_RCC_ClockConfig+0x194>)
+ 800118e:	5cd3      	ldrb	r3, [r2, r3]
+ 8001190:	000a      	movs	r2, r1
+ 8001192:	40da      	lsrs	r2, r3
+ 8001194:	4b09      	ldr	r3, [pc, #36]	; (80011bc <HAL_RCC_ClockConfig+0x198>)
+ 8001196:	601a      	str	r2, [r3, #0]
+
+  /* Configure the source of time base considering new system clocks settings*/
+  HAL_InitTick (TICK_INT_PRIORITY);
+ 8001198:	2003      	movs	r0, #3
+ 800119a:	f7ff f997 	bl	80004cc <HAL_InitTick>
+  
+  return HAL_OK;
+ 800119e:	2300      	movs	r3, #0
+}
+ 80011a0:	0018      	movs	r0, r3
+ 80011a2:	46bd      	mov	sp, r7
+ 80011a4:	b004      	add	sp, #16
+ 80011a6:	bd80      	pop	{r7, pc}
+ 80011a8:	40022000 	.word	0x40022000
+ 80011ac:	40021000 	.word	0x40021000
+ 80011b0:	00001388 	.word	0x00001388
+ 80011b4:	fffff8ff 	.word	0xfffff8ff
+ 80011b8:	08001690 	.word	0x08001690
+ 80011bc:	20000000 	.word	0x20000000
+
+080011c0 <HAL_RCC_GetSysClockFreq>:
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *         
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ 80011c0:	b590      	push	{r4, r7, lr}
+ 80011c2:	b08f      	sub	sp, #60	; 0x3c
+ 80011c4:	af00      	add	r7, sp, #0
+  const uint8_t aPLLMULFactorTable[16] = { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
+ 80011c6:	2314      	movs	r3, #20
+ 80011c8:	18fb      	adds	r3, r7, r3
+ 80011ca:	4a2b      	ldr	r2, [pc, #172]	; (8001278 <HAL_RCC_GetSysClockFreq+0xb8>)
+ 80011cc:	ca13      	ldmia	r2!, {r0, r1, r4}
+ 80011ce:	c313      	stmia	r3!, {r0, r1, r4}
+ 80011d0:	6812      	ldr	r2, [r2, #0]
+ 80011d2:	601a      	str	r2, [r3, #0]
+                                         10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
+  const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
+ 80011d4:	1d3b      	adds	r3, r7, #4
+ 80011d6:	4a29      	ldr	r2, [pc, #164]	; (800127c <HAL_RCC_GetSysClockFreq+0xbc>)
+ 80011d8:	ca13      	ldmia	r2!, {r0, r1, r4}
+ 80011da:	c313      	stmia	r3!, {r0, r1, r4}
+ 80011dc:	6812      	ldr	r2, [r2, #0]
+ 80011de:	601a      	str	r2, [r3, #0]
+                                           9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
+
+  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
+ 80011e0:	2300      	movs	r3, #0
+ 80011e2:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 80011e4:	2300      	movs	r3, #0
+ 80011e6:	62bb      	str	r3, [r7, #40]	; 0x28
+ 80011e8:	2300      	movs	r3, #0
+ 80011ea:	637b      	str	r3, [r7, #52]	; 0x34
+ 80011ec:	2300      	movs	r3, #0
+ 80011ee:	627b      	str	r3, [r7, #36]	; 0x24
+  uint32_t sysclockfreq = 0U;
+ 80011f0:	2300      	movs	r3, #0
+ 80011f2:	633b      	str	r3, [r7, #48]	; 0x30
+  
+  tmpreg = RCC->CFGR;
+ 80011f4:	4b22      	ldr	r3, [pc, #136]	; (8001280 <HAL_RCC_GetSysClockFreq+0xc0>)
+ 80011f6:	685b      	ldr	r3, [r3, #4]
+ 80011f8:	62fb      	str	r3, [r7, #44]	; 0x2c
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (tmpreg & RCC_CFGR_SWS)
+ 80011fa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 80011fc:	220c      	movs	r2, #12
+ 80011fe:	4013      	ands	r3, r2
+ 8001200:	2b04      	cmp	r3, #4
+ 8001202:	d002      	beq.n	800120a <HAL_RCC_GetSysClockFreq+0x4a>
+ 8001204:	2b08      	cmp	r3, #8
+ 8001206:	d003      	beq.n	8001210 <HAL_RCC_GetSysClockFreq+0x50>
+ 8001208:	e02d      	b.n	8001266 <HAL_RCC_GetSysClockFreq+0xa6>
+  {
+    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
+    {
+      sysclockfreq = HSE_VALUE;
+ 800120a:	4b1e      	ldr	r3, [pc, #120]	; (8001284 <HAL_RCC_GetSysClockFreq+0xc4>)
+ 800120c:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 800120e:	e02d      	b.n	800126c <HAL_RCC_GetSysClockFreq+0xac>
+    }
+    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
+    {
+      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
+ 8001210:	6afb      	ldr	r3, [r7, #44]	; 0x2c
+ 8001212:	0c9b      	lsrs	r3, r3, #18
+ 8001214:	220f      	movs	r2, #15
+ 8001216:	4013      	ands	r3, r2
+ 8001218:	2214      	movs	r2, #20
+ 800121a:	18ba      	adds	r2, r7, r2
+ 800121c:	5cd3      	ldrb	r3, [r2, r3]
+ 800121e:	627b      	str	r3, [r7, #36]	; 0x24
+      prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
+ 8001220:	4b17      	ldr	r3, [pc, #92]	; (8001280 <HAL_RCC_GetSysClockFreq+0xc0>)
+ 8001222:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8001224:	220f      	movs	r2, #15
+ 8001226:	4013      	ands	r3, r2
+ 8001228:	1d3a      	adds	r2, r7, #4
+ 800122a:	5cd3      	ldrb	r3, [r2, r3]
+ 800122c:	62bb      	str	r3, [r7, #40]	; 0x28
+      if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ 800122e:	6afa      	ldr	r2, [r7, #44]	; 0x2c
+ 8001230:	2380      	movs	r3, #128	; 0x80
+ 8001232:	025b      	lsls	r3, r3, #9
+ 8001234:	4013      	ands	r3, r2
+ 8001236:	d009      	beq.n	800124c <HAL_RCC_GetSysClockFreq+0x8c>
+      {
+        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+        pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
+ 8001238:	6ab9      	ldr	r1, [r7, #40]	; 0x28
+ 800123a:	4812      	ldr	r0, [pc, #72]	; (8001284 <HAL_RCC_GetSysClockFreq+0xc4>)
+ 800123c:	f7fe ff64 	bl	8000108 <__udivsi3>
+ 8001240:	0003      	movs	r3, r0
+ 8001242:	001a      	movs	r2, r3
+ 8001244:	6a7b      	ldr	r3, [r7, #36]	; 0x24
+ 8001246:	4353      	muls	r3, r2
+ 8001248:	637b      	str	r3, [r7, #52]	; 0x34
+ 800124a:	e009      	b.n	8001260 <HAL_RCC_GetSysClockFreq+0xa0>
+#if  (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
+        /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+        pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
+#else
+        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+        pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
+ 800124c:	6a79      	ldr	r1, [r7, #36]	; 0x24
+ 800124e:	000a      	movs	r2, r1
+ 8001250:	0152      	lsls	r2, r2, #5
+ 8001252:	1a52      	subs	r2, r2, r1
+ 8001254:	0193      	lsls	r3, r2, #6
+ 8001256:	1a9b      	subs	r3, r3, r2
+ 8001258:	00db      	lsls	r3, r3, #3
+ 800125a:	185b      	adds	r3, r3, r1
+ 800125c:	021b      	lsls	r3, r3, #8
+ 800125e:	637b      	str	r3, [r7, #52]	; 0x34
+#endif
+      }
+      sysclockfreq = pllclk;
+ 8001260:	6b7b      	ldr	r3, [r7, #52]	; 0x34
+ 8001262:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 8001264:	e002      	b.n	800126c <HAL_RCC_GetSysClockFreq+0xac>
+    }
+#endif /* RCC_CFGR_SWS_HSI48 */
+    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
+    default: /* HSI used as system clock */
+    {
+      sysclockfreq = HSI_VALUE;
+ 8001266:	4b07      	ldr	r3, [pc, #28]	; (8001284 <HAL_RCC_GetSysClockFreq+0xc4>)
+ 8001268:	633b      	str	r3, [r7, #48]	; 0x30
+      break;
+ 800126a:	46c0      	nop			; (mov r8, r8)
+    }
+  }
+  return sysclockfreq;
+ 800126c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
+}
+ 800126e:	0018      	movs	r0, r3
+ 8001270:	46bd      	mov	sp, r7
+ 8001272:	b00f      	add	sp, #60	; 0x3c
+ 8001274:	bd90      	pop	{r4, r7, pc}
+ 8001276:	46c0      	nop			; (mov r8, r8)
+ 8001278:	08001670 	.word	0x08001670
+ 800127c:	08001680 	.word	0x08001680
+ 8001280:	40021000 	.word	0x40021000
+ 8001284:	007a1200 	.word	0x007a1200
+
+08001288 <ds_in_or_out>:
+	char led_n:1;
+	char led_err:1;
+}dis_buff;
+
+void ds_in_or_out(char a)//change the io function
+{
+ 8001288:	b590      	push	{r4, r7, lr}
+ 800128a:	b089      	sub	sp, #36	; 0x24
+ 800128c:	af00      	add	r7, sp, #0
+ 800128e:	0002      	movs	r2, r0
+ 8001290:	1dfb      	adds	r3, r7, #7
+ 8001292:	701a      	strb	r2, [r3, #0]
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001294:	240c      	movs	r4, #12
+ 8001296:	193b      	adds	r3, r7, r4
+ 8001298:	0018      	movs	r0, r3
+ 800129a:	2314      	movs	r3, #20
+ 800129c:	001a      	movs	r2, r3
+ 800129e:	2100      	movs	r1, #0
+ 80012a0:	f000 f9d2 	bl	8001648 <memset>
+    GPIO_InitStruct.Pin = HC595_DLK_Pin;
+ 80012a4:	0021      	movs	r1, r4
+ 80012a6:	187b      	adds	r3, r7, r1
+ 80012a8:	2220      	movs	r2, #32
+ 80012aa:	601a      	str	r2, [r3, #0]
+
+		GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ 80012ac:	187b      	adds	r3, r7, r1
+ 80012ae:	2203      	movs	r2, #3
+ 80012b0:	60da      	str	r2, [r3, #12]
+    if(a==0)
+ 80012b2:	1dfb      	adds	r3, r7, #7
+ 80012b4:	781b      	ldrb	r3, [r3, #0]
+ 80012b6:	2b00      	cmp	r3, #0
+ 80012b8:	d105      	bne.n	80012c6 <ds_in_or_out+0x3e>
+    {
+				GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 80012ba:	187b      	adds	r3, r7, r1
+ 80012bc:	2201      	movs	r2, #1
+ 80012be:	609a      	str	r2, [r3, #8]
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 80012c0:	187b      	adds	r3, r7, r1
+ 80012c2:	2200      	movs	r2, #0
+ 80012c4:	605a      	str	r2, [r3, #4]
+    }
+    if(a==1)
+ 80012c6:	1dfb      	adds	r3, r7, #7
+ 80012c8:	781b      	ldrb	r3, [r3, #0]
+ 80012ca:	2b01      	cmp	r3, #1
+ 80012cc:	d106      	bne.n	80012dc <ds_in_or_out+0x54>
+    {
+				GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80012ce:	210c      	movs	r1, #12
+ 80012d0:	187b      	adds	r3, r7, r1
+ 80012d2:	2200      	movs	r2, #0
+ 80012d4:	609a      	str	r2, [r3, #8]
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 80012d6:	187b      	adds	r3, r7, r1
+ 80012d8:	2201      	movs	r2, #1
+ 80012da:	605a      	str	r2, [r3, #4]
+    }
+    HAL_GPIO_Init(HC595_DLK_GPIO_Port, &GPIO_InitStruct);
+ 80012dc:	230c      	movs	r3, #12
+ 80012de:	18fa      	adds	r2, r7, r3
+ 80012e0:	2390      	movs	r3, #144	; 0x90
+ 80012e2:	05db      	lsls	r3, r3, #23
+ 80012e4:	0011      	movs	r1, r2
+ 80012e6:	0018      	movs	r0, r3
+ 80012e8:	f7ff f9f4 	bl	80006d4 <HAL_GPIO_Init>
+}
+ 80012ec:	46c0      	nop			; (mov r8, r8)
+ 80012ee:	46bd      	mov	sp, r7
+ 80012f0:	b009      	add	sp, #36	; 0x24
+ 80012f2:	bd90      	pop	{r4, r7, pc}
+
+080012f4 <Sand_Byte_to_595>:
+{
+	ds_in_or_out(0);
+	if(READ_HC595_DCK){return 0;}else{return 1;}
+}
+void Sand_Byte_to_595(uint8_t h,uint8_t l)
+{
+ 80012f4:	b580      	push	{r7, lr}
+ 80012f6:	b084      	sub	sp, #16
+ 80012f8:	af00      	add	r7, sp, #0
+ 80012fa:	0002      	movs	r2, r0
+ 80012fc:	1dfb      	adds	r3, r7, #7
+ 80012fe:	701a      	strb	r2, [r3, #0]
+ 8001300:	1dbb      	adds	r3, r7, #6
+ 8001302:	1c0a      	adds	r2, r1, #0
+ 8001304:	701a      	strb	r2, [r3, #0]
+	ds_in_or_out(1);
+ 8001306:	2001      	movs	r0, #1
+ 8001308:	f7ff ffbe 	bl	8001288 <ds_in_or_out>
+	HC595_DCK(0);
+ 800130c:	2390      	movs	r3, #144	; 0x90
+ 800130e:	05db      	lsls	r3, r3, #23
+ 8001310:	2200      	movs	r2, #0
+ 8001312:	2120      	movs	r1, #32
+ 8001314:	0018      	movs	r0, r3
+ 8001316:	f7ff fb4d 	bl	80009b4 <HAL_GPIO_WritePin>
+	HC595_SCK(0);
+ 800131a:	2390      	movs	r3, #144	; 0x90
+ 800131c:	05db      	lsls	r3, r3, #23
+ 800131e:	2200      	movs	r2, #0
+ 8001320:	2140      	movs	r1, #64	; 0x40
+ 8001322:	0018      	movs	r0, r3
+ 8001324:	f7ff fb46 	bl	80009b4 <HAL_GPIO_WritePin>
+	HC595_RCK(0);
+ 8001328:	2390      	movs	r3, #144	; 0x90
+ 800132a:	05db      	lsls	r3, r3, #23
+ 800132c:	2200      	movs	r2, #0
+ 800132e:	2180      	movs	r1, #128	; 0x80
+ 8001330:	0018      	movs	r0, r3
+ 8001332:	f7ff fb3f 	bl	80009b4 <HAL_GPIO_WritePin>
+	for(char a=0;a<8;a++)
+ 8001336:	230f      	movs	r3, #15
+ 8001338:	18fb      	adds	r3, r7, r3
+ 800133a:	2200      	movs	r2, #0
+ 800133c:	701a      	strb	r2, [r3, #0]
+ 800133e:	e02c      	b.n	800139a <Sand_Byte_to_595+0xa6>
+	{
+		if((h<<a)&0x80)
+ 8001340:	1dfb      	adds	r3, r7, #7
+ 8001342:	781a      	ldrb	r2, [r3, #0]
+ 8001344:	230f      	movs	r3, #15
+ 8001346:	18fb      	adds	r3, r7, r3
+ 8001348:	781b      	ldrb	r3, [r3, #0]
+ 800134a:	409a      	lsls	r2, r3
+ 800134c:	0013      	movs	r3, r2
+ 800134e:	2280      	movs	r2, #128	; 0x80
+ 8001350:	4013      	ands	r3, r2
+ 8001352:	d007      	beq.n	8001364 <Sand_Byte_to_595+0x70>
+		{
+			HC595_DCK(1);
+ 8001354:	2390      	movs	r3, #144	; 0x90
+ 8001356:	05db      	lsls	r3, r3, #23
+ 8001358:	2201      	movs	r2, #1
+ 800135a:	2120      	movs	r1, #32
+ 800135c:	0018      	movs	r0, r3
+ 800135e:	f7ff fb29 	bl	80009b4 <HAL_GPIO_WritePin>
+ 8001362:	e006      	b.n	8001372 <Sand_Byte_to_595+0x7e>
+		}else
+		{
+			HC595_DCK(0);
+ 8001364:	2390      	movs	r3, #144	; 0x90
+ 8001366:	05db      	lsls	r3, r3, #23
+ 8001368:	2200      	movs	r2, #0
+ 800136a:	2120      	movs	r1, #32
+ 800136c:	0018      	movs	r0, r3
+ 800136e:	f7ff fb21 	bl	80009b4 <HAL_GPIO_WritePin>
+		}
+		HC595_SCK(1);
+ 8001372:	2390      	movs	r3, #144	; 0x90
+ 8001374:	05db      	lsls	r3, r3, #23
+ 8001376:	2201      	movs	r2, #1
+ 8001378:	2140      	movs	r1, #64	; 0x40
+ 800137a:	0018      	movs	r0, r3
+ 800137c:	f7ff fb1a 	bl	80009b4 <HAL_GPIO_WritePin>
+		HC595_SCK(0);
+ 8001380:	2390      	movs	r3, #144	; 0x90
+ 8001382:	05db      	lsls	r3, r3, #23
+ 8001384:	2200      	movs	r2, #0
+ 8001386:	2140      	movs	r1, #64	; 0x40
+ 8001388:	0018      	movs	r0, r3
+ 800138a:	f7ff fb13 	bl	80009b4 <HAL_GPIO_WritePin>
+	for(char a=0;a<8;a++)
+ 800138e:	210f      	movs	r1, #15
+ 8001390:	187b      	adds	r3, r7, r1
+ 8001392:	781a      	ldrb	r2, [r3, #0]
+ 8001394:	187b      	adds	r3, r7, r1
+ 8001396:	3201      	adds	r2, #1
+ 8001398:	701a      	strb	r2, [r3, #0]
+ 800139a:	230f      	movs	r3, #15
+ 800139c:	18fb      	adds	r3, r7, r3
+ 800139e:	781b      	ldrb	r3, [r3, #0]
+ 80013a0:	2b07      	cmp	r3, #7
+ 80013a2:	d9cd      	bls.n	8001340 <Sand_Byte_to_595+0x4c>
+	}
+	for(char a=0;a<8;a++)
+ 80013a4:	230e      	movs	r3, #14
+ 80013a6:	18fb      	adds	r3, r7, r3
+ 80013a8:	2200      	movs	r2, #0
+ 80013aa:	701a      	strb	r2, [r3, #0]
+ 80013ac:	e02c      	b.n	8001408 <Sand_Byte_to_595+0x114>
+	{
+		if((l<<a)&0x80)
+ 80013ae:	1dbb      	adds	r3, r7, #6
+ 80013b0:	781a      	ldrb	r2, [r3, #0]
+ 80013b2:	230e      	movs	r3, #14
+ 80013b4:	18fb      	adds	r3, r7, r3
+ 80013b6:	781b      	ldrb	r3, [r3, #0]
+ 80013b8:	409a      	lsls	r2, r3
+ 80013ba:	0013      	movs	r3, r2
+ 80013bc:	2280      	movs	r2, #128	; 0x80
+ 80013be:	4013      	ands	r3, r2
+ 80013c0:	d007      	beq.n	80013d2 <Sand_Byte_to_595+0xde>
+		{
+			HC595_DCK(1);
+ 80013c2:	2390      	movs	r3, #144	; 0x90
+ 80013c4:	05db      	lsls	r3, r3, #23
+ 80013c6:	2201      	movs	r2, #1
+ 80013c8:	2120      	movs	r1, #32
+ 80013ca:	0018      	movs	r0, r3
+ 80013cc:	f7ff faf2 	bl	80009b4 <HAL_GPIO_WritePin>
+ 80013d0:	e006      	b.n	80013e0 <Sand_Byte_to_595+0xec>
+		}else
+		{
+			HC595_DCK(0);
+ 80013d2:	2390      	movs	r3, #144	; 0x90
+ 80013d4:	05db      	lsls	r3, r3, #23
+ 80013d6:	2200      	movs	r2, #0
+ 80013d8:	2120      	movs	r1, #32
+ 80013da:	0018      	movs	r0, r3
+ 80013dc:	f7ff faea 	bl	80009b4 <HAL_GPIO_WritePin>
+		}
+		HC595_SCK(1);
+ 80013e0:	2390      	movs	r3, #144	; 0x90
+ 80013e2:	05db      	lsls	r3, r3, #23
+ 80013e4:	2201      	movs	r2, #1
+ 80013e6:	2140      	movs	r1, #64	; 0x40
+ 80013e8:	0018      	movs	r0, r3
+ 80013ea:	f7ff fae3 	bl	80009b4 <HAL_GPIO_WritePin>
+		HC595_SCK(0);
+ 80013ee:	2390      	movs	r3, #144	; 0x90
+ 80013f0:	05db      	lsls	r3, r3, #23
+ 80013f2:	2200      	movs	r2, #0
+ 80013f4:	2140      	movs	r1, #64	; 0x40
+ 80013f6:	0018      	movs	r0, r3
+ 80013f8:	f7ff fadc 	bl	80009b4 <HAL_GPIO_WritePin>
+	for(char a=0;a<8;a++)
+ 80013fc:	210e      	movs	r1, #14
+ 80013fe:	187b      	adds	r3, r7, r1
+ 8001400:	781a      	ldrb	r2, [r3, #0]
+ 8001402:	187b      	adds	r3, r7, r1
+ 8001404:	3201      	adds	r2, #1
+ 8001406:	701a      	strb	r2, [r3, #0]
+ 8001408:	230e      	movs	r3, #14
+ 800140a:	18fb      	adds	r3, r7, r3
+ 800140c:	781b      	ldrb	r3, [r3, #0]
+ 800140e:	2b07      	cmp	r3, #7
+ 8001410:	d9cd      	bls.n	80013ae <Sand_Byte_to_595+0xba>
+	}
+	HC595_RCK(1);
+ 8001412:	2390      	movs	r3, #144	; 0x90
+ 8001414:	05db      	lsls	r3, r3, #23
+ 8001416:	2201      	movs	r2, #1
+ 8001418:	2180      	movs	r1, #128	; 0x80
+ 800141a:	0018      	movs	r0, r3
+ 800141c:	f7ff faca 	bl	80009b4 <HAL_GPIO_WritePin>
+	HC595_RCK(0);
+ 8001420:	2390      	movs	r3, #144	; 0x90
+ 8001422:	05db      	lsls	r3, r3, #23
+ 8001424:	2200      	movs	r2, #0
+ 8001426:	2180      	movs	r1, #128	; 0x80
+ 8001428:	0018      	movs	r0, r3
+ 800142a:	f7ff fac3 	bl	80009b4 <HAL_GPIO_WritePin>
+}
+ 800142e:	46c0      	nop			; (mov r8, r8)
+ 8001430:	46bd      	mov	sp, r7
+ 8001432:	b004      	add	sp, #16
+ 8001434:	bd80      	pop	{r7, pc}
+	...
+
+08001438 <display_and_button_loop>:
+#define H 0x01
+
+const char num_com[4]={0x1,0x2,0x4,0x8};
+
+void display_and_button_loop()
+{
+ 8001438:	b580      	push	{r7, lr}
+ 800143a:	b084      	sub	sp, #16
+ 800143c:	af00      	add	r7, sp, #0
+	char lcd_buff[4];
+	char change_buff;
+	char h,l;
+	//fast time change 1
+
+	for(int a=0;a<4;a++)
+ 800143e:	2300      	movs	r3, #0
+ 8001440:	60fb      	str	r3, [r7, #12]
+ 8001442:	e090      	b.n	8001566 <display_and_button_loop+0x12e>
+	{
+		change_buff=d_num_data[dis_buff.d_num[a]];//num to data model
+ 8001444:	4a61      	ldr	r2, [pc, #388]	; (80015cc <display_and_button_loop+0x194>)
+ 8001446:	68fb      	ldr	r3, [r7, #12]
+ 8001448:	18d3      	adds	r3, r2, r3
+ 800144a:	781b      	ldrb	r3, [r3, #0]
+ 800144c:	0019      	movs	r1, r3
+ 800144e:	1d7b      	adds	r3, r7, #5
+ 8001450:	4a5f      	ldr	r2, [pc, #380]	; (80015d0 <display_and_button_loop+0x198>)
+ 8001452:	5c52      	ldrb	r2, [r2, r1]
+ 8001454:	701a      	strb	r2, [r3, #0]
+		if(change_buff&A)
+ 8001456:	1d7b      	adds	r3, r7, #5
+ 8001458:	781b      	ldrb	r3, [r3, #0]
+ 800145a:	b25b      	sxtb	r3, r3
+ 800145c:	2b00      	cmp	r3, #0
+ 800145e:	da0d      	bge.n	800147c <display_and_button_loop+0x44>
+		{
+			lcd_buff[0]|=0x80>>(a*2);
+ 8001460:	003b      	movs	r3, r7
+ 8001462:	781b      	ldrb	r3, [r3, #0]
+ 8001464:	b25a      	sxtb	r2, r3
+ 8001466:	68fb      	ldr	r3, [r7, #12]
+ 8001468:	005b      	lsls	r3, r3, #1
+ 800146a:	2180      	movs	r1, #128	; 0x80
+ 800146c:	4119      	asrs	r1, r3
+ 800146e:	000b      	movs	r3, r1
+ 8001470:	b25b      	sxtb	r3, r3
+ 8001472:	4313      	orrs	r3, r2
+ 8001474:	b25b      	sxtb	r3, r3
+ 8001476:	b2da      	uxtb	r2, r3
+ 8001478:	003b      	movs	r3, r7
+ 800147a:	701a      	strb	r2, [r3, #0]
+		}
+		if(change_buff&B)
+ 800147c:	1d7b      	adds	r3, r7, #5
+ 800147e:	781b      	ldrb	r3, [r3, #0]
+ 8001480:	2240      	movs	r2, #64	; 0x40
+ 8001482:	4013      	ands	r3, r2
+ 8001484:	d00d      	beq.n	80014a2 <display_and_button_loop+0x6a>
+		{
+			lcd_buff[0]|=0x40>>(a*2);
+ 8001486:	003b      	movs	r3, r7
+ 8001488:	781b      	ldrb	r3, [r3, #0]
+ 800148a:	b25a      	sxtb	r2, r3
+ 800148c:	68fb      	ldr	r3, [r7, #12]
+ 800148e:	005b      	lsls	r3, r3, #1
+ 8001490:	2140      	movs	r1, #64	; 0x40
+ 8001492:	4119      	asrs	r1, r3
+ 8001494:	000b      	movs	r3, r1
+ 8001496:	b25b      	sxtb	r3, r3
+ 8001498:	4313      	orrs	r3, r2
+ 800149a:	b25b      	sxtb	r3, r3
+ 800149c:	b2da      	uxtb	r2, r3
+ 800149e:	003b      	movs	r3, r7
+ 80014a0:	701a      	strb	r2, [r3, #0]
+		}
+		if(change_buff&C)
+ 80014a2:	1d7b      	adds	r3, r7, #5
+ 80014a4:	781b      	ldrb	r3, [r3, #0]
+ 80014a6:	2220      	movs	r2, #32
+ 80014a8:	4013      	ands	r3, r2
+ 80014aa:	d00d      	beq.n	80014c8 <display_and_button_loop+0x90>
+		{
+			lcd_buff[2]|=0x40>>(a*2);
+ 80014ac:	003b      	movs	r3, r7
+ 80014ae:	789b      	ldrb	r3, [r3, #2]
+ 80014b0:	b25a      	sxtb	r2, r3
+ 80014b2:	68fb      	ldr	r3, [r7, #12]
+ 80014b4:	005b      	lsls	r3, r3, #1
+ 80014b6:	2140      	movs	r1, #64	; 0x40
+ 80014b8:	4119      	asrs	r1, r3
+ 80014ba:	000b      	movs	r3, r1
+ 80014bc:	b25b      	sxtb	r3, r3
+ 80014be:	4313      	orrs	r3, r2
+ 80014c0:	b25b      	sxtb	r3, r3
+ 80014c2:	b2da      	uxtb	r2, r3
+ 80014c4:	003b      	movs	r3, r7
+ 80014c6:	709a      	strb	r2, [r3, #2]
+		}
+		if(change_buff&D)
+ 80014c8:	1d7b      	adds	r3, r7, #5
+ 80014ca:	781b      	ldrb	r3, [r3, #0]
+ 80014cc:	2210      	movs	r2, #16
+ 80014ce:	4013      	ands	r3, r2
+ 80014d0:	d00d      	beq.n	80014ee <display_and_button_loop+0xb6>
+		{
+			lcd_buff[3]|=0x40>>(a*2);
+ 80014d2:	003b      	movs	r3, r7
+ 80014d4:	78db      	ldrb	r3, [r3, #3]
+ 80014d6:	b25a      	sxtb	r2, r3
+ 80014d8:	68fb      	ldr	r3, [r7, #12]
+ 80014da:	005b      	lsls	r3, r3, #1
+ 80014dc:	2140      	movs	r1, #64	; 0x40
+ 80014de:	4119      	asrs	r1, r3
+ 80014e0:	000b      	movs	r3, r1
+ 80014e2:	b25b      	sxtb	r3, r3
+ 80014e4:	4313      	orrs	r3, r2
+ 80014e6:	b25b      	sxtb	r3, r3
+ 80014e8:	b2da      	uxtb	r2, r3
+ 80014ea:	003b      	movs	r3, r7
+ 80014ec:	70da      	strb	r2, [r3, #3]
+		}
+		if(change_buff&E)
+ 80014ee:	1d7b      	adds	r3, r7, #5
+ 80014f0:	781b      	ldrb	r3, [r3, #0]
+ 80014f2:	2208      	movs	r2, #8
+ 80014f4:	4013      	ands	r3, r2
+ 80014f6:	d00d      	beq.n	8001514 <display_and_button_loop+0xdc>
+		{
+			lcd_buff[2]|=0x80>>(a*2);
+ 80014f8:	003b      	movs	r3, r7
+ 80014fa:	789b      	ldrb	r3, [r3, #2]
+ 80014fc:	b25a      	sxtb	r2, r3
+ 80014fe:	68fb      	ldr	r3, [r7, #12]
+ 8001500:	005b      	lsls	r3, r3, #1
+ 8001502:	2180      	movs	r1, #128	; 0x80
+ 8001504:	4119      	asrs	r1, r3
+ 8001506:	000b      	movs	r3, r1
+ 8001508:	b25b      	sxtb	r3, r3
+ 800150a:	4313      	orrs	r3, r2
+ 800150c:	b25b      	sxtb	r3, r3
+ 800150e:	b2da      	uxtb	r2, r3
+ 8001510:	003b      	movs	r3, r7
+ 8001512:	709a      	strb	r2, [r3, #2]
+		}
+		if(change_buff&F)
+ 8001514:	1d7b      	adds	r3, r7, #5
+ 8001516:	781b      	ldrb	r3, [r3, #0]
+ 8001518:	2204      	movs	r2, #4
+ 800151a:	4013      	ands	r3, r2
+ 800151c:	d00d      	beq.n	800153a <display_and_button_loop+0x102>
+		{
+			lcd_buff[1]|=0x80>>(a*2);
+ 800151e:	003b      	movs	r3, r7
+ 8001520:	785b      	ldrb	r3, [r3, #1]
+ 8001522:	b25a      	sxtb	r2, r3
+ 8001524:	68fb      	ldr	r3, [r7, #12]
+ 8001526:	005b      	lsls	r3, r3, #1
+ 8001528:	2180      	movs	r1, #128	; 0x80
+ 800152a:	4119      	asrs	r1, r3
+ 800152c:	000b      	movs	r3, r1
+ 800152e:	b25b      	sxtb	r3, r3
+ 8001530:	4313      	orrs	r3, r2
+ 8001532:	b25b      	sxtb	r3, r3
+ 8001534:	b2da      	uxtb	r2, r3
+ 8001536:	003b      	movs	r3, r7
+ 8001538:	705a      	strb	r2, [r3, #1]
+		}
+		if(change_buff&G)
+ 800153a:	1d7b      	adds	r3, r7, #5
+ 800153c:	781b      	ldrb	r3, [r3, #0]
+ 800153e:	2202      	movs	r2, #2
+ 8001540:	4013      	ands	r3, r2
+ 8001542:	d00d      	beq.n	8001560 <display_and_button_loop+0x128>
+		{
+			lcd_buff[1]|=0x40>>(a*2);
+ 8001544:	003b      	movs	r3, r7
+ 8001546:	785b      	ldrb	r3, [r3, #1]
+ 8001548:	b25a      	sxtb	r2, r3
+ 800154a:	68fb      	ldr	r3, [r7, #12]
+ 800154c:	005b      	lsls	r3, r3, #1
+ 800154e:	2140      	movs	r1, #64	; 0x40
+ 8001550:	4119      	asrs	r1, r3
+ 8001552:	000b      	movs	r3, r1
+ 8001554:	b25b      	sxtb	r3, r3
+ 8001556:	4313      	orrs	r3, r2
+ 8001558:	b25b      	sxtb	r3, r3
+ 800155a:	b2da      	uxtb	r2, r3
+ 800155c:	003b      	movs	r3, r7
+ 800155e:	705a      	strb	r2, [r3, #1]
+	for(int a=0;a<4;a++)
+ 8001560:	68fb      	ldr	r3, [r7, #12]
+ 8001562:	3301      	adds	r3, #1
+ 8001564:	60fb      	str	r3, [r7, #12]
+ 8001566:	68fb      	ldr	r3, [r7, #12]
+ 8001568:	2b03      	cmp	r3, #3
+ 800156a:	dc00      	bgt.n	800156e <display_and_button_loop+0x136>
+ 800156c:	e76a      	b.n	8001444 <display_and_button_loop+0xc>
+	//Sand_Byte_to_595(0xff,0xff);
+	//Sand_Byte_to_595(~h,~l);
+	//Sand_Byte_to_595(0,0);
+	//Sand_Byte_to_595(0xff,0xff);
+
+	for(int a=0;a<4;a++)
+ 800156e:	2300      	movs	r3, #0
+ 8001570:	60bb      	str	r3, [r7, #8]
+ 8001572:	e023      	b.n	80015bc <display_and_button_loop+0x184>
+	{
+		l=lcd_buff[a];
+ 8001574:	1dfb      	adds	r3, r7, #7
+ 8001576:	0039      	movs	r1, r7
+ 8001578:	68ba      	ldr	r2, [r7, #8]
+ 800157a:	188a      	adds	r2, r1, r2
+ 800157c:	7812      	ldrb	r2, [r2, #0]
+ 800157e:	701a      	strb	r2, [r3, #0]
+		h=~num_com[a];
+ 8001580:	4a14      	ldr	r2, [pc, #80]	; (80015d4 <display_and_button_loop+0x19c>)
+ 8001582:	68bb      	ldr	r3, [r7, #8]
+ 8001584:	18d3      	adds	r3, r2, r3
+ 8001586:	781a      	ldrb	r2, [r3, #0]
+ 8001588:	1dbb      	adds	r3, r7, #6
+ 800158a:	43d2      	mvns	r2, r2
+ 800158c:	701a      	strb	r2, [r3, #0]
+		Sand_Byte_to_595(h,l);
+ 800158e:	1dfb      	adds	r3, r7, #7
+ 8001590:	781a      	ldrb	r2, [r3, #0]
+ 8001592:	1dbb      	adds	r3, r7, #6
+ 8001594:	781b      	ldrb	r3, [r3, #0]
+ 8001596:	0011      	movs	r1, r2
+ 8001598:	0018      	movs	r0, r3
+ 800159a:	f7ff feab 	bl	80012f4 <Sand_Byte_to_595>
+
+		Sand_Byte_to_595(~h,~l);
+ 800159e:	1dbb      	adds	r3, r7, #6
+ 80015a0:	781b      	ldrb	r3, [r3, #0]
+ 80015a2:	43db      	mvns	r3, r3
+ 80015a4:	b2da      	uxtb	r2, r3
+ 80015a6:	1dfb      	adds	r3, r7, #7
+ 80015a8:	781b      	ldrb	r3, [r3, #0]
+ 80015aa:	43db      	mvns	r3, r3
+ 80015ac:	b2db      	uxtb	r3, r3
+ 80015ae:	0019      	movs	r1, r3
+ 80015b0:	0010      	movs	r0, r2
+ 80015b2:	f7ff fe9f 	bl	80012f4 <Sand_Byte_to_595>
+	for(int a=0;a<4;a++)
+ 80015b6:	68bb      	ldr	r3, [r7, #8]
+ 80015b8:	3301      	adds	r3, #1
+ 80015ba:	60bb      	str	r3, [r7, #8]
+ 80015bc:	68bb      	ldr	r3, [r7, #8]
+ 80015be:	2b03      	cmp	r3, #3
+ 80015c0:	ddd8      	ble.n	8001574 <display_and_button_loop+0x13c>
+
+	}
+
+
+
+}
+ 80015c2:	46c0      	nop			; (mov r8, r8)
+ 80015c4:	46c0      	nop			; (mov r8, r8)
+ 80015c6:	46bd      	mov	sp, r7
+ 80015c8:	b004      	add	sp, #16
+ 80015ca:	bd80      	pop	{r7, pc}
+ 80015cc:	2000002c 	.word	0x2000002c
+ 80015d0:	080016a0 	.word	0x080016a0
+ 80015d4:	080016ac 	.word	0x080016ac
+
+080015d8 <my_code>:
+
+void my_code()
+{
+ 80015d8:	b580      	push	{r7, lr}
+ 80015da:	af00      	add	r7, sp, #0
+
+	dis_buff.d_num[0]=1;
+ 80015dc:	4b07      	ldr	r3, [pc, #28]	; (80015fc <my_code+0x24>)
+ 80015de:	2201      	movs	r2, #1
+ 80015e0:	701a      	strb	r2, [r3, #0]
+	dis_buff.d_num[1]=3;
+ 80015e2:	4b06      	ldr	r3, [pc, #24]	; (80015fc <my_code+0x24>)
+ 80015e4:	2203      	movs	r2, #3
+ 80015e6:	705a      	strb	r2, [r3, #1]
+	dis_buff.d_num[2]=0;
+ 80015e8:	4b04      	ldr	r3, [pc, #16]	; (80015fc <my_code+0x24>)
+ 80015ea:	2200      	movs	r2, #0
+ 80015ec:	709a      	strb	r2, [r3, #2]
+	dis_buff.d_num[3]=0;
+ 80015ee:	4b03      	ldr	r3, [pc, #12]	; (80015fc <my_code+0x24>)
+ 80015f0:	2200      	movs	r2, #0
+ 80015f2:	70da      	strb	r2, [r3, #3]
+
+	while(1)
+	{
+
+		display_and_button_loop();
+ 80015f4:	f7ff ff20 	bl	8001438 <display_and_button_loop>
+ 80015f8:	e7fc      	b.n	80015f4 <my_code+0x1c>
+ 80015fa:	46c0      	nop			; (mov r8, r8)
+ 80015fc:	2000002c 	.word	0x2000002c
+
+08001600 <__libc_init_array>:
+ 8001600:	b570      	push	{r4, r5, r6, lr}
+ 8001602:	2600      	movs	r6, #0
+ 8001604:	4d0c      	ldr	r5, [pc, #48]	; (8001638 <__libc_init_array+0x38>)
+ 8001606:	4c0d      	ldr	r4, [pc, #52]	; (800163c <__libc_init_array+0x3c>)
+ 8001608:	1b64      	subs	r4, r4, r5
+ 800160a:	10a4      	asrs	r4, r4, #2
+ 800160c:	42a6      	cmp	r6, r4
+ 800160e:	d109      	bne.n	8001624 <__libc_init_array+0x24>
+ 8001610:	2600      	movs	r6, #0
+ 8001612:	f000 f821 	bl	8001658 <_init>
+ 8001616:	4d0a      	ldr	r5, [pc, #40]	; (8001640 <__libc_init_array+0x40>)
+ 8001618:	4c0a      	ldr	r4, [pc, #40]	; (8001644 <__libc_init_array+0x44>)
+ 800161a:	1b64      	subs	r4, r4, r5
+ 800161c:	10a4      	asrs	r4, r4, #2
+ 800161e:	42a6      	cmp	r6, r4
+ 8001620:	d105      	bne.n	800162e <__libc_init_array+0x2e>
+ 8001622:	bd70      	pop	{r4, r5, r6, pc}
+ 8001624:	00b3      	lsls	r3, r6, #2
+ 8001626:	58eb      	ldr	r3, [r5, r3]
+ 8001628:	4798      	blx	r3
+ 800162a:	3601      	adds	r6, #1
+ 800162c:	e7ee      	b.n	800160c <__libc_init_array+0xc>
+ 800162e:	00b3      	lsls	r3, r6, #2
+ 8001630:	58eb      	ldr	r3, [r5, r3]
+ 8001632:	4798      	blx	r3
+ 8001634:	3601      	adds	r6, #1
+ 8001636:	e7f2      	b.n	800161e <__libc_init_array+0x1e>
+ 8001638:	080016b0 	.word	0x080016b0
+ 800163c:	080016b0 	.word	0x080016b0
+ 8001640:	080016b0 	.word	0x080016b0
+ 8001644:	080016b4 	.word	0x080016b4
+
+08001648 <memset>:
+ 8001648:	0003      	movs	r3, r0
+ 800164a:	1882      	adds	r2, r0, r2
+ 800164c:	4293      	cmp	r3, r2
+ 800164e:	d100      	bne.n	8001652 <memset+0xa>
+ 8001650:	4770      	bx	lr
+ 8001652:	7019      	strb	r1, [r3, #0]
+ 8001654:	3301      	adds	r3, #1
+ 8001656:	e7f9      	b.n	800164c <memset+0x4>
+
+08001658 <_init>:
+ 8001658:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 800165a:	46c0      	nop			; (mov r8, r8)
+ 800165c:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 800165e:	bc08      	pop	{r3}
+ 8001660:	469e      	mov	lr, r3
+ 8001662:	4770      	bx	lr
+
+08001664 <_fini>:
+ 8001664:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8001666:	46c0      	nop			; (mov r8, r8)
+ 8001668:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 800166a:	bc08      	pop	{r3}
+ 800166c:	469e      	mov	lr, r3
+ 800166e:	4770      	bx	lr
diff --git a/Debug/Motor_Controller2.map b/Debug/Motor_Controller2.map
new file mode 100644
index 0000000..4cf6dad
--- /dev/null
+++ b/Debug/Motor_Controller2.map
@@ -0,0 +1,2830 @@
+Archive member included to satisfy reference by file (symbol)
+
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o)
+                              ./Core/Src/syscalls.o (__errno)
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o)
+                              /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit)
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o)
+                              /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+                              /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array)
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+                              /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset)
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+                              ./Core/Src/system_stm32f0xx.o (__aeabi_uidiv)
+/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+                              /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+
+Allocating common symbols
+Common symbol       size              file
+
+uwTick              0x4               ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+pFlash              0x20              ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o
+dis_buff            0x5               ./my_software/my_code.o
+
+Discarded input sections
+
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+ .ARM.attributes
+                0x000000000000001e       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ .ARM.attributes
+                0x000000000000004a       0x2c ./Core/Src/main.o
+ .ARM.attributes
+                0x0000000000000076       0x2c ./Core/Src/stm32f0xx_hal_msp.o
+ .ARM.attributes
+                0x00000000000000a2       0x2c ./Core/Src/stm32f0xx_it.o
+ .ARM.attributes
+                0x00000000000000ce       0x2c ./Core/Src/system_stm32f0xx.o
+ .ARM.attributes
+                0x00000000000000fa       0x21 ./Core/Startup/startup_stm32f030f4px.o
+ .ARM.attributes
+                0x000000000000011b       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .ARM.attributes
+                0x0000000000000147       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .ARM.attributes
+                0x0000000000000173       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .ARM.attributes
+                0x000000000000019f       0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .ARM.attributes
+                0x00000000000001cb       0x2c ./my_software/my_code.o
+ .ARM.attributes
+                0x00000000000001f7       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ .ARM.attributes
+                0x0000000000000223       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ .ARM.attributes
+                0x000000000000024f       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .ARM.attributes
+                0x000000000000026d       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .ARM.attributes
+                0x000000000000028b       0x1e /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+OUTPUT(Motor_Controller2.elf elf32-littlearm)
+LOAD linker stubs
+LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc.a
+LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a
+LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+
+.debug_info     0x0000000000000000     0x2f23
+ .debug_info    0x0000000000000000      0x58d ./Core/Src/main.o
+ .debug_info    0x000000000000058d      0x27d ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_info    0x000000000000080a      0x1b3 ./Core/Src/stm32f0xx_it.o
+ .debug_info    0x00000000000009bd      0x2c3 ./Core/Src/system_stm32f0xx.o
+ .debug_info    0x0000000000000c80       0x22 ./Core/Startup/startup_stm32f030f4px.o
+ .debug_info    0x0000000000000ca2      0x6be ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_info    0x0000000000001360      0x7a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_info    0x0000000000001b00      0x6d3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_info    0x00000000000021d3      0x88d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_info    0x0000000000002a60      0x4c3 ./my_software/my_code.o
+
+.debug_abbrev   0x0000000000000000      0xfb6
+ .debug_abbrev  0x0000000000000000      0x1c4 ./Core/Src/main.o
+ .debug_abbrev  0x00000000000001c4      0x11d ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_abbrev  0x00000000000002e1       0xd2 ./Core/Src/stm32f0xx_it.o
+ .debug_abbrev  0x00000000000003b3      0x145 ./Core/Src/system_stm32f0xx.o
+ .debug_abbrev  0x00000000000004f8       0x12 ./Core/Startup/startup_stm32f030f4px.o
+ .debug_abbrev  0x000000000000050a      0x21e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_abbrev  0x0000000000000728      0x2a9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_abbrev  0x00000000000009d1      0x1e8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_abbrev  0x0000000000000bb9      0x23b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_abbrev  0x0000000000000df4      0x1c2 ./my_software/my_code.o
+
+.debug_aranges  0x0000000000000000      0x390
+ .debug_aranges
+                0x0000000000000000       0x38 ./Core/Src/main.o
+ .debug_aranges
+                0x0000000000000038       0x20 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_aranges
+                0x0000000000000058       0x40 ./Core/Src/stm32f0xx_it.o
+ .debug_aranges
+                0x0000000000000098       0x28 ./Core/Src/system_stm32f0xx.o
+ .debug_aranges
+                0x00000000000000c0       0x28 ./Core/Startup/startup_stm32f030f4px.o
+ .debug_aranges
+                0x00000000000000e8       0xd0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_aranges
+                0x00000000000001b8       0xc0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_aranges
+                0x0000000000000278       0x58 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_aranges
+                0x00000000000002d0       0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_aranges
+                0x0000000000000350       0x40 ./my_software/my_code.o
+
+.debug_ranges   0x0000000000000000      0x2f8
+ .debug_ranges  0x0000000000000000       0x28 ./Core/Src/main.o
+ .debug_ranges  0x0000000000000028       0x10 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_ranges  0x0000000000000038       0x30 ./Core/Src/stm32f0xx_it.o
+ .debug_ranges  0x0000000000000068       0x18 ./Core/Src/system_stm32f0xx.o
+ .debug_ranges  0x0000000000000080       0x20 ./Core/Startup/startup_stm32f030f4px.o
+ .debug_ranges  0x00000000000000a0       0xc0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_ranges  0x0000000000000160       0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_ranges  0x0000000000000210       0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_ranges  0x0000000000000258       0x70 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_ranges  0x00000000000002c8       0x30 ./my_software/my_code.o
+
+.debug_macro    0x0000000000000000     0xe10b
+ .debug_macro   0x0000000000000000      0x1b2 ./Core/Src/main.o
+ .debug_macro   0x00000000000001b2      0xa7e ./Core/Src/main.o
+ .debug_macro   0x0000000000000c30      0x127 ./Core/Src/main.o
+ .debug_macro   0x0000000000000d57       0x2e ./Core/Src/main.o
+ .debug_macro   0x0000000000000d85       0x22 ./Core/Src/main.o
+ .debug_macro   0x0000000000000da7       0x22 ./Core/Src/main.o
+ .debug_macro   0x0000000000000dc9       0x8e ./Core/Src/main.o
+ .debug_macro   0x0000000000000e57       0x51 ./Core/Src/main.o
+ .debug_macro   0x0000000000000ea8      0x103 ./Core/Src/main.o
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+ .debug_macro   0x00000000000011f4       0x1c ./Core/Src/main.o
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+ .debug_macro   0x0000000000001232       0xb5 ./Core/Src/main.o
+ .debug_macro   0x00000000000012e7      0x391 ./Core/Src/main.o
+ .debug_macro   0x0000000000001678     0x6e67 ./Core/Src/main.o
+ .debug_macro   0x00000000000084df       0x66 ./Core/Src/main.o
+ .debug_macro   0x0000000000008545     0x34a6 ./Core/Src/main.o
+ .debug_macro   0x000000000000b9eb      0x174 ./Core/Src/main.o
+ .debug_macro   0x000000000000bb5f       0x55 ./Core/Src/main.o
+ .debug_macro   0x000000000000bbb4      0x924 ./Core/Src/main.o
+ .debug_macro   0x000000000000c4d8       0xe5 ./Core/Src/main.o
+ .debug_macro   0x000000000000c5bd      0x1af ./Core/Src/main.o
+ .debug_macro   0x000000000000c76c       0xb3 ./Core/Src/main.o
+ .debug_macro   0x000000000000c81f      0x1a0 ./Core/Src/main.o
+ .debug_macro   0x000000000000c9bf      0x1ed ./Core/Src/main.o
+ .debug_macro   0x000000000000cbac       0x34 ./Core/Src/main.o
+ .debug_macro   0x000000000000cbe0       0x43 ./Core/Src/main.o
+ .debug_macro   0x000000000000cc23       0x28 ./Core/Src/main.o
+ .debug_macro   0x000000000000cc4b       0xb0 ./Core/Src/main.o
+ .debug_macro   0x000000000000ccfb      0x15a ./Core/Src/main.o
+ .debug_macro   0x000000000000ce55      0x22c ./Core/Src/main.o
+ .debug_macro   0x000000000000d081       0x61 ./Core/Src/main.o
+ .debug_macro   0x000000000000d0e2       0xa5 ./Core/Src/main.o
+ .debug_macro   0x000000000000d187       0x4c ./Core/Src/main.o
+ .debug_macro   0x000000000000d1d3       0x2b ./Core/Src/main.o
+ .debug_macro   0x000000000000d1fe       0xf1 ./Core/Src/main.o
+ .debug_macro   0x000000000000d2ef       0x88 ./Core/Src/main.o
+ .debug_macro   0x000000000000d377      0x1a8 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_macro   0x000000000000d51f      0x1b2 ./Core/Src/stm32f0xx_it.o
+ .debug_macro   0x000000000000d6d1      0x199 ./Core/Src/system_stm32f0xx.o
+ .debug_macro   0x000000000000d86a      0x1bd ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_macro   0x000000000000da27      0x199 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_macro   0x000000000000dbc0      0x1a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_macro   0x000000000000dd60      0x1ab ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_macro   0x000000000000df0b      0x200 ./my_software/my_code.o
+
+.debug_line     0x0000000000000000     0x505a
+ .debug_line    0x0000000000000000      0x7ba ./Core/Src/main.o
+ .debug_line    0x00000000000007ba      0x6af ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_line    0x0000000000000e69      0x713 ./Core/Src/stm32f0xx_it.o
+ .debug_line    0x000000000000157c      0x71e ./Core/Src/system_stm32f0xx.o
+ .debug_line    0x0000000000001c9a       0x89 ./Core/Startup/startup_stm32f030f4px.o
+ .debug_line    0x0000000000001d23      0x929 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_line    0x000000000000264c      0x9d5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_line    0x0000000000003021      0xaa6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_line    0x0000000000003ac7      0xd15 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_line    0x00000000000047dc      0x87e ./my_software/my_code.o
+
+.debug_str      0x0000000000000000    0x537f2
+ .debug_str     0x0000000000000000    0x52aae ./Core/Src/main.o
+                                      0x52d2b (size before relaxing)
+ .debug_str     0x0000000000052aae       0x2c ./Core/Src/stm32f0xx_hal_msp.o
+                                      0x52b1a (size before relaxing)
+ .debug_str     0x0000000000052ada       0x76 ./Core/Src/stm32f0xx_it.o
+                                      0x52b0a (size before relaxing)
+ .debug_str     0x0000000000052b50       0x5f ./Core/Src/system_stm32f0xx.o
+                                      0x5293d (size before relaxing)
+ .debug_str     0x0000000000052baf       0x36 ./Core/Startup/startup_stm32f030f4px.o
+                                         0x7c (size before relaxing)
+ .debug_str     0x0000000000052be5      0x413 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+                                      0x52e14 (size before relaxing)
+ .debug_str     0x0000000000052ff8      0x204 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+                                      0x52cc8 (size before relaxing)
+ .debug_str     0x00000000000531fc      0x156 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+                                      0x52b1c (size before relaxing)
+ .debug_str     0x0000000000053352      0x240 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+                                      0x52d47 (size before relaxing)
+ .debug_str     0x0000000000053592      0x260 ./my_software/my_code.o
+                                      0x52d81 (size before relaxing)
+
+.comment        0x0000000000000000       0x53
+ .comment       0x0000000000000000       0x53 ./Core/Src/main.o
+                                         0x54 (size before relaxing)
+ .comment       0x0000000000000053       0x54 ./Core/Src/stm32f0xx_hal_msp.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/stm32f0xx_it.o
+ .comment       0x0000000000000053       0x54 ./Core/Src/system_stm32f0xx.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .comment       0x0000000000000053       0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .comment       0x0000000000000053       0x54 ./my_software/my_code.o
+
+.debug_frame    0x0000000000000000      0xaa0
+ .debug_frame   0x0000000000000000       0x88 ./Core/Src/main.o
+ .debug_frame   0x0000000000000088       0x30 ./Core/Src/stm32f0xx_hal_msp.o
+ .debug_frame   0x00000000000000b8       0x9c ./Core/Src/stm32f0xx_it.o
+ .debug_frame   0x0000000000000154       0x4c ./Core/Src/system_stm32f0xx.o
+ .debug_frame   0x00000000000001a0      0x2a4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o
+ .debug_frame   0x0000000000000444      0x2a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o
+ .debug_frame   0x00000000000006e4      0x110 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o
+ .debug_frame   0x00000000000007f4      0x198 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o
+ .debug_frame   0x000000000000098c       0xa8 ./my_software/my_code.o
+ .debug_frame   0x0000000000000a34       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ .debug_frame   0x0000000000000a60       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ .debug_frame   0x0000000000000a80       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
diff --git a/Debug/makefile b/Debug/makefile
new file mode 100644
index 0000000..76e1bd7
--- /dev/null
+++ b/Debug/makefile
@@ -0,0 +1,101 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include my_software/subdir.mk
+-include Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk
+-include Core/Startup/subdir.mk
+-include Core/Src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_DEPS)),)
+-include $(S_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := Motor_Controller2
+BUILD_ARTIFACT_EXTENSION := elf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables 
+EXECUTABLES += \
+Motor_Controller2.elf \
+
+SIZE_OUTPUT += \
+default.size.stdout \
+
+OBJDUMP_LIST += \
+Motor_Controller2.list \
+
+OBJCOPY_BIN += \
+Motor_Controller2.bin \
+
+
+# All Target
+all: main-build
+
+# Main-build Target
+main-build: Motor_Controller2.elf secondary-outputs
+
+# Tool invocations
+Motor_Controller2.elf: $(OBJS) $(USER_OBJS) /Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/STM32F030F4PX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-gcc -o "Motor_Controller2.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0 -T"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/STM32F030F4PX_FLASH.ld" --specs=nosys.specs -Wl,-Map="Motor_Controller2.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-size  $(EXECUTABLES)
+	@echo 'Finished building: $@'
+	@echo ' '
+
+Motor_Controller2.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "Motor_Controller2.list"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+Motor_Controller2.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objcopy  -O binary $(EXECUTABLES) "Motor_Controller2.bin"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SIZE_OUTPUT)$(OBJDUMP_LIST)$(EXECUTABLES)$(OBJS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(OBJCOPY_BIN) Motor_Controller2.elf
+	-@echo ' '
+
+secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN)
+
+fail-specified-linker-script-missing:
+	@echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.'
+	@exit 2
+
+warn-no-linker-script-specified:
+	@echo 'Warning: No linker script specified. Check the linker settings in the build configuration.'
+
+.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified
+
+-include ../makefile.targets
diff --git a/Debug/my_software/my_code.d b/Debug/my_software/my_code.d
new file mode 100644
index 0000000..7fb8bb4
--- /dev/null
+++ b/Debug/my_software/my_code.d
@@ -0,0 +1,80 @@
+my_software/my_code.o: ../my_software/my_code.c ../my_software/my_code.h \
+ ../Core/Inc/main.h ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \
+ ../Core/Inc/stm32f0xx_hal_conf.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h \
+ ../Drivers/CMSIS/Include/core_cm0.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \
+ ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
+
+../my_software/my_code.h:
+
+../Core/Inc/main.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h:
+
+../Core/Inc/stm32f0xx_hal_conf.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h:
+
+../Drivers/CMSIS/Include/core_cm0.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h:
+
+../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h:
diff --git a/Debug/my_software/my_code.su b/Debug/my_software/my_code.su
new file mode 100644
index 0000000..54c939d
--- /dev/null
+++ b/Debug/my_software/my_code.su
@@ -0,0 +1,5 @@
+my_code.c:31:6:ds_in_or_out	48	static
+my_code.c:49:9:Read_Ds	8	static
+my_code.c:54:6:Sand_Byte_to_595	24	static
+my_code.c:99:6:display_and_button_loop	24	static
+my_code.c:162:6:my_code	8	static
diff --git a/Debug/my_software/subdir.mk b/Debug/my_software/subdir.mk
new file mode 100644
index 0000000..faa34e2
--- /dev/null
+++ b/Debug/my_software/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../my_software/my_code.c 
+
+OBJS += \
+./my_software/my_code.o 
+
+C_DEPS += \
+./my_software/my_code.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+my_software/%.o: ../my_software/%.c my_software/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F030x6 -c -I../Core/Inc -I"/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/my_software" -I../Drivers/STM32F0xx_HAL_Driver/Inc -I../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Debug/objects.list b/Debug/objects.list
new file mode 100644
index 0000000..06df9e6
--- /dev/null
+++ b/Debug/objects.list
@@ -0,0 +1,23 @@
+"./Core/Src/main.o"
+"./Core/Src/stm32f0xx_hal_msp.o"
+"./Core/Src/stm32f0xx_it.o"
+"./Core/Src/syscalls.o"
+"./Core/Src/sysmem.o"
+"./Core/Src/system_stm32f0xx.o"
+"./Core/Startup/startup_stm32f030f4px.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o"
+"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o"
+"./my_software/my_code.o"
diff --git a/Debug/objects.mk b/Debug/objects.mk
new file mode 100644
index 0000000..e12976d
--- /dev/null
+++ b/Debug/objects.mk
@@ -0,0 +1,9 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Debug/sources.mk b/Debug/sources.mk
new file mode 100644
index 0000000..f7431c9
--- /dev/null
+++ b/Debug/sources.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+ELF_SRCS := 
+OBJ_SRCS := 
+S_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+O_SRCS := 
+SIZE_OUTPUT := 
+OBJDUMP_LIST := 
+EXECUTABLES := 
+OBJS := 
+S_DEPS := 
+S_UPPER_DEPS := 
+C_DEPS := 
+OBJCOPY_BIN := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Core/Src \
+Core/Startup \
+Drivers/STM32F0xx_HAL_Driver/Src \
+my_software \
+
diff --git a/Motor_Controller2 Debug.cfg b/Motor_Controller2 Debug.cfg
new file mode 100644
index 0000000..1cbd87e
--- /dev/null
+++ b/Motor_Controller2 Debug.cfg	
@@ -0,0 +1,42 @@
+# This is an genericBoard board with a single STM32F030F4Px chip
+#
+# Generated by STM32CubeIDE
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
+
+source [find interface/stlink-dap.cfg]
+
+
+set WORKAREASIZE 0x1000
+
+transport select "dapdirect_swd"
+
+set CHIPNAME STM32F030F4Px
+set BOARDNAME genericBoard
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 8000
+
+# Reset configuration
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate connect_assert_srst
+set CONNECT_UNDER_RESET 1
+set CORE_RESET 0
+
+# ACCESS PORT NUMBER
+set AP_NUM 0
+# GDB PORT
+set GDB_PORT 3333
+
+
+
+# BCTM CPU variables
+
+source [find target/stm32f0x.cfg]
+
diff --git a/Motor_Controller2 Debug.launch b/Motor_Controller2 Debug.launch
new file mode 100644
index 0000000..c26569b
--- /dev/null
+++ b/Motor_Controller2 Debug.launch	
@@ -0,0 +1,93 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{&quot;fItems&quot;:[{&quot;fIsFromMainTab&quot;:true,&quot;fPath&quot;:&quot;Debug/Motor_Controller2.elf&quot;,&quot;fProjectName&quot;:&quot;Motor_Controller2&quot;,&quot;fPerformBuild&quot;:true,&quot;fDownload&quot;:true,&quot;fLoadSymbols&quot;:true}]}"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.CTI_ALLOW_HALT" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.CTI_SIGNAL_HALT" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_DEVICE_SHAREABLE_ALLOWED" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_INTERFACE" value="Swd"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_INTERFACE_FREQUENCY" value="8000000.0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_LOW_POWER_MODE_ALLOWED" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_RESET_MODE" value="connect_under_reset"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_STOP_WATCHDOG_THEN_HALTED_ALLOWED" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_GENERATOR_OPTION" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_NAME" value="&quot;${stm32cubeide_openocd_path}/openocd&quot;"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_OTHER_OPTIONS" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_SCRIPT" value="${ProjDirPath}/Motor_Controller2 Debug.cfg"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_SCRIPT_CHOICE" value="automated"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocdenable_rtos" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader_init" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/Users/wuwenfeng/STM32CubeIDE/workspace_1.7.0/Motor_Controller2/Debug/st-link_gdbserver_log.txt"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{&quot;fItems&quot;:[{&quot;fDisplayName&quot;:&quot;Reset&quot;,&quot;fIsSuppressible&quot;:false,&quot;fResetAttribute&quot;:&quot;Software system reset&quot;,&quot;fResetStrategies&quot;:[{&quot;fDisplayName&quot;:&quot;Software system reset&quot;,&quot;fLaunchAttribute&quot;:&quot;system_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Hardware reset&quot;,&quot;fLaunchAttribute&quot;:&quot;hardware_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset hardware\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Core reset&quot;,&quot;fLaunchAttribute&quot;:&quot;core_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset core\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;None&quot;,&quot;fLaunchAttribute&quot;:&quot;no_reset&quot;,&quot;fGdbCommands&quot;:[],&quot;fCmdOptions&quot;:[&quot;-g&quot;]}],&quot;fGdbCommandGroup&quot;:{&quot;name&quot;:&quot;Additional commands&quot;,&quot;commands&quot;:[]}}]}"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/Motor_Controller2.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Motor_Controller2"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1859796831"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/Motor_Controller2"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/my_software/my_code.c b/my_software/my_code.c
new file mode 100644
index 0000000..85929ab
--- /dev/null
+++ b/my_software/my_code.c
@@ -0,0 +1,175 @@
+/*
+ * my_code.c
+ *
+ *  Created on: Oct 2, 2021
+ *      Author: wuwenfeng
+ */
+#include "my_code.h"
+#define HC595_DCK(x)	HAL_GPIO_WritePin(HC595_DLK_GPIO_Port, HC595_DLK_Pin, x);
+#define HC595_RCK(x)	HAL_GPIO_WritePin(HC595_RLK_GPIO_Port, HC595_RLK_Pin, x);
+#define HC595_SCK(x)	HAL_GPIO_WritePin(HC595_SLK_GPIO_Port, HC595_SLK_Pin, x);
+#define HC595_SCK2(x)	HAL_GPIO_WritePin(HC595_SLK2_GPIO_Port, HC595_SLK2_Pin, x);
+#define READ_HC595_DCK  HAL_GPIO_ReadPin(HC595_DLK_GPIO_Port,HC595_DLK_Pin)
+const char d_num_data[10]=
+{
+	0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f
+
+};
+struct
+{
+	char d_num[4];
+	char dot1:1;
+	char dot2:1;
+	char dot3:1;
+	char dot4:1;
+	char led_run:1;
+	char led_p:1;
+	char led_n:1;
+	char led_err:1;
+}dis_buff;
+
+void ds_in_or_out(char a)//change the io function
+{
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+    GPIO_InitStruct.Pin = HC595_DLK_Pin;
+
+		GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    if(a==0)
+    {
+				GPIO_InitStruct.Pull = GPIO_PULLUP;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    }
+    if(a==1)
+    {
+				GPIO_InitStruct.Pull = GPIO_NOPULL;
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    }
+    HAL_GPIO_Init(HC595_DLK_GPIO_Port, &GPIO_InitStruct);
+}
+uint8_t Read_Ds()
+{
+	ds_in_or_out(0);
+	if(READ_HC595_DCK){return 0;}else{return 1;}
+}
+void Sand_Byte_to_595(uint8_t h,uint8_t l)
+{
+	ds_in_or_out(1);
+	HC595_DCK(0);
+	HC595_SCK(0);
+	HC595_RCK(0);
+	for(char a=0;a<8;a++)
+	{
+		if((h<<a)&0x80)
+		{
+			HC595_DCK(1);
+		}else
+		{
+			HC595_DCK(0);
+		}
+		HC595_SCK(1);
+		HC595_SCK(0);
+	}
+	for(char a=0;a<8;a++)
+	{
+		if((l<<a)&0x80)
+		{
+			HC595_DCK(1);
+		}else
+		{
+			HC595_DCK(0);
+		}
+		HC595_SCK(1);
+		HC595_SCK(0);
+	}
+	HC595_RCK(1);
+	HC595_RCK(0);
+}
+
+#define A 0x80
+#define B 0x40
+#define C 0x20
+#define D 0x10
+#define E 0x08
+#define F 0x04
+#define G 0x02
+#define H 0x01
+
+const char num_com[4]={0x1,0x2,0x4,0x8};
+
+void display_and_button_loop()
+{
+	//Sand_Byte_to_595(0x00,0xff);
+	//Sand_Byte_to_595(0xff,0x00);
+	char lcd_buff[4];
+	char change_buff;
+	char h,l;
+	//fast time change 1
+
+	for(int a=0;a<4;a++)
+	{
+		change_buff=d_num_data[dis_buff.d_num[a]];//num to data model
+		if(change_buff&A)
+		{
+			lcd_buff[0]|=0x80>>(a*2);
+		}
+		if(change_buff&B)
+		{
+			lcd_buff[0]|=0x40>>(a*2);
+		}
+		if(change_buff&C)
+		{
+			lcd_buff[2]|=0x40>>(a*2);
+		}
+		if(change_buff&D)
+		{
+			lcd_buff[3]|=0x40>>(a*2);
+		}
+		if(change_buff&E)
+		{
+			lcd_buff[2]|=0x80>>(a*2);
+		}
+		if(change_buff&F)
+		{
+			lcd_buff[1]|=0x80>>(a*2);
+		}
+		if(change_buff&G)
+		{
+			lcd_buff[1]|=0x40>>(a*2);
+		}
+	}
+
+
+
+	//Sand_Byte_to_595(0xff,0xff);
+	//Sand_Byte_to_595(~h,~l);
+	//Sand_Byte_to_595(0,0);
+	//Sand_Byte_to_595(0xff,0xff);
+
+	for(int a=0;a<4;a++)
+	{
+		l=lcd_buff[a];
+		h=~num_com[a];
+		Sand_Byte_to_595(h,l);
+
+		Sand_Byte_to_595(~h,~l);
+
+	}
+
+
+
+}
+
+void my_code()
+{
+
+	dis_buff.d_num[0]=1;
+	dis_buff.d_num[1]=3;
+	dis_buff.d_num[2]=0;
+	dis_buff.d_num[3]=0;
+
+	while(1)
+	{
+
+		display_and_button_loop();
+	}
+}
diff --git a/my_software/my_code.h b/my_software/my_code.h
new file mode 100644
index 0000000..4819008
--- /dev/null
+++ b/my_software/my_code.h
@@ -0,0 +1,14 @@
+/*
+ * my_code.h
+ *
+ *  Created on: Oct 2, 2021
+ *      Author: wuwenfeng
+ */
+
+#ifndef MY_CODE_H_
+#define MY_CODE_H_
+#include "main.h"
+void my_code();
+
+
+#endif /* MY_CODE_H_ */