Motor_Controller2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00003d58 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000060 08003e18 08003e18 00013e18 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08003e78 08003e78 0002000c 2**0 CONTENTS 4 .ARM 00000000 08003e78 08003e78 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 08003e78 08003e78 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08003e78 08003e78 00013e78 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08003e7c 08003e7c 00013e7c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 08003e80 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000154 2000000c 08003e8c 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000600 20000160 08003e8c 00020160 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 0000be50 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002278 00000000 00000000 0002be84 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000b88 00000000 00000000 0002e100 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000a50 00000000 00000000 0002ec88 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00010412 00000000 00000000 0002f6d8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000f206 00000000 00000000 0003faea 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0005f4b6 00000000 00000000 0004ecf0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 000ae1a6 2**0 CONTENTS, READONLY 20 .debug_frame 0000278c 00000000 00000000 000ae1fc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 2000000c .word 0x2000000c 80000e0: 00000000 .word 0x00000000 80000e4: 08003e00 .word 0x08003e00 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000010 .word 0x20000010 8000104: 08003e00 .word 0x08003e00 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__divsi3>: 800021c: 4603 mov r3, r0 800021e: 430b orrs r3, r1 8000220: d47f bmi.n 8000322 <__divsi3+0x106> 8000222: 2200 movs r2, #0 8000224: 0843 lsrs r3, r0, #1 8000226: 428b cmp r3, r1 8000228: d374 bcc.n 8000314 <__divsi3+0xf8> 800022a: 0903 lsrs r3, r0, #4 800022c: 428b cmp r3, r1 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4> 8000230: 0a03 lsrs r3, r0, #8 8000232: 428b cmp r3, r1 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4> 8000236: 0b03 lsrs r3, r0, #12 8000238: 428b cmp r3, r1 800023a: d328 bcc.n 800028e <__divsi3+0x72> 800023c: 0c03 lsrs r3, r0, #16 800023e: 428b cmp r3, r1 8000240: d30d bcc.n 800025e <__divsi3+0x42> 8000242: 22ff movs r2, #255 ; 0xff 8000244: 0209 lsls r1, r1, #8 8000246: ba12 rev r2, r2 8000248: 0c03 lsrs r3, r0, #16 800024a: 428b cmp r3, r1 800024c: d302 bcc.n 8000254 <__divsi3+0x38> 800024e: 1212 asrs r2, r2, #8 8000250: 0209 lsls r1, r1, #8 8000252: d065 beq.n 8000320 <__divsi3+0x104> 8000254: 0b03 lsrs r3, r0, #12 8000256: 428b cmp r3, r1 8000258: d319 bcc.n 800028e <__divsi3+0x72> 800025a: e000 b.n 800025e <__divsi3+0x42> 800025c: 0a09 lsrs r1, r1, #8 800025e: 0bc3 lsrs r3, r0, #15 8000260: 428b cmp r3, r1 8000262: d301 bcc.n 8000268 <__divsi3+0x4c> 8000264: 03cb lsls r3, r1, #15 8000266: 1ac0 subs r0, r0, r3 8000268: 4152 adcs r2, r2 800026a: 0b83 lsrs r3, r0, #14 800026c: 428b cmp r3, r1 800026e: d301 bcc.n 8000274 <__divsi3+0x58> 8000270: 038b lsls r3, r1, #14 8000272: 1ac0 subs r0, r0, r3 8000274: 4152 adcs r2, r2 8000276: 0b43 lsrs r3, r0, #13 8000278: 428b cmp r3, r1 800027a: d301 bcc.n 8000280 <__divsi3+0x64> 800027c: 034b lsls r3, r1, #13 800027e: 1ac0 subs r0, r0, r3 8000280: 4152 adcs r2, r2 8000282: 0b03 lsrs r3, r0, #12 8000284: 428b cmp r3, r1 8000286: d301 bcc.n 800028c <__divsi3+0x70> 8000288: 030b lsls r3, r1, #12 800028a: 1ac0 subs r0, r0, r3 800028c: 4152 adcs r2, r2 800028e: 0ac3 lsrs r3, r0, #11 8000290: 428b cmp r3, r1 8000292: d301 bcc.n 8000298 <__divsi3+0x7c> 8000294: 02cb lsls r3, r1, #11 8000296: 1ac0 subs r0, r0, r3 8000298: 4152 adcs r2, r2 800029a: 0a83 lsrs r3, r0, #10 800029c: 428b cmp r3, r1 800029e: d301 bcc.n 80002a4 <__divsi3+0x88> 80002a0: 028b lsls r3, r1, #10 80002a2: 1ac0 subs r0, r0, r3 80002a4: 4152 adcs r2, r2 80002a6: 0a43 lsrs r3, r0, #9 80002a8: 428b cmp r3, r1 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94> 80002ac: 024b lsls r3, r1, #9 80002ae: 1ac0 subs r0, r0, r3 80002b0: 4152 adcs r2, r2 80002b2: 0a03 lsrs r3, r0, #8 80002b4: 428b cmp r3, r1 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0> 80002b8: 020b lsls r3, r1, #8 80002ba: 1ac0 subs r0, r0, r3 80002bc: 4152 adcs r2, r2 80002be: d2cd bcs.n 800025c <__divsi3+0x40> 80002c0: 09c3 lsrs r3, r0, #7 80002c2: 428b cmp r3, r1 80002c4: d301 bcc.n 80002ca <__divsi3+0xae> 80002c6: 01cb lsls r3, r1, #7 80002c8: 1ac0 subs r0, r0, r3 80002ca: 4152 adcs r2, r2 80002cc: 0983 lsrs r3, r0, #6 80002ce: 428b cmp r3, r1 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba> 80002d2: 018b lsls r3, r1, #6 80002d4: 1ac0 subs r0, r0, r3 80002d6: 4152 adcs r2, r2 80002d8: 0943 lsrs r3, r0, #5 80002da: 428b cmp r3, r1 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6> 80002de: 014b lsls r3, r1, #5 80002e0: 1ac0 subs r0, r0, r3 80002e2: 4152 adcs r2, r2 80002e4: 0903 lsrs r3, r0, #4 80002e6: 428b cmp r3, r1 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2> 80002ea: 010b lsls r3, r1, #4 80002ec: 1ac0 subs r0, r0, r3 80002ee: 4152 adcs r2, r2 80002f0: 08c3 lsrs r3, r0, #3 80002f2: 428b cmp r3, r1 80002f4: d301 bcc.n 80002fa <__divsi3+0xde> 80002f6: 00cb lsls r3, r1, #3 80002f8: 1ac0 subs r0, r0, r3 80002fa: 4152 adcs r2, r2 80002fc: 0883 lsrs r3, r0, #2 80002fe: 428b cmp r3, r1 8000300: d301 bcc.n 8000306 <__divsi3+0xea> 8000302: 008b lsls r3, r1, #2 8000304: 1ac0 subs r0, r0, r3 8000306: 4152 adcs r2, r2 8000308: 0843 lsrs r3, r0, #1 800030a: 428b cmp r3, r1 800030c: d301 bcc.n 8000312 <__divsi3+0xf6> 800030e: 004b lsls r3, r1, #1 8000310: 1ac0 subs r0, r0, r3 8000312: 4152 adcs r2, r2 8000314: 1a41 subs r1, r0, r1 8000316: d200 bcs.n 800031a <__divsi3+0xfe> 8000318: 4601 mov r1, r0 800031a: 4152 adcs r2, r2 800031c: 4610 mov r0, r2 800031e: 4770 bx lr 8000320: e05d b.n 80003de <__divsi3+0x1c2> 8000322: 0fca lsrs r2, r1, #31 8000324: d000 beq.n 8000328 <__divsi3+0x10c> 8000326: 4249 negs r1, r1 8000328: 1003 asrs r3, r0, #32 800032a: d300 bcc.n 800032e <__divsi3+0x112> 800032c: 4240 negs r0, r0 800032e: 4053 eors r3, r2 8000330: 2200 movs r2, #0 8000332: 469c mov ip, r3 8000334: 0903 lsrs r3, r0, #4 8000336: 428b cmp r3, r1 8000338: d32d bcc.n 8000396 <__divsi3+0x17a> 800033a: 0a03 lsrs r3, r0, #8 800033c: 428b cmp r3, r1 800033e: d312 bcc.n 8000366 <__divsi3+0x14a> 8000340: 22fc movs r2, #252 ; 0xfc 8000342: 0189 lsls r1, r1, #6 8000344: ba12 rev r2, r2 8000346: 0a03 lsrs r3, r0, #8 8000348: 428b cmp r3, r1 800034a: d30c bcc.n 8000366 <__divsi3+0x14a> 800034c: 0189 lsls r1, r1, #6 800034e: 1192 asrs r2, r2, #6 8000350: 428b cmp r3, r1 8000352: d308 bcc.n 8000366 <__divsi3+0x14a> 8000354: 0189 lsls r1, r1, #6 8000356: 1192 asrs r2, r2, #6 8000358: 428b cmp r3, r1 800035a: d304 bcc.n 8000366 <__divsi3+0x14a> 800035c: 0189 lsls r1, r1, #6 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba> 8000360: 1192 asrs r2, r2, #6 8000362: e000 b.n 8000366 <__divsi3+0x14a> 8000364: 0989 lsrs r1, r1, #6 8000366: 09c3 lsrs r3, r0, #7 8000368: 428b cmp r3, r1 800036a: d301 bcc.n 8000370 <__divsi3+0x154> 800036c: 01cb lsls r3, r1, #7 800036e: 1ac0 subs r0, r0, r3 8000370: 4152 adcs r2, r2 8000372: 0983 lsrs r3, r0, #6 8000374: 428b cmp r3, r1 8000376: d301 bcc.n 800037c <__divsi3+0x160> 8000378: 018b lsls r3, r1, #6 800037a: 1ac0 subs r0, r0, r3 800037c: 4152 adcs r2, r2 800037e: 0943 lsrs r3, r0, #5 8000380: 428b cmp r3, r1 8000382: d301 bcc.n 8000388 <__divsi3+0x16c> 8000384: 014b lsls r3, r1, #5 8000386: 1ac0 subs r0, r0, r3 8000388: 4152 adcs r2, r2 800038a: 0903 lsrs r3, r0, #4 800038c: 428b cmp r3, r1 800038e: d301 bcc.n 8000394 <__divsi3+0x178> 8000390: 010b lsls r3, r1, #4 8000392: 1ac0 subs r0, r0, r3 8000394: 4152 adcs r2, r2 8000396: 08c3 lsrs r3, r0, #3 8000398: 428b cmp r3, r1 800039a: d301 bcc.n 80003a0 <__divsi3+0x184> 800039c: 00cb lsls r3, r1, #3 800039e: 1ac0 subs r0, r0, r3 80003a0: 4152 adcs r2, r2 80003a2: 0883 lsrs r3, r0, #2 80003a4: 428b cmp r3, r1 80003a6: d301 bcc.n 80003ac <__divsi3+0x190> 80003a8: 008b lsls r3, r1, #2 80003aa: 1ac0 subs r0, r0, r3 80003ac: 4152 adcs r2, r2 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148> 80003b0: 0843 lsrs r3, r0, #1 80003b2: 428b cmp r3, r1 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e> 80003b6: 004b lsls r3, r1, #1 80003b8: 1ac0 subs r0, r0, r3 80003ba: 4152 adcs r2, r2 80003bc: 1a41 subs r1, r0, r1 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6> 80003c0: 4601 mov r1, r0 80003c2: 4663 mov r3, ip 80003c4: 4152 adcs r2, r2 80003c6: 105b asrs r3, r3, #1 80003c8: 4610 mov r0, r2 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4> 80003cc: 4240 negs r0, r0 80003ce: 2b00 cmp r3, #0 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8> 80003d2: 4249 negs r1, r1 80003d4: 4770 bx lr 80003d6: 4663 mov r3, ip 80003d8: 105b asrs r3, r3, #1 80003da: d300 bcc.n 80003de <__divsi3+0x1c2> 80003dc: 4240 negs r0, r0 80003de: b501 push {r0, lr} 80003e0: 2000 movs r0, #0 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0> 80003e6: bd02 pop {r1, pc} 080003e8 <__aeabi_idivmod>: 80003e8: 2900 cmp r1, #0 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2> 80003ec: e716 b.n 800021c <__divsi3> 80003ee: 4770 bx lr 080003f0 <__aeabi_idiv0>: 80003f0: 4770 bx lr 80003f2: 46c0 nop ; (mov r8, r8) 080003f4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003f4: b580 push {r7, lr} 80003f6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80003f8: f000 faac bl 8000954 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80003fc: f000 f809 bl 8000412 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000400: f000 f8e4 bl 80005cc MX_ADC_Init(); 8000404: f000 f856 bl 80004b4 MX_TIM14_Init(); 8000408: f000 f8bc bl 8000584 /* USER CODE BEGIN 2 */ my_code(); 800040c: f002 ff72 bl 80032f4 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000410: e7fe b.n 8000410 08000412 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000412: b590 push {r4, r7, lr} 8000414: b091 sub sp, #68 ; 0x44 8000416: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000418: 2410 movs r4, #16 800041a: 193b adds r3, r7, r4 800041c: 0018 movs r0, r3 800041e: 2330 movs r3, #48 ; 0x30 8000420: 001a movs r2, r3 8000422: 2100 movs r1, #0 8000424: f003 fce4 bl 8003df0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000428: 003b movs r3, r7 800042a: 0018 movs r0, r3 800042c: 2310 movs r3, #16 800042e: 001a movs r2, r3 8000430: 2100 movs r1, #0 8000432: f003 fcdd bl 8003df0 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14; 8000436: 0021 movs r1, r4 8000438: 187b adds r3, r7, r1 800043a: 2212 movs r2, #18 800043c: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800043e: 187b adds r3, r7, r1 8000440: 2201 movs r2, #1 8000442: 60da str r2, [r3, #12] RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 8000444: 187b adds r3, r7, r1 8000446: 2201 movs r2, #1 8000448: 615a str r2, [r3, #20] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800044a: 187b adds r3, r7, r1 800044c: 2210 movs r2, #16 800044e: 611a str r2, [r3, #16] RCC_OscInitStruct.HSI14CalibrationValue = 16; 8000450: 187b adds r3, r7, r1 8000452: 2210 movs r2, #16 8000454: 619a str r2, [r3, #24] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000456: 187b adds r3, r7, r1 8000458: 2202 movs r2, #2 800045a: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 800045c: 187b adds r3, r7, r1 800045e: 2200 movs r2, #0 8000460: 625a str r2, [r3, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; 8000462: 187b adds r3, r7, r1 8000464: 22a0 movs r2, #160 ; 0xa0 8000466: 0392 lsls r2, r2, #14 8000468: 629a str r2, [r3, #40] ; 0x28 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; 800046a: 187b adds r3, r7, r1 800046c: 2200 movs r2, #0 800046e: 62da str r2, [r3, #44] ; 0x2c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000470: 187b adds r3, r7, r1 8000472: 0018 movs r0, r3 8000474: f001 fa44 bl 8001900 8000478: 1e03 subs r3, r0, #0 800047a: d001 beq.n 8000480 { Error_Handler(); 800047c: f000 f976 bl 800076c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000480: 003b movs r3, r7 8000482: 2207 movs r2, #7 8000484: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000486: 003b movs r3, r7 8000488: 2202 movs r2, #2 800048a: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800048c: 003b movs r3, r7 800048e: 2200 movs r2, #0 8000490: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000492: 003b movs r3, r7 8000494: 2200 movs r2, #0 8000496: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000498: 003b movs r3, r7 800049a: 2101 movs r1, #1 800049c: 0018 movs r0, r3 800049e: f001 fd49 bl 8001f34 80004a2: 1e03 subs r3, r0, #0 80004a4: d001 beq.n 80004aa { Error_Handler(); 80004a6: f000 f961 bl 800076c } } 80004aa: 46c0 nop ; (mov r8, r8) 80004ac: 46bd mov sp, r7 80004ae: b011 add sp, #68 ; 0x44 80004b0: bd90 pop {r4, r7, pc} ... 080004b4 : * @brief ADC Initialization Function * @param None * @retval None */ static void MX_ADC_Init(void) { 80004b4: b580 push {r7, lr} 80004b6: b084 sub sp, #16 80004b8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC_Init 0 */ /* USER CODE END ADC_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80004ba: 1d3b adds r3, r7, #4 80004bc: 0018 movs r0, r3 80004be: 230c movs r3, #12 80004c0: 001a movs r2, r3 80004c2: 2100 movs r1, #0 80004c4: f003 fc94 bl 8003df0 /* USER CODE BEGIN ADC_Init 1 */ /* USER CODE END ADC_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc.Instance = ADC1; 80004c8: 4b2c ldr r3, [pc, #176] ; (800057c ) 80004ca: 4a2d ldr r2, [pc, #180] ; (8000580 ) 80004cc: 601a str r2, [r3, #0] hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80004ce: 4b2b ldr r3, [pc, #172] ; (800057c ) 80004d0: 2200 movs r2, #0 80004d2: 605a str r2, [r3, #4] hadc.Init.Resolution = ADC_RESOLUTION_12B; 80004d4: 4b29 ldr r3, [pc, #164] ; (800057c ) 80004d6: 2200 movs r2, #0 80004d8: 609a str r2, [r3, #8] hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80004da: 4b28 ldr r3, [pc, #160] ; (800057c ) 80004dc: 2200 movs r2, #0 80004de: 60da str r2, [r3, #12] hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 80004e0: 4b26 ldr r3, [pc, #152] ; (800057c ) 80004e2: 2201 movs r2, #1 80004e4: 611a str r2, [r3, #16] hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80004e6: 4b25 ldr r3, [pc, #148] ; (800057c ) 80004e8: 2204 movs r2, #4 80004ea: 615a str r2, [r3, #20] hadc.Init.LowPowerAutoWait = DISABLE; 80004ec: 4b23 ldr r3, [pc, #140] ; (800057c ) 80004ee: 2200 movs r2, #0 80004f0: 761a strb r2, [r3, #24] hadc.Init.LowPowerAutoPowerOff = DISABLE; 80004f2: 4b22 ldr r3, [pc, #136] ; (800057c ) 80004f4: 2200 movs r2, #0 80004f6: 765a strb r2, [r3, #25] hadc.Init.ContinuousConvMode = DISABLE; 80004f8: 4b20 ldr r3, [pc, #128] ; (800057c ) 80004fa: 2200 movs r2, #0 80004fc: 769a strb r2, [r3, #26] hadc.Init.DiscontinuousConvMode = DISABLE; 80004fe: 4b1f ldr r3, [pc, #124] ; (800057c ) 8000500: 2200 movs r2, #0 8000502: 76da strb r2, [r3, #27] hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000504: 4b1d ldr r3, [pc, #116] ; (800057c ) 8000506: 22c2 movs r2, #194 ; 0xc2 8000508: 32ff adds r2, #255 ; 0xff 800050a: 61da str r2, [r3, #28] hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 800050c: 4b1b ldr r3, [pc, #108] ; (800057c ) 800050e: 2200 movs r2, #0 8000510: 621a str r2, [r3, #32] hadc.Init.DMAContinuousRequests = DISABLE; 8000512: 4b1a ldr r3, [pc, #104] ; (800057c ) 8000514: 2224 movs r2, #36 ; 0x24 8000516: 2100 movs r1, #0 8000518: 5499 strb r1, [r3, r2] hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 800051a: 4b18 ldr r3, [pc, #96] ; (800057c ) 800051c: 2201 movs r2, #1 800051e: 629a str r2, [r3, #40] ; 0x28 if (HAL_ADC_Init(&hadc) != HAL_OK) 8000520: 4b16 ldr r3, [pc, #88] ; (800057c ) 8000522: 0018 movs r0, r3 8000524: f000 fa7a bl 8000a1c 8000528: 1e03 subs r3, r0, #0 800052a: d001 beq.n 8000530 { Error_Handler(); 800052c: f000 f91e bl 800076c } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_0; 8000530: 1d3b adds r3, r7, #4 8000532: 2200 movs r2, #0 8000534: 601a str r2, [r3, #0] sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 8000536: 1d3b adds r3, r7, #4 8000538: 2280 movs r2, #128 ; 0x80 800053a: 0152 lsls r2, r2, #5 800053c: 605a str r2, [r3, #4] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800053e: 1d3b adds r3, r7, #4 8000540: 2280 movs r2, #128 ; 0x80 8000542: 0552 lsls r2, r2, #21 8000544: 609a str r2, [r3, #8] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000546: 1d3a adds r2, r7, #4 8000548: 4b0c ldr r3, [pc, #48] ; (800057c ) 800054a: 0011 movs r1, r2 800054c: 0018 movs r0, r3 800054e: f000 fcdd bl 8000f0c 8000552: 1e03 subs r3, r0, #0 8000554: d001 beq.n 800055a { Error_Handler(); 8000556: f000 f909 bl 800076c } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_1; 800055a: 1d3b adds r3, r7, #4 800055c: 2201 movs r2, #1 800055e: 601a str r2, [r3, #0] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000560: 1d3a adds r2, r7, #4 8000562: 4b06 ldr r3, [pc, #24] ; (800057c ) 8000564: 0011 movs r1, r2 8000566: 0018 movs r0, r3 8000568: f000 fcd0 bl 8000f0c 800056c: 1e03 subs r3, r0, #0 800056e: d001 beq.n 8000574 { Error_Handler(); 8000570: f000 f8fc bl 800076c } /* USER CODE BEGIN ADC_Init 2 */ /* USER CODE END ADC_Init 2 */ } 8000574: 46c0 nop ; (mov r8, r8) 8000576: 46bd mov sp, r7 8000578: b004 add sp, #16 800057a: bd80 pop {r7, pc} 800057c: 20000094 .word 0x20000094 8000580: 40012400 .word 0x40012400 08000584 : * @brief TIM14 Initialization Function * @param None * @retval None */ static void MX_TIM14_Init(void) { 8000584: b580 push {r7, lr} 8000586: af00 add r7, sp, #0 /* USER CODE END TIM14_Init 0 */ /* USER CODE BEGIN TIM14_Init 1 */ /* USER CODE END TIM14_Init 1 */ htim14.Instance = TIM14; 8000588: 4b0e ldr r3, [pc, #56] ; (80005c4 ) 800058a: 4a0f ldr r2, [pc, #60] ; (80005c8 ) 800058c: 601a str r2, [r3, #0] htim14.Init.Prescaler = 48-1; 800058e: 4b0d ldr r3, [pc, #52] ; (80005c4 ) 8000590: 222f movs r2, #47 ; 0x2f 8000592: 605a str r2, [r3, #4] htim14.Init.CounterMode = TIM_COUNTERMODE_UP; 8000594: 4b0b ldr r3, [pc, #44] ; (80005c4 ) 8000596: 2200 movs r2, #0 8000598: 609a str r2, [r3, #8] htim14.Init.Period = 100-1; 800059a: 4b0a ldr r3, [pc, #40] ; (80005c4 ) 800059c: 2263 movs r2, #99 ; 0x63 800059e: 60da str r2, [r3, #12] htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80005a0: 4b08 ldr r3, [pc, #32] ; (80005c4 ) 80005a2: 2200 movs r2, #0 80005a4: 611a str r2, [r3, #16] htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80005a6: 4b07 ldr r3, [pc, #28] ; (80005c4 ) 80005a8: 2200 movs r2, #0 80005aa: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim14) != HAL_OK) 80005ac: 4b05 ldr r3, [pc, #20] ; (80005c4 ) 80005ae: 0018 movs r0, r3 80005b0: f001 fdf2 bl 8002198 80005b4: 1e03 subs r3, r0, #0 80005b6: d001 beq.n 80005bc { Error_Handler(); 80005b8: f000 f8d8 bl 800076c } /* USER CODE BEGIN TIM14_Init 2 */ /* USER CODE END TIM14_Init 2 */ } 80005bc: 46c0 nop ; (mov r8, r8) 80005be: 46bd mov sp, r7 80005c0: bd80 pop {r7, pc} 80005c2: 46c0 nop ; (mov r8, r8) 80005c4: 2000004c .word 0x2000004c 80005c8: 40002000 .word 0x40002000 080005cc : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80005cc: b590 push {r4, r7, lr} 80005ce: b089 sub sp, #36 ; 0x24 80005d0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80005d2: 240c movs r4, #12 80005d4: 193b adds r3, r7, r4 80005d6: 0018 movs r0, r3 80005d8: 2314 movs r3, #20 80005da: 001a movs r2, r3 80005dc: 2100 movs r1, #0 80005de: f003 fc07 bl 8003df0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80005e2: 4b5f ldr r3, [pc, #380] ; (8000760 ) 80005e4: 695a ldr r2, [r3, #20] 80005e6: 4b5e ldr r3, [pc, #376] ; (8000760 ) 80005e8: 2180 movs r1, #128 ; 0x80 80005ea: 03c9 lsls r1, r1, #15 80005ec: 430a orrs r2, r1 80005ee: 615a str r2, [r3, #20] 80005f0: 4b5b ldr r3, [pc, #364] ; (8000760 ) 80005f2: 695a ldr r2, [r3, #20] 80005f4: 2380 movs r3, #128 ; 0x80 80005f6: 03db lsls r3, r3, #15 80005f8: 4013 ands r3, r2 80005fa: 60bb str r3, [r7, #8] 80005fc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80005fe: 4b58 ldr r3, [pc, #352] ; (8000760 ) 8000600: 695a ldr r2, [r3, #20] 8000602: 4b57 ldr r3, [pc, #348] ; (8000760 ) 8000604: 2180 movs r1, #128 ; 0x80 8000606: 0289 lsls r1, r1, #10 8000608: 430a orrs r2, r1 800060a: 615a str r2, [r3, #20] 800060c: 4b54 ldr r3, [pc, #336] ; (8000760 ) 800060e: 695a ldr r2, [r3, #20] 8000610: 2380 movs r3, #128 ; 0x80 8000612: 029b lsls r3, r3, #10 8000614: 4013 ands r3, r2 8000616: 607b str r3, [r7, #4] 8000618: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 800061a: 4b51 ldr r3, [pc, #324] ; (8000760 ) 800061c: 695a ldr r2, [r3, #20] 800061e: 4b50 ldr r3, [pc, #320] ; (8000760 ) 8000620: 2180 movs r1, #128 ; 0x80 8000622: 02c9 lsls r1, r1, #11 8000624: 430a orrs r2, r1 8000626: 615a str r2, [r3, #20] 8000628: 4b4d ldr r3, [pc, #308] ; (8000760 ) 800062a: 695a ldr r2, [r3, #20] 800062c: 2380 movs r3, #128 ; 0x80 800062e: 02db lsls r3, r3, #11 8000630: 4013 ands r3, r2 8000632: 603b str r3, [r7, #0] 8000634: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin 8000636: 23b9 movs r3, #185 ; 0xb9 8000638: 0099 lsls r1, r3, #2 800063a: 2390 movs r3, #144 ; 0x90 800063c: 05db lsls r3, r3, #23 800063e: 2200 movs r2, #0 8000640: 0018 movs r0, r3 8000642: f001 f906 bl 8001852 |HC595_SLK2_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(iic_sda_GPIO_Port, iic_sda_Pin, GPIO_PIN_SET); 8000646: 4b47 ldr r3, [pc, #284] ; (8000764 ) 8000648: 2201 movs r2, #1 800064a: 2102 movs r1, #2 800064c: 0018 movs r0, r3 800064e: f001 f900 bl 8001852 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(iic_scl_GPIO_Port, iic_scl_Pin, GPIO_PIN_SET); 8000652: 2380 movs r3, #128 ; 0x80 8000654: 00d9 lsls r1, r3, #3 8000656: 2390 movs r3, #144 ; 0x90 8000658: 05db lsls r3, r3, #23 800065a: 2201 movs r2, #1 800065c: 0018 movs r0, r3 800065e: f001 f8f8 bl 8001852 /*Configure GPIO pins : MOT_IN1_Pin MOT_IN2_Pin */ GPIO_InitStruct.Pin = MOT_IN1_Pin|MOT_IN2_Pin; 8000662: 193b adds r3, r7, r4 8000664: 2203 movs r2, #3 8000666: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000668: 193b adds r3, r7, r4 800066a: 2200 movs r2, #0 800066c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800066e: 193b adds r3, r7, r4 8000670: 2202 movs r2, #2 8000672: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8000674: 193b adds r3, r7, r4 8000676: 4a3c ldr r2, [pc, #240] ; (8000768 ) 8000678: 0019 movs r1, r3 800067a: 0010 movs r0, r2 800067c: f000 ff5c bl 8001538 /*Configure GPIO pins : U_T_Pin HC595_DLK_Pin HC595_SLK_Pin HC595_RLK_Pin HC595_SLK2_Pin */ GPIO_InitStruct.Pin = U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin 8000680: 0021 movs r1, r4 8000682: 187b adds r3, r7, r1 8000684: 22b9 movs r2, #185 ; 0xb9 8000686: 0092 lsls r2, r2, #2 8000688: 601a str r2, [r3, #0] |HC595_SLK2_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800068a: 000c movs r4, r1 800068c: 193b adds r3, r7, r4 800068e: 2201 movs r2, #1 8000690: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 8000692: 193b adds r3, r7, r4 8000694: 2202 movs r2, #2 8000696: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000698: 193b adds r3, r7, r4 800069a: 2203 movs r2, #3 800069c: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800069e: 193a adds r2, r7, r4 80006a0: 2390 movs r3, #144 ; 0x90 80006a2: 05db lsls r3, r3, #23 80006a4: 0011 movs r1, r2 80006a6: 0018 movs r0, r3 80006a8: f000 ff46 bl 8001538 /*Configure GPIO pin : infeaed_Pin */ GPIO_InitStruct.Pin = infeaed_Pin; 80006ac: 193b adds r3, r7, r4 80006ae: 2208 movs r2, #8 80006b0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80006b2: 193b adds r3, r7, r4 80006b4: 22c4 movs r2, #196 ; 0xc4 80006b6: 0392 lsls r2, r2, #14 80006b8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006ba: 193b adds r3, r7, r4 80006bc: 2201 movs r2, #1 80006be: 609a str r2, [r3, #8] HAL_GPIO_Init(infeaed_GPIO_Port, &GPIO_InitStruct); 80006c0: 193a adds r2, r7, r4 80006c2: 2390 movs r3, #144 ; 0x90 80006c4: 05db lsls r3, r3, #23 80006c6: 0011 movs r1, r2 80006c8: 0018 movs r0, r3 80006ca: f000 ff35 bl 8001538 /*Configure GPIO pin : I_R_Pin */ GPIO_InitStruct.Pin = I_R_Pin; 80006ce: 193b adds r3, r7, r4 80006d0: 2210 movs r2, #16 80006d2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 193b adds r3, r7, r4 80006d6: 2200 movs r2, #0 80006d8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006da: 193b adds r3, r7, r4 80006dc: 2202 movs r2, #2 80006de: 609a str r2, [r3, #8] HAL_GPIO_Init(I_R_GPIO_Port, &GPIO_InitStruct); 80006e0: 193a adds r2, r7, r4 80006e2: 2390 movs r3, #144 ; 0x90 80006e4: 05db lsls r3, r3, #23 80006e6: 0011 movs r1, r2 80006e8: 0018 movs r0, r3 80006ea: f000 ff25 bl 8001538 /*Configure GPIO pin : iic_sda_Pin */ GPIO_InitStruct.Pin = iic_sda_Pin; 80006ee: 193b adds r3, r7, r4 80006f0: 2202 movs r2, #2 80006f2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006f4: 193b adds r3, r7, r4 80006f6: 2201 movs r2, #1 80006f8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006fa: 193b adds r3, r7, r4 80006fc: 2201 movs r2, #1 80006fe: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000700: 193b adds r3, r7, r4 8000702: 2203 movs r2, #3 8000704: 60da str r2, [r3, #12] HAL_GPIO_Init(iic_sda_GPIO_Port, &GPIO_InitStruct); 8000706: 193b adds r3, r7, r4 8000708: 4a16 ldr r2, [pc, #88] ; (8000764 ) 800070a: 0019 movs r1, r3 800070c: 0010 movs r0, r2 800070e: f000 ff13 bl 8001538 /*Configure GPIO pin : iic_scl_Pin */ GPIO_InitStruct.Pin = iic_scl_Pin; 8000712: 0021 movs r1, r4 8000714: 187b adds r3, r7, r1 8000716: 2280 movs r2, #128 ; 0x80 8000718: 00d2 lsls r2, r2, #3 800071a: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800071c: 187b adds r3, r7, r1 800071e: 2201 movs r2, #1 8000720: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000722: 187b adds r3, r7, r1 8000724: 2201 movs r2, #1 8000726: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000728: 187b adds r3, r7, r1 800072a: 2203 movs r2, #3 800072c: 60da str r2, [r3, #12] HAL_GPIO_Init(iic_scl_GPIO_Port, &GPIO_InitStruct); 800072e: 187a adds r2, r7, r1 8000730: 2390 movs r3, #144 ; 0x90 8000732: 05db lsls r3, r3, #23 8000734: 0011 movs r1, r2 8000736: 0018 movs r0, r3 8000738: f000 fefe bl 8001538 /**/ HAL_I2CEx_EnableFastModePlus(SYSCFG_CFGR1_I2C_FMP_PA10); 800073c: 2380 movs r3, #128 ; 0x80 800073e: 041b lsls r3, r3, #16 8000740: 0018 movs r0, r3 8000742: f001 f8bf bl 80018c4 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI2_3_IRQn, 0, 0); 8000746: 2200 movs r2, #0 8000748: 2100 movs r1, #0 800074a: 2006 movs r0, #6 800074c: f000 fec2 bl 80014d4 HAL_NVIC_EnableIRQ(EXTI2_3_IRQn); 8000750: 2006 movs r0, #6 8000752: f000 fed4 bl 80014fe } 8000756: 46c0 nop ; (mov r8, r8) 8000758: 46bd mov sp, r7 800075a: b009 add sp, #36 ; 0x24 800075c: bd90 pop {r4, r7, pc} 800075e: 46c0 nop ; (mov r8, r8) 8000760: 40021000 .word 0x40021000 8000764: 48000400 .word 0x48000400 8000768: 48001400 .word 0x48001400 0800076c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800076c: b580 push {r7, lr} 800076e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000770: b672 cpsid i } 8000772: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000774: e7fe b.n 8000774 ... 08000778 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000778: b580 push {r7, lr} 800077a: b082 sub sp, #8 800077c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800077e: 4b0f ldr r3, [pc, #60] ; (80007bc ) 8000780: 699a ldr r2, [r3, #24] 8000782: 4b0e ldr r3, [pc, #56] ; (80007bc ) 8000784: 2101 movs r1, #1 8000786: 430a orrs r2, r1 8000788: 619a str r2, [r3, #24] 800078a: 4b0c ldr r3, [pc, #48] ; (80007bc ) 800078c: 699b ldr r3, [r3, #24] 800078e: 2201 movs r2, #1 8000790: 4013 ands r3, r2 8000792: 607b str r3, [r7, #4] 8000794: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000796: 4b09 ldr r3, [pc, #36] ; (80007bc ) 8000798: 69da ldr r2, [r3, #28] 800079a: 4b08 ldr r3, [pc, #32] ; (80007bc ) 800079c: 2180 movs r1, #128 ; 0x80 800079e: 0549 lsls r1, r1, #21 80007a0: 430a orrs r2, r1 80007a2: 61da str r2, [r3, #28] 80007a4: 4b05 ldr r3, [pc, #20] ; (80007bc ) 80007a6: 69da ldr r2, [r3, #28] 80007a8: 2380 movs r3, #128 ; 0x80 80007aa: 055b lsls r3, r3, #21 80007ac: 4013 ands r3, r2 80007ae: 603b str r3, [r7, #0] 80007b0: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80007b2: 46c0 nop ; (mov r8, r8) 80007b4: 46bd mov sp, r7 80007b6: b002 add sp, #8 80007b8: bd80 pop {r7, pc} 80007ba: 46c0 nop ; (mov r8, r8) 80007bc: 40021000 .word 0x40021000 080007c0 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 80007c0: b590 push {r4, r7, lr} 80007c2: b08b sub sp, #44 ; 0x2c 80007c4: af00 add r7, sp, #0 80007c6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007c8: 2414 movs r4, #20 80007ca: 193b adds r3, r7, r4 80007cc: 0018 movs r0, r3 80007ce: 2314 movs r3, #20 80007d0: 001a movs r2, r3 80007d2: 2100 movs r1, #0 80007d4: f003 fb0c bl 8003df0 if(hadc->Instance==ADC1) 80007d8: 687b ldr r3, [r7, #4] 80007da: 681b ldr r3, [r3, #0] 80007dc: 4a19 ldr r2, [pc, #100] ; (8000844 ) 80007de: 4293 cmp r3, r2 80007e0: d12b bne.n 800083a { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80007e2: 4b19 ldr r3, [pc, #100] ; (8000848 ) 80007e4: 699a ldr r2, [r3, #24] 80007e6: 4b18 ldr r3, [pc, #96] ; (8000848 ) 80007e8: 2180 movs r1, #128 ; 0x80 80007ea: 0089 lsls r1, r1, #2 80007ec: 430a orrs r2, r1 80007ee: 619a str r2, [r3, #24] 80007f0: 4b15 ldr r3, [pc, #84] ; (8000848 ) 80007f2: 699a ldr r2, [r3, #24] 80007f4: 2380 movs r3, #128 ; 0x80 80007f6: 009b lsls r3, r3, #2 80007f8: 4013 ands r3, r2 80007fa: 613b str r3, [r7, #16] 80007fc: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80007fe: 4b12 ldr r3, [pc, #72] ; (8000848 ) 8000800: 695a ldr r2, [r3, #20] 8000802: 4b11 ldr r3, [pc, #68] ; (8000848 ) 8000804: 2180 movs r1, #128 ; 0x80 8000806: 0289 lsls r1, r1, #10 8000808: 430a orrs r2, r1 800080a: 615a str r2, [r3, #20] 800080c: 4b0e ldr r3, [pc, #56] ; (8000848 ) 800080e: 695a ldr r2, [r3, #20] 8000810: 2380 movs r3, #128 ; 0x80 8000812: 029b lsls r3, r3, #10 8000814: 4013 ands r3, r2 8000816: 60fb str r3, [r7, #12] 8000818: 68fb ldr r3, [r7, #12] /**ADC GPIO Configuration PA0 ------> ADC_IN0 PA1 ------> ADC_IN1 */ GPIO_InitStruct.Pin = ADC_CH0_Pin|ADC_CH1_Pin; 800081a: 193b adds r3, r7, r4 800081c: 2203 movs r2, #3 800081e: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000820: 193b adds r3, r7, r4 8000822: 2203 movs r2, #3 8000824: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000826: 193b adds r3, r7, r4 8000828: 2200 movs r2, #0 800082a: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800082c: 193a adds r2, r7, r4 800082e: 2390 movs r3, #144 ; 0x90 8000830: 05db lsls r3, r3, #23 8000832: 0011 movs r1, r2 8000834: 0018 movs r0, r3 8000836: f000 fe7f bl 8001538 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 800083a: 46c0 nop ; (mov r8, r8) 800083c: 46bd mov sp, r7 800083e: b00b add sp, #44 ; 0x2c 8000840: bd90 pop {r4, r7, pc} 8000842: 46c0 nop ; (mov r8, r8) 8000844: 40012400 .word 0x40012400 8000848: 40021000 .word 0x40021000 0800084c : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 800084c: b580 push {r7, lr} 800084e: b084 sub sp, #16 8000850: af00 add r7, sp, #0 8000852: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM14) 8000854: 687b ldr r3, [r7, #4] 8000856: 681b ldr r3, [r3, #0] 8000858: 4a0e ldr r2, [pc, #56] ; (8000894 ) 800085a: 4293 cmp r3, r2 800085c: d115 bne.n 800088a { /* USER CODE BEGIN TIM14_MspInit 0 */ /* USER CODE END TIM14_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM14_CLK_ENABLE(); 800085e: 4b0e ldr r3, [pc, #56] ; (8000898 ) 8000860: 69da ldr r2, [r3, #28] 8000862: 4b0d ldr r3, [pc, #52] ; (8000898 ) 8000864: 2180 movs r1, #128 ; 0x80 8000866: 0049 lsls r1, r1, #1 8000868: 430a orrs r2, r1 800086a: 61da str r2, [r3, #28] 800086c: 4b0a ldr r3, [pc, #40] ; (8000898 ) 800086e: 69da ldr r2, [r3, #28] 8000870: 2380 movs r3, #128 ; 0x80 8000872: 005b lsls r3, r3, #1 8000874: 4013 ands r3, r2 8000876: 60fb str r3, [r7, #12] 8000878: 68fb ldr r3, [r7, #12] /* TIM14 interrupt Init */ HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0); 800087a: 2200 movs r2, #0 800087c: 2100 movs r1, #0 800087e: 2013 movs r0, #19 8000880: f000 fe28 bl 80014d4 HAL_NVIC_EnableIRQ(TIM14_IRQn); 8000884: 2013 movs r0, #19 8000886: f000 fe3a bl 80014fe /* USER CODE BEGIN TIM14_MspInit 1 */ /* USER CODE END TIM14_MspInit 1 */ } } 800088a: 46c0 nop ; (mov r8, r8) 800088c: 46bd mov sp, r7 800088e: b004 add sp, #16 8000890: bd80 pop {r7, pc} 8000892: 46c0 nop ; (mov r8, r8) 8000894: 40002000 .word 0x40002000 8000898: 40021000 .word 0x40021000 0800089c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800089c: b580 push {r7, lr} 800089e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80008a0: e7fe b.n 80008a0 080008a2 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80008a2: b580 push {r7, lr} 80008a4: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80008a6: e7fe b.n 80008a6 080008a8 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80008a8: b580 push {r7, lr} 80008aa: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 80008ac: 46c0 nop ; (mov r8, r8) 80008ae: 46bd mov sp, r7 80008b0: bd80 pop {r7, pc} 080008b2 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80008b2: b580 push {r7, lr} 80008b4: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80008b6: 46c0 nop ; (mov r8, r8) 80008b8: 46bd mov sp, r7 80008ba: bd80 pop {r7, pc} 080008bc : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80008bc: b580 push {r7, lr} 80008be: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80008c0: f000 f890 bl 80009e4 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80008c4: 46c0 nop ; (mov r8, r8) 80008c6: 46bd mov sp, r7 80008c8: bd80 pop {r7, pc} 080008ca : /** * @brief This function handles EXTI line 2 and 3 interrupts. */ void EXTI2_3_IRQHandler(void) { 80008ca: b580 push {r7, lr} 80008cc: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI2_3_IRQn 0 */ /* USER CODE END EXTI2_3_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); 80008ce: 2008 movs r0, #8 80008d0: f000 ffdc bl 800188c /* USER CODE BEGIN EXTI2_3_IRQn 1 */ /* USER CODE END EXTI2_3_IRQn 1 */ } 80008d4: 46c0 nop ; (mov r8, r8) 80008d6: 46bd mov sp, r7 80008d8: bd80 pop {r7, pc} ... 080008dc : /** * @brief This function handles TIM14 global interrupt. */ void TIM14_IRQHandler(void) { 80008dc: b580 push {r7, lr} 80008de: af00 add r7, sp, #0 /* USER CODE BEGIN TIM14_IRQn 0 */ /* USER CODE END TIM14_IRQn 0 */ HAL_TIM_IRQHandler(&htim14); 80008e0: 4b03 ldr r3, [pc, #12] ; (80008f0 ) 80008e2: 0018 movs r0, r3 80008e4: f001 fcee bl 80022c4 /* USER CODE BEGIN TIM14_IRQn 1 */ /* USER CODE END TIM14_IRQn 1 */ } 80008e8: 46c0 nop ; (mov r8, r8) 80008ea: 46bd mov sp, r7 80008ec: bd80 pop {r7, pc} 80008ee: 46c0 nop ; (mov r8, r8) 80008f0: 2000004c .word 0x2000004c 080008f4 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 80008f4: b580 push {r7, lr} 80008f6: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 80008f8: 46c0 nop ; (mov r8, r8) 80008fa: 46bd mov sp, r7 80008fc: bd80 pop {r7, pc} ... 08000900 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000900: 480d ldr r0, [pc, #52] ; (8000938 ) mov sp, r0 /* set stack pointer */ 8000902: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000904: 480d ldr r0, [pc, #52] ; (800093c ) ldr r1, =_edata 8000906: 490e ldr r1, [pc, #56] ; (8000940 ) ldr r2, =_sidata 8000908: 4a0e ldr r2, [pc, #56] ; (8000944 ) movs r3, #0 800090a: 2300 movs r3, #0 b LoopCopyDataInit 800090c: e002 b.n 8000914 0800090e : CopyDataInit: ldr r4, [r2, r3] 800090e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000910: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000912: 3304 adds r3, #4 08000914 : LoopCopyDataInit: adds r4, r0, r3 8000914: 18c4 adds r4, r0, r3 cmp r4, r1 8000916: 428c cmp r4, r1 bcc CopyDataInit 8000918: d3f9 bcc.n 800090e /* Zero fill the bss segment. */ ldr r2, =_sbss 800091a: 4a0b ldr r2, [pc, #44] ; (8000948 ) ldr r4, =_ebss 800091c: 4c0b ldr r4, [pc, #44] ; (800094c ) movs r3, #0 800091e: 2300 movs r3, #0 b LoopFillZerobss 8000920: e001 b.n 8000926 08000922 : FillZerobss: str r3, [r2] 8000922: 6013 str r3, [r2, #0] adds r2, r2, #4 8000924: 3204 adds r2, #4 08000926 : LoopFillZerobss: cmp r2, r4 8000926: 42a2 cmp r2, r4 bcc FillZerobss 8000928: d3fb bcc.n 8000922 /* Call the clock system intitialization function.*/ bl SystemInit 800092a: f7ff ffe3 bl 80008f4 /* Call static constructors */ bl __libc_init_array 800092e: f003 fa3b bl 8003da8 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000932: f7ff fd5f bl 80003f4
08000936 : LoopForever: b LoopForever 8000936: e7fe b.n 8000936 ldr r0, =_estack 8000938: 20001000 .word 0x20001000 ldr r0, =_sdata 800093c: 20000000 .word 0x20000000 ldr r1, =_edata 8000940: 2000000c .word 0x2000000c ldr r2, =_sidata 8000944: 08003e80 .word 0x08003e80 ldr r2, =_sbss 8000948: 2000000c .word 0x2000000c ldr r4, =_ebss 800094c: 20000160 .word 0x20000160 08000950 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000950: e7fe b.n 8000950 ... 08000954 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000954: b580 push {r7, lr} 8000956: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000958: 4b07 ldr r3, [pc, #28] ; (8000978 ) 800095a: 681a ldr r2, [r3, #0] 800095c: 4b06 ldr r3, [pc, #24] ; (8000978 ) 800095e: 2110 movs r1, #16 8000960: 430a orrs r2, r1 8000962: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000964: 2003 movs r0, #3 8000966: f000 f809 bl 800097c /* Init the low level hardware */ HAL_MspInit(); 800096a: f7ff ff05 bl 8000778 /* Return function status */ return HAL_OK; 800096e: 2300 movs r3, #0 } 8000970: 0018 movs r0, r3 8000972: 46bd mov sp, r7 8000974: bd80 pop {r7, pc} 8000976: 46c0 nop ; (mov r8, r8) 8000978: 40022000 .word 0x40022000 0800097c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800097c: b590 push {r4, r7, lr} 800097e: b083 sub sp, #12 8000980: af00 add r7, sp, #0 8000982: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000984: 4b14 ldr r3, [pc, #80] ; (80009d8 ) 8000986: 681c ldr r4, [r3, #0] 8000988: 4b14 ldr r3, [pc, #80] ; (80009dc ) 800098a: 781b ldrb r3, [r3, #0] 800098c: 0019 movs r1, r3 800098e: 23fa movs r3, #250 ; 0xfa 8000990: 0098 lsls r0, r3, #2 8000992: f7ff fbb9 bl 8000108 <__udivsi3> 8000996: 0003 movs r3, r0 8000998: 0019 movs r1, r3 800099a: 0020 movs r0, r4 800099c: f7ff fbb4 bl 8000108 <__udivsi3> 80009a0: 0003 movs r3, r0 80009a2: 0018 movs r0, r3 80009a4: f000 fdbb bl 800151e 80009a8: 1e03 subs r3, r0, #0 80009aa: d001 beq.n 80009b0 { return HAL_ERROR; 80009ac: 2301 movs r3, #1 80009ae: e00f b.n 80009d0 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80009b0: 687b ldr r3, [r7, #4] 80009b2: 2b03 cmp r3, #3 80009b4: d80b bhi.n 80009ce { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80009b6: 6879 ldr r1, [r7, #4] 80009b8: 2301 movs r3, #1 80009ba: 425b negs r3, r3 80009bc: 2200 movs r2, #0 80009be: 0018 movs r0, r3 80009c0: f000 fd88 bl 80014d4 uwTickPrio = TickPriority; 80009c4: 4b06 ldr r3, [pc, #24] ; (80009e0 ) 80009c6: 687a ldr r2, [r7, #4] 80009c8: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80009ca: 2300 movs r3, #0 80009cc: e000 b.n 80009d0 return HAL_ERROR; 80009ce: 2301 movs r3, #1 } 80009d0: 0018 movs r0, r3 80009d2: 46bd mov sp, r7 80009d4: b003 add sp, #12 80009d6: bd90 pop {r4, r7, pc} 80009d8: 20000000 .word 0x20000000 80009dc: 20000008 .word 0x20000008 80009e0: 20000004 .word 0x20000004 080009e4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80009e4: b580 push {r7, lr} 80009e6: af00 add r7, sp, #0 uwTick += uwTickFreq; 80009e8: 4b05 ldr r3, [pc, #20] ; (8000a00 ) 80009ea: 781b ldrb r3, [r3, #0] 80009ec: 001a movs r2, r3 80009ee: 4b05 ldr r3, [pc, #20] ; (8000a04 ) 80009f0: 681b ldr r3, [r3, #0] 80009f2: 18d2 adds r2, r2, r3 80009f4: 4b03 ldr r3, [pc, #12] ; (8000a04 ) 80009f6: 601a str r2, [r3, #0] } 80009f8: 46c0 nop ; (mov r8, r8) 80009fa: 46bd mov sp, r7 80009fc: bd80 pop {r7, pc} 80009fe: 46c0 nop ; (mov r8, r8) 8000a00: 20000008 .word 0x20000008 8000a04: 200000d4 .word 0x200000d4 08000a08 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000a08: b580 push {r7, lr} 8000a0a: af00 add r7, sp, #0 return uwTick; 8000a0c: 4b02 ldr r3, [pc, #8] ; (8000a18 ) 8000a0e: 681b ldr r3, [r3, #0] } 8000a10: 0018 movs r0, r3 8000a12: 46bd mov sp, r7 8000a14: bd80 pop {r7, pc} 8000a16: 46c0 nop ; (mov r8, r8) 8000a18: 200000d4 .word 0x200000d4 08000a1c : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8000a1c: b580 push {r7, lr} 8000a1e: b084 sub sp, #16 8000a20: af00 add r7, sp, #0 8000a22: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000a24: 230f movs r3, #15 8000a26: 18fb adds r3, r7, r3 8000a28: 2200 movs r2, #0 8000a2a: 701a strb r2, [r3, #0] uint32_t tmpCFGR1 = 0U; 8000a2c: 2300 movs r3, #0 8000a2e: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) 8000a30: 687b ldr r3, [r7, #4] 8000a32: 2b00 cmp r3, #0 8000a34: d101 bne.n 8000a3a { return HAL_ERROR; 8000a36: 2301 movs r3, #1 8000a38: e125 b.n 8000c86 /* Refer to header of this file for more details on clock enabling procedure*/ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) 8000a3a: 687b ldr r3, [r7, #4] 8000a3c: 6b9b ldr r3, [r3, #56] ; 0x38 8000a3e: 2b00 cmp r3, #0 8000a40: d10a bne.n 8000a58 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8000a42: 687b ldr r3, [r7, #4] 8000a44: 2200 movs r2, #0 8000a46: 63da str r2, [r3, #60] ; 0x3c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8000a48: 687b ldr r3, [r7, #4] 8000a4a: 2234 movs r2, #52 ; 0x34 8000a4c: 2100 movs r1, #0 8000a4e: 5499 strb r1, [r3, r2] /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8000a50: 687b ldr r3, [r7, #4] 8000a52: 0018 movs r0, r3 8000a54: f7ff feb4 bl 80007c0 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ /* and if there is no conversion on going on regular group (ADC can be */ /* enabled anyway, in case of call of this function to update a parameter */ /* on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8000a58: 687b ldr r3, [r7, #4] 8000a5a: 6b9b ldr r3, [r3, #56] ; 0x38 8000a5c: 2210 movs r2, #16 8000a5e: 4013 ands r3, r2 8000a60: d000 beq.n 8000a64 8000a62: e103 b.n 8000c6c 8000a64: 230f movs r3, #15 8000a66: 18fb adds r3, r7, r3 8000a68: 781b ldrb r3, [r3, #0] 8000a6a: 2b00 cmp r3, #0 8000a6c: d000 beq.n 8000a70 8000a6e: e0fd b.n 8000c6c (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 8000a70: 687b ldr r3, [r7, #4] 8000a72: 681b ldr r3, [r3, #0] 8000a74: 689b ldr r3, [r3, #8] 8000a76: 2204 movs r2, #4 8000a78: 4013 ands r3, r2 (tmp_hal_status == HAL_OK) && 8000a7a: d000 beq.n 8000a7e 8000a7c: e0f6 b.n 8000c6c { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000a7e: 687b ldr r3, [r7, #4] 8000a80: 6b9b ldr r3, [r3, #56] ; 0x38 8000a82: 4a83 ldr r2, [pc, #524] ; (8000c90 ) 8000a84: 4013 ands r3, r2 8000a86: 2202 movs r2, #2 8000a88: 431a orrs r2, r3 8000a8a: 687b ldr r3, [r7, #4] 8000a8c: 639a str r2, [r3, #56] ; 0x38 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - ADC clock mode */ /* - ADC clock prescaler */ /* - ADC resolution */ if (ADC_IS_ENABLE(hadc) == RESET) 8000a8e: 687b ldr r3, [r7, #4] 8000a90: 681b ldr r3, [r3, #0] 8000a92: 689b ldr r3, [r3, #8] 8000a94: 2203 movs r2, #3 8000a96: 4013 ands r3, r2 8000a98: 2b01 cmp r3, #1 8000a9a: d112 bne.n 8000ac2 8000a9c: 687b ldr r3, [r7, #4] 8000a9e: 681b ldr r3, [r3, #0] 8000aa0: 681b ldr r3, [r3, #0] 8000aa2: 2201 movs r2, #1 8000aa4: 4013 ands r3, r2 8000aa6: 2b01 cmp r3, #1 8000aa8: d009 beq.n 8000abe 8000aaa: 687b ldr r3, [r7, #4] 8000aac: 681b ldr r3, [r3, #0] 8000aae: 68da ldr r2, [r3, #12] 8000ab0: 2380 movs r3, #128 ; 0x80 8000ab2: 021b lsls r3, r3, #8 8000ab4: 401a ands r2, r3 8000ab6: 2380 movs r3, #128 ; 0x80 8000ab8: 021b lsls r3, r3, #8 8000aba: 429a cmp r2, r3 8000abc: d101 bne.n 8000ac2 8000abe: 2301 movs r3, #1 8000ac0: e000 b.n 8000ac4 8000ac2: 2300 movs r3, #0 8000ac4: 2b00 cmp r3, #0 8000ac6: d116 bne.n 8000af6 /* parameters): */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ MODIFY_REG(hadc->Instance->CFGR1, 8000ac8: 687b ldr r3, [r7, #4] 8000aca: 681b ldr r3, [r3, #0] 8000acc: 68db ldr r3, [r3, #12] 8000ace: 2218 movs r2, #24 8000ad0: 4393 bics r3, r2 8000ad2: 0019 movs r1, r3 8000ad4: 687b ldr r3, [r7, #4] 8000ad6: 689a ldr r2, [r3, #8] 8000ad8: 687b ldr r3, [r7, #4] 8000ada: 681b ldr r3, [r3, #0] 8000adc: 430a orrs r2, r1 8000ade: 60da str r2, [r3, #12] ADC_CFGR1_RES , hadc->Init.Resolution ); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler */ MODIFY_REG(hadc->Instance->CFGR2 , 8000ae0: 687b ldr r3, [r7, #4] 8000ae2: 681b ldr r3, [r3, #0] 8000ae4: 691b ldr r3, [r3, #16] 8000ae6: 009b lsls r3, r3, #2 8000ae8: 0899 lsrs r1, r3, #2 8000aea: 687b ldr r3, [r7, #4] 8000aec: 685a ldr r2, [r3, #4] 8000aee: 687b ldr r3, [r7, #4] 8000af0: 681b ldr r3, [r3, #0] 8000af2: 430a orrs r2, r1 8000af4: 611a str r2, [r3, #16] /* - external trigger polarity */ /* - data alignment */ /* - resolution */ /* - scan direction */ /* - DMA continuous request */ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | 8000af6: 687b ldr r3, [r7, #4] 8000af8: 681b ldr r3, [r3, #0] 8000afa: 68da ldr r2, [r3, #12] 8000afc: 687b ldr r3, [r7, #4] 8000afe: 681b ldr r3, [r3, #0] 8000b00: 4964 ldr r1, [pc, #400] ; (8000c94 ) 8000b02: 400a ands r2, r1 8000b04: 60da str r2, [r3, #12] ADC_CFGR1_EXTEN | ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG ); tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b06: 687b ldr r3, [r7, #4] 8000b08: 7e1b ldrb r3, [r3, #24] 8000b0a: 039a lsls r2, r3, #14 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b0c: 687b ldr r3, [r7, #4] 8000b0e: 7e5b ldrb r3, [r3, #25] 8000b10: 03db lsls r3, r3, #15 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b12: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b14: 687b ldr r3, [r7, #4] 8000b16: 7e9b ldrb r3, [r3, #26] 8000b18: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b1a: 431a orrs r2, r3 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b1c: 687b ldr r3, [r7, #4] 8000b1e: 6a9b ldr r3, [r3, #40] ; 0x28 8000b20: 2b01 cmp r3, #1 8000b22: d002 beq.n 8000b2a 8000b24: 2380 movs r3, #128 ; 0x80 8000b26: 015b lsls r3, r3, #5 8000b28: e000 b.n 8000b2c 8000b2a: 2300 movs r3, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b2c: 431a orrs r2, r3 hadc->Init.DataAlign | 8000b2e: 687b ldr r3, [r7, #4] 8000b30: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b32: 431a orrs r2, r3 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b34: 687b ldr r3, [r7, #4] 8000b36: 691b ldr r3, [r3, #16] 8000b38: 2b02 cmp r3, #2 8000b3a: d101 bne.n 8000b40 8000b3c: 2304 movs r3, #4 8000b3e: e000 b.n 8000b42 8000b40: 2300 movs r3, #0 hadc->Init.DataAlign | 8000b42: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); 8000b44: 687b ldr r3, [r7, #4] 8000b46: 2124 movs r1, #36 ; 0x24 8000b48: 5c5b ldrb r3, [r3, r1] 8000b4a: 005b lsls r3, r3, #1 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b4c: 4313 orrs r3, r2 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b4e: 68ba ldr r2, [r7, #8] 8000b50: 4313 orrs r3, r2 8000b52: 60bb str r3, [r7, #8] /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8000b54: 687b ldr r3, [r7, #4] 8000b56: 7edb ldrb r3, [r3, #27] 8000b58: 2b01 cmp r3, #1 8000b5a: d115 bne.n 8000b88 { if (hadc->Init.ContinuousConvMode == DISABLE) 8000b5c: 687b ldr r3, [r7, #4] 8000b5e: 7e9b ldrb r3, [r3, #26] 8000b60: 2b00 cmp r3, #0 8000b62: d105 bne.n 8000b70 { /* Enable the selected ADC group regular discontinuous mode */ tmpCFGR1 |= ADC_CFGR1_DISCEN; 8000b64: 68bb ldr r3, [r7, #8] 8000b66: 2280 movs r2, #128 ; 0x80 8000b68: 0252 lsls r2, r2, #9 8000b6a: 4313 orrs r3, r2 8000b6c: 60bb str r3, [r7, #8] 8000b6e: e00b b.n 8000b88 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000b70: 687b ldr r3, [r7, #4] 8000b72: 6b9b ldr r3, [r3, #56] ; 0x38 8000b74: 2220 movs r2, #32 8000b76: 431a orrs r2, r3 8000b78: 687b ldr r3, [r7, #4] 8000b7a: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000b7c: 687b ldr r3, [r7, #4] 8000b7e: 6bdb ldr r3, [r3, #60] ; 0x3c 8000b80: 2201 movs r2, #1 8000b82: 431a orrs r2, r3 8000b84: 687b ldr r3, [r7, #4] 8000b86: 63da str r2, [r3, #60] ; 0x3c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8000b88: 687b ldr r3, [r7, #4] 8000b8a: 69da ldr r2, [r3, #28] 8000b8c: 23c2 movs r3, #194 ; 0xc2 8000b8e: 33ff adds r3, #255 ; 0xff 8000b90: 429a cmp r2, r3 8000b92: d007 beq.n 8000ba4 { tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000b94: 687b ldr r3, [r7, #4] 8000b96: 69da ldr r2, [r3, #28] hadc->Init.ExternalTrigConvEdge ); 8000b98: 687b ldr r3, [r7, #4] 8000b9a: 6a1b ldr r3, [r3, #32] tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000b9c: 4313 orrs r3, r2 8000b9e: 68ba ldr r2, [r7, #8] 8000ba0: 4313 orrs r3, r2 8000ba2: 60bb str r3, [r7, #8] } /* Update ADC configuration register with previous settings */ hadc->Instance->CFGR1 |= tmpCFGR1; 8000ba4: 687b ldr r3, [r7, #4] 8000ba6: 681b ldr r3, [r3, #0] 8000ba8: 68d9 ldr r1, [r3, #12] 8000baa: 687b ldr r3, [r7, #4] 8000bac: 681b ldr r3, [r3, #0] 8000bae: 68ba ldr r2, [r7, #8] 8000bb0: 430a orrs r2, r1 8000bb2: 60da str r2, [r3, #12] /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function if parameter */ /* "SamplingTimeCommon" has been set to a valid sampling time. */ /* Otherwise, sampling time is set into ADC channel initialization */ /* structure with parameter "SamplingTime" (obsolete). */ if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000bb4: 687b ldr r3, [r7, #4] 8000bb6: 6ada ldr r2, [r3, #44] ; 0x2c 8000bb8: 2380 movs r3, #128 ; 0x80 8000bba: 055b lsls r3, r3, #21 8000bbc: 429a cmp r2, r3 8000bbe: d01b beq.n 8000bf8 8000bc0: 687b ldr r3, [r7, #4] 8000bc2: 6adb ldr r3, [r3, #44] ; 0x2c 8000bc4: 2b01 cmp r3, #1 8000bc6: d017 beq.n 8000bf8 8000bc8: 687b ldr r3, [r7, #4] 8000bca: 6adb ldr r3, [r3, #44] ; 0x2c 8000bcc: 2b02 cmp r3, #2 8000bce: d013 beq.n 8000bf8 8000bd0: 687b ldr r3, [r7, #4] 8000bd2: 6adb ldr r3, [r3, #44] ; 0x2c 8000bd4: 2b03 cmp r3, #3 8000bd6: d00f beq.n 8000bf8 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 6adb ldr r3, [r3, #44] ; 0x2c 8000bdc: 2b04 cmp r3, #4 8000bde: d00b beq.n 8000bf8 8000be0: 687b ldr r3, [r7, #4] 8000be2: 6adb ldr r3, [r3, #44] ; 0x2c 8000be4: 2b05 cmp r3, #5 8000be6: d007 beq.n 8000bf8 8000be8: 687b ldr r3, [r7, #4] 8000bea: 6adb ldr r3, [r3, #44] ; 0x2c 8000bec: 2b06 cmp r3, #6 8000bee: d003 beq.n 8000bf8 8000bf0: 687b ldr r3, [r7, #4] 8000bf2: 6adb ldr r3, [r3, #44] ; 0x2c 8000bf4: 2b07 cmp r3, #7 8000bf6: d112 bne.n 8000c1e { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000bf8: 687b ldr r3, [r7, #4] 8000bfa: 681b ldr r3, [r3, #0] 8000bfc: 695a ldr r2, [r3, #20] 8000bfe: 687b ldr r3, [r7, #4] 8000c00: 681b ldr r3, [r3, #0] 8000c02: 2107 movs r1, #7 8000c04: 438a bics r2, r1 8000c06: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); 8000c08: 687b ldr r3, [r7, #4] 8000c0a: 681b ldr r3, [r3, #0] 8000c0c: 6959 ldr r1, [r3, #20] 8000c0e: 687b ldr r3, [r7, #4] 8000c10: 6adb ldr r3, [r3, #44] ; 0x2c 8000c12: 2207 movs r2, #7 8000c14: 401a ands r2, r3 8000c16: 687b ldr r3, [r7, #4] 8000c18: 681b ldr r3, [r3, #0] 8000c1a: 430a orrs r2, r1 8000c1c: 615a str r2, [r3, #20] /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ /* set into separate dedicated function, and bits of ADC resolution set */ /* out of temporary variable 'tmpCFGR1'). */ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c1e: 687b ldr r3, [r7, #4] 8000c20: 681b ldr r3, [r3, #0] 8000c22: 68db ldr r3, [r3, #12] 8000c24: 4a1c ldr r2, [pc, #112] ; (8000c98 ) 8000c26: 4013 ands r3, r2 8000c28: 68ba ldr r2, [r7, #8] 8000c2a: 429a cmp r2, r3 8000c2c: d10b bne.n 8000c46 == tmpCFGR1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8000c2e: 687b ldr r3, [r7, #4] 8000c30: 2200 movs r2, #0 8000c32: 63da str r2, [r3, #60] ; 0x3c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000c34: 687b ldr r3, [r7, #4] 8000c36: 6b9b ldr r3, [r3, #56] ; 0x38 8000c38: 2203 movs r2, #3 8000c3a: 4393 bics r3, r2 8000c3c: 2201 movs r2, #1 8000c3e: 431a orrs r2, r3 8000c40: 687b ldr r3, [r7, #4] 8000c42: 639a str r2, [r3, #56] ; 0x38 if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c44: e01c b.n 8000c80 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8000c46: 687b ldr r3, [r7, #4] 8000c48: 6b9b ldr r3, [r3, #56] ; 0x38 8000c4a: 2212 movs r2, #18 8000c4c: 4393 bics r3, r2 8000c4e: 2210 movs r2, #16 8000c50: 431a orrs r2, r3 8000c52: 687b ldr r3, [r7, #4] 8000c54: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000c56: 687b ldr r3, [r7, #4] 8000c58: 6bdb ldr r3, [r3, #60] ; 0x3c 8000c5a: 2201 movs r2, #1 8000c5c: 431a orrs r2, r3 8000c5e: 687b ldr r3, [r7, #4] 8000c60: 63da str r2, [r3, #60] ; 0x3c tmp_hal_status = HAL_ERROR; 8000c62: 230f movs r3, #15 8000c64: 18fb adds r3, r7, r3 8000c66: 2201 movs r2, #1 8000c68: 701a strb r2, [r3, #0] if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c6a: e009 b.n 8000c80 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000c6c: 687b ldr r3, [r7, #4] 8000c6e: 6b9b ldr r3, [r3, #56] ; 0x38 8000c70: 2210 movs r2, #16 8000c72: 431a orrs r2, r3 8000c74: 687b ldr r3, [r7, #4] 8000c76: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000c78: 230f movs r3, #15 8000c7a: 18fb adds r3, r7, r3 8000c7c: 2201 movs r2, #1 8000c7e: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000c80: 230f movs r3, #15 8000c82: 18fb adds r3, r7, r3 8000c84: 781b ldrb r3, [r3, #0] } 8000c86: 0018 movs r0, r3 8000c88: 46bd mov sp, r7 8000c8a: b004 add sp, #16 8000c8c: bd80 pop {r7, pc} 8000c8e: 46c0 nop ; (mov r8, r8) 8000c90: fffffefd .word 0xfffffefd 8000c94: fffe0219 .word 0xfffe0219 8000c98: 833fffe7 .word 0x833fffe7 08000c9c : * Interruptions enabled in this function: None. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 8000c9c: b590 push {r4, r7, lr} 8000c9e: b085 sub sp, #20 8000ca0: af00 add r7, sp, #0 8000ca2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000ca4: 230f movs r3, #15 8000ca6: 18fb adds r3, r7, r3 8000ca8: 2200 movs r2, #0 8000caa: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000cac: 687b ldr r3, [r7, #4] 8000cae: 681b ldr r3, [r3, #0] 8000cb0: 689b ldr r3, [r3, #8] 8000cb2: 2204 movs r2, #4 8000cb4: 4013 ands r3, r2 8000cb6: d138 bne.n 8000d2a { /* Process locked */ __HAL_LOCK(hadc); 8000cb8: 687b ldr r3, [r7, #4] 8000cba: 2234 movs r2, #52 ; 0x34 8000cbc: 5c9b ldrb r3, [r3, r2] 8000cbe: 2b01 cmp r3, #1 8000cc0: d101 bne.n 8000cc6 8000cc2: 2302 movs r3, #2 8000cc4: e038 b.n 8000d38 8000cc6: 687b ldr r3, [r7, #4] 8000cc8: 2234 movs r2, #52 ; 0x34 8000cca: 2101 movs r1, #1 8000ccc: 5499 strb r1, [r3, r2] /* Enable the ADC peripheral */ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) 8000cce: 687b ldr r3, [r7, #4] 8000cd0: 7e5b ldrb r3, [r3, #25] 8000cd2: 2b01 cmp r3, #1 8000cd4: d007 beq.n 8000ce6 { tmp_hal_status = ADC_Enable(hadc); 8000cd6: 230f movs r3, #15 8000cd8: 18fc adds r4, r7, r3 8000cda: 687b ldr r3, [r7, #4] 8000cdc: 0018 movs r0, r3 8000cde: f000 fa0b bl 80010f8 8000ce2: 0003 movs r3, r0 8000ce4: 7023 strb r3, [r4, #0] } /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8000ce6: 230f movs r3, #15 8000ce8: 18fb adds r3, r7, r3 8000cea: 781b ldrb r3, [r3, #0] 8000cec: 2b00 cmp r3, #0 8000cee: d120 bne.n 8000d32 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8000cf0: 687b ldr r3, [r7, #4] 8000cf2: 6b9b ldr r3, [r3, #56] ; 0x38 8000cf4: 4a12 ldr r2, [pc, #72] ; (8000d40 ) 8000cf6: 4013 ands r3, r2 8000cf8: 2280 movs r2, #128 ; 0x80 8000cfa: 0052 lsls r2, r2, #1 8000cfc: 431a orrs r2, r3 8000cfe: 687b ldr r3, [r7, #4] 8000d00: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8000d02: 687b ldr r3, [r7, #4] 8000d04: 2200 movs r2, #0 8000d06: 63da str r2, [r3, #60] ; 0x3c /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8000d08: 687b ldr r3, [r7, #4] 8000d0a: 2234 movs r2, #52 ; 0x34 8000d0c: 2100 movs r1, #0 8000d0e: 5499 strb r1, [r3, r2] /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8000d10: 687b ldr r3, [r7, #4] 8000d12: 681b ldr r3, [r3, #0] 8000d14: 221c movs r2, #28 8000d16: 601a str r2, [r3, #0] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ hadc->Instance->CR |= ADC_CR_ADSTART; 8000d18: 687b ldr r3, [r7, #4] 8000d1a: 681b ldr r3, [r3, #0] 8000d1c: 689a ldr r2, [r3, #8] 8000d1e: 687b ldr r3, [r7, #4] 8000d20: 681b ldr r3, [r3, #0] 8000d22: 2104 movs r1, #4 8000d24: 430a orrs r2, r1 8000d26: 609a str r2, [r3, #8] 8000d28: e003 b.n 8000d32 } } else { tmp_hal_status = HAL_BUSY; 8000d2a: 230f movs r3, #15 8000d2c: 18fb adds r3, r7, r3 8000d2e: 2202 movs r2, #2 8000d30: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000d32: 230f movs r3, #15 8000d34: 18fb adds r3, r7, r3 8000d36: 781b ldrb r3, [r3, #0] } 8000d38: 0018 movs r0, r3 8000d3a: 46bd mov sp, r7 8000d3c: b005 add sp, #20 8000d3e: bd90 pop {r4, r7, pc} 8000d40: fffff0fe .word 0xfffff0fe 08000d44 : * @brief Stop ADC conversion of regular group, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 8000d44: b5b0 push {r4, r5, r7, lr} 8000d46: b084 sub sp, #16 8000d48: af00 add r7, sp, #0 8000d4a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000d4c: 230f movs r3, #15 8000d4e: 18fb adds r3, r7, r3 8000d50: 2200 movs r2, #0 8000d52: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8000d54: 687b ldr r3, [r7, #4] 8000d56: 2234 movs r2, #52 ; 0x34 8000d58: 5c9b ldrb r3, [r3, r2] 8000d5a: 2b01 cmp r3, #1 8000d5c: d101 bne.n 8000d62 8000d5e: 2302 movs r3, #2 8000d60: e029 b.n 8000db6 8000d62: 687b ldr r3, [r7, #4] 8000d64: 2234 movs r2, #52 ; 0x34 8000d66: 2101 movs r1, #1 8000d68: 5499 strb r1, [r3, r2] /* 1. Stop potential conversion on going, on regular group */ tmp_hal_status = ADC_ConversionStop(hadc); 8000d6a: 250f movs r5, #15 8000d6c: 197c adds r4, r7, r5 8000d6e: 687b ldr r3, [r7, #4] 8000d70: 0018 movs r0, r3 8000d72: f000 fab6 bl 80012e2 8000d76: 0003 movs r3, r0 8000d78: 7023 strb r3, [r4, #0] /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) 8000d7a: 197b adds r3, r7, r5 8000d7c: 781b ldrb r3, [r3, #0] 8000d7e: 2b00 cmp r3, #0 8000d80: d112 bne.n 8000da8 { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); 8000d82: 197c adds r4, r7, r5 8000d84: 687b ldr r3, [r7, #4] 8000d86: 0018 movs r0, r3 8000d88: f000 fa3a bl 8001200 8000d8c: 0003 movs r3, r0 8000d8e: 7023 strb r3, [r4, #0] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8000d90: 197b adds r3, r7, r5 8000d92: 781b ldrb r3, [r3, #0] 8000d94: 2b00 cmp r3, #0 8000d96: d107 bne.n 8000da8 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000d98: 687b ldr r3, [r7, #4] 8000d9a: 6b9b ldr r3, [r3, #56] ; 0x38 8000d9c: 4a08 ldr r2, [pc, #32] ; (8000dc0 ) 8000d9e: 4013 ands r3, r2 8000da0: 2201 movs r2, #1 8000da2: 431a orrs r2, r3 8000da4: 687b ldr r3, [r7, #4] 8000da6: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000da8: 687b ldr r3, [r7, #4] 8000daa: 2234 movs r2, #52 ; 0x34 8000dac: 2100 movs r1, #0 8000dae: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 8000db0: 230f movs r3, #15 8000db2: 18fb adds r3, r7, r3 8000db4: 781b ldrb r3, [r3, #0] } 8000db6: 0018 movs r0, r3 8000db8: 46bd mov sp, r7 8000dba: b004 add sp, #16 8000dbc: bdb0 pop {r4, r5, r7, pc} 8000dbe: 46c0 nop ; (mov r8, r8) 8000dc0: fffffefe .word 0xfffffefe 08000dc4 : * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8000dc4: b580 push {r7, lr} 8000dc6: b084 sub sp, #16 8000dc8: af00 add r7, sp, #0 8000dca: 6078 str r0, [r7, #4] 8000dcc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) 8000dce: 687b ldr r3, [r7, #4] 8000dd0: 695b ldr r3, [r3, #20] 8000dd2: 2b08 cmp r3, #8 8000dd4: d102 bne.n 8000ddc { tmp_Flag_EOC = ADC_FLAG_EOS; 8000dd6: 2308 movs r3, #8 8000dd8: 60fb str r3, [r7, #12] 8000dda: e014 b.n 8000e06 /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) 8000ddc: 687b ldr r3, [r7, #4] 8000dde: 681b ldr r3, [r3, #0] 8000de0: 68db ldr r3, [r3, #12] 8000de2: 2201 movs r2, #1 8000de4: 4013 ands r3, r2 8000de6: 2b01 cmp r3, #1 8000de8: d10b bne.n 8000e02 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000dea: 687b ldr r3, [r7, #4] 8000dec: 6b9b ldr r3, [r3, #56] ; 0x38 8000dee: 2220 movs r2, #32 8000df0: 431a orrs r2, r3 8000df2: 687b ldr r3, [r7, #4] 8000df4: 639a str r2, [r3, #56] ; 0x38 /* Process unlocked */ __HAL_UNLOCK(hadc); 8000df6: 687b ldr r3, [r7, #4] 8000df8: 2234 movs r2, #52 ; 0x34 8000dfa: 2100 movs r1, #0 8000dfc: 5499 strb r1, [r3, r2] return HAL_ERROR; 8000dfe: 2301 movs r3, #1 8000e00: e071 b.n 8000ee6 } else { tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); 8000e02: 230c movs r3, #12 8000e04: 60fb str r3, [r7, #12] } } /* Get tick count */ tickstart = HAL_GetTick(); 8000e06: f7ff fdff bl 8000a08 8000e0a: 0003 movs r3, r0 8000e0c: 60bb str r3, [r7, #8] /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e0e: e01f b.n 8000e50 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8000e10: 683b ldr r3, [r7, #0] 8000e12: 3301 adds r3, #1 8000e14: d01c beq.n 8000e50 { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) 8000e16: 683b ldr r3, [r7, #0] 8000e18: 2b00 cmp r3, #0 8000e1a: d007 beq.n 8000e2c 8000e1c: f7ff fdf4 bl 8000a08 8000e20: 0002 movs r2, r0 8000e22: 68bb ldr r3, [r7, #8] 8000e24: 1ad3 subs r3, r2, r3 8000e26: 683a ldr r2, [r7, #0] 8000e28: 429a cmp r2, r3 8000e2a: d211 bcs.n 8000e50 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e2c: 687b ldr r3, [r7, #4] 8000e2e: 681b ldr r3, [r3, #0] 8000e30: 681b ldr r3, [r3, #0] 8000e32: 68fa ldr r2, [r7, #12] 8000e34: 4013 ands r3, r2 8000e36: d10b bne.n 8000e50 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8000e38: 687b ldr r3, [r7, #4] 8000e3a: 6b9b ldr r3, [r3, #56] ; 0x38 8000e3c: 2204 movs r2, #4 8000e3e: 431a orrs r2, r3 8000e40: 687b ldr r3, [r7, #4] 8000e42: 639a str r2, [r3, #56] ; 0x38 /* Process unlocked */ __HAL_UNLOCK(hadc); 8000e44: 687b ldr r3, [r7, #4] 8000e46: 2234 movs r2, #52 ; 0x34 8000e48: 2100 movs r1, #0 8000e4a: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 8000e4c: 2303 movs r3, #3 8000e4e: e04a b.n 8000ee6 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e50: 687b ldr r3, [r7, #4] 8000e52: 681b ldr r3, [r3, #0] 8000e54: 681b ldr r3, [r3, #0] 8000e56: 68fa ldr r2, [r7, #12] 8000e58: 4013 ands r3, r2 8000e5a: d0d9 beq.n 8000e10 } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8000e5c: 687b ldr r3, [r7, #4] 8000e5e: 6b9b ldr r3, [r3, #56] ; 0x38 8000e60: 2280 movs r2, #128 ; 0x80 8000e62: 0092 lsls r2, r2, #2 8000e64: 431a orrs r2, r3 8000e66: 687b ldr r3, [r7, #4] 8000e68: 639a str r2, [r3, #56] ; 0x38 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000e6a: 687b ldr r3, [r7, #4] 8000e6c: 681b ldr r3, [r3, #0] 8000e6e: 68da ldr r2, [r3, #12] 8000e70: 23c0 movs r3, #192 ; 0xc0 8000e72: 011b lsls r3, r3, #4 8000e74: 4013 ands r3, r2 8000e76: d12d bne.n 8000ed4 (hadc->Init.ContinuousConvMode == DISABLE) ) 8000e78: 687b ldr r3, [r7, #4] 8000e7a: 7e9b ldrb r3, [r3, #26] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000e7c: 2b00 cmp r3, #0 8000e7e: d129 bne.n 8000ed4 { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) 8000e80: 687b ldr r3, [r7, #4] 8000e82: 681b ldr r3, [r3, #0] 8000e84: 681b ldr r3, [r3, #0] 8000e86: 2208 movs r2, #8 8000e88: 4013 ands r3, r2 8000e8a: 2b08 cmp r3, #8 8000e8c: d122 bne.n 8000ed4 { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000e8e: 687b ldr r3, [r7, #4] 8000e90: 681b ldr r3, [r3, #0] 8000e92: 689b ldr r3, [r3, #8] 8000e94: 2204 movs r2, #4 8000e96: 4013 ands r3, r2 8000e98: d110 bne.n 8000ebc { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 8000e9a: 687b ldr r3, [r7, #4] 8000e9c: 681b ldr r3, [r3, #0] 8000e9e: 685a ldr r2, [r3, #4] 8000ea0: 687b ldr r3, [r7, #4] 8000ea2: 681b ldr r3, [r3, #0] 8000ea4: 210c movs r1, #12 8000ea6: 438a bics r2, r1 8000ea8: 605a str r2, [r3, #4] /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000eaa: 687b ldr r3, [r7, #4] 8000eac: 6b9b ldr r3, [r3, #56] ; 0x38 8000eae: 4a10 ldr r2, [pc, #64] ; (8000ef0 ) 8000eb0: 4013 ands r3, r2 8000eb2: 2201 movs r2, #1 8000eb4: 431a orrs r2, r3 8000eb6: 687b ldr r3, [r7, #4] 8000eb8: 639a str r2, [r3, #56] ; 0x38 8000eba: e00b b.n 8000ed4 HAL_ADC_STATE_READY); } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000ebc: 687b ldr r3, [r7, #4] 8000ebe: 6b9b ldr r3, [r3, #56] ; 0x38 8000ec0: 2220 movs r2, #32 8000ec2: 431a orrs r2, r3 8000ec4: 687b ldr r3, [r7, #4] 8000ec6: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 6bdb ldr r3, [r3, #60] ; 0x3c 8000ecc: 2201 movs r2, #1 8000ece: 431a orrs r2, r3 8000ed0: 687b ldr r3, [r7, #4] 8000ed2: 63da str r2, [r3, #60] ; 0x3c } /* Clear end of conversion flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (hadc->Init.LowPowerAutoWait == DISABLE) 8000ed4: 687b ldr r3, [r7, #4] 8000ed6: 7e1b ldrb r3, [r3, #24] 8000ed8: 2b00 cmp r3, #0 8000eda: d103 bne.n 8000ee4 { /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); 8000edc: 687b ldr r3, [r7, #4] 8000ede: 681b ldr r3, [r3, #0] 8000ee0: 220c movs r2, #12 8000ee2: 601a str r2, [r3, #0] } /* Return ADC state */ return HAL_OK; 8000ee4: 2300 movs r3, #0 } 8000ee6: 0018 movs r0, r3 8000ee8: 46bd mov sp, r7 8000eea: b004 add sp, #16 8000eec: bd80 pop {r7, pc} 8000eee: 46c0 nop ; (mov r8, r8) 8000ef0: fffffefe .word 0xfffffefe 08000ef4 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8000ef4: b580 push {r7, lr} 8000ef6: b082 sub sp, #8 8000ef8: af00 add r7, sp, #0 8000efa: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8000efc: 687b ldr r3, [r7, #4] 8000efe: 681b ldr r3, [r3, #0] 8000f00: 6c1b ldr r3, [r3, #64] ; 0x40 } 8000f02: 0018 movs r0, r3 8000f04: 46bd mov sp, r7 8000f06: b002 add sp, #8 8000f08: bd80 pop {r7, pc} ... 08000f0c : * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8000f0c: b580 push {r7, lr} 8000f0e: b084 sub sp, #16 8000f10: af00 add r7, sp, #0 8000f12: 6078 str r0, [r7, #4] 8000f14: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000f16: 230f movs r3, #15 8000f18: 18fb adds r3, r7, r3 8000f1a: 2200 movs r2, #0 8000f1c: 701a strb r2, [r3, #0] __IO uint32_t wait_loop_index = 0U; 8000f1e: 2300 movs r3, #0 8000f20: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_RANK(sConfig->Rank)); if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000f22: 687b ldr r3, [r7, #4] 8000f24: 6ada ldr r2, [r3, #44] ; 0x2c 8000f26: 2380 movs r3, #128 ; 0x80 8000f28: 055b lsls r3, r3, #21 8000f2a: 429a cmp r2, r3 8000f2c: d011 beq.n 8000f52 8000f2e: 687b ldr r3, [r7, #4] 8000f30: 6adb ldr r3, [r3, #44] ; 0x2c 8000f32: 2b01 cmp r3, #1 8000f34: d00d beq.n 8000f52 8000f36: 687b ldr r3, [r7, #4] 8000f38: 6adb ldr r3, [r3, #44] ; 0x2c 8000f3a: 2b02 cmp r3, #2 8000f3c: d009 beq.n 8000f52 8000f3e: 687b ldr r3, [r7, #4] 8000f40: 6adb ldr r3, [r3, #44] ; 0x2c 8000f42: 2b03 cmp r3, #3 8000f44: d005 beq.n 8000f52 8000f46: 687b ldr r3, [r7, #4] 8000f48: 6adb ldr r3, [r3, #44] ; 0x2c 8000f4a: 2b04 cmp r3, #4 8000f4c: d001 beq.n 8000f52 8000f4e: 687b ldr r3, [r7, #4] 8000f50: 6adb ldr r3, [r3, #44] ; 0x2c { assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); } /* Process locked */ __HAL_LOCK(hadc); 8000f52: 687b ldr r3, [r7, #4] 8000f54: 2234 movs r2, #52 ; 0x34 8000f56: 5c9b ldrb r3, [r3, r2] 8000f58: 2b01 cmp r3, #1 8000f5a: d101 bne.n 8000f60 8000f5c: 2302 movs r3, #2 8000f5e: e0bb b.n 80010d8 8000f60: 687b ldr r3, [r7, #4] 8000f62: 2234 movs r2, #52 ; 0x34 8000f64: 2101 movs r1, #1 8000f66: 5499 strb r1, [r3, r2] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000f68: 687b ldr r3, [r7, #4] 8000f6a: 681b ldr r3, [r3, #0] 8000f6c: 689b ldr r3, [r3, #8] 8000f6e: 2204 movs r2, #4 8000f70: 4013 ands r3, r2 8000f72: d000 beq.n 8000f76 8000f74: e09f b.n 80010b6 { /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC conversion sequencer. */ if (sConfig->Rank != ADC_RANK_NONE) 8000f76: 683b ldr r3, [r7, #0] 8000f78: 685b ldr r3, [r3, #4] 8000f7a: 4a59 ldr r2, [pc, #356] ; (80010e0 ) 8000f7c: 4293 cmp r3, r2 8000f7e: d100 bne.n 8000f82 8000f80: e077 b.n 8001072 { /* Regular sequence configuration */ /* Set the channel selection register from the selected channel */ hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); 8000f82: 687b ldr r3, [r7, #4] 8000f84: 681b ldr r3, [r3, #0] 8000f86: 6a99 ldr r1, [r3, #40] ; 0x28 8000f88: 683b ldr r3, [r7, #0] 8000f8a: 681b ldr r3, [r3, #0] 8000f8c: 2201 movs r2, #1 8000f8e: 409a lsls r2, r3 8000f90: 687b ldr r3, [r7, #4] 8000f92: 681b ldr r3, [r3, #0] 8000f94: 430a orrs r2, r1 8000f96: 629a str r2, [r3, #40] ; 0x28 /* Channel sampling time configuration */ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function with */ /* parameter "SamplingTime" (obsolete) only if not already set into */ /* ADC initialization structure with parameter "SamplingTimeCommon". */ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000f98: 687b ldr r3, [r7, #4] 8000f9a: 6ada ldr r2, [r3, #44] ; 0x2c 8000f9c: 2380 movs r3, #128 ; 0x80 8000f9e: 055b lsls r3, r3, #21 8000fa0: 429a cmp r2, r3 8000fa2: d037 beq.n 8001014 8000fa4: 687b ldr r3, [r7, #4] 8000fa6: 6adb ldr r3, [r3, #44] ; 0x2c 8000fa8: 2b01 cmp r3, #1 8000faa: d033 beq.n 8001014 8000fac: 687b ldr r3, [r7, #4] 8000fae: 6adb ldr r3, [r3, #44] ; 0x2c 8000fb0: 2b02 cmp r3, #2 8000fb2: d02f beq.n 8001014 8000fb4: 687b ldr r3, [r7, #4] 8000fb6: 6adb ldr r3, [r3, #44] ; 0x2c 8000fb8: 2b03 cmp r3, #3 8000fba: d02b beq.n 8001014 8000fbc: 687b ldr r3, [r7, #4] 8000fbe: 6adb ldr r3, [r3, #44] ; 0x2c 8000fc0: 2b04 cmp r3, #4 8000fc2: d027 beq.n 8001014 8000fc4: 687b ldr r3, [r7, #4] 8000fc6: 6adb ldr r3, [r3, #44] ; 0x2c 8000fc8: 2b05 cmp r3, #5 8000fca: d023 beq.n 8001014 8000fcc: 687b ldr r3, [r7, #4] 8000fce: 6adb ldr r3, [r3, #44] ; 0x2c 8000fd0: 2b06 cmp r3, #6 8000fd2: d01f beq.n 8001014 8000fd4: 687b ldr r3, [r7, #4] 8000fd6: 6adb ldr r3, [r3, #44] ; 0x2c 8000fd8: 2b07 cmp r3, #7 8000fda: d01b beq.n 8001014 { /* Modify sampling time if needed (not needed in case of reoccurrence */ /* for several channels programmed consecutively into the sequencer) */ if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) 8000fdc: 683b ldr r3, [r7, #0] 8000fde: 689a ldr r2, [r3, #8] 8000fe0: 687b ldr r3, [r7, #4] 8000fe2: 681b ldr r3, [r3, #0] 8000fe4: 695b ldr r3, [r3, #20] 8000fe6: 2107 movs r1, #7 8000fe8: 400b ands r3, r1 8000fea: 429a cmp r2, r3 8000fec: d012 beq.n 8001014 { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000fee: 687b ldr r3, [r7, #4] 8000ff0: 681b ldr r3, [r3, #0] 8000ff2: 695a ldr r2, [r3, #20] 8000ff4: 687b ldr r3, [r7, #4] 8000ff6: 681b ldr r3, [r3, #0] 8000ff8: 2107 movs r1, #7 8000ffa: 438a bics r2, r1 8000ffc: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); 8000ffe: 687b ldr r3, [r7, #4] 8001000: 681b ldr r3, [r3, #0] 8001002: 6959 ldr r1, [r3, #20] 8001004: 683b ldr r3, [r7, #0] 8001006: 689b ldr r3, [r3, #8] 8001008: 2207 movs r2, #7 800100a: 401a ands r2, r3 800100c: 687b ldr r3, [r7, #4] 800100e: 681b ldr r3, [r3, #0] 8001010: 430a orrs r2, r1 8001012: 615a str r2, [r3, #20] /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8001014: 683b ldr r3, [r7, #0] 8001016: 681b ldr r3, [r3, #0] 8001018: 2b10 cmp r3, #16 800101a: d003 beq.n 8001024 800101c: 683b ldr r3, [r7, #0] 800101e: 681b ldr r3, [r3, #0] 8001020: 2b11 cmp r3, #17 8001022: d152 bne.n 80010ca { /* If Channel_16 is selected, enable Temp. sensor measurement path. */ /* If Channel_17 is selected, enable VREFINT measurement path. */ /* If Channel_18 is selected, enable VBAT measurement path. */ ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 8001024: 4b2f ldr r3, [pc, #188] ; (80010e4 ) 8001026: 6819 ldr r1, [r3, #0] 8001028: 683b ldr r3, [r7, #0] 800102a: 681b ldr r3, [r3, #0] 800102c: 2b10 cmp r3, #16 800102e: d102 bne.n 8001036 8001030: 2380 movs r3, #128 ; 0x80 8001032: 041b lsls r3, r3, #16 8001034: e001 b.n 800103a 8001036: 2380 movs r3, #128 ; 0x80 8001038: 03db lsls r3, r3, #15 800103a: 4a2a ldr r2, [pc, #168] ; (80010e4 ) 800103c: 430b orrs r3, r1 800103e: 6013 str r3, [r2, #0] /* If Temp. sensor is selected, wait for stabilization delay */ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8001040: 683b ldr r3, [r7, #0] 8001042: 681b ldr r3, [r3, #0] 8001044: 2b10 cmp r3, #16 8001046: d140 bne.n 80010ca { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001048: 4b27 ldr r3, [pc, #156] ; (80010e8 ) 800104a: 681b ldr r3, [r3, #0] 800104c: 4927 ldr r1, [pc, #156] ; (80010ec ) 800104e: 0018 movs r0, r3 8001050: f7ff f85a bl 8000108 <__udivsi3> 8001054: 0003 movs r3, r0 8001056: 001a movs r2, r3 8001058: 0013 movs r3, r2 800105a: 009b lsls r3, r3, #2 800105c: 189b adds r3, r3, r2 800105e: 005b lsls r3, r3, #1 8001060: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001062: e002 b.n 800106a { wait_loop_index--; 8001064: 68bb ldr r3, [r7, #8] 8001066: 3b01 subs r3, #1 8001068: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800106a: 68bb ldr r3, [r7, #8] 800106c: 2b00 cmp r3, #0 800106e: d1f9 bne.n 8001064 8001070: e02b b.n 80010ca } else { /* Regular sequence configuration */ /* Reset the channel selection register from the selected channel */ hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); 8001072: 687b ldr r3, [r7, #4] 8001074: 681b ldr r3, [r3, #0] 8001076: 6a9a ldr r2, [r3, #40] ; 0x28 8001078: 683b ldr r3, [r7, #0] 800107a: 681b ldr r3, [r3, #0] 800107c: 2101 movs r1, #1 800107e: 4099 lsls r1, r3 8001080: 000b movs r3, r1 8001082: 43d9 mvns r1, r3 8001084: 687b ldr r3, [r7, #4] 8001086: 681b ldr r3, [r3, #0] 8001088: 400a ands r2, r1 800108a: 629a str r2, [r3, #40] ; 0x28 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths disable: If internal channel selected, */ /* disable dedicated internal buffers and path. */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 800108c: 683b ldr r3, [r7, #0] 800108e: 681b ldr r3, [r3, #0] 8001090: 2b10 cmp r3, #16 8001092: d003 beq.n 800109c 8001094: 683b ldr r3, [r7, #0] 8001096: 681b ldr r3, [r3, #0] 8001098: 2b11 cmp r3, #17 800109a: d116 bne.n 80010ca { /* If Channel_16 is selected, disable Temp. sensor measurement path. */ /* If Channel_17 is selected, disable VREFINT measurement path. */ /* If Channel_18 is selected, disable VBAT measurement path. */ ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 800109c: 4b11 ldr r3, [pc, #68] ; (80010e4 ) 800109e: 6819 ldr r1, [r3, #0] 80010a0: 683b ldr r3, [r7, #0] 80010a2: 681b ldr r3, [r3, #0] 80010a4: 2b10 cmp r3, #16 80010a6: d101 bne.n 80010ac 80010a8: 4a11 ldr r2, [pc, #68] ; (80010f0 ) 80010aa: e000 b.n 80010ae 80010ac: 4a11 ldr r2, [pc, #68] ; (80010f4 ) 80010ae: 4b0d ldr r3, [pc, #52] ; (80010e4 ) 80010b0: 400a ands r2, r1 80010b2: 601a str r2, [r3, #0] 80010b4: e009 b.n 80010ca /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80010b6: 687b ldr r3, [r7, #4] 80010b8: 6b9b ldr r3, [r3, #56] ; 0x38 80010ba: 2220 movs r2, #32 80010bc: 431a orrs r2, r3 80010be: 687b ldr r3, [r7, #4] 80010c0: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 80010c2: 230f movs r3, #15 80010c4: 18fb adds r3, r7, r3 80010c6: 2201 movs r2, #1 80010c8: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hadc); 80010ca: 687b ldr r3, [r7, #4] 80010cc: 2234 movs r2, #52 ; 0x34 80010ce: 2100 movs r1, #0 80010d0: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 80010d2: 230f movs r3, #15 80010d4: 18fb adds r3, r7, r3 80010d6: 781b ldrb r3, [r3, #0] } 80010d8: 0018 movs r0, r3 80010da: 46bd mov sp, r7 80010dc: b004 add sp, #16 80010de: bd80 pop {r7, pc} 80010e0: 00001001 .word 0x00001001 80010e4: 40012708 .word 0x40012708 80010e8: 20000000 .word 0x20000000 80010ec: 000f4240 .word 0x000f4240 80010f0: ff7fffff .word 0xff7fffff 80010f4: ffbfffff .word 0xffbfffff 080010f8 : * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 80010f8: b580 push {r7, lr} 80010fa: b084 sub sp, #16 80010fc: af00 add r7, sp, #0 80010fe: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001100: 2300 movs r3, #0 8001102: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8001104: 2300 movs r3, #0 8001106: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8001108: 687b ldr r3, [r7, #4] 800110a: 681b ldr r3, [r3, #0] 800110c: 689b ldr r3, [r3, #8] 800110e: 2203 movs r2, #3 8001110: 4013 ands r3, r2 8001112: 2b01 cmp r3, #1 8001114: d112 bne.n 800113c 8001116: 687b ldr r3, [r7, #4] 8001118: 681b ldr r3, [r3, #0] 800111a: 681b ldr r3, [r3, #0] 800111c: 2201 movs r2, #1 800111e: 4013 ands r3, r2 8001120: 2b01 cmp r3, #1 8001122: d009 beq.n 8001138 8001124: 687b ldr r3, [r7, #4] 8001126: 681b ldr r3, [r3, #0] 8001128: 68da ldr r2, [r3, #12] 800112a: 2380 movs r3, #128 ; 0x80 800112c: 021b lsls r3, r3, #8 800112e: 401a ands r2, r3 8001130: 2380 movs r3, #128 ; 0x80 8001132: 021b lsls r3, r3, #8 8001134: 429a cmp r2, r3 8001136: d101 bne.n 800113c 8001138: 2301 movs r3, #1 800113a: e000 b.n 800113e 800113c: 2300 movs r3, #0 800113e: 2b00 cmp r3, #0 8001140: d152 bne.n 80011e8 { /* Check if conditions to enable the ADC are fulfilled */ if (ADC_ENABLING_CONDITIONS(hadc) == RESET) 8001142: 687b ldr r3, [r7, #4] 8001144: 681b ldr r3, [r3, #0] 8001146: 689b ldr r3, [r3, #8] 8001148: 4a2a ldr r2, [pc, #168] ; (80011f4 ) 800114a: 4013 ands r3, r2 800114c: d00d beq.n 800116a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800114e: 687b ldr r3, [r7, #4] 8001150: 6b9b ldr r3, [r3, #56] ; 0x38 8001152: 2210 movs r2, #16 8001154: 431a orrs r2, r3 8001156: 687b ldr r3, [r7, #4] 8001158: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800115a: 687b ldr r3, [r7, #4] 800115c: 6bdb ldr r3, [r3, #60] ; 0x3c 800115e: 2201 movs r2, #1 8001160: 431a orrs r2, r3 8001162: 687b ldr r3, [r7, #4] 8001164: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 8001166: 2301 movs r3, #1 8001168: e03f b.n 80011ea } /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); 800116a: 687b ldr r3, [r7, #4] 800116c: 681b ldr r3, [r3, #0] 800116e: 689a ldr r2, [r3, #8] 8001170: 687b ldr r3, [r7, #4] 8001172: 681b ldr r3, [r3, #0] 8001174: 2101 movs r1, #1 8001176: 430a orrs r2, r1 8001178: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800117a: 4b1f ldr r3, [pc, #124] ; (80011f8 ) 800117c: 681b ldr r3, [r3, #0] 800117e: 491f ldr r1, [pc, #124] ; (80011fc ) 8001180: 0018 movs r0, r3 8001182: f7fe ffc1 bl 8000108 <__udivsi3> 8001186: 0003 movs r3, r0 8001188: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800118a: e002 b.n 8001192 { wait_loop_index--; 800118c: 68bb ldr r3, [r7, #8] 800118e: 3b01 subs r3, #1 8001190: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001192: 68bb ldr r3, [r7, #8] 8001194: 2b00 cmp r3, #0 8001196: d1f9 bne.n 800118c } /* Get tick count */ tickstart = HAL_GetTick(); 8001198: f7ff fc36 bl 8000a08 800119c: 0003 movs r3, r0 800119e: 60fb str r3, [r7, #12] /* Wait for ADC effectively enabled */ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80011a0: e01b b.n 80011da { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80011a2: f7ff fc31 bl 8000a08 80011a6: 0002 movs r2, r0 80011a8: 68fb ldr r3, [r7, #12] 80011aa: 1ad3 subs r3, r2, r3 80011ac: 2b02 cmp r3, #2 80011ae: d914 bls.n 80011da { /* New check to avoid false timeout detection in case of preemption */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80011b0: 687b ldr r3, [r7, #4] 80011b2: 681b ldr r3, [r3, #0] 80011b4: 681b ldr r3, [r3, #0] 80011b6: 2201 movs r2, #1 80011b8: 4013 ands r3, r2 80011ba: 2b01 cmp r3, #1 80011bc: d00d beq.n 80011da { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80011be: 687b ldr r3, [r7, #4] 80011c0: 6b9b ldr r3, [r3, #56] ; 0x38 80011c2: 2210 movs r2, #16 80011c4: 431a orrs r2, r3 80011c6: 687b ldr r3, [r7, #4] 80011c8: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80011ca: 687b ldr r3, [r7, #4] 80011cc: 6bdb ldr r3, [r3, #60] ; 0x3c 80011ce: 2201 movs r2, #1 80011d0: 431a orrs r2, r3 80011d2: 687b ldr r3, [r7, #4] 80011d4: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80011d6: 2301 movs r3, #1 80011d8: e007 b.n 80011ea while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80011da: 687b ldr r3, [r7, #4] 80011dc: 681b ldr r3, [r3, #0] 80011de: 681b ldr r3, [r3, #0] 80011e0: 2201 movs r2, #1 80011e2: 4013 ands r3, r2 80011e4: 2b01 cmp r3, #1 80011e6: d1dc bne.n 80011a2 } } } /* Return HAL status */ return HAL_OK; 80011e8: 2300 movs r3, #0 } 80011ea: 0018 movs r0, r3 80011ec: 46bd mov sp, r7 80011ee: b004 add sp, #16 80011f0: bd80 pop {r7, pc} 80011f2: 46c0 nop ; (mov r8, r8) 80011f4: 80000017 .word 0x80000017 80011f8: 20000000 .word 0x20000000 80011fc: 000f4240 .word 0x000f4240 08001200 : * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { 8001200: b580 push {r7, lr} 8001202: b084 sub sp, #16 8001204: af00 add r7, sp, #0 8001206: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001208: 2300 movs r3, #0 800120a: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET) 800120c: 687b ldr r3, [r7, #4] 800120e: 681b ldr r3, [r3, #0] 8001210: 689b ldr r3, [r3, #8] 8001212: 2203 movs r2, #3 8001214: 4013 ands r3, r2 8001216: 2b01 cmp r3, #1 8001218: d112 bne.n 8001240 800121a: 687b ldr r3, [r7, #4] 800121c: 681b ldr r3, [r3, #0] 800121e: 681b ldr r3, [r3, #0] 8001220: 2201 movs r2, #1 8001222: 4013 ands r3, r2 8001224: 2b01 cmp r3, #1 8001226: d009 beq.n 800123c 8001228: 687b ldr r3, [r7, #4] 800122a: 681b ldr r3, [r3, #0] 800122c: 68da ldr r2, [r3, #12] 800122e: 2380 movs r3, #128 ; 0x80 8001230: 021b lsls r3, r3, #8 8001232: 401a ands r2, r3 8001234: 2380 movs r3, #128 ; 0x80 8001236: 021b lsls r3, r3, #8 8001238: 429a cmp r2, r3 800123a: d101 bne.n 8001240 800123c: 2301 movs r3, #1 800123e: e000 b.n 8001242 8001240: 2300 movs r3, #0 8001242: 2b00 cmp r3, #0 8001244: d048 beq.n 80012d8 { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) 8001246: 687b ldr r3, [r7, #4] 8001248: 681b ldr r3, [r3, #0] 800124a: 689b ldr r3, [r3, #8] 800124c: 2205 movs r2, #5 800124e: 4013 ands r3, r2 8001250: 2b01 cmp r3, #1 8001252: d110 bne.n 8001276 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8001254: 687b ldr r3, [r7, #4] 8001256: 681b ldr r3, [r3, #0] 8001258: 689a ldr r2, [r3, #8] 800125a: 687b ldr r3, [r7, #4] 800125c: 681b ldr r3, [r3, #0] 800125e: 2102 movs r1, #2 8001260: 430a orrs r2, r1 8001262: 609a str r2, [r3, #8] 8001264: 687b ldr r3, [r7, #4] 8001266: 681b ldr r3, [r3, #0] 8001268: 2203 movs r2, #3 800126a: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 800126c: f7ff fbcc bl 8000a08 8001270: 0003 movs r3, r0 8001272: 60fb str r3, [r7, #12] while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 8001274: e029 b.n 80012ca SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001276: 687b ldr r3, [r7, #4] 8001278: 6b9b ldr r3, [r3, #56] ; 0x38 800127a: 2210 movs r2, #16 800127c: 431a orrs r2, r3 800127e: 687b ldr r3, [r7, #4] 8001280: 639a str r2, [r3, #56] ; 0x38 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001282: 687b ldr r3, [r7, #4] 8001284: 6bdb ldr r3, [r3, #60] ; 0x3c 8001286: 2201 movs r2, #1 8001288: 431a orrs r2, r3 800128a: 687b ldr r3, [r7, #4] 800128c: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 800128e: 2301 movs r3, #1 8001290: e023 b.n 80012da { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8001292: f7ff fbb9 bl 8000a08 8001296: 0002 movs r2, r0 8001298: 68fb ldr r3, [r7, #12] 800129a: 1ad3 subs r3, r2, r3 800129c: 2b02 cmp r3, #2 800129e: d914 bls.n 80012ca { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80012a0: 687b ldr r3, [r7, #4] 80012a2: 681b ldr r3, [r3, #0] 80012a4: 689b ldr r3, [r3, #8] 80012a6: 2201 movs r2, #1 80012a8: 4013 ands r3, r2 80012aa: 2b01 cmp r3, #1 80012ac: d10d bne.n 80012ca { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80012ae: 687b ldr r3, [r7, #4] 80012b0: 6b9b ldr r3, [r3, #56] ; 0x38 80012b2: 2210 movs r2, #16 80012b4: 431a orrs r2, r3 80012b6: 687b ldr r3, [r7, #4] 80012b8: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80012ba: 687b ldr r3, [r7, #4] 80012bc: 6bdb ldr r3, [r3, #60] ; 0x3c 80012be: 2201 movs r2, #1 80012c0: 431a orrs r2, r3 80012c2: 687b ldr r3, [r7, #4] 80012c4: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80012c6: 2301 movs r3, #1 80012c8: e007 b.n 80012da while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80012ca: 687b ldr r3, [r7, #4] 80012cc: 681b ldr r3, [r3, #0] 80012ce: 689b ldr r3, [r3, #8] 80012d0: 2201 movs r2, #1 80012d2: 4013 ands r3, r2 80012d4: 2b01 cmp r3, #1 80012d6: d0dc beq.n 8001292 } } } /* Return HAL status */ return HAL_OK; 80012d8: 2300 movs r3, #0 } 80012da: 0018 movs r0, r3 80012dc: 46bd mov sp, r7 80012de: b004 add sp, #16 80012e0: bd80 pop {r7, pc} 080012e2 : * stopped to disable the ADC. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) { 80012e2: b580 push {r7, lr} 80012e4: b084 sub sp, #16 80012e6: af00 add r7, sp, #0 80012e8: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80012ea: 2300 movs r3, #0 80012ec: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Verification if ADC is not already stopped on regular group to bypass */ /* this function if not needed. */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) 80012ee: 687b ldr r3, [r7, #4] 80012f0: 681b ldr r3, [r3, #0] 80012f2: 689b ldr r3, [r3, #8] 80012f4: 2204 movs r2, #4 80012f6: 4013 ands r3, r2 80012f8: d03a beq.n 8001370 { /* Stop potential conversion on going on regular group */ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 80012fa: 687b ldr r3, [r7, #4] 80012fc: 681b ldr r3, [r3, #0] 80012fe: 689b ldr r3, [r3, #8] 8001300: 2204 movs r2, #4 8001302: 4013 ands r3, r2 8001304: 2b04 cmp r3, #4 8001306: d10d bne.n 8001324 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) 8001308: 687b ldr r3, [r7, #4] 800130a: 681b ldr r3, [r3, #0] 800130c: 689b ldr r3, [r3, #8] 800130e: 2202 movs r2, #2 8001310: 4013 ands r3, r2 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 8001312: d107 bne.n 8001324 { /* Stop conversions on regular group */ hadc->Instance->CR |= ADC_CR_ADSTP; 8001314: 687b ldr r3, [r7, #4] 8001316: 681b ldr r3, [r3, #0] 8001318: 689a ldr r2, [r3, #8] 800131a: 687b ldr r3, [r7, #4] 800131c: 681b ldr r3, [r3, #0] 800131e: 2110 movs r1, #16 8001320: 430a orrs r2, r1 8001322: 609a str r2, [r3, #8] } /* Wait for conversion effectively stopped */ /* Get tick count */ tickstart = HAL_GetTick(); 8001324: f7ff fb70 bl 8000a08 8001328: 0003 movs r3, r0 800132a: 60fb str r3, [r7, #12] while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 800132c: e01a b.n 8001364 { if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 800132e: f7ff fb6b bl 8000a08 8001332: 0002 movs r2, r0 8001334: 68fb ldr r3, [r7, #12] 8001336: 1ad3 subs r3, r2, r3 8001338: 2b02 cmp r3, #2 800133a: d913 bls.n 8001364 { /* New check to avoid false timeout detection in case of preemption */ if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 800133c: 687b ldr r3, [r7, #4] 800133e: 681b ldr r3, [r3, #0] 8001340: 689b ldr r3, [r3, #8] 8001342: 2204 movs r2, #4 8001344: 4013 ands r3, r2 8001346: d00d beq.n 8001364 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001348: 687b ldr r3, [r7, #4] 800134a: 6b9b ldr r3, [r3, #56] ; 0x38 800134c: 2210 movs r2, #16 800134e: 431a orrs r2, r3 8001350: 687b ldr r3, [r7, #4] 8001352: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001354: 687b ldr r3, [r7, #4] 8001356: 6bdb ldr r3, [r3, #60] ; 0x3c 8001358: 2201 movs r2, #1 800135a: 431a orrs r2, r3 800135c: 687b ldr r3, [r7, #4] 800135e: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 8001360: 2301 movs r3, #1 8001362: e006 b.n 8001372 while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 8001364: 687b ldr r3, [r7, #4] 8001366: 681b ldr r3, [r3, #0] 8001368: 689b ldr r3, [r3, #8] 800136a: 2204 movs r2, #4 800136c: 4013 ands r3, r2 800136e: d1de bne.n 800132e } } } /* Return HAL status */ return HAL_OK; 8001370: 2300 movs r3, #0 } 8001372: 0018 movs r0, r3 8001374: 46bd mov sp, r7 8001376: b004 add sp, #16 8001378: bd80 pop {r7, pc} ... 0800137c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800137c: b580 push {r7, lr} 800137e: b082 sub sp, #8 8001380: af00 add r7, sp, #0 8001382: 0002 movs r2, r0 8001384: 1dfb adds r3, r7, #7 8001386: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8001388: 1dfb adds r3, r7, #7 800138a: 781b ldrb r3, [r3, #0] 800138c: 2b7f cmp r3, #127 ; 0x7f 800138e: d809 bhi.n 80013a4 <__NVIC_EnableIRQ+0x28> { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001390: 1dfb adds r3, r7, #7 8001392: 781b ldrb r3, [r3, #0] 8001394: 001a movs r2, r3 8001396: 231f movs r3, #31 8001398: 401a ands r2, r3 800139a: 4b04 ldr r3, [pc, #16] ; (80013ac <__NVIC_EnableIRQ+0x30>) 800139c: 2101 movs r1, #1 800139e: 4091 lsls r1, r2 80013a0: 000a movs r2, r1 80013a2: 601a str r2, [r3, #0] } } 80013a4: 46c0 nop ; (mov r8, r8) 80013a6: 46bd mov sp, r7 80013a8: b002 add sp, #8 80013aa: bd80 pop {r7, pc} 80013ac: e000e100 .word 0xe000e100 080013b0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80013b0: b590 push {r4, r7, lr} 80013b2: b083 sub sp, #12 80013b4: af00 add r7, sp, #0 80013b6: 0002 movs r2, r0 80013b8: 6039 str r1, [r7, #0] 80013ba: 1dfb adds r3, r7, #7 80013bc: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80013be: 1dfb adds r3, r7, #7 80013c0: 781b ldrb r3, [r3, #0] 80013c2: 2b7f cmp r3, #127 ; 0x7f 80013c4: d828 bhi.n 8001418 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80013c6: 4a2f ldr r2, [pc, #188] ; (8001484 <__NVIC_SetPriority+0xd4>) 80013c8: 1dfb adds r3, r7, #7 80013ca: 781b ldrb r3, [r3, #0] 80013cc: b25b sxtb r3, r3 80013ce: 089b lsrs r3, r3, #2 80013d0: 33c0 adds r3, #192 ; 0xc0 80013d2: 009b lsls r3, r3, #2 80013d4: 589b ldr r3, [r3, r2] 80013d6: 1dfa adds r2, r7, #7 80013d8: 7812 ldrb r2, [r2, #0] 80013da: 0011 movs r1, r2 80013dc: 2203 movs r2, #3 80013de: 400a ands r2, r1 80013e0: 00d2 lsls r2, r2, #3 80013e2: 21ff movs r1, #255 ; 0xff 80013e4: 4091 lsls r1, r2 80013e6: 000a movs r2, r1 80013e8: 43d2 mvns r2, r2 80013ea: 401a ands r2, r3 80013ec: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80013ee: 683b ldr r3, [r7, #0] 80013f0: 019b lsls r3, r3, #6 80013f2: 22ff movs r2, #255 ; 0xff 80013f4: 401a ands r2, r3 80013f6: 1dfb adds r3, r7, #7 80013f8: 781b ldrb r3, [r3, #0] 80013fa: 0018 movs r0, r3 80013fc: 2303 movs r3, #3 80013fe: 4003 ands r3, r0 8001400: 00db lsls r3, r3, #3 8001402: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001404: 481f ldr r0, [pc, #124] ; (8001484 <__NVIC_SetPriority+0xd4>) 8001406: 1dfb adds r3, r7, #7 8001408: 781b ldrb r3, [r3, #0] 800140a: b25b sxtb r3, r3 800140c: 089b lsrs r3, r3, #2 800140e: 430a orrs r2, r1 8001410: 33c0 adds r3, #192 ; 0xc0 8001412: 009b lsls r3, r3, #2 8001414: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8001416: e031 b.n 800147c <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001418: 4a1b ldr r2, [pc, #108] ; (8001488 <__NVIC_SetPriority+0xd8>) 800141a: 1dfb adds r3, r7, #7 800141c: 781b ldrb r3, [r3, #0] 800141e: 0019 movs r1, r3 8001420: 230f movs r3, #15 8001422: 400b ands r3, r1 8001424: 3b08 subs r3, #8 8001426: 089b lsrs r3, r3, #2 8001428: 3306 adds r3, #6 800142a: 009b lsls r3, r3, #2 800142c: 18d3 adds r3, r2, r3 800142e: 3304 adds r3, #4 8001430: 681b ldr r3, [r3, #0] 8001432: 1dfa adds r2, r7, #7 8001434: 7812 ldrb r2, [r2, #0] 8001436: 0011 movs r1, r2 8001438: 2203 movs r2, #3 800143a: 400a ands r2, r1 800143c: 00d2 lsls r2, r2, #3 800143e: 21ff movs r1, #255 ; 0xff 8001440: 4091 lsls r1, r2 8001442: 000a movs r2, r1 8001444: 43d2 mvns r2, r2 8001446: 401a ands r2, r3 8001448: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800144a: 683b ldr r3, [r7, #0] 800144c: 019b lsls r3, r3, #6 800144e: 22ff movs r2, #255 ; 0xff 8001450: 401a ands r2, r3 8001452: 1dfb adds r3, r7, #7 8001454: 781b ldrb r3, [r3, #0] 8001456: 0018 movs r0, r3 8001458: 2303 movs r3, #3 800145a: 4003 ands r3, r0 800145c: 00db lsls r3, r3, #3 800145e: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001460: 4809 ldr r0, [pc, #36] ; (8001488 <__NVIC_SetPriority+0xd8>) 8001462: 1dfb adds r3, r7, #7 8001464: 781b ldrb r3, [r3, #0] 8001466: 001c movs r4, r3 8001468: 230f movs r3, #15 800146a: 4023 ands r3, r4 800146c: 3b08 subs r3, #8 800146e: 089b lsrs r3, r3, #2 8001470: 430a orrs r2, r1 8001472: 3306 adds r3, #6 8001474: 009b lsls r3, r3, #2 8001476: 18c3 adds r3, r0, r3 8001478: 3304 adds r3, #4 800147a: 601a str r2, [r3, #0] } 800147c: 46c0 nop ; (mov r8, r8) 800147e: 46bd mov sp, r7 8001480: b003 add sp, #12 8001482: bd90 pop {r4, r7, pc} 8001484: e000e100 .word 0xe000e100 8001488: e000ed00 .word 0xe000ed00 0800148c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800148c: b580 push {r7, lr} 800148e: b082 sub sp, #8 8001490: af00 add r7, sp, #0 8001492: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001494: 687b ldr r3, [r7, #4] 8001496: 1e5a subs r2, r3, #1 8001498: 2380 movs r3, #128 ; 0x80 800149a: 045b lsls r3, r3, #17 800149c: 429a cmp r2, r3 800149e: d301 bcc.n 80014a4 { return (1UL); /* Reload value impossible */ 80014a0: 2301 movs r3, #1 80014a2: e010 b.n 80014c6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80014a4: 4b0a ldr r3, [pc, #40] ; (80014d0 ) 80014a6: 687a ldr r2, [r7, #4] 80014a8: 3a01 subs r2, #1 80014aa: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80014ac: 2301 movs r3, #1 80014ae: 425b negs r3, r3 80014b0: 2103 movs r1, #3 80014b2: 0018 movs r0, r3 80014b4: f7ff ff7c bl 80013b0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80014b8: 4b05 ldr r3, [pc, #20] ; (80014d0 ) 80014ba: 2200 movs r2, #0 80014bc: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80014be: 4b04 ldr r3, [pc, #16] ; (80014d0 ) 80014c0: 2207 movs r2, #7 80014c2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80014c4: 2300 movs r3, #0 } 80014c6: 0018 movs r0, r3 80014c8: 46bd mov sp, r7 80014ca: b002 add sp, #8 80014cc: bd80 pop {r7, pc} 80014ce: 46c0 nop ; (mov r8, r8) 80014d0: e000e010 .word 0xe000e010 080014d4 : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80014d4: b580 push {r7, lr} 80014d6: b084 sub sp, #16 80014d8: af00 add r7, sp, #0 80014da: 60b9 str r1, [r7, #8] 80014dc: 607a str r2, [r7, #4] 80014de: 210f movs r1, #15 80014e0: 187b adds r3, r7, r1 80014e2: 1c02 adds r2, r0, #0 80014e4: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 80014e6: 68ba ldr r2, [r7, #8] 80014e8: 187b adds r3, r7, r1 80014ea: 781b ldrb r3, [r3, #0] 80014ec: b25b sxtb r3, r3 80014ee: 0011 movs r1, r2 80014f0: 0018 movs r0, r3 80014f2: f7ff ff5d bl 80013b0 <__NVIC_SetPriority> } 80014f6: 46c0 nop ; (mov r8, r8) 80014f8: 46bd mov sp, r7 80014fa: b004 add sp, #16 80014fc: bd80 pop {r7, pc} 080014fe : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80014fe: b580 push {r7, lr} 8001500: b082 sub sp, #8 8001502: af00 add r7, sp, #0 8001504: 0002 movs r2, r0 8001506: 1dfb adds r3, r7, #7 8001508: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800150a: 1dfb adds r3, r7, #7 800150c: 781b ldrb r3, [r3, #0] 800150e: b25b sxtb r3, r3 8001510: 0018 movs r0, r3 8001512: f7ff ff33 bl 800137c <__NVIC_EnableIRQ> } 8001516: 46c0 nop ; (mov r8, r8) 8001518: 46bd mov sp, r7 800151a: b002 add sp, #8 800151c: bd80 pop {r7, pc} 0800151e : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800151e: b580 push {r7, lr} 8001520: b082 sub sp, #8 8001522: af00 add r7, sp, #0 8001524: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001526: 687b ldr r3, [r7, #4] 8001528: 0018 movs r0, r3 800152a: f7ff ffaf bl 800148c 800152e: 0003 movs r3, r0 } 8001530: 0018 movs r0, r3 8001532: 46bd mov sp, r7 8001534: b002 add sp, #8 8001536: bd80 pop {r7, pc} 08001538 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001538: b580 push {r7, lr} 800153a: b086 sub sp, #24 800153c: af00 add r7, sp, #0 800153e: 6078 str r0, [r7, #4] 8001540: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8001542: 2300 movs r3, #0 8001544: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8001546: e14f b.n 80017e8 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8001548: 683b ldr r3, [r7, #0] 800154a: 681b ldr r3, [r3, #0] 800154c: 2101 movs r1, #1 800154e: 697a ldr r2, [r7, #20] 8001550: 4091 lsls r1, r2 8001552: 000a movs r2, r1 8001554: 4013 ands r3, r2 8001556: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8001558: 68fb ldr r3, [r7, #12] 800155a: 2b00 cmp r3, #0 800155c: d100 bne.n 8001560 800155e: e140 b.n 80017e2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001560: 683b ldr r3, [r7, #0] 8001562: 685b ldr r3, [r3, #4] 8001564: 2203 movs r2, #3 8001566: 4013 ands r3, r2 8001568: 2b01 cmp r3, #1 800156a: d005 beq.n 8001578 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800156c: 683b ldr r3, [r7, #0] 800156e: 685b ldr r3, [r3, #4] 8001570: 2203 movs r2, #3 8001572: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001574: 2b02 cmp r3, #2 8001576: d130 bne.n 80015da { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001578: 687b ldr r3, [r7, #4] 800157a: 689b ldr r3, [r3, #8] 800157c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 800157e: 697b ldr r3, [r7, #20] 8001580: 005b lsls r3, r3, #1 8001582: 2203 movs r2, #3 8001584: 409a lsls r2, r3 8001586: 0013 movs r3, r2 8001588: 43da mvns r2, r3 800158a: 693b ldr r3, [r7, #16] 800158c: 4013 ands r3, r2 800158e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8001590: 683b ldr r3, [r7, #0] 8001592: 68da ldr r2, [r3, #12] 8001594: 697b ldr r3, [r7, #20] 8001596: 005b lsls r3, r3, #1 8001598: 409a lsls r2, r3 800159a: 0013 movs r3, r2 800159c: 693a ldr r2, [r7, #16] 800159e: 4313 orrs r3, r2 80015a0: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80015a2: 687b ldr r3, [r7, #4] 80015a4: 693a ldr r2, [r7, #16] 80015a6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80015a8: 687b ldr r3, [r7, #4] 80015aa: 685b ldr r3, [r3, #4] 80015ac: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80015ae: 2201 movs r2, #1 80015b0: 697b ldr r3, [r7, #20] 80015b2: 409a lsls r2, r3 80015b4: 0013 movs r3, r2 80015b6: 43da mvns r2, r3 80015b8: 693b ldr r3, [r7, #16] 80015ba: 4013 ands r3, r2 80015bc: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80015be: 683b ldr r3, [r7, #0] 80015c0: 685b ldr r3, [r3, #4] 80015c2: 091b lsrs r3, r3, #4 80015c4: 2201 movs r2, #1 80015c6: 401a ands r2, r3 80015c8: 697b ldr r3, [r7, #20] 80015ca: 409a lsls r2, r3 80015cc: 0013 movs r3, r2 80015ce: 693a ldr r2, [r7, #16] 80015d0: 4313 orrs r3, r2 80015d2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80015d4: 687b ldr r3, [r7, #4] 80015d6: 693a ldr r2, [r7, #16] 80015d8: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80015da: 683b ldr r3, [r7, #0] 80015dc: 685b ldr r3, [r3, #4] 80015de: 2203 movs r2, #3 80015e0: 4013 ands r3, r2 80015e2: 2b03 cmp r3, #3 80015e4: d017 beq.n 8001616 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80015e6: 687b ldr r3, [r7, #4] 80015e8: 68db ldr r3, [r3, #12] 80015ea: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 80015ec: 697b ldr r3, [r7, #20] 80015ee: 005b lsls r3, r3, #1 80015f0: 2203 movs r2, #3 80015f2: 409a lsls r2, r3 80015f4: 0013 movs r3, r2 80015f6: 43da mvns r2, r3 80015f8: 693b ldr r3, [r7, #16] 80015fa: 4013 ands r3, r2 80015fc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 80015fe: 683b ldr r3, [r7, #0] 8001600: 689a ldr r2, [r3, #8] 8001602: 697b ldr r3, [r7, #20] 8001604: 005b lsls r3, r3, #1 8001606: 409a lsls r2, r3 8001608: 0013 movs r3, r2 800160a: 693a ldr r2, [r7, #16] 800160c: 4313 orrs r3, r2 800160e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001610: 687b ldr r3, [r7, #4] 8001612: 693a ldr r2, [r7, #16] 8001614: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001616: 683b ldr r3, [r7, #0] 8001618: 685b ldr r3, [r3, #4] 800161a: 2203 movs r2, #3 800161c: 4013 ands r3, r2 800161e: 2b02 cmp r3, #2 8001620: d123 bne.n 800166a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8001622: 697b ldr r3, [r7, #20] 8001624: 08da lsrs r2, r3, #3 8001626: 687b ldr r3, [r7, #4] 8001628: 3208 adds r2, #8 800162a: 0092 lsls r2, r2, #2 800162c: 58d3 ldr r3, [r2, r3] 800162e: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001630: 697b ldr r3, [r7, #20] 8001632: 2207 movs r2, #7 8001634: 4013 ands r3, r2 8001636: 009b lsls r3, r3, #2 8001638: 220f movs r2, #15 800163a: 409a lsls r2, r3 800163c: 0013 movs r3, r2 800163e: 43da mvns r2, r3 8001640: 693b ldr r3, [r7, #16] 8001642: 4013 ands r3, r2 8001644: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8001646: 683b ldr r3, [r7, #0] 8001648: 691a ldr r2, [r3, #16] 800164a: 697b ldr r3, [r7, #20] 800164c: 2107 movs r1, #7 800164e: 400b ands r3, r1 8001650: 009b lsls r3, r3, #2 8001652: 409a lsls r2, r3 8001654: 0013 movs r3, r2 8001656: 693a ldr r2, [r7, #16] 8001658: 4313 orrs r3, r2 800165a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 800165c: 697b ldr r3, [r7, #20] 800165e: 08da lsrs r2, r3, #3 8001660: 687b ldr r3, [r7, #4] 8001662: 3208 adds r2, #8 8001664: 0092 lsls r2, r2, #2 8001666: 6939 ldr r1, [r7, #16] 8001668: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800166a: 687b ldr r3, [r7, #4] 800166c: 681b ldr r3, [r3, #0] 800166e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8001670: 697b ldr r3, [r7, #20] 8001672: 005b lsls r3, r3, #1 8001674: 2203 movs r2, #3 8001676: 409a lsls r2, r3 8001678: 0013 movs r3, r2 800167a: 43da mvns r2, r3 800167c: 693b ldr r3, [r7, #16] 800167e: 4013 ands r3, r2 8001680: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8001682: 683b ldr r3, [r7, #0] 8001684: 685b ldr r3, [r3, #4] 8001686: 2203 movs r2, #3 8001688: 401a ands r2, r3 800168a: 697b ldr r3, [r7, #20] 800168c: 005b lsls r3, r3, #1 800168e: 409a lsls r2, r3 8001690: 0013 movs r3, r2 8001692: 693a ldr r2, [r7, #16] 8001694: 4313 orrs r3, r2 8001696: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001698: 687b ldr r3, [r7, #4] 800169a: 693a ldr r2, [r7, #16] 800169c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 800169e: 683b ldr r3, [r7, #0] 80016a0: 685a ldr r2, [r3, #4] 80016a2: 23c0 movs r3, #192 ; 0xc0 80016a4: 029b lsls r3, r3, #10 80016a6: 4013 ands r3, r2 80016a8: d100 bne.n 80016ac 80016aa: e09a b.n 80017e2 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80016ac: 4b54 ldr r3, [pc, #336] ; (8001800 ) 80016ae: 699a ldr r2, [r3, #24] 80016b0: 4b53 ldr r3, [pc, #332] ; (8001800 ) 80016b2: 2101 movs r1, #1 80016b4: 430a orrs r2, r1 80016b6: 619a str r2, [r3, #24] 80016b8: 4b51 ldr r3, [pc, #324] ; (8001800 ) 80016ba: 699b ldr r3, [r3, #24] 80016bc: 2201 movs r2, #1 80016be: 4013 ands r3, r2 80016c0: 60bb str r3, [r7, #8] 80016c2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 80016c4: 4a4f ldr r2, [pc, #316] ; (8001804 ) 80016c6: 697b ldr r3, [r7, #20] 80016c8: 089b lsrs r3, r3, #2 80016ca: 3302 adds r3, #2 80016cc: 009b lsls r3, r3, #2 80016ce: 589b ldr r3, [r3, r2] 80016d0: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80016d2: 697b ldr r3, [r7, #20] 80016d4: 2203 movs r2, #3 80016d6: 4013 ands r3, r2 80016d8: 009b lsls r3, r3, #2 80016da: 220f movs r2, #15 80016dc: 409a lsls r2, r3 80016de: 0013 movs r3, r2 80016e0: 43da mvns r2, r3 80016e2: 693b ldr r3, [r7, #16] 80016e4: 4013 ands r3, r2 80016e6: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 80016e8: 687a ldr r2, [r7, #4] 80016ea: 2390 movs r3, #144 ; 0x90 80016ec: 05db lsls r3, r3, #23 80016ee: 429a cmp r2, r3 80016f0: d013 beq.n 800171a 80016f2: 687b ldr r3, [r7, #4] 80016f4: 4a44 ldr r2, [pc, #272] ; (8001808 ) 80016f6: 4293 cmp r3, r2 80016f8: d00d beq.n 8001716 80016fa: 687b ldr r3, [r7, #4] 80016fc: 4a43 ldr r2, [pc, #268] ; (800180c ) 80016fe: 4293 cmp r3, r2 8001700: d007 beq.n 8001712 8001702: 687b ldr r3, [r7, #4] 8001704: 4a42 ldr r2, [pc, #264] ; (8001810 ) 8001706: 4293 cmp r3, r2 8001708: d101 bne.n 800170e 800170a: 2303 movs r3, #3 800170c: e006 b.n 800171c 800170e: 2305 movs r3, #5 8001710: e004 b.n 800171c 8001712: 2302 movs r3, #2 8001714: e002 b.n 800171c 8001716: 2301 movs r3, #1 8001718: e000 b.n 800171c 800171a: 2300 movs r3, #0 800171c: 697a ldr r2, [r7, #20] 800171e: 2103 movs r1, #3 8001720: 400a ands r2, r1 8001722: 0092 lsls r2, r2, #2 8001724: 4093 lsls r3, r2 8001726: 693a ldr r2, [r7, #16] 8001728: 4313 orrs r3, r2 800172a: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 800172c: 4935 ldr r1, [pc, #212] ; (8001804 ) 800172e: 697b ldr r3, [r7, #20] 8001730: 089b lsrs r3, r3, #2 8001732: 3302 adds r3, #2 8001734: 009b lsls r3, r3, #2 8001736: 693a ldr r2, [r7, #16] 8001738: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ temp = EXTI->IMR; 800173a: 4b36 ldr r3, [pc, #216] ; (8001814 ) 800173c: 681b ldr r3, [r3, #0] 800173e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001740: 68fb ldr r3, [r7, #12] 8001742: 43da mvns r2, r3 8001744: 693b ldr r3, [r7, #16] 8001746: 4013 ands r3, r2 8001748: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 800174a: 683b ldr r3, [r7, #0] 800174c: 685a ldr r2, [r3, #4] 800174e: 2380 movs r3, #128 ; 0x80 8001750: 025b lsls r3, r3, #9 8001752: 4013 ands r3, r2 8001754: d003 beq.n 800175e { temp |= iocurrent; 8001756: 693a ldr r2, [r7, #16] 8001758: 68fb ldr r3, [r7, #12] 800175a: 4313 orrs r3, r2 800175c: 613b str r3, [r7, #16] } EXTI->IMR = temp; 800175e: 4b2d ldr r3, [pc, #180] ; (8001814 ) 8001760: 693a ldr r2, [r7, #16] 8001762: 601a str r2, [r3, #0] temp = EXTI->EMR; 8001764: 4b2b ldr r3, [pc, #172] ; (8001814 ) 8001766: 685b ldr r3, [r3, #4] 8001768: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800176a: 68fb ldr r3, [r7, #12] 800176c: 43da mvns r2, r3 800176e: 693b ldr r3, [r7, #16] 8001770: 4013 ands r3, r2 8001772: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8001774: 683b ldr r3, [r7, #0] 8001776: 685a ldr r2, [r3, #4] 8001778: 2380 movs r3, #128 ; 0x80 800177a: 029b lsls r3, r3, #10 800177c: 4013 ands r3, r2 800177e: d003 beq.n 8001788 { temp |= iocurrent; 8001780: 693a ldr r2, [r7, #16] 8001782: 68fb ldr r3, [r7, #12] 8001784: 4313 orrs r3, r2 8001786: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8001788: 4b22 ldr r3, [pc, #136] ; (8001814 ) 800178a: 693a ldr r2, [r7, #16] 800178c: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 800178e: 4b21 ldr r3, [pc, #132] ; (8001814 ) 8001790: 689b ldr r3, [r3, #8] 8001792: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001794: 68fb ldr r3, [r7, #12] 8001796: 43da mvns r2, r3 8001798: 693b ldr r3, [r7, #16] 800179a: 4013 ands r3, r2 800179c: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 800179e: 683b ldr r3, [r7, #0] 80017a0: 685a ldr r2, [r3, #4] 80017a2: 2380 movs r3, #128 ; 0x80 80017a4: 035b lsls r3, r3, #13 80017a6: 4013 ands r3, r2 80017a8: d003 beq.n 80017b2 { temp |= iocurrent; 80017aa: 693a ldr r2, [r7, #16] 80017ac: 68fb ldr r3, [r7, #12] 80017ae: 4313 orrs r3, r2 80017b0: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 80017b2: 4b18 ldr r3, [pc, #96] ; (8001814 ) 80017b4: 693a ldr r2, [r7, #16] 80017b6: 609a str r2, [r3, #8] temp = EXTI->FTSR; 80017b8: 4b16 ldr r3, [pc, #88] ; (8001814 ) 80017ba: 68db ldr r3, [r3, #12] 80017bc: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80017be: 68fb ldr r3, [r7, #12] 80017c0: 43da mvns r2, r3 80017c2: 693b ldr r3, [r7, #16] 80017c4: 4013 ands r3, r2 80017c6: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 80017c8: 683b ldr r3, [r7, #0] 80017ca: 685a ldr r2, [r3, #4] 80017cc: 2380 movs r3, #128 ; 0x80 80017ce: 039b lsls r3, r3, #14 80017d0: 4013 ands r3, r2 80017d2: d003 beq.n 80017dc { temp |= iocurrent; 80017d4: 693a ldr r2, [r7, #16] 80017d6: 68fb ldr r3, [r7, #12] 80017d8: 4313 orrs r3, r2 80017da: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 80017dc: 4b0d ldr r3, [pc, #52] ; (8001814 ) 80017de: 693a ldr r2, [r7, #16] 80017e0: 60da str r2, [r3, #12] } } position++; 80017e2: 697b ldr r3, [r7, #20] 80017e4: 3301 adds r3, #1 80017e6: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 80017e8: 683b ldr r3, [r7, #0] 80017ea: 681a ldr r2, [r3, #0] 80017ec: 697b ldr r3, [r7, #20] 80017ee: 40da lsrs r2, r3 80017f0: 1e13 subs r3, r2, #0 80017f2: d000 beq.n 80017f6 80017f4: e6a8 b.n 8001548 } } 80017f6: 46c0 nop ; (mov r8, r8) 80017f8: 46c0 nop ; (mov r8, r8) 80017fa: 46bd mov sp, r7 80017fc: b006 add sp, #24 80017fe: bd80 pop {r7, pc} 8001800: 40021000 .word 0x40021000 8001804: 40010000 .word 0x40010000 8001808: 48000400 .word 0x48000400 800180c: 48000800 .word 0x48000800 8001810: 48000c00 .word 0x48000c00 8001814: 40010400 .word 0x40010400 08001818 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001818: b580 push {r7, lr} 800181a: b084 sub sp, #16 800181c: af00 add r7, sp, #0 800181e: 6078 str r0, [r7, #4] 8001820: 000a movs r2, r1 8001822: 1cbb adds r3, r7, #2 8001824: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001826: 687b ldr r3, [r7, #4] 8001828: 691b ldr r3, [r3, #16] 800182a: 1cba adds r2, r7, #2 800182c: 8812 ldrh r2, [r2, #0] 800182e: 4013 ands r3, r2 8001830: d004 beq.n 800183c { bitstatus = GPIO_PIN_SET; 8001832: 230f movs r3, #15 8001834: 18fb adds r3, r7, r3 8001836: 2201 movs r2, #1 8001838: 701a strb r2, [r3, #0] 800183a: e003 b.n 8001844 } else { bitstatus = GPIO_PIN_RESET; 800183c: 230f movs r3, #15 800183e: 18fb adds r3, r7, r3 8001840: 2200 movs r2, #0 8001842: 701a strb r2, [r3, #0] } return bitstatus; 8001844: 230f movs r3, #15 8001846: 18fb adds r3, r7, r3 8001848: 781b ldrb r3, [r3, #0] } 800184a: 0018 movs r0, r3 800184c: 46bd mov sp, r7 800184e: b004 add sp, #16 8001850: bd80 pop {r7, pc} 08001852 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001852: b580 push {r7, lr} 8001854: b082 sub sp, #8 8001856: af00 add r7, sp, #0 8001858: 6078 str r0, [r7, #4] 800185a: 0008 movs r0, r1 800185c: 0011 movs r1, r2 800185e: 1cbb adds r3, r7, #2 8001860: 1c02 adds r2, r0, #0 8001862: 801a strh r2, [r3, #0] 8001864: 1c7b adds r3, r7, #1 8001866: 1c0a adds r2, r1, #0 8001868: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800186a: 1c7b adds r3, r7, #1 800186c: 781b ldrb r3, [r3, #0] 800186e: 2b00 cmp r3, #0 8001870: d004 beq.n 800187c { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001872: 1cbb adds r3, r7, #2 8001874: 881a ldrh r2, [r3, #0] 8001876: 687b ldr r3, [r7, #4] 8001878: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 800187a: e003 b.n 8001884 GPIOx->BRR = (uint32_t)GPIO_Pin; 800187c: 1cbb adds r3, r7, #2 800187e: 881a ldrh r2, [r3, #0] 8001880: 687b ldr r3, [r7, #4] 8001882: 629a str r2, [r3, #40] ; 0x28 } 8001884: 46c0 nop ; (mov r8, r8) 8001886: 46bd mov sp, r7 8001888: b002 add sp, #8 800188a: bd80 pop {r7, pc} 0800188c : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800188c: b580 push {r7, lr} 800188e: b082 sub sp, #8 8001890: af00 add r7, sp, #0 8001892: 0002 movs r2, r0 8001894: 1dbb adds r3, r7, #6 8001896: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 8001898: 4b09 ldr r3, [pc, #36] ; (80018c0 ) 800189a: 695b ldr r3, [r3, #20] 800189c: 1dba adds r2, r7, #6 800189e: 8812 ldrh r2, [r2, #0] 80018a0: 4013 ands r3, r2 80018a2: d008 beq.n 80018b6 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 80018a4: 4b06 ldr r3, [pc, #24] ; (80018c0 ) 80018a6: 1dba adds r2, r7, #6 80018a8: 8812 ldrh r2, [r2, #0] 80018aa: 615a str r2, [r3, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 80018ac: 1dbb adds r3, r7, #6 80018ae: 881b ldrh r3, [r3, #0] 80018b0: 0018 movs r0, r3 80018b2: f002 fa53 bl 8003d5c } } 80018b6: 46c0 nop ; (mov r8, r8) 80018b8: 46bd mov sp, r7 80018ba: b002 add sp, #8 80018bc: bd80 pop {r7, pc} 80018be: 46c0 nop ; (mov r8, r8) 80018c0: 40010400 .word 0x40010400 080018c4 : * @note For all I2C2 pins fast mode plus driving capability can be enabled * only by using I2C_FASTMODEPLUS_I2C2 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) { 80018c4: b580 push {r7, lr} 80018c6: b084 sub sp, #16 80018c8: af00 add r7, sp, #0 80018ca: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80018cc: 4b0a ldr r3, [pc, #40] ; (80018f8 ) 80018ce: 699a ldr r2, [r3, #24] 80018d0: 4b09 ldr r3, [pc, #36] ; (80018f8 ) 80018d2: 2101 movs r1, #1 80018d4: 430a orrs r2, r1 80018d6: 619a str r2, [r3, #24] 80018d8: 4b07 ldr r3, [pc, #28] ; (80018f8 ) 80018da: 699b ldr r3, [r3, #24] 80018dc: 2201 movs r2, #1 80018de: 4013 ands r3, r2 80018e0: 60fb str r3, [r7, #12] 80018e2: 68fb ldr r3, [r7, #12] /* Enable fast mode plus driving capability for selected pin */ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 80018e4: 4b05 ldr r3, [pc, #20] ; (80018fc ) 80018e6: 6819 ldr r1, [r3, #0] 80018e8: 4b04 ldr r3, [pc, #16] ; (80018fc ) 80018ea: 687a ldr r2, [r7, #4] 80018ec: 430a orrs r2, r1 80018ee: 601a str r2, [r3, #0] } 80018f0: 46c0 nop ; (mov r8, r8) 80018f2: 46bd mov sp, r7 80018f4: b004 add sp, #16 80018f6: bd80 pop {r7, pc} 80018f8: 40021000 .word 0x40021000 80018fc: 40010000 .word 0x40010000 08001900 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001900: b580 push {r7, lr} 8001902: b088 sub sp, #32 8001904: af00 add r7, sp, #0 8001906: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8001908: 687b ldr r3, [r7, #4] 800190a: 2b00 cmp r3, #0 800190c: d101 bne.n 8001912 { return HAL_ERROR; 800190e: 2301 movs r3, #1 8001910: e301 b.n 8001f16 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8001912: 687b ldr r3, [r7, #4] 8001914: 681b ldr r3, [r3, #0] 8001916: 2201 movs r2, #1 8001918: 4013 ands r3, r2 800191a: d100 bne.n 800191e 800191c: e08d b.n 8001a3a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800191e: 4bc3 ldr r3, [pc, #780] ; (8001c2c ) 8001920: 685b ldr r3, [r3, #4] 8001922: 220c movs r2, #12 8001924: 4013 ands r3, r2 8001926: 2b04 cmp r3, #4 8001928: d00e beq.n 8001948 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800192a: 4bc0 ldr r3, [pc, #768] ; (8001c2c ) 800192c: 685b ldr r3, [r3, #4] 800192e: 220c movs r2, #12 8001930: 4013 ands r3, r2 8001932: 2b08 cmp r3, #8 8001934: d116 bne.n 8001964 8001936: 4bbd ldr r3, [pc, #756] ; (8001c2c ) 8001938: 685a ldr r2, [r3, #4] 800193a: 2380 movs r3, #128 ; 0x80 800193c: 025b lsls r3, r3, #9 800193e: 401a ands r2, r3 8001940: 2380 movs r3, #128 ; 0x80 8001942: 025b lsls r3, r3, #9 8001944: 429a cmp r2, r3 8001946: d10d bne.n 8001964 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001948: 4bb8 ldr r3, [pc, #736] ; (8001c2c ) 800194a: 681a ldr r2, [r3, #0] 800194c: 2380 movs r3, #128 ; 0x80 800194e: 029b lsls r3, r3, #10 8001950: 4013 ands r3, r2 8001952: d100 bne.n 8001956 8001954: e070 b.n 8001a38 8001956: 687b ldr r3, [r7, #4] 8001958: 685b ldr r3, [r3, #4] 800195a: 2b00 cmp r3, #0 800195c: d000 beq.n 8001960 800195e: e06b b.n 8001a38 { return HAL_ERROR; 8001960: 2301 movs r3, #1 8001962: e2d8 b.n 8001f16 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001964: 687b ldr r3, [r7, #4] 8001966: 685b ldr r3, [r3, #4] 8001968: 2b01 cmp r3, #1 800196a: d107 bne.n 800197c 800196c: 4baf ldr r3, [pc, #700] ; (8001c2c ) 800196e: 681a ldr r2, [r3, #0] 8001970: 4bae ldr r3, [pc, #696] ; (8001c2c ) 8001972: 2180 movs r1, #128 ; 0x80 8001974: 0249 lsls r1, r1, #9 8001976: 430a orrs r2, r1 8001978: 601a str r2, [r3, #0] 800197a: e02f b.n 80019dc 800197c: 687b ldr r3, [r7, #4] 800197e: 685b ldr r3, [r3, #4] 8001980: 2b00 cmp r3, #0 8001982: d10c bne.n 800199e 8001984: 4ba9 ldr r3, [pc, #676] ; (8001c2c ) 8001986: 681a ldr r2, [r3, #0] 8001988: 4ba8 ldr r3, [pc, #672] ; (8001c2c ) 800198a: 49a9 ldr r1, [pc, #676] ; (8001c30 ) 800198c: 400a ands r2, r1 800198e: 601a str r2, [r3, #0] 8001990: 4ba6 ldr r3, [pc, #664] ; (8001c2c ) 8001992: 681a ldr r2, [r3, #0] 8001994: 4ba5 ldr r3, [pc, #660] ; (8001c2c ) 8001996: 49a7 ldr r1, [pc, #668] ; (8001c34 ) 8001998: 400a ands r2, r1 800199a: 601a str r2, [r3, #0] 800199c: e01e b.n 80019dc 800199e: 687b ldr r3, [r7, #4] 80019a0: 685b ldr r3, [r3, #4] 80019a2: 2b05 cmp r3, #5 80019a4: d10e bne.n 80019c4 80019a6: 4ba1 ldr r3, [pc, #644] ; (8001c2c ) 80019a8: 681a ldr r2, [r3, #0] 80019aa: 4ba0 ldr r3, [pc, #640] ; (8001c2c ) 80019ac: 2180 movs r1, #128 ; 0x80 80019ae: 02c9 lsls r1, r1, #11 80019b0: 430a orrs r2, r1 80019b2: 601a str r2, [r3, #0] 80019b4: 4b9d ldr r3, [pc, #628] ; (8001c2c ) 80019b6: 681a ldr r2, [r3, #0] 80019b8: 4b9c ldr r3, [pc, #624] ; (8001c2c ) 80019ba: 2180 movs r1, #128 ; 0x80 80019bc: 0249 lsls r1, r1, #9 80019be: 430a orrs r2, r1 80019c0: 601a str r2, [r3, #0] 80019c2: e00b b.n 80019dc 80019c4: 4b99 ldr r3, [pc, #612] ; (8001c2c ) 80019c6: 681a ldr r2, [r3, #0] 80019c8: 4b98 ldr r3, [pc, #608] ; (8001c2c ) 80019ca: 4999 ldr r1, [pc, #612] ; (8001c30 ) 80019cc: 400a ands r2, r1 80019ce: 601a str r2, [r3, #0] 80019d0: 4b96 ldr r3, [pc, #600] ; (8001c2c ) 80019d2: 681a ldr r2, [r3, #0] 80019d4: 4b95 ldr r3, [pc, #596] ; (8001c2c ) 80019d6: 4997 ldr r1, [pc, #604] ; (8001c34 ) 80019d8: 400a ands r2, r1 80019da: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80019dc: 687b ldr r3, [r7, #4] 80019de: 685b ldr r3, [r3, #4] 80019e0: 2b00 cmp r3, #0 80019e2: d014 beq.n 8001a0e { /* Get Start Tick */ tickstart = HAL_GetTick(); 80019e4: f7ff f810 bl 8000a08 80019e8: 0003 movs r3, r0 80019ea: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80019ec: e008 b.n 8001a00 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80019ee: f7ff f80b bl 8000a08 80019f2: 0002 movs r2, r0 80019f4: 69bb ldr r3, [r7, #24] 80019f6: 1ad3 subs r3, r2, r3 80019f8: 2b64 cmp r3, #100 ; 0x64 80019fa: d901 bls.n 8001a00 { return HAL_TIMEOUT; 80019fc: 2303 movs r3, #3 80019fe: e28a b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001a00: 4b8a ldr r3, [pc, #552] ; (8001c2c ) 8001a02: 681a ldr r2, [r3, #0] 8001a04: 2380 movs r3, #128 ; 0x80 8001a06: 029b lsls r3, r3, #10 8001a08: 4013 ands r3, r2 8001a0a: d0f0 beq.n 80019ee 8001a0c: e015 b.n 8001a3a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a0e: f7fe fffb bl 8000a08 8001a12: 0003 movs r3, r0 8001a14: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001a16: e008 b.n 8001a2a { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001a18: f7fe fff6 bl 8000a08 8001a1c: 0002 movs r2, r0 8001a1e: 69bb ldr r3, [r7, #24] 8001a20: 1ad3 subs r3, r2, r3 8001a22: 2b64 cmp r3, #100 ; 0x64 8001a24: d901 bls.n 8001a2a { return HAL_TIMEOUT; 8001a26: 2303 movs r3, #3 8001a28: e275 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001a2a: 4b80 ldr r3, [pc, #512] ; (8001c2c ) 8001a2c: 681a ldr r2, [r3, #0] 8001a2e: 2380 movs r3, #128 ; 0x80 8001a30: 029b lsls r3, r3, #10 8001a32: 4013 ands r3, r2 8001a34: d1f0 bne.n 8001a18 8001a36: e000 b.n 8001a3a if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001a38: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001a3a: 687b ldr r3, [r7, #4] 8001a3c: 681b ldr r3, [r3, #0] 8001a3e: 2202 movs r2, #2 8001a40: 4013 ands r3, r2 8001a42: d100 bne.n 8001a46 8001a44: e069 b.n 8001b1a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001a46: 4b79 ldr r3, [pc, #484] ; (8001c2c ) 8001a48: 685b ldr r3, [r3, #4] 8001a4a: 220c movs r2, #12 8001a4c: 4013 ands r3, r2 8001a4e: d00b beq.n 8001a68 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8001a50: 4b76 ldr r3, [pc, #472] ; (8001c2c ) 8001a52: 685b ldr r3, [r3, #4] 8001a54: 220c movs r2, #12 8001a56: 4013 ands r3, r2 8001a58: 2b08 cmp r3, #8 8001a5a: d11c bne.n 8001a96 8001a5c: 4b73 ldr r3, [pc, #460] ; (8001c2c ) 8001a5e: 685a ldr r2, [r3, #4] 8001a60: 2380 movs r3, #128 ; 0x80 8001a62: 025b lsls r3, r3, #9 8001a64: 4013 ands r3, r2 8001a66: d116 bne.n 8001a96 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001a68: 4b70 ldr r3, [pc, #448] ; (8001c2c ) 8001a6a: 681b ldr r3, [r3, #0] 8001a6c: 2202 movs r2, #2 8001a6e: 4013 ands r3, r2 8001a70: d005 beq.n 8001a7e 8001a72: 687b ldr r3, [r7, #4] 8001a74: 68db ldr r3, [r3, #12] 8001a76: 2b01 cmp r3, #1 8001a78: d001 beq.n 8001a7e { return HAL_ERROR; 8001a7a: 2301 movs r3, #1 8001a7c: e24b b.n 8001f16 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001a7e: 4b6b ldr r3, [pc, #428] ; (8001c2c ) 8001a80: 681b ldr r3, [r3, #0] 8001a82: 22f8 movs r2, #248 ; 0xf8 8001a84: 4393 bics r3, r2 8001a86: 0019 movs r1, r3 8001a88: 687b ldr r3, [r7, #4] 8001a8a: 691b ldr r3, [r3, #16] 8001a8c: 00da lsls r2, r3, #3 8001a8e: 4b67 ldr r3, [pc, #412] ; (8001c2c ) 8001a90: 430a orrs r2, r1 8001a92: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001a94: e041 b.n 8001b1a } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001a96: 687b ldr r3, [r7, #4] 8001a98: 68db ldr r3, [r3, #12] 8001a9a: 2b00 cmp r3, #0 8001a9c: d024 beq.n 8001ae8 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001a9e: 4b63 ldr r3, [pc, #396] ; (8001c2c ) 8001aa0: 681a ldr r2, [r3, #0] 8001aa2: 4b62 ldr r3, [pc, #392] ; (8001c2c ) 8001aa4: 2101 movs r1, #1 8001aa6: 430a orrs r2, r1 8001aa8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001aaa: f7fe ffad bl 8000a08 8001aae: 0003 movs r3, r0 8001ab0: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001ab2: e008 b.n 8001ac6 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001ab4: f7fe ffa8 bl 8000a08 8001ab8: 0002 movs r2, r0 8001aba: 69bb ldr r3, [r7, #24] 8001abc: 1ad3 subs r3, r2, r3 8001abe: 2b02 cmp r3, #2 8001ac0: d901 bls.n 8001ac6 { return HAL_TIMEOUT; 8001ac2: 2303 movs r3, #3 8001ac4: e227 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001ac6: 4b59 ldr r3, [pc, #356] ; (8001c2c ) 8001ac8: 681b ldr r3, [r3, #0] 8001aca: 2202 movs r2, #2 8001acc: 4013 ands r3, r2 8001ace: d0f1 beq.n 8001ab4 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001ad0: 4b56 ldr r3, [pc, #344] ; (8001c2c ) 8001ad2: 681b ldr r3, [r3, #0] 8001ad4: 22f8 movs r2, #248 ; 0xf8 8001ad6: 4393 bics r3, r2 8001ad8: 0019 movs r1, r3 8001ada: 687b ldr r3, [r7, #4] 8001adc: 691b ldr r3, [r3, #16] 8001ade: 00da lsls r2, r3, #3 8001ae0: 4b52 ldr r3, [pc, #328] ; (8001c2c ) 8001ae2: 430a orrs r2, r1 8001ae4: 601a str r2, [r3, #0] 8001ae6: e018 b.n 8001b1a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001ae8: 4b50 ldr r3, [pc, #320] ; (8001c2c ) 8001aea: 681a ldr r2, [r3, #0] 8001aec: 4b4f ldr r3, [pc, #316] ; (8001c2c ) 8001aee: 2101 movs r1, #1 8001af0: 438a bics r2, r1 8001af2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001af4: f7fe ff88 bl 8000a08 8001af8: 0003 movs r3, r0 8001afa: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001afc: e008 b.n 8001b10 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001afe: f7fe ff83 bl 8000a08 8001b02: 0002 movs r2, r0 8001b04: 69bb ldr r3, [r7, #24] 8001b06: 1ad3 subs r3, r2, r3 8001b08: 2b02 cmp r3, #2 8001b0a: d901 bls.n 8001b10 { return HAL_TIMEOUT; 8001b0c: 2303 movs r3, #3 8001b0e: e202 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001b10: 4b46 ldr r3, [pc, #280] ; (8001c2c ) 8001b12: 681b ldr r3, [r3, #0] 8001b14: 2202 movs r2, #2 8001b16: 4013 ands r3, r2 8001b18: d1f1 bne.n 8001afe } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001b1a: 687b ldr r3, [r7, #4] 8001b1c: 681b ldr r3, [r3, #0] 8001b1e: 2208 movs r2, #8 8001b20: 4013 ands r3, r2 8001b22: d036 beq.n 8001b92 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001b24: 687b ldr r3, [r7, #4] 8001b26: 69db ldr r3, [r3, #28] 8001b28: 2b00 cmp r3, #0 8001b2a: d019 beq.n 8001b60 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001b2c: 4b3f ldr r3, [pc, #252] ; (8001c2c ) 8001b2e: 6a5a ldr r2, [r3, #36] ; 0x24 8001b30: 4b3e ldr r3, [pc, #248] ; (8001c2c ) 8001b32: 2101 movs r1, #1 8001b34: 430a orrs r2, r1 8001b36: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b38: f7fe ff66 bl 8000a08 8001b3c: 0003 movs r3, r0 8001b3e: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001b40: e008 b.n 8001b54 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001b42: f7fe ff61 bl 8000a08 8001b46: 0002 movs r2, r0 8001b48: 69bb ldr r3, [r7, #24] 8001b4a: 1ad3 subs r3, r2, r3 8001b4c: 2b02 cmp r3, #2 8001b4e: d901 bls.n 8001b54 { return HAL_TIMEOUT; 8001b50: 2303 movs r3, #3 8001b52: e1e0 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001b54: 4b35 ldr r3, [pc, #212] ; (8001c2c ) 8001b56: 6a5b ldr r3, [r3, #36] ; 0x24 8001b58: 2202 movs r2, #2 8001b5a: 4013 ands r3, r2 8001b5c: d0f1 beq.n 8001b42 8001b5e: e018 b.n 8001b92 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001b60: 4b32 ldr r3, [pc, #200] ; (8001c2c ) 8001b62: 6a5a ldr r2, [r3, #36] ; 0x24 8001b64: 4b31 ldr r3, [pc, #196] ; (8001c2c ) 8001b66: 2101 movs r1, #1 8001b68: 438a bics r2, r1 8001b6a: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b6c: f7fe ff4c bl 8000a08 8001b70: 0003 movs r3, r0 8001b72: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001b74: e008 b.n 8001b88 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001b76: f7fe ff47 bl 8000a08 8001b7a: 0002 movs r2, r0 8001b7c: 69bb ldr r3, [r7, #24] 8001b7e: 1ad3 subs r3, r2, r3 8001b80: 2b02 cmp r3, #2 8001b82: d901 bls.n 8001b88 { return HAL_TIMEOUT; 8001b84: 2303 movs r3, #3 8001b86: e1c6 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001b88: 4b28 ldr r3, [pc, #160] ; (8001c2c ) 8001b8a: 6a5b ldr r3, [r3, #36] ; 0x24 8001b8c: 2202 movs r2, #2 8001b8e: 4013 ands r3, r2 8001b90: d1f1 bne.n 8001b76 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001b92: 687b ldr r3, [r7, #4] 8001b94: 681b ldr r3, [r3, #0] 8001b96: 2204 movs r2, #4 8001b98: 4013 ands r3, r2 8001b9a: d100 bne.n 8001b9e 8001b9c: e0b4 b.n 8001d08 { FlagStatus pwrclkchanged = RESET; 8001b9e: 201f movs r0, #31 8001ba0: 183b adds r3, r7, r0 8001ba2: 2200 movs r2, #0 8001ba4: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001ba6: 4b21 ldr r3, [pc, #132] ; (8001c2c ) 8001ba8: 69da ldr r2, [r3, #28] 8001baa: 2380 movs r3, #128 ; 0x80 8001bac: 055b lsls r3, r3, #21 8001bae: 4013 ands r3, r2 8001bb0: d110 bne.n 8001bd4 { __HAL_RCC_PWR_CLK_ENABLE(); 8001bb2: 4b1e ldr r3, [pc, #120] ; (8001c2c ) 8001bb4: 69da ldr r2, [r3, #28] 8001bb6: 4b1d ldr r3, [pc, #116] ; (8001c2c ) 8001bb8: 2180 movs r1, #128 ; 0x80 8001bba: 0549 lsls r1, r1, #21 8001bbc: 430a orrs r2, r1 8001bbe: 61da str r2, [r3, #28] 8001bc0: 4b1a ldr r3, [pc, #104] ; (8001c2c ) 8001bc2: 69da ldr r2, [r3, #28] 8001bc4: 2380 movs r3, #128 ; 0x80 8001bc6: 055b lsls r3, r3, #21 8001bc8: 4013 ands r3, r2 8001bca: 60fb str r3, [r7, #12] 8001bcc: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8001bce: 183b adds r3, r7, r0 8001bd0: 2201 movs r2, #1 8001bd2: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001bd4: 4b18 ldr r3, [pc, #96] ; (8001c38 ) 8001bd6: 681a ldr r2, [r3, #0] 8001bd8: 2380 movs r3, #128 ; 0x80 8001bda: 005b lsls r3, r3, #1 8001bdc: 4013 ands r3, r2 8001bde: d11a bne.n 8001c16 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001be0: 4b15 ldr r3, [pc, #84] ; (8001c38 ) 8001be2: 681a ldr r2, [r3, #0] 8001be4: 4b14 ldr r3, [pc, #80] ; (8001c38 ) 8001be6: 2180 movs r1, #128 ; 0x80 8001be8: 0049 lsls r1, r1, #1 8001bea: 430a orrs r2, r1 8001bec: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001bee: f7fe ff0b bl 8000a08 8001bf2: 0003 movs r3, r0 8001bf4: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001bf6: e008 b.n 8001c0a { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001bf8: f7fe ff06 bl 8000a08 8001bfc: 0002 movs r2, r0 8001bfe: 69bb ldr r3, [r7, #24] 8001c00: 1ad3 subs r3, r2, r3 8001c02: 2b64 cmp r3, #100 ; 0x64 8001c04: d901 bls.n 8001c0a { return HAL_TIMEOUT; 8001c06: 2303 movs r3, #3 8001c08: e185 b.n 8001f16 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001c0a: 4b0b ldr r3, [pc, #44] ; (8001c38 ) 8001c0c: 681a ldr r2, [r3, #0] 8001c0e: 2380 movs r3, #128 ; 0x80 8001c10: 005b lsls r3, r3, #1 8001c12: 4013 ands r3, r2 8001c14: d0f0 beq.n 8001bf8 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001c16: 687b ldr r3, [r7, #4] 8001c18: 689b ldr r3, [r3, #8] 8001c1a: 2b01 cmp r3, #1 8001c1c: d10e bne.n 8001c3c 8001c1e: 4b03 ldr r3, [pc, #12] ; (8001c2c ) 8001c20: 6a1a ldr r2, [r3, #32] 8001c22: 4b02 ldr r3, [pc, #8] ; (8001c2c ) 8001c24: 2101 movs r1, #1 8001c26: 430a orrs r2, r1 8001c28: 621a str r2, [r3, #32] 8001c2a: e035 b.n 8001c98 8001c2c: 40021000 .word 0x40021000 8001c30: fffeffff .word 0xfffeffff 8001c34: fffbffff .word 0xfffbffff 8001c38: 40007000 .word 0x40007000 8001c3c: 687b ldr r3, [r7, #4] 8001c3e: 689b ldr r3, [r3, #8] 8001c40: 2b00 cmp r3, #0 8001c42: d10c bne.n 8001c5e 8001c44: 4bb6 ldr r3, [pc, #728] ; (8001f20 ) 8001c46: 6a1a ldr r2, [r3, #32] 8001c48: 4bb5 ldr r3, [pc, #724] ; (8001f20 ) 8001c4a: 2101 movs r1, #1 8001c4c: 438a bics r2, r1 8001c4e: 621a str r2, [r3, #32] 8001c50: 4bb3 ldr r3, [pc, #716] ; (8001f20 ) 8001c52: 6a1a ldr r2, [r3, #32] 8001c54: 4bb2 ldr r3, [pc, #712] ; (8001f20 ) 8001c56: 2104 movs r1, #4 8001c58: 438a bics r2, r1 8001c5a: 621a str r2, [r3, #32] 8001c5c: e01c b.n 8001c98 8001c5e: 687b ldr r3, [r7, #4] 8001c60: 689b ldr r3, [r3, #8] 8001c62: 2b05 cmp r3, #5 8001c64: d10c bne.n 8001c80 8001c66: 4bae ldr r3, [pc, #696] ; (8001f20 ) 8001c68: 6a1a ldr r2, [r3, #32] 8001c6a: 4bad ldr r3, [pc, #692] ; (8001f20 ) 8001c6c: 2104 movs r1, #4 8001c6e: 430a orrs r2, r1 8001c70: 621a str r2, [r3, #32] 8001c72: 4bab ldr r3, [pc, #684] ; (8001f20 ) 8001c74: 6a1a ldr r2, [r3, #32] 8001c76: 4baa ldr r3, [pc, #680] ; (8001f20 ) 8001c78: 2101 movs r1, #1 8001c7a: 430a orrs r2, r1 8001c7c: 621a str r2, [r3, #32] 8001c7e: e00b b.n 8001c98 8001c80: 4ba7 ldr r3, [pc, #668] ; (8001f20 ) 8001c82: 6a1a ldr r2, [r3, #32] 8001c84: 4ba6 ldr r3, [pc, #664] ; (8001f20 ) 8001c86: 2101 movs r1, #1 8001c88: 438a bics r2, r1 8001c8a: 621a str r2, [r3, #32] 8001c8c: 4ba4 ldr r3, [pc, #656] ; (8001f20 ) 8001c8e: 6a1a ldr r2, [r3, #32] 8001c90: 4ba3 ldr r3, [pc, #652] ; (8001f20 ) 8001c92: 2104 movs r1, #4 8001c94: 438a bics r2, r1 8001c96: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001c98: 687b ldr r3, [r7, #4] 8001c9a: 689b ldr r3, [r3, #8] 8001c9c: 2b00 cmp r3, #0 8001c9e: d014 beq.n 8001cca { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001ca0: f7fe feb2 bl 8000a08 8001ca4: 0003 movs r3, r0 8001ca6: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001ca8: e009 b.n 8001cbe { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001caa: f7fe fead bl 8000a08 8001cae: 0002 movs r2, r0 8001cb0: 69bb ldr r3, [r7, #24] 8001cb2: 1ad3 subs r3, r2, r3 8001cb4: 4a9b ldr r2, [pc, #620] ; (8001f24 ) 8001cb6: 4293 cmp r3, r2 8001cb8: d901 bls.n 8001cbe { return HAL_TIMEOUT; 8001cba: 2303 movs r3, #3 8001cbc: e12b b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001cbe: 4b98 ldr r3, [pc, #608] ; (8001f20 ) 8001cc0: 6a1b ldr r3, [r3, #32] 8001cc2: 2202 movs r2, #2 8001cc4: 4013 ands r3, r2 8001cc6: d0f0 beq.n 8001caa 8001cc8: e013 b.n 8001cf2 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001cca: f7fe fe9d bl 8000a08 8001cce: 0003 movs r3, r0 8001cd0: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001cd2: e009 b.n 8001ce8 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001cd4: f7fe fe98 bl 8000a08 8001cd8: 0002 movs r2, r0 8001cda: 69bb ldr r3, [r7, #24] 8001cdc: 1ad3 subs r3, r2, r3 8001cde: 4a91 ldr r2, [pc, #580] ; (8001f24 ) 8001ce0: 4293 cmp r3, r2 8001ce2: d901 bls.n 8001ce8 { return HAL_TIMEOUT; 8001ce4: 2303 movs r3, #3 8001ce6: e116 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001ce8: 4b8d ldr r3, [pc, #564] ; (8001f20 ) 8001cea: 6a1b ldr r3, [r3, #32] 8001cec: 2202 movs r2, #2 8001cee: 4013 ands r3, r2 8001cf0: d1f0 bne.n 8001cd4 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8001cf2: 231f movs r3, #31 8001cf4: 18fb adds r3, r7, r3 8001cf6: 781b ldrb r3, [r3, #0] 8001cf8: 2b01 cmp r3, #1 8001cfa: d105 bne.n 8001d08 { __HAL_RCC_PWR_CLK_DISABLE(); 8001cfc: 4b88 ldr r3, [pc, #544] ; (8001f20 ) 8001cfe: 69da ldr r2, [r3, #28] 8001d00: 4b87 ldr r3, [pc, #540] ; (8001f20 ) 8001d02: 4989 ldr r1, [pc, #548] ; (8001f28 ) 8001d04: 400a ands r2, r1 8001d06: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8001d08: 687b ldr r3, [r7, #4] 8001d0a: 681b ldr r3, [r3, #0] 8001d0c: 2210 movs r2, #16 8001d0e: 4013 ands r3, r2 8001d10: d063 beq.n 8001dda /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 8001d12: 687b ldr r3, [r7, #4] 8001d14: 695b ldr r3, [r3, #20] 8001d16: 2b01 cmp r3, #1 8001d18: d12a bne.n 8001d70 { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001d1a: 4b81 ldr r3, [pc, #516] ; (8001f20 ) 8001d1c: 6b5a ldr r2, [r3, #52] ; 0x34 8001d1e: 4b80 ldr r3, [pc, #512] ; (8001f20 ) 8001d20: 2104 movs r1, #4 8001d22: 430a orrs r2, r1 8001d24: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 8001d26: 4b7e ldr r3, [pc, #504] ; (8001f20 ) 8001d28: 6b5a ldr r2, [r3, #52] ; 0x34 8001d2a: 4b7d ldr r3, [pc, #500] ; (8001f20 ) 8001d2c: 2101 movs r1, #1 8001d2e: 430a orrs r2, r1 8001d30: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001d32: f7fe fe69 bl 8000a08 8001d36: 0003 movs r3, r0 8001d38: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001d3a: e008 b.n 8001d4e { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001d3c: f7fe fe64 bl 8000a08 8001d40: 0002 movs r2, r0 8001d42: 69bb ldr r3, [r7, #24] 8001d44: 1ad3 subs r3, r2, r3 8001d46: 2b02 cmp r3, #2 8001d48: d901 bls.n 8001d4e { return HAL_TIMEOUT; 8001d4a: 2303 movs r3, #3 8001d4c: e0e3 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001d4e: 4b74 ldr r3, [pc, #464] ; (8001f20 ) 8001d50: 6b5b ldr r3, [r3, #52] ; 0x34 8001d52: 2202 movs r2, #2 8001d54: 4013 ands r3, r2 8001d56: d0f1 beq.n 8001d3c } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001d58: 4b71 ldr r3, [pc, #452] ; (8001f20 ) 8001d5a: 6b5b ldr r3, [r3, #52] ; 0x34 8001d5c: 22f8 movs r2, #248 ; 0xf8 8001d5e: 4393 bics r3, r2 8001d60: 0019 movs r1, r3 8001d62: 687b ldr r3, [r7, #4] 8001d64: 699b ldr r3, [r3, #24] 8001d66: 00da lsls r2, r3, #3 8001d68: 4b6d ldr r3, [pc, #436] ; (8001f20 ) 8001d6a: 430a orrs r2, r1 8001d6c: 635a str r2, [r3, #52] ; 0x34 8001d6e: e034 b.n 8001dda } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8001d70: 687b ldr r3, [r7, #4] 8001d72: 695b ldr r3, [r3, #20] 8001d74: 3305 adds r3, #5 8001d76: d111 bne.n 8001d9c { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001d78: 4b69 ldr r3, [pc, #420] ; (8001f20 ) 8001d7a: 6b5a ldr r2, [r3, #52] ; 0x34 8001d7c: 4b68 ldr r3, [pc, #416] ; (8001f20 ) 8001d7e: 2104 movs r1, #4 8001d80: 438a bics r2, r1 8001d82: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001d84: 4b66 ldr r3, [pc, #408] ; (8001f20 ) 8001d86: 6b5b ldr r3, [r3, #52] ; 0x34 8001d88: 22f8 movs r2, #248 ; 0xf8 8001d8a: 4393 bics r3, r2 8001d8c: 0019 movs r1, r3 8001d8e: 687b ldr r3, [r7, #4] 8001d90: 699b ldr r3, [r3, #24] 8001d92: 00da lsls r2, r3, #3 8001d94: 4b62 ldr r3, [pc, #392] ; (8001f20 ) 8001d96: 430a orrs r2, r1 8001d98: 635a str r2, [r3, #52] ; 0x34 8001d9a: e01e b.n 8001dda } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001d9c: 4b60 ldr r3, [pc, #384] ; (8001f20 ) 8001d9e: 6b5a ldr r2, [r3, #52] ; 0x34 8001da0: 4b5f ldr r3, [pc, #380] ; (8001f20 ) 8001da2: 2104 movs r1, #4 8001da4: 430a orrs r2, r1 8001da6: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001da8: 4b5d ldr r3, [pc, #372] ; (8001f20 ) 8001daa: 6b5a ldr r2, [r3, #52] ; 0x34 8001dac: 4b5c ldr r3, [pc, #368] ; (8001f20 ) 8001dae: 2101 movs r1, #1 8001db0: 438a bics r2, r1 8001db2: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001db4: f7fe fe28 bl 8000a08 8001db8: 0003 movs r3, r0 8001dba: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001dbc: e008 b.n 8001dd0 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001dbe: f7fe fe23 bl 8000a08 8001dc2: 0002 movs r2, r0 8001dc4: 69bb ldr r3, [r7, #24] 8001dc6: 1ad3 subs r3, r2, r3 8001dc8: 2b02 cmp r3, #2 8001dca: d901 bls.n 8001dd0 { return HAL_TIMEOUT; 8001dcc: 2303 movs r3, #3 8001dce: e0a2 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001dd0: 4b53 ldr r3, [pc, #332] ; (8001f20 ) 8001dd2: 6b5b ldr r3, [r3, #52] ; 0x34 8001dd4: 2202 movs r2, #2 8001dd6: 4013 ands r3, r2 8001dd8: d1f1 bne.n 8001dbe #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001dda: 687b ldr r3, [r7, #4] 8001ddc: 6a1b ldr r3, [r3, #32] 8001dde: 2b00 cmp r3, #0 8001de0: d100 bne.n 8001de4 8001de2: e097 b.n 8001f14 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001de4: 4b4e ldr r3, [pc, #312] ; (8001f20 ) 8001de6: 685b ldr r3, [r3, #4] 8001de8: 220c movs r2, #12 8001dea: 4013 ands r3, r2 8001dec: 2b08 cmp r3, #8 8001dee: d100 bne.n 8001df2 8001df0: e06b b.n 8001eca { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8001df2: 687b ldr r3, [r7, #4] 8001df4: 6a1b ldr r3, [r3, #32] 8001df6: 2b02 cmp r3, #2 8001df8: d14c bne.n 8001e94 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001dfa: 4b49 ldr r3, [pc, #292] ; (8001f20 ) 8001dfc: 681a ldr r2, [r3, #0] 8001dfe: 4b48 ldr r3, [pc, #288] ; (8001f20 ) 8001e00: 494a ldr r1, [pc, #296] ; (8001f2c ) 8001e02: 400a ands r2, r1 8001e04: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e06: f7fe fdff bl 8000a08 8001e0a: 0003 movs r3, r0 8001e0c: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e0e: e008 b.n 8001e22 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001e10: f7fe fdfa bl 8000a08 8001e14: 0002 movs r2, r0 8001e16: 69bb ldr r3, [r7, #24] 8001e18: 1ad3 subs r3, r2, r3 8001e1a: 2b02 cmp r3, #2 8001e1c: d901 bls.n 8001e22 { return HAL_TIMEOUT; 8001e1e: 2303 movs r3, #3 8001e20: e079 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e22: 4b3f ldr r3, [pc, #252] ; (8001f20 ) 8001e24: 681a ldr r2, [r3, #0] 8001e26: 2380 movs r3, #128 ; 0x80 8001e28: 049b lsls r3, r3, #18 8001e2a: 4013 ands r3, r2 8001e2c: d1f0 bne.n 8001e10 } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8001e2e: 4b3c ldr r3, [pc, #240] ; (8001f20 ) 8001e30: 6adb ldr r3, [r3, #44] ; 0x2c 8001e32: 220f movs r2, #15 8001e34: 4393 bics r3, r2 8001e36: 0019 movs r1, r3 8001e38: 687b ldr r3, [r7, #4] 8001e3a: 6ada ldr r2, [r3, #44] ; 0x2c 8001e3c: 4b38 ldr r3, [pc, #224] ; (8001f20 ) 8001e3e: 430a orrs r2, r1 8001e40: 62da str r2, [r3, #44] ; 0x2c 8001e42: 4b37 ldr r3, [pc, #220] ; (8001f20 ) 8001e44: 685b ldr r3, [r3, #4] 8001e46: 4a3a ldr r2, [pc, #232] ; (8001f30 ) 8001e48: 4013 ands r3, r2 8001e4a: 0019 movs r1, r3 8001e4c: 687b ldr r3, [r7, #4] 8001e4e: 6a9a ldr r2, [r3, #40] ; 0x28 8001e50: 687b ldr r3, [r7, #4] 8001e52: 6a5b ldr r3, [r3, #36] ; 0x24 8001e54: 431a orrs r2, r3 8001e56: 4b32 ldr r3, [pc, #200] ; (8001f20 ) 8001e58: 430a orrs r2, r1 8001e5a: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001e5c: 4b30 ldr r3, [pc, #192] ; (8001f20 ) 8001e5e: 681a ldr r2, [r3, #0] 8001e60: 4b2f ldr r3, [pc, #188] ; (8001f20 ) 8001e62: 2180 movs r1, #128 ; 0x80 8001e64: 0449 lsls r1, r1, #17 8001e66: 430a orrs r2, r1 8001e68: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e6a: f7fe fdcd bl 8000a08 8001e6e: 0003 movs r3, r0 8001e70: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001e72: e008 b.n 8001e86 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001e74: f7fe fdc8 bl 8000a08 8001e78: 0002 movs r2, r0 8001e7a: 69bb ldr r3, [r7, #24] 8001e7c: 1ad3 subs r3, r2, r3 8001e7e: 2b02 cmp r3, #2 8001e80: d901 bls.n 8001e86 { return HAL_TIMEOUT; 8001e82: 2303 movs r3, #3 8001e84: e047 b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001e86: 4b26 ldr r3, [pc, #152] ; (8001f20 ) 8001e88: 681a ldr r2, [r3, #0] 8001e8a: 2380 movs r3, #128 ; 0x80 8001e8c: 049b lsls r3, r3, #18 8001e8e: 4013 ands r3, r2 8001e90: d0f0 beq.n 8001e74 8001e92: e03f b.n 8001f14 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001e94: 4b22 ldr r3, [pc, #136] ; (8001f20 ) 8001e96: 681a ldr r2, [r3, #0] 8001e98: 4b21 ldr r3, [pc, #132] ; (8001f20 ) 8001e9a: 4924 ldr r1, [pc, #144] ; (8001f2c ) 8001e9c: 400a ands r2, r1 8001e9e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001ea0: f7fe fdb2 bl 8000a08 8001ea4: 0003 movs r3, r0 8001ea6: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001ea8: e008 b.n 8001ebc { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001eaa: f7fe fdad bl 8000a08 8001eae: 0002 movs r2, r0 8001eb0: 69bb ldr r3, [r7, #24] 8001eb2: 1ad3 subs r3, r2, r3 8001eb4: 2b02 cmp r3, #2 8001eb6: d901 bls.n 8001ebc { return HAL_TIMEOUT; 8001eb8: 2303 movs r3, #3 8001eba: e02c b.n 8001f16 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001ebc: 4b18 ldr r3, [pc, #96] ; (8001f20 ) 8001ebe: 681a ldr r2, [r3, #0] 8001ec0: 2380 movs r3, #128 ; 0x80 8001ec2: 049b lsls r3, r3, #18 8001ec4: 4013 ands r3, r2 8001ec6: d1f0 bne.n 8001eaa 8001ec8: e024 b.n 8001f14 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001eca: 687b ldr r3, [r7, #4] 8001ecc: 6a1b ldr r3, [r3, #32] 8001ece: 2b01 cmp r3, #1 8001ed0: d101 bne.n 8001ed6 { return HAL_ERROR; 8001ed2: 2301 movs r3, #1 8001ed4: e01f b.n 8001f16 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001ed6: 4b12 ldr r3, [pc, #72] ; (8001f20 ) 8001ed8: 685b ldr r3, [r3, #4] 8001eda: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001edc: 4b10 ldr r3, [pc, #64] ; (8001f20 ) 8001ede: 6adb ldr r3, [r3, #44] ; 0x2c 8001ee0: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001ee2: 697a ldr r2, [r7, #20] 8001ee4: 2380 movs r3, #128 ; 0x80 8001ee6: 025b lsls r3, r3, #9 8001ee8: 401a ands r2, r3 8001eea: 687b ldr r3, [r7, #4] 8001eec: 6a5b ldr r3, [r3, #36] ; 0x24 8001eee: 429a cmp r2, r3 8001ef0: d10e bne.n 8001f10 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001ef2: 693b ldr r3, [r7, #16] 8001ef4: 220f movs r2, #15 8001ef6: 401a ands r2, r3 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001efc: 429a cmp r2, r3 8001efe: d107 bne.n 8001f10 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 8001f00: 697a ldr r2, [r7, #20] 8001f02: 23f0 movs r3, #240 ; 0xf0 8001f04: 039b lsls r3, r3, #14 8001f06: 401a ands r2, r3 8001f08: 687b ldr r3, [r7, #4] 8001f0a: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001f0c: 429a cmp r2, r3 8001f0e: d001 beq.n 8001f14 { return HAL_ERROR; 8001f10: 2301 movs r3, #1 8001f12: e000 b.n 8001f16 } } } } return HAL_OK; 8001f14: 2300 movs r3, #0 } 8001f16: 0018 movs r0, r3 8001f18: 46bd mov sp, r7 8001f1a: b008 add sp, #32 8001f1c: bd80 pop {r7, pc} 8001f1e: 46c0 nop ; (mov r8, r8) 8001f20: 40021000 .word 0x40021000 8001f24: 00001388 .word 0x00001388 8001f28: efffffff .word 0xefffffff 8001f2c: feffffff .word 0xfeffffff 8001f30: ffc2ffff .word 0xffc2ffff 08001f34 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001f34: b580 push {r7, lr} 8001f36: b084 sub sp, #16 8001f38: af00 add r7, sp, #0 8001f3a: 6078 str r0, [r7, #4] 8001f3c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8001f3e: 687b ldr r3, [r7, #4] 8001f40: 2b00 cmp r3, #0 8001f42: d101 bne.n 8001f48 { return HAL_ERROR; 8001f44: 2301 movs r3, #1 8001f46: e0b3 b.n 80020b0 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8001f48: 4b5b ldr r3, [pc, #364] ; (80020b8 ) 8001f4a: 681b ldr r3, [r3, #0] 8001f4c: 2201 movs r2, #1 8001f4e: 4013 ands r3, r2 8001f50: 683a ldr r2, [r7, #0] 8001f52: 429a cmp r2, r3 8001f54: d911 bls.n 8001f7a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001f56: 4b58 ldr r3, [pc, #352] ; (80020b8 ) 8001f58: 681b ldr r3, [r3, #0] 8001f5a: 2201 movs r2, #1 8001f5c: 4393 bics r3, r2 8001f5e: 0019 movs r1, r3 8001f60: 4b55 ldr r3, [pc, #340] ; (80020b8 ) 8001f62: 683a ldr r2, [r7, #0] 8001f64: 430a orrs r2, r1 8001f66: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001f68: 4b53 ldr r3, [pc, #332] ; (80020b8 ) 8001f6a: 681b ldr r3, [r3, #0] 8001f6c: 2201 movs r2, #1 8001f6e: 4013 ands r3, r2 8001f70: 683a ldr r2, [r7, #0] 8001f72: 429a cmp r2, r3 8001f74: d001 beq.n 8001f7a { return HAL_ERROR; 8001f76: 2301 movs r3, #1 8001f78: e09a b.n 80020b0 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001f7a: 687b ldr r3, [r7, #4] 8001f7c: 681b ldr r3, [r3, #0] 8001f7e: 2202 movs r2, #2 8001f80: 4013 ands r3, r2 8001f82: d015 beq.n 8001fb0 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001f84: 687b ldr r3, [r7, #4] 8001f86: 681b ldr r3, [r3, #0] 8001f88: 2204 movs r2, #4 8001f8a: 4013 ands r3, r2 8001f8c: d006 beq.n 8001f9c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001f8e: 4b4b ldr r3, [pc, #300] ; (80020bc ) 8001f90: 685a ldr r2, [r3, #4] 8001f92: 4b4a ldr r3, [pc, #296] ; (80020bc ) 8001f94: 21e0 movs r1, #224 ; 0xe0 8001f96: 00c9 lsls r1, r1, #3 8001f98: 430a orrs r2, r1 8001f9a: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001f9c: 4b47 ldr r3, [pc, #284] ; (80020bc ) 8001f9e: 685b ldr r3, [r3, #4] 8001fa0: 22f0 movs r2, #240 ; 0xf0 8001fa2: 4393 bics r3, r2 8001fa4: 0019 movs r1, r3 8001fa6: 687b ldr r3, [r7, #4] 8001fa8: 689a ldr r2, [r3, #8] 8001faa: 4b44 ldr r3, [pc, #272] ; (80020bc ) 8001fac: 430a orrs r2, r1 8001fae: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001fb0: 687b ldr r3, [r7, #4] 8001fb2: 681b ldr r3, [r3, #0] 8001fb4: 2201 movs r2, #1 8001fb6: 4013 ands r3, r2 8001fb8: d040 beq.n 800203c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8001fba: 687b ldr r3, [r7, #4] 8001fbc: 685b ldr r3, [r3, #4] 8001fbe: 2b01 cmp r3, #1 8001fc0: d107 bne.n 8001fd2 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001fc2: 4b3e ldr r3, [pc, #248] ; (80020bc ) 8001fc4: 681a ldr r2, [r3, #0] 8001fc6: 2380 movs r3, #128 ; 0x80 8001fc8: 029b lsls r3, r3, #10 8001fca: 4013 ands r3, r2 8001fcc: d114 bne.n 8001ff8 { return HAL_ERROR; 8001fce: 2301 movs r3, #1 8001fd0: e06e b.n 80020b0 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001fd2: 687b ldr r3, [r7, #4] 8001fd4: 685b ldr r3, [r3, #4] 8001fd6: 2b02 cmp r3, #2 8001fd8: d107 bne.n 8001fea { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001fda: 4b38 ldr r3, [pc, #224] ; (80020bc ) 8001fdc: 681a ldr r2, [r3, #0] 8001fde: 2380 movs r3, #128 ; 0x80 8001fe0: 049b lsls r3, r3, #18 8001fe2: 4013 ands r3, r2 8001fe4: d108 bne.n 8001ff8 { return HAL_ERROR; 8001fe6: 2301 movs r3, #1 8001fe8: e062 b.n 80020b0 #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001fea: 4b34 ldr r3, [pc, #208] ; (80020bc ) 8001fec: 681b ldr r3, [r3, #0] 8001fee: 2202 movs r2, #2 8001ff0: 4013 ands r3, r2 8001ff2: d101 bne.n 8001ff8 { return HAL_ERROR; 8001ff4: 2301 movs r3, #1 8001ff6: e05b b.n 80020b0 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8001ff8: 4b30 ldr r3, [pc, #192] ; (80020bc ) 8001ffa: 685b ldr r3, [r3, #4] 8001ffc: 2203 movs r2, #3 8001ffe: 4393 bics r3, r2 8002000: 0019 movs r1, r3 8002002: 687b ldr r3, [r7, #4] 8002004: 685a ldr r2, [r3, #4] 8002006: 4b2d ldr r3, [pc, #180] ; (80020bc ) 8002008: 430a orrs r2, r1 800200a: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800200c: f7fe fcfc bl 8000a08 8002010: 0003 movs r3, r0 8002012: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002014: e009 b.n 800202a { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8002016: f7fe fcf7 bl 8000a08 800201a: 0002 movs r2, r0 800201c: 68fb ldr r3, [r7, #12] 800201e: 1ad3 subs r3, r2, r3 8002020: 4a27 ldr r2, [pc, #156] ; (80020c0 ) 8002022: 4293 cmp r3, r2 8002024: d901 bls.n 800202a { return HAL_TIMEOUT; 8002026: 2303 movs r3, #3 8002028: e042 b.n 80020b0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800202a: 4b24 ldr r3, [pc, #144] ; (80020bc ) 800202c: 685b ldr r3, [r3, #4] 800202e: 220c movs r2, #12 8002030: 401a ands r2, r3 8002032: 687b ldr r3, [r7, #4] 8002034: 685b ldr r3, [r3, #4] 8002036: 009b lsls r3, r3, #2 8002038: 429a cmp r2, r3 800203a: d1ec bne.n 8002016 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 800203c: 4b1e ldr r3, [pc, #120] ; (80020b8 ) 800203e: 681b ldr r3, [r3, #0] 8002040: 2201 movs r2, #1 8002042: 4013 ands r3, r2 8002044: 683a ldr r2, [r7, #0] 8002046: 429a cmp r2, r3 8002048: d211 bcs.n 800206e { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800204a: 4b1b ldr r3, [pc, #108] ; (80020b8 ) 800204c: 681b ldr r3, [r3, #0] 800204e: 2201 movs r2, #1 8002050: 4393 bics r3, r2 8002052: 0019 movs r1, r3 8002054: 4b18 ldr r3, [pc, #96] ; (80020b8 ) 8002056: 683a ldr r2, [r7, #0] 8002058: 430a orrs r2, r1 800205a: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800205c: 4b16 ldr r3, [pc, #88] ; (80020b8 ) 800205e: 681b ldr r3, [r3, #0] 8002060: 2201 movs r2, #1 8002062: 4013 ands r3, r2 8002064: 683a ldr r2, [r7, #0] 8002066: 429a cmp r2, r3 8002068: d001 beq.n 800206e { return HAL_ERROR; 800206a: 2301 movs r3, #1 800206c: e020 b.n 80020b0 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800206e: 687b ldr r3, [r7, #4] 8002070: 681b ldr r3, [r3, #0] 8002072: 2204 movs r2, #4 8002074: 4013 ands r3, r2 8002076: d009 beq.n 800208c { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8002078: 4b10 ldr r3, [pc, #64] ; (80020bc ) 800207a: 685b ldr r3, [r3, #4] 800207c: 4a11 ldr r2, [pc, #68] ; (80020c4 ) 800207e: 4013 ands r3, r2 8002080: 0019 movs r1, r3 8002082: 687b ldr r3, [r7, #4] 8002084: 68da ldr r2, [r3, #12] 8002086: 4b0d ldr r3, [pc, #52] ; (80020bc ) 8002088: 430a orrs r2, r1 800208a: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 800208c: f000 f820 bl 80020d0 8002090: 0001 movs r1, r0 8002092: 4b0a ldr r3, [pc, #40] ; (80020bc ) 8002094: 685b ldr r3, [r3, #4] 8002096: 091b lsrs r3, r3, #4 8002098: 220f movs r2, #15 800209a: 4013 ands r3, r2 800209c: 4a0a ldr r2, [pc, #40] ; (80020c8 ) 800209e: 5cd3 ldrb r3, [r2, r3] 80020a0: 000a movs r2, r1 80020a2: 40da lsrs r2, r3 80020a4: 4b09 ldr r3, [pc, #36] ; (80020cc ) 80020a6: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 80020a8: 2003 movs r0, #3 80020aa: f7fe fc67 bl 800097c return HAL_OK; 80020ae: 2300 movs r3, #0 } 80020b0: 0018 movs r0, r3 80020b2: 46bd mov sp, r7 80020b4: b004 add sp, #16 80020b6: bd80 pop {r7, pc} 80020b8: 40022000 .word 0x40022000 80020bc: 40021000 .word 0x40021000 80020c0: 00001388 .word 0x00001388 80020c4: fffff8ff .word 0xfffff8ff 80020c8: 08003e38 .word 0x08003e38 80020cc: 20000000 .word 0x20000000 080020d0 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80020d0: b590 push {r4, r7, lr} 80020d2: b08f sub sp, #60 ; 0x3c 80020d4: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 80020d6: 2314 movs r3, #20 80020d8: 18fb adds r3, r7, r3 80020da: 4a2b ldr r2, [pc, #172] ; (8002188 ) 80020dc: ca13 ldmia r2!, {r0, r1, r4} 80020de: c313 stmia r3!, {r0, r1, r4} 80020e0: 6812 ldr r2, [r2, #0] 80020e2: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 80020e4: 1d3b adds r3, r7, #4 80020e6: 4a29 ldr r2, [pc, #164] ; (800218c ) 80020e8: ca13 ldmia r2!, {r0, r1, r4} 80020ea: c313 stmia r3!, {r0, r1, r4} 80020ec: 6812 ldr r2, [r2, #0] 80020ee: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80020f0: 2300 movs r3, #0 80020f2: 62fb str r3, [r7, #44] ; 0x2c 80020f4: 2300 movs r3, #0 80020f6: 62bb str r3, [r7, #40] ; 0x28 80020f8: 2300 movs r3, #0 80020fa: 637b str r3, [r7, #52] ; 0x34 80020fc: 2300 movs r3, #0 80020fe: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8002100: 2300 movs r3, #0 8002102: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 8002104: 4b22 ldr r3, [pc, #136] ; (8002190 ) 8002106: 685b ldr r3, [r3, #4] 8002108: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 800210a: 6afb ldr r3, [r7, #44] ; 0x2c 800210c: 220c movs r2, #12 800210e: 4013 ands r3, r2 8002110: 2b04 cmp r3, #4 8002112: d002 beq.n 800211a 8002114: 2b08 cmp r3, #8 8002116: d003 beq.n 8002120 8002118: e02d b.n 8002176 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 800211a: 4b1e ldr r3, [pc, #120] ; (8002194 ) 800211c: 633b str r3, [r7, #48] ; 0x30 break; 800211e: e02d b.n 800217c } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 8002120: 6afb ldr r3, [r7, #44] ; 0x2c 8002122: 0c9b lsrs r3, r3, #18 8002124: 220f movs r2, #15 8002126: 4013 ands r3, r2 8002128: 2214 movs r2, #20 800212a: 18ba adds r2, r7, r2 800212c: 5cd3 ldrb r3, [r2, r3] 800212e: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 8002130: 4b17 ldr r3, [pc, #92] ; (8002190 ) 8002132: 6adb ldr r3, [r3, #44] ; 0x2c 8002134: 220f movs r2, #15 8002136: 4013 ands r3, r2 8002138: 1d3a adds r2, r7, #4 800213a: 5cd3 ldrb r3, [r2, r3] 800213c: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 800213e: 6afa ldr r2, [r7, #44] ; 0x2c 8002140: 2380 movs r3, #128 ; 0x80 8002142: 025b lsls r3, r3, #9 8002144: 4013 ands r3, r2 8002146: d009 beq.n 800215c { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8002148: 6ab9 ldr r1, [r7, #40] ; 0x28 800214a: 4812 ldr r0, [pc, #72] ; (8002194 ) 800214c: f7fd ffdc bl 8000108 <__udivsi3> 8002150: 0003 movs r3, r0 8002152: 001a movs r2, r3 8002154: 6a7b ldr r3, [r7, #36] ; 0x24 8002156: 4353 muls r3, r2 8002158: 637b str r3, [r7, #52] ; 0x34 800215a: e009 b.n 8002170 #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 800215c: 6a79 ldr r1, [r7, #36] ; 0x24 800215e: 000a movs r2, r1 8002160: 0152 lsls r2, r2, #5 8002162: 1a52 subs r2, r2, r1 8002164: 0193 lsls r3, r2, #6 8002166: 1a9b subs r3, r3, r2 8002168: 00db lsls r3, r3, #3 800216a: 185b adds r3, r3, r1 800216c: 021b lsls r3, r3, #8 800216e: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 8002170: 6b7b ldr r3, [r7, #52] ; 0x34 8002172: 633b str r3, [r7, #48] ; 0x30 break; 8002174: e002 b.n 800217c } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8002176: 4b07 ldr r3, [pc, #28] ; (8002194 ) 8002178: 633b str r3, [r7, #48] ; 0x30 break; 800217a: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 800217c: 6b3b ldr r3, [r7, #48] ; 0x30 } 800217e: 0018 movs r0, r3 8002180: 46bd mov sp, r7 8002182: b00f add sp, #60 ; 0x3c 8002184: bd90 pop {r4, r7, pc} 8002186: 46c0 nop ; (mov r8, r8) 8002188: 08003e18 .word 0x08003e18 800218c: 08003e28 .word 0x08003e28 8002190: 40021000 .word 0x40021000 8002194: 007a1200 .word 0x007a1200 08002198 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8002198: b580 push {r7, lr} 800219a: b082 sub sp, #8 800219c: af00 add r7, sp, #0 800219e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80021a0: 687b ldr r3, [r7, #4] 80021a2: 2b00 cmp r3, #0 80021a4: d101 bne.n 80021aa { return HAL_ERROR; 80021a6: 2301 movs r3, #1 80021a8: e042 b.n 8002230 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80021aa: 687b ldr r3, [r7, #4] 80021ac: 223d movs r2, #61 ; 0x3d 80021ae: 5c9b ldrb r3, [r3, r2] 80021b0: b2db uxtb r3, r3 80021b2: 2b00 cmp r3, #0 80021b4: d107 bne.n 80021c6 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80021b6: 687b ldr r3, [r7, #4] 80021b8: 223c movs r2, #60 ; 0x3c 80021ba: 2100 movs r1, #0 80021bc: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 80021be: 687b ldr r3, [r7, #4] 80021c0: 0018 movs r0, r3 80021c2: f7fe fb43 bl 800084c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80021c6: 687b ldr r3, [r7, #4] 80021c8: 223d movs r2, #61 ; 0x3d 80021ca: 2102 movs r1, #2 80021cc: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80021ce: 687b ldr r3, [r7, #4] 80021d0: 681a ldr r2, [r3, #0] 80021d2: 687b ldr r3, [r7, #4] 80021d4: 3304 adds r3, #4 80021d6: 0019 movs r1, r3 80021d8: 0010 movs r0, r2 80021da: f000 f9a9 bl 8002530 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80021de: 687b ldr r3, [r7, #4] 80021e0: 2246 movs r2, #70 ; 0x46 80021e2: 2101 movs r1, #1 80021e4: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80021e6: 687b ldr r3, [r7, #4] 80021e8: 223e movs r2, #62 ; 0x3e 80021ea: 2101 movs r1, #1 80021ec: 5499 strb r1, [r3, r2] 80021ee: 687b ldr r3, [r7, #4] 80021f0: 223f movs r2, #63 ; 0x3f 80021f2: 2101 movs r1, #1 80021f4: 5499 strb r1, [r3, r2] 80021f6: 687b ldr r3, [r7, #4] 80021f8: 2240 movs r2, #64 ; 0x40 80021fa: 2101 movs r1, #1 80021fc: 5499 strb r1, [r3, r2] 80021fe: 687b ldr r3, [r7, #4] 8002200: 2241 movs r2, #65 ; 0x41 8002202: 2101 movs r1, #1 8002204: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8002206: 687b ldr r3, [r7, #4] 8002208: 2242 movs r2, #66 ; 0x42 800220a: 2101 movs r1, #1 800220c: 5499 strb r1, [r3, r2] 800220e: 687b ldr r3, [r7, #4] 8002210: 2243 movs r2, #67 ; 0x43 8002212: 2101 movs r1, #1 8002214: 5499 strb r1, [r3, r2] 8002216: 687b ldr r3, [r7, #4] 8002218: 2244 movs r2, #68 ; 0x44 800221a: 2101 movs r1, #1 800221c: 5499 strb r1, [r3, r2] 800221e: 687b ldr r3, [r7, #4] 8002220: 2245 movs r2, #69 ; 0x45 8002222: 2101 movs r1, #1 8002224: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8002226: 687b ldr r3, [r7, #4] 8002228: 223d movs r2, #61 ; 0x3d 800222a: 2101 movs r1, #1 800222c: 5499 strb r1, [r3, r2] return HAL_OK; 800222e: 2300 movs r3, #0 } 8002230: 0018 movs r0, r3 8002232: 46bd mov sp, r7 8002234: b002 add sp, #8 8002236: bd80 pop {r7, pc} 08002238 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8002238: b580 push {r7, lr} 800223a: b084 sub sp, #16 800223c: af00 add r7, sp, #0 800223e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8002240: 687b ldr r3, [r7, #4] 8002242: 223d movs r2, #61 ; 0x3d 8002244: 5c9b ldrb r3, [r3, r2] 8002246: b2db uxtb r3, r3 8002248: 2b01 cmp r3, #1 800224a: d001 beq.n 8002250 { return HAL_ERROR; 800224c: 2301 movs r3, #1 800224e: e030 b.n 80022b2 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8002250: 687b ldr r3, [r7, #4] 8002252: 223d movs r2, #61 ; 0x3d 8002254: 2102 movs r1, #2 8002256: 5499 strb r1, [r3, r2] /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8002258: 687b ldr r3, [r7, #4] 800225a: 681b ldr r3, [r3, #0] 800225c: 68da ldr r2, [r3, #12] 800225e: 687b ldr r3, [r7, #4] 8002260: 681b ldr r3, [r3, #0] 8002262: 2101 movs r1, #1 8002264: 430a orrs r2, r1 8002266: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8002268: 687b ldr r3, [r7, #4] 800226a: 681b ldr r3, [r3, #0] 800226c: 4a13 ldr r2, [pc, #76] ; (80022bc ) 800226e: 4293 cmp r3, r2 8002270: d004 beq.n 800227c 8002272: 687b ldr r3, [r7, #4] 8002274: 681b ldr r3, [r3, #0] 8002276: 4a12 ldr r2, [pc, #72] ; (80022c0 ) 8002278: 4293 cmp r3, r2 800227a: d111 bne.n 80022a0 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800227c: 687b ldr r3, [r7, #4] 800227e: 681b ldr r3, [r3, #0] 8002280: 689b ldr r3, [r3, #8] 8002282: 2207 movs r2, #7 8002284: 4013 ands r3, r2 8002286: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8002288: 68fb ldr r3, [r7, #12] 800228a: 2b06 cmp r3, #6 800228c: d010 beq.n 80022b0 { __HAL_TIM_ENABLE(htim); 800228e: 687b ldr r3, [r7, #4] 8002290: 681b ldr r3, [r3, #0] 8002292: 681a ldr r2, [r3, #0] 8002294: 687b ldr r3, [r7, #4] 8002296: 681b ldr r3, [r3, #0] 8002298: 2101 movs r1, #1 800229a: 430a orrs r2, r1 800229c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800229e: e007 b.n 80022b0 } } else { __HAL_TIM_ENABLE(htim); 80022a0: 687b ldr r3, [r7, #4] 80022a2: 681b ldr r3, [r3, #0] 80022a4: 681a ldr r2, [r3, #0] 80022a6: 687b ldr r3, [r7, #4] 80022a8: 681b ldr r3, [r3, #0] 80022aa: 2101 movs r1, #1 80022ac: 430a orrs r2, r1 80022ae: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80022b0: 2300 movs r3, #0 } 80022b2: 0018 movs r0, r3 80022b4: 46bd mov sp, r7 80022b6: b004 add sp, #16 80022b8: bd80 pop {r7, pc} 80022ba: 46c0 nop ; (mov r8, r8) 80022bc: 40012c00 .word 0x40012c00 80022c0: 40000400 .word 0x40000400 080022c4 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80022c4: b580 push {r7, lr} 80022c6: b082 sub sp, #8 80022c8: af00 add r7, sp, #0 80022ca: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80022cc: 687b ldr r3, [r7, #4] 80022ce: 681b ldr r3, [r3, #0] 80022d0: 691b ldr r3, [r3, #16] 80022d2: 2202 movs r2, #2 80022d4: 4013 ands r3, r2 80022d6: 2b02 cmp r3, #2 80022d8: d124 bne.n 8002324 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 80022da: 687b ldr r3, [r7, #4] 80022dc: 681b ldr r3, [r3, #0] 80022de: 68db ldr r3, [r3, #12] 80022e0: 2202 movs r2, #2 80022e2: 4013 ands r3, r2 80022e4: 2b02 cmp r3, #2 80022e6: d11d bne.n 8002324 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 80022e8: 687b ldr r3, [r7, #4] 80022ea: 681b ldr r3, [r3, #0] 80022ec: 2203 movs r2, #3 80022ee: 4252 negs r2, r2 80022f0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80022f2: 687b ldr r3, [r7, #4] 80022f4: 2201 movs r2, #1 80022f6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80022f8: 687b ldr r3, [r7, #4] 80022fa: 681b ldr r3, [r3, #0] 80022fc: 699b ldr r3, [r3, #24] 80022fe: 2203 movs r2, #3 8002300: 4013 ands r3, r2 8002302: d004 beq.n 800230e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002304: 687b ldr r3, [r7, #4] 8002306: 0018 movs r0, r3 8002308: f000 f8fa bl 8002500 800230c: e007 b.n 800231e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800230e: 687b ldr r3, [r7, #4] 8002310: 0018 movs r0, r3 8002312: f000 f8ed bl 80024f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002316: 687b ldr r3, [r7, #4] 8002318: 0018 movs r0, r3 800231a: f000 f8f9 bl 8002510 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800231e: 687b ldr r3, [r7, #4] 8002320: 2200 movs r2, #0 8002322: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 8002324: 687b ldr r3, [r7, #4] 8002326: 681b ldr r3, [r3, #0] 8002328: 691b ldr r3, [r3, #16] 800232a: 2204 movs r2, #4 800232c: 4013 ands r3, r2 800232e: 2b04 cmp r3, #4 8002330: d125 bne.n 800237e { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 8002332: 687b ldr r3, [r7, #4] 8002334: 681b ldr r3, [r3, #0] 8002336: 68db ldr r3, [r3, #12] 8002338: 2204 movs r2, #4 800233a: 4013 ands r3, r2 800233c: 2b04 cmp r3, #4 800233e: d11e bne.n 800237e { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8002340: 687b ldr r3, [r7, #4] 8002342: 681b ldr r3, [r3, #0] 8002344: 2205 movs r2, #5 8002346: 4252 negs r2, r2 8002348: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800234a: 687b ldr r3, [r7, #4] 800234c: 2202 movs r2, #2 800234e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8002350: 687b ldr r3, [r7, #4] 8002352: 681b ldr r3, [r3, #0] 8002354: 699a ldr r2, [r3, #24] 8002356: 23c0 movs r3, #192 ; 0xc0 8002358: 009b lsls r3, r3, #2 800235a: 4013 ands r3, r2 800235c: d004 beq.n 8002368 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800235e: 687b ldr r3, [r7, #4] 8002360: 0018 movs r0, r3 8002362: f000 f8cd bl 8002500 8002366: e007 b.n 8002378 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002368: 687b ldr r3, [r7, #4] 800236a: 0018 movs r0, r3 800236c: f000 f8c0 bl 80024f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002370: 687b ldr r3, [r7, #4] 8002372: 0018 movs r0, r3 8002374: f000 f8cc bl 8002510 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002378: 687b ldr r3, [r7, #4] 800237a: 2200 movs r2, #0 800237c: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 800237e: 687b ldr r3, [r7, #4] 8002380: 681b ldr r3, [r3, #0] 8002382: 691b ldr r3, [r3, #16] 8002384: 2208 movs r2, #8 8002386: 4013 ands r3, r2 8002388: 2b08 cmp r3, #8 800238a: d124 bne.n 80023d6 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 800238c: 687b ldr r3, [r7, #4] 800238e: 681b ldr r3, [r3, #0] 8002390: 68db ldr r3, [r3, #12] 8002392: 2208 movs r2, #8 8002394: 4013 ands r3, r2 8002396: 2b08 cmp r3, #8 8002398: d11d bne.n 80023d6 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 800239a: 687b ldr r3, [r7, #4] 800239c: 681b ldr r3, [r3, #0] 800239e: 2209 movs r2, #9 80023a0: 4252 negs r2, r2 80023a2: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80023a4: 687b ldr r3, [r7, #4] 80023a6: 2204 movs r2, #4 80023a8: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80023aa: 687b ldr r3, [r7, #4] 80023ac: 681b ldr r3, [r3, #0] 80023ae: 69db ldr r3, [r3, #28] 80023b0: 2203 movs r2, #3 80023b2: 4013 ands r3, r2 80023b4: d004 beq.n 80023c0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80023b6: 687b ldr r3, [r7, #4] 80023b8: 0018 movs r0, r3 80023ba: f000 f8a1 bl 8002500 80023be: e007 b.n 80023d0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80023c0: 687b ldr r3, [r7, #4] 80023c2: 0018 movs r0, r3 80023c4: f000 f894 bl 80024f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 80023c8: 687b ldr r3, [r7, #4] 80023ca: 0018 movs r0, r3 80023cc: f000 f8a0 bl 8002510 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80023d0: 687b ldr r3, [r7, #4] 80023d2: 2200 movs r2, #0 80023d4: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 80023d6: 687b ldr r3, [r7, #4] 80023d8: 681b ldr r3, [r3, #0] 80023da: 691b ldr r3, [r3, #16] 80023dc: 2210 movs r2, #16 80023de: 4013 ands r3, r2 80023e0: 2b10 cmp r3, #16 80023e2: d125 bne.n 8002430 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 80023e4: 687b ldr r3, [r7, #4] 80023e6: 681b ldr r3, [r3, #0] 80023e8: 68db ldr r3, [r3, #12] 80023ea: 2210 movs r2, #16 80023ec: 4013 ands r3, r2 80023ee: 2b10 cmp r3, #16 80023f0: d11e bne.n 8002430 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 80023f2: 687b ldr r3, [r7, #4] 80023f4: 681b ldr r3, [r3, #0] 80023f6: 2211 movs r2, #17 80023f8: 4252 negs r2, r2 80023fa: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80023fc: 687b ldr r3, [r7, #4] 80023fe: 2208 movs r2, #8 8002400: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8002402: 687b ldr r3, [r7, #4] 8002404: 681b ldr r3, [r3, #0] 8002406: 69da ldr r2, [r3, #28] 8002408: 23c0 movs r3, #192 ; 0xc0 800240a: 009b lsls r3, r3, #2 800240c: 4013 ands r3, r2 800240e: d004 beq.n 800241a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002410: 687b ldr r3, [r7, #4] 8002412: 0018 movs r0, r3 8002414: f000 f874 bl 8002500 8002418: e007 b.n 800242a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800241a: 687b ldr r3, [r7, #4] 800241c: 0018 movs r0, r3 800241e: f000 f867 bl 80024f0 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002422: 687b ldr r3, [r7, #4] 8002424: 0018 movs r0, r3 8002426: f000 f873 bl 8002510 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800242a: 687b ldr r3, [r7, #4] 800242c: 2200 movs r2, #0 800242e: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8002430: 687b ldr r3, [r7, #4] 8002432: 681b ldr r3, [r3, #0] 8002434: 691b ldr r3, [r3, #16] 8002436: 2201 movs r2, #1 8002438: 4013 ands r3, r2 800243a: 2b01 cmp r3, #1 800243c: d10f bne.n 800245e { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 800243e: 687b ldr r3, [r7, #4] 8002440: 681b ldr r3, [r3, #0] 8002442: 68db ldr r3, [r3, #12] 8002444: 2201 movs r2, #1 8002446: 4013 ands r3, r2 8002448: 2b01 cmp r3, #1 800244a: d108 bne.n 800245e { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 800244c: 687b ldr r3, [r7, #4] 800244e: 681b ldr r3, [r3, #0] 8002450: 2202 movs r2, #2 8002452: 4252 negs r2, r2 8002454: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8002456: 687b ldr r3, [r7, #4] 8002458: 0018 movs r0, r3 800245a: f001 fc8f bl 8003d7c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 800245e: 687b ldr r3, [r7, #4] 8002460: 681b ldr r3, [r3, #0] 8002462: 691b ldr r3, [r3, #16] 8002464: 2280 movs r2, #128 ; 0x80 8002466: 4013 ands r3, r2 8002468: 2b80 cmp r3, #128 ; 0x80 800246a: d10f bne.n 800248c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 800246c: 687b ldr r3, [r7, #4] 800246e: 681b ldr r3, [r3, #0] 8002470: 68db ldr r3, [r3, #12] 8002472: 2280 movs r2, #128 ; 0x80 8002474: 4013 ands r3, r2 8002476: 2b80 cmp r3, #128 ; 0x80 8002478: d108 bne.n 800248c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 800247a: 687b ldr r3, [r7, #4] 800247c: 681b ldr r3, [r3, #0] 800247e: 2281 movs r2, #129 ; 0x81 8002480: 4252 negs r2, r2 8002482: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8002484: 687b ldr r3, [r7, #4] 8002486: 0018 movs r0, r3 8002488: f000 f8c6 bl 8002618 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 800248c: 687b ldr r3, [r7, #4] 800248e: 681b ldr r3, [r3, #0] 8002490: 691b ldr r3, [r3, #16] 8002492: 2240 movs r2, #64 ; 0x40 8002494: 4013 ands r3, r2 8002496: 2b40 cmp r3, #64 ; 0x40 8002498: d10f bne.n 80024ba { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 800249a: 687b ldr r3, [r7, #4] 800249c: 681b ldr r3, [r3, #0] 800249e: 68db ldr r3, [r3, #12] 80024a0: 2240 movs r2, #64 ; 0x40 80024a2: 4013 ands r3, r2 80024a4: 2b40 cmp r3, #64 ; 0x40 80024a6: d108 bne.n 80024ba { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80024a8: 687b ldr r3, [r7, #4] 80024aa: 681b ldr r3, [r3, #0] 80024ac: 2241 movs r2, #65 ; 0x41 80024ae: 4252 negs r2, r2 80024b0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80024b2: 687b ldr r3, [r7, #4] 80024b4: 0018 movs r0, r3 80024b6: f000 f833 bl 8002520 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 80024ba: 687b ldr r3, [r7, #4] 80024bc: 681b ldr r3, [r3, #0] 80024be: 691b ldr r3, [r3, #16] 80024c0: 2220 movs r2, #32 80024c2: 4013 ands r3, r2 80024c4: 2b20 cmp r3, #32 80024c6: d10f bne.n 80024e8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 80024c8: 687b ldr r3, [r7, #4] 80024ca: 681b ldr r3, [r3, #0] 80024cc: 68db ldr r3, [r3, #12] 80024ce: 2220 movs r2, #32 80024d0: 4013 ands r3, r2 80024d2: 2b20 cmp r3, #32 80024d4: d108 bne.n 80024e8 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80024d6: 687b ldr r3, [r7, #4] 80024d8: 681b ldr r3, [r3, #0] 80024da: 2221 movs r2, #33 ; 0x21 80024dc: 4252 negs r2, r2 80024de: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80024e0: 687b ldr r3, [r7, #4] 80024e2: 0018 movs r0, r3 80024e4: f000 f890 bl 8002608 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 80024e8: 46c0 nop ; (mov r8, r8) 80024ea: 46bd mov sp, r7 80024ec: b002 add sp, #8 80024ee: bd80 pop {r7, pc} 080024f0 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80024f0: b580 push {r7, lr} 80024f2: b082 sub sp, #8 80024f4: af00 add r7, sp, #0 80024f6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80024f8: 46c0 nop ; (mov r8, r8) 80024fa: 46bd mov sp, r7 80024fc: b002 add sp, #8 80024fe: bd80 pop {r7, pc} 08002500 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8002500: b580 push {r7, lr} 8002502: b082 sub sp, #8 8002504: af00 add r7, sp, #0 8002506: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8002508: 46c0 nop ; (mov r8, r8) 800250a: 46bd mov sp, r7 800250c: b002 add sp, #8 800250e: bd80 pop {r7, pc} 08002510 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8002510: b580 push {r7, lr} 8002512: b082 sub sp, #8 8002514: af00 add r7, sp, #0 8002516: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8002518: 46c0 nop ; (mov r8, r8) 800251a: 46bd mov sp, r7 800251c: b002 add sp, #8 800251e: bd80 pop {r7, pc} 08002520 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8002520: b580 push {r7, lr} 8002522: b082 sub sp, #8 8002524: af00 add r7, sp, #0 8002526: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8002528: 46c0 nop ; (mov r8, r8) 800252a: 46bd mov sp, r7 800252c: b002 add sp, #8 800252e: bd80 pop {r7, pc} 08002530 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 8002530: b580 push {r7, lr} 8002532: b084 sub sp, #16 8002534: af00 add r7, sp, #0 8002536: 6078 str r0, [r7, #4] 8002538: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800253a: 687b ldr r3, [r7, #4] 800253c: 681b ldr r3, [r3, #0] 800253e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8002540: 687b ldr r3, [r7, #4] 8002542: 4a2b ldr r2, [pc, #172] ; (80025f0 ) 8002544: 4293 cmp r3, r2 8002546: d003 beq.n 8002550 8002548: 687b ldr r3, [r7, #4] 800254a: 4a2a ldr r2, [pc, #168] ; (80025f4 ) 800254c: 4293 cmp r3, r2 800254e: d108 bne.n 8002562 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8002550: 68fb ldr r3, [r7, #12] 8002552: 2270 movs r2, #112 ; 0x70 8002554: 4393 bics r3, r2 8002556: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8002558: 683b ldr r3, [r7, #0] 800255a: 685b ldr r3, [r3, #4] 800255c: 68fa ldr r2, [r7, #12] 800255e: 4313 orrs r3, r2 8002560: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8002562: 687b ldr r3, [r7, #4] 8002564: 4a22 ldr r2, [pc, #136] ; (80025f0 ) 8002566: 4293 cmp r3, r2 8002568: d00f beq.n 800258a 800256a: 687b ldr r3, [r7, #4] 800256c: 4a21 ldr r2, [pc, #132] ; (80025f4 ) 800256e: 4293 cmp r3, r2 8002570: d00b beq.n 800258a 8002572: 687b ldr r3, [r7, #4] 8002574: 4a20 ldr r2, [pc, #128] ; (80025f8 ) 8002576: 4293 cmp r3, r2 8002578: d007 beq.n 800258a 800257a: 687b ldr r3, [r7, #4] 800257c: 4a1f ldr r2, [pc, #124] ; (80025fc ) 800257e: 4293 cmp r3, r2 8002580: d003 beq.n 800258a 8002582: 687b ldr r3, [r7, #4] 8002584: 4a1e ldr r2, [pc, #120] ; (8002600 ) 8002586: 4293 cmp r3, r2 8002588: d108 bne.n 800259c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800258a: 68fb ldr r3, [r7, #12] 800258c: 4a1d ldr r2, [pc, #116] ; (8002604 ) 800258e: 4013 ands r3, r2 8002590: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8002592: 683b ldr r3, [r7, #0] 8002594: 68db ldr r3, [r3, #12] 8002596: 68fa ldr r2, [r7, #12] 8002598: 4313 orrs r3, r2 800259a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800259c: 68fb ldr r3, [r7, #12] 800259e: 2280 movs r2, #128 ; 0x80 80025a0: 4393 bics r3, r2 80025a2: 001a movs r2, r3 80025a4: 683b ldr r3, [r7, #0] 80025a6: 695b ldr r3, [r3, #20] 80025a8: 4313 orrs r3, r2 80025aa: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80025ac: 687b ldr r3, [r7, #4] 80025ae: 68fa ldr r2, [r7, #12] 80025b0: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80025b2: 683b ldr r3, [r7, #0] 80025b4: 689a ldr r2, [r3, #8] 80025b6: 687b ldr r3, [r7, #4] 80025b8: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80025ba: 683b ldr r3, [r7, #0] 80025bc: 681a ldr r2, [r3, #0] 80025be: 687b ldr r3, [r7, #4] 80025c0: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80025c2: 687b ldr r3, [r7, #4] 80025c4: 4a0a ldr r2, [pc, #40] ; (80025f0 ) 80025c6: 4293 cmp r3, r2 80025c8: d007 beq.n 80025da 80025ca: 687b ldr r3, [r7, #4] 80025cc: 4a0b ldr r2, [pc, #44] ; (80025fc ) 80025ce: 4293 cmp r3, r2 80025d0: d003 beq.n 80025da 80025d2: 687b ldr r3, [r7, #4] 80025d4: 4a0a ldr r2, [pc, #40] ; (8002600 ) 80025d6: 4293 cmp r3, r2 80025d8: d103 bne.n 80025e2 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80025da: 683b ldr r3, [r7, #0] 80025dc: 691a ldr r2, [r3, #16] 80025de: 687b ldr r3, [r7, #4] 80025e0: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80025e2: 687b ldr r3, [r7, #4] 80025e4: 2201 movs r2, #1 80025e6: 615a str r2, [r3, #20] } 80025e8: 46c0 nop ; (mov r8, r8) 80025ea: 46bd mov sp, r7 80025ec: b004 add sp, #16 80025ee: bd80 pop {r7, pc} 80025f0: 40012c00 .word 0x40012c00 80025f4: 40000400 .word 0x40000400 80025f8: 40002000 .word 0x40002000 80025fc: 40014400 .word 0x40014400 8002600: 40014800 .word 0x40014800 8002604: fffffcff .word 0xfffffcff 08002608 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8002608: b580 push {r7, lr} 800260a: b082 sub sp, #8 800260c: af00 add r7, sp, #0 800260e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8002610: 46c0 nop ; (mov r8, r8) 8002612: 46bd mov sp, r7 8002614: b002 add sp, #8 8002616: bd80 pop {r7, pc} 08002618 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8002618: b580 push {r7, lr} 800261a: b082 sub sp, #8 800261c: af00 add r7, sp, #0 800261e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8002620: 46c0 nop ; (mov r8, r8) 8002622: 46bd mov sp, r7 8002624: b002 add sp, #8 8002626: bd80 pop {r7, pc} 08002628 : */ #include "button.h" void GEI_BUTTON_CODE(struct button *bt,uint8_t in) { 8002628: b580 push {r7, lr} 800262a: b082 sub sp, #8 800262c: af00 add r7, sp, #0 800262e: 6078 str r0, [r7, #4] 8002630: 000a movs r2, r1 8002632: 1cfb adds r3, r7, #3 8002634: 701a strb r2, [r3, #0] #define t 250 bt->code=0; 8002636: 687b ldr r3, [r7, #4] 8002638: 2200 movs r2, #0 800263a: 601a str r2, [r3, #0] if(in==1) 800263c: 1cfb adds r3, r7, #3 800263e: 781b ldrb r3, [r3, #0] 8002640: 2b01 cmp r3, #1 8002642: d138 bne.n 80026b6 { if(bt->lock==0) 8002644: 687b ldr r3, [r7, #4] 8002646: 791b ldrb r3, [r3, #4] 8002648: 2b00 cmp r3, #0 800264a: d120 bne.n 800268e { if(HAL_GetTick()time+t) 800264c: f7fe f9dc bl 8000a08 8002650: 0002 movs r2, r0 8002652: 687b ldr r3, [r7, #4] 8002654: 689b ldr r3, [r3, #8] 8002656: 33fa adds r3, #250 ; 0xfa 8002658: 429a cmp r2, r3 800265a: d20d bcs.n 8002678 { bt->times++; 800265c: 687b ldr r3, [r7, #4] 800265e: 68db ldr r3, [r3, #12] 8002660: 1c5a adds r2, r3, #1 8002662: 687b ldr r3, [r7, #4] 8002664: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 8002666: f7fe f9cf bl 8000a08 800266a: 0002 movs r2, r0 800266c: 687b ldr r3, [r7, #4] 800266e: 609a str r2, [r3, #8] bt->lock=1; 8002670: 687b ldr r3, [r7, #4] 8002672: 2201 movs r2, #1 8002674: 711a strb r2, [r3, #4] 8002676: e00a b.n 800268e }else { bt->times=1; 8002678: 687b ldr r3, [r7, #4] 800267a: 2201 movs r2, #1 800267c: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 800267e: f7fe f9c3 bl 8000a08 8002682: 0002 movs r2, r0 8002684: 687b ldr r3, [r7, #4] 8002686: 609a str r2, [r3, #8] bt->lock=1; 8002688: 687b ldr r3, [r7, #4] 800268a: 2201 movs r2, #1 800268c: 711a strb r2, [r3, #4] } } if(bt->lock==1) 800268e: 687b ldr r3, [r7, #4] 8002690: 791b ldrb r3, [r3, #4] 8002692: 2b01 cmp r3, #1 8002694: d10f bne.n 80026b6 { if(HAL_GetTick()>bt->time+t) 8002696: f7fe f9b7 bl 8000a08 800269a: 0002 movs r2, r0 800269c: 687b ldr r3, [r7, #4] 800269e: 689b ldr r3, [r3, #8] 80026a0: 33fa adds r3, #250 ; 0xfa 80026a2: 429a cmp r2, r3 80026a4: d907 bls.n 80026b6 { bt->code=-1; 80026a6: 687b ldr r3, [r7, #4] 80026a8: 2201 movs r2, #1 80026aa: 4252 negs r2, r2 80026ac: 601a str r2, [r3, #0] bt->times=-1; 80026ae: 687b ldr r3, [r7, #4] 80026b0: 2201 movs r2, #1 80026b2: 4252 negs r2, r2 80026b4: 60da str r2, [r3, #12] } } } if(in==0) 80026b6: 1cfb adds r3, r7, #3 80026b8: 781b ldrb r3, [r3, #0] 80026ba: 2b00 cmp r3, #0 80026bc: d10e bne.n 80026dc { if(bt->lock==1) 80026be: 687b ldr r3, [r7, #4] 80026c0: 791b ldrb r3, [r3, #4] 80026c2: 2b01 cmp r3, #1 80026c4: d10a bne.n 80026dc { if(bt->code==-1) 80026c6: 687b ldr r3, [r7, #4] 80026c8: 681b ldr r3, [r3, #0] 80026ca: 3301 adds r3, #1 80026cc: d003 beq.n 80026d6 { }else { bt->code=bt->times; 80026ce: 687b ldr r3, [r7, #4] 80026d0: 68da ldr r2, [r3, #12] 80026d2: 687b ldr r3, [r7, #4] 80026d4: 601a str r2, [r3, #0] } bt->lock=0; 80026d6: 687b ldr r3, [r7, #4] 80026d8: 2200 movs r2, #0 80026da: 711a strb r2, [r3, #4] } } } 80026dc: 46c0 nop ; (mov r8, r8) 80026de: 46bd mov sp, r7 80026e0: b002 add sp, #8 80026e2: bd80 pop {r7, pc} 080026e4 : //在AT24CXX指定地址读出一个数据 //ReadAddr:开始读数的地址 //返回值 :读到的数据 uint8_t AT24CXX_ReadOneByte(uint16_t ReadAddr) { 80026e4: b5b0 push {r4, r5, r7, lr} 80026e6: b084 sub sp, #16 80026e8: af00 add r7, sp, #0 80026ea: 0002 movs r2, r0 80026ec: 1dbb adds r3, r7, #6 80026ee: 801a strh r2, [r3, #0] uint8_t temp=0; 80026f0: 240f movs r4, #15 80026f2: 193b adds r3, r7, r4 80026f4: 2200 movs r2, #0 80026f6: 701a strb r2, [r3, #0] IIC_Start(); 80026f8: f000 fa58 bl 8002bac { IIC_Send_Byte(0XA0); //发送写命令 IIC_Wait_Ack(); IIC_Send_Byte(ReadAddr>>8);//发送高地址 IIC_Wait_Ack(); }else IIC_Send_Byte(0XA0+((ReadAddr/256)<<1)); //发送器件地址0XA0,写数据 80026fc: 1dbb adds r3, r7, #6 80026fe: 881b ldrh r3, [r3, #0] 8002700: 0a1b lsrs r3, r3, #8 8002702: b29b uxth r3, r3 8002704: b2db uxtb r3, r3 8002706: 18db adds r3, r3, r3 8002708: b2db uxtb r3, r3 800270a: 3b60 subs r3, #96 ; 0x60 800270c: b2db uxtb r3, r3 800270e: 0018 movs r0, r3 8002710: f000 fb36 bl 8002d80 IIC_Wait_Ack(); 8002714: f000 fa9e bl 8002c54 IIC_Send_Byte(ReadAddr%256); //发送低地址 8002718: 1dbb adds r3, r7, #6 800271a: 881b ldrh r3, [r3, #0] 800271c: b2db uxtb r3, r3 800271e: 0018 movs r0, r3 8002720: f000 fb2e bl 8002d80 IIC_Wait_Ack(); 8002724: f000 fa96 bl 8002c54 IIC_Start(); 8002728: f000 fa40 bl 8002bac IIC_Send_Byte(0XA1); //进入接收模式 800272c: 20a1 movs r0, #161 ; 0xa1 800272e: f000 fb27 bl 8002d80 IIC_Wait_Ack(); 8002732: f000 fa8f bl 8002c54 temp=IIC_Read_Byte(0); 8002736: 0025 movs r5, r4 8002738: 193c adds r4, r7, r4 800273a: 2000 movs r0, #0 800273c: f000 fb72 bl 8002e24 8002740: 0003 movs r3, r0 8002742: 7023 strb r3, [r4, #0] IIC_Stop();//产生一个停止条件 8002744: f000 fa5c bl 8002c00 return temp; 8002748: 197b adds r3, r7, r5 800274a: 781b ldrb r3, [r3, #0] } 800274c: 0018 movs r0, r3 800274e: 46bd mov sp, r7 8002750: b004 add sp, #16 8002752: bdb0 pop {r4, r5, r7, pc} 08002754 : //在AT24CXX指定地址写入一个数据 //WriteAddr :写入数据的目的地址 //DataToWrite:要写入的数据 void AT24CXX_WriteOneByte(uint16_t WriteAddr,uint8_t DataToWrite) { 8002754: b580 push {r7, lr} 8002756: b082 sub sp, #8 8002758: af00 add r7, sp, #0 800275a: 0002 movs r2, r0 800275c: 1dbb adds r3, r7, #6 800275e: 801a strh r2, [r3, #0] 8002760: 1d7b adds r3, r7, #5 8002762: 1c0a adds r2, r1, #0 8002764: 701a strb r2, [r3, #0] IIC_Start(); 8002766: f000 fa21 bl 8002bac IIC_Send_Byte(0XA0); //发送写命令 IIC_Wait_Ack(); IIC_Send_Byte(WriteAddr>>8);//发送高地址 }else { IIC_Send_Byte(0XA0+((WriteAddr/256)<<1)); //发送器件地址0XA0,写数据 800276a: 1dbb adds r3, r7, #6 800276c: 881b ldrh r3, [r3, #0] 800276e: 0a1b lsrs r3, r3, #8 8002770: b29b uxth r3, r3 8002772: b2db uxtb r3, r3 8002774: 18db adds r3, r3, r3 8002776: b2db uxtb r3, r3 8002778: 3b60 subs r3, #96 ; 0x60 800277a: b2db uxtb r3, r3 800277c: 0018 movs r0, r3 800277e: f000 faff bl 8002d80 } IIC_Wait_Ack(); 8002782: f000 fa67 bl 8002c54 IIC_Send_Byte(WriteAddr%256); //发送低地址 8002786: 1dbb adds r3, r7, #6 8002788: 881b ldrh r3, [r3, #0] 800278a: b2db uxtb r3, r3 800278c: 0018 movs r0, r3 800278e: f000 faf7 bl 8002d80 IIC_Wait_Ack(); 8002792: f000 fa5f bl 8002c54 IIC_Send_Byte(DataToWrite); //发送字节 8002796: 1d7b adds r3, r7, #5 8002798: 781b ldrb r3, [r3, #0] 800279a: 0018 movs r0, r3 800279c: f000 faf0 bl 8002d80 IIC_Wait_Ack(); 80027a0: f000 fa58 bl 8002c54 IIC_Stop();//产生一个停止条件 80027a4: f000 fa2c bl 8002c00 } 80027a8: 46c0 nop ; (mov r8, r8) 80027aa: 46bd mov sp, r7 80027ac: b002 add sp, #8 80027ae: bd80 pop {r7, pc} 080027b0 : //在AT24CXX里面的指定地址开始读出指定个数的数据 //ReadAddr :开始读出的地址 对24c02为0~255 //pBuffer :数据数组首地址 //NumToRead:要读出数据的个数 void AT24CXX_Read(uint16_t ReadAddr,uint8_t *pBuffer,uint16_t NumToRead) { 80027b0: b590 push {r4, r7, lr} 80027b2: b083 sub sp, #12 80027b4: af00 add r7, sp, #0 80027b6: 6039 str r1, [r7, #0] 80027b8: 0011 movs r1, r2 80027ba: 1dbb adds r3, r7, #6 80027bc: 1c02 adds r2, r0, #0 80027be: 801a strh r2, [r3, #0] 80027c0: 1d3b adds r3, r7, #4 80027c2: 1c0a adds r2, r1, #0 80027c4: 801a strh r2, [r3, #0] while(NumToRead) 80027c6: e011 b.n 80027ec { *pBuffer++=AT24CXX_ReadOneByte(ReadAddr++); 80027c8: 1dbb adds r3, r7, #6 80027ca: 881b ldrh r3, [r3, #0] 80027cc: 1dba adds r2, r7, #6 80027ce: 1c59 adds r1, r3, #1 80027d0: 8011 strh r1, [r2, #0] 80027d2: 683c ldr r4, [r7, #0] 80027d4: 1c62 adds r2, r4, #1 80027d6: 603a str r2, [r7, #0] 80027d8: 0018 movs r0, r3 80027da: f7ff ff83 bl 80026e4 80027de: 0003 movs r3, r0 80027e0: 7023 strb r3, [r4, #0] NumToRead--; 80027e2: 1d3b adds r3, r7, #4 80027e4: 881a ldrh r2, [r3, #0] 80027e6: 1d3b adds r3, r7, #4 80027e8: 3a01 subs r2, #1 80027ea: 801a strh r2, [r3, #0] while(NumToRead) 80027ec: 1d3b adds r3, r7, #4 80027ee: 881b ldrh r3, [r3, #0] 80027f0: 2b00 cmp r3, #0 80027f2: d1e9 bne.n 80027c8 } } 80027f4: 46c0 nop ; (mov r8, r8) 80027f6: 46c0 nop ; (mov r8, r8) 80027f8: 46bd mov sp, r7 80027fa: b003 add sp, #12 80027fc: bd90 pop {r4, r7, pc} 080027fe : //在AT24CXX里面的指定地址开始写入指定个数的数据 //WriteAddr :开始写入的地址 对24c02为0~255 //pBuffer :数据数组首地址 //NumToWrite:要写入数据的个数 void AT24CXX_Write(uint16_t WriteAddr,uint8_t *pBuffer,uint16_t NumToWrite) { 80027fe: b580 push {r7, lr} 8002800: b082 sub sp, #8 8002802: af00 add r7, sp, #0 8002804: 6039 str r1, [r7, #0] 8002806: 0011 movs r1, r2 8002808: 1dbb adds r3, r7, #6 800280a: 1c02 adds r2, r0, #0 800280c: 801a strh r2, [r3, #0] 800280e: 1d3b adds r3, r7, #4 8002810: 1c0a adds r2, r1, #0 8002812: 801a strh r2, [r3, #0] while(NumToWrite--) 8002814: e00f b.n 8002836 { AT24CXX_WriteOneByte(WriteAddr,*pBuffer); 8002816: 683b ldr r3, [r7, #0] 8002818: 781a ldrb r2, [r3, #0] 800281a: 1dbb adds r3, r7, #6 800281c: 881b ldrh r3, [r3, #0] 800281e: 0011 movs r1, r2 8002820: 0018 movs r0, r3 8002822: f7ff ff97 bl 8002754 WriteAddr++; 8002826: 1dbb adds r3, r7, #6 8002828: 881a ldrh r2, [r3, #0] 800282a: 1dbb adds r3, r7, #6 800282c: 3201 adds r2, #1 800282e: 801a strh r2, [r3, #0] pBuffer++; 8002830: 683b ldr r3, [r7, #0] 8002832: 3301 adds r3, #1 8002834: 603b str r3, [r7, #0] while(NumToWrite--) 8002836: 1d3b adds r3, r7, #4 8002838: 881b ldrh r3, [r3, #0] 800283a: 1d3a adds r2, r7, #4 800283c: 1e59 subs r1, r3, #1 800283e: 8011 strh r1, [r2, #0] 8002840: 2b00 cmp r3, #0 8002842: d1e8 bne.n 8002816 } } 8002844: 46c0 nop ; (mov r8, r8) 8002846: 46c0 nop ; (mov r8, r8) 8002848: 46bd mov sp, r7 800284a: b002 add sp, #8 800284c: bd80 pop {r7, pc} 0800284e : * Author: wuwenfeng */ #include "gpio.h" void change_io_function(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin,char a) { 800284e: b580 push {r7, lr} 8002850: b088 sub sp, #32 8002852: af00 add r7, sp, #0 8002854: 6078 str r0, [r7, #4] 8002856: 0008 movs r0, r1 8002858: 0011 movs r1, r2 800285a: 1cbb adds r3, r7, #2 800285c: 1c02 adds r2, r0, #0 800285e: 801a strh r2, [r3, #0] 8002860: 1c7b adds r3, r7, #1 8002862: 1c0a adds r2, r1, #0 8002864: 701a strb r2, [r3, #0] GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_Pin; 8002866: 1cbb adds r3, r7, #2 8002868: 881a ldrh r2, [r3, #0] 800286a: 210c movs r1, #12 800286c: 187b adds r3, r7, r1 800286e: 601a str r2, [r3, #0] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8002870: 187b adds r3, r7, r1 8002872: 2203 movs r2, #3 8002874: 60da str r2, [r3, #12] if(a==1) 8002876: 1c7b adds r3, r7, #1 8002878: 781b ldrb r3, [r3, #0] 800287a: 2b01 cmp r3, #1 800287c: d105 bne.n 800288a { GPIO_InitStruct.Pull = GPIO_PULLUP; 800287e: 187b adds r3, r7, r1 8002880: 2201 movs r2, #1 8002882: 609a str r2, [r3, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8002884: 187b adds r3, r7, r1 8002886: 2200 movs r2, #0 8002888: 605a str r2, [r3, #4] } if(a==0) 800288a: 1c7b adds r3, r7, #1 800288c: 781b ldrb r3, [r3, #0] 800288e: 2b00 cmp r3, #0 8002890: d106 bne.n 80028a0 { GPIO_InitStruct.Pull = GPIO_NOPULL; 8002892: 210c movs r1, #12 8002894: 187b adds r3, r7, r1 8002896: 2200 movs r2, #0 8002898: 609a str r2, [r3, #8] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800289a: 187b adds r3, r7, r1 800289c: 2201 movs r2, #1 800289e: 605a str r2, [r3, #4] } HAL_GPIO_Init(GPIOx, &GPIO_InitStruct); 80028a0: 230c movs r3, #12 80028a2: 18fa adds r2, r7, r3 80028a4: 687b ldr r3, [r7, #4] 80028a6: 0011 movs r1, r2 80028a8: 0018 movs r0, r3 80028aa: f7fe fe45 bl 8001538 } 80028ae: 46c0 nop ; (mov r8, r8) 80028b0: 46bd mov sp, r7 80028b2: b008 add sp, #32 80028b4: bd80 pop {r7, pc} 080028b6 : #include "my_code.h" #define HT1621_addrbit 6 void WriteClockHT1621(void) { 80028b6: b580 push {r7, lr} 80028b8: af00 add r7, sp, #0 HC595_SCK(0); 80028ba: 2390 movs r3, #144 ; 0x90 80028bc: 05db lsls r3, r3, #23 80028be: 2200 movs r2, #0 80028c0: 2140 movs r1, #64 ; 0x40 80028c2: 0018 movs r0, r3 80028c4: f7fe ffc5 bl 8001852 HC595_SCK(1); 80028c8: 2390 movs r3, #144 ; 0x90 80028ca: 05db lsls r3, r3, #23 80028cc: 2201 movs r2, #1 80028ce: 2140 movs r1, #64 ; 0x40 80028d0: 0018 movs r0, r3 80028d2: f7fe ffbe bl 8001852 } 80028d6: 46c0 nop ; (mov r8, r8) 80028d8: 46bd mov sp, r7 80028da: bd80 pop {r7, pc} 080028dc : void WriteCommandHT1621(unsigned char FunctonCode) { 80028dc: b580 push {r7, lr} 80028de: b084 sub sp, #16 80028e0: af00 add r7, sp, #0 80028e2: 0002 movs r2, r0 80028e4: 1dfb adds r3, r7, #7 80028e6: 701a strb r2, [r3, #0] unsigned char Shift = 0x80; 80028e8: 230f movs r3, #15 80028ea: 18fb adds r3, r7, r3 80028ec: 2280 movs r2, #128 ; 0x80 80028ee: 701a strb r2, [r3, #0] unsigned char i; HC595_RCK(0); 80028f0: 2390 movs r3, #144 ; 0x90 80028f2: 05db lsls r3, r3, #23 80028f4: 2200 movs r2, #0 80028f6: 2180 movs r1, #128 ; 0x80 80028f8: 0018 movs r0, r3 80028fa: f7fe ffaa bl 8001852 HC595_DCK(1); 80028fe: 2390 movs r3, #144 ; 0x90 8002900: 05db lsls r3, r3, #23 8002902: 2201 movs r2, #1 8002904: 2120 movs r1, #32 8002906: 0018 movs r0, r3 8002908: f7fe ffa3 bl 8001852 WriteClockHT1621(); 800290c: f7ff ffd3 bl 80028b6 HC595_DCK(0); 8002910: 2390 movs r3, #144 ; 0x90 8002912: 05db lsls r3, r3, #23 8002914: 2200 movs r2, #0 8002916: 2120 movs r1, #32 8002918: 0018 movs r0, r3 800291a: f7fe ff9a bl 8001852 WriteClockHT1621(); 800291e: f7ff ffca bl 80028b6 HC595_DCK(0); 8002922: 2390 movs r3, #144 ; 0x90 8002924: 05db lsls r3, r3, #23 8002926: 2200 movs r2, #0 8002928: 2120 movs r1, #32 800292a: 0018 movs r0, r3 800292c: f7fe ff91 bl 8001852 WriteClockHT1621(); 8002930: f7ff ffc1 bl 80028b6 for(i = 0; i < 8; i++) 8002934: 230e movs r3, #14 8002936: 18fb adds r3, r7, r3 8002938: 2200 movs r2, #0 800293a: 701a strb r2, [r3, #0] 800293c: e025 b.n 800298a { if(Shift & FunctonCode) 800293e: 230f movs r3, #15 8002940: 18fb adds r3, r7, r3 8002942: 1dfa adds r2, r7, #7 8002944: 781b ldrb r3, [r3, #0] 8002946: 7812 ldrb r2, [r2, #0] 8002948: 4013 ands r3, r2 800294a: b2db uxtb r3, r3 800294c: 2b00 cmp r3, #0 800294e: d007 beq.n 8002960 {HC595_DCK(1);} 8002950: 2390 movs r3, #144 ; 0x90 8002952: 05db lsls r3, r3, #23 8002954: 2201 movs r2, #1 8002956: 2120 movs r1, #32 8002958: 0018 movs r0, r3 800295a: f7fe ff7a bl 8001852 800295e: e006 b.n 800296e else {HC595_DCK(0);} 8002960: 2390 movs r3, #144 ; 0x90 8002962: 05db lsls r3, r3, #23 8002964: 2200 movs r2, #0 8002966: 2120 movs r1, #32 8002968: 0018 movs r0, r3 800296a: f7fe ff72 bl 8001852 WriteClockHT1621(); 800296e: f7ff ffa2 bl 80028b6 Shift = Shift >> 1; 8002972: 220f movs r2, #15 8002974: 18bb adds r3, r7, r2 8002976: 18ba adds r2, r7, r2 8002978: 7812 ldrb r2, [r2, #0] 800297a: 0852 lsrs r2, r2, #1 800297c: 701a strb r2, [r3, #0] for(i = 0; i < 8; i++) 800297e: 210e movs r1, #14 8002980: 187b adds r3, r7, r1 8002982: 781a ldrb r2, [r3, #0] 8002984: 187b adds r3, r7, r1 8002986: 3201 adds r2, #1 8002988: 701a strb r2, [r3, #0] 800298a: 230e movs r3, #14 800298c: 18fb adds r3, r7, r3 800298e: 781b ldrb r3, [r3, #0] 8002990: 2b07 cmp r3, #7 8002992: d9d4 bls.n 800293e } {HC595_DCK(0);} 8002994: 2390 movs r3, #144 ; 0x90 8002996: 05db lsls r3, r3, #23 8002998: 2200 movs r2, #0 800299a: 2120 movs r1, #32 800299c: 0018 movs r0, r3 800299e: f7fe ff58 bl 8001852 WriteClockHT1621(); 80029a2: f7ff ff88 bl 80028b6 HC595_RCK(1); 80029a6: 2390 movs r3, #144 ; 0x90 80029a8: 05db lsls r3, r3, #23 80029aa: 2201 movs r2, #1 80029ac: 2180 movs r1, #128 ; 0x80 80029ae: 0018 movs r0, r3 80029b0: f7fe ff4f bl 8001852 HC595_DCK(1); 80029b4: 2390 movs r3, #144 ; 0x90 80029b6: 05db lsls r3, r3, #23 80029b8: 2201 movs r2, #1 80029ba: 2120 movs r1, #32 80029bc: 0018 movs r0, r3 80029be: f7fe ff48 bl 8001852 } 80029c2: 46c0 nop ; (mov r8, r8) 80029c4: 46bd mov sp, r7 80029c6: b004 add sp, #16 80029c8: bd80 pop {r7, pc} 080029ca : void WritenDataHT1621(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt) { 80029ca: b580 push {r7, lr} 80029cc: b084 sub sp, #16 80029ce: af00 add r7, sp, #0 80029d0: 6039 str r1, [r7, #0] 80029d2: 0011 movs r1, r2 80029d4: 1dfb adds r3, r7, #7 80029d6: 1c02 adds r2, r0, #0 80029d8: 701a strb r2, [r3, #0] 80029da: 1dbb adds r3, r7, #6 80029dc: 1c0a adds r2, r1, #0 80029de: 701a strb r2, [r3, #0] unsigned char i,j; unsigned char Shift; unsigned char dataval; HC595_RCK(0); 80029e0: 2390 movs r3, #144 ; 0x90 80029e2: 05db lsls r3, r3, #23 80029e4: 2200 movs r2, #0 80029e6: 2180 movs r1, #128 ; 0x80 80029e8: 0018 movs r0, r3 80029ea: f7fe ff32 bl 8001852 HC595_DCK(1); //101 80029ee: 2390 movs r3, #144 ; 0x90 80029f0: 05db lsls r3, r3, #23 80029f2: 2201 movs r2, #1 80029f4: 2120 movs r1, #32 80029f6: 0018 movs r0, r3 80029f8: f7fe ff2b bl 8001852 WriteClockHT1621(); 80029fc: f7ff ff5b bl 80028b6 HC595_DCK(0); 8002a00: 2390 movs r3, #144 ; 0x90 8002a02: 05db lsls r3, r3, #23 8002a04: 2200 movs r2, #0 8002a06: 2120 movs r1, #32 8002a08: 0018 movs r0, r3 8002a0a: f7fe ff22 bl 8001852 WriteClockHT1621(); 8002a0e: f7ff ff52 bl 80028b6 HC595_DCK(1); 8002a12: 2390 movs r3, #144 ; 0x90 8002a14: 05db lsls r3, r3, #23 8002a16: 2201 movs r2, #1 8002a18: 2120 movs r1, #32 8002a1a: 0018 movs r0, r3 8002a1c: f7fe ff19 bl 8001852 WriteClockHT1621(); 8002a20: f7ff ff49 bl 80028b6 Shift = 0x20; 8002a24: 230d movs r3, #13 8002a26: 18fb adds r3, r7, r3 8002a28: 2220 movs r2, #32 8002a2a: 701a strb r2, [r3, #0] for( i = 0; i < HT1621_addrbit; i++) 8002a2c: 230f movs r3, #15 8002a2e: 18fb adds r3, r7, r3 8002a30: 2200 movs r2, #0 8002a32: 701a strb r2, [r3, #0] 8002a34: e025 b.n 8002a82 { if (Addr & Shift) 8002a36: 1dfb adds r3, r7, #7 8002a38: 220d movs r2, #13 8002a3a: 18ba adds r2, r7, r2 8002a3c: 781b ldrb r3, [r3, #0] 8002a3e: 7812 ldrb r2, [r2, #0] 8002a40: 4013 ands r3, r2 8002a42: b2db uxtb r3, r3 8002a44: 2b00 cmp r3, #0 8002a46: d007 beq.n 8002a58 {HC595_DCK(1);} 8002a48: 2390 movs r3, #144 ; 0x90 8002a4a: 05db lsls r3, r3, #23 8002a4c: 2201 movs r2, #1 8002a4e: 2120 movs r1, #32 8002a50: 0018 movs r0, r3 8002a52: f7fe fefe bl 8001852 8002a56: e006 b.n 8002a66 else {HC595_DCK(0);} 8002a58: 2390 movs r3, #144 ; 0x90 8002a5a: 05db lsls r3, r3, #23 8002a5c: 2200 movs r2, #0 8002a5e: 2120 movs r1, #32 8002a60: 0018 movs r0, r3 8002a62: f7fe fef6 bl 8001852 WriteClockHT1621(); 8002a66: f7ff ff26 bl 80028b6 Shift = Shift >> 1; 8002a6a: 220d movs r2, #13 8002a6c: 18bb adds r3, r7, r2 8002a6e: 18ba adds r2, r7, r2 8002a70: 7812 ldrb r2, [r2, #0] 8002a72: 0852 lsrs r2, r2, #1 8002a74: 701a strb r2, [r3, #0] for( i = 0; i < HT1621_addrbit; i++) 8002a76: 210f movs r1, #15 8002a78: 187b adds r3, r7, r1 8002a7a: 781a ldrb r2, [r3, #0] 8002a7c: 187b adds r3, r7, r1 8002a7e: 3201 adds r2, #1 8002a80: 701a strb r2, [r3, #0] 8002a82: 230f movs r3, #15 8002a84: 18fb adds r3, r7, r3 8002a86: 781b ldrb r3, [r3, #0] 8002a88: 2b05 cmp r3, #5 8002a8a: d9d4 bls.n 8002a36 } for (j = 0; j < Cnt; j++) 8002a8c: 230e movs r3, #14 8002a8e: 18fb adds r3, r7, r3 8002a90: 2200 movs r2, #0 8002a92: 701a strb r2, [r3, #0] 8002a94: e041 b.n 8002b1a { Shift = 0x01; 8002a96: 230d movs r3, #13 8002a98: 18fb adds r3, r7, r3 8002a9a: 2201 movs r2, #1 8002a9c: 701a strb r2, [r3, #0] dataval=*Databuf++; 8002a9e: 683b ldr r3, [r7, #0] 8002aa0: 1c5a adds r2, r3, #1 8002aa2: 603a str r2, [r7, #0] 8002aa4: 220c movs r2, #12 8002aa6: 18ba adds r2, r7, r2 8002aa8: 781b ldrb r3, [r3, #0] 8002aaa: 7013 strb r3, [r2, #0] for (i = 0; i < 4; i++) 8002aac: 230f movs r3, #15 8002aae: 18fb adds r3, r7, r3 8002ab0: 2200 movs r2, #0 8002ab2: 701a strb r2, [r3, #0] 8002ab4: e026 b.n 8002b04 { if( dataval & Shift) 8002ab6: 230c movs r3, #12 8002ab8: 18fb adds r3, r7, r3 8002aba: 220d movs r2, #13 8002abc: 18ba adds r2, r7, r2 8002abe: 781b ldrb r3, [r3, #0] 8002ac0: 7812 ldrb r2, [r2, #0] 8002ac2: 4013 ands r3, r2 8002ac4: b2db uxtb r3, r3 8002ac6: 2b00 cmp r3, #0 8002ac8: d007 beq.n 8002ada {HC595_DCK(1);} 8002aca: 2390 movs r3, #144 ; 0x90 8002acc: 05db lsls r3, r3, #23 8002ace: 2201 movs r2, #1 8002ad0: 2120 movs r1, #32 8002ad2: 0018 movs r0, r3 8002ad4: f7fe febd bl 8001852 8002ad8: e006 b.n 8002ae8 else {HC595_DCK(0);} 8002ada: 2390 movs r3, #144 ; 0x90 8002adc: 05db lsls r3, r3, #23 8002ade: 2200 movs r2, #0 8002ae0: 2120 movs r1, #32 8002ae2: 0018 movs r0, r3 8002ae4: f7fe feb5 bl 8001852 WriteClockHT1621(); 8002ae8: f7ff fee5 bl 80028b6 Shift = Shift << 1; 8002aec: 230d movs r3, #13 8002aee: 18fa adds r2, r7, r3 8002af0: 18fb adds r3, r7, r3 8002af2: 781b ldrb r3, [r3, #0] 8002af4: 18db adds r3, r3, r3 8002af6: 7013 strb r3, [r2, #0] for (i = 0; i < 4; i++) 8002af8: 210f movs r1, #15 8002afa: 187b adds r3, r7, r1 8002afc: 781a ldrb r2, [r3, #0] 8002afe: 187b adds r3, r7, r1 8002b00: 3201 adds r2, #1 8002b02: 701a strb r2, [r3, #0] 8002b04: 230f movs r3, #15 8002b06: 18fb adds r3, r7, r3 8002b08: 781b ldrb r3, [r3, #0] 8002b0a: 2b03 cmp r3, #3 8002b0c: d9d3 bls.n 8002ab6 for (j = 0; j < Cnt; j++) 8002b0e: 210e movs r1, #14 8002b10: 187b adds r3, r7, r1 8002b12: 781a ldrb r2, [r3, #0] 8002b14: 187b adds r3, r7, r1 8002b16: 3201 adds r2, #1 8002b18: 701a strb r2, [r3, #0] 8002b1a: 230e movs r3, #14 8002b1c: 18fa adds r2, r7, r3 8002b1e: 1dbb adds r3, r7, #6 8002b20: 7812 ldrb r2, [r2, #0] 8002b22: 781b ldrb r3, [r3, #0] 8002b24: 429a cmp r2, r3 8002b26: d3b6 bcc.n 8002a96 } } HC595_RCK(1); 8002b28: 2390 movs r3, #144 ; 0x90 8002b2a: 05db lsls r3, r3, #23 8002b2c: 2201 movs r2, #1 8002b2e: 2180 movs r1, #128 ; 0x80 8002b30: 0018 movs r0, r3 8002b32: f7fe fe8e bl 8001852 HC595_DCK(1); 8002b36: 2390 movs r3, #144 ; 0x90 8002b38: 05db lsls r3, r3, #23 8002b3a: 2201 movs r2, #1 8002b3c: 2120 movs r1, #32 8002b3e: 0018 movs r0, r3 8002b40: f7fe fe87 bl 8001852 } 8002b44: 46c0 nop ; (mov r8, r8) 8002b46: 46bd mov sp, r7 8002b48: b004 add sp, #16 8002b4a: bd80 pop {r7, pc} 08002b4c : void HT1621_Init(void) { 8002b4c: b580 push {r7, lr} 8002b4e: af00 add r7, sp, #0 HC595_RCK(1); 8002b50: 2390 movs r3, #144 ; 0x90 8002b52: 05db lsls r3, r3, #23 8002b54: 2201 movs r2, #1 8002b56: 2180 movs r1, #128 ; 0x80 8002b58: 0018 movs r0, r3 8002b5a: f7fe fe7a bl 8001852 HC595_SCK(1); 8002b5e: 2390 movs r3, #144 ; 0x90 8002b60: 05db lsls r3, r3, #23 8002b62: 2201 movs r2, #1 8002b64: 2140 movs r1, #64 ; 0x40 8002b66: 0018 movs r0, r3 8002b68: f7fe fe73 bl 8001852 HC595_DCK(1); 8002b6c: 2390 movs r3, #144 ; 0x90 8002b6e: 05db lsls r3, r3, #23 8002b70: 2201 movs r2, #1 8002b72: 2120 movs r1, #32 8002b74: 0018 movs r0, r3 8002b76: f7fe fe6c bl 8001852 WriteCommandHT1621(OSC_ON); 8002b7a: 2001 movs r0, #1 8002b7c: f7ff feae bl 80028dc WriteCommandHT1621(DISP_ON); 8002b80: 2003 movs r0, #3 8002b82: f7ff feab bl 80028dc WriteCommandHT1621(COM_1_3__4); 8002b86: 2029 movs r0, #41 ; 0x29 8002b88: f7ff fea8 bl 80028dc WriteCommandHT1621(TIMER_DIS); 8002b8c: 2004 movs r0, #4 8002b8e: f7ff fea5 bl 80028dc WriteCommandHT1621(WDT_DIS); 8002b92: 2005 movs r0, #5 8002b94: f7ff fea2 bl 80028dc WriteCommandHT1621(BUZZ_OFF); 8002b98: 2008 movs r0, #8 8002b9a: f7ff fe9f bl 80028dc WriteCommandHT1621(IRQ_DIS); 8002b9e: 2080 movs r0, #128 ; 0x80 8002ba0: f7ff fe9c bl 80028dc } 8002ba4: 46c0 nop ; (mov r8, r8) 8002ba6: 46bd mov sp, r7 8002ba8: bd80 pop {r7, pc} ... 08002bac : #define SDA_IN() change_io_function(iic_sda_GPIO_Port, iic_sda_Pin,1) #define READ_SDA read_iic_sda //产生IIC起始信号 void IIC_Start(void) { 8002bac: b580 push {r7, lr} 8002bae: af00 add r7, sp, #0 SDA_OUT(); //sda线输出 8002bb0: 4b12 ldr r3, [pc, #72] ; (8002bfc ) 8002bb2: 2200 movs r2, #0 8002bb4: 2102 movs r1, #2 8002bb6: 0018 movs r0, r3 8002bb8: f7ff fe49 bl 800284e IIC_SDA_SET; 8002bbc: 4b0f ldr r3, [pc, #60] ; (8002bfc ) 8002bbe: 2201 movs r2, #1 8002bc0: 2102 movs r1, #2 8002bc2: 0018 movs r0, r3 8002bc4: f7fe fe45 bl 8001852 IIC_SCL_SET; 8002bc8: 2380 movs r3, #128 ; 0x80 8002bca: 00d9 lsls r1, r3, #3 8002bcc: 2390 movs r3, #144 ; 0x90 8002bce: 05db lsls r3, r3, #23 8002bd0: 2201 movs r2, #1 8002bd2: 0018 movs r0, r3 8002bd4: f7fe fe3d bl 8001852 IIC_SDA_CLR;//START:when CLK is high,DATA change form high to low 8002bd8: 4b08 ldr r3, [pc, #32] ; (8002bfc ) 8002bda: 2200 movs r2, #0 8002bdc: 2102 movs r1, #2 8002bde: 0018 movs r0, r3 8002be0: f7fe fe37 bl 8001852 IIC_SCL_CLR;//钳住I2C总线，准备发送或接收数据 8002be4: 2380 movs r3, #128 ; 0x80 8002be6: 00d9 lsls r1, r3, #3 8002be8: 2390 movs r3, #144 ; 0x90 8002bea: 05db lsls r3, r3, #23 8002bec: 2200 movs r2, #0 8002bee: 0018 movs r0, r3 8002bf0: f7fe fe2f bl 8001852 } 8002bf4: 46c0 nop ; (mov r8, r8) 8002bf6: 46bd mov sp, r7 8002bf8: bd80 pop {r7, pc} 8002bfa: 46c0 nop ; (mov r8, r8) 8002bfc: 48000400 .word 0x48000400 08002c00 : //产生IIC停止信号 void IIC_Stop(void) { 8002c00: b580 push {r7, lr} 8002c02: af00 add r7, sp, #0 SDA_OUT();//sda线输出 8002c04: 4b12 ldr r3, [pc, #72] ; (8002c50 ) 8002c06: 2200 movs r2, #0 8002c08: 2102 movs r1, #2 8002c0a: 0018 movs r0, r3 8002c0c: f7ff fe1f bl 800284e IIC_SCL_CLR; 8002c10: 2380 movs r3, #128 ; 0x80 8002c12: 00d9 lsls r1, r3, #3 8002c14: 2390 movs r3, #144 ; 0x90 8002c16: 05db lsls r3, r3, #23 8002c18: 2200 movs r2, #0 8002c1a: 0018 movs r0, r3 8002c1c: f7fe fe19 bl 8001852 IIC_SDA_CLR;//STOP:when CLK is high DATA change form low to high 8002c20: 4b0b ldr r3, [pc, #44] ; (8002c50 ) 8002c22: 2200 movs r2, #0 8002c24: 2102 movs r1, #2 8002c26: 0018 movs r0, r3 8002c28: f7fe fe13 bl 8001852 IIC_SCL_SET; 8002c2c: 2380 movs r3, #128 ; 0x80 8002c2e: 00d9 lsls r1, r3, #3 8002c30: 2390 movs r3, #144 ; 0x90 8002c32: 05db lsls r3, r3, #23 8002c34: 2201 movs r2, #1 8002c36: 0018 movs r0, r3 8002c38: f7fe fe0b bl 8001852 IIC_SDA_SET;//发送I2C总线结束信号 8002c3c: 4b04 ldr r3, [pc, #16] ; (8002c50 ) 8002c3e: 2201 movs r2, #1 8002c40: 2102 movs r1, #2 8002c42: 0018 movs r0, r3 8002c44: f7fe fe05 bl 8001852 } 8002c48: 46c0 nop ; (mov r8, r8) 8002c4a: 46bd mov sp, r7 8002c4c: bd80 pop {r7, pc} 8002c4e: 46c0 nop ; (mov r8, r8) 8002c50: 48000400 .word 0x48000400 08002c54 : //等待应答信号到来 //返回值：1，接收应答失败 // 0，接收应答成功 uint8_t IIC_Wait_Ack(void) { 8002c54: b580 push {r7, lr} 8002c56: b082 sub sp, #8 8002c58: af00 add r7, sp, #0 uint8_t ucErrTime=0; 8002c5a: 1dfb adds r3, r7, #7 8002c5c: 2200 movs r2, #0 8002c5e: 701a strb r2, [r3, #0] SDA_IN(); //SDA设置为输入 8002c60: 4b1a ldr r3, [pc, #104] ; (8002ccc ) 8002c62: 2201 movs r2, #1 8002c64: 2102 movs r1, #2 8002c66: 0018 movs r0, r3 8002c68: f7ff fdf1 bl 800284e IIC_SDA_SET; 8002c6c: 4b17 ldr r3, [pc, #92] ; (8002ccc ) 8002c6e: 2201 movs r2, #1 8002c70: 2102 movs r1, #2 8002c72: 0018 movs r0, r3 8002c74: f7fe fded bl 8001852 IIC_SCL_SET; 8002c78: 2380 movs r3, #128 ; 0x80 8002c7a: 00d9 lsls r1, r3, #3 8002c7c: 2390 movs r3, #144 ; 0x90 8002c7e: 05db lsls r3, r3, #23 8002c80: 2201 movs r2, #1 8002c82: 0018 movs r0, r3 8002c84: f7fe fde5 bl 8001852 while(READ_SDA) 8002c88: e00c b.n 8002ca4 { ucErrTime++; 8002c8a: 1dfb adds r3, r7, #7 8002c8c: 781a ldrb r2, [r3, #0] 8002c8e: 1dfb adds r3, r7, #7 8002c90: 3201 adds r2, #1 8002c92: 701a strb r2, [r3, #0] if(ucErrTime>250) 8002c94: 1dfb adds r3, r7, #7 8002c96: 781b ldrb r3, [r3, #0] 8002c98: 2bfa cmp r3, #250 ; 0xfa 8002c9a: d903 bls.n 8002ca4 { IIC_Stop(); 8002c9c: f7ff ffb0 bl 8002c00 return 1; 8002ca0: 2301 movs r3, #1 8002ca2: e00f b.n 8002cc4 while(READ_SDA) 8002ca4: 4b09 ldr r3, [pc, #36] ; (8002ccc ) 8002ca6: 2102 movs r1, #2 8002ca8: 0018 movs r0, r3 8002caa: f7fe fdb5 bl 8001818 8002cae: 1e03 subs r3, r0, #0 8002cb0: d1eb bne.n 8002c8a } } IIC_SCL_CLR;//时钟输出0 8002cb2: 2380 movs r3, #128 ; 0x80 8002cb4: 00d9 lsls r1, r3, #3 8002cb6: 2390 movs r3, #144 ; 0x90 8002cb8: 05db lsls r3, r3, #23 8002cba: 2200 movs r2, #0 8002cbc: 0018 movs r0, r3 8002cbe: f7fe fdc8 bl 8001852 return 0; 8002cc2: 2300 movs r3, #0 } 8002cc4: 0018 movs r0, r3 8002cc6: 46bd mov sp, r7 8002cc8: b002 add sp, #8 8002cca: bd80 pop {r7, pc} 8002ccc: 48000400 .word 0x48000400 08002cd0 : //产生ACK应答 void IIC_Ack(void) { 8002cd0: b580 push {r7, lr} 8002cd2: af00 add r7, sp, #0 IIC_SCL_CLR; 8002cd4: 2380 movs r3, #128 ; 0x80 8002cd6: 00d9 lsls r1, r3, #3 8002cd8: 2390 movs r3, #144 ; 0x90 8002cda: 05db lsls r3, r3, #23 8002cdc: 2200 movs r2, #0 8002cde: 0018 movs r0, r3 8002ce0: f7fe fdb7 bl 8001852 SDA_OUT(); 8002ce4: 4b0f ldr r3, [pc, #60] ; (8002d24 ) 8002ce6: 2200 movs r2, #0 8002ce8: 2102 movs r1, #2 8002cea: 0018 movs r0, r3 8002cec: f7ff fdaf bl 800284e IIC_SDA_CLR; 8002cf0: 4b0c ldr r3, [pc, #48] ; (8002d24 ) 8002cf2: 2200 movs r2, #0 8002cf4: 2102 movs r1, #2 8002cf6: 0018 movs r0, r3 8002cf8: f7fe fdab bl 8001852 IIC_SCL_SET; 8002cfc: 2380 movs r3, #128 ; 0x80 8002cfe: 00d9 lsls r1, r3, #3 8002d00: 2390 movs r3, #144 ; 0x90 8002d02: 05db lsls r3, r3, #23 8002d04: 2201 movs r2, #1 8002d06: 0018 movs r0, r3 8002d08: f7fe fda3 bl 8001852 IIC_SCL_CLR; 8002d0c: 2380 movs r3, #128 ; 0x80 8002d0e: 00d9 lsls r1, r3, #3 8002d10: 2390 movs r3, #144 ; 0x90 8002d12: 05db lsls r3, r3, #23 8002d14: 2200 movs r2, #0 8002d16: 0018 movs r0, r3 8002d18: f7fe fd9b bl 8001852 } 8002d1c: 46c0 nop ; (mov r8, r8) 8002d1e: 46bd mov sp, r7 8002d20: bd80 pop {r7, pc} 8002d22: 46c0 nop ; (mov r8, r8) 8002d24: 48000400 .word 0x48000400 08002d28 : //不产生ACK应答 void IIC_NAck(void) { 8002d28: b580 push {r7, lr} 8002d2a: af00 add r7, sp, #0 IIC_SCL_CLR; 8002d2c: 2380 movs r3, #128 ; 0x80 8002d2e: 00d9 lsls r1, r3, #3 8002d30: 2390 movs r3, #144 ; 0x90 8002d32: 05db lsls r3, r3, #23 8002d34: 2200 movs r2, #0 8002d36: 0018 movs r0, r3 8002d38: f7fe fd8b bl 8001852 SDA_OUT(); 8002d3c: 4b0f ldr r3, [pc, #60] ; (8002d7c ) 8002d3e: 2200 movs r2, #0 8002d40: 2102 movs r1, #2 8002d42: 0018 movs r0, r3 8002d44: f7ff fd83 bl 800284e IIC_SDA_SET; 8002d48: 4b0c ldr r3, [pc, #48] ; (8002d7c ) 8002d4a: 2201 movs r2, #1 8002d4c: 2102 movs r1, #2 8002d4e: 0018 movs r0, r3 8002d50: f7fe fd7f bl 8001852 IIC_SCL_SET; 8002d54: 2380 movs r3, #128 ; 0x80 8002d56: 00d9 lsls r1, r3, #3 8002d58: 2390 movs r3, #144 ; 0x90 8002d5a: 05db lsls r3, r3, #23 8002d5c: 2201 movs r2, #1 8002d5e: 0018 movs r0, r3 8002d60: f7fe fd77 bl 8001852 IIC_SCL_CLR; 8002d64: 2380 movs r3, #128 ; 0x80 8002d66: 00d9 lsls r1, r3, #3 8002d68: 2390 movs r3, #144 ; 0x90 8002d6a: 05db lsls r3, r3, #23 8002d6c: 2200 movs r2, #0 8002d6e: 0018 movs r0, r3 8002d70: f7fe fd6f bl 8001852 } 8002d74: 46c0 nop ; (mov r8, r8) 8002d76: 46bd mov sp, r7 8002d78: bd80 pop {r7, pc} 8002d7a: 46c0 nop ; (mov r8, r8) 8002d7c: 48000400 .word 0x48000400 08002d80 : //IIC发送一个字节 //返回从机有无应答 //1，有应答 //0，无应答 void IIC_Send_Byte(uint8_t txd) { 8002d80: b580 push {r7, lr} 8002d82: b084 sub sp, #16 8002d84: af00 add r7, sp, #0 8002d86: 0002 movs r2, r0 8002d88: 1dfb adds r3, r7, #7 8002d8a: 701a strb r2, [r3, #0] uint8_t t; SDA_OUT(); 8002d8c: 4b24 ldr r3, [pc, #144] ; (8002e20 ) 8002d8e: 2200 movs r2, #0 8002d90: 2102 movs r1, #2 8002d92: 0018 movs r0, r3 8002d94: f7ff fd5b bl 800284e IIC_SCL_CLR;//拉低时钟开始数据传输 8002d98: 2380 movs r3, #128 ; 0x80 8002d9a: 00d9 lsls r1, r3, #3 8002d9c: 2390 movs r3, #144 ; 0x90 8002d9e: 05db lsls r3, r3, #23 8002da0: 2200 movs r2, #0 8002da2: 0018 movs r0, r3 8002da4: f7fe fd55 bl 8001852 for(t=0;t<8;t++) 8002da8: 230f movs r3, #15 8002daa: 18fb adds r3, r7, r3 8002dac: 2200 movs r2, #0 8002dae: 701a strb r2, [r3, #0] 8002db0: e02c b.n 8002e0c { //IIC_SDA=(txd&0x80)>>7; if((txd&0x80)>>7) 8002db2: 1dfb adds r3, r7, #7 8002db4: 781b ldrb r3, [r3, #0] 8002db6: b25b sxtb r3, r3 8002db8: 2b00 cmp r3, #0 8002dba: da06 bge.n 8002dca IIC_SDA_SET; 8002dbc: 4b18 ldr r3, [pc, #96] ; (8002e20 ) 8002dbe: 2201 movs r2, #1 8002dc0: 2102 movs r1, #2 8002dc2: 0018 movs r0, r3 8002dc4: f7fe fd45 bl 8001852 8002dc8: e005 b.n 8002dd6 else IIC_SDA_CLR; 8002dca: 4b15 ldr r3, [pc, #84] ; (8002e20 ) 8002dcc: 2200 movs r2, #0 8002dce: 2102 movs r1, #2 8002dd0: 0018 movs r0, r3 8002dd2: f7fe fd3e bl 8001852 txd<<=1; 8002dd6: 1dfa adds r2, r7, #7 8002dd8: 1dfb adds r3, r7, #7 8002dda: 781b ldrb r3, [r3, #0] 8002ddc: 18db adds r3, r3, r3 8002dde: 7013 strb r3, [r2, #0] IIC_SCL_SET; 8002de0: 2380 movs r3, #128 ; 0x80 8002de2: 00d9 lsls r1, r3, #3 8002de4: 2390 movs r3, #144 ; 0x90 8002de6: 05db lsls r3, r3, #23 8002de8: 2201 movs r2, #1 8002dea: 0018 movs r0, r3 8002dec: f7fe fd31 bl 8001852 IIC_SCL_CLR; 8002df0: 2380 movs r3, #128 ; 0x80 8002df2: 00d9 lsls r1, r3, #3 8002df4: 2390 movs r3, #144 ; 0x90 8002df6: 05db lsls r3, r3, #23 8002df8: 2200 movs r2, #0 8002dfa: 0018 movs r0, r3 8002dfc: f7fe fd29 bl 8001852 for(t=0;t<8;t++) 8002e00: 210f movs r1, #15 8002e02: 187b adds r3, r7, r1 8002e04: 781a ldrb r2, [r3, #0] 8002e06: 187b adds r3, r7, r1 8002e08: 3201 adds r2, #1 8002e0a: 701a strb r2, [r3, #0] 8002e0c: 230f movs r3, #15 8002e0e: 18fb adds r3, r7, r3 8002e10: 781b ldrb r3, [r3, #0] 8002e12: 2b07 cmp r3, #7 8002e14: d9cd bls.n 8002db2 } } 8002e16: 46c0 nop ; (mov r8, r8) 8002e18: 46c0 nop ; (mov r8, r8) 8002e1a: 46bd mov sp, r7 8002e1c: b004 add sp, #16 8002e1e: bd80 pop {r7, pc} 8002e20: 48000400 .word 0x48000400 08002e24 : //读1个字节，ack=1时，发送ACK，ack=0，发送nACK uint8_t IIC_Read_Byte(unsigned char ack) { 8002e24: b590 push {r4, r7, lr} 8002e26: b085 sub sp, #20 8002e28: af00 add r7, sp, #0 8002e2a: 0002 movs r2, r0 8002e2c: 1dfb adds r3, r7, #7 8002e2e: 701a strb r2, [r3, #0] unsigned char i,receive=0; 8002e30: 230e movs r3, #14 8002e32: 18fb adds r3, r7, r3 8002e34: 2200 movs r2, #0 8002e36: 701a strb r2, [r3, #0] SDA_IN();//SDA设置为输入 8002e38: 4b23 ldr r3, [pc, #140] ; (8002ec8 ) 8002e3a: 2201 movs r2, #1 8002e3c: 2102 movs r1, #2 8002e3e: 0018 movs r0, r3 8002e40: f7ff fd05 bl 800284e for(i=0;i<8;i++ ) 8002e44: 230f movs r3, #15 8002e46: 18fb adds r3, r7, r3 8002e48: 2200 movs r2, #0 8002e4a: 701a strb r2, [r3, #0] 8002e4c: e027 b.n 8002e9e { IIC_SCL_CLR; 8002e4e: 2380 movs r3, #128 ; 0x80 8002e50: 00d9 lsls r1, r3, #3 8002e52: 2390 movs r3, #144 ; 0x90 8002e54: 05db lsls r3, r3, #23 8002e56: 2200 movs r2, #0 8002e58: 0018 movs r0, r3 8002e5a: f7fe fcfa bl 8001852 IIC_SCL_SET; 8002e5e: 2380 movs r3, #128 ; 0x80 8002e60: 00d9 lsls r1, r3, #3 8002e62: 2390 movs r3, #144 ; 0x90 8002e64: 05db lsls r3, r3, #23 8002e66: 2201 movs r2, #1 8002e68: 0018 movs r0, r3 8002e6a: f7fe fcf2 bl 8001852 receive<<=1; 8002e6e: 240e movs r4, #14 8002e70: 193a adds r2, r7, r4 8002e72: 193b adds r3, r7, r4 8002e74: 781b ldrb r3, [r3, #0] 8002e76: 18db adds r3, r3, r3 8002e78: 7013 strb r3, [r2, #0] if(READ_SDA)receive++; 8002e7a: 4b13 ldr r3, [pc, #76] ; (8002ec8 ) 8002e7c: 2102 movs r1, #2 8002e7e: 0018 movs r0, r3 8002e80: f7fe fcca bl 8001818 8002e84: 1e03 subs r3, r0, #0 8002e86: d004 beq.n 8002e92 8002e88: 193b adds r3, r7, r4 8002e8a: 781a ldrb r2, [r3, #0] 8002e8c: 193b adds r3, r7, r4 8002e8e: 3201 adds r2, #1 8002e90: 701a strb r2, [r3, #0] for(i=0;i<8;i++ ) 8002e92: 210f movs r1, #15 8002e94: 187b adds r3, r7, r1 8002e96: 781a ldrb r2, [r3, #0] 8002e98: 187b adds r3, r7, r1 8002e9a: 3201 adds r2, #1 8002e9c: 701a strb r2, [r3, #0] 8002e9e: 230f movs r3, #15 8002ea0: 18fb adds r3, r7, r3 8002ea2: 781b ldrb r3, [r3, #0] 8002ea4: 2b07 cmp r3, #7 8002ea6: d9d2 bls.n 8002e4e } if (!ack) 8002ea8: 1dfb adds r3, r7, #7 8002eaa: 781b ldrb r3, [r3, #0] 8002eac: 2b00 cmp r3, #0 8002eae: d102 bne.n 8002eb6 IIC_NAck();//发送nACK 8002eb0: f7ff ff3a bl 8002d28 8002eb4: e001 b.n 8002eba else IIC_Ack(); //发送ACK 8002eb6: f7ff ff0b bl 8002cd0 return receive; 8002eba: 230e movs r3, #14 8002ebc: 18fb adds r3, r7, r3 8002ebe: 781b ldrb r3, [r3, #0] } 8002ec0: 0018 movs r0, r3 8002ec2: 46bd mov sp, r7 8002ec4: b005 add sp, #20 8002ec6: bd90 pop {r4, r7, pc} 8002ec8: 48000400 .word 0x48000400 08002ecc : //return READ_HC595_DCK; } //send data to 959 void Sand_Byte_to_595_2(uint8_t h) { 8002ecc: b580 push {r7, lr} 8002ece: b084 sub sp, #16 8002ed0: af00 add r7, sp, #0 8002ed2: 0002 movs r2, r0 8002ed4: 1dfb adds r3, r7, #7 8002ed6: 701a strb r2, [r3, #0] change_io_function(HC595_DLK_GPIO_Port,HC595_DLK_Pin,0); 8002ed8: 2390 movs r3, #144 ; 0x90 8002eda: 05db lsls r3, r3, #23 8002edc: 2200 movs r2, #0 8002ede: 2120 movs r1, #32 8002ee0: 0018 movs r0, r3 8002ee2: f7ff fcb4 bl 800284e HC595_DCK(0); 8002ee6: 2390 movs r3, #144 ; 0x90 8002ee8: 05db lsls r3, r3, #23 8002eea: 2200 movs r2, #0 8002eec: 2120 movs r1, #32 8002eee: 0018 movs r0, r3 8002ef0: f7fe fcaf bl 8001852 HC595_SCK2(0); 8002ef4: 2380 movs r3, #128 ; 0x80 8002ef6: 0099 lsls r1, r3, #2 8002ef8: 2390 movs r3, #144 ; 0x90 8002efa: 05db lsls r3, r3, #23 8002efc: 2200 movs r2, #0 8002efe: 0018 movs r0, r3 8002f00: f7fe fca7 bl 8001852 HC595_RCK(0); 8002f04: 2390 movs r3, #144 ; 0x90 8002f06: 05db lsls r3, r3, #23 8002f08: 2200 movs r2, #0 8002f0a: 2180 movs r1, #128 ; 0x80 8002f0c: 0018 movs r0, r3 8002f0e: f7fe fca0 bl 8001852 for(char a=0;a<8;a++) 8002f12: 230f movs r3, #15 8002f14: 18fb adds r3, r7, r3 8002f16: 2200 movs r2, #0 8002f18: 701a strb r2, [r3, #0] 8002f1a: e02e b.n 8002f7a { if((h< { HC595_DCK(1); 8002f30: 2390 movs r3, #144 ; 0x90 8002f32: 05db lsls r3, r3, #23 8002f34: 2201 movs r2, #1 8002f36: 2120 movs r1, #32 8002f38: 0018 movs r0, r3 8002f3a: f7fe fc8a bl 8001852 8002f3e: e006 b.n 8002f4e }else { HC595_DCK(0); 8002f40: 2390 movs r3, #144 ; 0x90 8002f42: 05db lsls r3, r3, #23 8002f44: 2200 movs r2, #0 8002f46: 2120 movs r1, #32 8002f48: 0018 movs r0, r3 8002f4a: f7fe fc82 bl 8001852 } HC595_SCK2(1); 8002f4e: 2380 movs r3, #128 ; 0x80 8002f50: 0099 lsls r1, r3, #2 8002f52: 2390 movs r3, #144 ; 0x90 8002f54: 05db lsls r3, r3, #23 8002f56: 2201 movs r2, #1 8002f58: 0018 movs r0, r3 8002f5a: f7fe fc7a bl 8001852 HC595_SCK2(0); 8002f5e: 2380 movs r3, #128 ; 0x80 8002f60: 0099 lsls r1, r3, #2 8002f62: 2390 movs r3, #144 ; 0x90 8002f64: 05db lsls r3, r3, #23 8002f66: 2200 movs r2, #0 8002f68: 0018 movs r0, r3 8002f6a: f7fe fc72 bl 8001852 for(char a=0;a<8;a++) 8002f6e: 210f movs r1, #15 8002f70: 187b adds r3, r7, r1 8002f72: 781a ldrb r2, [r3, #0] 8002f74: 187b adds r3, r7, r1 8002f76: 3201 adds r2, #1 8002f78: 701a strb r2, [r3, #0] 8002f7a: 230f movs r3, #15 8002f7c: 18fb adds r3, r7, r3 8002f7e: 781b ldrb r3, [r3, #0] 8002f80: 2b07 cmp r3, #7 8002f82: d9cb bls.n 8002f1c } HC595_RCK(1); 8002f84: 2390 movs r3, #144 ; 0x90 8002f86: 05db lsls r3, r3, #23 8002f88: 2201 movs r2, #1 8002f8a: 2180 movs r1, #128 ; 0x80 8002f8c: 0018 movs r0, r3 8002f8e: f7fe fc60 bl 8001852 HC595_RCK(0); 8002f92: 2390 movs r3, #144 ; 0x90 8002f94: 05db lsls r3, r3, #23 8002f96: 2200 movs r2, #0 8002f98: 2180 movs r1, #128 ; 0x80 8002f9a: 0018 movs r0, r3 8002f9c: f7fe fc59 bl 8001852 } 8002fa0: 46c0 nop ; (mov r8, r8) 8002fa2: 46bd mov sp, r7 8002fa4: b004 add sp, #16 8002fa6: bd80 pop {r7, pc} 08002fa8 : void hc2_sever() { 8002fa8: b580 push {r7, lr} 8002faa: b082 sub sp, #8 8002fac: af00 add r7, sp, #0 char h=0; 8002fae: 1dfb adds r3, r7, #7 8002fb0: 2200 movs r2, #0 8002fb2: 701a strb r2, [r3, #0] if(dis_buff.led_run==1) 8002fb4: 4b1d ldr r3, [pc, #116] ; (800302c ) 8002fb6: 7b1b ldrb r3, [r3, #12] 8002fb8: 2b01 cmp r3, #1 8002fba: d105 bne.n 8002fc8 { h|=0x01; 8002fbc: 1dfb adds r3, r7, #7 8002fbe: 1dfa adds r2, r7, #7 8002fc0: 7812 ldrb r2, [r2, #0] 8002fc2: 2101 movs r1, #1 8002fc4: 430a orrs r2, r1 8002fc6: 701a strb r2, [r3, #0] } if(dis_buff.moto1a==1) 8002fc8: 4b18 ldr r3, [pc, #96] ; (800302c ) 8002fca: 7b5b ldrb r3, [r3, #13] 8002fcc: 2b01 cmp r3, #1 8002fce: d105 bne.n 8002fdc { h|=0x02; 8002fd0: 1dfb adds r3, r7, #7 8002fd2: 1dfa adds r2, r7, #7 8002fd4: 7812 ldrb r2, [r2, #0] 8002fd6: 2102 movs r1, #2 8002fd8: 430a orrs r2, r1 8002fda: 701a strb r2, [r3, #0] } if(dis_buff.moto1b==1) 8002fdc: 4b13 ldr r3, [pc, #76] ; (800302c ) 8002fde: 7b9b ldrb r3, [r3, #14] 8002fe0: 2b01 cmp r3, #1 8002fe2: d105 bne.n 8002ff0 { h|=0x04; 8002fe4: 1dfb adds r3, r7, #7 8002fe6: 1dfa adds r2, r7, #7 8002fe8: 7812 ldrb r2, [r2, #0] 8002fea: 2104 movs r1, #4 8002fec: 430a orrs r2, r1 8002fee: 701a strb r2, [r3, #0] } if(dis_buff.moto2a==1) 8002ff0: 4b0e ldr r3, [pc, #56] ; (800302c ) 8002ff2: 7bdb ldrb r3, [r3, #15] 8002ff4: 2b01 cmp r3, #1 8002ff6: d105 bne.n 8003004 { h|=0x08; 8002ff8: 1dfb adds r3, r7, #7 8002ffa: 1dfa adds r2, r7, #7 8002ffc: 7812 ldrb r2, [r2, #0] 8002ffe: 2108 movs r1, #8 8003000: 430a orrs r2, r1 8003002: 701a strb r2, [r3, #0] } if(dis_buff.moto2b==1) 8003004: 4b09 ldr r3, [pc, #36] ; (800302c ) 8003006: 7c1b ldrb r3, [r3, #16] 8003008: 2b01 cmp r3, #1 800300a: d105 bne.n 8003018 { h|=0x10; 800300c: 1dfb adds r3, r7, #7 800300e: 1dfa adds r2, r7, #7 8003010: 7812 ldrb r2, [r2, #0] 8003012: 2110 movs r1, #16 8003014: 430a orrs r2, r1 8003016: 701a strb r2, [r3, #0] } Sand_Byte_to_595_2(h); 8003018: 1dfb adds r3, r7, #7 800301a: 781b ldrb r3, [r3, #0] 800301c: 0018 movs r0, r3 800301e: f7ff ff55 bl 8002ecc } 8003022: 46c0 nop ; (mov r8, r8) 8003024: 46bd mov sp, r7 8003026: b002 add sp, #8 8003028: bd80 pop {r7, pc} 800302a: 46c0 nop ; (mov r8, r8) 800302c: 20000038 .word 0x20000038 08003030 : //motor cool start void moto_server() { 8003030: b580 push {r7, lr} 8003032: af00 add r7, sp, #0 if(HAL_GetTick()>moto.moto_run) 8003034: f7fd fce8 bl 8000a08 8003038: 0002 movs r2, r0 800303a: 4b63 ldr r3, [pc, #396] ; (80031c8 ) 800303c: 681b ldr r3, [r3, #0] 800303e: 429a cmp r2, r3 8003040: d800 bhi.n 8003044 8003042: e07e b.n 8003142 { moto.moto_run=HAL_GetTick()+10; 8003044: f7fd fce0 bl 8000a08 8003048: 0003 movs r3, r0 800304a: 330a adds r3, #10 800304c: 001a movs r2, r3 800304e: 4b5e ldr r3, [pc, #376] ; (80031c8 ) 8003050: 601a str r2, [r3, #0] if(moto.moto1a!=moto.moto1a_) 8003052: 4b5d ldr r3, [pc, #372] ; (80031c8 ) 8003054: 7a1a ldrb r2, [r3, #8] 8003056: 4b5c ldr r3, [pc, #368] ; (80031c8 ) 8003058: 7b1b ldrb r3, [r3, #12] 800305a: 429a cmp r2, r3 800305c: d017 beq.n 800308e { if(moto.moto1a>moto.moto1a_) 800305e: 4b5a ldr r3, [pc, #360] ; (80031c8 ) 8003060: 7a1a ldrb r2, [r3, #8] 8003062: 4b59 ldr r3, [pc, #356] ; (80031c8 ) 8003064: 7b1b ldrb r3, [r3, #12] 8003066: 429a cmp r2, r3 8003068: d905 bls.n 8003076 { moto.moto1a_++; 800306a: 4b57 ldr r3, [pc, #348] ; (80031c8 ) 800306c: 7b1b ldrb r3, [r3, #12] 800306e: 3301 adds r3, #1 8003070: b2da uxtb r2, r3 8003072: 4b55 ldr r3, [pc, #340] ; (80031c8 ) 8003074: 731a strb r2, [r3, #12] } if(moto.moto1a) 8003078: 7a1a ldrb r2, [r3, #8] 800307a: 4b53 ldr r3, [pc, #332] ; (80031c8 ) 800307c: 7b1b ldrb r3, [r3, #12] 800307e: 429a cmp r2, r3 8003080: d205 bcs.n 800308e { moto.moto1a_--; 8003082: 4b51 ldr r3, [pc, #324] ; (80031c8 ) 8003084: 7b1b ldrb r3, [r3, #12] 8003086: 3b01 subs r3, #1 8003088: b2da uxtb r2, r3 800308a: 4b4f ldr r3, [pc, #316] ; (80031c8 ) 800308c: 731a strb r2, [r3, #12] } } if(moto.moto1b!=moto.moto1b_) 800308e: 4b4e ldr r3, [pc, #312] ; (80031c8 ) 8003090: 7a5a ldrb r2, [r3, #9] 8003092: 4b4d ldr r3, [pc, #308] ; (80031c8 ) 8003094: 7b5b ldrb r3, [r3, #13] 8003096: 429a cmp r2, r3 8003098: d017 beq.n 80030ca { if(moto.moto1b>moto.moto1b_) 800309a: 4b4b ldr r3, [pc, #300] ; (80031c8 ) 800309c: 7a5a ldrb r2, [r3, #9] 800309e: 4b4a ldr r3, [pc, #296] ; (80031c8 ) 80030a0: 7b5b ldrb r3, [r3, #13] 80030a2: 429a cmp r2, r3 80030a4: d905 bls.n 80030b2 { moto.moto1b_++; 80030a6: 4b48 ldr r3, [pc, #288] ; (80031c8 ) 80030a8: 7b5b ldrb r3, [r3, #13] 80030aa: 3301 adds r3, #1 80030ac: b2da uxtb r2, r3 80030ae: 4b46 ldr r3, [pc, #280] ; (80031c8 ) 80030b0: 735a strb r2, [r3, #13] } if(moto.moto1b) 80030b4: 7a5a ldrb r2, [r3, #9] 80030b6: 4b44 ldr r3, [pc, #272] ; (80031c8 ) 80030b8: 7b5b ldrb r3, [r3, #13] 80030ba: 429a cmp r2, r3 80030bc: d205 bcs.n 80030ca { moto.moto1b_--; 80030be: 4b42 ldr r3, [pc, #264] ; (80031c8 ) 80030c0: 7b5b ldrb r3, [r3, #13] 80030c2: 3b01 subs r3, #1 80030c4: b2da uxtb r2, r3 80030c6: 4b40 ldr r3, [pc, #256] ; (80031c8 ) 80030c8: 735a strb r2, [r3, #13] } } if(moto.moto2a!=moto.moto2a_) 80030ca: 4b3f ldr r3, [pc, #252] ; (80031c8 ) 80030cc: 7a9a ldrb r2, [r3, #10] 80030ce: 4b3e ldr r3, [pc, #248] ; (80031c8 ) 80030d0: 7b9b ldrb r3, [r3, #14] 80030d2: 429a cmp r2, r3 80030d4: d017 beq.n 8003106 { if(moto.moto2a>moto.moto2a_) 80030d6: 4b3c ldr r3, [pc, #240] ; (80031c8 ) 80030d8: 7a9a ldrb r2, [r3, #10] 80030da: 4b3b ldr r3, [pc, #236] ; (80031c8 ) 80030dc: 7b9b ldrb r3, [r3, #14] 80030de: 429a cmp r2, r3 80030e0: d905 bls.n 80030ee { moto.moto2a_++; 80030e2: 4b39 ldr r3, [pc, #228] ; (80031c8 ) 80030e4: 7b9b ldrb r3, [r3, #14] 80030e6: 3301 adds r3, #1 80030e8: b2da uxtb r2, r3 80030ea: 4b37 ldr r3, [pc, #220] ; (80031c8 ) 80030ec: 739a strb r2, [r3, #14] } if(moto.moto2a) 80030f0: 7a9a ldrb r2, [r3, #10] 80030f2: 4b35 ldr r3, [pc, #212] ; (80031c8 ) 80030f4: 7b9b ldrb r3, [r3, #14] 80030f6: 429a cmp r2, r3 80030f8: d205 bcs.n 8003106 { moto.moto2a_--; 80030fa: 4b33 ldr r3, [pc, #204] ; (80031c8 ) 80030fc: 7b9b ldrb r3, [r3, #14] 80030fe: 3b01 subs r3, #1 8003100: b2da uxtb r2, r3 8003102: 4b31 ldr r3, [pc, #196] ; (80031c8 ) 8003104: 739a strb r2, [r3, #14] } } if(moto.moto2b!=moto.moto2b_) 8003106: 4b30 ldr r3, [pc, #192] ; (80031c8 ) 8003108: 7ada ldrb r2, [r3, #11] 800310a: 4b2f ldr r3, [pc, #188] ; (80031c8 ) 800310c: 7bdb ldrb r3, [r3, #15] 800310e: 429a cmp r2, r3 8003110: d017 beq.n 8003142 { if(moto.moto2b>moto.moto2b_) 8003112: 4b2d ldr r3, [pc, #180] ; (80031c8 ) 8003114: 7ada ldrb r2, [r3, #11] 8003116: 4b2c ldr r3, [pc, #176] ; (80031c8 ) 8003118: 7bdb ldrb r3, [r3, #15] 800311a: 429a cmp r2, r3 800311c: d905 bls.n 800312a { moto.moto2b_++; 800311e: 4b2a ldr r3, [pc, #168] ; (80031c8 ) 8003120: 7bdb ldrb r3, [r3, #15] 8003122: 3301 adds r3, #1 8003124: b2da uxtb r2, r3 8003126: 4b28 ldr r3, [pc, #160] ; (80031c8 ) 8003128: 73da strb r2, [r3, #15] } if(moto.moto2b) 800312c: 7ada ldrb r2, [r3, #11] 800312e: 4b26 ldr r3, [pc, #152] ; (80031c8 ) 8003130: 7bdb ldrb r3, [r3, #15] 8003132: 429a cmp r2, r3 8003134: d205 bcs.n 8003142 { moto.moto2b_--; 8003136: 4b24 ldr r3, [pc, #144] ; (80031c8 ) 8003138: 7bdb ldrb r3, [r3, #15] 800313a: 3b01 subs r3, #1 800313c: b2da uxtb r2, r3 800313e: 4b22 ldr r3, [pc, #136] ; (80031c8 ) 8003140: 73da strb r2, [r3, #15] moto.pwm_run++; 8003142: 4b21 ldr r3, [pc, #132] ; (80031c8 ) 8003144: 685b ldr r3, [r3, #4] 8003146: 1c5a adds r2, r3, #1 8003148: 4b1f ldr r3, [pc, #124] ; (80031c8 ) 800314a: 605a str r2, [r3, #4] if(moto.pwm_run==10) 800314c: 4b1e ldr r3, [pc, #120] ; (80031c8 ) 800314e: 685b ldr r3, [r3, #4] 8003150: 2b0a cmp r3, #10 8003152: d102 bne.n 800315a { moto.pwm_run=0; 8003154: 4b1c ldr r3, [pc, #112] ; (80031c8 ) 8003156: 2200 movs r2, #0 8003158: 605a str r2, [r3, #4] } if(moto.pwm_run) 800315c: 685b ldr r3, [r3, #4] 800315e: 4a1a ldr r2, [pc, #104] ; (80031c8 ) 8003160: 7b12 ldrb r2, [r2, #12] 8003162: 4293 cmp r3, r2 8003164: da03 bge.n 800316e { dis_buff.moto1a=1; 8003166: 4b19 ldr r3, [pc, #100] ; (80031cc ) 8003168: 2201 movs r2, #1 800316a: 735a strb r2, [r3, #13] 800316c: e002 b.n 8003174 }else { dis_buff.moto1a=0; 800316e: 4b17 ldr r3, [pc, #92] ; (80031cc ) 8003170: 2200 movs r2, #0 8003172: 735a strb r2, [r3, #13] } if(moto.pwm_run) 8003176: 685b ldr r3, [r3, #4] 8003178: 4a13 ldr r2, [pc, #76] ; (80031c8 ) 800317a: 7b52 ldrb r2, [r2, #13] 800317c: 4293 cmp r3, r2 800317e: da03 bge.n 8003188 { dis_buff.moto1b=1; 8003180: 4b12 ldr r3, [pc, #72] ; (80031cc ) 8003182: 2201 movs r2, #1 8003184: 739a strb r2, [r3, #14] 8003186: e002 b.n 800318e }else { dis_buff.moto1b=0; 8003188: 4b10 ldr r3, [pc, #64] ; (80031cc ) 800318a: 2200 movs r2, #0 800318c: 739a strb r2, [r3, #14] } if(moto.pwm_run) 8003190: 685b ldr r3, [r3, #4] 8003192: 4a0d ldr r2, [pc, #52] ; (80031c8 ) 8003194: 7b92 ldrb r2, [r2, #14] 8003196: 4293 cmp r3, r2 8003198: da03 bge.n 80031a2 { dis_buff.moto2a=1; 800319a: 4b0c ldr r3, [pc, #48] ; (80031cc ) 800319c: 2201 movs r2, #1 800319e: 73da strb r2, [r3, #15] 80031a0: e002 b.n 80031a8 }else { dis_buff.moto2a=0; 80031a2: 4b0a ldr r3, [pc, #40] ; (80031cc ) 80031a4: 2200 movs r2, #0 80031a6: 73da strb r2, [r3, #15] } if(moto.pwm_run) 80031aa: 685b ldr r3, [r3, #4] 80031ac: 4a06 ldr r2, [pc, #24] ; (80031c8 ) 80031ae: 7bd2 ldrb r2, [r2, #15] 80031b0: 4293 cmp r3, r2 80031b2: da03 bge.n 80031bc { dis_buff.moto2b=1; 80031b4: 4b05 ldr r3, [pc, #20] ; (80031cc ) 80031b6: 2201 movs r2, #1 80031b8: 741a strb r2, [r3, #16] }else { dis_buff.moto2b=0; } } 80031ba: e002 b.n 80031c2 dis_buff.moto2b=0; 80031bc: 4b03 ldr r3, [pc, #12] ; (80031cc ) 80031be: 2200 movs r2, #0 80031c0: 741a strb r2, [r3, #16] } 80031c2: 46c0 nop ; (mov r8, r8) 80031c4: 46bd mov sp, r7 80031c6: bd80 pop {r7, pc} 80031c8: 20000144 .word 0x20000144 80031cc: 20000038 .word 0x20000038 080031d0 : #define E 0x08 #define F 0x04 #define G 0x02 #define H 0x01 void HT1621_Display_GetButton(void) { 80031d0: b580 push {r7, lr} 80031d2: b084 sub sp, #16 80031d4: af00 add r7, sp, #0 unsigned char send_buff[8]; unsigned char lcd_buff[4]; //WritenDataHT1621(0,send_buff,8); lcd_buff[0]=LED_Tab[dis_buff.d_num[0]]; 80031d6: 4b45 ldr r3, [pc, #276] ; (80032ec ) 80031d8: 781b ldrb r3, [r3, #0] 80031da: 001a movs r2, r3 80031dc: 4b44 ldr r3, [pc, #272] ; (80032f0 ) 80031de: 5c9a ldrb r2, [r3, r2] 80031e0: 1d3b adds r3, r7, #4 80031e2: 701a strb r2, [r3, #0] if(dis_buff.dot1==1) 80031e4: 4b41 ldr r3, [pc, #260] ; (80032ec ) 80031e6: 7a1b ldrb r3, [r3, #8] 80031e8: 2b01 cmp r3, #1 80031ea: d107 bne.n 80031fc { lcd_buff[0]|=0x80; 80031ec: 1d3b adds r3, r7, #4 80031ee: 781b ldrb r3, [r3, #0] 80031f0: 2280 movs r2, #128 ; 0x80 80031f2: 4252 negs r2, r2 80031f4: 4313 orrs r3, r2 80031f6: b2da uxtb r2, r3 80031f8: 1d3b adds r3, r7, #4 80031fa: 701a strb r2, [r3, #0] } lcd_buff[1]=LED_Tab[dis_buff.d_num[1]]; 80031fc: 4b3b ldr r3, [pc, #236] ; (80032ec ) 80031fe: 785b ldrb r3, [r3, #1] 8003200: 001a movs r2, r3 8003202: 4b3b ldr r3, [pc, #236] ; (80032f0 ) 8003204: 5c9a ldrb r2, [r3, r2] 8003206: 1d3b adds r3, r7, #4 8003208: 705a strb r2, [r3, #1] if(dis_buff.dot2==1) 800320a: 4b38 ldr r3, [pc, #224] ; (80032ec ) 800320c: 7a5b ldrb r3, [r3, #9] 800320e: 2b01 cmp r3, #1 8003210: d107 bne.n 8003222 { lcd_buff[1]|=0x80; 8003212: 1d3b adds r3, r7, #4 8003214: 785b ldrb r3, [r3, #1] 8003216: 2280 movs r2, #128 ; 0x80 8003218: 4252 negs r2, r2 800321a: 4313 orrs r3, r2 800321c: b2da uxtb r2, r3 800321e: 1d3b adds r3, r7, #4 8003220: 705a strb r2, [r3, #1] } lcd_buff[2]=LED_Tab[dis_buff.d_num[2]]; 8003222: 4b32 ldr r3, [pc, #200] ; (80032ec ) 8003224: 789b ldrb r3, [r3, #2] 8003226: 001a movs r2, r3 8003228: 4b31 ldr r3, [pc, #196] ; (80032f0 ) 800322a: 5c9a ldrb r2, [r3, r2] 800322c: 1d3b adds r3, r7, #4 800322e: 709a strb r2, [r3, #2] if(dis_buff.dot3==1) 8003230: 4b2e ldr r3, [pc, #184] ; (80032ec ) 8003232: 7a9b ldrb r3, [r3, #10] 8003234: 2b01 cmp r3, #1 8003236: d107 bne.n 8003248 { lcd_buff[2]|=0x80; 8003238: 1d3b adds r3, r7, #4 800323a: 789b ldrb r3, [r3, #2] 800323c: 2280 movs r2, #128 ; 0x80 800323e: 4252 negs r2, r2 8003240: 4313 orrs r3, r2 8003242: b2da uxtb r2, r3 8003244: 1d3b adds r3, r7, #4 8003246: 709a strb r2, [r3, #2] } lcd_buff[3]=LED_Tab[dis_buff.d_num[3]]; 8003248: 4b28 ldr r3, [pc, #160] ; (80032ec ) 800324a: 78db ldrb r3, [r3, #3] 800324c: 001a movs r2, r3 800324e: 4b28 ldr r3, [pc, #160] ; (80032f0 ) 8003250: 5c9a ldrb r2, [r3, r2] 8003252: 1d3b adds r3, r7, #4 8003254: 70da strb r2, [r3, #3] if(dis_buff.dot4==1) 8003256: 4b25 ldr r3, [pc, #148] ; (80032ec ) 8003258: 7adb ldrb r3, [r3, #11] 800325a: 2b01 cmp r3, #1 800325c: d107 bne.n 800326e { lcd_buff[3]|=0x80; 800325e: 1d3b adds r3, r7, #4 8003260: 78db ldrb r3, [r3, #3] 8003262: 2280 movs r2, #128 ; 0x80 8003264: 4252 negs r2, r2 8003266: 4313 orrs r3, r2 8003268: b2da uxtb r2, r3 800326a: 1d3b adds r3, r7, #4 800326c: 70da strb r2, [r3, #3] } send_buff[0]=lcd_buff[0]>>4; 800326e: 1d3b adds r3, r7, #4 8003270: 781b ldrb r3, [r3, #0] 8003272: 091b lsrs r3, r3, #4 8003274: b2da uxtb r2, r3 8003276: 2108 movs r1, #8 8003278: 187b adds r3, r7, r1 800327a: 701a strb r2, [r3, #0] send_buff[1]=lcd_buff[0]&0x0f; 800327c: 1d3b adds r3, r7, #4 800327e: 781b ldrb r3, [r3, #0] 8003280: 220f movs r2, #15 8003282: 4013 ands r3, r2 8003284: b2da uxtb r2, r3 8003286: 187b adds r3, r7, r1 8003288: 705a strb r2, [r3, #1] send_buff[2]=lcd_buff[1]>>4; 800328a: 1d3b adds r3, r7, #4 800328c: 785b ldrb r3, [r3, #1] 800328e: 091b lsrs r3, r3, #4 8003290: b2da uxtb r2, r3 8003292: 187b adds r3, r7, r1 8003294: 709a strb r2, [r3, #2] send_buff[3]=lcd_buff[1]&0x0f; 8003296: 1d3b adds r3, r7, #4 8003298: 785b ldrb r3, [r3, #1] 800329a: 220f movs r2, #15 800329c: 4013 ands r3, r2 800329e: b2da uxtb r2, r3 80032a0: 187b adds r3, r7, r1 80032a2: 70da strb r2, [r3, #3] send_buff[4]=lcd_buff[2]>>4; 80032a4: 1d3b adds r3, r7, #4 80032a6: 789b ldrb r3, [r3, #2] 80032a8: 091b lsrs r3, r3, #4 80032aa: b2da uxtb r2, r3 80032ac: 187b adds r3, r7, r1 80032ae: 711a strb r2, [r3, #4] send_buff[5]=lcd_buff[2]&0x0f; 80032b0: 1d3b adds r3, r7, #4 80032b2: 789b ldrb r3, [r3, #2] 80032b4: 220f movs r2, #15 80032b6: 4013 ands r3, r2 80032b8: b2da uxtb r2, r3 80032ba: 187b adds r3, r7, r1 80032bc: 715a strb r2, [r3, #5] send_buff[6]=lcd_buff[3]>>4; 80032be: 1d3b adds r3, r7, #4 80032c0: 78db ldrb r3, [r3, #3] 80032c2: 091b lsrs r3, r3, #4 80032c4: b2da uxtb r2, r3 80032c6: 187b adds r3, r7, r1 80032c8: 719a strb r2, [r3, #6] send_buff[7]=lcd_buff[3]&0x0f; 80032ca: 1d3b adds r3, r7, #4 80032cc: 78db ldrb r3, [r3, #3] 80032ce: 220f movs r2, #15 80032d0: 4013 ands r3, r2 80032d2: b2da uxtb r2, r3 80032d4: 187b adds r3, r7, r1 80032d6: 71da strb r2, [r3, #7] WritenDataHT1621(0,send_buff,8); 80032d8: 187b adds r3, r7, r1 80032da: 2208 movs r2, #8 80032dc: 0019 movs r1, r3 80032de: 2000 movs r0, #0 80032e0: f7ff fb73 bl 80029ca } 80032e4: 46c0 nop ; (mov r8, r8) 80032e6: 46bd mov sp, r7 80032e8: b004 add sp, #16 80032ea: bd80 pop {r7, pc} 80032ec: 20000038 .word 0x20000038 80032f0: 08003e48 .word 0x08003e48 080032f4 : void my_code() { 80032f4: b580 push {r7, lr} 80032f6: b086 sub sp, #24 80032f8: af00 add r7, sp, #0 uint32_t runtime=0,move=0; 80032fa: 2300 movs r3, #0 80032fc: 617b str r3, [r7, #20] 80032fe: 2300 movs r3, #0 8003300: 613b str r3, [r7, #16] uint8_t mode=6,overload_mode=0; 8003302: 230f movs r3, #15 8003304: 18fb adds r3, r7, r3 8003306: 2206 movs r2, #6 8003308: 701a strb r2, [r3, #0] 800330a: 230e movs r3, #14 800330c: 18fb adds r3, r7, r3 800330e: 2200 movs r2, #0 8003310: 701a strb r2, [r3, #0] uint16_t overload_times=0; 8003312: 230c movs r3, #12 8003314: 18fb adds r3, r7, r3 8003316: 2200 movs r2, #0 8003318: 801a strh r2, [r3, #0] long countdown=1000; 800331a: 23fa movs r3, #250 ; 0xfa 800331c: 009b lsls r3, r3, #2 800331e: 60bb str r3, [r7, #8] long countdown_set=15000; 8003320: 4bce ldr r3, [pc, #824] ; (800365c ) 8003322: 607b str r3, [r7, #4] HT1621_Init(); 8003324: f7ff fc12 bl 8002b4c r480_init(); 8003328: f000 fc6c bl 8003c04 config.begin=18; 800332c: 4bcc ldr r3, [pc, #816] ; (8003660 ) 800332e: 2212 movs r2, #18 8003330: 701a strb r2, [r3, #0] AT24CXX_Write(8,(char *)&config,sizeof(config_setting)); 8003332: 4bcb ldr r3, [pc, #812] ; (8003660 ) 8003334: 2208 movs r2, #8 8003336: 0019 movs r1, r3 8003338: 2008 movs r0, #8 800333a: f7ff fa60 bl 80027fe config.begin=1; 800333e: 4bc8 ldr r3, [pc, #800] ; (8003660 ) 8003340: 2201 movs r2, #1 8003342: 701a strb r2, [r3, #0] AT24CXX_Read(8,(char *)&config,sizeof(config_setting)); 8003344: 4bc6 ldr r3, [pc, #792] ; (8003660 ) 8003346: 2208 movs r2, #8 8003348: 0019 movs r1, r3 800334a: 2008 movs r0, #8 800334c: f7ff fa30 bl 80027b0 while(1) { //get ADC for(char a=0;a<2;a++) 8003350: 1cfb adds r3, r7, #3 8003352: 2200 movs r2, #0 8003354: 701a strb r2, [r3, #0] 8003356: e025 b.n 80033a4 { HAL_ADC_Start(&hadc); 8003358: 4bc2 ldr r3, [pc, #776] ; (8003664 ) 800335a: 0018 movs r0, r3 800335c: f7fd fc9e bl 8000c9c while(HAL_ADC_PollForConversion(&hadc,0xffff)!=HAL_OK); 8003360: 46c0 nop ; (mov r8, r8) 8003362: 4ac1 ldr r2, [pc, #772] ; (8003668 ) 8003364: 4bbf ldr r3, [pc, #764] ; (8003664 ) 8003366: 0011 movs r1, r2 8003368: 0018 movs r0, r3 800336a: f7fd fd2b bl 8000dc4 800336e: 1e03 subs r3, r0, #0 8003370: d1f7 bne.n 8003362 ADCC.adc_filtering[a]+=HAL_ADC_GetValue(&hadc); 8003372: 4bbc ldr r3, [pc, #752] ; (8003664 ) 8003374: 0018 movs r0, r3 8003376: f7fd fdbd bl 8000ef4 800337a: 0001 movs r1, r0 800337c: 1cfb adds r3, r7, #3 800337e: 781b ldrb r3, [r3, #0] 8003380: 4aba ldr r2, [pc, #744] ; (800366c ) 8003382: 009b lsls r3, r3, #2 8003384: 18d3 adds r3, r2, r3 8003386: 3304 adds r3, #4 8003388: 681a ldr r2, [r3, #0] 800338a: 1cfb adds r3, r7, #3 800338c: 781b ldrb r3, [r3, #0] 800338e: 188a adds r2, r1, r2 8003390: 49b6 ldr r1, [pc, #728] ; (800366c ) 8003392: 009b lsls r3, r3, #2 8003394: 18cb adds r3, r1, r3 8003396: 3304 adds r3, #4 8003398: 601a str r2, [r3, #0] for(char a=0;a<2;a++) 800339a: 1cfb adds r3, r7, #3 800339c: 781a ldrb r2, [r3, #0] 800339e: 1cfb adds r3, r7, #3 80033a0: 3201 adds r2, #1 80033a2: 701a strb r2, [r3, #0] 80033a4: 1cfb adds r3, r7, #3 80033a6: 781b ldrb r3, [r3, #0] 80033a8: 2b01 cmp r3, #1 80033aa: d9d5 bls.n 8003358 } HAL_ADC_Stop(&hadc); 80033ac: 4bad ldr r3, [pc, #692] ; (8003664 ) 80033ae: 0018 movs r0, r3 80033b0: f7fd fcc8 bl 8000d44 ADCC.filtering_times+=1; 80033b4: 4bad ldr r3, [pc, #692] ; (800366c ) 80033b6: 681b ldr r3, [r3, #0] 80033b8: 1c5a adds r2, r3, #1 80033ba: 4bac ldr r3, [pc, #688] ; (800366c ) 80033bc: 601a str r2, [r3, #0] if(ADCC.filtering_times==set_filtering_times) 80033be: 4bab ldr r3, [pc, #684] ; (800366c ) 80033c0: 681b ldr r3, [r3, #0] 80033c2: 2b32 cmp r3, #50 ; 0x32 80033c4: d11c bne.n 8003400 { ADCC.filtering_times=0; 80033c6: 4ba9 ldr r3, [pc, #676] ; (800366c ) 80033c8: 2200 movs r2, #0 80033ca: 601a str r2, [r3, #0] ADCC.adc_value[0]=ADCC.adc_filtering[0]/set_filtering_times; 80033cc: 4ba7 ldr r3, [pc, #668] ; (800366c ) 80033ce: 685b ldr r3, [r3, #4] 80033d0: 2132 movs r1, #50 ; 0x32 80033d2: 0018 movs r0, r3 80033d4: f7fc fe98 bl 8000108 <__udivsi3> 80033d8: 0003 movs r3, r0 80033da: 001a movs r2, r3 80033dc: 4ba3 ldr r3, [pc, #652] ; (800366c ) 80033de: 60da str r2, [r3, #12] ADCC.adc_filtering[0]=0; 80033e0: 4ba2 ldr r3, [pc, #648] ; (800366c ) 80033e2: 2200 movs r2, #0 80033e4: 605a str r2, [r3, #4] ADCC.adc_value[1]=ADCC.adc_filtering[1]/set_filtering_times; 80033e6: 4ba1 ldr r3, [pc, #644] ; (800366c ) 80033e8: 689b ldr r3, [r3, #8] 80033ea: 2132 movs r1, #50 ; 0x32 80033ec: 0018 movs r0, r3 80033ee: f7fc fe8b bl 8000108 <__udivsi3> 80033f2: 0003 movs r3, r0 80033f4: 001a movs r2, r3 80033f6: 4b9d ldr r3, [pc, #628] ; (800366c ) 80033f8: 611a str r2, [r3, #16] ADCC.adc_filtering[1]=0; 80033fa: 4b9c ldr r3, [pc, #624] ; (800366c ) 80033fc: 2200 movs r2, #0 80033fe: 609a str r2, [r3, #8] } switch(mode) 8003400: 230f movs r3, #15 8003402: 18fb adds r3, r7, r3 8003404: 781b ldrb r3, [r3, #0] 8003406: 2b06 cmp r3, #6 8003408: d900 bls.n 800340c 800340a: e382 b.n 8003b12 800340c: 009a lsls r2, r3, #2 800340e: 4b98 ldr r3, [pc, #608] ; (8003670 ) 8003410: 18d3 adds r3, r2, r3 8003412: 681b ldr r3, [r3, #0] 8003414: 469f mov pc, r3 { case 0: //Startup if(HAL_GetTick()>move) 8003416: f7fd faf7 bl 8000a08 800341a: 0002 movs r2, r0 800341c: 693b ldr r3, [r7, #16] 800341e: 4293 cmp r3, r2 8003420: d300 bcc.n 8003424 8003422: e36d b.n 8003b00 { move=HAL_GetTick()+100; 8003424: f7fd faf0 bl 8000a08 8003428: 0003 movs r3, r0 800342a: 3364 adds r3, #100 ; 0x64 800342c: 613b str r3, [r7, #16] countdown-=100; 800342e: 68bb ldr r3, [r7, #8] 8003430: 3b64 subs r3, #100 ; 0x64 8003432: 60bb str r3, [r7, #8] if(countdown<0) 8003434: 68bb ldr r3, [r7, #8] 8003436: 2b00 cmp r3, #0 8003438: da03 bge.n 8003442 { mode=1; 800343a: 230f movs r3, #15 800343c: 18fb adds r3, r7, r3 800343e: 2201 movs r2, #1 8003440: 701a strb r2, [r3, #0] } dis_buff.d_num[0]=((countdown/100)%10); 8003442: 68bb ldr r3, [r7, #8] 8003444: 2164 movs r1, #100 ; 0x64 8003446: 0018 movs r0, r3 8003448: f7fc fee8 bl 800021c <__divsi3> 800344c: 0003 movs r3, r0 800344e: 210a movs r1, #10 8003450: 0018 movs r0, r3 8003452: f7fc ffc9 bl 80003e8 <__aeabi_idivmod> 8003456: 000b movs r3, r1 8003458: b2da uxtb r2, r3 800345a: 4b86 ldr r3, [pc, #536] ; (8003674 ) 800345c: 701a strb r2, [r3, #0] dis_buff.d_num[1]=((countdown/100)%10); 800345e: 68bb ldr r3, [r7, #8] 8003460: 2164 movs r1, #100 ; 0x64 8003462: 0018 movs r0, r3 8003464: f7fc feda bl 800021c <__divsi3> 8003468: 0003 movs r3, r0 800346a: 210a movs r1, #10 800346c: 0018 movs r0, r3 800346e: f7fc ffbb bl 80003e8 <__aeabi_idivmod> 8003472: 000b movs r3, r1 8003474: b2da uxtb r2, r3 8003476: 4b7f ldr r3, [pc, #508] ; (8003674 ) 8003478: 705a strb r2, [r3, #1] dis_buff.d_num[2]=((countdown/100)%10); 800347a: 68bb ldr r3, [r7, #8] 800347c: 2164 movs r1, #100 ; 0x64 800347e: 0018 movs r0, r3 8003480: f7fc fecc bl 800021c <__divsi3> 8003484: 0003 movs r3, r0 8003486: 210a movs r1, #10 8003488: 0018 movs r0, r3 800348a: f7fc ffad bl 80003e8 <__aeabi_idivmod> 800348e: 000b movs r3, r1 8003490: b2da uxtb r2, r3 8003492: 4b78 ldr r3, [pc, #480] ; (8003674 ) 8003494: 709a strb r2, [r3, #2] dis_buff.d_num[3]=((countdown/100)%10); 8003496: 68bb ldr r3, [r7, #8] 8003498: 2164 movs r1, #100 ; 0x64 800349a: 0018 movs r0, r3 800349c: f7fc febe bl 800021c <__divsi3> 80034a0: 0003 movs r3, r0 80034a2: 210a movs r1, #10 80034a4: 0018 movs r0, r3 80034a6: f7fc ff9f bl 80003e8 <__aeabi_idivmod> 80034aa: 000b movs r3, r1 80034ac: b2da uxtb r2, r3 80034ae: 4b71 ldr r3, [pc, #452] ; (8003674 ) 80034b0: 70da strb r2, [r3, #3] dis_buff.dot1=countdown>>3; 80034b2: 68bb ldr r3, [r7, #8] 80034b4: 10db asrs r3, r3, #3 80034b6: b2da uxtb r2, r3 80034b8: 4b6e ldr r3, [pc, #440] ; (8003674 ) 80034ba: 721a strb r2, [r3, #8] dis_buff.dot2=countdown>>4; 80034bc: 68bb ldr r3, [r7, #8] 80034be: 111b asrs r3, r3, #4 80034c0: b2da uxtb r2, r3 80034c2: 4b6c ldr r3, [pc, #432] ; (8003674 ) 80034c4: 725a strb r2, [r3, #9] dis_buff.dot3=countdown>>5; 80034c6: 68bb ldr r3, [r7, #8] 80034c8: 115b asrs r3, r3, #5 80034ca: b2da uxtb r2, r3 80034cc: 4b69 ldr r3, [pc, #420] ; (8003674 ) 80034ce: 729a strb r2, [r3, #10] dis_buff.dot4=countdown>>6; 80034d0: 68bb ldr r3, [r7, #8] 80034d2: 119b asrs r3, r3, #6 80034d4: b2da uxtb r2, r3 80034d6: 4b67 ldr r3, [pc, #412] ; (8003674 ) 80034d8: 72da strb r2, [r3, #11] } break; 80034da: e311 b.n 8003b00 case 1: //standby moto.moto1a=0; 80034dc: 4b66 ldr r3, [pc, #408] ; (8003678 ) 80034de: 2200 movs r2, #0 80034e0: 721a strb r2, [r3, #8] moto.moto1b=0; 80034e2: 4b65 ldr r3, [pc, #404] ; (8003678 ) 80034e4: 2200 movs r2, #0 80034e6: 725a strb r2, [r3, #9] moto.moto2a=0; 80034e8: 4b63 ldr r3, [pc, #396] ; (8003678 ) 80034ea: 2200 movs r2, #0 80034ec: 729a strb r2, [r3, #10] moto.moto2b=0; 80034ee: 4b62 ldr r3, [pc, #392] ; (8003678 ) 80034f0: 2200 movs r2, #0 80034f2: 72da strb r2, [r3, #11] dis_buff.d_num[0]=16; 80034f4: 4b5f ldr r3, [pc, #380] ; (8003674 ) 80034f6: 2210 movs r2, #16 80034f8: 701a strb r2, [r3, #0] dis_buff.d_num[1]=16; 80034fa: 4b5e ldr r3, [pc, #376] ; (8003674 ) 80034fc: 2210 movs r2, #16 80034fe: 705a strb r2, [r3, #1] dis_buff.d_num[2]=16; 8003500: 4b5c ldr r3, [pc, #368] ; (8003674 ) 8003502: 2210 movs r2, #16 8003504: 709a strb r2, [r3, #2] dis_buff.d_num[3]=16; 8003506: 4b5b ldr r3, [pc, #364] ; (8003674 ) 8003508: 2210 movs r2, #16 800350a: 70da strb r2, [r3, #3] dis_buff.dot1=0; 800350c: 4b59 ldr r3, [pc, #356] ; (8003674 ) 800350e: 2200 movs r2, #0 8003510: 721a strb r2, [r3, #8] dis_buff.dot2=0; 8003512: 4b58 ldr r3, [pc, #352] ; (8003674 ) 8003514: 2200 movs r2, #0 8003516: 725a strb r2, [r3, #9] dis_buff.dot3=0; 8003518: 4b56 ldr r3, [pc, #344] ; (8003674 ) 800351a: 2200 movs r2, #0 800351c: 729a strb r2, [r3, #10] if(HAL_GetTick()>runtime) 800351e: f7fd fa73 bl 8000a08 8003522: 0002 movs r2, r0 8003524: 697b ldr r3, [r7, #20] 8003526: 4293 cmp r3, r2 8003528: d216 bcs.n 8003558 { runtime+=1000; 800352a: 697b ldr r3, [r7, #20] 800352c: 22fa movs r2, #250 ; 0xfa 800352e: 0092 lsls r2, r2, #2 8003530: 4694 mov ip, r2 8003532: 4463 add r3, ip 8003534: 617b str r3, [r7, #20] if(dis_buff.led_run==1) 8003536: 4b4f ldr r3, [pc, #316] ; (8003674 ) 8003538: 7b1b ldrb r3, [r3, #12] 800353a: 2b01 cmp r3, #1 800353c: d106 bne.n 800354c { dis_buff.led_run=0; 800353e: 4b4d ldr r3, [pc, #308] ; (8003674 ) 8003540: 2200 movs r2, #0 8003542: 731a strb r2, [r3, #12] dis_buff.dot4=1; 8003544: 4b4b ldr r3, [pc, #300] ; (8003674 ) 8003546: 2201 movs r2, #1 8003548: 72da strb r2, [r3, #11] 800354a: e005 b.n 8003558 }else { dis_buff.led_run=1; 800354c: 4b49 ldr r3, [pc, #292] ; (8003674 ) 800354e: 2201 movs r2, #1 8003550: 731a strb r2, [r3, #12] dis_buff.dot4=0; 8003552: 4b48 ldr r3, [pc, #288] ; (8003674 ) 8003554: 2200 movs r2, #0 8003556: 72da strb r2, [r3, #11] } } overload_times=0; 8003558: 230c movs r3, #12 800355a: 18fb adds r3, r7, r3 800355c: 2200 movs r2, #0 800355e: 801a strh r2, [r3, #0] if(key2.code!=0) 8003560: 4b46 ldr r3, [pc, #280] ; (800367c ) 8003562: 681b ldr r3, [r3, #0] 8003564: 2b00 cmp r3, #0 8003566: d005 beq.n 8003574 { mode=2; 8003568: 230f movs r3, #15 800356a: 18fb adds r3, r7, r3 800356c: 2202 movs r2, #2 800356e: 701a strb r2, [r3, #0] countdown=countdown_set; 8003570: 687b ldr r3, [r7, #4] 8003572: 60bb str r3, [r7, #8] } if(key3.code!=0) 8003574: 4b42 ldr r3, [pc, #264] ; (8003680 ) 8003576: 681b ldr r3, [r3, #0] 8003578: 2b00 cmp r3, #0 800357a: d005 beq.n 8003588 { mode=3; 800357c: 230f movs r3, #15 800357e: 18fb adds r3, r7, r3 8003580: 2203 movs r2, #3 8003582: 701a strb r2, [r3, #0] countdown=countdown_set; 8003584: 687b ldr r3, [r7, #4] 8003586: 60bb str r3, [r7, #8] } if(key1.code!=0) 8003588: 4b3e ldr r3, [pc, #248] ; (8003684 ) 800358a: 681b ldr r3, [r3, #0] 800358c: 2b00 cmp r3, #0 800358e: d100 bne.n 8003592 8003590: e2b8 b.n 8003b04 { mode=4; 8003592: 230f movs r3, #15 8003594: 18fb adds r3, r7, r3 8003596: 2204 movs r2, #4 8003598: 701a strb r2, [r3, #0] countdown=10000; 800359a: 4b3b ldr r3, [pc, #236] ; (8003688 ) 800359c: 60bb str r3, [r7, #8] } break; 800359e: e2b1 b.n 8003b04 case 2: moto.moto1a=10; 80035a0: 4b35 ldr r3, [pc, #212] ; (8003678 ) 80035a2: 220a movs r2, #10 80035a4: 721a strb r2, [r3, #8] moto.moto1b=0; 80035a6: 4b34 ldr r3, [pc, #208] ; (8003678 ) 80035a8: 2200 movs r2, #0 80035aa: 725a strb r2, [r3, #9] moto.moto2a=10; 80035ac: 4b32 ldr r3, [pc, #200] ; (8003678 ) 80035ae: 220a movs r2, #10 80035b0: 729a strb r2, [r3, #10] moto.moto2b=0; 80035b2: 4b31 ldr r3, [pc, #196] ; (8003678 ) 80035b4: 2200 movs r2, #0 80035b6: 72da strb r2, [r3, #11] if(HAL_GetTick()>move) 80035b8: f7fd fa26 bl 8000a08 80035bc: 0002 movs r2, r0 80035be: 693b ldr r3, [r7, #16] 80035c0: 4293 cmp r3, r2 80035c2: d219 bcs.n 80035f8 { move=HAL_GetTick()+100; 80035c4: f7fd fa20 bl 8000a08 80035c8: 0003 movs r3, r0 80035ca: 3364 adds r3, #100 ; 0x64 80035cc: 613b str r3, [r7, #16] if(dis_buff.led_run==1) 80035ce: 4b29 ldr r3, [pc, #164] ; (8003674 ) 80035d0: 7b1b ldrb r3, [r3, #12] 80035d2: 2b01 cmp r3, #1 80035d4: d103 bne.n 80035de { dis_buff.led_run=0; 80035d6: 4b27 ldr r3, [pc, #156] ; (8003674 ) 80035d8: 2200 movs r2, #0 80035da: 731a strb r2, [r3, #12] 80035dc: e002 b.n 80035e4 }else { dis_buff.led_run=1; 80035de: 4b25 ldr r3, [pc, #148] ; (8003674 ) 80035e0: 2201 movs r2, #1 80035e2: 731a strb r2, [r3, #12] } countdown-=100; 80035e4: 68bb ldr r3, [r7, #8] 80035e6: 3b64 subs r3, #100 ; 0x64 80035e8: 60bb str r3, [r7, #8] if(countdown<0) 80035ea: 68bb ldr r3, [r7, #8] 80035ec: 2b00 cmp r3, #0 80035ee: da03 bge.n 80035f8 { mode=1; 80035f0: 230f movs r3, #15 80035f2: 18fb adds r3, r7, r3 80035f4: 2201 movs r2, #1 80035f6: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 80035f8: 68bb ldr r3, [r7, #8] 80035fa: 2164 movs r1, #100 ; 0x64 80035fc: 0018 movs r0, r3 80035fe: f7fc fe0d bl 800021c <__divsi3> 8003602: 0003 movs r3, r0 8003604: 210a movs r1, #10 8003606: 0018 movs r0, r3 8003608: f7fc feee bl 80003e8 <__aeabi_idivmod> 800360c: 000b movs r3, r1 800360e: b2da uxtb r2, r3 8003610: 4b18 ldr r3, [pc, #96] ; (8003674 ) 8003612: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 8003614: 68bb ldr r3, [r7, #8] 8003616: 22fa movs r2, #250 ; 0xfa 8003618: 0091 lsls r1, r2, #2 800361a: 0018 movs r0, r3 800361c: f7fc fdfe bl 800021c <__divsi3> 8003620: 0003 movs r3, r0 8003622: 210a movs r1, #10 8003624: 0018 movs r0, r3 8003626: f7fc fedf bl 80003e8 <__aeabi_idivmod> 800362a: 000b movs r3, r1 800362c: b2da uxtb r2, r3 800362e: 4b11 ldr r3, [pc, #68] ; (8003674 ) 8003630: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 8003632: 68bb ldr r3, [r7, #8] 8003634: 4914 ldr r1, [pc, #80] ; (8003688 ) 8003636: 0018 movs r0, r3 8003638: f7fc fdf0 bl 800021c <__divsi3> 800363c: 0003 movs r3, r0 800363e: 210a movs r1, #10 8003640: 0018 movs r0, r3 8003642: f7fc fed1 bl 80003e8 <__aeabi_idivmod> 8003646: 000b movs r3, r1 8003648: b2da uxtb r2, r3 800364a: 4b0a ldr r3, [pc, #40] ; (8003674 ) 800364c: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 800364e: 4b09 ldr r3, [pc, #36] ; (8003674 ) 8003650: 785b ldrb r3, [r3, #1] 8003652: 2b00 cmp r3, #0 8003654: d01a beq.n 800368c 8003656: 4b07 ldr r3, [pc, #28] ; (8003674 ) 8003658: 785a ldrb r2, [r3, #1] 800365a: e018 b.n 800368e 800365c: 00003a98 .word 0x00003a98 8003660: 20000154 .word 0x20000154 8003664: 20000094 .word 0x20000094 8003668: 0000ffff .word 0x0000ffff 800366c: 20000120 .word 0x20000120 8003670: 08003e5c .word 0x08003e5c 8003674: 20000038 .word 0x20000038 8003678: 20000144 .word 0x20000144 800367c: 20000134 .word 0x20000134 8003680: 20000110 .word 0x20000110 8003684: 200000f0 .word 0x200000f0 8003688: 00002710 .word 0x00002710 800368c: 2210 movs r2, #16 800368e: 4bce ldr r3, [pc, #824] ; (80039c8 ) 8003690: 705a strb r2, [r3, #1] dis_buff.dot4=1; 8003692: 4bcd ldr r3, [pc, #820] ; (80039c8 ) 8003694: 2201 movs r2, #1 8003696: 72da strb r2, [r3, #11] if(key3.code!=0) 8003698: 4bcc ldr r3, [pc, #816] ; (80039cc ) 800369a: 681b ldr r3, [r3, #0] 800369c: 2b00 cmp r3, #0 800369e: d007 beq.n 80036b0 { mode=3; 80036a0: 230f movs r3, #15 80036a2: 18fb adds r3, r7, r3 80036a4: 2203 movs r2, #3 80036a6: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 80036a8: 687a ldr r2, [r7, #4] 80036aa: 68bb ldr r3, [r7, #8] 80036ac: 1ad3 subs r3, r2, r3 80036ae: 60bb str r3, [r7, #8] } if(key4.code!=0) 80036b0: 4bc7 ldr r3, [pc, #796] ; (80039d0 ) 80036b2: 681b ldr r3, [r3, #0] 80036b4: 2b00 cmp r3, #0 80036b6: d003 beq.n 80036c0 { mode=1; 80036b8: 230f movs r3, #15 80036ba: 18fb adds r3, r7, r3 80036bc: 2201 movs r2, #1 80036be: 701a strb r2, [r3, #0] } if(overload.code!=0) 80036c0: 4bc4 ldr r3, [pc, #784] ; (80039d4 ) 80036c2: 681b ldr r3, [r3, #0] 80036c4: 2b00 cmp r3, #0 80036c6: d005 beq.n 80036d4 { overload_times+=1; 80036c8: 220c movs r2, #12 80036ca: 18bb adds r3, r7, r2 80036cc: 18ba adds r2, r7, r2 80036ce: 8812 ldrh r2, [r2, #0] 80036d0: 3201 adds r2, #1 80036d2: 801a strh r2, [r3, #0] } if(overload_times>2) 80036d4: 230c movs r3, #12 80036d6: 18fb adds r3, r7, r3 80036d8: 881b ldrh r3, [r3, #0] 80036da: 2b02 cmp r3, #2 80036dc: d800 bhi.n 80036e0 80036de: e213 b.n 8003b08 { overload_mode=2; 80036e0: 230e movs r3, #14 80036e2: 18fb adds r3, r7, r3 80036e4: 2202 movs r2, #2 80036e6: 701a strb r2, [r3, #0] mode=5; 80036e8: 230f movs r3, #15 80036ea: 18fb adds r3, r7, r3 80036ec: 2205 movs r2, #5 80036ee: 701a strb r2, [r3, #0] } break; 80036f0: e20a b.n 8003b08 case 3: moto.moto1a=0; 80036f2: 4bb9 ldr r3, [pc, #740] ; (80039d8 ) 80036f4: 2200 movs r2, #0 80036f6: 721a strb r2, [r3, #8] moto.moto1b=10; 80036f8: 4bb7 ldr r3, [pc, #732] ; (80039d8 ) 80036fa: 220a movs r2, #10 80036fc: 725a strb r2, [r3, #9] moto.moto2a=0; 80036fe: 4bb6 ldr r3, [pc, #728] ; (80039d8 ) 8003700: 2200 movs r2, #0 8003702: 729a strb r2, [r3, #10] moto.moto2b=10; 8003704: 4bb4 ldr r3, [pc, #720] ; (80039d8 ) 8003706: 220a movs r2, #10 8003708: 72da strb r2, [r3, #11] if(HAL_GetTick()>move) 800370a: f7fd f97d bl 8000a08 800370e: 0002 movs r2, r0 8003710: 693b ldr r3, [r7, #16] 8003712: 4293 cmp r3, r2 8003714: d219 bcs.n 800374a { move=HAL_GetTick()+100; 8003716: f7fd f977 bl 8000a08 800371a: 0003 movs r3, r0 800371c: 3364 adds r3, #100 ; 0x64 800371e: 613b str r3, [r7, #16] if(dis_buff.led_run==1) 8003720: 4ba9 ldr r3, [pc, #676] ; (80039c8 ) 8003722: 7b1b ldrb r3, [r3, #12] 8003724: 2b01 cmp r3, #1 8003726: d103 bne.n 8003730 { dis_buff.led_run=0; 8003728: 4ba7 ldr r3, [pc, #668] ; (80039c8 ) 800372a: 2200 movs r2, #0 800372c: 731a strb r2, [r3, #12] 800372e: e002 b.n 8003736 }else { dis_buff.led_run=1; 8003730: 4ba5 ldr r3, [pc, #660] ; (80039c8 ) 8003732: 2201 movs r2, #1 8003734: 731a strb r2, [r3, #12] } countdown-=100; 8003736: 68bb ldr r3, [r7, #8] 8003738: 3b64 subs r3, #100 ; 0x64 800373a: 60bb str r3, [r7, #8] if(countdown<0) 800373c: 68bb ldr r3, [r7, #8] 800373e: 2b00 cmp r3, #0 8003740: da03 bge.n 800374a { mode=1; 8003742: 230f movs r3, #15 8003744: 18fb adds r3, r7, r3 8003746: 2201 movs r2, #1 8003748: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 800374a: 68bb ldr r3, [r7, #8] 800374c: 2164 movs r1, #100 ; 0x64 800374e: 0018 movs r0, r3 8003750: f7fc fd64 bl 800021c <__divsi3> 8003754: 0003 movs r3, r0 8003756: 210a movs r1, #10 8003758: 0018 movs r0, r3 800375a: f7fc fe45 bl 80003e8 <__aeabi_idivmod> 800375e: 000b movs r3, r1 8003760: b2da uxtb r2, r3 8003762: 4b99 ldr r3, [pc, #612] ; (80039c8 ) 8003764: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 8003766: 68bb ldr r3, [r7, #8] 8003768: 22fa movs r2, #250 ; 0xfa 800376a: 0091 lsls r1, r2, #2 800376c: 0018 movs r0, r3 800376e: f7fc fd55 bl 800021c <__divsi3> 8003772: 0003 movs r3, r0 8003774: 210a movs r1, #10 8003776: 0018 movs r0, r3 8003778: f7fc fe36 bl 80003e8 <__aeabi_idivmod> 800377c: 000b movs r3, r1 800377e: b2da uxtb r2, r3 8003780: 4b91 ldr r3, [pc, #580] ; (80039c8 ) 8003782: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 8003784: 68bb ldr r3, [r7, #8] 8003786: 4995 ldr r1, [pc, #596] ; (80039dc ) 8003788: 0018 movs r0, r3 800378a: f7fc fd47 bl 800021c <__divsi3> 800378e: 0003 movs r3, r0 8003790: 210a movs r1, #10 8003792: 0018 movs r0, r3 8003794: f7fc fe28 bl 80003e8 <__aeabi_idivmod> 8003798: 000b movs r3, r1 800379a: b2da uxtb r2, r3 800379c: 4b8a ldr r3, [pc, #552] ; (80039c8 ) 800379e: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 80037a0: 4b89 ldr r3, [pc, #548] ; (80039c8 ) 80037a2: 785b ldrb r3, [r3, #1] 80037a4: 2b00 cmp r3, #0 80037a6: d002 beq.n 80037ae 80037a8: 4b87 ldr r3, [pc, #540] ; (80039c8 ) 80037aa: 785a ldrb r2, [r3, #1] 80037ac: e000 b.n 80037b0 80037ae: 2210 movs r2, #16 80037b0: 4b85 ldr r3, [pc, #532] ; (80039c8 ) 80037b2: 705a strb r2, [r3, #1] dis_buff.dot4=1; 80037b4: 4b84 ldr r3, [pc, #528] ; (80039c8 ) 80037b6: 2201 movs r2, #1 80037b8: 72da strb r2, [r3, #11] if(key2.code!=0) 80037ba: 4b89 ldr r3, [pc, #548] ; (80039e0 ) 80037bc: 681b ldr r3, [r3, #0] 80037be: 2b00 cmp r3, #0 80037c0: d007 beq.n 80037d2 { mode=2; 80037c2: 230f movs r3, #15 80037c4: 18fb adds r3, r7, r3 80037c6: 2202 movs r2, #2 80037c8: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 80037ca: 687a ldr r2, [r7, #4] 80037cc: 68bb ldr r3, [r7, #8] 80037ce: 1ad3 subs r3, r2, r3 80037d0: 60bb str r3, [r7, #8] } if(key4.code!=0) 80037d2: 4b7f ldr r3, [pc, #508] ; (80039d0 ) 80037d4: 681b ldr r3, [r3, #0] 80037d6: 2b00 cmp r3, #0 80037d8: d003 beq.n 80037e2 { mode=1; 80037da: 230f movs r3, #15 80037dc: 18fb adds r3, r7, r3 80037de: 2201 movs r2, #1 80037e0: 701a strb r2, [r3, #0] } if(overload.code!=0) 80037e2: 4b7c ldr r3, [pc, #496] ; (80039d4 ) 80037e4: 681b ldr r3, [r3, #0] 80037e6: 2b00 cmp r3, #0 80037e8: d005 beq.n 80037f6 { overload_times+=1; 80037ea: 220c movs r2, #12 80037ec: 18bb adds r3, r7, r2 80037ee: 18ba adds r2, r7, r2 80037f0: 8812 ldrh r2, [r2, #0] 80037f2: 3201 adds r2, #1 80037f4: 801a strh r2, [r3, #0] } if(overload_times>2) 80037f6: 230c movs r3, #12 80037f8: 18fb adds r3, r7, r3 80037fa: 881b ldrh r3, [r3, #0] 80037fc: 2b02 cmp r3, #2 80037fe: d800 bhi.n 8003802 8003800: e184 b.n 8003b0c { overload_mode=3; 8003802: 230e movs r3, #14 8003804: 18fb adds r3, r7, r3 8003806: 2203 movs r2, #3 8003808: 701a strb r2, [r3, #0] mode=5; 800380a: 230f movs r3, #15 800380c: 18fb adds r3, r7, r3 800380e: 2205 movs r2, #5 8003810: 701a strb r2, [r3, #0] } break; 8003812: e17b b.n 8003b0c case 4: //setting mode dis_buff.led_run=0; 8003814: 4b6c ldr r3, [pc, #432] ; (80039c8 ) 8003816: 2200 movs r2, #0 8003818: 731a strb r2, [r3, #12] if(HAL_GetTick()>move) 800381a: f7fd f8f5 bl 8000a08 800381e: 0002 movs r2, r0 8003820: 693b ldr r3, [r7, #16] 8003822: 4293 cmp r3, r2 8003824: d230 bcs.n 8003888 { move=HAL_GetTick()+100; 8003826: f7fd f8ef bl 8000a08 800382a: 0003 movs r3, r0 800382c: 3364 adds r3, #100 ; 0x64 800382e: 613b str r3, [r7, #16] if(dis_buff.dot4==1) 8003830: 4b65 ldr r3, [pc, #404] ; (80039c8 ) 8003832: 7adb ldrb r3, [r3, #11] 8003834: 2b01 cmp r3, #1 8003836: d103 bne.n 8003840 { dis_buff.dot4=0; 8003838: 4b63 ldr r3, [pc, #396] ; (80039c8 ) 800383a: 2200 movs r2, #0 800383c: 72da strb r2, [r3, #11] 800383e: e002 b.n 8003846 }else { dis_buff.dot4=1; 8003840: 4b61 ldr r3, [pc, #388] ; (80039c8 ) 8003842: 2201 movs r2, #1 8003844: 72da strb r2, [r3, #11] } countdown-=100; 8003846: 68bb ldr r3, [r7, #8] 8003848: 3b64 subs r3, #100 ; 0x64 800384a: 60bb str r3, [r7, #8] if(countdown<0) 800384c: 68bb ldr r3, [r7, #8] 800384e: 2b00 cmp r3, #0 8003850: da03 bge.n 800385a { mode=1; 8003852: 230f movs r3, #15 8003854: 18fb adds r3, r7, r3 8003856: 2201 movs r2, #1 8003858: 701a strb r2, [r3, #0] } if(key2.code<0){countdown_set+=1000;countdown=10000;} 800385a: 4b61 ldr r3, [pc, #388] ; (80039e0 ) 800385c: 681b ldr r3, [r3, #0] 800385e: 2b00 cmp r3, #0 8003860: da07 bge.n 8003872 8003862: 687b ldr r3, [r7, #4] 8003864: 22fa movs r2, #250 ; 0xfa 8003866: 0092 lsls r2, r2, #2 8003868: 4694 mov ip, r2 800386a: 4463 add r3, ip 800386c: 607b str r3, [r7, #4] 800386e: 4b5b ldr r3, [pc, #364] ; (80039dc ) 8003870: 60bb str r3, [r7, #8] if(key3.code<0){countdown_set-=1000;countdown=10000;} 8003872: 4b56 ldr r3, [pc, #344] ; (80039cc ) 8003874: 681b ldr r3, [r3, #0] 8003876: 2b00 cmp r3, #0 8003878: da06 bge.n 8003888 800387a: 687b ldr r3, [r7, #4] 800387c: 4a59 ldr r2, [pc, #356] ; (80039e4 ) 800387e: 4694 mov ip, r2 8003880: 4463 add r3, ip 8003882: 607b str r3, [r7, #4] 8003884: 4b55 ldr r3, [pc, #340] ; (80039dc ) 8003886: 60bb str r3, [r7, #8] } if(key2.code>0){countdown_set+=100;countdown=10000;} 8003888: 4b55 ldr r3, [pc, #340] ; (80039e0 ) 800388a: 681b ldr r3, [r3, #0] 800388c: 2b00 cmp r3, #0 800388e: dd04 ble.n 800389a 8003890: 687b ldr r3, [r7, #4] 8003892: 3364 adds r3, #100 ; 0x64 8003894: 607b str r3, [r7, #4] 8003896: 4b51 ldr r3, [pc, #324] ; (80039dc ) 8003898: 60bb str r3, [r7, #8] if(key3.code>0){countdown_set-=100;countdown=10000;} 800389a: 4b4c ldr r3, [pc, #304] ; (80039cc ) 800389c: 681b ldr r3, [r3, #0] 800389e: 2b00 cmp r3, #0 80038a0: dd04 ble.n 80038ac 80038a2: 687b ldr r3, [r7, #4] 80038a4: 3b64 subs r3, #100 ; 0x64 80038a6: 607b str r3, [r7, #4] 80038a8: 4b4c ldr r3, [pc, #304] ; (80039dc ) 80038aa: 60bb str r3, [r7, #8] if(countdown_set<100){countdown_set=100;} 80038ac: 687b ldr r3, [r7, #4] 80038ae: 2b63 cmp r3, #99 ; 0x63 80038b0: dc01 bgt.n 80038b6 80038b2: 2364 movs r3, #100 ; 0x64 80038b4: 607b str r3, [r7, #4] if(countdown_set>60000){countdown_set=60000;} 80038b6: 687b ldr r3, [r7, #4] 80038b8: 4a4b ldr r2, [pc, #300] ; (80039e8 ) 80038ba: 4293 cmp r3, r2 80038bc: dd01 ble.n 80038c2 80038be: 4b4a ldr r3, [pc, #296] ; (80039e8 ) 80038c0: 607b str r3, [r7, #4] if(key4.code!=0){mode=1;} 80038c2: 4b43 ldr r3, [pc, #268] ; (80039d0 ) 80038c4: 681b ldr r3, [r3, #0] 80038c6: 2b00 cmp r3, #0 80038c8: d003 beq.n 80038d2 80038ca: 230f movs r3, #15 80038cc: 18fb adds r3, r7, r3 80038ce: 2201 movs r2, #1 80038d0: 701a strb r2, [r3, #0] dis_buff.d_num[3]=(countdown_set/100)%10; 80038d2: 687b ldr r3, [r7, #4] 80038d4: 2164 movs r1, #100 ; 0x64 80038d6: 0018 movs r0, r3 80038d8: f7fc fca0 bl 800021c <__divsi3> 80038dc: 0003 movs r3, r0 80038de: 210a movs r1, #10 80038e0: 0018 movs r0, r3 80038e2: f7fc fd81 bl 80003e8 <__aeabi_idivmod> 80038e6: 000b movs r3, r1 80038e8: b2da uxtb r2, r3 80038ea: 4b37 ldr r3, [pc, #220] ; (80039c8 ) 80038ec: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown_set/1000)%10; 80038ee: 687b ldr r3, [r7, #4] 80038f0: 22fa movs r2, #250 ; 0xfa 80038f2: 0091 lsls r1, r2, #2 80038f4: 0018 movs r0, r3 80038f6: f7fc fc91 bl 800021c <__divsi3> 80038fa: 0003 movs r3, r0 80038fc: 210a movs r1, #10 80038fe: 0018 movs r0, r3 8003900: f7fc fd72 bl 80003e8 <__aeabi_idivmod> 8003904: 000b movs r3, r1 8003906: b2da uxtb r2, r3 8003908: 4b2f ldr r3, [pc, #188] ; (80039c8 ) 800390a: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown_set/10000)%10); 800390c: 687b ldr r3, [r7, #4] 800390e: 4933 ldr r1, [pc, #204] ; (80039dc ) 8003910: 0018 movs r0, r3 8003912: f7fc fc83 bl 800021c <__divsi3> 8003916: 0003 movs r3, r0 8003918: 210a movs r1, #10 800391a: 0018 movs r0, r3 800391c: f7fc fd64 bl 80003e8 <__aeabi_idivmod> 8003920: 000b movs r3, r1 8003922: b2da uxtb r2, r3 8003924: 4b28 ldr r3, [pc, #160] ; (80039c8 ) 8003926: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 8003928: 4b27 ldr r3, [pc, #156] ; (80039c8 ) 800392a: 785b ldrb r3, [r3, #1] 800392c: 2b00 cmp r3, #0 800392e: d002 beq.n 8003936 8003930: 4b25 ldr r3, [pc, #148] ; (80039c8 ) 8003932: 785a ldrb r2, [r3, #1] 8003934: e000 b.n 8003938 8003936: 2210 movs r2, #16 8003938: 4b23 ldr r3, [pc, #140] ; (80039c8 ) 800393a: 705a strb r2, [r3, #1] break; 800393c: e0e9 b.n 8003b12 case 5: //overload moto.moto1a=0; 800393e: 4b26 ldr r3, [pc, #152] ; (80039d8 ) 8003940: 2200 movs r2, #0 8003942: 721a strb r2, [r3, #8] moto.moto1b=0; 8003944: 4b24 ldr r3, [pc, #144] ; (80039d8 ) 8003946: 2200 movs r2, #0 8003948: 725a strb r2, [r3, #9] moto.moto2a=0; 800394a: 4b23 ldr r3, [pc, #140] ; (80039d8 ) 800394c: 2200 movs r2, #0 800394e: 729a strb r2, [r3, #10] moto.moto2b=0; 8003950: 4b21 ldr r3, [pc, #132] ; (80039d8 ) 8003952: 2200 movs r2, #0 8003954: 72da strb r2, [r3, #11] dis_buff.led_run=1; 8003956: 4b1c ldr r3, [pc, #112] ; (80039c8 ) 8003958: 2201 movs r2, #1 800395a: 731a strb r2, [r3, #12] overload_times=0; 800395c: 230c movs r3, #12 800395e: 18fb adds r3, r7, r3 8003960: 2200 movs r2, #0 8003962: 801a strh r2, [r3, #0] dis_buff.d_num[3]=(countdown/100)%10; 8003964: 68bb ldr r3, [r7, #8] 8003966: 2164 movs r1, #100 ; 0x64 8003968: 0018 movs r0, r3 800396a: f7fc fc57 bl 800021c <__divsi3> 800396e: 0003 movs r3, r0 8003970: 210a movs r1, #10 8003972: 0018 movs r0, r3 8003974: f7fc fd38 bl 80003e8 <__aeabi_idivmod> 8003978: 000b movs r3, r1 800397a: b2da uxtb r2, r3 800397c: 4b12 ldr r3, [pc, #72] ; (80039c8 ) 800397e: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 8003980: 68bb ldr r3, [r7, #8] 8003982: 22fa movs r2, #250 ; 0xfa 8003984: 0091 lsls r1, r2, #2 8003986: 0018 movs r0, r3 8003988: f7fc fc48 bl 800021c <__divsi3> 800398c: 0003 movs r3, r0 800398e: 210a movs r1, #10 8003990: 0018 movs r0, r3 8003992: f7fc fd29 bl 80003e8 <__aeabi_idivmod> 8003996: 000b movs r3, r1 8003998: b2da uxtb r2, r3 800399a: 4b0b ldr r3, [pc, #44] ; (80039c8 ) 800399c: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 800399e: 68bb ldr r3, [r7, #8] 80039a0: 490e ldr r1, [pc, #56] ; (80039dc ) 80039a2: 0018 movs r0, r3 80039a4: f7fc fc3a bl 800021c <__divsi3> 80039a8: 0003 movs r3, r0 80039aa: 210a movs r1, #10 80039ac: 0018 movs r0, r3 80039ae: f7fc fd1b bl 80003e8 <__aeabi_idivmod> 80039b2: 000b movs r3, r1 80039b4: b2da uxtb r2, r3 80039b6: 4b04 ldr r3, [pc, #16] ; (80039c8 ) 80039b8: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 80039ba: 4b03 ldr r3, [pc, #12] ; (80039c8 ) 80039bc: 785b ldrb r3, [r3, #1] 80039be: 2b00 cmp r3, #0 80039c0: d014 beq.n 80039ec 80039c2: 4b01 ldr r3, [pc, #4] ; (80039c8 ) 80039c4: 785a ldrb r2, [r3, #1] 80039c6: e012 b.n 80039ee 80039c8: 20000038 .word 0x20000038 80039cc: 20000110 .word 0x20000110 80039d0: 200000d8 .word 0x200000d8 80039d4: 20000100 .word 0x20000100 80039d8: 20000144 .word 0x20000144 80039dc: 00002710 .word 0x00002710 80039e0: 20000134 .word 0x20000134 80039e4: fffffc18 .word 0xfffffc18 80039e8: 0000ea60 .word 0x0000ea60 80039ec: 2210 movs r2, #16 80039ee: 4b7c ldr r3, [pc, #496] ; (8003be0 ) 80039f0: 705a strb r2, [r3, #1] dis_buff.dot3=1; 80039f2: 4b7b ldr r3, [pc, #492] ; (8003be0 ) 80039f4: 2201 movs r2, #1 80039f6: 729a strb r2, [r3, #10] if(key4.code!=0){mode=1;} 80039f8: 4b7a ldr r3, [pc, #488] ; (8003be4 ) 80039fa: 681b ldr r3, [r3, #0] 80039fc: 2b00 cmp r3, #0 80039fe: d003 beq.n 8003a08 8003a00: 230f movs r3, #15 8003a02: 18fb adds r3, r7, r3 8003a04: 2201 movs r2, #1 8003a06: 701a strb r2, [r3, #0] if(key2.code!=0) 8003a08: 4b77 ldr r3, [pc, #476] ; (8003be8 ) 8003a0a: 681b ldr r3, [r3, #0] 8003a0c: 2b00 cmp r3, #0 8003a0e: d00c beq.n 8003a2a { mode=2; 8003a10: 230f movs r3, #15 8003a12: 18fb adds r3, r7, r3 8003a14: 2202 movs r2, #2 8003a16: 701a strb r2, [r3, #0] if(overload_mode==2) 8003a18: 230e movs r3, #14 8003a1a: 18fb adds r3, r7, r3 8003a1c: 781b ldrb r3, [r3, #0] 8003a1e: 2b02 cmp r3, #2 8003a20: d003 beq.n 8003a2a { }else { countdown=countdown_set-countdown; 8003a22: 687a ldr r2, [r7, #4] 8003a24: 68bb ldr r3, [r7, #8] 8003a26: 1ad3 subs r3, r2, r3 8003a28: 60bb str r3, [r7, #8] } } if(key3.code!=0) 8003a2a: 4b70 ldr r3, [pc, #448] ; (8003bec ) 8003a2c: 681b ldr r3, [r3, #0] 8003a2e: 2b00 cmp r3, #0 8003a30: d06e beq.n 8003b10 { mode=3; 8003a32: 230f movs r3, #15 8003a34: 18fb adds r3, r7, r3 8003a36: 2203 movs r2, #3 8003a38: 701a strb r2, [r3, #0] if(overload_mode==3) 8003a3a: 230e movs r3, #14 8003a3c: 18fb adds r3, r7, r3 8003a3e: 781b ldrb r3, [r3, #0] 8003a40: 2b03 cmp r3, #3 8003a42: d065 beq.n 8003b10 { }else { countdown=countdown_set-countdown; 8003a44: 687a ldr r2, [r7, #4] 8003a46: 68bb ldr r3, [r7, #8] 8003a48: 1ad3 subs r3, r2, r3 8003a4a: 60bb str r3, [r7, #8] } } break; 8003a4c: e060 b.n 8003b10 case 6: //stady mode //config.begin=0xab; //EEPROM_WRITE_BATY(16,(char *)&config,sizeof(config_setting)); //mode=0; if(HAL_GetTick()>runtime) 8003a4e: f7fc ffdb bl 8000a08 8003a52: 0002 movs r2, r0 8003a54: 697b ldr r3, [r7, #20] 8003a56: 4293 cmp r3, r2 8003a58: d216 bcs.n 8003a88 { runtime+=1000; 8003a5a: 697b ldr r3, [r7, #20] 8003a5c: 22fa movs r2, #250 ; 0xfa 8003a5e: 0092 lsls r2, r2, #2 8003a60: 4694 mov ip, r2 8003a62: 4463 add r3, ip 8003a64: 617b str r3, [r7, #20] if(dis_buff.led_run==1) 8003a66: 4b5e ldr r3, [pc, #376] ; (8003be0 ) 8003a68: 7b1b ldrb r3, [r3, #12] 8003a6a: 2b01 cmp r3, #1 8003a6c: d106 bne.n 8003a7c { dis_buff.led_run=0; 8003a6e: 4b5c ldr r3, [pc, #368] ; (8003be0 ) 8003a70: 2200 movs r2, #0 8003a72: 731a strb r2, [r3, #12] dis_buff.dot4=1; 8003a74: 4b5a ldr r3, [pc, #360] ; (8003be0 ) 8003a76: 2201 movs r2, #1 8003a78: 72da strb r2, [r3, #11] 8003a7a: e005 b.n 8003a88 }else { dis_buff.led_run=1; 8003a7c: 4b58 ldr r3, [pc, #352] ; (8003be0 ) 8003a7e: 2201 movs r2, #1 8003a80: 731a strb r2, [r3, #12] dis_buff.dot4=0; 8003a82: 4b57 ldr r3, [pc, #348] ; (8003be0 ) 8003a84: 2200 movs r2, #0 8003a86: 72da strb r2, [r3, #11] } } dis_buff.d_num[3]=(config.begin)%10; 8003a88: 4b59 ldr r3, [pc, #356] ; (8003bf0 ) 8003a8a: 781b ldrb r3, [r3, #0] 8003a8c: 210a movs r1, #10 8003a8e: 0018 movs r0, r3 8003a90: f7fc fbc0 bl 8000214 <__aeabi_uidivmod> 8003a94: 000b movs r3, r1 8003a96: b2da uxtb r2, r3 8003a98: 4b51 ldr r3, [pc, #324] ; (8003be0 ) 8003a9a: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(config.begin/10)%10; 8003a9c: 4b54 ldr r3, [pc, #336] ; (8003bf0 ) 8003a9e: 781b ldrb r3, [r3, #0] 8003aa0: 210a movs r1, #10 8003aa2: 0018 movs r0, r3 8003aa4: f7fc fb30 bl 8000108 <__udivsi3> 8003aa8: 0003 movs r3, r0 8003aaa: b2db uxtb r3, r3 8003aac: 210a movs r1, #10 8003aae: 0018 movs r0, r3 8003ab0: f7fc fbb0 bl 8000214 <__aeabi_uidivmod> 8003ab4: 000b movs r3, r1 8003ab6: b2da uxtb r2, r3 8003ab8: 4b49 ldr r3, [pc, #292] ; (8003be0 ) 8003aba: 709a strb r2, [r3, #2] dis_buff.d_num[1]=(config.begin/100)%10; 8003abc: 4b4c ldr r3, [pc, #304] ; (8003bf0 ) 8003abe: 781b ldrb r3, [r3, #0] 8003ac0: 2164 movs r1, #100 ; 0x64 8003ac2: 0018 movs r0, r3 8003ac4: f7fc fb20 bl 8000108 <__udivsi3> 8003ac8: 0003 movs r3, r0 8003aca: b2db uxtb r3, r3 8003acc: 210a movs r1, #10 8003ace: 0018 movs r0, r3 8003ad0: f7fc fba0 bl 8000214 <__aeabi_uidivmod> 8003ad4: 000b movs r3, r1 8003ad6: b2da uxtb r2, r3 8003ad8: 4b41 ldr r3, [pc, #260] ; (8003be0 ) 8003ada: 705a strb r2, [r3, #1] dis_buff.d_num[0]=(config.begin/1000)%10; 8003adc: 4b44 ldr r3, [pc, #272] ; (8003bf0 ) 8003ade: 781b ldrb r3, [r3, #0] 8003ae0: 001a movs r2, r3 8003ae2: 23fa movs r3, #250 ; 0xfa 8003ae4: 0099 lsls r1, r3, #2 8003ae6: 0010 movs r0, r2 8003ae8: f7fc fb98 bl 800021c <__divsi3> 8003aec: 0003 movs r3, r0 8003aee: 210a movs r1, #10 8003af0: 0018 movs r0, r3 8003af2: f7fc fc79 bl 80003e8 <__aeabi_idivmod> 8003af6: 000b movs r3, r1 8003af8: b2da uxtb r2, r3 8003afa: 4b39 ldr r3, [pc, #228] ; (8003be0 ) 8003afc: 701a strb r2, [r3, #0] break; 8003afe: e008 b.n 8003b12 break; 8003b00: 46c0 nop ; (mov r8, r8) 8003b02: e006 b.n 8003b12 break; 8003b04: 46c0 nop ; (mov r8, r8) 8003b06: e004 b.n 8003b12 break; 8003b08: 46c0 nop ; (mov r8, r8) 8003b0a: e002 b.n 8003b12 break; 8003b0c: 46c0 nop ; (mov r8, r8) 8003b0e: e000 b.n 8003b12 break; 8003b10: 46c0 nop ; (mov r8, r8) } if(ADCC.adc_value[0]>600||ADCC.adc_value[1]>600) 8003b12: 4b38 ldr r3, [pc, #224] ; (8003bf4 ) 8003b14: 68da ldr r2, [r3, #12] 8003b16: 2396 movs r3, #150 ; 0x96 8003b18: 009b lsls r3, r3, #2 8003b1a: 429a cmp r2, r3 8003b1c: dc05 bgt.n 8003b2a 8003b1e: 4b35 ldr r3, [pc, #212] ; (8003bf4 ) 8003b20: 691a ldr r2, [r3, #16] 8003b22: 2396 movs r3, #150 ; 0x96 8003b24: 009b lsls r3, r3, #2 8003b26: 429a cmp r2, r3 8003b28: dd05 ble.n 8003b36 { GEI_BUTTON_CODE(&overload,1); 8003b2a: 4b33 ldr r3, [pc, #204] ; (8003bf8 ) 8003b2c: 2101 movs r1, #1 8003b2e: 0018 movs r0, r3 8003b30: f7fe fd7a bl 8002628 8003b34: e004 b.n 8003b40 }else { GEI_BUTTON_CODE(&overload,0); 8003b36: 4b30 ldr r3, [pc, #192] ; (8003bf8 ) 8003b38: 2100 movs r1, #0 8003b3a: 0018 movs r0, r3 8003b3c: f7fe fd74 bl 8002628 } switch(r480.key) 8003b40: 4b2e ldr r3, [pc, #184] ; (8003bfc ) 8003b42: 789b ldrb r3, [r3, #2] 8003b44: 2bde cmp r3, #222 ; 0xde 8003b46: d014 beq.n 8003b72 8003b48: dc17 bgt.n 8003b7a 8003b4a: 2bdd cmp r3, #221 ; 0xdd 8003b4c: d00d beq.n 8003b6a 8003b4e: dc14 bgt.n 8003b7a 8003b50: 2bd7 cmp r3, #215 ; 0xd7 8003b52: d002 beq.n 8003b5a 8003b54: 2bdb cmp r3, #219 ; 0xdb 8003b56: d004 beq.n 8003b62 8003b58: e00f b.n 8003b7a { case 0xd7: dis_buff.button_flag[0]=1; 8003b5a: 4b21 ldr r3, [pc, #132] ; (8003be0 ) 8003b5c: 2201 movs r2, #1 8003b5e: 711a strb r2, [r3, #4] break; 8003b60: e00b b.n 8003b7a case 0xdb: dis_buff.button_flag[1]=1; 8003b62: 4b1f ldr r3, [pc, #124] ; (8003be0 ) 8003b64: 2201 movs r2, #1 8003b66: 715a strb r2, [r3, #5] break; 8003b68: e007 b.n 8003b7a case 0xdd: dis_buff.button_flag[2]=1; 8003b6a: 4b1d ldr r3, [pc, #116] ; (8003be0 ) 8003b6c: 2201 movs r2, #1 8003b6e: 719a strb r2, [r3, #6] break; 8003b70: e003 b.n 8003b7a case 0xde: dis_buff.button_flag[3]=1; 8003b72: 4b1b ldr r3, [pc, #108] ; (8003be0 ) 8003b74: 2201 movs r2, #1 8003b76: 71da strb r2, [r3, #7] break; 8003b78: 46c0 nop ; (mov r8, r8) } r480.key=0; 8003b7a: 4b20 ldr r3, [pc, #128] ; (8003bfc ) 8003b7c: 2200 movs r2, #0 8003b7e: 709a strb r2, [r3, #2] GEI_BUTTON_CODE(&key1,dis_buff.button_flag[0]); 8003b80: 4b17 ldr r3, [pc, #92] ; (8003be0 ) 8003b82: 791a ldrb r2, [r3, #4] 8003b84: 4b1e ldr r3, [pc, #120] ; (8003c00 ) 8003b86: 0011 movs r1, r2 8003b88: 0018 movs r0, r3 8003b8a: f7fe fd4d bl 8002628 GEI_BUTTON_CODE(&key2,dis_buff.button_flag[1]); 8003b8e: 4b14 ldr r3, [pc, #80] ; (8003be0 ) 8003b90: 795a ldrb r2, [r3, #5] 8003b92: 4b15 ldr r3, [pc, #84] ; (8003be8 ) 8003b94: 0011 movs r1, r2 8003b96: 0018 movs r0, r3 8003b98: f7fe fd46 bl 8002628 GEI_BUTTON_CODE(&key3,dis_buff.button_flag[2]); 8003b9c: 4b10 ldr r3, [pc, #64] ; (8003be0 ) 8003b9e: 799a ldrb r2, [r3, #6] 8003ba0: 4b12 ldr r3, [pc, #72] ; (8003bec ) 8003ba2: 0011 movs r1, r2 8003ba4: 0018 movs r0, r3 8003ba6: f7fe fd3f bl 8002628 GEI_BUTTON_CODE(&key4,dis_buff.button_flag[3]); 8003baa: 4b0d ldr r3, [pc, #52] ; (8003be0 ) 8003bac: 79da ldrb r2, [r3, #7] 8003bae: 4b0d ldr r3, [pc, #52] ; (8003be4 ) 8003bb0: 0011 movs r1, r2 8003bb2: 0018 movs r0, r3 8003bb4: f7fe fd38 bl 8002628 dis_buff.button_flag[0]=0; 8003bb8: 4b09 ldr r3, [pc, #36] ; (8003be0 ) 8003bba: 2200 movs r2, #0 8003bbc: 711a strb r2, [r3, #4] dis_buff.button_flag[1]=0; 8003bbe: 4b08 ldr r3, [pc, #32] ; (8003be0 ) 8003bc0: 2200 movs r2, #0 8003bc2: 715a strb r2, [r3, #5] dis_buff.button_flag[2]=0; 8003bc4: 4b06 ldr r3, [pc, #24] ; (8003be0 ) 8003bc6: 2200 movs r2, #0 8003bc8: 719a strb r2, [r3, #6] dis_buff.button_flag[3]=0; 8003bca: 4b05 ldr r3, [pc, #20] ; (8003be0 ) 8003bcc: 2200 movs r2, #0 8003bce: 71da strb r2, [r3, #7] HT1621_Display_GetButton(); 8003bd0: f7ff fafe bl 80031d0 hc2_sever(); 8003bd4: f7ff f9e8 bl 8002fa8 moto_server(); 8003bd8: f7ff fa2a bl 8003030 for(char a=0;a<2;a++) 8003bdc: f7ff fbb8 bl 8003350 8003be0: 20000038 .word 0x20000038 8003be4: 200000d8 .word 0x200000d8 8003be8: 20000134 .word 0x20000134 8003bec: 20000110 .word 0x20000110 8003bf0: 20000154 .word 0x20000154 8003bf4: 20000120 .word 0x20000120 8003bf8: 20000100 .word 0x20000100 8003bfc: 200000e8 .word 0x200000e8 8003c00: 200000f0 .word 0x200000f0 08003c04 : int read_char_flag=0; char read_data_buffer[3]; char read_begin=0; void r480_init() { 8003c04: b580 push {r7, lr} 8003c06: af00 add r7, sp, #0 HAL_TIM_Base_Start_IT(&htim14); 8003c08: 4b04 ldr r3, [pc, #16] ; (8003c1c ) 8003c0a: 0018 movs r0, r3 8003c0c: f7fe fb14 bl 8002238 r480.times=0; 8003c10: 4b03 ldr r3, [pc, #12] ; (8003c20 ) 8003c12: 2200 movs r2, #0 8003c14: 809a strh r2, [r3, #4] } 8003c16: 46c0 nop ; (mov r8, r8) 8003c18: 46bd mov sp, r7 8003c1a: bd80 pop {r7, pc} 8003c1c: 2000004c .word 0x2000004c 8003c20: 200000e8 .word 0x200000e8 08003c24 : void read_433_exit() { 8003c24: b590 push {r4, r7, lr} 8003c26: b083 sub sp, #12 8003c28: af00 add r7, sp, #0 char a=read_infrared; 8003c2a: 1dfc adds r4, r7, #7 8003c2c: 2390 movs r3, #144 ; 0x90 8003c2e: 05db lsls r3, r3, #23 8003c30: 2108 movs r1, #8 8003c32: 0018 movs r0, r3 8003c34: f7fd fdf0 bl 8001818 8003c38: 0003 movs r3, r0 8003c3a: 7023 strb r3, [r4, #0] int b; if(read_begin==0) 8003c3c: 4b41 ldr r3, [pc, #260] ; (8003d44 ) 8003c3e: 781b ldrb r3, [r3, #0] 8003c40: 2b00 cmp r3, #0 8003c42: d123 bne.n 8003c8c { if(a==0) 8003c44: 1dfb adds r3, r7, #7 8003c46: 781b ldrb r3, [r3, #0] 8003c48: 2b00 cmp r3, #0 8003c4a: d103 bne.n 8003c54 { timer_100us_tick=0; 8003c4c: 4b3e ldr r3, [pc, #248] ; (8003d48 ) 8003c4e: 2200 movs r2, #0 8003c50: 801a strh r2, [r3, #0] return ; 8003c52: e073 b.n 8003d3c }else { if(timer_100us_tick>70&&timer_100us_tick<100) 8003c54: 4b3c ldr r3, [pc, #240] ; (8003d48 ) 8003c56: 881b ldrh r3, [r3, #0] 8003c58: 2b46 cmp r3, #70 ; 0x46 8003c5a: d800 bhi.n 8003c5e 8003c5c: e06e b.n 8003d3c 8003c5e: 4b3a ldr r3, [pc, #232] ; (8003d48 ) 8003c60: 881b ldrh r3, [r3, #0] 8003c62: 2b63 cmp r3, #99 ; 0x63 8003c64: d86a bhi.n 8003d3c { read_begin=1; 8003c66: 4b37 ldr r3, [pc, #220] ; (8003d44 ) 8003c68: 2201 movs r2, #1 8003c6a: 701a strb r2, [r3, #0] r480.times++; 8003c6c: 4b37 ldr r3, [pc, #220] ; (8003d4c ) 8003c6e: 889b ldrh r3, [r3, #4] 8003c70: 3301 adds r3, #1 8003c72: b29a uxth r2, r3 8003c74: 4b35 ldr r3, [pc, #212] ; (8003d4c ) 8003c76: 809a strh r2, [r3, #4] read_bit_flag=0; 8003c78: 4b35 ldr r3, [pc, #212] ; (8003d50 ) 8003c7a: 2200 movs r2, #0 8003c7c: 601a str r2, [r3, #0] read_char_flag=0; 8003c7e: 4b35 ldr r3, [pc, #212] ; (8003d54 ) 8003c80: 2200 movs r2, #0 8003c82: 601a str r2, [r3, #0] timer_100us_tick=0; 8003c84: 4b30 ldr r3, [pc, #192] ; (8003d48 ) 8003c86: 2200 movs r2, #0 8003c88: 801a strh r2, [r3, #0] return ; 8003c8a: e057 b.n 8003d3c } } }else { if(timer_100us_tick<5) 8003c8c: 4b2e ldr r3, [pc, #184] ; (8003d48 ) 8003c8e: 881b ldrh r3, [r3, #0] 8003c90: 2b04 cmp r3, #4 8003c92: d803 bhi.n 8003c9c { timer_100us_tick=0; 8003c94: 4b2c ldr r3, [pc, #176] ; (8003d48 ) 8003c96: 2200 movs r2, #0 8003c98: 801a strh r2, [r3, #0] return ; 8003c9a: e04f b.n 8003d3c }else if(timer_100us_tick<12) 8003c9c: 4b2a ldr r3, [pc, #168] ; (8003d48 ) 8003c9e: 881b ldrh r3, [r3, #0] 8003ca0: 2b0b cmp r3, #11 8003ca2: d844 bhi.n 8003d2e { read_data_buffer[read_char_flag]<<=1; 8003ca4: 4b2b ldr r3, [pc, #172] ; (8003d54 ) 8003ca6: 681b ldr r3, [r3, #0] 8003ca8: 4a2b ldr r2, [pc, #172] ; (8003d58 ) 8003caa: 5cd1 ldrb r1, [r2, r3] 8003cac: 4b29 ldr r3, [pc, #164] ; (8003d54 ) 8003cae: 681a ldr r2, [r3, #0] 8003cb0: 1c0b adds r3, r1, #0 8003cb2: 18db adds r3, r3, r3 8003cb4: b2d9 uxtb r1, r3 8003cb6: 4b28 ldr r3, [pc, #160] ; (8003d58 ) 8003cb8: 5499 strb r1, [r3, r2] if(a==1) 8003cba: 1dfb adds r3, r7, #7 8003cbc: 781b ldrb r3, [r3, #0] 8003cbe: 2b01 cmp r3, #1 8003cc0: d10a bne.n 8003cd8 { read_data_buffer[read_char_flag]|=0x01; 8003cc2: 4b24 ldr r3, [pc, #144] ; (8003d54 ) 8003cc4: 681b ldr r3, [r3, #0] 8003cc6: 4a24 ldr r2, [pc, #144] ; (8003d58 ) 8003cc8: 5cd2 ldrb r2, [r2, r3] 8003cca: 4b22 ldr r3, [pc, #136] ; (8003d54 ) 8003ccc: 681b ldr r3, [r3, #0] 8003cce: 2101 movs r1, #1 8003cd0: 430a orrs r2, r1 8003cd2: b2d1 uxtb r1, r2 8003cd4: 4a20 ldr r2, [pc, #128] ; (8003d58 ) 8003cd6: 54d1 strb r1, [r2, r3] } read_bit_flag++; 8003cd8: 4b1d ldr r3, [pc, #116] ; (8003d50 ) 8003cda: 681b ldr r3, [r3, #0] 8003cdc: 1c5a adds r2, r3, #1 8003cde: 4b1c ldr r3, [pc, #112] ; (8003d50 ) 8003ce0: 601a str r2, [r3, #0] if(read_bit_flag==8) 8003ce2: 4b1b ldr r3, [pc, #108] ; (8003d50 ) 8003ce4: 681b ldr r3, [r3, #0] 8003ce6: 2b08 cmp r3, #8 8003ce8: d11d bne.n 8003d26 { read_bit_flag=0; 8003cea: 4b19 ldr r3, [pc, #100] ; (8003d50 ) 8003cec: 2200 movs r2, #0 8003cee: 601a str r2, [r3, #0] read_char_flag++; 8003cf0: 4b18 ldr r3, [pc, #96] ; (8003d54 ) 8003cf2: 681b ldr r3, [r3, #0] 8003cf4: 1c5a adds r2, r3, #1 8003cf6: 4b17 ldr r3, [pc, #92] ; (8003d54 ) 8003cf8: 601a str r2, [r3, #0] if(read_char_flag==3) 8003cfa: 4b16 ldr r3, [pc, #88] ; (8003d54 ) 8003cfc: 681b ldr r3, [r3, #0] 8003cfe: 2b03 cmp r3, #3 8003d00: d111 bne.n 8003d26 { //got data read_char_flag=0; 8003d02: 4b14 ldr r3, [pc, #80] ; (8003d54 ) 8003d04: 2200 movs r2, #0 8003d06: 601a str r2, [r3, #0] timer_100us_tick=0; 8003d08: 4b0f ldr r3, [pc, #60] ; (8003d48 ) 8003d0a: 2200 movs r2, #0 8003d0c: 801a strh r2, [r3, #0] r480.add[0]=read_data_buffer[0]; 8003d0e: 4b12 ldr r3, [pc, #72] ; (8003d58 ) 8003d10: 781a ldrb r2, [r3, #0] 8003d12: 4b0e ldr r3, [pc, #56] ; (8003d4c ) 8003d14: 701a strb r2, [r3, #0] r480.add[1]=read_data_buffer[1]; 8003d16: 4b10 ldr r3, [pc, #64] ; (8003d58 ) 8003d18: 785a ldrb r2, [r3, #1] 8003d1a: 4b0c ldr r3, [pc, #48] ; (8003d4c ) 8003d1c: 705a strb r2, [r3, #1] r480.key=read_data_buffer[2]; 8003d1e: 4b0e ldr r3, [pc, #56] ; (8003d58 ) 8003d20: 789a ldrb r2, [r3, #2] 8003d22: 4b0a ldr r3, [pc, #40] ; (8003d4c ) 8003d24: 709a strb r2, [r3, #2] } } timer_100us_tick=0; 8003d26: 4b08 ldr r3, [pc, #32] ; (8003d48 ) 8003d28: 2200 movs r2, #0 8003d2a: 801a strh r2, [r3, #0] return ; 8003d2c: e006 b.n 8003d3c }else//time out { read_begin=0; 8003d2e: 4b05 ldr r3, [pc, #20] ; (8003d44 ) 8003d30: 2200 movs r2, #0 8003d32: 701a strb r2, [r3, #0] timer_100us_tick=0; 8003d34: 4b04 ldr r3, [pc, #16] ; (8003d48 ) 8003d36: 2200 movs r2, #0 8003d38: 801a strh r2, [r3, #0] return ; 8003d3a: 46c0 nop ; (mov r8, r8) } } } 8003d3c: 46bd mov sp, r7 8003d3e: b003 add sp, #12 8003d40: bd90 pop {r4, r7, pc} 8003d42: 46c0 nop ; (mov r8, r8) 8003d44: 20000034 .word 0x20000034 8003d48: 20000028 .word 0x20000028 8003d4c: 200000e8 .word 0x200000e8 8003d50: 2000002c .word 0x2000002c 8003d54: 20000030 .word 0x20000030 8003d58: 2000015c .word 0x2000015c 08003d5c : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8003d5c: b580 push {r7, lr} 8003d5e: b082 sub sp, #8 8003d60: af00 add r7, sp, #0 8003d62: 0002 movs r2, r0 8003d64: 1dbb adds r3, r7, #6 8003d66: 801a strh r2, [r3, #0] switch(GPIO_Pin) 8003d68: 1dbb adds r3, r7, #6 8003d6a: 881b ldrh r3, [r3, #0] 8003d6c: 2b08 cmp r3, #8 8003d6e: d102 bne.n 8003d76 { case infeaed_Pin: read_433_exit(); 8003d70: f7ff ff58 bl 8003c24 return ; 8003d74: 46c0 nop ; (mov r8, r8) break; } } 8003d76: 46bd mov sp, r7 8003d78: b002 add sp, #8 8003d7a: bd80 pop {r7, pc} 08003d7c : void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)//100us { 8003d7c: b580 push {r7, lr} 8003d7e: b082 sub sp, #8 8003d80: af00 add r7, sp, #0 8003d82: 6078 str r0, [r7, #4] if (htim == (&htim14)) 8003d84: 687a ldr r2, [r7, #4] 8003d86: 4b06 ldr r3, [pc, #24] ; (8003da0 ) 8003d88: 429a cmp r2, r3 8003d8a: d105 bne.n 8003d98 { timer_100us_tick++; 8003d8c: 4b05 ldr r3, [pc, #20] ; (8003da4 ) 8003d8e: 881b ldrh r3, [r3, #0] 8003d90: 3301 adds r3, #1 8003d92: b29a uxth r2, r3 8003d94: 4b03 ldr r3, [pc, #12] ; (8003da4 ) 8003d96: 801a strh r2, [r3, #0] } } 8003d98: 46c0 nop ; (mov r8, r8) 8003d9a: 46bd mov sp, r7 8003d9c: b002 add sp, #8 8003d9e: bd80 pop {r7, pc} 8003da0: 2000004c .word 0x2000004c 8003da4: 20000028 .word 0x20000028 08003da8 <__libc_init_array>: 8003da8: b570 push {r4, r5, r6, lr} 8003daa: 2600 movs r6, #0 8003dac: 4d0c ldr r5, [pc, #48] ; (8003de0 <__libc_init_array+0x38>) 8003dae: 4c0d ldr r4, [pc, #52] ; (8003de4 <__libc_init_array+0x3c>) 8003db0: 1b64 subs r4, r4, r5 8003db2: 10a4 asrs r4, r4, #2 8003db4: 42a6 cmp r6, r4 8003db6: d109 bne.n 8003dcc <__libc_init_array+0x24> 8003db8: 2600 movs r6, #0 8003dba: f000 f821 bl 8003e00 <_init> 8003dbe: 4d0a ldr r5, [pc, #40] ; (8003de8 <__libc_init_array+0x40>) 8003dc0: 4c0a ldr r4, [pc, #40] ; (8003dec <__libc_init_array+0x44>) 8003dc2: 1b64 subs r4, r4, r5 8003dc4: 10a4 asrs r4, r4, #2 8003dc6: 42a6 cmp r6, r4 8003dc8: d105 bne.n 8003dd6 <__libc_init_array+0x2e> 8003dca: bd70 pop {r4, r5, r6, pc} 8003dcc: 00b3 lsls r3, r6, #2 8003dce: 58eb ldr r3, [r5, r3] 8003dd0: 4798 blx r3 8003dd2: 3601 adds r6, #1 8003dd4: e7ee b.n 8003db4 <__libc_init_array+0xc> 8003dd6: 00b3 lsls r3, r6, #2 8003dd8: 58eb ldr r3, [r5, r3] 8003dda: 4798 blx r3 8003ddc: 3601 adds r6, #1 8003dde: e7f2 b.n 8003dc6 <__libc_init_array+0x1e> 8003de0: 08003e78 .word 0x08003e78 8003de4: 08003e78 .word 0x08003e78 8003de8: 08003e78 .word 0x08003e78 8003dec: 08003e7c .word 0x08003e7c 08003df0 : 8003df0: 0003 movs r3, r0 8003df2: 1882 adds r2, r0, r2 8003df4: 4293 cmp r3, r2 8003df6: d100 bne.n 8003dfa 8003df8: 4770 bx lr 8003dfa: 7019 strb r1, [r3, #0] 8003dfc: 3301 adds r3, #1 8003dfe: e7f9 b.n 8003df4 08003e00 <_init>: 8003e00: b5f8 push {r3, r4, r5, r6, r7, lr} 8003e02: 46c0 nop ; (mov r8, r8) 8003e04: bcf8 pop {r3, r4, r5, r6, r7} 8003e06: bc08 pop {r3} 8003e08: 469e mov lr, r3 8003e0a: 4770 bx lr 08003e0c <_fini>: 8003e0c: b5f8 push {r3, r4, r5, r6, r7, lr} 8003e0e: 46c0 nop ; (mov r8, r8) 8003e10: bcf8 pop {r3, r4, r5, r6, r7} 8003e12: bc08 pop {r3} 8003e14: 469e mov lr, r3 8003e16: 4770 bx lr