Motor_Controller2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00003c7c 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000060 08003d3c 08003d3c 00013d3c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08003d9c 08003d9c 00020070 2**0 CONTENTS 4 .ARM 00000000 08003d9c 08003d9c 00020070 2**0 CONTENTS 5 .preinit_array 00000000 08003d9c 08003d9c 00020070 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08003d9c 08003d9c 00013d9c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08003da0 08003da0 00013da0 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000070 20000000 08003da4 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000178 20000070 08003e14 00020070 2**2 ALLOC 10 ._user_heap_stack 00000600 200001e8 08003e14 000201e8 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00020070 2**0 CONTENTS, READONLY 12 .debug_info 0000b642 00000000 00000000 00020098 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002119 00000000 00000000 0002b6da 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000b40 00000000 00000000 0002d7f8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000a30 00000000 00000000 0002e338 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000101a6 00000000 00000000 0002ed68 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000e927 00000000 00000000 0003ef0e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0005f097 00000000 00000000 0004d835 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 000ac8cc 2**0 CONTENTS, READONLY 20 .debug_frame 00002844 00000000 00000000 000ac920 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 20000070 .word 0x20000070 80000e0: 00000000 .word 0x00000000 80000e4: 08003d24 .word 0x08003d24 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000074 .word 0x20000074 8000104: 08003d24 .word 0x08003d24 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__divsi3>: 800021c: 4603 mov r3, r0 800021e: 430b orrs r3, r1 8000220: d47f bmi.n 8000322 <__divsi3+0x106> 8000222: 2200 movs r2, #0 8000224: 0843 lsrs r3, r0, #1 8000226: 428b cmp r3, r1 8000228: d374 bcc.n 8000314 <__divsi3+0xf8> 800022a: 0903 lsrs r3, r0, #4 800022c: 428b cmp r3, r1 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4> 8000230: 0a03 lsrs r3, r0, #8 8000232: 428b cmp r3, r1 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4> 8000236: 0b03 lsrs r3, r0, #12 8000238: 428b cmp r3, r1 800023a: d328 bcc.n 800028e <__divsi3+0x72> 800023c: 0c03 lsrs r3, r0, #16 800023e: 428b cmp r3, r1 8000240: d30d bcc.n 800025e <__divsi3+0x42> 8000242: 22ff movs r2, #255 ; 0xff 8000244: 0209 lsls r1, r1, #8 8000246: ba12 rev r2, r2 8000248: 0c03 lsrs r3, r0, #16 800024a: 428b cmp r3, r1 800024c: d302 bcc.n 8000254 <__divsi3+0x38> 800024e: 1212 asrs r2, r2, #8 8000250: 0209 lsls r1, r1, #8 8000252: d065 beq.n 8000320 <__divsi3+0x104> 8000254: 0b03 lsrs r3, r0, #12 8000256: 428b cmp r3, r1 8000258: d319 bcc.n 800028e <__divsi3+0x72> 800025a: e000 b.n 800025e <__divsi3+0x42> 800025c: 0a09 lsrs r1, r1, #8 800025e: 0bc3 lsrs r3, r0, #15 8000260: 428b cmp r3, r1 8000262: d301 bcc.n 8000268 <__divsi3+0x4c> 8000264: 03cb lsls r3, r1, #15 8000266: 1ac0 subs r0, r0, r3 8000268: 4152 adcs r2, r2 800026a: 0b83 lsrs r3, r0, #14 800026c: 428b cmp r3, r1 800026e: d301 bcc.n 8000274 <__divsi3+0x58> 8000270: 038b lsls r3, r1, #14 8000272: 1ac0 subs r0, r0, r3 8000274: 4152 adcs r2, r2 8000276: 0b43 lsrs r3, r0, #13 8000278: 428b cmp r3, r1 800027a: d301 bcc.n 8000280 <__divsi3+0x64> 800027c: 034b lsls r3, r1, #13 800027e: 1ac0 subs r0, r0, r3 8000280: 4152 adcs r2, r2 8000282: 0b03 lsrs r3, r0, #12 8000284: 428b cmp r3, r1 8000286: d301 bcc.n 800028c <__divsi3+0x70> 8000288: 030b lsls r3, r1, #12 800028a: 1ac0 subs r0, r0, r3 800028c: 4152 adcs r2, r2 800028e: 0ac3 lsrs r3, r0, #11 8000290: 428b cmp r3, r1 8000292: d301 bcc.n 8000298 <__divsi3+0x7c> 8000294: 02cb lsls r3, r1, #11 8000296: 1ac0 subs r0, r0, r3 8000298: 4152 adcs r2, r2 800029a: 0a83 lsrs r3, r0, #10 800029c: 428b cmp r3, r1 800029e: d301 bcc.n 80002a4 <__divsi3+0x88> 80002a0: 028b lsls r3, r1, #10 80002a2: 1ac0 subs r0, r0, r3 80002a4: 4152 adcs r2, r2 80002a6: 0a43 lsrs r3, r0, #9 80002a8: 428b cmp r3, r1 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94> 80002ac: 024b lsls r3, r1, #9 80002ae: 1ac0 subs r0, r0, r3 80002b0: 4152 adcs r2, r2 80002b2: 0a03 lsrs r3, r0, #8 80002b4: 428b cmp r3, r1 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0> 80002b8: 020b lsls r3, r1, #8 80002ba: 1ac0 subs r0, r0, r3 80002bc: 4152 adcs r2, r2 80002be: d2cd bcs.n 800025c <__divsi3+0x40> 80002c0: 09c3 lsrs r3, r0, #7 80002c2: 428b cmp r3, r1 80002c4: d301 bcc.n 80002ca <__divsi3+0xae> 80002c6: 01cb lsls r3, r1, #7 80002c8: 1ac0 subs r0, r0, r3 80002ca: 4152 adcs r2, r2 80002cc: 0983 lsrs r3, r0, #6 80002ce: 428b cmp r3, r1 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba> 80002d2: 018b lsls r3, r1, #6 80002d4: 1ac0 subs r0, r0, r3 80002d6: 4152 adcs r2, r2 80002d8: 0943 lsrs r3, r0, #5 80002da: 428b cmp r3, r1 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6> 80002de: 014b lsls r3, r1, #5 80002e0: 1ac0 subs r0, r0, r3 80002e2: 4152 adcs r2, r2 80002e4: 0903 lsrs r3, r0, #4 80002e6: 428b cmp r3, r1 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2> 80002ea: 010b lsls r3, r1, #4 80002ec: 1ac0 subs r0, r0, r3 80002ee: 4152 adcs r2, r2 80002f0: 08c3 lsrs r3, r0, #3 80002f2: 428b cmp r3, r1 80002f4: d301 bcc.n 80002fa <__divsi3+0xde> 80002f6: 00cb lsls r3, r1, #3 80002f8: 1ac0 subs r0, r0, r3 80002fa: 4152 adcs r2, r2 80002fc: 0883 lsrs r3, r0, #2 80002fe: 428b cmp r3, r1 8000300: d301 bcc.n 8000306 <__divsi3+0xea> 8000302: 008b lsls r3, r1, #2 8000304: 1ac0 subs r0, r0, r3 8000306: 4152 adcs r2, r2 8000308: 0843 lsrs r3, r0, #1 800030a: 428b cmp r3, r1 800030c: d301 bcc.n 8000312 <__divsi3+0xf6> 800030e: 004b lsls r3, r1, #1 8000310: 1ac0 subs r0, r0, r3 8000312: 4152 adcs r2, r2 8000314: 1a41 subs r1, r0, r1 8000316: d200 bcs.n 800031a <__divsi3+0xfe> 8000318: 4601 mov r1, r0 800031a: 4152 adcs r2, r2 800031c: 4610 mov r0, r2 800031e: 4770 bx lr 8000320: e05d b.n 80003de <__divsi3+0x1c2> 8000322: 0fca lsrs r2, r1, #31 8000324: d000 beq.n 8000328 <__divsi3+0x10c> 8000326: 4249 negs r1, r1 8000328: 1003 asrs r3, r0, #32 800032a: d300 bcc.n 800032e <__divsi3+0x112> 800032c: 4240 negs r0, r0 800032e: 4053 eors r3, r2 8000330: 2200 movs r2, #0 8000332: 469c mov ip, r3 8000334: 0903 lsrs r3, r0, #4 8000336: 428b cmp r3, r1 8000338: d32d bcc.n 8000396 <__divsi3+0x17a> 800033a: 0a03 lsrs r3, r0, #8 800033c: 428b cmp r3, r1 800033e: d312 bcc.n 8000366 <__divsi3+0x14a> 8000340: 22fc movs r2, #252 ; 0xfc 8000342: 0189 lsls r1, r1, #6 8000344: ba12 rev r2, r2 8000346: 0a03 lsrs r3, r0, #8 8000348: 428b cmp r3, r1 800034a: d30c bcc.n 8000366 <__divsi3+0x14a> 800034c: 0189 lsls r1, r1, #6 800034e: 1192 asrs r2, r2, #6 8000350: 428b cmp r3, r1 8000352: d308 bcc.n 8000366 <__divsi3+0x14a> 8000354: 0189 lsls r1, r1, #6 8000356: 1192 asrs r2, r2, #6 8000358: 428b cmp r3, r1 800035a: d304 bcc.n 8000366 <__divsi3+0x14a> 800035c: 0189 lsls r1, r1, #6 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba> 8000360: 1192 asrs r2, r2, #6 8000362: e000 b.n 8000366 <__divsi3+0x14a> 8000364: 0989 lsrs r1, r1, #6 8000366: 09c3 lsrs r3, r0, #7 8000368: 428b cmp r3, r1 800036a: d301 bcc.n 8000370 <__divsi3+0x154> 800036c: 01cb lsls r3, r1, #7 800036e: 1ac0 subs r0, r0, r3 8000370: 4152 adcs r2, r2 8000372: 0983 lsrs r3, r0, #6 8000374: 428b cmp r3, r1 8000376: d301 bcc.n 800037c <__divsi3+0x160> 8000378: 018b lsls r3, r1, #6 800037a: 1ac0 subs r0, r0, r3 800037c: 4152 adcs r2, r2 800037e: 0943 lsrs r3, r0, #5 8000380: 428b cmp r3, r1 8000382: d301 bcc.n 8000388 <__divsi3+0x16c> 8000384: 014b lsls r3, r1, #5 8000386: 1ac0 subs r0, r0, r3 8000388: 4152 adcs r2, r2 800038a: 0903 lsrs r3, r0, #4 800038c: 428b cmp r3, r1 800038e: d301 bcc.n 8000394 <__divsi3+0x178> 8000390: 010b lsls r3, r1, #4 8000392: 1ac0 subs r0, r0, r3 8000394: 4152 adcs r2, r2 8000396: 08c3 lsrs r3, r0, #3 8000398: 428b cmp r3, r1 800039a: d301 bcc.n 80003a0 <__divsi3+0x184> 800039c: 00cb lsls r3, r1, #3 800039e: 1ac0 subs r0, r0, r3 80003a0: 4152 adcs r2, r2 80003a2: 0883 lsrs r3, r0, #2 80003a4: 428b cmp r3, r1 80003a6: d301 bcc.n 80003ac <__divsi3+0x190> 80003a8: 008b lsls r3, r1, #2 80003aa: 1ac0 subs r0, r0, r3 80003ac: 4152 adcs r2, r2 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148> 80003b0: 0843 lsrs r3, r0, #1 80003b2: 428b cmp r3, r1 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e> 80003b6: 004b lsls r3, r1, #1 80003b8: 1ac0 subs r0, r0, r3 80003ba: 4152 adcs r2, r2 80003bc: 1a41 subs r1, r0, r1 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6> 80003c0: 4601 mov r1, r0 80003c2: 4663 mov r3, ip 80003c4: 4152 adcs r2, r2 80003c6: 105b asrs r3, r3, #1 80003c8: 4610 mov r0, r2 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4> 80003cc: 4240 negs r0, r0 80003ce: 2b00 cmp r3, #0 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8> 80003d2: 4249 negs r1, r1 80003d4: 4770 bx lr 80003d6: 4663 mov r3, ip 80003d8: 105b asrs r3, r3, #1 80003da: d300 bcc.n 80003de <__divsi3+0x1c2> 80003dc: 4240 negs r0, r0 80003de: b501 push {r0, lr} 80003e0: 2000 movs r0, #0 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0> 80003e6: bd02 pop {r1, pc} 080003e8 <__aeabi_idivmod>: 80003e8: 2900 cmp r1, #0 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2> 80003ec: e716 b.n 800021c <__divsi3> 80003ee: 4770 bx lr 080003f0 <__aeabi_idiv0>: 80003f0: 4770 bx lr 80003f2: 46c0 nop ; (mov r8, r8) 080003f4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003f4: b580 push {r7, lr} 80003f6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80003f8: f000 faa0 bl 800093c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80003fc: f000 f809 bl 8000412 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000400: f000 f8e4 bl 80005cc MX_ADC_Init(); 8000404: f000 f856 bl 80004b4 MX_TIM14_Init(); 8000408: f000 f8bc bl 8000584 /* USER CODE BEGIN 2 */ my_code(); 800040c: f002 fef0 bl 80031f0 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000410: e7fe b.n 8000410 08000412 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000412: b590 push {r4, r7, lr} 8000414: b091 sub sp, #68 ; 0x44 8000416: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000418: 2410 movs r4, #16 800041a: 193b adds r3, r7, r4 800041c: 0018 movs r0, r3 800041e: 2330 movs r3, #48 ; 0x30 8000420: 001a movs r2, r3 8000422: 2100 movs r1, #0 8000424: f003 fc1a bl 8003c5c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000428: 003b movs r3, r7 800042a: 0018 movs r0, r3 800042c: 2310 movs r3, #16 800042e: 001a movs r2, r3 8000430: 2100 movs r1, #0 8000432: f003 fc13 bl 8003c5c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14; 8000436: 0021 movs r1, r4 8000438: 187b adds r3, r7, r1 800043a: 2212 movs r2, #18 800043c: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800043e: 187b adds r3, r7, r1 8000440: 2201 movs r2, #1 8000442: 60da str r2, [r3, #12] RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 8000444: 187b adds r3, r7, r1 8000446: 2201 movs r2, #1 8000448: 615a str r2, [r3, #20] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800044a: 187b adds r3, r7, r1 800044c: 2210 movs r2, #16 800044e: 611a str r2, [r3, #16] RCC_OscInitStruct.HSI14CalibrationValue = 16; 8000450: 187b adds r3, r7, r1 8000452: 2210 movs r2, #16 8000454: 619a str r2, [r3, #24] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000456: 187b adds r3, r7, r1 8000458: 2202 movs r2, #2 800045a: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 800045c: 187b adds r3, r7, r1 800045e: 2200 movs r2, #0 8000460: 625a str r2, [r3, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; 8000462: 187b adds r3, r7, r1 8000464: 22a0 movs r2, #160 ; 0xa0 8000466: 0392 lsls r2, r2, #14 8000468: 629a str r2, [r3, #40] ; 0x28 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; 800046a: 187b adds r3, r7, r1 800046c: 2200 movs r2, #0 800046e: 62da str r2, [r3, #44] ; 0x2c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000470: 187b adds r3, r7, r1 8000472: 0018 movs r0, r3 8000474: f001 fa1a bl 80018ac 8000478: 1e03 subs r3, r0, #0 800047a: d001 beq.n 8000480 { Error_Handler(); 800047c: f000 f96a bl 8000754 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000480: 003b movs r3, r7 8000482: 2207 movs r2, #7 8000484: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000486: 003b movs r3, r7 8000488: 2202 movs r2, #2 800048a: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800048c: 003b movs r3, r7 800048e: 2200 movs r2, #0 8000490: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000492: 003b movs r3, r7 8000494: 2200 movs r2, #0 8000496: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000498: 003b movs r3, r7 800049a: 2101 movs r1, #1 800049c: 0018 movs r0, r3 800049e: f001 fd1f bl 8001ee0 80004a2: 1e03 subs r3, r0, #0 80004a4: d001 beq.n 80004aa { Error_Handler(); 80004a6: f000 f955 bl 8000754 } } 80004aa: 46c0 nop ; (mov r8, r8) 80004ac: 46bd mov sp, r7 80004ae: b011 add sp, #68 ; 0x44 80004b0: bd90 pop {r4, r7, pc} ... 080004b4 : * @brief ADC Initialization Function * @param None * @retval None */ static void MX_ADC_Init(void) { 80004b4: b580 push {r7, lr} 80004b6: b084 sub sp, #16 80004b8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC_Init 0 */ /* USER CODE END ADC_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80004ba: 1d3b adds r3, r7, #4 80004bc: 0018 movs r0, r3 80004be: 230c movs r3, #12 80004c0: 001a movs r2, r3 80004c2: 2100 movs r1, #0 80004c4: f003 fbca bl 8003c5c /* USER CODE BEGIN ADC_Init 1 */ /* USER CODE END ADC_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc.Instance = ADC1; 80004c8: 4b2c ldr r3, [pc, #176] ; (800057c ) 80004ca: 4a2d ldr r2, [pc, #180] ; (8000580 ) 80004cc: 601a str r2, [r3, #0] hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80004ce: 4b2b ldr r3, [pc, #172] ; (800057c ) 80004d0: 2200 movs r2, #0 80004d2: 605a str r2, [r3, #4] hadc.Init.Resolution = ADC_RESOLUTION_12B; 80004d4: 4b29 ldr r3, [pc, #164] ; (800057c ) 80004d6: 2200 movs r2, #0 80004d8: 609a str r2, [r3, #8] hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80004da: 4b28 ldr r3, [pc, #160] ; (800057c ) 80004dc: 2200 movs r2, #0 80004de: 60da str r2, [r3, #12] hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 80004e0: 4b26 ldr r3, [pc, #152] ; (800057c ) 80004e2: 2201 movs r2, #1 80004e4: 611a str r2, [r3, #16] hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80004e6: 4b25 ldr r3, [pc, #148] ; (800057c ) 80004e8: 2204 movs r2, #4 80004ea: 615a str r2, [r3, #20] hadc.Init.LowPowerAutoWait = DISABLE; 80004ec: 4b23 ldr r3, [pc, #140] ; (800057c ) 80004ee: 2200 movs r2, #0 80004f0: 761a strb r2, [r3, #24] hadc.Init.LowPowerAutoPowerOff = DISABLE; 80004f2: 4b22 ldr r3, [pc, #136] ; (800057c ) 80004f4: 2200 movs r2, #0 80004f6: 765a strb r2, [r3, #25] hadc.Init.ContinuousConvMode = DISABLE; 80004f8: 4b20 ldr r3, [pc, #128] ; (800057c ) 80004fa: 2200 movs r2, #0 80004fc: 769a strb r2, [r3, #26] hadc.Init.DiscontinuousConvMode = DISABLE; 80004fe: 4b1f ldr r3, [pc, #124] ; (800057c ) 8000500: 2200 movs r2, #0 8000502: 76da strb r2, [r3, #27] hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000504: 4b1d ldr r3, [pc, #116] ; (800057c ) 8000506: 22c2 movs r2, #194 ; 0xc2 8000508: 32ff adds r2, #255 ; 0xff 800050a: 61da str r2, [r3, #28] hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 800050c: 4b1b ldr r3, [pc, #108] ; (800057c ) 800050e: 2200 movs r2, #0 8000510: 621a str r2, [r3, #32] hadc.Init.DMAContinuousRequests = DISABLE; 8000512: 4b1a ldr r3, [pc, #104] ; (800057c ) 8000514: 2224 movs r2, #36 ; 0x24 8000516: 2100 movs r1, #0 8000518: 5499 strb r1, [r3, r2] hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 800051a: 4b18 ldr r3, [pc, #96] ; (800057c ) 800051c: 2201 movs r2, #1 800051e: 629a str r2, [r3, #40] ; 0x28 if (HAL_ADC_Init(&hadc) != HAL_OK) 8000520: 4b16 ldr r3, [pc, #88] ; (800057c ) 8000522: 0018 movs r0, r3 8000524: f000 fa6e bl 8000a04 8000528: 1e03 subs r3, r0, #0 800052a: d001 beq.n 8000530 { Error_Handler(); 800052c: f000 f912 bl 8000754 } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_0; 8000530: 1d3b adds r3, r7, #4 8000532: 2200 movs r2, #0 8000534: 601a str r2, [r3, #0] sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 8000536: 1d3b adds r3, r7, #4 8000538: 2280 movs r2, #128 ; 0x80 800053a: 0152 lsls r2, r2, #5 800053c: 605a str r2, [r3, #4] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800053e: 1d3b adds r3, r7, #4 8000540: 2280 movs r2, #128 ; 0x80 8000542: 0552 lsls r2, r2, #21 8000544: 609a str r2, [r3, #8] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000546: 1d3a adds r2, r7, #4 8000548: 4b0c ldr r3, [pc, #48] ; (800057c ) 800054a: 0011 movs r1, r2 800054c: 0018 movs r0, r3 800054e: f000 fcd1 bl 8000ef4 8000552: 1e03 subs r3, r0, #0 8000554: d001 beq.n 800055a { Error_Handler(); 8000556: f000 f8fd bl 8000754 } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_1; 800055a: 1d3b adds r3, r7, #4 800055c: 2201 movs r2, #1 800055e: 601a str r2, [r3, #0] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000560: 1d3a adds r2, r7, #4 8000562: 4b06 ldr r3, [pc, #24] ; (800057c ) 8000564: 0011 movs r1, r2 8000566: 0018 movs r0, r3 8000568: f000 fcc4 bl 8000ef4 800056c: 1e03 subs r3, r0, #0 800056e: d001 beq.n 8000574 { Error_Handler(); 8000570: f000 f8f0 bl 8000754 } /* USER CODE BEGIN ADC_Init 2 */ /* USER CODE END ADC_Init 2 */ } 8000574: 46c0 nop ; (mov r8, r8) 8000576: 46bd mov sp, r7 8000578: b004 add sp, #16 800057a: bd80 pop {r7, pc} 800057c: 200000fc .word 0x200000fc 8000580: 40012400 .word 0x40012400 08000584 : * @brief TIM14 Initialization Function * @param None * @retval None */ static void MX_TIM14_Init(void) { 8000584: b580 push {r7, lr} 8000586: af00 add r7, sp, #0 /* USER CODE END TIM14_Init 0 */ /* USER CODE BEGIN TIM14_Init 1 */ /* USER CODE END TIM14_Init 1 */ htim14.Instance = TIM14; 8000588: 4b0e ldr r3, [pc, #56] ; (80005c4 ) 800058a: 4a0f ldr r2, [pc, #60] ; (80005c8 ) 800058c: 601a str r2, [r3, #0] htim14.Init.Prescaler = 48-1; 800058e: 4b0d ldr r3, [pc, #52] ; (80005c4 ) 8000590: 222f movs r2, #47 ; 0x2f 8000592: 605a str r2, [r3, #4] htim14.Init.CounterMode = TIM_COUNTERMODE_UP; 8000594: 4b0b ldr r3, [pc, #44] ; (80005c4 ) 8000596: 2200 movs r2, #0 8000598: 609a str r2, [r3, #8] htim14.Init.Period = 100-1; 800059a: 4b0a ldr r3, [pc, #40] ; (80005c4 ) 800059c: 2263 movs r2, #99 ; 0x63 800059e: 60da str r2, [r3, #12] htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80005a0: 4b08 ldr r3, [pc, #32] ; (80005c4 ) 80005a2: 2200 movs r2, #0 80005a4: 611a str r2, [r3, #16] htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80005a6: 4b07 ldr r3, [pc, #28] ; (80005c4 ) 80005a8: 2200 movs r2, #0 80005aa: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim14) != HAL_OK) 80005ac: 4b05 ldr r3, [pc, #20] ; (80005c4 ) 80005ae: 0018 movs r0, r3 80005b0: f001 fdc8 bl 8002144 80005b4: 1e03 subs r3, r0, #0 80005b6: d001 beq.n 80005bc { Error_Handler(); 80005b8: f000 f8cc bl 8000754 } /* USER CODE BEGIN TIM14_Init 2 */ /* USER CODE END TIM14_Init 2 */ } 80005bc: 46c0 nop ; (mov r8, r8) 80005be: 46bd mov sp, r7 80005c0: bd80 pop {r7, pc} 80005c2: 46c0 nop ; (mov r8, r8) 80005c4: 200000b4 .word 0x200000b4 80005c8: 40002000 .word 0x40002000 080005cc : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80005cc: b590 push {r4, r7, lr} 80005ce: b089 sub sp, #36 ; 0x24 80005d0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80005d2: 240c movs r4, #12 80005d4: 193b adds r3, r7, r4 80005d6: 0018 movs r0, r3 80005d8: 2314 movs r3, #20 80005da: 001a movs r2, r3 80005dc: 2100 movs r1, #0 80005de: f003 fb3d bl 8003c5c /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80005e2: 4b58 ldr r3, [pc, #352] ; (8000744 ) 80005e4: 695a ldr r2, [r3, #20] 80005e6: 4b57 ldr r3, [pc, #348] ; (8000744 ) 80005e8: 2180 movs r1, #128 ; 0x80 80005ea: 03c9 lsls r1, r1, #15 80005ec: 430a orrs r2, r1 80005ee: 615a str r2, [r3, #20] 80005f0: 4b54 ldr r3, [pc, #336] ; (8000744 ) 80005f2: 695a ldr r2, [r3, #20] 80005f4: 2380 movs r3, #128 ; 0x80 80005f6: 03db lsls r3, r3, #15 80005f8: 4013 ands r3, r2 80005fa: 60bb str r3, [r7, #8] 80005fc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80005fe: 4b51 ldr r3, [pc, #324] ; (8000744 ) 8000600: 695a ldr r2, [r3, #20] 8000602: 4b50 ldr r3, [pc, #320] ; (8000744 ) 8000604: 2180 movs r1, #128 ; 0x80 8000606: 0289 lsls r1, r1, #10 8000608: 430a orrs r2, r1 800060a: 615a str r2, [r3, #20] 800060c: 4b4d ldr r3, [pc, #308] ; (8000744 ) 800060e: 695a ldr r2, [r3, #20] 8000610: 2380 movs r3, #128 ; 0x80 8000612: 029b lsls r3, r3, #10 8000614: 4013 ands r3, r2 8000616: 607b str r3, [r7, #4] 8000618: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 800061a: 4b4a ldr r3, [pc, #296] ; (8000744 ) 800061c: 695a ldr r2, [r3, #20] 800061e: 4b49 ldr r3, [pc, #292] ; (8000744 ) 8000620: 2180 movs r1, #128 ; 0x80 8000622: 02c9 lsls r1, r1, #11 8000624: 430a orrs r2, r1 8000626: 615a str r2, [r3, #20] 8000628: 4b46 ldr r3, [pc, #280] ; (8000744 ) 800062a: 695a ldr r2, [r3, #20] 800062c: 2380 movs r3, #128 ; 0x80 800062e: 02db lsls r3, r3, #11 8000630: 4013 ands r3, r2 8000632: 603b str r3, [r7, #0] 8000634: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin 8000636: 4944 ldr r1, [pc, #272] ; (8000748 ) 8000638: 2390 movs r3, #144 ; 0x90 800063a: 05db lsls r3, r3, #23 800063c: 2200 movs r2, #0 800063e: 0018 movs r0, r3 8000640: f001 f8fb bl 800183a |HC595_SLK2_Pin|iic_scl_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(iic_sda_GPIO_Port, iic_sda_Pin, GPIO_PIN_RESET); 8000644: 4b41 ldr r3, [pc, #260] ; (800074c ) 8000646: 2200 movs r2, #0 8000648: 2102 movs r1, #2 800064a: 0018 movs r0, r3 800064c: f001 f8f5 bl 800183a /*Configure GPIO pins : MOT_IN1_Pin MOT_IN2_Pin */ GPIO_InitStruct.Pin = MOT_IN1_Pin|MOT_IN2_Pin; 8000650: 193b adds r3, r7, r4 8000652: 2203 movs r2, #3 8000654: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000656: 193b adds r3, r7, r4 8000658: 2200 movs r2, #0 800065a: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800065c: 193b adds r3, r7, r4 800065e: 2202 movs r2, #2 8000660: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8000662: 193b adds r3, r7, r4 8000664: 4a3a ldr r2, [pc, #232] ; (8000750 ) 8000666: 0019 movs r1, r3 8000668: 0010 movs r0, r2 800066a: f000 ff59 bl 8001520 /*Configure GPIO pins : U_T_Pin HC595_DLK_Pin HC595_SLK_Pin HC595_RLK_Pin HC595_SLK2_Pin */ GPIO_InitStruct.Pin = U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin 800066e: 0021 movs r1, r4 8000670: 187b adds r3, r7, r1 8000672: 22b9 movs r2, #185 ; 0xb9 8000674: 0092 lsls r2, r2, #2 8000676: 601a str r2, [r3, #0] |HC595_SLK2_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000678: 000c movs r4, r1 800067a: 193b adds r3, r7, r4 800067c: 2201 movs r2, #1 800067e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 8000680: 193b adds r3, r7, r4 8000682: 2202 movs r2, #2 8000684: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000686: 193b adds r3, r7, r4 8000688: 2203 movs r2, #3 800068a: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800068c: 193a adds r2, r7, r4 800068e: 2390 movs r3, #144 ; 0x90 8000690: 05db lsls r3, r3, #23 8000692: 0011 movs r1, r2 8000694: 0018 movs r0, r3 8000696: f000 ff43 bl 8001520 /*Configure GPIO pin : infeaed_Pin */ GPIO_InitStruct.Pin = infeaed_Pin; 800069a: 193b adds r3, r7, r4 800069c: 2208 movs r2, #8 800069e: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80006a0: 193b adds r3, r7, r4 80006a2: 22c4 movs r2, #196 ; 0xc4 80006a4: 0392 lsls r2, r2, #14 80006a6: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006a8: 193b adds r3, r7, r4 80006aa: 2201 movs r2, #1 80006ac: 609a str r2, [r3, #8] HAL_GPIO_Init(infeaed_GPIO_Port, &GPIO_InitStruct); 80006ae: 193a adds r2, r7, r4 80006b0: 2390 movs r3, #144 ; 0x90 80006b2: 05db lsls r3, r3, #23 80006b4: 0011 movs r1, r2 80006b6: 0018 movs r0, r3 80006b8: f000 ff32 bl 8001520 /*Configure GPIO pin : I_R_Pin */ GPIO_InitStruct.Pin = I_R_Pin; 80006bc: 193b adds r3, r7, r4 80006be: 2210 movs r2, #16 80006c0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006c2: 193b adds r3, r7, r4 80006c4: 2200 movs r2, #0 80006c6: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006c8: 193b adds r3, r7, r4 80006ca: 2202 movs r2, #2 80006cc: 609a str r2, [r3, #8] HAL_GPIO_Init(I_R_GPIO_Port, &GPIO_InitStruct); 80006ce: 193a adds r2, r7, r4 80006d0: 2390 movs r3, #144 ; 0x90 80006d2: 05db lsls r3, r3, #23 80006d4: 0011 movs r1, r2 80006d6: 0018 movs r0, r3 80006d8: f000 ff22 bl 8001520 /*Configure GPIO pin : iic_sda_Pin */ GPIO_InitStruct.Pin = iic_sda_Pin; 80006dc: 193b adds r3, r7, r4 80006de: 2202 movs r2, #2 80006e0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006e2: 193b adds r3, r7, r4 80006e4: 2201 movs r2, #1 80006e6: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006e8: 193b adds r3, r7, r4 80006ea: 2200 movs r2, #0 80006ec: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006ee: 193b adds r3, r7, r4 80006f0: 2200 movs r2, #0 80006f2: 60da str r2, [r3, #12] HAL_GPIO_Init(iic_sda_GPIO_Port, &GPIO_InitStruct); 80006f4: 193b adds r3, r7, r4 80006f6: 4a15 ldr r2, [pc, #84] ; (800074c ) 80006f8: 0019 movs r1, r3 80006fa: 0010 movs r0, r2 80006fc: f000 ff10 bl 8001520 /*Configure GPIO pin : iic_scl_Pin */ GPIO_InitStruct.Pin = iic_scl_Pin; 8000700: 0021 movs r1, r4 8000702: 187b adds r3, r7, r1 8000704: 2280 movs r2, #128 ; 0x80 8000706: 00d2 lsls r2, r2, #3 8000708: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070a: 187b adds r3, r7, r1 800070c: 2201 movs r2, #1 800070e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 187b adds r3, r7, r1 8000712: 2200 movs r2, #0 8000714: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000716: 187b adds r3, r7, r1 8000718: 2200 movs r2, #0 800071a: 60da str r2, [r3, #12] HAL_GPIO_Init(iic_scl_GPIO_Port, &GPIO_InitStruct); 800071c: 187a adds r2, r7, r1 800071e: 2390 movs r3, #144 ; 0x90 8000720: 05db lsls r3, r3, #23 8000722: 0011 movs r1, r2 8000724: 0018 movs r0, r3 8000726: f000 fefb bl 8001520 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI2_3_IRQn, 0, 0); 800072a: 2200 movs r2, #0 800072c: 2100 movs r1, #0 800072e: 2006 movs r0, #6 8000730: f000 fec4 bl 80014bc HAL_NVIC_EnableIRQ(EXTI2_3_IRQn); 8000734: 2006 movs r0, #6 8000736: f000 fed6 bl 80014e6 } 800073a: 46c0 nop ; (mov r8, r8) 800073c: 46bd mov sp, r7 800073e: b009 add sp, #36 ; 0x24 8000740: bd90 pop {r4, r7, pc} 8000742: 46c0 nop ; (mov r8, r8) 8000744: 40021000 .word 0x40021000 8000748: 000006e4 .word 0x000006e4 800074c: 48000400 .word 0x48000400 8000750: 48001400 .word 0x48001400 08000754 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000754: b580 push {r7, lr} 8000756: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000758: b672 cpsid i } 800075a: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800075c: e7fe b.n 800075c ... 08000760 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000760: b580 push {r7, lr} 8000762: b082 sub sp, #8 8000764: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000766: 4b0f ldr r3, [pc, #60] ; (80007a4 ) 8000768: 699a ldr r2, [r3, #24] 800076a: 4b0e ldr r3, [pc, #56] ; (80007a4 ) 800076c: 2101 movs r1, #1 800076e: 430a orrs r2, r1 8000770: 619a str r2, [r3, #24] 8000772: 4b0c ldr r3, [pc, #48] ; (80007a4 ) 8000774: 699b ldr r3, [r3, #24] 8000776: 2201 movs r2, #1 8000778: 4013 ands r3, r2 800077a: 607b str r3, [r7, #4] 800077c: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 800077e: 4b09 ldr r3, [pc, #36] ; (80007a4 ) 8000780: 69da ldr r2, [r3, #28] 8000782: 4b08 ldr r3, [pc, #32] ; (80007a4 ) 8000784: 2180 movs r1, #128 ; 0x80 8000786: 0549 lsls r1, r1, #21 8000788: 430a orrs r2, r1 800078a: 61da str r2, [r3, #28] 800078c: 4b05 ldr r3, [pc, #20] ; (80007a4 ) 800078e: 69da ldr r2, [r3, #28] 8000790: 2380 movs r3, #128 ; 0x80 8000792: 055b lsls r3, r3, #21 8000794: 4013 ands r3, r2 8000796: 603b str r3, [r7, #0] 8000798: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800079a: 46c0 nop ; (mov r8, r8) 800079c: 46bd mov sp, r7 800079e: b002 add sp, #8 80007a0: bd80 pop {r7, pc} 80007a2: 46c0 nop ; (mov r8, r8) 80007a4: 40021000 .word 0x40021000 080007a8 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 80007a8: b590 push {r4, r7, lr} 80007aa: b08b sub sp, #44 ; 0x2c 80007ac: af00 add r7, sp, #0 80007ae: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007b0: 2414 movs r4, #20 80007b2: 193b adds r3, r7, r4 80007b4: 0018 movs r0, r3 80007b6: 2314 movs r3, #20 80007b8: 001a movs r2, r3 80007ba: 2100 movs r1, #0 80007bc: f003 fa4e bl 8003c5c if(hadc->Instance==ADC1) 80007c0: 687b ldr r3, [r7, #4] 80007c2: 681b ldr r3, [r3, #0] 80007c4: 4a19 ldr r2, [pc, #100] ; (800082c ) 80007c6: 4293 cmp r3, r2 80007c8: d12b bne.n 8000822 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80007ca: 4b19 ldr r3, [pc, #100] ; (8000830 ) 80007cc: 699a ldr r2, [r3, #24] 80007ce: 4b18 ldr r3, [pc, #96] ; (8000830 ) 80007d0: 2180 movs r1, #128 ; 0x80 80007d2: 0089 lsls r1, r1, #2 80007d4: 430a orrs r2, r1 80007d6: 619a str r2, [r3, #24] 80007d8: 4b15 ldr r3, [pc, #84] ; (8000830 ) 80007da: 699a ldr r2, [r3, #24] 80007dc: 2380 movs r3, #128 ; 0x80 80007de: 009b lsls r3, r3, #2 80007e0: 4013 ands r3, r2 80007e2: 613b str r3, [r7, #16] 80007e4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80007e6: 4b12 ldr r3, [pc, #72] ; (8000830 ) 80007e8: 695a ldr r2, [r3, #20] 80007ea: 4b11 ldr r3, [pc, #68] ; (8000830 ) 80007ec: 2180 movs r1, #128 ; 0x80 80007ee: 0289 lsls r1, r1, #10 80007f0: 430a orrs r2, r1 80007f2: 615a str r2, [r3, #20] 80007f4: 4b0e ldr r3, [pc, #56] ; (8000830 ) 80007f6: 695a ldr r2, [r3, #20] 80007f8: 2380 movs r3, #128 ; 0x80 80007fa: 029b lsls r3, r3, #10 80007fc: 4013 ands r3, r2 80007fe: 60fb str r3, [r7, #12] 8000800: 68fb ldr r3, [r7, #12] /**ADC GPIO Configuration PA0 ------> ADC_IN0 PA1 ------> ADC_IN1 */ GPIO_InitStruct.Pin = ADC_CH0_Pin|ADC_CH1_Pin; 8000802: 193b adds r3, r7, r4 8000804: 2203 movs r2, #3 8000806: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000808: 193b adds r3, r7, r4 800080a: 2203 movs r2, #3 800080c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 800080e: 193b adds r3, r7, r4 8000810: 2200 movs r2, #0 8000812: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000814: 193a adds r2, r7, r4 8000816: 2390 movs r3, #144 ; 0x90 8000818: 05db lsls r3, r3, #23 800081a: 0011 movs r1, r2 800081c: 0018 movs r0, r3 800081e: f000 fe7f bl 8001520 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8000822: 46c0 nop ; (mov r8, r8) 8000824: 46bd mov sp, r7 8000826: b00b add sp, #44 ; 0x2c 8000828: bd90 pop {r4, r7, pc} 800082a: 46c0 nop ; (mov r8, r8) 800082c: 40012400 .word 0x40012400 8000830: 40021000 .word 0x40021000 08000834 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8000834: b580 push {r7, lr} 8000836: b084 sub sp, #16 8000838: af00 add r7, sp, #0 800083a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM14) 800083c: 687b ldr r3, [r7, #4] 800083e: 681b ldr r3, [r3, #0] 8000840: 4a0e ldr r2, [pc, #56] ; (800087c ) 8000842: 4293 cmp r3, r2 8000844: d115 bne.n 8000872 { /* USER CODE BEGIN TIM14_MspInit 0 */ /* USER CODE END TIM14_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM14_CLK_ENABLE(); 8000846: 4b0e ldr r3, [pc, #56] ; (8000880 ) 8000848: 69da ldr r2, [r3, #28] 800084a: 4b0d ldr r3, [pc, #52] ; (8000880 ) 800084c: 2180 movs r1, #128 ; 0x80 800084e: 0049 lsls r1, r1, #1 8000850: 430a orrs r2, r1 8000852: 61da str r2, [r3, #28] 8000854: 4b0a ldr r3, [pc, #40] ; (8000880 ) 8000856: 69da ldr r2, [r3, #28] 8000858: 2380 movs r3, #128 ; 0x80 800085a: 005b lsls r3, r3, #1 800085c: 4013 ands r3, r2 800085e: 60fb str r3, [r7, #12] 8000860: 68fb ldr r3, [r7, #12] /* TIM14 interrupt Init */ HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0); 8000862: 2200 movs r2, #0 8000864: 2100 movs r1, #0 8000866: 2013 movs r0, #19 8000868: f000 fe28 bl 80014bc HAL_NVIC_EnableIRQ(TIM14_IRQn); 800086c: 2013 movs r0, #19 800086e: f000 fe3a bl 80014e6 /* USER CODE BEGIN TIM14_MspInit 1 */ /* USER CODE END TIM14_MspInit 1 */ } } 8000872: 46c0 nop ; (mov r8, r8) 8000874: 46bd mov sp, r7 8000876: b004 add sp, #16 8000878: bd80 pop {r7, pc} 800087a: 46c0 nop ; (mov r8, r8) 800087c: 40002000 .word 0x40002000 8000880: 40021000 .word 0x40021000 08000884 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000884: b580 push {r7, lr} 8000886: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000888: e7fe b.n 8000888 0800088a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800088a: b580 push {r7, lr} 800088c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800088e: e7fe b.n 800088e 08000890 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000890: b580 push {r7, lr} 8000892: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 8000894: 46c0 nop ; (mov r8, r8) 8000896: 46bd mov sp, r7 8000898: bd80 pop {r7, pc} 0800089a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800089a: b580 push {r7, lr} 800089c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800089e: 46c0 nop ; (mov r8, r8) 80008a0: 46bd mov sp, r7 80008a2: bd80 pop {r7, pc} 080008a4 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80008a4: b580 push {r7, lr} 80008a6: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80008a8: f000 f890 bl 80009cc /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80008ac: 46c0 nop ; (mov r8, r8) 80008ae: 46bd mov sp, r7 80008b0: bd80 pop {r7, pc} 080008b2 : /** * @brief This function handles EXTI line 2 and 3 interrupts. */ void EXTI2_3_IRQHandler(void) { 80008b2: b580 push {r7, lr} 80008b4: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI2_3_IRQn 0 */ /* USER CODE END EXTI2_3_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); 80008b6: 2008 movs r0, #8 80008b8: f000 ffdc bl 8001874 /* USER CODE BEGIN EXTI2_3_IRQn 1 */ /* USER CODE END EXTI2_3_IRQn 1 */ } 80008bc: 46c0 nop ; (mov r8, r8) 80008be: 46bd mov sp, r7 80008c0: bd80 pop {r7, pc} ... 080008c4 : /** * @brief This function handles TIM14 global interrupt. */ void TIM14_IRQHandler(void) { 80008c4: b580 push {r7, lr} 80008c6: af00 add r7, sp, #0 /* USER CODE BEGIN TIM14_IRQn 0 */ /* USER CODE END TIM14_IRQn 0 */ HAL_TIM_IRQHandler(&htim14); 80008c8: 4b03 ldr r3, [pc, #12] ; (80008d8 ) 80008ca: 0018 movs r0, r3 80008cc: f001 fcd0 bl 8002270 /* USER CODE BEGIN TIM14_IRQn 1 */ /* USER CODE END TIM14_IRQn 1 */ } 80008d0: 46c0 nop ; (mov r8, r8) 80008d2: 46bd mov sp, r7 80008d4: bd80 pop {r7, pc} 80008d6: 46c0 nop ; (mov r8, r8) 80008d8: 200000b4 .word 0x200000b4 080008dc : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 80008dc: b580 push {r7, lr} 80008de: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 80008e0: 46c0 nop ; (mov r8, r8) 80008e2: 46bd mov sp, r7 80008e4: bd80 pop {r7, pc} ... 080008e8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80008e8: 480d ldr r0, [pc, #52] ; (8000920 ) mov sp, r0 /* set stack pointer */ 80008ea: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80008ec: 480d ldr r0, [pc, #52] ; (8000924 ) ldr r1, =_edata 80008ee: 490e ldr r1, [pc, #56] ; (8000928 ) ldr r2, =_sidata 80008f0: 4a0e ldr r2, [pc, #56] ; (800092c ) movs r3, #0 80008f2: 2300 movs r3, #0 b LoopCopyDataInit 80008f4: e002 b.n 80008fc 080008f6 : CopyDataInit: ldr r4, [r2, r3] 80008f6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80008f8: 50c4 str r4, [r0, r3] adds r3, r3, #4 80008fa: 3304 adds r3, #4 080008fc : LoopCopyDataInit: adds r4, r0, r3 80008fc: 18c4 adds r4, r0, r3 cmp r4, r1 80008fe: 428c cmp r4, r1 bcc CopyDataInit 8000900: d3f9 bcc.n 80008f6 /* Zero fill the bss segment. */ ldr r2, =_sbss 8000902: 4a0b ldr r2, [pc, #44] ; (8000930 ) ldr r4, =_ebss 8000904: 4c0b ldr r4, [pc, #44] ; (8000934 ) movs r3, #0 8000906: 2300 movs r3, #0 b LoopFillZerobss 8000908: e001 b.n 800090e 0800090a : FillZerobss: str r3, [r2] 800090a: 6013 str r3, [r2, #0] adds r2, r2, #4 800090c: 3204 adds r2, #4 0800090e : LoopFillZerobss: cmp r2, r4 800090e: 42a2 cmp r2, r4 bcc FillZerobss 8000910: d3fb bcc.n 800090a /* Call the clock system intitialization function.*/ bl SystemInit 8000912: f7ff ffe3 bl 80008dc /* Call static constructors */ bl __libc_init_array 8000916: f003 f973 bl 8003c00 <__libc_init_array> /* Call the application's entry point.*/ bl main 800091a: f7ff fd6b bl 80003f4
0800091e : LoopForever: b LoopForever 800091e: e7fe b.n 800091e ldr r0, =_estack 8000920: 20001000 .word 0x20001000 ldr r0, =_sdata 8000924: 20000000 .word 0x20000000 ldr r1, =_edata 8000928: 20000070 .word 0x20000070 ldr r2, =_sidata 800092c: 08003da4 .word 0x08003da4 ldr r2, =_sbss 8000930: 20000070 .word 0x20000070 ldr r4, =_ebss 8000934: 200001e8 .word 0x200001e8 08000938 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000938: e7fe b.n 8000938 ... 0800093c : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800093c: b580 push {r7, lr} 800093e: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000940: 4b07 ldr r3, [pc, #28] ; (8000960 ) 8000942: 681a ldr r2, [r3, #0] 8000944: 4b06 ldr r3, [pc, #24] ; (8000960 ) 8000946: 2110 movs r1, #16 8000948: 430a orrs r2, r1 800094a: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800094c: 2003 movs r0, #3 800094e: f000 f809 bl 8000964 /* Init the low level hardware */ HAL_MspInit(); 8000952: f7ff ff05 bl 8000760 /* Return function status */ return HAL_OK; 8000956: 2300 movs r3, #0 } 8000958: 0018 movs r0, r3 800095a: 46bd mov sp, r7 800095c: bd80 pop {r7, pc} 800095e: 46c0 nop ; (mov r8, r8) 8000960: 40022000 .word 0x40022000 08000964 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000964: b590 push {r4, r7, lr} 8000966: b083 sub sp, #12 8000968: af00 add r7, sp, #0 800096a: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800096c: 4b14 ldr r3, [pc, #80] ; (80009c0 ) 800096e: 681c ldr r4, [r3, #0] 8000970: 4b14 ldr r3, [pc, #80] ; (80009c4 ) 8000972: 781b ldrb r3, [r3, #0] 8000974: 0019 movs r1, r3 8000976: 23fa movs r3, #250 ; 0xfa 8000978: 0098 lsls r0, r3, #2 800097a: f7ff fbc5 bl 8000108 <__udivsi3> 800097e: 0003 movs r3, r0 8000980: 0019 movs r1, r3 8000982: 0020 movs r0, r4 8000984: f7ff fbc0 bl 8000108 <__udivsi3> 8000988: 0003 movs r3, r0 800098a: 0018 movs r0, r3 800098c: f000 fdbb bl 8001506 8000990: 1e03 subs r3, r0, #0 8000992: d001 beq.n 8000998 { return HAL_ERROR; 8000994: 2301 movs r3, #1 8000996: e00f b.n 80009b8 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000998: 687b ldr r3, [r7, #4] 800099a: 2b03 cmp r3, #3 800099c: d80b bhi.n 80009b6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800099e: 6879 ldr r1, [r7, #4] 80009a0: 2301 movs r3, #1 80009a2: 425b negs r3, r3 80009a4: 2200 movs r2, #0 80009a6: 0018 movs r0, r3 80009a8: f000 fd88 bl 80014bc uwTickPrio = TickPriority; 80009ac: 4b06 ldr r3, [pc, #24] ; (80009c8 ) 80009ae: 687a ldr r2, [r7, #4] 80009b0: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80009b2: 2300 movs r3, #0 80009b4: e000 b.n 80009b8 return HAL_ERROR; 80009b6: 2301 movs r3, #1 } 80009b8: 0018 movs r0, r3 80009ba: 46bd mov sp, r7 80009bc: b003 add sp, #12 80009be: bd90 pop {r4, r7, pc} 80009c0: 20000000 .word 0x20000000 80009c4: 20000008 .word 0x20000008 80009c8: 20000004 .word 0x20000004 080009cc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80009cc: b580 push {r7, lr} 80009ce: af00 add r7, sp, #0 uwTick += uwTickFreq; 80009d0: 4b05 ldr r3, [pc, #20] ; (80009e8 ) 80009d2: 781b ldrb r3, [r3, #0] 80009d4: 001a movs r2, r3 80009d6: 4b05 ldr r3, [pc, #20] ; (80009ec ) 80009d8: 681b ldr r3, [r3, #0] 80009da: 18d2 adds r2, r2, r3 80009dc: 4b03 ldr r3, [pc, #12] ; (80009ec ) 80009de: 601a str r2, [r3, #0] } 80009e0: 46c0 nop ; (mov r8, r8) 80009e2: 46bd mov sp, r7 80009e4: bd80 pop {r7, pc} 80009e6: 46c0 nop ; (mov r8, r8) 80009e8: 20000008 .word 0x20000008 80009ec: 2000013c .word 0x2000013c 080009f0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80009f0: b580 push {r7, lr} 80009f2: af00 add r7, sp, #0 return uwTick; 80009f4: 4b02 ldr r3, [pc, #8] ; (8000a00 ) 80009f6: 681b ldr r3, [r3, #0] } 80009f8: 0018 movs r0, r3 80009fa: 46bd mov sp, r7 80009fc: bd80 pop {r7, pc} 80009fe: 46c0 nop ; (mov r8, r8) 8000a00: 2000013c .word 0x2000013c 08000a04 : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8000a04: b580 push {r7, lr} 8000a06: b084 sub sp, #16 8000a08: af00 add r7, sp, #0 8000a0a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000a0c: 230f movs r3, #15 8000a0e: 18fb adds r3, r7, r3 8000a10: 2200 movs r2, #0 8000a12: 701a strb r2, [r3, #0] uint32_t tmpCFGR1 = 0U; 8000a14: 2300 movs r3, #0 8000a16: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) 8000a18: 687b ldr r3, [r7, #4] 8000a1a: 2b00 cmp r3, #0 8000a1c: d101 bne.n 8000a22 { return HAL_ERROR; 8000a1e: 2301 movs r3, #1 8000a20: e125 b.n 8000c6e /* Refer to header of this file for more details on clock enabling procedure*/ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) 8000a22: 687b ldr r3, [r7, #4] 8000a24: 6b9b ldr r3, [r3, #56] ; 0x38 8000a26: 2b00 cmp r3, #0 8000a28: d10a bne.n 8000a40 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8000a2a: 687b ldr r3, [r7, #4] 8000a2c: 2200 movs r2, #0 8000a2e: 63da str r2, [r3, #60] ; 0x3c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8000a30: 687b ldr r3, [r7, #4] 8000a32: 2234 movs r2, #52 ; 0x34 8000a34: 2100 movs r1, #0 8000a36: 5499 strb r1, [r3, r2] /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8000a38: 687b ldr r3, [r7, #4] 8000a3a: 0018 movs r0, r3 8000a3c: f7ff feb4 bl 80007a8 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ /* and if there is no conversion on going on regular group (ADC can be */ /* enabled anyway, in case of call of this function to update a parameter */ /* on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8000a40: 687b ldr r3, [r7, #4] 8000a42: 6b9b ldr r3, [r3, #56] ; 0x38 8000a44: 2210 movs r2, #16 8000a46: 4013 ands r3, r2 8000a48: d000 beq.n 8000a4c 8000a4a: e103 b.n 8000c54 8000a4c: 230f movs r3, #15 8000a4e: 18fb adds r3, r7, r3 8000a50: 781b ldrb r3, [r3, #0] 8000a52: 2b00 cmp r3, #0 8000a54: d000 beq.n 8000a58 8000a56: e0fd b.n 8000c54 (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 8000a58: 687b ldr r3, [r7, #4] 8000a5a: 681b ldr r3, [r3, #0] 8000a5c: 689b ldr r3, [r3, #8] 8000a5e: 2204 movs r2, #4 8000a60: 4013 ands r3, r2 (tmp_hal_status == HAL_OK) && 8000a62: d000 beq.n 8000a66 8000a64: e0f6 b.n 8000c54 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000a66: 687b ldr r3, [r7, #4] 8000a68: 6b9b ldr r3, [r3, #56] ; 0x38 8000a6a: 4a83 ldr r2, [pc, #524] ; (8000c78 ) 8000a6c: 4013 ands r3, r2 8000a6e: 2202 movs r2, #2 8000a70: 431a orrs r2, r3 8000a72: 687b ldr r3, [r7, #4] 8000a74: 639a str r2, [r3, #56] ; 0x38 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - ADC clock mode */ /* - ADC clock prescaler */ /* - ADC resolution */ if (ADC_IS_ENABLE(hadc) == RESET) 8000a76: 687b ldr r3, [r7, #4] 8000a78: 681b ldr r3, [r3, #0] 8000a7a: 689b ldr r3, [r3, #8] 8000a7c: 2203 movs r2, #3 8000a7e: 4013 ands r3, r2 8000a80: 2b01 cmp r3, #1 8000a82: d112 bne.n 8000aaa 8000a84: 687b ldr r3, [r7, #4] 8000a86: 681b ldr r3, [r3, #0] 8000a88: 681b ldr r3, [r3, #0] 8000a8a: 2201 movs r2, #1 8000a8c: 4013 ands r3, r2 8000a8e: 2b01 cmp r3, #1 8000a90: d009 beq.n 8000aa6 8000a92: 687b ldr r3, [r7, #4] 8000a94: 681b ldr r3, [r3, #0] 8000a96: 68da ldr r2, [r3, #12] 8000a98: 2380 movs r3, #128 ; 0x80 8000a9a: 021b lsls r3, r3, #8 8000a9c: 401a ands r2, r3 8000a9e: 2380 movs r3, #128 ; 0x80 8000aa0: 021b lsls r3, r3, #8 8000aa2: 429a cmp r2, r3 8000aa4: d101 bne.n 8000aaa 8000aa6: 2301 movs r3, #1 8000aa8: e000 b.n 8000aac 8000aaa: 2300 movs r3, #0 8000aac: 2b00 cmp r3, #0 8000aae: d116 bne.n 8000ade /* parameters): */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ MODIFY_REG(hadc->Instance->CFGR1, 8000ab0: 687b ldr r3, [r7, #4] 8000ab2: 681b ldr r3, [r3, #0] 8000ab4: 68db ldr r3, [r3, #12] 8000ab6: 2218 movs r2, #24 8000ab8: 4393 bics r3, r2 8000aba: 0019 movs r1, r3 8000abc: 687b ldr r3, [r7, #4] 8000abe: 689a ldr r2, [r3, #8] 8000ac0: 687b ldr r3, [r7, #4] 8000ac2: 681b ldr r3, [r3, #0] 8000ac4: 430a orrs r2, r1 8000ac6: 60da str r2, [r3, #12] ADC_CFGR1_RES , hadc->Init.Resolution ); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler */ MODIFY_REG(hadc->Instance->CFGR2 , 8000ac8: 687b ldr r3, [r7, #4] 8000aca: 681b ldr r3, [r3, #0] 8000acc: 691b ldr r3, [r3, #16] 8000ace: 009b lsls r3, r3, #2 8000ad0: 0899 lsrs r1, r3, #2 8000ad2: 687b ldr r3, [r7, #4] 8000ad4: 685a ldr r2, [r3, #4] 8000ad6: 687b ldr r3, [r7, #4] 8000ad8: 681b ldr r3, [r3, #0] 8000ada: 430a orrs r2, r1 8000adc: 611a str r2, [r3, #16] /* - external trigger polarity */ /* - data alignment */ /* - resolution */ /* - scan direction */ /* - DMA continuous request */ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | 8000ade: 687b ldr r3, [r7, #4] 8000ae0: 681b ldr r3, [r3, #0] 8000ae2: 68da ldr r2, [r3, #12] 8000ae4: 687b ldr r3, [r7, #4] 8000ae6: 681b ldr r3, [r3, #0] 8000ae8: 4964 ldr r1, [pc, #400] ; (8000c7c ) 8000aea: 400a ands r2, r1 8000aec: 60da str r2, [r3, #12] ADC_CFGR1_EXTEN | ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG ); tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000aee: 687b ldr r3, [r7, #4] 8000af0: 7e1b ldrb r3, [r3, #24] 8000af2: 039a lsls r2, r3, #14 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000af4: 687b ldr r3, [r7, #4] 8000af6: 7e5b ldrb r3, [r3, #25] 8000af8: 03db lsls r3, r3, #15 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000afa: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000afc: 687b ldr r3, [r7, #4] 8000afe: 7e9b ldrb r3, [r3, #26] 8000b00: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b02: 431a orrs r2, r3 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b04: 687b ldr r3, [r7, #4] 8000b06: 6a9b ldr r3, [r3, #40] ; 0x28 8000b08: 2b01 cmp r3, #1 8000b0a: d002 beq.n 8000b12 8000b0c: 2380 movs r3, #128 ; 0x80 8000b0e: 015b lsls r3, r3, #5 8000b10: e000 b.n 8000b14 8000b12: 2300 movs r3, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b14: 431a orrs r2, r3 hadc->Init.DataAlign | 8000b16: 687b ldr r3, [r7, #4] 8000b18: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b1a: 431a orrs r2, r3 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b1c: 687b ldr r3, [r7, #4] 8000b1e: 691b ldr r3, [r3, #16] 8000b20: 2b02 cmp r3, #2 8000b22: d101 bne.n 8000b28 8000b24: 2304 movs r3, #4 8000b26: e000 b.n 8000b2a 8000b28: 2300 movs r3, #0 hadc->Init.DataAlign | 8000b2a: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); 8000b2c: 687b ldr r3, [r7, #4] 8000b2e: 2124 movs r1, #36 ; 0x24 8000b30: 5c5b ldrb r3, [r3, r1] 8000b32: 005b lsls r3, r3, #1 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b34: 4313 orrs r3, r2 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b36: 68ba ldr r2, [r7, #8] 8000b38: 4313 orrs r3, r2 8000b3a: 60bb str r3, [r7, #8] /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8000b3c: 687b ldr r3, [r7, #4] 8000b3e: 7edb ldrb r3, [r3, #27] 8000b40: 2b01 cmp r3, #1 8000b42: d115 bne.n 8000b70 { if (hadc->Init.ContinuousConvMode == DISABLE) 8000b44: 687b ldr r3, [r7, #4] 8000b46: 7e9b ldrb r3, [r3, #26] 8000b48: 2b00 cmp r3, #0 8000b4a: d105 bne.n 8000b58 { /* Enable the selected ADC group regular discontinuous mode */ tmpCFGR1 |= ADC_CFGR1_DISCEN; 8000b4c: 68bb ldr r3, [r7, #8] 8000b4e: 2280 movs r2, #128 ; 0x80 8000b50: 0252 lsls r2, r2, #9 8000b52: 4313 orrs r3, r2 8000b54: 60bb str r3, [r7, #8] 8000b56: e00b b.n 8000b70 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000b58: 687b ldr r3, [r7, #4] 8000b5a: 6b9b ldr r3, [r3, #56] ; 0x38 8000b5c: 2220 movs r2, #32 8000b5e: 431a orrs r2, r3 8000b60: 687b ldr r3, [r7, #4] 8000b62: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000b64: 687b ldr r3, [r7, #4] 8000b66: 6bdb ldr r3, [r3, #60] ; 0x3c 8000b68: 2201 movs r2, #1 8000b6a: 431a orrs r2, r3 8000b6c: 687b ldr r3, [r7, #4] 8000b6e: 63da str r2, [r3, #60] ; 0x3c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8000b70: 687b ldr r3, [r7, #4] 8000b72: 69da ldr r2, [r3, #28] 8000b74: 23c2 movs r3, #194 ; 0xc2 8000b76: 33ff adds r3, #255 ; 0xff 8000b78: 429a cmp r2, r3 8000b7a: d007 beq.n 8000b8c { tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000b7c: 687b ldr r3, [r7, #4] 8000b7e: 69da ldr r2, [r3, #28] hadc->Init.ExternalTrigConvEdge ); 8000b80: 687b ldr r3, [r7, #4] 8000b82: 6a1b ldr r3, [r3, #32] tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000b84: 4313 orrs r3, r2 8000b86: 68ba ldr r2, [r7, #8] 8000b88: 4313 orrs r3, r2 8000b8a: 60bb str r3, [r7, #8] } /* Update ADC configuration register with previous settings */ hadc->Instance->CFGR1 |= tmpCFGR1; 8000b8c: 687b ldr r3, [r7, #4] 8000b8e: 681b ldr r3, [r3, #0] 8000b90: 68d9 ldr r1, [r3, #12] 8000b92: 687b ldr r3, [r7, #4] 8000b94: 681b ldr r3, [r3, #0] 8000b96: 68ba ldr r2, [r7, #8] 8000b98: 430a orrs r2, r1 8000b9a: 60da str r2, [r3, #12] /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function if parameter */ /* "SamplingTimeCommon" has been set to a valid sampling time. */ /* Otherwise, sampling time is set into ADC channel initialization */ /* structure with parameter "SamplingTime" (obsolete). */ if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000b9c: 687b ldr r3, [r7, #4] 8000b9e: 6ada ldr r2, [r3, #44] ; 0x2c 8000ba0: 2380 movs r3, #128 ; 0x80 8000ba2: 055b lsls r3, r3, #21 8000ba4: 429a cmp r2, r3 8000ba6: d01b beq.n 8000be0 8000ba8: 687b ldr r3, [r7, #4] 8000baa: 6adb ldr r3, [r3, #44] ; 0x2c 8000bac: 2b01 cmp r3, #1 8000bae: d017 beq.n 8000be0 8000bb0: 687b ldr r3, [r7, #4] 8000bb2: 6adb ldr r3, [r3, #44] ; 0x2c 8000bb4: 2b02 cmp r3, #2 8000bb6: d013 beq.n 8000be0 8000bb8: 687b ldr r3, [r7, #4] 8000bba: 6adb ldr r3, [r3, #44] ; 0x2c 8000bbc: 2b03 cmp r3, #3 8000bbe: d00f beq.n 8000be0 8000bc0: 687b ldr r3, [r7, #4] 8000bc2: 6adb ldr r3, [r3, #44] ; 0x2c 8000bc4: 2b04 cmp r3, #4 8000bc6: d00b beq.n 8000be0 8000bc8: 687b ldr r3, [r7, #4] 8000bca: 6adb ldr r3, [r3, #44] ; 0x2c 8000bcc: 2b05 cmp r3, #5 8000bce: d007 beq.n 8000be0 8000bd0: 687b ldr r3, [r7, #4] 8000bd2: 6adb ldr r3, [r3, #44] ; 0x2c 8000bd4: 2b06 cmp r3, #6 8000bd6: d003 beq.n 8000be0 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 6adb ldr r3, [r3, #44] ; 0x2c 8000bdc: 2b07 cmp r3, #7 8000bde: d112 bne.n 8000c06 { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000be0: 687b ldr r3, [r7, #4] 8000be2: 681b ldr r3, [r3, #0] 8000be4: 695a ldr r2, [r3, #20] 8000be6: 687b ldr r3, [r7, #4] 8000be8: 681b ldr r3, [r3, #0] 8000bea: 2107 movs r1, #7 8000bec: 438a bics r2, r1 8000bee: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); 8000bf0: 687b ldr r3, [r7, #4] 8000bf2: 681b ldr r3, [r3, #0] 8000bf4: 6959 ldr r1, [r3, #20] 8000bf6: 687b ldr r3, [r7, #4] 8000bf8: 6adb ldr r3, [r3, #44] ; 0x2c 8000bfa: 2207 movs r2, #7 8000bfc: 401a ands r2, r3 8000bfe: 687b ldr r3, [r7, #4] 8000c00: 681b ldr r3, [r3, #0] 8000c02: 430a orrs r2, r1 8000c04: 615a str r2, [r3, #20] /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ /* set into separate dedicated function, and bits of ADC resolution set */ /* out of temporary variable 'tmpCFGR1'). */ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c06: 687b ldr r3, [r7, #4] 8000c08: 681b ldr r3, [r3, #0] 8000c0a: 68db ldr r3, [r3, #12] 8000c0c: 4a1c ldr r2, [pc, #112] ; (8000c80 ) 8000c0e: 4013 ands r3, r2 8000c10: 68ba ldr r2, [r7, #8] 8000c12: 429a cmp r2, r3 8000c14: d10b bne.n 8000c2e == tmpCFGR1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8000c16: 687b ldr r3, [r7, #4] 8000c18: 2200 movs r2, #0 8000c1a: 63da str r2, [r3, #60] ; 0x3c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000c1c: 687b ldr r3, [r7, #4] 8000c1e: 6b9b ldr r3, [r3, #56] ; 0x38 8000c20: 2203 movs r2, #3 8000c22: 4393 bics r3, r2 8000c24: 2201 movs r2, #1 8000c26: 431a orrs r2, r3 8000c28: 687b ldr r3, [r7, #4] 8000c2a: 639a str r2, [r3, #56] ; 0x38 if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c2c: e01c b.n 8000c68 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8000c2e: 687b ldr r3, [r7, #4] 8000c30: 6b9b ldr r3, [r3, #56] ; 0x38 8000c32: 2212 movs r2, #18 8000c34: 4393 bics r3, r2 8000c36: 2210 movs r2, #16 8000c38: 431a orrs r2, r3 8000c3a: 687b ldr r3, [r7, #4] 8000c3c: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000c3e: 687b ldr r3, [r7, #4] 8000c40: 6bdb ldr r3, [r3, #60] ; 0x3c 8000c42: 2201 movs r2, #1 8000c44: 431a orrs r2, r3 8000c46: 687b ldr r3, [r7, #4] 8000c48: 63da str r2, [r3, #60] ; 0x3c tmp_hal_status = HAL_ERROR; 8000c4a: 230f movs r3, #15 8000c4c: 18fb adds r3, r7, r3 8000c4e: 2201 movs r2, #1 8000c50: 701a strb r2, [r3, #0] if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c52: e009 b.n 8000c68 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000c54: 687b ldr r3, [r7, #4] 8000c56: 6b9b ldr r3, [r3, #56] ; 0x38 8000c58: 2210 movs r2, #16 8000c5a: 431a orrs r2, r3 8000c5c: 687b ldr r3, [r7, #4] 8000c5e: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000c60: 230f movs r3, #15 8000c62: 18fb adds r3, r7, r3 8000c64: 2201 movs r2, #1 8000c66: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000c68: 230f movs r3, #15 8000c6a: 18fb adds r3, r7, r3 8000c6c: 781b ldrb r3, [r3, #0] } 8000c6e: 0018 movs r0, r3 8000c70: 46bd mov sp, r7 8000c72: b004 add sp, #16 8000c74: bd80 pop {r7, pc} 8000c76: 46c0 nop ; (mov r8, r8) 8000c78: fffffefd .word 0xfffffefd 8000c7c: fffe0219 .word 0xfffe0219 8000c80: 833fffe7 .word 0x833fffe7 08000c84 : * Interruptions enabled in this function: None. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 8000c84: b590 push {r4, r7, lr} 8000c86: b085 sub sp, #20 8000c88: af00 add r7, sp, #0 8000c8a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000c8c: 230f movs r3, #15 8000c8e: 18fb adds r3, r7, r3 8000c90: 2200 movs r2, #0 8000c92: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000c94: 687b ldr r3, [r7, #4] 8000c96: 681b ldr r3, [r3, #0] 8000c98: 689b ldr r3, [r3, #8] 8000c9a: 2204 movs r2, #4 8000c9c: 4013 ands r3, r2 8000c9e: d138 bne.n 8000d12 { /* Process locked */ __HAL_LOCK(hadc); 8000ca0: 687b ldr r3, [r7, #4] 8000ca2: 2234 movs r2, #52 ; 0x34 8000ca4: 5c9b ldrb r3, [r3, r2] 8000ca6: 2b01 cmp r3, #1 8000ca8: d101 bne.n 8000cae 8000caa: 2302 movs r3, #2 8000cac: e038 b.n 8000d20 8000cae: 687b ldr r3, [r7, #4] 8000cb0: 2234 movs r2, #52 ; 0x34 8000cb2: 2101 movs r1, #1 8000cb4: 5499 strb r1, [r3, r2] /* Enable the ADC peripheral */ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) 8000cb6: 687b ldr r3, [r7, #4] 8000cb8: 7e5b ldrb r3, [r3, #25] 8000cba: 2b01 cmp r3, #1 8000cbc: d007 beq.n 8000cce { tmp_hal_status = ADC_Enable(hadc); 8000cbe: 230f movs r3, #15 8000cc0: 18fc adds r4, r7, r3 8000cc2: 687b ldr r3, [r7, #4] 8000cc4: 0018 movs r0, r3 8000cc6: f000 fa0b bl 80010e0 8000cca: 0003 movs r3, r0 8000ccc: 7023 strb r3, [r4, #0] } /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8000cce: 230f movs r3, #15 8000cd0: 18fb adds r3, r7, r3 8000cd2: 781b ldrb r3, [r3, #0] 8000cd4: 2b00 cmp r3, #0 8000cd6: d120 bne.n 8000d1a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8000cd8: 687b ldr r3, [r7, #4] 8000cda: 6b9b ldr r3, [r3, #56] ; 0x38 8000cdc: 4a12 ldr r2, [pc, #72] ; (8000d28 ) 8000cde: 4013 ands r3, r2 8000ce0: 2280 movs r2, #128 ; 0x80 8000ce2: 0052 lsls r2, r2, #1 8000ce4: 431a orrs r2, r3 8000ce6: 687b ldr r3, [r7, #4] 8000ce8: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8000cea: 687b ldr r3, [r7, #4] 8000cec: 2200 movs r2, #0 8000cee: 63da str r2, [r3, #60] ; 0x3c /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8000cf0: 687b ldr r3, [r7, #4] 8000cf2: 2234 movs r2, #52 ; 0x34 8000cf4: 2100 movs r1, #0 8000cf6: 5499 strb r1, [r3, r2] /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8000cf8: 687b ldr r3, [r7, #4] 8000cfa: 681b ldr r3, [r3, #0] 8000cfc: 221c movs r2, #28 8000cfe: 601a str r2, [r3, #0] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ hadc->Instance->CR |= ADC_CR_ADSTART; 8000d00: 687b ldr r3, [r7, #4] 8000d02: 681b ldr r3, [r3, #0] 8000d04: 689a ldr r2, [r3, #8] 8000d06: 687b ldr r3, [r7, #4] 8000d08: 681b ldr r3, [r3, #0] 8000d0a: 2104 movs r1, #4 8000d0c: 430a orrs r2, r1 8000d0e: 609a str r2, [r3, #8] 8000d10: e003 b.n 8000d1a } } else { tmp_hal_status = HAL_BUSY; 8000d12: 230f movs r3, #15 8000d14: 18fb adds r3, r7, r3 8000d16: 2202 movs r2, #2 8000d18: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000d1a: 230f movs r3, #15 8000d1c: 18fb adds r3, r7, r3 8000d1e: 781b ldrb r3, [r3, #0] } 8000d20: 0018 movs r0, r3 8000d22: 46bd mov sp, r7 8000d24: b005 add sp, #20 8000d26: bd90 pop {r4, r7, pc} 8000d28: fffff0fe .word 0xfffff0fe 08000d2c : * @brief Stop ADC conversion of regular group, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 8000d2c: b5b0 push {r4, r5, r7, lr} 8000d2e: b084 sub sp, #16 8000d30: af00 add r7, sp, #0 8000d32: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000d34: 230f movs r3, #15 8000d36: 18fb adds r3, r7, r3 8000d38: 2200 movs r2, #0 8000d3a: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8000d3c: 687b ldr r3, [r7, #4] 8000d3e: 2234 movs r2, #52 ; 0x34 8000d40: 5c9b ldrb r3, [r3, r2] 8000d42: 2b01 cmp r3, #1 8000d44: d101 bne.n 8000d4a 8000d46: 2302 movs r3, #2 8000d48: e029 b.n 8000d9e 8000d4a: 687b ldr r3, [r7, #4] 8000d4c: 2234 movs r2, #52 ; 0x34 8000d4e: 2101 movs r1, #1 8000d50: 5499 strb r1, [r3, r2] /* 1. Stop potential conversion on going, on regular group */ tmp_hal_status = ADC_ConversionStop(hadc); 8000d52: 250f movs r5, #15 8000d54: 197c adds r4, r7, r5 8000d56: 687b ldr r3, [r7, #4] 8000d58: 0018 movs r0, r3 8000d5a: f000 fab6 bl 80012ca 8000d5e: 0003 movs r3, r0 8000d60: 7023 strb r3, [r4, #0] /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) 8000d62: 197b adds r3, r7, r5 8000d64: 781b ldrb r3, [r3, #0] 8000d66: 2b00 cmp r3, #0 8000d68: d112 bne.n 8000d90 { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); 8000d6a: 197c adds r4, r7, r5 8000d6c: 687b ldr r3, [r7, #4] 8000d6e: 0018 movs r0, r3 8000d70: f000 fa3a bl 80011e8 8000d74: 0003 movs r3, r0 8000d76: 7023 strb r3, [r4, #0] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8000d78: 197b adds r3, r7, r5 8000d7a: 781b ldrb r3, [r3, #0] 8000d7c: 2b00 cmp r3, #0 8000d7e: d107 bne.n 8000d90 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000d80: 687b ldr r3, [r7, #4] 8000d82: 6b9b ldr r3, [r3, #56] ; 0x38 8000d84: 4a08 ldr r2, [pc, #32] ; (8000da8 ) 8000d86: 4013 ands r3, r2 8000d88: 2201 movs r2, #1 8000d8a: 431a orrs r2, r3 8000d8c: 687b ldr r3, [r7, #4] 8000d8e: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000d90: 687b ldr r3, [r7, #4] 8000d92: 2234 movs r2, #52 ; 0x34 8000d94: 2100 movs r1, #0 8000d96: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 8000d98: 230f movs r3, #15 8000d9a: 18fb adds r3, r7, r3 8000d9c: 781b ldrb r3, [r3, #0] } 8000d9e: 0018 movs r0, r3 8000da0: 46bd mov sp, r7 8000da2: b004 add sp, #16 8000da4: bdb0 pop {r4, r5, r7, pc} 8000da6: 46c0 nop ; (mov r8, r8) 8000da8: fffffefe .word 0xfffffefe 08000dac : * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8000dac: b580 push {r7, lr} 8000dae: b084 sub sp, #16 8000db0: af00 add r7, sp, #0 8000db2: 6078 str r0, [r7, #4] 8000db4: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) 8000db6: 687b ldr r3, [r7, #4] 8000db8: 695b ldr r3, [r3, #20] 8000dba: 2b08 cmp r3, #8 8000dbc: d102 bne.n 8000dc4 { tmp_Flag_EOC = ADC_FLAG_EOS; 8000dbe: 2308 movs r3, #8 8000dc0: 60fb str r3, [r7, #12] 8000dc2: e014 b.n 8000dee /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) 8000dc4: 687b ldr r3, [r7, #4] 8000dc6: 681b ldr r3, [r3, #0] 8000dc8: 68db ldr r3, [r3, #12] 8000dca: 2201 movs r2, #1 8000dcc: 4013 ands r3, r2 8000dce: 2b01 cmp r3, #1 8000dd0: d10b bne.n 8000dea { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000dd2: 687b ldr r3, [r7, #4] 8000dd4: 6b9b ldr r3, [r3, #56] ; 0x38 8000dd6: 2220 movs r2, #32 8000dd8: 431a orrs r2, r3 8000dda: 687b ldr r3, [r7, #4] 8000ddc: 639a str r2, [r3, #56] ; 0x38 /* Process unlocked */ __HAL_UNLOCK(hadc); 8000dde: 687b ldr r3, [r7, #4] 8000de0: 2234 movs r2, #52 ; 0x34 8000de2: 2100 movs r1, #0 8000de4: 5499 strb r1, [r3, r2] return HAL_ERROR; 8000de6: 2301 movs r3, #1 8000de8: e071 b.n 8000ece } else { tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); 8000dea: 230c movs r3, #12 8000dec: 60fb str r3, [r7, #12] } } /* Get tick count */ tickstart = HAL_GetTick(); 8000dee: f7ff fdff bl 80009f0 8000df2: 0003 movs r3, r0 8000df4: 60bb str r3, [r7, #8] /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000df6: e01f b.n 8000e38 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8000df8: 683b ldr r3, [r7, #0] 8000dfa: 3301 adds r3, #1 8000dfc: d01c beq.n 8000e38 { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) 8000dfe: 683b ldr r3, [r7, #0] 8000e00: 2b00 cmp r3, #0 8000e02: d007 beq.n 8000e14 8000e04: f7ff fdf4 bl 80009f0 8000e08: 0002 movs r2, r0 8000e0a: 68bb ldr r3, [r7, #8] 8000e0c: 1ad3 subs r3, r2, r3 8000e0e: 683a ldr r2, [r7, #0] 8000e10: 429a cmp r2, r3 8000e12: d211 bcs.n 8000e38 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e14: 687b ldr r3, [r7, #4] 8000e16: 681b ldr r3, [r3, #0] 8000e18: 681b ldr r3, [r3, #0] 8000e1a: 68fa ldr r2, [r7, #12] 8000e1c: 4013 ands r3, r2 8000e1e: d10b bne.n 8000e38 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8000e20: 687b ldr r3, [r7, #4] 8000e22: 6b9b ldr r3, [r3, #56] ; 0x38 8000e24: 2204 movs r2, #4 8000e26: 431a orrs r2, r3 8000e28: 687b ldr r3, [r7, #4] 8000e2a: 639a str r2, [r3, #56] ; 0x38 /* Process unlocked */ __HAL_UNLOCK(hadc); 8000e2c: 687b ldr r3, [r7, #4] 8000e2e: 2234 movs r2, #52 ; 0x34 8000e30: 2100 movs r1, #0 8000e32: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 8000e34: 2303 movs r3, #3 8000e36: e04a b.n 8000ece while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e38: 687b ldr r3, [r7, #4] 8000e3a: 681b ldr r3, [r3, #0] 8000e3c: 681b ldr r3, [r3, #0] 8000e3e: 68fa ldr r2, [r7, #12] 8000e40: 4013 ands r3, r2 8000e42: d0d9 beq.n 8000df8 } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8000e44: 687b ldr r3, [r7, #4] 8000e46: 6b9b ldr r3, [r3, #56] ; 0x38 8000e48: 2280 movs r2, #128 ; 0x80 8000e4a: 0092 lsls r2, r2, #2 8000e4c: 431a orrs r2, r3 8000e4e: 687b ldr r3, [r7, #4] 8000e50: 639a str r2, [r3, #56] ; 0x38 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000e52: 687b ldr r3, [r7, #4] 8000e54: 681b ldr r3, [r3, #0] 8000e56: 68da ldr r2, [r3, #12] 8000e58: 23c0 movs r3, #192 ; 0xc0 8000e5a: 011b lsls r3, r3, #4 8000e5c: 4013 ands r3, r2 8000e5e: d12d bne.n 8000ebc (hadc->Init.ContinuousConvMode == DISABLE) ) 8000e60: 687b ldr r3, [r7, #4] 8000e62: 7e9b ldrb r3, [r3, #26] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000e64: 2b00 cmp r3, #0 8000e66: d129 bne.n 8000ebc { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) 8000e68: 687b ldr r3, [r7, #4] 8000e6a: 681b ldr r3, [r3, #0] 8000e6c: 681b ldr r3, [r3, #0] 8000e6e: 2208 movs r2, #8 8000e70: 4013 ands r3, r2 8000e72: 2b08 cmp r3, #8 8000e74: d122 bne.n 8000ebc { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000e76: 687b ldr r3, [r7, #4] 8000e78: 681b ldr r3, [r3, #0] 8000e7a: 689b ldr r3, [r3, #8] 8000e7c: 2204 movs r2, #4 8000e7e: 4013 ands r3, r2 8000e80: d110 bne.n 8000ea4 { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 8000e82: 687b ldr r3, [r7, #4] 8000e84: 681b ldr r3, [r3, #0] 8000e86: 685a ldr r2, [r3, #4] 8000e88: 687b ldr r3, [r7, #4] 8000e8a: 681b ldr r3, [r3, #0] 8000e8c: 210c movs r1, #12 8000e8e: 438a bics r2, r1 8000e90: 605a str r2, [r3, #4] /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000e92: 687b ldr r3, [r7, #4] 8000e94: 6b9b ldr r3, [r3, #56] ; 0x38 8000e96: 4a10 ldr r2, [pc, #64] ; (8000ed8 ) 8000e98: 4013 ands r3, r2 8000e9a: 2201 movs r2, #1 8000e9c: 431a orrs r2, r3 8000e9e: 687b ldr r3, [r7, #4] 8000ea0: 639a str r2, [r3, #56] ; 0x38 8000ea2: e00b b.n 8000ebc HAL_ADC_STATE_READY); } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000ea4: 687b ldr r3, [r7, #4] 8000ea6: 6b9b ldr r3, [r3, #56] ; 0x38 8000ea8: 2220 movs r2, #32 8000eaa: 431a orrs r2, r3 8000eac: 687b ldr r3, [r7, #4] 8000eae: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000eb0: 687b ldr r3, [r7, #4] 8000eb2: 6bdb ldr r3, [r3, #60] ; 0x3c 8000eb4: 2201 movs r2, #1 8000eb6: 431a orrs r2, r3 8000eb8: 687b ldr r3, [r7, #4] 8000eba: 63da str r2, [r3, #60] ; 0x3c } /* Clear end of conversion flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (hadc->Init.LowPowerAutoWait == DISABLE) 8000ebc: 687b ldr r3, [r7, #4] 8000ebe: 7e1b ldrb r3, [r3, #24] 8000ec0: 2b00 cmp r3, #0 8000ec2: d103 bne.n 8000ecc { /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); 8000ec4: 687b ldr r3, [r7, #4] 8000ec6: 681b ldr r3, [r3, #0] 8000ec8: 220c movs r2, #12 8000eca: 601a str r2, [r3, #0] } /* Return ADC state */ return HAL_OK; 8000ecc: 2300 movs r3, #0 } 8000ece: 0018 movs r0, r3 8000ed0: 46bd mov sp, r7 8000ed2: b004 add sp, #16 8000ed4: bd80 pop {r7, pc} 8000ed6: 46c0 nop ; (mov r8, r8) 8000ed8: fffffefe .word 0xfffffefe 08000edc : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8000edc: b580 push {r7, lr} 8000ede: b082 sub sp, #8 8000ee0: af00 add r7, sp, #0 8000ee2: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8000ee4: 687b ldr r3, [r7, #4] 8000ee6: 681b ldr r3, [r3, #0] 8000ee8: 6c1b ldr r3, [r3, #64] ; 0x40 } 8000eea: 0018 movs r0, r3 8000eec: 46bd mov sp, r7 8000eee: b002 add sp, #8 8000ef0: bd80 pop {r7, pc} ... 08000ef4 : * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8000ef4: b580 push {r7, lr} 8000ef6: b084 sub sp, #16 8000ef8: af00 add r7, sp, #0 8000efa: 6078 str r0, [r7, #4] 8000efc: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000efe: 230f movs r3, #15 8000f00: 18fb adds r3, r7, r3 8000f02: 2200 movs r2, #0 8000f04: 701a strb r2, [r3, #0] __IO uint32_t wait_loop_index = 0U; 8000f06: 2300 movs r3, #0 8000f08: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_RANK(sConfig->Rank)); if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000f0a: 687b ldr r3, [r7, #4] 8000f0c: 6ada ldr r2, [r3, #44] ; 0x2c 8000f0e: 2380 movs r3, #128 ; 0x80 8000f10: 055b lsls r3, r3, #21 8000f12: 429a cmp r2, r3 8000f14: d011 beq.n 8000f3a 8000f16: 687b ldr r3, [r7, #4] 8000f18: 6adb ldr r3, [r3, #44] ; 0x2c 8000f1a: 2b01 cmp r3, #1 8000f1c: d00d beq.n 8000f3a 8000f1e: 687b ldr r3, [r7, #4] 8000f20: 6adb ldr r3, [r3, #44] ; 0x2c 8000f22: 2b02 cmp r3, #2 8000f24: d009 beq.n 8000f3a 8000f26: 687b ldr r3, [r7, #4] 8000f28: 6adb ldr r3, [r3, #44] ; 0x2c 8000f2a: 2b03 cmp r3, #3 8000f2c: d005 beq.n 8000f3a 8000f2e: 687b ldr r3, [r7, #4] 8000f30: 6adb ldr r3, [r3, #44] ; 0x2c 8000f32: 2b04 cmp r3, #4 8000f34: d001 beq.n 8000f3a 8000f36: 687b ldr r3, [r7, #4] 8000f38: 6adb ldr r3, [r3, #44] ; 0x2c { assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); } /* Process locked */ __HAL_LOCK(hadc); 8000f3a: 687b ldr r3, [r7, #4] 8000f3c: 2234 movs r2, #52 ; 0x34 8000f3e: 5c9b ldrb r3, [r3, r2] 8000f40: 2b01 cmp r3, #1 8000f42: d101 bne.n 8000f48 8000f44: 2302 movs r3, #2 8000f46: e0bb b.n 80010c0 8000f48: 687b ldr r3, [r7, #4] 8000f4a: 2234 movs r2, #52 ; 0x34 8000f4c: 2101 movs r1, #1 8000f4e: 5499 strb r1, [r3, r2] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000f50: 687b ldr r3, [r7, #4] 8000f52: 681b ldr r3, [r3, #0] 8000f54: 689b ldr r3, [r3, #8] 8000f56: 2204 movs r2, #4 8000f58: 4013 ands r3, r2 8000f5a: d000 beq.n 8000f5e 8000f5c: e09f b.n 800109e { /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC conversion sequencer. */ if (sConfig->Rank != ADC_RANK_NONE) 8000f5e: 683b ldr r3, [r7, #0] 8000f60: 685b ldr r3, [r3, #4] 8000f62: 4a59 ldr r2, [pc, #356] ; (80010c8 ) 8000f64: 4293 cmp r3, r2 8000f66: d100 bne.n 8000f6a 8000f68: e077 b.n 800105a { /* Regular sequence configuration */ /* Set the channel selection register from the selected channel */ hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); 8000f6a: 687b ldr r3, [r7, #4] 8000f6c: 681b ldr r3, [r3, #0] 8000f6e: 6a99 ldr r1, [r3, #40] ; 0x28 8000f70: 683b ldr r3, [r7, #0] 8000f72: 681b ldr r3, [r3, #0] 8000f74: 2201 movs r2, #1 8000f76: 409a lsls r2, r3 8000f78: 687b ldr r3, [r7, #4] 8000f7a: 681b ldr r3, [r3, #0] 8000f7c: 430a orrs r2, r1 8000f7e: 629a str r2, [r3, #40] ; 0x28 /* Channel sampling time configuration */ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function with */ /* parameter "SamplingTime" (obsolete) only if not already set into */ /* ADC initialization structure with parameter "SamplingTimeCommon". */ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000f80: 687b ldr r3, [r7, #4] 8000f82: 6ada ldr r2, [r3, #44] ; 0x2c 8000f84: 2380 movs r3, #128 ; 0x80 8000f86: 055b lsls r3, r3, #21 8000f88: 429a cmp r2, r3 8000f8a: d037 beq.n 8000ffc 8000f8c: 687b ldr r3, [r7, #4] 8000f8e: 6adb ldr r3, [r3, #44] ; 0x2c 8000f90: 2b01 cmp r3, #1 8000f92: d033 beq.n 8000ffc 8000f94: 687b ldr r3, [r7, #4] 8000f96: 6adb ldr r3, [r3, #44] ; 0x2c 8000f98: 2b02 cmp r3, #2 8000f9a: d02f beq.n 8000ffc 8000f9c: 687b ldr r3, [r7, #4] 8000f9e: 6adb ldr r3, [r3, #44] ; 0x2c 8000fa0: 2b03 cmp r3, #3 8000fa2: d02b beq.n 8000ffc 8000fa4: 687b ldr r3, [r7, #4] 8000fa6: 6adb ldr r3, [r3, #44] ; 0x2c 8000fa8: 2b04 cmp r3, #4 8000faa: d027 beq.n 8000ffc 8000fac: 687b ldr r3, [r7, #4] 8000fae: 6adb ldr r3, [r3, #44] ; 0x2c 8000fb0: 2b05 cmp r3, #5 8000fb2: d023 beq.n 8000ffc 8000fb4: 687b ldr r3, [r7, #4] 8000fb6: 6adb ldr r3, [r3, #44] ; 0x2c 8000fb8: 2b06 cmp r3, #6 8000fba: d01f beq.n 8000ffc 8000fbc: 687b ldr r3, [r7, #4] 8000fbe: 6adb ldr r3, [r3, #44] ; 0x2c 8000fc0: 2b07 cmp r3, #7 8000fc2: d01b beq.n 8000ffc { /* Modify sampling time if needed (not needed in case of reoccurrence */ /* for several channels programmed consecutively into the sequencer) */ if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) 8000fc4: 683b ldr r3, [r7, #0] 8000fc6: 689a ldr r2, [r3, #8] 8000fc8: 687b ldr r3, [r7, #4] 8000fca: 681b ldr r3, [r3, #0] 8000fcc: 695b ldr r3, [r3, #20] 8000fce: 2107 movs r1, #7 8000fd0: 400b ands r3, r1 8000fd2: 429a cmp r2, r3 8000fd4: d012 beq.n 8000ffc { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000fd6: 687b ldr r3, [r7, #4] 8000fd8: 681b ldr r3, [r3, #0] 8000fda: 695a ldr r2, [r3, #20] 8000fdc: 687b ldr r3, [r7, #4] 8000fde: 681b ldr r3, [r3, #0] 8000fe0: 2107 movs r1, #7 8000fe2: 438a bics r2, r1 8000fe4: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); 8000fe6: 687b ldr r3, [r7, #4] 8000fe8: 681b ldr r3, [r3, #0] 8000fea: 6959 ldr r1, [r3, #20] 8000fec: 683b ldr r3, [r7, #0] 8000fee: 689b ldr r3, [r3, #8] 8000ff0: 2207 movs r2, #7 8000ff2: 401a ands r2, r3 8000ff4: 687b ldr r3, [r7, #4] 8000ff6: 681b ldr r3, [r3, #0] 8000ff8: 430a orrs r2, r1 8000ffa: 615a str r2, [r3, #20] /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8000ffc: 683b ldr r3, [r7, #0] 8000ffe: 681b ldr r3, [r3, #0] 8001000: 2b10 cmp r3, #16 8001002: d003 beq.n 800100c 8001004: 683b ldr r3, [r7, #0] 8001006: 681b ldr r3, [r3, #0] 8001008: 2b11 cmp r3, #17 800100a: d152 bne.n 80010b2 { /* If Channel_16 is selected, enable Temp. sensor measurement path. */ /* If Channel_17 is selected, enable VREFINT measurement path. */ /* If Channel_18 is selected, enable VBAT measurement path. */ ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 800100c: 4b2f ldr r3, [pc, #188] ; (80010cc ) 800100e: 6819 ldr r1, [r3, #0] 8001010: 683b ldr r3, [r7, #0] 8001012: 681b ldr r3, [r3, #0] 8001014: 2b10 cmp r3, #16 8001016: d102 bne.n 800101e 8001018: 2380 movs r3, #128 ; 0x80 800101a: 041b lsls r3, r3, #16 800101c: e001 b.n 8001022 800101e: 2380 movs r3, #128 ; 0x80 8001020: 03db lsls r3, r3, #15 8001022: 4a2a ldr r2, [pc, #168] ; (80010cc ) 8001024: 430b orrs r3, r1 8001026: 6013 str r3, [r2, #0] /* If Temp. sensor is selected, wait for stabilization delay */ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8001028: 683b ldr r3, [r7, #0] 800102a: 681b ldr r3, [r3, #0] 800102c: 2b10 cmp r3, #16 800102e: d140 bne.n 80010b2 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001030: 4b27 ldr r3, [pc, #156] ; (80010d0 ) 8001032: 681b ldr r3, [r3, #0] 8001034: 4927 ldr r1, [pc, #156] ; (80010d4 ) 8001036: 0018 movs r0, r3 8001038: f7ff f866 bl 8000108 <__udivsi3> 800103c: 0003 movs r3, r0 800103e: 001a movs r2, r3 8001040: 0013 movs r3, r2 8001042: 009b lsls r3, r3, #2 8001044: 189b adds r3, r3, r2 8001046: 005b lsls r3, r3, #1 8001048: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800104a: e002 b.n 8001052 { wait_loop_index--; 800104c: 68bb ldr r3, [r7, #8] 800104e: 3b01 subs r3, #1 8001050: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001052: 68bb ldr r3, [r7, #8] 8001054: 2b00 cmp r3, #0 8001056: d1f9 bne.n 800104c 8001058: e02b b.n 80010b2 } else { /* Regular sequence configuration */ /* Reset the channel selection register from the selected channel */ hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); 800105a: 687b ldr r3, [r7, #4] 800105c: 681b ldr r3, [r3, #0] 800105e: 6a9a ldr r2, [r3, #40] ; 0x28 8001060: 683b ldr r3, [r7, #0] 8001062: 681b ldr r3, [r3, #0] 8001064: 2101 movs r1, #1 8001066: 4099 lsls r1, r3 8001068: 000b movs r3, r1 800106a: 43d9 mvns r1, r3 800106c: 687b ldr r3, [r7, #4] 800106e: 681b ldr r3, [r3, #0] 8001070: 400a ands r2, r1 8001072: 629a str r2, [r3, #40] ; 0x28 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths disable: If internal channel selected, */ /* disable dedicated internal buffers and path. */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8001074: 683b ldr r3, [r7, #0] 8001076: 681b ldr r3, [r3, #0] 8001078: 2b10 cmp r3, #16 800107a: d003 beq.n 8001084 800107c: 683b ldr r3, [r7, #0] 800107e: 681b ldr r3, [r3, #0] 8001080: 2b11 cmp r3, #17 8001082: d116 bne.n 80010b2 { /* If Channel_16 is selected, disable Temp. sensor measurement path. */ /* If Channel_17 is selected, disable VREFINT measurement path. */ /* If Channel_18 is selected, disable VBAT measurement path. */ ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 8001084: 4b11 ldr r3, [pc, #68] ; (80010cc ) 8001086: 6819 ldr r1, [r3, #0] 8001088: 683b ldr r3, [r7, #0] 800108a: 681b ldr r3, [r3, #0] 800108c: 2b10 cmp r3, #16 800108e: d101 bne.n 8001094 8001090: 4a11 ldr r2, [pc, #68] ; (80010d8 ) 8001092: e000 b.n 8001096 8001094: 4a11 ldr r2, [pc, #68] ; (80010dc ) 8001096: 4b0d ldr r3, [pc, #52] ; (80010cc ) 8001098: 400a ands r2, r1 800109a: 601a str r2, [r3, #0] 800109c: e009 b.n 80010b2 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800109e: 687b ldr r3, [r7, #4] 80010a0: 6b9b ldr r3, [r3, #56] ; 0x38 80010a2: 2220 movs r2, #32 80010a4: 431a orrs r2, r3 80010a6: 687b ldr r3, [r7, #4] 80010a8: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 80010aa: 230f movs r3, #15 80010ac: 18fb adds r3, r7, r3 80010ae: 2201 movs r2, #1 80010b0: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hadc); 80010b2: 687b ldr r3, [r7, #4] 80010b4: 2234 movs r2, #52 ; 0x34 80010b6: 2100 movs r1, #0 80010b8: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 80010ba: 230f movs r3, #15 80010bc: 18fb adds r3, r7, r3 80010be: 781b ldrb r3, [r3, #0] } 80010c0: 0018 movs r0, r3 80010c2: 46bd mov sp, r7 80010c4: b004 add sp, #16 80010c6: bd80 pop {r7, pc} 80010c8: 00001001 .word 0x00001001 80010cc: 40012708 .word 0x40012708 80010d0: 20000000 .word 0x20000000 80010d4: 000f4240 .word 0x000f4240 80010d8: ff7fffff .word 0xff7fffff 80010dc: ffbfffff .word 0xffbfffff 080010e0 : * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 80010e0: b580 push {r7, lr} 80010e2: b084 sub sp, #16 80010e4: af00 add r7, sp, #0 80010e6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80010e8: 2300 movs r3, #0 80010ea: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 80010ec: 2300 movs r3, #0 80010ee: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 80010f0: 687b ldr r3, [r7, #4] 80010f2: 681b ldr r3, [r3, #0] 80010f4: 689b ldr r3, [r3, #8] 80010f6: 2203 movs r2, #3 80010f8: 4013 ands r3, r2 80010fa: 2b01 cmp r3, #1 80010fc: d112 bne.n 8001124 80010fe: 687b ldr r3, [r7, #4] 8001100: 681b ldr r3, [r3, #0] 8001102: 681b ldr r3, [r3, #0] 8001104: 2201 movs r2, #1 8001106: 4013 ands r3, r2 8001108: 2b01 cmp r3, #1 800110a: d009 beq.n 8001120 800110c: 687b ldr r3, [r7, #4] 800110e: 681b ldr r3, [r3, #0] 8001110: 68da ldr r2, [r3, #12] 8001112: 2380 movs r3, #128 ; 0x80 8001114: 021b lsls r3, r3, #8 8001116: 401a ands r2, r3 8001118: 2380 movs r3, #128 ; 0x80 800111a: 021b lsls r3, r3, #8 800111c: 429a cmp r2, r3 800111e: d101 bne.n 8001124 8001120: 2301 movs r3, #1 8001122: e000 b.n 8001126 8001124: 2300 movs r3, #0 8001126: 2b00 cmp r3, #0 8001128: d152 bne.n 80011d0 { /* Check if conditions to enable the ADC are fulfilled */ if (ADC_ENABLING_CONDITIONS(hadc) == RESET) 800112a: 687b ldr r3, [r7, #4] 800112c: 681b ldr r3, [r3, #0] 800112e: 689b ldr r3, [r3, #8] 8001130: 4a2a ldr r2, [pc, #168] ; (80011dc ) 8001132: 4013 ands r3, r2 8001134: d00d beq.n 8001152 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001136: 687b ldr r3, [r7, #4] 8001138: 6b9b ldr r3, [r3, #56] ; 0x38 800113a: 2210 movs r2, #16 800113c: 431a orrs r2, r3 800113e: 687b ldr r3, [r7, #4] 8001140: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001142: 687b ldr r3, [r7, #4] 8001144: 6bdb ldr r3, [r3, #60] ; 0x3c 8001146: 2201 movs r2, #1 8001148: 431a orrs r2, r3 800114a: 687b ldr r3, [r7, #4] 800114c: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 800114e: 2301 movs r3, #1 8001150: e03f b.n 80011d2 } /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); 8001152: 687b ldr r3, [r7, #4] 8001154: 681b ldr r3, [r3, #0] 8001156: 689a ldr r2, [r3, #8] 8001158: 687b ldr r3, [r7, #4] 800115a: 681b ldr r3, [r3, #0] 800115c: 2101 movs r1, #1 800115e: 430a orrs r2, r1 8001160: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8001162: 4b1f ldr r3, [pc, #124] ; (80011e0 ) 8001164: 681b ldr r3, [r3, #0] 8001166: 491f ldr r1, [pc, #124] ; (80011e4 ) 8001168: 0018 movs r0, r3 800116a: f7fe ffcd bl 8000108 <__udivsi3> 800116e: 0003 movs r3, r0 8001170: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001172: e002 b.n 800117a { wait_loop_index--; 8001174: 68bb ldr r3, [r7, #8] 8001176: 3b01 subs r3, #1 8001178: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800117a: 68bb ldr r3, [r7, #8] 800117c: 2b00 cmp r3, #0 800117e: d1f9 bne.n 8001174 } /* Get tick count */ tickstart = HAL_GetTick(); 8001180: f7ff fc36 bl 80009f0 8001184: 0003 movs r3, r0 8001186: 60fb str r3, [r7, #12] /* Wait for ADC effectively enabled */ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 8001188: e01b b.n 80011c2 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800118a: f7ff fc31 bl 80009f0 800118e: 0002 movs r2, r0 8001190: 68fb ldr r3, [r7, #12] 8001192: 1ad3 subs r3, r2, r3 8001194: 2b02 cmp r3, #2 8001196: d914 bls.n 80011c2 { /* New check to avoid false timeout detection in case of preemption */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 8001198: 687b ldr r3, [r7, #4] 800119a: 681b ldr r3, [r3, #0] 800119c: 681b ldr r3, [r3, #0] 800119e: 2201 movs r2, #1 80011a0: 4013 ands r3, r2 80011a2: 2b01 cmp r3, #1 80011a4: d00d beq.n 80011c2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80011a6: 687b ldr r3, [r7, #4] 80011a8: 6b9b ldr r3, [r3, #56] ; 0x38 80011aa: 2210 movs r2, #16 80011ac: 431a orrs r2, r3 80011ae: 687b ldr r3, [r7, #4] 80011b0: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80011b2: 687b ldr r3, [r7, #4] 80011b4: 6bdb ldr r3, [r3, #60] ; 0x3c 80011b6: 2201 movs r2, #1 80011b8: 431a orrs r2, r3 80011ba: 687b ldr r3, [r7, #4] 80011bc: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80011be: 2301 movs r3, #1 80011c0: e007 b.n 80011d2 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80011c2: 687b ldr r3, [r7, #4] 80011c4: 681b ldr r3, [r3, #0] 80011c6: 681b ldr r3, [r3, #0] 80011c8: 2201 movs r2, #1 80011ca: 4013 ands r3, r2 80011cc: 2b01 cmp r3, #1 80011ce: d1dc bne.n 800118a } } } /* Return HAL status */ return HAL_OK; 80011d0: 2300 movs r3, #0 } 80011d2: 0018 movs r0, r3 80011d4: 46bd mov sp, r7 80011d6: b004 add sp, #16 80011d8: bd80 pop {r7, pc} 80011da: 46c0 nop ; (mov r8, r8) 80011dc: 80000017 .word 0x80000017 80011e0: 20000000 .word 0x20000000 80011e4: 000f4240 .word 0x000f4240 080011e8 : * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { 80011e8: b580 push {r7, lr} 80011ea: b084 sub sp, #16 80011ec: af00 add r7, sp, #0 80011ee: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80011f0: 2300 movs r3, #0 80011f2: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET) 80011f4: 687b ldr r3, [r7, #4] 80011f6: 681b ldr r3, [r3, #0] 80011f8: 689b ldr r3, [r3, #8] 80011fa: 2203 movs r2, #3 80011fc: 4013 ands r3, r2 80011fe: 2b01 cmp r3, #1 8001200: d112 bne.n 8001228 8001202: 687b ldr r3, [r7, #4] 8001204: 681b ldr r3, [r3, #0] 8001206: 681b ldr r3, [r3, #0] 8001208: 2201 movs r2, #1 800120a: 4013 ands r3, r2 800120c: 2b01 cmp r3, #1 800120e: d009 beq.n 8001224 8001210: 687b ldr r3, [r7, #4] 8001212: 681b ldr r3, [r3, #0] 8001214: 68da ldr r2, [r3, #12] 8001216: 2380 movs r3, #128 ; 0x80 8001218: 021b lsls r3, r3, #8 800121a: 401a ands r2, r3 800121c: 2380 movs r3, #128 ; 0x80 800121e: 021b lsls r3, r3, #8 8001220: 429a cmp r2, r3 8001222: d101 bne.n 8001228 8001224: 2301 movs r3, #1 8001226: e000 b.n 800122a 8001228: 2300 movs r3, #0 800122a: 2b00 cmp r3, #0 800122c: d048 beq.n 80012c0 { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) 800122e: 687b ldr r3, [r7, #4] 8001230: 681b ldr r3, [r3, #0] 8001232: 689b ldr r3, [r3, #8] 8001234: 2205 movs r2, #5 8001236: 4013 ands r3, r2 8001238: 2b01 cmp r3, #1 800123a: d110 bne.n 800125e { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800123c: 687b ldr r3, [r7, #4] 800123e: 681b ldr r3, [r3, #0] 8001240: 689a ldr r2, [r3, #8] 8001242: 687b ldr r3, [r7, #4] 8001244: 681b ldr r3, [r3, #0] 8001246: 2102 movs r1, #2 8001248: 430a orrs r2, r1 800124a: 609a str r2, [r3, #8] 800124c: 687b ldr r3, [r7, #4] 800124e: 681b ldr r3, [r3, #0] 8001250: 2203 movs r2, #3 8001252: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8001254: f7ff fbcc bl 80009f0 8001258: 0003 movs r3, r0 800125a: 60fb str r3, [r7, #12] while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 800125c: e029 b.n 80012b2 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800125e: 687b ldr r3, [r7, #4] 8001260: 6b9b ldr r3, [r3, #56] ; 0x38 8001262: 2210 movs r2, #16 8001264: 431a orrs r2, r3 8001266: 687b ldr r3, [r7, #4] 8001268: 639a str r2, [r3, #56] ; 0x38 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800126a: 687b ldr r3, [r7, #4] 800126c: 6bdb ldr r3, [r3, #60] ; 0x3c 800126e: 2201 movs r2, #1 8001270: 431a orrs r2, r3 8001272: 687b ldr r3, [r7, #4] 8001274: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 8001276: 2301 movs r3, #1 8001278: e023 b.n 80012c2 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800127a: f7ff fbb9 bl 80009f0 800127e: 0002 movs r2, r0 8001280: 68fb ldr r3, [r7, #12] 8001282: 1ad3 subs r3, r2, r3 8001284: 2b02 cmp r3, #2 8001286: d914 bls.n 80012b2 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 8001288: 687b ldr r3, [r7, #4] 800128a: 681b ldr r3, [r3, #0] 800128c: 689b ldr r3, [r3, #8] 800128e: 2201 movs r2, #1 8001290: 4013 ands r3, r2 8001292: 2b01 cmp r3, #1 8001294: d10d bne.n 80012b2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001296: 687b ldr r3, [r7, #4] 8001298: 6b9b ldr r3, [r3, #56] ; 0x38 800129a: 2210 movs r2, #16 800129c: 431a orrs r2, r3 800129e: 687b ldr r3, [r7, #4] 80012a0: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80012a2: 687b ldr r3, [r7, #4] 80012a4: 6bdb ldr r3, [r3, #60] ; 0x3c 80012a6: 2201 movs r2, #1 80012a8: 431a orrs r2, r3 80012aa: 687b ldr r3, [r7, #4] 80012ac: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80012ae: 2301 movs r3, #1 80012b0: e007 b.n 80012c2 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80012b2: 687b ldr r3, [r7, #4] 80012b4: 681b ldr r3, [r3, #0] 80012b6: 689b ldr r3, [r3, #8] 80012b8: 2201 movs r2, #1 80012ba: 4013 ands r3, r2 80012bc: 2b01 cmp r3, #1 80012be: d0dc beq.n 800127a } } } /* Return HAL status */ return HAL_OK; 80012c0: 2300 movs r3, #0 } 80012c2: 0018 movs r0, r3 80012c4: 46bd mov sp, r7 80012c6: b004 add sp, #16 80012c8: bd80 pop {r7, pc} 080012ca : * stopped to disable the ADC. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) { 80012ca: b580 push {r7, lr} 80012cc: b084 sub sp, #16 80012ce: af00 add r7, sp, #0 80012d0: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80012d2: 2300 movs r3, #0 80012d4: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Verification if ADC is not already stopped on regular group to bypass */ /* this function if not needed. */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) 80012d6: 687b ldr r3, [r7, #4] 80012d8: 681b ldr r3, [r3, #0] 80012da: 689b ldr r3, [r3, #8] 80012dc: 2204 movs r2, #4 80012de: 4013 ands r3, r2 80012e0: d03a beq.n 8001358 { /* Stop potential conversion on going on regular group */ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 80012e2: 687b ldr r3, [r7, #4] 80012e4: 681b ldr r3, [r3, #0] 80012e6: 689b ldr r3, [r3, #8] 80012e8: 2204 movs r2, #4 80012ea: 4013 ands r3, r2 80012ec: 2b04 cmp r3, #4 80012ee: d10d bne.n 800130c HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) 80012f0: 687b ldr r3, [r7, #4] 80012f2: 681b ldr r3, [r3, #0] 80012f4: 689b ldr r3, [r3, #8] 80012f6: 2202 movs r2, #2 80012f8: 4013 ands r3, r2 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 80012fa: d107 bne.n 800130c { /* Stop conversions on regular group */ hadc->Instance->CR |= ADC_CR_ADSTP; 80012fc: 687b ldr r3, [r7, #4] 80012fe: 681b ldr r3, [r3, #0] 8001300: 689a ldr r2, [r3, #8] 8001302: 687b ldr r3, [r7, #4] 8001304: 681b ldr r3, [r3, #0] 8001306: 2110 movs r1, #16 8001308: 430a orrs r2, r1 800130a: 609a str r2, [r3, #8] } /* Wait for conversion effectively stopped */ /* Get tick count */ tickstart = HAL_GetTick(); 800130c: f7ff fb70 bl 80009f0 8001310: 0003 movs r3, r0 8001312: 60fb str r3, [r7, #12] while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 8001314: e01a b.n 800134c { if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 8001316: f7ff fb6b bl 80009f0 800131a: 0002 movs r2, r0 800131c: 68fb ldr r3, [r7, #12] 800131e: 1ad3 subs r3, r2, r3 8001320: 2b02 cmp r3, #2 8001322: d913 bls.n 800134c { /* New check to avoid false timeout detection in case of preemption */ if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 8001324: 687b ldr r3, [r7, #4] 8001326: 681b ldr r3, [r3, #0] 8001328: 689b ldr r3, [r3, #8] 800132a: 2204 movs r2, #4 800132c: 4013 ands r3, r2 800132e: d00d beq.n 800134c { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001330: 687b ldr r3, [r7, #4] 8001332: 6b9b ldr r3, [r3, #56] ; 0x38 8001334: 2210 movs r2, #16 8001336: 431a orrs r2, r3 8001338: 687b ldr r3, [r7, #4] 800133a: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800133c: 687b ldr r3, [r7, #4] 800133e: 6bdb ldr r3, [r3, #60] ; 0x3c 8001340: 2201 movs r2, #1 8001342: 431a orrs r2, r3 8001344: 687b ldr r3, [r7, #4] 8001346: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 8001348: 2301 movs r3, #1 800134a: e006 b.n 800135a while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 800134c: 687b ldr r3, [r7, #4] 800134e: 681b ldr r3, [r3, #0] 8001350: 689b ldr r3, [r3, #8] 8001352: 2204 movs r2, #4 8001354: 4013 ands r3, r2 8001356: d1de bne.n 8001316 } } } /* Return HAL status */ return HAL_OK; 8001358: 2300 movs r3, #0 } 800135a: 0018 movs r0, r3 800135c: 46bd mov sp, r7 800135e: b004 add sp, #16 8001360: bd80 pop {r7, pc} ... 08001364 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001364: b580 push {r7, lr} 8001366: b082 sub sp, #8 8001368: af00 add r7, sp, #0 800136a: 0002 movs r2, r0 800136c: 1dfb adds r3, r7, #7 800136e: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8001370: 1dfb adds r3, r7, #7 8001372: 781b ldrb r3, [r3, #0] 8001374: 2b7f cmp r3, #127 ; 0x7f 8001376: d809 bhi.n 800138c <__NVIC_EnableIRQ+0x28> { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001378: 1dfb adds r3, r7, #7 800137a: 781b ldrb r3, [r3, #0] 800137c: 001a movs r2, r3 800137e: 231f movs r3, #31 8001380: 401a ands r2, r3 8001382: 4b04 ldr r3, [pc, #16] ; (8001394 <__NVIC_EnableIRQ+0x30>) 8001384: 2101 movs r1, #1 8001386: 4091 lsls r1, r2 8001388: 000a movs r2, r1 800138a: 601a str r2, [r3, #0] } } 800138c: 46c0 nop ; (mov r8, r8) 800138e: 46bd mov sp, r7 8001390: b002 add sp, #8 8001392: bd80 pop {r7, pc} 8001394: e000e100 .word 0xe000e100 08001398 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001398: b590 push {r4, r7, lr} 800139a: b083 sub sp, #12 800139c: af00 add r7, sp, #0 800139e: 0002 movs r2, r0 80013a0: 6039 str r1, [r7, #0] 80013a2: 1dfb adds r3, r7, #7 80013a4: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80013a6: 1dfb adds r3, r7, #7 80013a8: 781b ldrb r3, [r3, #0] 80013aa: 2b7f cmp r3, #127 ; 0x7f 80013ac: d828 bhi.n 8001400 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80013ae: 4a2f ldr r2, [pc, #188] ; (800146c <__NVIC_SetPriority+0xd4>) 80013b0: 1dfb adds r3, r7, #7 80013b2: 781b ldrb r3, [r3, #0] 80013b4: b25b sxtb r3, r3 80013b6: 089b lsrs r3, r3, #2 80013b8: 33c0 adds r3, #192 ; 0xc0 80013ba: 009b lsls r3, r3, #2 80013bc: 589b ldr r3, [r3, r2] 80013be: 1dfa adds r2, r7, #7 80013c0: 7812 ldrb r2, [r2, #0] 80013c2: 0011 movs r1, r2 80013c4: 2203 movs r2, #3 80013c6: 400a ands r2, r1 80013c8: 00d2 lsls r2, r2, #3 80013ca: 21ff movs r1, #255 ; 0xff 80013cc: 4091 lsls r1, r2 80013ce: 000a movs r2, r1 80013d0: 43d2 mvns r2, r2 80013d2: 401a ands r2, r3 80013d4: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80013d6: 683b ldr r3, [r7, #0] 80013d8: 019b lsls r3, r3, #6 80013da: 22ff movs r2, #255 ; 0xff 80013dc: 401a ands r2, r3 80013de: 1dfb adds r3, r7, #7 80013e0: 781b ldrb r3, [r3, #0] 80013e2: 0018 movs r0, r3 80013e4: 2303 movs r3, #3 80013e6: 4003 ands r3, r0 80013e8: 00db lsls r3, r3, #3 80013ea: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80013ec: 481f ldr r0, [pc, #124] ; (800146c <__NVIC_SetPriority+0xd4>) 80013ee: 1dfb adds r3, r7, #7 80013f0: 781b ldrb r3, [r3, #0] 80013f2: b25b sxtb r3, r3 80013f4: 089b lsrs r3, r3, #2 80013f6: 430a orrs r2, r1 80013f8: 33c0 adds r3, #192 ; 0xc0 80013fa: 009b lsls r3, r3, #2 80013fc: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 80013fe: e031 b.n 8001464 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001400: 4a1b ldr r2, [pc, #108] ; (8001470 <__NVIC_SetPriority+0xd8>) 8001402: 1dfb adds r3, r7, #7 8001404: 781b ldrb r3, [r3, #0] 8001406: 0019 movs r1, r3 8001408: 230f movs r3, #15 800140a: 400b ands r3, r1 800140c: 3b08 subs r3, #8 800140e: 089b lsrs r3, r3, #2 8001410: 3306 adds r3, #6 8001412: 009b lsls r3, r3, #2 8001414: 18d3 adds r3, r2, r3 8001416: 3304 adds r3, #4 8001418: 681b ldr r3, [r3, #0] 800141a: 1dfa adds r2, r7, #7 800141c: 7812 ldrb r2, [r2, #0] 800141e: 0011 movs r1, r2 8001420: 2203 movs r2, #3 8001422: 400a ands r2, r1 8001424: 00d2 lsls r2, r2, #3 8001426: 21ff movs r1, #255 ; 0xff 8001428: 4091 lsls r1, r2 800142a: 000a movs r2, r1 800142c: 43d2 mvns r2, r2 800142e: 401a ands r2, r3 8001430: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8001432: 683b ldr r3, [r7, #0] 8001434: 019b lsls r3, r3, #6 8001436: 22ff movs r2, #255 ; 0xff 8001438: 401a ands r2, r3 800143a: 1dfb adds r3, r7, #7 800143c: 781b ldrb r3, [r3, #0] 800143e: 0018 movs r0, r3 8001440: 2303 movs r3, #3 8001442: 4003 ands r3, r0 8001444: 00db lsls r3, r3, #3 8001446: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001448: 4809 ldr r0, [pc, #36] ; (8001470 <__NVIC_SetPriority+0xd8>) 800144a: 1dfb adds r3, r7, #7 800144c: 781b ldrb r3, [r3, #0] 800144e: 001c movs r4, r3 8001450: 230f movs r3, #15 8001452: 4023 ands r3, r4 8001454: 3b08 subs r3, #8 8001456: 089b lsrs r3, r3, #2 8001458: 430a orrs r2, r1 800145a: 3306 adds r3, #6 800145c: 009b lsls r3, r3, #2 800145e: 18c3 adds r3, r0, r3 8001460: 3304 adds r3, #4 8001462: 601a str r2, [r3, #0] } 8001464: 46c0 nop ; (mov r8, r8) 8001466: 46bd mov sp, r7 8001468: b003 add sp, #12 800146a: bd90 pop {r4, r7, pc} 800146c: e000e100 .word 0xe000e100 8001470: e000ed00 .word 0xe000ed00 08001474 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001474: b580 push {r7, lr} 8001476: b082 sub sp, #8 8001478: af00 add r7, sp, #0 800147a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800147c: 687b ldr r3, [r7, #4] 800147e: 1e5a subs r2, r3, #1 8001480: 2380 movs r3, #128 ; 0x80 8001482: 045b lsls r3, r3, #17 8001484: 429a cmp r2, r3 8001486: d301 bcc.n 800148c { return (1UL); /* Reload value impossible */ 8001488: 2301 movs r3, #1 800148a: e010 b.n 80014ae } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800148c: 4b0a ldr r3, [pc, #40] ; (80014b8 ) 800148e: 687a ldr r2, [r7, #4] 8001490: 3a01 subs r2, #1 8001492: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001494: 2301 movs r3, #1 8001496: 425b negs r3, r3 8001498: 2103 movs r1, #3 800149a: 0018 movs r0, r3 800149c: f7ff ff7c bl 8001398 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80014a0: 4b05 ldr r3, [pc, #20] ; (80014b8 ) 80014a2: 2200 movs r2, #0 80014a4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80014a6: 4b04 ldr r3, [pc, #16] ; (80014b8 ) 80014a8: 2207 movs r2, #7 80014aa: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80014ac: 2300 movs r3, #0 } 80014ae: 0018 movs r0, r3 80014b0: 46bd mov sp, r7 80014b2: b002 add sp, #8 80014b4: bd80 pop {r7, pc} 80014b6: 46c0 nop ; (mov r8, r8) 80014b8: e000e010 .word 0xe000e010 080014bc : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80014bc: b580 push {r7, lr} 80014be: b084 sub sp, #16 80014c0: af00 add r7, sp, #0 80014c2: 60b9 str r1, [r7, #8] 80014c4: 607a str r2, [r7, #4] 80014c6: 210f movs r1, #15 80014c8: 187b adds r3, r7, r1 80014ca: 1c02 adds r2, r0, #0 80014cc: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 80014ce: 68ba ldr r2, [r7, #8] 80014d0: 187b adds r3, r7, r1 80014d2: 781b ldrb r3, [r3, #0] 80014d4: b25b sxtb r3, r3 80014d6: 0011 movs r1, r2 80014d8: 0018 movs r0, r3 80014da: f7ff ff5d bl 8001398 <__NVIC_SetPriority> } 80014de: 46c0 nop ; (mov r8, r8) 80014e0: 46bd mov sp, r7 80014e2: b004 add sp, #16 80014e4: bd80 pop {r7, pc} 080014e6 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80014e6: b580 push {r7, lr} 80014e8: b082 sub sp, #8 80014ea: af00 add r7, sp, #0 80014ec: 0002 movs r2, r0 80014ee: 1dfb adds r3, r7, #7 80014f0: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80014f2: 1dfb adds r3, r7, #7 80014f4: 781b ldrb r3, [r3, #0] 80014f6: b25b sxtb r3, r3 80014f8: 0018 movs r0, r3 80014fa: f7ff ff33 bl 8001364 <__NVIC_EnableIRQ> } 80014fe: 46c0 nop ; (mov r8, r8) 8001500: 46bd mov sp, r7 8001502: b002 add sp, #8 8001504: bd80 pop {r7, pc} 08001506 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001506: b580 push {r7, lr} 8001508: b082 sub sp, #8 800150a: af00 add r7, sp, #0 800150c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800150e: 687b ldr r3, [r7, #4] 8001510: 0018 movs r0, r3 8001512: f7ff ffaf bl 8001474 8001516: 0003 movs r3, r0 } 8001518: 0018 movs r0, r3 800151a: 46bd mov sp, r7 800151c: b002 add sp, #8 800151e: bd80 pop {r7, pc} 08001520 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001520: b580 push {r7, lr} 8001522: b086 sub sp, #24 8001524: af00 add r7, sp, #0 8001526: 6078 str r0, [r7, #4] 8001528: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800152a: 2300 movs r3, #0 800152c: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800152e: e14f b.n 80017d0 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8001530: 683b ldr r3, [r7, #0] 8001532: 681b ldr r3, [r3, #0] 8001534: 2101 movs r1, #1 8001536: 697a ldr r2, [r7, #20] 8001538: 4091 lsls r1, r2 800153a: 000a movs r2, r1 800153c: 4013 ands r3, r2 800153e: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8001540: 68fb ldr r3, [r7, #12] 8001542: 2b00 cmp r3, #0 8001544: d100 bne.n 8001548 8001546: e140 b.n 80017ca { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001548: 683b ldr r3, [r7, #0] 800154a: 685b ldr r3, [r3, #4] 800154c: 2203 movs r2, #3 800154e: 4013 ands r3, r2 8001550: 2b01 cmp r3, #1 8001552: d005 beq.n 8001560 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8001554: 683b ldr r3, [r7, #0] 8001556: 685b ldr r3, [r3, #4] 8001558: 2203 movs r2, #3 800155a: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 800155c: 2b02 cmp r3, #2 800155e: d130 bne.n 80015c2 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001560: 687b ldr r3, [r7, #4] 8001562: 689b ldr r3, [r3, #8] 8001564: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 8001566: 697b ldr r3, [r7, #20] 8001568: 005b lsls r3, r3, #1 800156a: 2203 movs r2, #3 800156c: 409a lsls r2, r3 800156e: 0013 movs r3, r2 8001570: 43da mvns r2, r3 8001572: 693b ldr r3, [r7, #16] 8001574: 4013 ands r3, r2 8001576: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8001578: 683b ldr r3, [r7, #0] 800157a: 68da ldr r2, [r3, #12] 800157c: 697b ldr r3, [r7, #20] 800157e: 005b lsls r3, r3, #1 8001580: 409a lsls r2, r3 8001582: 0013 movs r3, r2 8001584: 693a ldr r2, [r7, #16] 8001586: 4313 orrs r3, r2 8001588: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 800158a: 687b ldr r3, [r7, #4] 800158c: 693a ldr r2, [r7, #16] 800158e: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001590: 687b ldr r3, [r7, #4] 8001592: 685b ldr r3, [r3, #4] 8001594: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001596: 2201 movs r2, #1 8001598: 697b ldr r3, [r7, #20] 800159a: 409a lsls r2, r3 800159c: 0013 movs r3, r2 800159e: 43da mvns r2, r3 80015a0: 693b ldr r3, [r7, #16] 80015a2: 4013 ands r3, r2 80015a4: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80015a6: 683b ldr r3, [r7, #0] 80015a8: 685b ldr r3, [r3, #4] 80015aa: 091b lsrs r3, r3, #4 80015ac: 2201 movs r2, #1 80015ae: 401a ands r2, r3 80015b0: 697b ldr r3, [r7, #20] 80015b2: 409a lsls r2, r3 80015b4: 0013 movs r3, r2 80015b6: 693a ldr r2, [r7, #16] 80015b8: 4313 orrs r3, r2 80015ba: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80015bc: 687b ldr r3, [r7, #4] 80015be: 693a ldr r2, [r7, #16] 80015c0: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80015c2: 683b ldr r3, [r7, #0] 80015c4: 685b ldr r3, [r3, #4] 80015c6: 2203 movs r2, #3 80015c8: 4013 ands r3, r2 80015ca: 2b03 cmp r3, #3 80015cc: d017 beq.n 80015fe { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80015ce: 687b ldr r3, [r7, #4] 80015d0: 68db ldr r3, [r3, #12] 80015d2: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 80015d4: 697b ldr r3, [r7, #20] 80015d6: 005b lsls r3, r3, #1 80015d8: 2203 movs r2, #3 80015da: 409a lsls r2, r3 80015dc: 0013 movs r3, r2 80015de: 43da mvns r2, r3 80015e0: 693b ldr r3, [r7, #16] 80015e2: 4013 ands r3, r2 80015e4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 80015e6: 683b ldr r3, [r7, #0] 80015e8: 689a ldr r2, [r3, #8] 80015ea: 697b ldr r3, [r7, #20] 80015ec: 005b lsls r3, r3, #1 80015ee: 409a lsls r2, r3 80015f0: 0013 movs r3, r2 80015f2: 693a ldr r2, [r7, #16] 80015f4: 4313 orrs r3, r2 80015f6: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 80015f8: 687b ldr r3, [r7, #4] 80015fa: 693a ldr r2, [r7, #16] 80015fc: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80015fe: 683b ldr r3, [r7, #0] 8001600: 685b ldr r3, [r3, #4] 8001602: 2203 movs r2, #3 8001604: 4013 ands r3, r2 8001606: 2b02 cmp r3, #2 8001608: d123 bne.n 8001652 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 800160a: 697b ldr r3, [r7, #20] 800160c: 08da lsrs r2, r3, #3 800160e: 687b ldr r3, [r7, #4] 8001610: 3208 adds r2, #8 8001612: 0092 lsls r2, r2, #2 8001614: 58d3 ldr r3, [r2, r3] 8001616: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001618: 697b ldr r3, [r7, #20] 800161a: 2207 movs r2, #7 800161c: 4013 ands r3, r2 800161e: 009b lsls r3, r3, #2 8001620: 220f movs r2, #15 8001622: 409a lsls r2, r3 8001624: 0013 movs r3, r2 8001626: 43da mvns r2, r3 8001628: 693b ldr r3, [r7, #16] 800162a: 4013 ands r3, r2 800162c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 800162e: 683b ldr r3, [r7, #0] 8001630: 691a ldr r2, [r3, #16] 8001632: 697b ldr r3, [r7, #20] 8001634: 2107 movs r1, #7 8001636: 400b ands r3, r1 8001638: 009b lsls r3, r3, #2 800163a: 409a lsls r2, r3 800163c: 0013 movs r3, r2 800163e: 693a ldr r2, [r7, #16] 8001640: 4313 orrs r3, r2 8001642: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8001644: 697b ldr r3, [r7, #20] 8001646: 08da lsrs r2, r3, #3 8001648: 687b ldr r3, [r7, #4] 800164a: 3208 adds r2, #8 800164c: 0092 lsls r2, r2, #2 800164e: 6939 ldr r1, [r7, #16] 8001650: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001652: 687b ldr r3, [r7, #4] 8001654: 681b ldr r3, [r3, #0] 8001656: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8001658: 697b ldr r3, [r7, #20] 800165a: 005b lsls r3, r3, #1 800165c: 2203 movs r2, #3 800165e: 409a lsls r2, r3 8001660: 0013 movs r3, r2 8001662: 43da mvns r2, r3 8001664: 693b ldr r3, [r7, #16] 8001666: 4013 ands r3, r2 8001668: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 800166a: 683b ldr r3, [r7, #0] 800166c: 685b ldr r3, [r3, #4] 800166e: 2203 movs r2, #3 8001670: 401a ands r2, r3 8001672: 697b ldr r3, [r7, #20] 8001674: 005b lsls r3, r3, #1 8001676: 409a lsls r2, r3 8001678: 0013 movs r3, r2 800167a: 693a ldr r2, [r7, #16] 800167c: 4313 orrs r3, r2 800167e: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001680: 687b ldr r3, [r7, #4] 8001682: 693a ldr r2, [r7, #16] 8001684: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8001686: 683b ldr r3, [r7, #0] 8001688: 685a ldr r2, [r3, #4] 800168a: 23c0 movs r3, #192 ; 0xc0 800168c: 029b lsls r3, r3, #10 800168e: 4013 ands r3, r2 8001690: d100 bne.n 8001694 8001692: e09a b.n 80017ca { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001694: 4b54 ldr r3, [pc, #336] ; (80017e8 ) 8001696: 699a ldr r2, [r3, #24] 8001698: 4b53 ldr r3, [pc, #332] ; (80017e8 ) 800169a: 2101 movs r1, #1 800169c: 430a orrs r2, r1 800169e: 619a str r2, [r3, #24] 80016a0: 4b51 ldr r3, [pc, #324] ; (80017e8 ) 80016a2: 699b ldr r3, [r3, #24] 80016a4: 2201 movs r2, #1 80016a6: 4013 ands r3, r2 80016a8: 60bb str r3, [r7, #8] 80016aa: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 80016ac: 4a4f ldr r2, [pc, #316] ; (80017ec ) 80016ae: 697b ldr r3, [r7, #20] 80016b0: 089b lsrs r3, r3, #2 80016b2: 3302 adds r3, #2 80016b4: 009b lsls r3, r3, #2 80016b6: 589b ldr r3, [r3, r2] 80016b8: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80016ba: 697b ldr r3, [r7, #20] 80016bc: 2203 movs r2, #3 80016be: 4013 ands r3, r2 80016c0: 009b lsls r3, r3, #2 80016c2: 220f movs r2, #15 80016c4: 409a lsls r2, r3 80016c6: 0013 movs r3, r2 80016c8: 43da mvns r2, r3 80016ca: 693b ldr r3, [r7, #16] 80016cc: 4013 ands r3, r2 80016ce: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 80016d0: 687a ldr r2, [r7, #4] 80016d2: 2390 movs r3, #144 ; 0x90 80016d4: 05db lsls r3, r3, #23 80016d6: 429a cmp r2, r3 80016d8: d013 beq.n 8001702 80016da: 687b ldr r3, [r7, #4] 80016dc: 4a44 ldr r2, [pc, #272] ; (80017f0 ) 80016de: 4293 cmp r3, r2 80016e0: d00d beq.n 80016fe 80016e2: 687b ldr r3, [r7, #4] 80016e4: 4a43 ldr r2, [pc, #268] ; (80017f4 ) 80016e6: 4293 cmp r3, r2 80016e8: d007 beq.n 80016fa 80016ea: 687b ldr r3, [r7, #4] 80016ec: 4a42 ldr r2, [pc, #264] ; (80017f8 ) 80016ee: 4293 cmp r3, r2 80016f0: d101 bne.n 80016f6 80016f2: 2303 movs r3, #3 80016f4: e006 b.n 8001704 80016f6: 2305 movs r3, #5 80016f8: e004 b.n 8001704 80016fa: 2302 movs r3, #2 80016fc: e002 b.n 8001704 80016fe: 2301 movs r3, #1 8001700: e000 b.n 8001704 8001702: 2300 movs r3, #0 8001704: 697a ldr r2, [r7, #20] 8001706: 2103 movs r1, #3 8001708: 400a ands r2, r1 800170a: 0092 lsls r2, r2, #2 800170c: 4093 lsls r3, r2 800170e: 693a ldr r2, [r7, #16] 8001710: 4313 orrs r3, r2 8001712: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8001714: 4935 ldr r1, [pc, #212] ; (80017ec ) 8001716: 697b ldr r3, [r7, #20] 8001718: 089b lsrs r3, r3, #2 800171a: 3302 adds r3, #2 800171c: 009b lsls r3, r3, #2 800171e: 693a ldr r2, [r7, #16] 8001720: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001722: 4b36 ldr r3, [pc, #216] ; (80017fc ) 8001724: 681b ldr r3, [r3, #0] 8001726: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001728: 68fb ldr r3, [r7, #12] 800172a: 43da mvns r2, r3 800172c: 693b ldr r3, [r7, #16] 800172e: 4013 ands r3, r2 8001730: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8001732: 683b ldr r3, [r7, #0] 8001734: 685a ldr r2, [r3, #4] 8001736: 2380 movs r3, #128 ; 0x80 8001738: 025b lsls r3, r3, #9 800173a: 4013 ands r3, r2 800173c: d003 beq.n 8001746 { temp |= iocurrent; 800173e: 693a ldr r2, [r7, #16] 8001740: 68fb ldr r3, [r7, #12] 8001742: 4313 orrs r3, r2 8001744: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8001746: 4b2d ldr r3, [pc, #180] ; (80017fc ) 8001748: 693a ldr r2, [r7, #16] 800174a: 601a str r2, [r3, #0] temp = EXTI->EMR; 800174c: 4b2b ldr r3, [pc, #172] ; (80017fc ) 800174e: 685b ldr r3, [r3, #4] 8001750: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001752: 68fb ldr r3, [r7, #12] 8001754: 43da mvns r2, r3 8001756: 693b ldr r3, [r7, #16] 8001758: 4013 ands r3, r2 800175a: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 800175c: 683b ldr r3, [r7, #0] 800175e: 685a ldr r2, [r3, #4] 8001760: 2380 movs r3, #128 ; 0x80 8001762: 029b lsls r3, r3, #10 8001764: 4013 ands r3, r2 8001766: d003 beq.n 8001770 { temp |= iocurrent; 8001768: 693a ldr r2, [r7, #16] 800176a: 68fb ldr r3, [r7, #12] 800176c: 4313 orrs r3, r2 800176e: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8001770: 4b22 ldr r3, [pc, #136] ; (80017fc ) 8001772: 693a ldr r2, [r7, #16] 8001774: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8001776: 4b21 ldr r3, [pc, #132] ; (80017fc ) 8001778: 689b ldr r3, [r3, #8] 800177a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800177c: 68fb ldr r3, [r7, #12] 800177e: 43da mvns r2, r3 8001780: 693b ldr r3, [r7, #16] 8001782: 4013 ands r3, r2 8001784: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8001786: 683b ldr r3, [r7, #0] 8001788: 685a ldr r2, [r3, #4] 800178a: 2380 movs r3, #128 ; 0x80 800178c: 035b lsls r3, r3, #13 800178e: 4013 ands r3, r2 8001790: d003 beq.n 800179a { temp |= iocurrent; 8001792: 693a ldr r2, [r7, #16] 8001794: 68fb ldr r3, [r7, #12] 8001796: 4313 orrs r3, r2 8001798: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 800179a: 4b18 ldr r3, [pc, #96] ; (80017fc ) 800179c: 693a ldr r2, [r7, #16] 800179e: 609a str r2, [r3, #8] temp = EXTI->FTSR; 80017a0: 4b16 ldr r3, [pc, #88] ; (80017fc ) 80017a2: 68db ldr r3, [r3, #12] 80017a4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80017a6: 68fb ldr r3, [r7, #12] 80017a8: 43da mvns r2, r3 80017aa: 693b ldr r3, [r7, #16] 80017ac: 4013 ands r3, r2 80017ae: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 80017b0: 683b ldr r3, [r7, #0] 80017b2: 685a ldr r2, [r3, #4] 80017b4: 2380 movs r3, #128 ; 0x80 80017b6: 039b lsls r3, r3, #14 80017b8: 4013 ands r3, r2 80017ba: d003 beq.n 80017c4 { temp |= iocurrent; 80017bc: 693a ldr r2, [r7, #16] 80017be: 68fb ldr r3, [r7, #12] 80017c0: 4313 orrs r3, r2 80017c2: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 80017c4: 4b0d ldr r3, [pc, #52] ; (80017fc ) 80017c6: 693a ldr r2, [r7, #16] 80017c8: 60da str r2, [r3, #12] } } position++; 80017ca: 697b ldr r3, [r7, #20] 80017cc: 3301 adds r3, #1 80017ce: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 80017d0: 683b ldr r3, [r7, #0] 80017d2: 681a ldr r2, [r3, #0] 80017d4: 697b ldr r3, [r7, #20] 80017d6: 40da lsrs r2, r3 80017d8: 1e13 subs r3, r2, #0 80017da: d000 beq.n 80017de 80017dc: e6a8 b.n 8001530 } } 80017de: 46c0 nop ; (mov r8, r8) 80017e0: 46c0 nop ; (mov r8, r8) 80017e2: 46bd mov sp, r7 80017e4: b006 add sp, #24 80017e6: bd80 pop {r7, pc} 80017e8: 40021000 .word 0x40021000 80017ec: 40010000 .word 0x40010000 80017f0: 48000400 .word 0x48000400 80017f4: 48000800 .word 0x48000800 80017f8: 48000c00 .word 0x48000c00 80017fc: 40010400 .word 0x40010400 08001800 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001800: b580 push {r7, lr} 8001802: b084 sub sp, #16 8001804: af00 add r7, sp, #0 8001806: 6078 str r0, [r7, #4] 8001808: 000a movs r2, r1 800180a: 1cbb adds r3, r7, #2 800180c: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800180e: 687b ldr r3, [r7, #4] 8001810: 691b ldr r3, [r3, #16] 8001812: 1cba adds r2, r7, #2 8001814: 8812 ldrh r2, [r2, #0] 8001816: 4013 ands r3, r2 8001818: d004 beq.n 8001824 { bitstatus = GPIO_PIN_SET; 800181a: 230f movs r3, #15 800181c: 18fb adds r3, r7, r3 800181e: 2201 movs r2, #1 8001820: 701a strb r2, [r3, #0] 8001822: e003 b.n 800182c } else { bitstatus = GPIO_PIN_RESET; 8001824: 230f movs r3, #15 8001826: 18fb adds r3, r7, r3 8001828: 2200 movs r2, #0 800182a: 701a strb r2, [r3, #0] } return bitstatus; 800182c: 230f movs r3, #15 800182e: 18fb adds r3, r7, r3 8001830: 781b ldrb r3, [r3, #0] } 8001832: 0018 movs r0, r3 8001834: 46bd mov sp, r7 8001836: b004 add sp, #16 8001838: bd80 pop {r7, pc} 0800183a : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800183a: b580 push {r7, lr} 800183c: b082 sub sp, #8 800183e: af00 add r7, sp, #0 8001840: 6078 str r0, [r7, #4] 8001842: 0008 movs r0, r1 8001844: 0011 movs r1, r2 8001846: 1cbb adds r3, r7, #2 8001848: 1c02 adds r2, r0, #0 800184a: 801a strh r2, [r3, #0] 800184c: 1c7b adds r3, r7, #1 800184e: 1c0a adds r2, r1, #0 8001850: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001852: 1c7b adds r3, r7, #1 8001854: 781b ldrb r3, [r3, #0] 8001856: 2b00 cmp r3, #0 8001858: d004 beq.n 8001864 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 800185a: 1cbb adds r3, r7, #2 800185c: 881a ldrh r2, [r3, #0] 800185e: 687b ldr r3, [r7, #4] 8001860: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8001862: e003 b.n 800186c GPIOx->BRR = (uint32_t)GPIO_Pin; 8001864: 1cbb adds r3, r7, #2 8001866: 881a ldrh r2, [r3, #0] 8001868: 687b ldr r3, [r7, #4] 800186a: 629a str r2, [r3, #40] ; 0x28 } 800186c: 46c0 nop ; (mov r8, r8) 800186e: 46bd mov sp, r7 8001870: b002 add sp, #8 8001872: bd80 pop {r7, pc} 08001874 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8001874: b580 push {r7, lr} 8001876: b082 sub sp, #8 8001878: af00 add r7, sp, #0 800187a: 0002 movs r2, r0 800187c: 1dbb adds r3, r7, #6 800187e: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 8001880: 4b09 ldr r3, [pc, #36] ; (80018a8 ) 8001882: 695b ldr r3, [r3, #20] 8001884: 1dba adds r2, r7, #6 8001886: 8812 ldrh r2, [r2, #0] 8001888: 4013 ands r3, r2 800188a: d008 beq.n 800189e { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800188c: 4b06 ldr r3, [pc, #24] ; (80018a8 ) 800188e: 1dba adds r2, r7, #6 8001890: 8812 ldrh r2, [r2, #0] 8001892: 615a str r2, [r3, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 8001894: 1dbb adds r3, r7, #6 8001896: 881b ldrh r3, [r3, #0] 8001898: 0018 movs r0, r3 800189a: f002 f98b bl 8003bb4 } } 800189e: 46c0 nop ; (mov r8, r8) 80018a0: 46bd mov sp, r7 80018a2: b002 add sp, #8 80018a4: bd80 pop {r7, pc} 80018a6: 46c0 nop ; (mov r8, r8) 80018a8: 40010400 .word 0x40010400 080018ac : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80018ac: b580 push {r7, lr} 80018ae: b088 sub sp, #32 80018b0: af00 add r7, sp, #0 80018b2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 80018b4: 687b ldr r3, [r7, #4] 80018b6: 2b00 cmp r3, #0 80018b8: d101 bne.n 80018be { return HAL_ERROR; 80018ba: 2301 movs r3, #1 80018bc: e301 b.n 8001ec2 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80018be: 687b ldr r3, [r7, #4] 80018c0: 681b ldr r3, [r3, #0] 80018c2: 2201 movs r2, #1 80018c4: 4013 ands r3, r2 80018c6: d100 bne.n 80018ca 80018c8: e08d b.n 80019e6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80018ca: 4bc3 ldr r3, [pc, #780] ; (8001bd8 ) 80018cc: 685b ldr r3, [r3, #4] 80018ce: 220c movs r2, #12 80018d0: 4013 ands r3, r2 80018d2: 2b04 cmp r3, #4 80018d4: d00e beq.n 80018f4 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80018d6: 4bc0 ldr r3, [pc, #768] ; (8001bd8 ) 80018d8: 685b ldr r3, [r3, #4] 80018da: 220c movs r2, #12 80018dc: 4013 ands r3, r2 80018de: 2b08 cmp r3, #8 80018e0: d116 bne.n 8001910 80018e2: 4bbd ldr r3, [pc, #756] ; (8001bd8 ) 80018e4: 685a ldr r2, [r3, #4] 80018e6: 2380 movs r3, #128 ; 0x80 80018e8: 025b lsls r3, r3, #9 80018ea: 401a ands r2, r3 80018ec: 2380 movs r3, #128 ; 0x80 80018ee: 025b lsls r3, r3, #9 80018f0: 429a cmp r2, r3 80018f2: d10d bne.n 8001910 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80018f4: 4bb8 ldr r3, [pc, #736] ; (8001bd8 ) 80018f6: 681a ldr r2, [r3, #0] 80018f8: 2380 movs r3, #128 ; 0x80 80018fa: 029b lsls r3, r3, #10 80018fc: 4013 ands r3, r2 80018fe: d100 bne.n 8001902 8001900: e070 b.n 80019e4 8001902: 687b ldr r3, [r7, #4] 8001904: 685b ldr r3, [r3, #4] 8001906: 2b00 cmp r3, #0 8001908: d000 beq.n 800190c 800190a: e06b b.n 80019e4 { return HAL_ERROR; 800190c: 2301 movs r3, #1 800190e: e2d8 b.n 8001ec2 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001910: 687b ldr r3, [r7, #4] 8001912: 685b ldr r3, [r3, #4] 8001914: 2b01 cmp r3, #1 8001916: d107 bne.n 8001928 8001918: 4baf ldr r3, [pc, #700] ; (8001bd8 ) 800191a: 681a ldr r2, [r3, #0] 800191c: 4bae ldr r3, [pc, #696] ; (8001bd8 ) 800191e: 2180 movs r1, #128 ; 0x80 8001920: 0249 lsls r1, r1, #9 8001922: 430a orrs r2, r1 8001924: 601a str r2, [r3, #0] 8001926: e02f b.n 8001988 8001928: 687b ldr r3, [r7, #4] 800192a: 685b ldr r3, [r3, #4] 800192c: 2b00 cmp r3, #0 800192e: d10c bne.n 800194a 8001930: 4ba9 ldr r3, [pc, #676] ; (8001bd8 ) 8001932: 681a ldr r2, [r3, #0] 8001934: 4ba8 ldr r3, [pc, #672] ; (8001bd8 ) 8001936: 49a9 ldr r1, [pc, #676] ; (8001bdc ) 8001938: 400a ands r2, r1 800193a: 601a str r2, [r3, #0] 800193c: 4ba6 ldr r3, [pc, #664] ; (8001bd8 ) 800193e: 681a ldr r2, [r3, #0] 8001940: 4ba5 ldr r3, [pc, #660] ; (8001bd8 ) 8001942: 49a7 ldr r1, [pc, #668] ; (8001be0 ) 8001944: 400a ands r2, r1 8001946: 601a str r2, [r3, #0] 8001948: e01e b.n 8001988 800194a: 687b ldr r3, [r7, #4] 800194c: 685b ldr r3, [r3, #4] 800194e: 2b05 cmp r3, #5 8001950: d10e bne.n 8001970 8001952: 4ba1 ldr r3, [pc, #644] ; (8001bd8 ) 8001954: 681a ldr r2, [r3, #0] 8001956: 4ba0 ldr r3, [pc, #640] ; (8001bd8 ) 8001958: 2180 movs r1, #128 ; 0x80 800195a: 02c9 lsls r1, r1, #11 800195c: 430a orrs r2, r1 800195e: 601a str r2, [r3, #0] 8001960: 4b9d ldr r3, [pc, #628] ; (8001bd8 ) 8001962: 681a ldr r2, [r3, #0] 8001964: 4b9c ldr r3, [pc, #624] ; (8001bd8 ) 8001966: 2180 movs r1, #128 ; 0x80 8001968: 0249 lsls r1, r1, #9 800196a: 430a orrs r2, r1 800196c: 601a str r2, [r3, #0] 800196e: e00b b.n 8001988 8001970: 4b99 ldr r3, [pc, #612] ; (8001bd8 ) 8001972: 681a ldr r2, [r3, #0] 8001974: 4b98 ldr r3, [pc, #608] ; (8001bd8 ) 8001976: 4999 ldr r1, [pc, #612] ; (8001bdc ) 8001978: 400a ands r2, r1 800197a: 601a str r2, [r3, #0] 800197c: 4b96 ldr r3, [pc, #600] ; (8001bd8 ) 800197e: 681a ldr r2, [r3, #0] 8001980: 4b95 ldr r3, [pc, #596] ; (8001bd8 ) 8001982: 4997 ldr r1, [pc, #604] ; (8001be0 ) 8001984: 400a ands r2, r1 8001986: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001988: 687b ldr r3, [r7, #4] 800198a: 685b ldr r3, [r3, #4] 800198c: 2b00 cmp r3, #0 800198e: d014 beq.n 80019ba { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001990: f7ff f82e bl 80009f0 8001994: 0003 movs r3, r0 8001996: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001998: e008 b.n 80019ac { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 800199a: f7ff f829 bl 80009f0 800199e: 0002 movs r2, r0 80019a0: 69bb ldr r3, [r7, #24] 80019a2: 1ad3 subs r3, r2, r3 80019a4: 2b64 cmp r3, #100 ; 0x64 80019a6: d901 bls.n 80019ac { return HAL_TIMEOUT; 80019a8: 2303 movs r3, #3 80019aa: e28a b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80019ac: 4b8a ldr r3, [pc, #552] ; (8001bd8 ) 80019ae: 681a ldr r2, [r3, #0] 80019b0: 2380 movs r3, #128 ; 0x80 80019b2: 029b lsls r3, r3, #10 80019b4: 4013 ands r3, r2 80019b6: d0f0 beq.n 800199a 80019b8: e015 b.n 80019e6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80019ba: f7ff f819 bl 80009f0 80019be: 0003 movs r3, r0 80019c0: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80019c2: e008 b.n 80019d6 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80019c4: f7ff f814 bl 80009f0 80019c8: 0002 movs r2, r0 80019ca: 69bb ldr r3, [r7, #24] 80019cc: 1ad3 subs r3, r2, r3 80019ce: 2b64 cmp r3, #100 ; 0x64 80019d0: d901 bls.n 80019d6 { return HAL_TIMEOUT; 80019d2: 2303 movs r3, #3 80019d4: e275 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80019d6: 4b80 ldr r3, [pc, #512] ; (8001bd8 ) 80019d8: 681a ldr r2, [r3, #0] 80019da: 2380 movs r3, #128 ; 0x80 80019dc: 029b lsls r3, r3, #10 80019de: 4013 ands r3, r2 80019e0: d1f0 bne.n 80019c4 80019e2: e000 b.n 80019e6 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80019e4: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80019e6: 687b ldr r3, [r7, #4] 80019e8: 681b ldr r3, [r3, #0] 80019ea: 2202 movs r2, #2 80019ec: 4013 ands r3, r2 80019ee: d100 bne.n 80019f2 80019f0: e069 b.n 8001ac6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80019f2: 4b79 ldr r3, [pc, #484] ; (8001bd8 ) 80019f4: 685b ldr r3, [r3, #4] 80019f6: 220c movs r2, #12 80019f8: 4013 ands r3, r2 80019fa: d00b beq.n 8001a14 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 80019fc: 4b76 ldr r3, [pc, #472] ; (8001bd8 ) 80019fe: 685b ldr r3, [r3, #4] 8001a00: 220c movs r2, #12 8001a02: 4013 ands r3, r2 8001a04: 2b08 cmp r3, #8 8001a06: d11c bne.n 8001a42 8001a08: 4b73 ldr r3, [pc, #460] ; (8001bd8 ) 8001a0a: 685a ldr r2, [r3, #4] 8001a0c: 2380 movs r3, #128 ; 0x80 8001a0e: 025b lsls r3, r3, #9 8001a10: 4013 ands r3, r2 8001a12: d116 bne.n 8001a42 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001a14: 4b70 ldr r3, [pc, #448] ; (8001bd8 ) 8001a16: 681b ldr r3, [r3, #0] 8001a18: 2202 movs r2, #2 8001a1a: 4013 ands r3, r2 8001a1c: d005 beq.n 8001a2a 8001a1e: 687b ldr r3, [r7, #4] 8001a20: 68db ldr r3, [r3, #12] 8001a22: 2b01 cmp r3, #1 8001a24: d001 beq.n 8001a2a { return HAL_ERROR; 8001a26: 2301 movs r3, #1 8001a28: e24b b.n 8001ec2 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001a2a: 4b6b ldr r3, [pc, #428] ; (8001bd8 ) 8001a2c: 681b ldr r3, [r3, #0] 8001a2e: 22f8 movs r2, #248 ; 0xf8 8001a30: 4393 bics r3, r2 8001a32: 0019 movs r1, r3 8001a34: 687b ldr r3, [r7, #4] 8001a36: 691b ldr r3, [r3, #16] 8001a38: 00da lsls r2, r3, #3 8001a3a: 4b67 ldr r3, [pc, #412] ; (8001bd8 ) 8001a3c: 430a orrs r2, r1 8001a3e: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001a40: e041 b.n 8001ac6 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001a42: 687b ldr r3, [r7, #4] 8001a44: 68db ldr r3, [r3, #12] 8001a46: 2b00 cmp r3, #0 8001a48: d024 beq.n 8001a94 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001a4a: 4b63 ldr r3, [pc, #396] ; (8001bd8 ) 8001a4c: 681a ldr r2, [r3, #0] 8001a4e: 4b62 ldr r3, [pc, #392] ; (8001bd8 ) 8001a50: 2101 movs r1, #1 8001a52: 430a orrs r2, r1 8001a54: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a56: f7fe ffcb bl 80009f0 8001a5a: 0003 movs r3, r0 8001a5c: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001a5e: e008 b.n 8001a72 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001a60: f7fe ffc6 bl 80009f0 8001a64: 0002 movs r2, r0 8001a66: 69bb ldr r3, [r7, #24] 8001a68: 1ad3 subs r3, r2, r3 8001a6a: 2b02 cmp r3, #2 8001a6c: d901 bls.n 8001a72 { return HAL_TIMEOUT; 8001a6e: 2303 movs r3, #3 8001a70: e227 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001a72: 4b59 ldr r3, [pc, #356] ; (8001bd8 ) 8001a74: 681b ldr r3, [r3, #0] 8001a76: 2202 movs r2, #2 8001a78: 4013 ands r3, r2 8001a7a: d0f1 beq.n 8001a60 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001a7c: 4b56 ldr r3, [pc, #344] ; (8001bd8 ) 8001a7e: 681b ldr r3, [r3, #0] 8001a80: 22f8 movs r2, #248 ; 0xf8 8001a82: 4393 bics r3, r2 8001a84: 0019 movs r1, r3 8001a86: 687b ldr r3, [r7, #4] 8001a88: 691b ldr r3, [r3, #16] 8001a8a: 00da lsls r2, r3, #3 8001a8c: 4b52 ldr r3, [pc, #328] ; (8001bd8 ) 8001a8e: 430a orrs r2, r1 8001a90: 601a str r2, [r3, #0] 8001a92: e018 b.n 8001ac6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001a94: 4b50 ldr r3, [pc, #320] ; (8001bd8 ) 8001a96: 681a ldr r2, [r3, #0] 8001a98: 4b4f ldr r3, [pc, #316] ; (8001bd8 ) 8001a9a: 2101 movs r1, #1 8001a9c: 438a bics r2, r1 8001a9e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001aa0: f7fe ffa6 bl 80009f0 8001aa4: 0003 movs r3, r0 8001aa6: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001aa8: e008 b.n 8001abc { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001aaa: f7fe ffa1 bl 80009f0 8001aae: 0002 movs r2, r0 8001ab0: 69bb ldr r3, [r7, #24] 8001ab2: 1ad3 subs r3, r2, r3 8001ab4: 2b02 cmp r3, #2 8001ab6: d901 bls.n 8001abc { return HAL_TIMEOUT; 8001ab8: 2303 movs r3, #3 8001aba: e202 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001abc: 4b46 ldr r3, [pc, #280] ; (8001bd8 ) 8001abe: 681b ldr r3, [r3, #0] 8001ac0: 2202 movs r2, #2 8001ac2: 4013 ands r3, r2 8001ac4: d1f1 bne.n 8001aaa } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001ac6: 687b ldr r3, [r7, #4] 8001ac8: 681b ldr r3, [r3, #0] 8001aca: 2208 movs r2, #8 8001acc: 4013 ands r3, r2 8001ace: d036 beq.n 8001b3e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001ad0: 687b ldr r3, [r7, #4] 8001ad2: 69db ldr r3, [r3, #28] 8001ad4: 2b00 cmp r3, #0 8001ad6: d019 beq.n 8001b0c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001ad8: 4b3f ldr r3, [pc, #252] ; (8001bd8 ) 8001ada: 6a5a ldr r2, [r3, #36] ; 0x24 8001adc: 4b3e ldr r3, [pc, #248] ; (8001bd8 ) 8001ade: 2101 movs r1, #1 8001ae0: 430a orrs r2, r1 8001ae2: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001ae4: f7fe ff84 bl 80009f0 8001ae8: 0003 movs r3, r0 8001aea: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001aec: e008 b.n 8001b00 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001aee: f7fe ff7f bl 80009f0 8001af2: 0002 movs r2, r0 8001af4: 69bb ldr r3, [r7, #24] 8001af6: 1ad3 subs r3, r2, r3 8001af8: 2b02 cmp r3, #2 8001afa: d901 bls.n 8001b00 { return HAL_TIMEOUT; 8001afc: 2303 movs r3, #3 8001afe: e1e0 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001b00: 4b35 ldr r3, [pc, #212] ; (8001bd8 ) 8001b02: 6a5b ldr r3, [r3, #36] ; 0x24 8001b04: 2202 movs r2, #2 8001b06: 4013 ands r3, r2 8001b08: d0f1 beq.n 8001aee 8001b0a: e018 b.n 8001b3e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001b0c: 4b32 ldr r3, [pc, #200] ; (8001bd8 ) 8001b0e: 6a5a ldr r2, [r3, #36] ; 0x24 8001b10: 4b31 ldr r3, [pc, #196] ; (8001bd8 ) 8001b12: 2101 movs r1, #1 8001b14: 438a bics r2, r1 8001b16: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b18: f7fe ff6a bl 80009f0 8001b1c: 0003 movs r3, r0 8001b1e: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001b20: e008 b.n 8001b34 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001b22: f7fe ff65 bl 80009f0 8001b26: 0002 movs r2, r0 8001b28: 69bb ldr r3, [r7, #24] 8001b2a: 1ad3 subs r3, r2, r3 8001b2c: 2b02 cmp r3, #2 8001b2e: d901 bls.n 8001b34 { return HAL_TIMEOUT; 8001b30: 2303 movs r3, #3 8001b32: e1c6 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001b34: 4b28 ldr r3, [pc, #160] ; (8001bd8 ) 8001b36: 6a5b ldr r3, [r3, #36] ; 0x24 8001b38: 2202 movs r2, #2 8001b3a: 4013 ands r3, r2 8001b3c: d1f1 bne.n 8001b22 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001b3e: 687b ldr r3, [r7, #4] 8001b40: 681b ldr r3, [r3, #0] 8001b42: 2204 movs r2, #4 8001b44: 4013 ands r3, r2 8001b46: d100 bne.n 8001b4a 8001b48: e0b4 b.n 8001cb4 { FlagStatus pwrclkchanged = RESET; 8001b4a: 201f movs r0, #31 8001b4c: 183b adds r3, r7, r0 8001b4e: 2200 movs r2, #0 8001b50: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001b52: 4b21 ldr r3, [pc, #132] ; (8001bd8 ) 8001b54: 69da ldr r2, [r3, #28] 8001b56: 2380 movs r3, #128 ; 0x80 8001b58: 055b lsls r3, r3, #21 8001b5a: 4013 ands r3, r2 8001b5c: d110 bne.n 8001b80 { __HAL_RCC_PWR_CLK_ENABLE(); 8001b5e: 4b1e ldr r3, [pc, #120] ; (8001bd8 ) 8001b60: 69da ldr r2, [r3, #28] 8001b62: 4b1d ldr r3, [pc, #116] ; (8001bd8 ) 8001b64: 2180 movs r1, #128 ; 0x80 8001b66: 0549 lsls r1, r1, #21 8001b68: 430a orrs r2, r1 8001b6a: 61da str r2, [r3, #28] 8001b6c: 4b1a ldr r3, [pc, #104] ; (8001bd8 ) 8001b6e: 69da ldr r2, [r3, #28] 8001b70: 2380 movs r3, #128 ; 0x80 8001b72: 055b lsls r3, r3, #21 8001b74: 4013 ands r3, r2 8001b76: 60fb str r3, [r7, #12] 8001b78: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8001b7a: 183b adds r3, r7, r0 8001b7c: 2201 movs r2, #1 8001b7e: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001b80: 4b18 ldr r3, [pc, #96] ; (8001be4 ) 8001b82: 681a ldr r2, [r3, #0] 8001b84: 2380 movs r3, #128 ; 0x80 8001b86: 005b lsls r3, r3, #1 8001b88: 4013 ands r3, r2 8001b8a: d11a bne.n 8001bc2 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001b8c: 4b15 ldr r3, [pc, #84] ; (8001be4 ) 8001b8e: 681a ldr r2, [r3, #0] 8001b90: 4b14 ldr r3, [pc, #80] ; (8001be4 ) 8001b92: 2180 movs r1, #128 ; 0x80 8001b94: 0049 lsls r1, r1, #1 8001b96: 430a orrs r2, r1 8001b98: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001b9a: f7fe ff29 bl 80009f0 8001b9e: 0003 movs r3, r0 8001ba0: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001ba2: e008 b.n 8001bb6 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001ba4: f7fe ff24 bl 80009f0 8001ba8: 0002 movs r2, r0 8001baa: 69bb ldr r3, [r7, #24] 8001bac: 1ad3 subs r3, r2, r3 8001bae: 2b64 cmp r3, #100 ; 0x64 8001bb0: d901 bls.n 8001bb6 { return HAL_TIMEOUT; 8001bb2: 2303 movs r3, #3 8001bb4: e185 b.n 8001ec2 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001bb6: 4b0b ldr r3, [pc, #44] ; (8001be4 ) 8001bb8: 681a ldr r2, [r3, #0] 8001bba: 2380 movs r3, #128 ; 0x80 8001bbc: 005b lsls r3, r3, #1 8001bbe: 4013 ands r3, r2 8001bc0: d0f0 beq.n 8001ba4 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001bc2: 687b ldr r3, [r7, #4] 8001bc4: 689b ldr r3, [r3, #8] 8001bc6: 2b01 cmp r3, #1 8001bc8: d10e bne.n 8001be8 8001bca: 4b03 ldr r3, [pc, #12] ; (8001bd8 ) 8001bcc: 6a1a ldr r2, [r3, #32] 8001bce: 4b02 ldr r3, [pc, #8] ; (8001bd8 ) 8001bd0: 2101 movs r1, #1 8001bd2: 430a orrs r2, r1 8001bd4: 621a str r2, [r3, #32] 8001bd6: e035 b.n 8001c44 8001bd8: 40021000 .word 0x40021000 8001bdc: fffeffff .word 0xfffeffff 8001be0: fffbffff .word 0xfffbffff 8001be4: 40007000 .word 0x40007000 8001be8: 687b ldr r3, [r7, #4] 8001bea: 689b ldr r3, [r3, #8] 8001bec: 2b00 cmp r3, #0 8001bee: d10c bne.n 8001c0a 8001bf0: 4bb6 ldr r3, [pc, #728] ; (8001ecc ) 8001bf2: 6a1a ldr r2, [r3, #32] 8001bf4: 4bb5 ldr r3, [pc, #724] ; (8001ecc ) 8001bf6: 2101 movs r1, #1 8001bf8: 438a bics r2, r1 8001bfa: 621a str r2, [r3, #32] 8001bfc: 4bb3 ldr r3, [pc, #716] ; (8001ecc ) 8001bfe: 6a1a ldr r2, [r3, #32] 8001c00: 4bb2 ldr r3, [pc, #712] ; (8001ecc ) 8001c02: 2104 movs r1, #4 8001c04: 438a bics r2, r1 8001c06: 621a str r2, [r3, #32] 8001c08: e01c b.n 8001c44 8001c0a: 687b ldr r3, [r7, #4] 8001c0c: 689b ldr r3, [r3, #8] 8001c0e: 2b05 cmp r3, #5 8001c10: d10c bne.n 8001c2c 8001c12: 4bae ldr r3, [pc, #696] ; (8001ecc ) 8001c14: 6a1a ldr r2, [r3, #32] 8001c16: 4bad ldr r3, [pc, #692] ; (8001ecc ) 8001c18: 2104 movs r1, #4 8001c1a: 430a orrs r2, r1 8001c1c: 621a str r2, [r3, #32] 8001c1e: 4bab ldr r3, [pc, #684] ; (8001ecc ) 8001c20: 6a1a ldr r2, [r3, #32] 8001c22: 4baa ldr r3, [pc, #680] ; (8001ecc ) 8001c24: 2101 movs r1, #1 8001c26: 430a orrs r2, r1 8001c28: 621a str r2, [r3, #32] 8001c2a: e00b b.n 8001c44 8001c2c: 4ba7 ldr r3, [pc, #668] ; (8001ecc ) 8001c2e: 6a1a ldr r2, [r3, #32] 8001c30: 4ba6 ldr r3, [pc, #664] ; (8001ecc ) 8001c32: 2101 movs r1, #1 8001c34: 438a bics r2, r1 8001c36: 621a str r2, [r3, #32] 8001c38: 4ba4 ldr r3, [pc, #656] ; (8001ecc ) 8001c3a: 6a1a ldr r2, [r3, #32] 8001c3c: 4ba3 ldr r3, [pc, #652] ; (8001ecc ) 8001c3e: 2104 movs r1, #4 8001c40: 438a bics r2, r1 8001c42: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001c44: 687b ldr r3, [r7, #4] 8001c46: 689b ldr r3, [r3, #8] 8001c48: 2b00 cmp r3, #0 8001c4a: d014 beq.n 8001c76 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001c4c: f7fe fed0 bl 80009f0 8001c50: 0003 movs r3, r0 8001c52: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001c54: e009 b.n 8001c6a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001c56: f7fe fecb bl 80009f0 8001c5a: 0002 movs r2, r0 8001c5c: 69bb ldr r3, [r7, #24] 8001c5e: 1ad3 subs r3, r2, r3 8001c60: 4a9b ldr r2, [pc, #620] ; (8001ed0 ) 8001c62: 4293 cmp r3, r2 8001c64: d901 bls.n 8001c6a { return HAL_TIMEOUT; 8001c66: 2303 movs r3, #3 8001c68: e12b b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001c6a: 4b98 ldr r3, [pc, #608] ; (8001ecc ) 8001c6c: 6a1b ldr r3, [r3, #32] 8001c6e: 2202 movs r2, #2 8001c70: 4013 ands r3, r2 8001c72: d0f0 beq.n 8001c56 8001c74: e013 b.n 8001c9e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001c76: f7fe febb bl 80009f0 8001c7a: 0003 movs r3, r0 8001c7c: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001c7e: e009 b.n 8001c94 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001c80: f7fe feb6 bl 80009f0 8001c84: 0002 movs r2, r0 8001c86: 69bb ldr r3, [r7, #24] 8001c88: 1ad3 subs r3, r2, r3 8001c8a: 4a91 ldr r2, [pc, #580] ; (8001ed0 ) 8001c8c: 4293 cmp r3, r2 8001c8e: d901 bls.n 8001c94 { return HAL_TIMEOUT; 8001c90: 2303 movs r3, #3 8001c92: e116 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001c94: 4b8d ldr r3, [pc, #564] ; (8001ecc ) 8001c96: 6a1b ldr r3, [r3, #32] 8001c98: 2202 movs r2, #2 8001c9a: 4013 ands r3, r2 8001c9c: d1f0 bne.n 8001c80 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8001c9e: 231f movs r3, #31 8001ca0: 18fb adds r3, r7, r3 8001ca2: 781b ldrb r3, [r3, #0] 8001ca4: 2b01 cmp r3, #1 8001ca6: d105 bne.n 8001cb4 { __HAL_RCC_PWR_CLK_DISABLE(); 8001ca8: 4b88 ldr r3, [pc, #544] ; (8001ecc ) 8001caa: 69da ldr r2, [r3, #28] 8001cac: 4b87 ldr r3, [pc, #540] ; (8001ecc ) 8001cae: 4989 ldr r1, [pc, #548] ; (8001ed4 ) 8001cb0: 400a ands r2, r1 8001cb2: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8001cb4: 687b ldr r3, [r7, #4] 8001cb6: 681b ldr r3, [r3, #0] 8001cb8: 2210 movs r2, #16 8001cba: 4013 ands r3, r2 8001cbc: d063 beq.n 8001d86 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 8001cbe: 687b ldr r3, [r7, #4] 8001cc0: 695b ldr r3, [r3, #20] 8001cc2: 2b01 cmp r3, #1 8001cc4: d12a bne.n 8001d1c { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001cc6: 4b81 ldr r3, [pc, #516] ; (8001ecc ) 8001cc8: 6b5a ldr r2, [r3, #52] ; 0x34 8001cca: 4b80 ldr r3, [pc, #512] ; (8001ecc ) 8001ccc: 2104 movs r1, #4 8001cce: 430a orrs r2, r1 8001cd0: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 8001cd2: 4b7e ldr r3, [pc, #504] ; (8001ecc ) 8001cd4: 6b5a ldr r2, [r3, #52] ; 0x34 8001cd6: 4b7d ldr r3, [pc, #500] ; (8001ecc ) 8001cd8: 2101 movs r1, #1 8001cda: 430a orrs r2, r1 8001cdc: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001cde: f7fe fe87 bl 80009f0 8001ce2: 0003 movs r3, r0 8001ce4: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001ce6: e008 b.n 8001cfa { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001ce8: f7fe fe82 bl 80009f0 8001cec: 0002 movs r2, r0 8001cee: 69bb ldr r3, [r7, #24] 8001cf0: 1ad3 subs r3, r2, r3 8001cf2: 2b02 cmp r3, #2 8001cf4: d901 bls.n 8001cfa { return HAL_TIMEOUT; 8001cf6: 2303 movs r3, #3 8001cf8: e0e3 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001cfa: 4b74 ldr r3, [pc, #464] ; (8001ecc ) 8001cfc: 6b5b ldr r3, [r3, #52] ; 0x34 8001cfe: 2202 movs r2, #2 8001d00: 4013 ands r3, r2 8001d02: d0f1 beq.n 8001ce8 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001d04: 4b71 ldr r3, [pc, #452] ; (8001ecc ) 8001d06: 6b5b ldr r3, [r3, #52] ; 0x34 8001d08: 22f8 movs r2, #248 ; 0xf8 8001d0a: 4393 bics r3, r2 8001d0c: 0019 movs r1, r3 8001d0e: 687b ldr r3, [r7, #4] 8001d10: 699b ldr r3, [r3, #24] 8001d12: 00da lsls r2, r3, #3 8001d14: 4b6d ldr r3, [pc, #436] ; (8001ecc ) 8001d16: 430a orrs r2, r1 8001d18: 635a str r2, [r3, #52] ; 0x34 8001d1a: e034 b.n 8001d86 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8001d1c: 687b ldr r3, [r7, #4] 8001d1e: 695b ldr r3, [r3, #20] 8001d20: 3305 adds r3, #5 8001d22: d111 bne.n 8001d48 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001d24: 4b69 ldr r3, [pc, #420] ; (8001ecc ) 8001d26: 6b5a ldr r2, [r3, #52] ; 0x34 8001d28: 4b68 ldr r3, [pc, #416] ; (8001ecc ) 8001d2a: 2104 movs r1, #4 8001d2c: 438a bics r2, r1 8001d2e: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001d30: 4b66 ldr r3, [pc, #408] ; (8001ecc ) 8001d32: 6b5b ldr r3, [r3, #52] ; 0x34 8001d34: 22f8 movs r2, #248 ; 0xf8 8001d36: 4393 bics r3, r2 8001d38: 0019 movs r1, r3 8001d3a: 687b ldr r3, [r7, #4] 8001d3c: 699b ldr r3, [r3, #24] 8001d3e: 00da lsls r2, r3, #3 8001d40: 4b62 ldr r3, [pc, #392] ; (8001ecc ) 8001d42: 430a orrs r2, r1 8001d44: 635a str r2, [r3, #52] ; 0x34 8001d46: e01e b.n 8001d86 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001d48: 4b60 ldr r3, [pc, #384] ; (8001ecc ) 8001d4a: 6b5a ldr r2, [r3, #52] ; 0x34 8001d4c: 4b5f ldr r3, [pc, #380] ; (8001ecc ) 8001d4e: 2104 movs r1, #4 8001d50: 430a orrs r2, r1 8001d52: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001d54: 4b5d ldr r3, [pc, #372] ; (8001ecc ) 8001d56: 6b5a ldr r2, [r3, #52] ; 0x34 8001d58: 4b5c ldr r3, [pc, #368] ; (8001ecc ) 8001d5a: 2101 movs r1, #1 8001d5c: 438a bics r2, r1 8001d5e: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001d60: f7fe fe46 bl 80009f0 8001d64: 0003 movs r3, r0 8001d66: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001d68: e008 b.n 8001d7c { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001d6a: f7fe fe41 bl 80009f0 8001d6e: 0002 movs r2, r0 8001d70: 69bb ldr r3, [r7, #24] 8001d72: 1ad3 subs r3, r2, r3 8001d74: 2b02 cmp r3, #2 8001d76: d901 bls.n 8001d7c { return HAL_TIMEOUT; 8001d78: 2303 movs r3, #3 8001d7a: e0a2 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001d7c: 4b53 ldr r3, [pc, #332] ; (8001ecc ) 8001d7e: 6b5b ldr r3, [r3, #52] ; 0x34 8001d80: 2202 movs r2, #2 8001d82: 4013 ands r3, r2 8001d84: d1f1 bne.n 8001d6a #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001d86: 687b ldr r3, [r7, #4] 8001d88: 6a1b ldr r3, [r3, #32] 8001d8a: 2b00 cmp r3, #0 8001d8c: d100 bne.n 8001d90 8001d8e: e097 b.n 8001ec0 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001d90: 4b4e ldr r3, [pc, #312] ; (8001ecc ) 8001d92: 685b ldr r3, [r3, #4] 8001d94: 220c movs r2, #12 8001d96: 4013 ands r3, r2 8001d98: 2b08 cmp r3, #8 8001d9a: d100 bne.n 8001d9e 8001d9c: e06b b.n 8001e76 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8001d9e: 687b ldr r3, [r7, #4] 8001da0: 6a1b ldr r3, [r3, #32] 8001da2: 2b02 cmp r3, #2 8001da4: d14c bne.n 8001e40 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001da6: 4b49 ldr r3, [pc, #292] ; (8001ecc ) 8001da8: 681a ldr r2, [r3, #0] 8001daa: 4b48 ldr r3, [pc, #288] ; (8001ecc ) 8001dac: 494a ldr r1, [pc, #296] ; (8001ed8 ) 8001dae: 400a ands r2, r1 8001db0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001db2: f7fe fe1d bl 80009f0 8001db6: 0003 movs r3, r0 8001db8: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001dba: e008 b.n 8001dce { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001dbc: f7fe fe18 bl 80009f0 8001dc0: 0002 movs r2, r0 8001dc2: 69bb ldr r3, [r7, #24] 8001dc4: 1ad3 subs r3, r2, r3 8001dc6: 2b02 cmp r3, #2 8001dc8: d901 bls.n 8001dce { return HAL_TIMEOUT; 8001dca: 2303 movs r3, #3 8001dcc: e079 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001dce: 4b3f ldr r3, [pc, #252] ; (8001ecc ) 8001dd0: 681a ldr r2, [r3, #0] 8001dd2: 2380 movs r3, #128 ; 0x80 8001dd4: 049b lsls r3, r3, #18 8001dd6: 4013 ands r3, r2 8001dd8: d1f0 bne.n 8001dbc } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8001dda: 4b3c ldr r3, [pc, #240] ; (8001ecc ) 8001ddc: 6adb ldr r3, [r3, #44] ; 0x2c 8001dde: 220f movs r2, #15 8001de0: 4393 bics r3, r2 8001de2: 0019 movs r1, r3 8001de4: 687b ldr r3, [r7, #4] 8001de6: 6ada ldr r2, [r3, #44] ; 0x2c 8001de8: 4b38 ldr r3, [pc, #224] ; (8001ecc ) 8001dea: 430a orrs r2, r1 8001dec: 62da str r2, [r3, #44] ; 0x2c 8001dee: 4b37 ldr r3, [pc, #220] ; (8001ecc ) 8001df0: 685b ldr r3, [r3, #4] 8001df2: 4a3a ldr r2, [pc, #232] ; (8001edc ) 8001df4: 4013 ands r3, r2 8001df6: 0019 movs r1, r3 8001df8: 687b ldr r3, [r7, #4] 8001dfa: 6a9a ldr r2, [r3, #40] ; 0x28 8001dfc: 687b ldr r3, [r7, #4] 8001dfe: 6a5b ldr r3, [r3, #36] ; 0x24 8001e00: 431a orrs r2, r3 8001e02: 4b32 ldr r3, [pc, #200] ; (8001ecc ) 8001e04: 430a orrs r2, r1 8001e06: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001e08: 4b30 ldr r3, [pc, #192] ; (8001ecc ) 8001e0a: 681a ldr r2, [r3, #0] 8001e0c: 4b2f ldr r3, [pc, #188] ; (8001ecc ) 8001e0e: 2180 movs r1, #128 ; 0x80 8001e10: 0449 lsls r1, r1, #17 8001e12: 430a orrs r2, r1 8001e14: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e16: f7fe fdeb bl 80009f0 8001e1a: 0003 movs r3, r0 8001e1c: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001e1e: e008 b.n 8001e32 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001e20: f7fe fde6 bl 80009f0 8001e24: 0002 movs r2, r0 8001e26: 69bb ldr r3, [r7, #24] 8001e28: 1ad3 subs r3, r2, r3 8001e2a: 2b02 cmp r3, #2 8001e2c: d901 bls.n 8001e32 { return HAL_TIMEOUT; 8001e2e: 2303 movs r3, #3 8001e30: e047 b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001e32: 4b26 ldr r3, [pc, #152] ; (8001ecc ) 8001e34: 681a ldr r2, [r3, #0] 8001e36: 2380 movs r3, #128 ; 0x80 8001e38: 049b lsls r3, r3, #18 8001e3a: 4013 ands r3, r2 8001e3c: d0f0 beq.n 8001e20 8001e3e: e03f b.n 8001ec0 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001e40: 4b22 ldr r3, [pc, #136] ; (8001ecc ) 8001e42: 681a ldr r2, [r3, #0] 8001e44: 4b21 ldr r3, [pc, #132] ; (8001ecc ) 8001e46: 4924 ldr r1, [pc, #144] ; (8001ed8 ) 8001e48: 400a ands r2, r1 8001e4a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e4c: f7fe fdd0 bl 80009f0 8001e50: 0003 movs r3, r0 8001e52: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e54: e008 b.n 8001e68 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001e56: f7fe fdcb bl 80009f0 8001e5a: 0002 movs r2, r0 8001e5c: 69bb ldr r3, [r7, #24] 8001e5e: 1ad3 subs r3, r2, r3 8001e60: 2b02 cmp r3, #2 8001e62: d901 bls.n 8001e68 { return HAL_TIMEOUT; 8001e64: 2303 movs r3, #3 8001e66: e02c b.n 8001ec2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e68: 4b18 ldr r3, [pc, #96] ; (8001ecc ) 8001e6a: 681a ldr r2, [r3, #0] 8001e6c: 2380 movs r3, #128 ; 0x80 8001e6e: 049b lsls r3, r3, #18 8001e70: 4013 ands r3, r2 8001e72: d1f0 bne.n 8001e56 8001e74: e024 b.n 8001ec0 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001e76: 687b ldr r3, [r7, #4] 8001e78: 6a1b ldr r3, [r3, #32] 8001e7a: 2b01 cmp r3, #1 8001e7c: d101 bne.n 8001e82 { return HAL_ERROR; 8001e7e: 2301 movs r3, #1 8001e80: e01f b.n 8001ec2 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001e82: 4b12 ldr r3, [pc, #72] ; (8001ecc ) 8001e84: 685b ldr r3, [r3, #4] 8001e86: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001e88: 4b10 ldr r3, [pc, #64] ; (8001ecc ) 8001e8a: 6adb ldr r3, [r3, #44] ; 0x2c 8001e8c: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001e8e: 697a ldr r2, [r7, #20] 8001e90: 2380 movs r3, #128 ; 0x80 8001e92: 025b lsls r3, r3, #9 8001e94: 401a ands r2, r3 8001e96: 687b ldr r3, [r7, #4] 8001e98: 6a5b ldr r3, [r3, #36] ; 0x24 8001e9a: 429a cmp r2, r3 8001e9c: d10e bne.n 8001ebc (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001e9e: 693b ldr r3, [r7, #16] 8001ea0: 220f movs r2, #15 8001ea2: 401a ands r2, r3 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001ea8: 429a cmp r2, r3 8001eaa: d107 bne.n 8001ebc (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 8001eac: 697a ldr r2, [r7, #20] 8001eae: 23f0 movs r3, #240 ; 0xf0 8001eb0: 039b lsls r3, r3, #14 8001eb2: 401a ands r2, r3 8001eb4: 687b ldr r3, [r7, #4] 8001eb6: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001eb8: 429a cmp r2, r3 8001eba: d001 beq.n 8001ec0 { return HAL_ERROR; 8001ebc: 2301 movs r3, #1 8001ebe: e000 b.n 8001ec2 } } } } return HAL_OK; 8001ec0: 2300 movs r3, #0 } 8001ec2: 0018 movs r0, r3 8001ec4: 46bd mov sp, r7 8001ec6: b008 add sp, #32 8001ec8: bd80 pop {r7, pc} 8001eca: 46c0 nop ; (mov r8, r8) 8001ecc: 40021000 .word 0x40021000 8001ed0: 00001388 .word 0x00001388 8001ed4: efffffff .word 0xefffffff 8001ed8: feffffff .word 0xfeffffff 8001edc: ffc2ffff .word 0xffc2ffff 08001ee0 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001ee0: b580 push {r7, lr} 8001ee2: b084 sub sp, #16 8001ee4: af00 add r7, sp, #0 8001ee6: 6078 str r0, [r7, #4] 8001ee8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8001eea: 687b ldr r3, [r7, #4] 8001eec: 2b00 cmp r3, #0 8001eee: d101 bne.n 8001ef4 { return HAL_ERROR; 8001ef0: 2301 movs r3, #1 8001ef2: e0b3 b.n 800205c /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8001ef4: 4b5b ldr r3, [pc, #364] ; (8002064 ) 8001ef6: 681b ldr r3, [r3, #0] 8001ef8: 2201 movs r2, #1 8001efa: 4013 ands r3, r2 8001efc: 683a ldr r2, [r7, #0] 8001efe: 429a cmp r2, r3 8001f00: d911 bls.n 8001f26 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001f02: 4b58 ldr r3, [pc, #352] ; (8002064 ) 8001f04: 681b ldr r3, [r3, #0] 8001f06: 2201 movs r2, #1 8001f08: 4393 bics r3, r2 8001f0a: 0019 movs r1, r3 8001f0c: 4b55 ldr r3, [pc, #340] ; (8002064 ) 8001f0e: 683a ldr r2, [r7, #0] 8001f10: 430a orrs r2, r1 8001f12: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001f14: 4b53 ldr r3, [pc, #332] ; (8002064 ) 8001f16: 681b ldr r3, [r3, #0] 8001f18: 2201 movs r2, #1 8001f1a: 4013 ands r3, r2 8001f1c: 683a ldr r2, [r7, #0] 8001f1e: 429a cmp r2, r3 8001f20: d001 beq.n 8001f26 { return HAL_ERROR; 8001f22: 2301 movs r3, #1 8001f24: e09a b.n 800205c } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001f26: 687b ldr r3, [r7, #4] 8001f28: 681b ldr r3, [r3, #0] 8001f2a: 2202 movs r2, #2 8001f2c: 4013 ands r3, r2 8001f2e: d015 beq.n 8001f5c { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001f30: 687b ldr r3, [r7, #4] 8001f32: 681b ldr r3, [r3, #0] 8001f34: 2204 movs r2, #4 8001f36: 4013 ands r3, r2 8001f38: d006 beq.n 8001f48 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001f3a: 4b4b ldr r3, [pc, #300] ; (8002068 ) 8001f3c: 685a ldr r2, [r3, #4] 8001f3e: 4b4a ldr r3, [pc, #296] ; (8002068 ) 8001f40: 21e0 movs r1, #224 ; 0xe0 8001f42: 00c9 lsls r1, r1, #3 8001f44: 430a orrs r2, r1 8001f46: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001f48: 4b47 ldr r3, [pc, #284] ; (8002068 ) 8001f4a: 685b ldr r3, [r3, #4] 8001f4c: 22f0 movs r2, #240 ; 0xf0 8001f4e: 4393 bics r3, r2 8001f50: 0019 movs r1, r3 8001f52: 687b ldr r3, [r7, #4] 8001f54: 689a ldr r2, [r3, #8] 8001f56: 4b44 ldr r3, [pc, #272] ; (8002068 ) 8001f58: 430a orrs r2, r1 8001f5a: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001f5c: 687b ldr r3, [r7, #4] 8001f5e: 681b ldr r3, [r3, #0] 8001f60: 2201 movs r2, #1 8001f62: 4013 ands r3, r2 8001f64: d040 beq.n 8001fe8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8001f66: 687b ldr r3, [r7, #4] 8001f68: 685b ldr r3, [r3, #4] 8001f6a: 2b01 cmp r3, #1 8001f6c: d107 bne.n 8001f7e { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001f6e: 4b3e ldr r3, [pc, #248] ; (8002068 ) 8001f70: 681a ldr r2, [r3, #0] 8001f72: 2380 movs r3, #128 ; 0x80 8001f74: 029b lsls r3, r3, #10 8001f76: 4013 ands r3, r2 8001f78: d114 bne.n 8001fa4 { return HAL_ERROR; 8001f7a: 2301 movs r3, #1 8001f7c: e06e b.n 800205c } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001f7e: 687b ldr r3, [r7, #4] 8001f80: 685b ldr r3, [r3, #4] 8001f82: 2b02 cmp r3, #2 8001f84: d107 bne.n 8001f96 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001f86: 4b38 ldr r3, [pc, #224] ; (8002068 ) 8001f88: 681a ldr r2, [r3, #0] 8001f8a: 2380 movs r3, #128 ; 0x80 8001f8c: 049b lsls r3, r3, #18 8001f8e: 4013 ands r3, r2 8001f90: d108 bne.n 8001fa4 { return HAL_ERROR; 8001f92: 2301 movs r3, #1 8001f94: e062 b.n 800205c #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001f96: 4b34 ldr r3, [pc, #208] ; (8002068 ) 8001f98: 681b ldr r3, [r3, #0] 8001f9a: 2202 movs r2, #2 8001f9c: 4013 ands r3, r2 8001f9e: d101 bne.n 8001fa4 { return HAL_ERROR; 8001fa0: 2301 movs r3, #1 8001fa2: e05b b.n 800205c } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8001fa4: 4b30 ldr r3, [pc, #192] ; (8002068 ) 8001fa6: 685b ldr r3, [r3, #4] 8001fa8: 2203 movs r2, #3 8001faa: 4393 bics r3, r2 8001fac: 0019 movs r1, r3 8001fae: 687b ldr r3, [r7, #4] 8001fb0: 685a ldr r2, [r3, #4] 8001fb2: 4b2d ldr r3, [pc, #180] ; (8002068 ) 8001fb4: 430a orrs r2, r1 8001fb6: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001fb8: f7fe fd1a bl 80009f0 8001fbc: 0003 movs r3, r0 8001fbe: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001fc0: e009 b.n 8001fd6 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001fc2: f7fe fd15 bl 80009f0 8001fc6: 0002 movs r2, r0 8001fc8: 68fb ldr r3, [r7, #12] 8001fca: 1ad3 subs r3, r2, r3 8001fcc: 4a27 ldr r2, [pc, #156] ; (800206c ) 8001fce: 4293 cmp r3, r2 8001fd0: d901 bls.n 8001fd6 { return HAL_TIMEOUT; 8001fd2: 2303 movs r3, #3 8001fd4: e042 b.n 800205c while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001fd6: 4b24 ldr r3, [pc, #144] ; (8002068 ) 8001fd8: 685b ldr r3, [r3, #4] 8001fda: 220c movs r2, #12 8001fdc: 401a ands r2, r3 8001fde: 687b ldr r3, [r7, #4] 8001fe0: 685b ldr r3, [r3, #4] 8001fe2: 009b lsls r3, r3, #2 8001fe4: 429a cmp r2, r3 8001fe6: d1ec bne.n 8001fc2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8001fe8: 4b1e ldr r3, [pc, #120] ; (8002064 ) 8001fea: 681b ldr r3, [r3, #0] 8001fec: 2201 movs r2, #1 8001fee: 4013 ands r3, r2 8001ff0: 683a ldr r2, [r7, #0] 8001ff2: 429a cmp r2, r3 8001ff4: d211 bcs.n 800201a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001ff6: 4b1b ldr r3, [pc, #108] ; (8002064 ) 8001ff8: 681b ldr r3, [r3, #0] 8001ffa: 2201 movs r2, #1 8001ffc: 4393 bics r3, r2 8001ffe: 0019 movs r1, r3 8002000: 4b18 ldr r3, [pc, #96] ; (8002064 ) 8002002: 683a ldr r2, [r7, #0] 8002004: 430a orrs r2, r1 8002006: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8002008: 4b16 ldr r3, [pc, #88] ; (8002064 ) 800200a: 681b ldr r3, [r3, #0] 800200c: 2201 movs r2, #1 800200e: 4013 ands r3, r2 8002010: 683a ldr r2, [r7, #0] 8002012: 429a cmp r2, r3 8002014: d001 beq.n 800201a { return HAL_ERROR; 8002016: 2301 movs r3, #1 8002018: e020 b.n 800205c } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800201a: 687b ldr r3, [r7, #4] 800201c: 681b ldr r3, [r3, #0] 800201e: 2204 movs r2, #4 8002020: 4013 ands r3, r2 8002022: d009 beq.n 8002038 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8002024: 4b10 ldr r3, [pc, #64] ; (8002068 ) 8002026: 685b ldr r3, [r3, #4] 8002028: 4a11 ldr r2, [pc, #68] ; (8002070 ) 800202a: 4013 ands r3, r2 800202c: 0019 movs r1, r3 800202e: 687b ldr r3, [r7, #4] 8002030: 68da ldr r2, [r3, #12] 8002032: 4b0d ldr r3, [pc, #52] ; (8002068 ) 8002034: 430a orrs r2, r1 8002036: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8002038: f000 f820 bl 800207c 800203c: 0001 movs r1, r0 800203e: 4b0a ldr r3, [pc, #40] ; (8002068 ) 8002040: 685b ldr r3, [r3, #4] 8002042: 091b lsrs r3, r3, #4 8002044: 220f movs r2, #15 8002046: 4013 ands r3, r2 8002048: 4a0a ldr r2, [pc, #40] ; (8002074 ) 800204a: 5cd3 ldrb r3, [r2, r3] 800204c: 000a movs r2, r1 800204e: 40da lsrs r2, r3 8002050: 4b09 ldr r3, [pc, #36] ; (8002078 ) 8002052: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8002054: 2003 movs r0, #3 8002056: f7fe fc85 bl 8000964 return HAL_OK; 800205a: 2300 movs r3, #0 } 800205c: 0018 movs r0, r3 800205e: 46bd mov sp, r7 8002060: b004 add sp, #16 8002062: bd80 pop {r7, pc} 8002064: 40022000 .word 0x40022000 8002068: 40021000 .word 0x40021000 800206c: 00001388 .word 0x00001388 8002070: fffff8ff .word 0xfffff8ff 8002074: 08003d5c .word 0x08003d5c 8002078: 20000000 .word 0x20000000 0800207c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800207c: b590 push {r4, r7, lr} 800207e: b08f sub sp, #60 ; 0x3c 8002080: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 8002082: 2314 movs r3, #20 8002084: 18fb adds r3, r7, r3 8002086: 4a2b ldr r2, [pc, #172] ; (8002134 ) 8002088: ca13 ldmia r2!, {r0, r1, r4} 800208a: c313 stmia r3!, {r0, r1, r4} 800208c: 6812 ldr r2, [r2, #0] 800208e: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8002090: 1d3b adds r3, r7, #4 8002092: 4a29 ldr r2, [pc, #164] ; (8002138 ) 8002094: ca13 ldmia r2!, {r0, r1, r4} 8002096: c313 stmia r3!, {r0, r1, r4} 8002098: 6812 ldr r2, [r2, #0] 800209a: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 800209c: 2300 movs r3, #0 800209e: 62fb str r3, [r7, #44] ; 0x2c 80020a0: 2300 movs r3, #0 80020a2: 62bb str r3, [r7, #40] ; 0x28 80020a4: 2300 movs r3, #0 80020a6: 637b str r3, [r7, #52] ; 0x34 80020a8: 2300 movs r3, #0 80020aa: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 80020ac: 2300 movs r3, #0 80020ae: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 80020b0: 4b22 ldr r3, [pc, #136] ; (800213c ) 80020b2: 685b ldr r3, [r3, #4] 80020b4: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80020b6: 6afb ldr r3, [r7, #44] ; 0x2c 80020b8: 220c movs r2, #12 80020ba: 4013 ands r3, r2 80020bc: 2b04 cmp r3, #4 80020be: d002 beq.n 80020c6 80020c0: 2b08 cmp r3, #8 80020c2: d003 beq.n 80020cc 80020c4: e02d b.n 8002122 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80020c6: 4b1e ldr r3, [pc, #120] ; (8002140 ) 80020c8: 633b str r3, [r7, #48] ; 0x30 break; 80020ca: e02d b.n 8002128 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 80020cc: 6afb ldr r3, [r7, #44] ; 0x2c 80020ce: 0c9b lsrs r3, r3, #18 80020d0: 220f movs r2, #15 80020d2: 4013 ands r3, r2 80020d4: 2214 movs r2, #20 80020d6: 18ba adds r2, r7, r2 80020d8: 5cd3 ldrb r3, [r2, r3] 80020da: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 80020dc: 4b17 ldr r3, [pc, #92] ; (800213c ) 80020de: 6adb ldr r3, [r3, #44] ; 0x2c 80020e0: 220f movs r2, #15 80020e2: 4013 ands r3, r2 80020e4: 1d3a adds r2, r7, #4 80020e6: 5cd3 ldrb r3, [r2, r3] 80020e8: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 80020ea: 6afa ldr r2, [r7, #44] ; 0x2c 80020ec: 2380 movs r3, #128 ; 0x80 80020ee: 025b lsls r3, r3, #9 80020f0: 4013 ands r3, r2 80020f2: d009 beq.n 8002108 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80020f4: 6ab9 ldr r1, [r7, #40] ; 0x28 80020f6: 4812 ldr r0, [pc, #72] ; (8002140 ) 80020f8: f7fe f806 bl 8000108 <__udivsi3> 80020fc: 0003 movs r3, r0 80020fe: 001a movs r2, r3 8002100: 6a7b ldr r3, [r7, #36] ; 0x24 8002102: 4353 muls r3, r2 8002104: 637b str r3, [r7, #52] ; 0x34 8002106: e009 b.n 800211c #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 8002108: 6a79 ldr r1, [r7, #36] ; 0x24 800210a: 000a movs r2, r1 800210c: 0152 lsls r2, r2, #5 800210e: 1a52 subs r2, r2, r1 8002110: 0193 lsls r3, r2, #6 8002112: 1a9b subs r3, r3, r2 8002114: 00db lsls r3, r3, #3 8002116: 185b adds r3, r3, r1 8002118: 021b lsls r3, r3, #8 800211a: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 800211c: 6b7b ldr r3, [r7, #52] ; 0x34 800211e: 633b str r3, [r7, #48] ; 0x30 break; 8002120: e002 b.n 8002128 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8002122: 4b07 ldr r3, [pc, #28] ; (8002140 ) 8002124: 633b str r3, [r7, #48] ; 0x30 break; 8002126: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8002128: 6b3b ldr r3, [r7, #48] ; 0x30 } 800212a: 0018 movs r0, r3 800212c: 46bd mov sp, r7 800212e: b00f add sp, #60 ; 0x3c 8002130: bd90 pop {r4, r7, pc} 8002132: 46c0 nop ; (mov r8, r8) 8002134: 08003d3c .word 0x08003d3c 8002138: 08003d4c .word 0x08003d4c 800213c: 40021000 .word 0x40021000 8002140: 007a1200 .word 0x007a1200 08002144 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8002144: b580 push {r7, lr} 8002146: b082 sub sp, #8 8002148: af00 add r7, sp, #0 800214a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800214c: 687b ldr r3, [r7, #4] 800214e: 2b00 cmp r3, #0 8002150: d101 bne.n 8002156 { return HAL_ERROR; 8002152: 2301 movs r3, #1 8002154: e042 b.n 80021dc assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8002156: 687b ldr r3, [r7, #4] 8002158: 223d movs r2, #61 ; 0x3d 800215a: 5c9b ldrb r3, [r3, r2] 800215c: b2db uxtb r3, r3 800215e: 2b00 cmp r3, #0 8002160: d107 bne.n 8002172 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8002162: 687b ldr r3, [r7, #4] 8002164: 223c movs r2, #60 ; 0x3c 8002166: 2100 movs r1, #0 8002168: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800216a: 687b ldr r3, [r7, #4] 800216c: 0018 movs r0, r3 800216e: f7fe fb61 bl 8000834 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8002172: 687b ldr r3, [r7, #4] 8002174: 223d movs r2, #61 ; 0x3d 8002176: 2102 movs r1, #2 8002178: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800217a: 687b ldr r3, [r7, #4] 800217c: 681a ldr r2, [r3, #0] 800217e: 687b ldr r3, [r7, #4] 8002180: 3304 adds r3, #4 8002182: 0019 movs r1, r3 8002184: 0010 movs r0, r2 8002186: f000 f9a9 bl 80024dc /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800218a: 687b ldr r3, [r7, #4] 800218c: 2246 movs r2, #70 ; 0x46 800218e: 2101 movs r1, #1 8002190: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8002192: 687b ldr r3, [r7, #4] 8002194: 223e movs r2, #62 ; 0x3e 8002196: 2101 movs r1, #1 8002198: 5499 strb r1, [r3, r2] 800219a: 687b ldr r3, [r7, #4] 800219c: 223f movs r2, #63 ; 0x3f 800219e: 2101 movs r1, #1 80021a0: 5499 strb r1, [r3, r2] 80021a2: 687b ldr r3, [r7, #4] 80021a4: 2240 movs r2, #64 ; 0x40 80021a6: 2101 movs r1, #1 80021a8: 5499 strb r1, [r3, r2] 80021aa: 687b ldr r3, [r7, #4] 80021ac: 2241 movs r2, #65 ; 0x41 80021ae: 2101 movs r1, #1 80021b0: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80021b2: 687b ldr r3, [r7, #4] 80021b4: 2242 movs r2, #66 ; 0x42 80021b6: 2101 movs r1, #1 80021b8: 5499 strb r1, [r3, r2] 80021ba: 687b ldr r3, [r7, #4] 80021bc: 2243 movs r2, #67 ; 0x43 80021be: 2101 movs r1, #1 80021c0: 5499 strb r1, [r3, r2] 80021c2: 687b ldr r3, [r7, #4] 80021c4: 2244 movs r2, #68 ; 0x44 80021c6: 2101 movs r1, #1 80021c8: 5499 strb r1, [r3, r2] 80021ca: 687b ldr r3, [r7, #4] 80021cc: 2245 movs r2, #69 ; 0x45 80021ce: 2101 movs r1, #1 80021d0: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80021d2: 687b ldr r3, [r7, #4] 80021d4: 223d movs r2, #61 ; 0x3d 80021d6: 2101 movs r1, #1 80021d8: 5499 strb r1, [r3, r2] return HAL_OK; 80021da: 2300 movs r3, #0 } 80021dc: 0018 movs r0, r3 80021de: 46bd mov sp, r7 80021e0: b002 add sp, #8 80021e2: bd80 pop {r7, pc} 080021e4 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 80021e4: b580 push {r7, lr} 80021e6: b084 sub sp, #16 80021e8: af00 add r7, sp, #0 80021ea: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 80021ec: 687b ldr r3, [r7, #4] 80021ee: 223d movs r2, #61 ; 0x3d 80021f0: 5c9b ldrb r3, [r3, r2] 80021f2: b2db uxtb r3, r3 80021f4: 2b01 cmp r3, #1 80021f6: d001 beq.n 80021fc { return HAL_ERROR; 80021f8: 2301 movs r3, #1 80021fa: e030 b.n 800225e } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80021fc: 687b ldr r3, [r7, #4] 80021fe: 223d movs r2, #61 ; 0x3d 8002200: 2102 movs r1, #2 8002202: 5499 strb r1, [r3, r2] /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8002204: 687b ldr r3, [r7, #4] 8002206: 681b ldr r3, [r3, #0] 8002208: 68da ldr r2, [r3, #12] 800220a: 687b ldr r3, [r7, #4] 800220c: 681b ldr r3, [r3, #0] 800220e: 2101 movs r1, #1 8002210: 430a orrs r2, r1 8002212: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8002214: 687b ldr r3, [r7, #4] 8002216: 681b ldr r3, [r3, #0] 8002218: 4a13 ldr r2, [pc, #76] ; (8002268 ) 800221a: 4293 cmp r3, r2 800221c: d004 beq.n 8002228 800221e: 687b ldr r3, [r7, #4] 8002220: 681b ldr r3, [r3, #0] 8002222: 4a12 ldr r2, [pc, #72] ; (800226c ) 8002224: 4293 cmp r3, r2 8002226: d111 bne.n 800224c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8002228: 687b ldr r3, [r7, #4] 800222a: 681b ldr r3, [r3, #0] 800222c: 689b ldr r3, [r3, #8] 800222e: 2207 movs r2, #7 8002230: 4013 ands r3, r2 8002232: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8002234: 68fb ldr r3, [r7, #12] 8002236: 2b06 cmp r3, #6 8002238: d010 beq.n 800225c { __HAL_TIM_ENABLE(htim); 800223a: 687b ldr r3, [r7, #4] 800223c: 681b ldr r3, [r3, #0] 800223e: 681a ldr r2, [r3, #0] 8002240: 687b ldr r3, [r7, #4] 8002242: 681b ldr r3, [r3, #0] 8002244: 2101 movs r1, #1 8002246: 430a orrs r2, r1 8002248: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800224a: e007 b.n 800225c } } else { __HAL_TIM_ENABLE(htim); 800224c: 687b ldr r3, [r7, #4] 800224e: 681b ldr r3, [r3, #0] 8002250: 681a ldr r2, [r3, #0] 8002252: 687b ldr r3, [r7, #4] 8002254: 681b ldr r3, [r3, #0] 8002256: 2101 movs r1, #1 8002258: 430a orrs r2, r1 800225a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800225c: 2300 movs r3, #0 } 800225e: 0018 movs r0, r3 8002260: 46bd mov sp, r7 8002262: b004 add sp, #16 8002264: bd80 pop {r7, pc} 8002266: 46c0 nop ; (mov r8, r8) 8002268: 40012c00 .word 0x40012c00 800226c: 40000400 .word 0x40000400 08002270 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8002270: b580 push {r7, lr} 8002272: b082 sub sp, #8 8002274: af00 add r7, sp, #0 8002276: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8002278: 687b ldr r3, [r7, #4] 800227a: 681b ldr r3, [r3, #0] 800227c: 691b ldr r3, [r3, #16] 800227e: 2202 movs r2, #2 8002280: 4013 ands r3, r2 8002282: 2b02 cmp r3, #2 8002284: d124 bne.n 80022d0 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 8002286: 687b ldr r3, [r7, #4] 8002288: 681b ldr r3, [r3, #0] 800228a: 68db ldr r3, [r3, #12] 800228c: 2202 movs r2, #2 800228e: 4013 ands r3, r2 8002290: 2b02 cmp r3, #2 8002292: d11d bne.n 80022d0 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8002294: 687b ldr r3, [r7, #4] 8002296: 681b ldr r3, [r3, #0] 8002298: 2203 movs r2, #3 800229a: 4252 negs r2, r2 800229c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800229e: 687b ldr r3, [r7, #4] 80022a0: 2201 movs r2, #1 80022a2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80022a4: 687b ldr r3, [r7, #4] 80022a6: 681b ldr r3, [r3, #0] 80022a8: 699b ldr r3, [r3, #24] 80022aa: 2203 movs r2, #3 80022ac: 4013 ands r3, r2 80022ae: d004 beq.n 80022ba { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80022b0: 687b ldr r3, [r7, #4] 80022b2: 0018 movs r0, r3 80022b4: f000 f8fa bl 80024ac 80022b8: e007 b.n 80022ca { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80022ba: 687b ldr r3, [r7, #4] 80022bc: 0018 movs r0, r3 80022be: f000 f8ed bl 800249c HAL_TIM_PWM_PulseFinishedCallback(htim); 80022c2: 687b ldr r3, [r7, #4] 80022c4: 0018 movs r0, r3 80022c6: f000 f8f9 bl 80024bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80022ca: 687b ldr r3, [r7, #4] 80022cc: 2200 movs r2, #0 80022ce: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 80022d0: 687b ldr r3, [r7, #4] 80022d2: 681b ldr r3, [r3, #0] 80022d4: 691b ldr r3, [r3, #16] 80022d6: 2204 movs r2, #4 80022d8: 4013 ands r3, r2 80022da: 2b04 cmp r3, #4 80022dc: d125 bne.n 800232a { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 80022de: 687b ldr r3, [r7, #4] 80022e0: 681b ldr r3, [r3, #0] 80022e2: 68db ldr r3, [r3, #12] 80022e4: 2204 movs r2, #4 80022e6: 4013 ands r3, r2 80022e8: 2b04 cmp r3, #4 80022ea: d11e bne.n 800232a { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 80022ec: 687b ldr r3, [r7, #4] 80022ee: 681b ldr r3, [r3, #0] 80022f0: 2205 movs r2, #5 80022f2: 4252 negs r2, r2 80022f4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80022f6: 687b ldr r3, [r7, #4] 80022f8: 2202 movs r2, #2 80022fa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80022fc: 687b ldr r3, [r7, #4] 80022fe: 681b ldr r3, [r3, #0] 8002300: 699a ldr r2, [r3, #24] 8002302: 23c0 movs r3, #192 ; 0xc0 8002304: 009b lsls r3, r3, #2 8002306: 4013 ands r3, r2 8002308: d004 beq.n 8002314 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800230a: 687b ldr r3, [r7, #4] 800230c: 0018 movs r0, r3 800230e: f000 f8cd bl 80024ac 8002312: e007 b.n 8002324 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002314: 687b ldr r3, [r7, #4] 8002316: 0018 movs r0, r3 8002318: f000 f8c0 bl 800249c HAL_TIM_PWM_PulseFinishedCallback(htim); 800231c: 687b ldr r3, [r7, #4] 800231e: 0018 movs r0, r3 8002320: f000 f8cc bl 80024bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002324: 687b ldr r3, [r7, #4] 8002326: 2200 movs r2, #0 8002328: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 800232a: 687b ldr r3, [r7, #4] 800232c: 681b ldr r3, [r3, #0] 800232e: 691b ldr r3, [r3, #16] 8002330: 2208 movs r2, #8 8002332: 4013 ands r3, r2 8002334: 2b08 cmp r3, #8 8002336: d124 bne.n 8002382 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 8002338: 687b ldr r3, [r7, #4] 800233a: 681b ldr r3, [r3, #0] 800233c: 68db ldr r3, [r3, #12] 800233e: 2208 movs r2, #8 8002340: 4013 ands r3, r2 8002342: 2b08 cmp r3, #8 8002344: d11d bne.n 8002382 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 8002346: 687b ldr r3, [r7, #4] 8002348: 681b ldr r3, [r3, #0] 800234a: 2209 movs r2, #9 800234c: 4252 negs r2, r2 800234e: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8002350: 687b ldr r3, [r7, #4] 8002352: 2204 movs r2, #4 8002354: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8002356: 687b ldr r3, [r7, #4] 8002358: 681b ldr r3, [r3, #0] 800235a: 69db ldr r3, [r3, #28] 800235c: 2203 movs r2, #3 800235e: 4013 ands r3, r2 8002360: d004 beq.n 800236c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002362: 687b ldr r3, [r7, #4] 8002364: 0018 movs r0, r3 8002366: f000 f8a1 bl 80024ac 800236a: e007 b.n 800237c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800236c: 687b ldr r3, [r7, #4] 800236e: 0018 movs r0, r3 8002370: f000 f894 bl 800249c HAL_TIM_PWM_PulseFinishedCallback(htim); 8002374: 687b ldr r3, [r7, #4] 8002376: 0018 movs r0, r3 8002378: f000 f8a0 bl 80024bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800237c: 687b ldr r3, [r7, #4] 800237e: 2200 movs r2, #0 8002380: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 8002382: 687b ldr r3, [r7, #4] 8002384: 681b ldr r3, [r3, #0] 8002386: 691b ldr r3, [r3, #16] 8002388: 2210 movs r2, #16 800238a: 4013 ands r3, r2 800238c: 2b10 cmp r3, #16 800238e: d125 bne.n 80023dc { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 8002390: 687b ldr r3, [r7, #4] 8002392: 681b ldr r3, [r3, #0] 8002394: 68db ldr r3, [r3, #12] 8002396: 2210 movs r2, #16 8002398: 4013 ands r3, r2 800239a: 2b10 cmp r3, #16 800239c: d11e bne.n 80023dc { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 800239e: 687b ldr r3, [r7, #4] 80023a0: 681b ldr r3, [r3, #0] 80023a2: 2211 movs r2, #17 80023a4: 4252 negs r2, r2 80023a6: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80023a8: 687b ldr r3, [r7, #4] 80023aa: 2208 movs r2, #8 80023ac: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80023ae: 687b ldr r3, [r7, #4] 80023b0: 681b ldr r3, [r3, #0] 80023b2: 69da ldr r2, [r3, #28] 80023b4: 23c0 movs r3, #192 ; 0xc0 80023b6: 009b lsls r3, r3, #2 80023b8: 4013 ands r3, r2 80023ba: d004 beq.n 80023c6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80023bc: 687b ldr r3, [r7, #4] 80023be: 0018 movs r0, r3 80023c0: f000 f874 bl 80024ac 80023c4: e007 b.n 80023d6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80023c6: 687b ldr r3, [r7, #4] 80023c8: 0018 movs r0, r3 80023ca: f000 f867 bl 800249c HAL_TIM_PWM_PulseFinishedCallback(htim); 80023ce: 687b ldr r3, [r7, #4] 80023d0: 0018 movs r0, r3 80023d2: f000 f873 bl 80024bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80023d6: 687b ldr r3, [r7, #4] 80023d8: 2200 movs r2, #0 80023da: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 80023dc: 687b ldr r3, [r7, #4] 80023de: 681b ldr r3, [r3, #0] 80023e0: 691b ldr r3, [r3, #16] 80023e2: 2201 movs r2, #1 80023e4: 4013 ands r3, r2 80023e6: 2b01 cmp r3, #1 80023e8: d10f bne.n 800240a { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 80023ea: 687b ldr r3, [r7, #4] 80023ec: 681b ldr r3, [r3, #0] 80023ee: 68db ldr r3, [r3, #12] 80023f0: 2201 movs r2, #1 80023f2: 4013 ands r3, r2 80023f4: 2b01 cmp r3, #1 80023f6: d108 bne.n 800240a { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 80023f8: 687b ldr r3, [r7, #4] 80023fa: 681b ldr r3, [r3, #0] 80023fc: 2202 movs r2, #2 80023fe: 4252 negs r2, r2 8002400: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8002402: 687b ldr r3, [r7, #4] 8002404: 0018 movs r0, r3 8002406: f001 fbe5 bl 8003bd4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 800240a: 687b ldr r3, [r7, #4] 800240c: 681b ldr r3, [r3, #0] 800240e: 691b ldr r3, [r3, #16] 8002410: 2280 movs r2, #128 ; 0x80 8002412: 4013 ands r3, r2 8002414: 2b80 cmp r3, #128 ; 0x80 8002416: d10f bne.n 8002438 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 8002418: 687b ldr r3, [r7, #4] 800241a: 681b ldr r3, [r3, #0] 800241c: 68db ldr r3, [r3, #12] 800241e: 2280 movs r2, #128 ; 0x80 8002420: 4013 ands r3, r2 8002422: 2b80 cmp r3, #128 ; 0x80 8002424: d108 bne.n 8002438 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 8002426: 687b ldr r3, [r7, #4] 8002428: 681b ldr r3, [r3, #0] 800242a: 2281 movs r2, #129 ; 0x81 800242c: 4252 negs r2, r2 800242e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8002430: 687b ldr r3, [r7, #4] 8002432: 0018 movs r0, r3 8002434: f000 f8c6 bl 80025c4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 8002438: 687b ldr r3, [r7, #4] 800243a: 681b ldr r3, [r3, #0] 800243c: 691b ldr r3, [r3, #16] 800243e: 2240 movs r2, #64 ; 0x40 8002440: 4013 ands r3, r2 8002442: 2b40 cmp r3, #64 ; 0x40 8002444: d10f bne.n 8002466 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 8002446: 687b ldr r3, [r7, #4] 8002448: 681b ldr r3, [r3, #0] 800244a: 68db ldr r3, [r3, #12] 800244c: 2240 movs r2, #64 ; 0x40 800244e: 4013 ands r3, r2 8002450: 2b40 cmp r3, #64 ; 0x40 8002452: d108 bne.n 8002466 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 8002454: 687b ldr r3, [r7, #4] 8002456: 681b ldr r3, [r3, #0] 8002458: 2241 movs r2, #65 ; 0x41 800245a: 4252 negs r2, r2 800245c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800245e: 687b ldr r3, [r7, #4] 8002460: 0018 movs r0, r3 8002462: f000 f833 bl 80024cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 8002466: 687b ldr r3, [r7, #4] 8002468: 681b ldr r3, [r3, #0] 800246a: 691b ldr r3, [r3, #16] 800246c: 2220 movs r2, #32 800246e: 4013 ands r3, r2 8002470: 2b20 cmp r3, #32 8002472: d10f bne.n 8002494 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 8002474: 687b ldr r3, [r7, #4] 8002476: 681b ldr r3, [r3, #0] 8002478: 68db ldr r3, [r3, #12] 800247a: 2220 movs r2, #32 800247c: 4013 ands r3, r2 800247e: 2b20 cmp r3, #32 8002480: d108 bne.n 8002494 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 8002482: 687b ldr r3, [r7, #4] 8002484: 681b ldr r3, [r3, #0] 8002486: 2221 movs r2, #33 ; 0x21 8002488: 4252 negs r2, r2 800248a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800248c: 687b ldr r3, [r7, #4] 800248e: 0018 movs r0, r3 8002490: f000 f890 bl 80025b4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8002494: 46c0 nop ; (mov r8, r8) 8002496: 46bd mov sp, r7 8002498: b002 add sp, #8 800249a: bd80 pop {r7, pc} 0800249c : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800249c: b580 push {r7, lr} 800249e: b082 sub sp, #8 80024a0: af00 add r7, sp, #0 80024a2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80024a4: 46c0 nop ; (mov r8, r8) 80024a6: 46bd mov sp, r7 80024a8: b002 add sp, #8 80024aa: bd80 pop {r7, pc} 080024ac : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80024ac: b580 push {r7, lr} 80024ae: b082 sub sp, #8 80024b0: af00 add r7, sp, #0 80024b2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80024b4: 46c0 nop ; (mov r8, r8) 80024b6: 46bd mov sp, r7 80024b8: b002 add sp, #8 80024ba: bd80 pop {r7, pc} 080024bc : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80024bc: b580 push {r7, lr} 80024be: b082 sub sp, #8 80024c0: af00 add r7, sp, #0 80024c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80024c4: 46c0 nop ; (mov r8, r8) 80024c6: 46bd mov sp, r7 80024c8: b002 add sp, #8 80024ca: bd80 pop {r7, pc} 080024cc : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80024cc: b580 push {r7, lr} 80024ce: b082 sub sp, #8 80024d0: af00 add r7, sp, #0 80024d2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80024d4: 46c0 nop ; (mov r8, r8) 80024d6: 46bd mov sp, r7 80024d8: b002 add sp, #8 80024da: bd80 pop {r7, pc} 080024dc : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 80024dc: b580 push {r7, lr} 80024de: b084 sub sp, #16 80024e0: af00 add r7, sp, #0 80024e2: 6078 str r0, [r7, #4] 80024e4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80024e6: 687b ldr r3, [r7, #4] 80024e8: 681b ldr r3, [r3, #0] 80024ea: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80024ec: 687b ldr r3, [r7, #4] 80024ee: 4a2b ldr r2, [pc, #172] ; (800259c ) 80024f0: 4293 cmp r3, r2 80024f2: d003 beq.n 80024fc 80024f4: 687b ldr r3, [r7, #4] 80024f6: 4a2a ldr r2, [pc, #168] ; (80025a0 ) 80024f8: 4293 cmp r3, r2 80024fa: d108 bne.n 800250e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80024fc: 68fb ldr r3, [r7, #12] 80024fe: 2270 movs r2, #112 ; 0x70 8002500: 4393 bics r3, r2 8002502: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8002504: 683b ldr r3, [r7, #0] 8002506: 685b ldr r3, [r3, #4] 8002508: 68fa ldr r2, [r7, #12] 800250a: 4313 orrs r3, r2 800250c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800250e: 687b ldr r3, [r7, #4] 8002510: 4a22 ldr r2, [pc, #136] ; (800259c ) 8002512: 4293 cmp r3, r2 8002514: d00f beq.n 8002536 8002516: 687b ldr r3, [r7, #4] 8002518: 4a21 ldr r2, [pc, #132] ; (80025a0 ) 800251a: 4293 cmp r3, r2 800251c: d00b beq.n 8002536 800251e: 687b ldr r3, [r7, #4] 8002520: 4a20 ldr r2, [pc, #128] ; (80025a4 ) 8002522: 4293 cmp r3, r2 8002524: d007 beq.n 8002536 8002526: 687b ldr r3, [r7, #4] 8002528: 4a1f ldr r2, [pc, #124] ; (80025a8 ) 800252a: 4293 cmp r3, r2 800252c: d003 beq.n 8002536 800252e: 687b ldr r3, [r7, #4] 8002530: 4a1e ldr r2, [pc, #120] ; (80025ac ) 8002532: 4293 cmp r3, r2 8002534: d108 bne.n 8002548 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8002536: 68fb ldr r3, [r7, #12] 8002538: 4a1d ldr r2, [pc, #116] ; (80025b0 ) 800253a: 4013 ands r3, r2 800253c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800253e: 683b ldr r3, [r7, #0] 8002540: 68db ldr r3, [r3, #12] 8002542: 68fa ldr r2, [r7, #12] 8002544: 4313 orrs r3, r2 8002546: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8002548: 68fb ldr r3, [r7, #12] 800254a: 2280 movs r2, #128 ; 0x80 800254c: 4393 bics r3, r2 800254e: 001a movs r2, r3 8002550: 683b ldr r3, [r7, #0] 8002552: 695b ldr r3, [r3, #20] 8002554: 4313 orrs r3, r2 8002556: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8002558: 687b ldr r3, [r7, #4] 800255a: 68fa ldr r2, [r7, #12] 800255c: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800255e: 683b ldr r3, [r7, #0] 8002560: 689a ldr r2, [r3, #8] 8002562: 687b ldr r3, [r7, #4] 8002564: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8002566: 683b ldr r3, [r7, #0] 8002568: 681a ldr r2, [r3, #0] 800256a: 687b ldr r3, [r7, #4] 800256c: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800256e: 687b ldr r3, [r7, #4] 8002570: 4a0a ldr r2, [pc, #40] ; (800259c ) 8002572: 4293 cmp r3, r2 8002574: d007 beq.n 8002586 8002576: 687b ldr r3, [r7, #4] 8002578: 4a0b ldr r2, [pc, #44] ; (80025a8 ) 800257a: 4293 cmp r3, r2 800257c: d003 beq.n 8002586 800257e: 687b ldr r3, [r7, #4] 8002580: 4a0a ldr r2, [pc, #40] ; (80025ac ) 8002582: 4293 cmp r3, r2 8002584: d103 bne.n 800258e { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8002586: 683b ldr r3, [r7, #0] 8002588: 691a ldr r2, [r3, #16] 800258a: 687b ldr r3, [r7, #4] 800258c: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800258e: 687b ldr r3, [r7, #4] 8002590: 2201 movs r2, #1 8002592: 615a str r2, [r3, #20] } 8002594: 46c0 nop ; (mov r8, r8) 8002596: 46bd mov sp, r7 8002598: b004 add sp, #16 800259a: bd80 pop {r7, pc} 800259c: 40012c00 .word 0x40012c00 80025a0: 40000400 .word 0x40000400 80025a4: 40002000 .word 0x40002000 80025a8: 40014400 .word 0x40014400 80025ac: 40014800 .word 0x40014800 80025b0: fffffcff .word 0xfffffcff 080025b4 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80025b4: b580 push {r7, lr} 80025b6: b082 sub sp, #8 80025b8: af00 add r7, sp, #0 80025ba: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 80025bc: 46c0 nop ; (mov r8, r8) 80025be: 46bd mov sp, r7 80025c0: b002 add sp, #8 80025c2: bd80 pop {r7, pc} 080025c4 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 80025c4: b580 push {r7, lr} 80025c6: b082 sub sp, #8 80025c8: af00 add r7, sp, #0 80025ca: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80025cc: 46c0 nop ; (mov r8, r8) 80025ce: 46bd mov sp, r7 80025d0: b002 add sp, #8 80025d2: bd80 pop {r7, pc} 080025d4 : */ #include "button.h" void GEI_BUTTON_CODE(struct button *bt,uint8_t in) { 80025d4: b580 push {r7, lr} 80025d6: b082 sub sp, #8 80025d8: af00 add r7, sp, #0 80025da: 6078 str r0, [r7, #4] 80025dc: 000a movs r2, r1 80025de: 1cfb adds r3, r7, #3 80025e0: 701a strb r2, [r3, #0] #define t 250 bt->code=0; 80025e2: 687b ldr r3, [r7, #4] 80025e4: 2200 movs r2, #0 80025e6: 601a str r2, [r3, #0] if(in==1) 80025e8: 1cfb adds r3, r7, #3 80025ea: 781b ldrb r3, [r3, #0] 80025ec: 2b01 cmp r3, #1 80025ee: d138 bne.n 8002662 { if(bt->lock==0) 80025f0: 687b ldr r3, [r7, #4] 80025f2: 791b ldrb r3, [r3, #4] 80025f4: 2b00 cmp r3, #0 80025f6: d120 bne.n 800263a { if(HAL_GetTick()time+t) 80025f8: f7fe f9fa bl 80009f0 80025fc: 0002 movs r2, r0 80025fe: 687b ldr r3, [r7, #4] 8002600: 689b ldr r3, [r3, #8] 8002602: 33fa adds r3, #250 ; 0xfa 8002604: 429a cmp r2, r3 8002606: d20d bcs.n 8002624 { bt->times++; 8002608: 687b ldr r3, [r7, #4] 800260a: 68db ldr r3, [r3, #12] 800260c: 1c5a adds r2, r3, #1 800260e: 687b ldr r3, [r7, #4] 8002610: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 8002612: f7fe f9ed bl 80009f0 8002616: 0002 movs r2, r0 8002618: 687b ldr r3, [r7, #4] 800261a: 609a str r2, [r3, #8] bt->lock=1; 800261c: 687b ldr r3, [r7, #4] 800261e: 2201 movs r2, #1 8002620: 711a strb r2, [r3, #4] 8002622: e00a b.n 800263a }else { bt->times=1; 8002624: 687b ldr r3, [r7, #4] 8002626: 2201 movs r2, #1 8002628: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 800262a: f7fe f9e1 bl 80009f0 800262e: 0002 movs r2, r0 8002630: 687b ldr r3, [r7, #4] 8002632: 609a str r2, [r3, #8] bt->lock=1; 8002634: 687b ldr r3, [r7, #4] 8002636: 2201 movs r2, #1 8002638: 711a strb r2, [r3, #4] } } if(bt->lock==1) 800263a: 687b ldr r3, [r7, #4] 800263c: 791b ldrb r3, [r3, #4] 800263e: 2b01 cmp r3, #1 8002640: d10f bne.n 8002662 { if(HAL_GetTick()>bt->time+t) 8002642: f7fe f9d5 bl 80009f0 8002646: 0002 movs r2, r0 8002648: 687b ldr r3, [r7, #4] 800264a: 689b ldr r3, [r3, #8] 800264c: 33fa adds r3, #250 ; 0xfa 800264e: 429a cmp r2, r3 8002650: d907 bls.n 8002662 { bt->code=-1; 8002652: 687b ldr r3, [r7, #4] 8002654: 2201 movs r2, #1 8002656: 4252 negs r2, r2 8002658: 601a str r2, [r3, #0] bt->times=-1; 800265a: 687b ldr r3, [r7, #4] 800265c: 2201 movs r2, #1 800265e: 4252 negs r2, r2 8002660: 60da str r2, [r3, #12] } } } if(in==0) 8002662: 1cfb adds r3, r7, #3 8002664: 781b ldrb r3, [r3, #0] 8002666: 2b00 cmp r3, #0 8002668: d10e bne.n 8002688 { if(bt->lock==1) 800266a: 687b ldr r3, [r7, #4] 800266c: 791b ldrb r3, [r3, #4] 800266e: 2b01 cmp r3, #1 8002670: d10a bne.n 8002688 { if(bt->code==-1) 8002672: 687b ldr r3, [r7, #4] 8002674: 681b ldr r3, [r3, #0] 8002676: 3301 adds r3, #1 8002678: d003 beq.n 8002682 { }else { bt->code=bt->times; 800267a: 687b ldr r3, [r7, #4] 800267c: 68da ldr r2, [r3, #12] 800267e: 687b ldr r3, [r7, #4] 8002680: 601a str r2, [r3, #0] } bt->lock=0; 8002682: 687b ldr r3, [r7, #4] 8002684: 2200 movs r2, #0 8002686: 711a strb r2, [r3, #4] } } } 8002688: 46c0 nop ; (mov r8, r8) 800268a: 46bd mov sp, r7 800268c: b002 add sp, #8 800268e: bd80 pop {r7, pc} 08002690 : eeprom_write_buff_info eeprom_write_buffer; void EPPROM_SLOWWRITE_INIT() { 8002690: b580 push {r7, lr} 8002692: af00 add r7, sp, #0 eeprom_write_buffer.buff=NULL; 8002694: 4b09 ldr r3, [pc, #36] ; (80026bc ) 8002696: 2200 movs r2, #0 8002698: 601a str r2, [r3, #0] eeprom_write_buffer.end=NULL; 800269a: 4b08 ldr r3, [pc, #32] ; (80026bc ) 800269c: 2200 movs r2, #0 800269e: 609a str r2, [r3, #8] eeprom_write_buffer.head=NULL; 80026a0: 4b06 ldr r3, [pc, #24] ; (80026bc ) 80026a2: 2200 movs r2, #0 80026a4: 605a str r2, [r3, #4] eeprom_write_buffer.save_timeout=5; 80026a6: 4b05 ldr r3, [pc, #20] ; (80026bc ) 80026a8: 2205 movs r2, #5 80026aa: 741a strb r2, [r3, #16] eeprom_write_buffer.save_busy=0; 80026ac: 4b03 ldr r3, [pc, #12] ; (80026bc ) 80026ae: 7c5a ldrb r2, [r3, #17] 80026b0: 2101 movs r1, #1 80026b2: 438a bics r2, r1 80026b4: 745a strb r2, [r3, #17] } 80026b6: 46c0 nop ; (mov r8, r8) 80026b8: 46bd mov sp, r7 80026ba: bd80 pop {r7, pc} 80026bc: 20000140 .word 0x20000140 080026c0 : void EEPROM_SLOWWRITE_SERVER() { 80026c0: b580 push {r7, lr} 80026c2: b082 sub sp, #8 80026c4: af00 add r7, sp, #0 eeprom_write_buff *buff; char data; if(eeprom_write_buffer.save_busy) 80026c6: 4b21 ldr r3, [pc, #132] ; (800274c ) 80026c8: 7c5b ldrb r3, [r3, #17] 80026ca: 2201 movs r2, #1 80026cc: 4013 ands r3, r2 80026ce: b2db uxtb r3, r3 80026d0: 2b00 cmp r3, #0 80026d2: d00c beq.n 80026ee { if(HAL_GetTick()>eeprom_write_buffer.save_time) 80026d4: f7fe f98c bl 80009f0 80026d8: 0002 movs r2, r0 80026da: 4b1c ldr r3, [pc, #112] ; (800274c ) 80026dc: 68db ldr r3, [r3, #12] 80026de: 429a cmp r2, r3 80026e0: d930 bls.n 8002744 { eeprom_write_buffer.save_busy=0; 80026e2: 4b1a ldr r3, [pc, #104] ; (800274c ) 80026e4: 7c5a ldrb r2, [r3, #17] 80026e6: 2101 movs r1, #1 80026e8: 438a bics r2, r1 80026ea: 745a strb r2, [r3, #17] free(eeprom_write_buffer.head); eeprom_write_buffer.head=buff; } } } 80026ec: e02a b.n 8002744 if(eeprom_write_buffer.head!=NULL) 80026ee: 4b17 ldr r3, [pc, #92] ; (800274c ) 80026f0: 685b ldr r3, [r3, #4] 80026f2: 2b00 cmp r3, #0 80026f4: d026 beq.n 8002744 eeprom_write_buffer.save_busy=1; 80026f6: 4b15 ldr r3, [pc, #84] ; (800274c ) 80026f8: 7c5a ldrb r2, [r3, #17] 80026fa: 2101 movs r1, #1 80026fc: 430a orrs r2, r1 80026fe: 745a strb r2, [r3, #17] eeprom_write_buffer.save_time=HAL_GetTick()+eeprom_write_buffer.save_timeout; 8002700: f7fe f976 bl 80009f0 8002704: 0002 movs r2, r0 8002706: 4b11 ldr r3, [pc, #68] ; (800274c ) 8002708: 7c1b ldrb r3, [r3, #16] 800270a: 18d2 adds r2, r2, r3 800270c: 4b0f ldr r3, [pc, #60] ; (800274c ) 800270e: 60da str r2, [r3, #12] buff=eeprom_write_buffer.head->next; 8002710: 4b0e ldr r3, [pc, #56] ; (800274c ) 8002712: 685b ldr r3, [r3, #4] 8002714: 681b ldr r3, [r3, #0] 8002716: 607b str r3, [r7, #4] data=eeprom_write_buffer.head->date; 8002718: 4b0c ldr r3, [pc, #48] ; (800274c ) 800271a: 685b ldr r3, [r3, #4] 800271c: 799a ldrb r2, [r3, #6] 800271e: 1cfb adds r3, r7, #3 8002720: 701a strb r2, [r3, #0] IIC_SAND_DATE(EEPROM_ADDRESS,eeprom_write_buffer.head->add,&data,1); 8002722: 4b0a ldr r3, [pc, #40] ; (800274c ) 8002724: 685b ldr r3, [r3, #4] 8002726: 889b ldrh r3, [r3, #4] 8002728: b2d9 uxtb r1, r3 800272a: 1cfa adds r2, r7, #3 800272c: 2301 movs r3, #1 800272e: 20a0 movs r0, #160 ; 0xa0 8002730: f000 fac8 bl 8002cc4 free(eeprom_write_buffer.head); 8002734: 4b05 ldr r3, [pc, #20] ; (800274c ) 8002736: 685b ldr r3, [r3, #4] 8002738: 0018 movs r0, r3 800273a: f001 fa85 bl 8003c48 eeprom_write_buffer.head=buff; 800273e: 4b03 ldr r3, [pc, #12] ; (800274c ) 8002740: 687a ldr r2, [r7, #4] 8002742: 605a str r2, [r3, #4] } 8002744: 46c0 nop ; (mov r8, r8) 8002746: 46bd mov sp, r7 8002748: b002 add sp, #8 800274a: bd80 pop {r7, pc} 800274c: 20000140 .word 0x20000140 08002750 : void EEPROM_READ_BATY(uint16_t IN_DEVICE_ADD,char *DATAS,uint16_t LONG) { 8002750: b580 push {r7, lr} 8002752: b082 sub sp, #8 8002754: af00 add r7, sp, #0 8002756: 6039 str r1, [r7, #0] 8002758: 0011 movs r1, r2 800275a: 1dbb adds r3, r7, #6 800275c: 1c02 adds r2, r0, #0 800275e: 801a strh r2, [r3, #0] 8002760: 1d3b adds r3, r7, #4 8002762: 1c0a adds r2, r1, #0 8002764: 801a strh r2, [r3, #0] IIC_READ_DATE(EEPROM_ADDRESS,IN_DEVICE_ADD,DATAS,LONG); 8002766: 1dbb adds r3, r7, #6 8002768: 881b ldrh r3, [r3, #0] 800276a: b2d9 uxtb r1, r3 800276c: 1d3b adds r3, r7, #4 800276e: 881b ldrh r3, [r3, #0] 8002770: 683a ldr r2, [r7, #0] 8002772: 20a0 movs r0, #160 ; 0xa0 8002774: f000 fae1 bl 8002d3a } 8002778: 46c0 nop ; (mov r8, r8) 800277a: 46bd mov sp, r7 800277c: b002 add sp, #8 800277e: bd80 pop {r7, pc} 08002780 : * Author: wuwenfeng */ #include "gpio.h" void change_io_function(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin,char a) { 8002780: b580 push {r7, lr} 8002782: b088 sub sp, #32 8002784: af00 add r7, sp, #0 8002786: 6078 str r0, [r7, #4] 8002788: 0008 movs r0, r1 800278a: 0011 movs r1, r2 800278c: 1cbb adds r3, r7, #2 800278e: 1c02 adds r2, r0, #0 8002790: 801a strh r2, [r3, #0] 8002792: 1c7b adds r3, r7, #1 8002794: 1c0a adds r2, r1, #0 8002796: 701a strb r2, [r3, #0] GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_Pin; 8002798: 1cbb adds r3, r7, #2 800279a: 881a ldrh r2, [r3, #0] 800279c: 210c movs r1, #12 800279e: 187b adds r3, r7, r1 80027a0: 601a str r2, [r3, #0] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80027a2: 187b adds r3, r7, r1 80027a4: 2203 movs r2, #3 80027a6: 60da str r2, [r3, #12] if(a==1) 80027a8: 1c7b adds r3, r7, #1 80027aa: 781b ldrb r3, [r3, #0] 80027ac: 2b01 cmp r3, #1 80027ae: d105 bne.n 80027bc { GPIO_InitStruct.Pull = GPIO_PULLUP; 80027b0: 187b adds r3, r7, r1 80027b2: 2201 movs r2, #1 80027b4: 609a str r2, [r3, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80027b6: 187b adds r3, r7, r1 80027b8: 2200 movs r2, #0 80027ba: 605a str r2, [r3, #4] } if(a==0) 80027bc: 1c7b adds r3, r7, #1 80027be: 781b ldrb r3, [r3, #0] 80027c0: 2b00 cmp r3, #0 80027c2: d106 bne.n 80027d2 { GPIO_InitStruct.Pull = GPIO_NOPULL; 80027c4: 210c movs r1, #12 80027c6: 187b adds r3, r7, r1 80027c8: 2200 movs r2, #0 80027ca: 609a str r2, [r3, #8] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80027cc: 187b adds r3, r7, r1 80027ce: 2201 movs r2, #1 80027d0: 605a str r2, [r3, #4] } HAL_GPIO_Init(GPIOx, &GPIO_InitStruct); 80027d2: 230c movs r3, #12 80027d4: 18fa adds r2, r7, r3 80027d6: 687b ldr r3, [r7, #4] 80027d8: 0011 movs r1, r2 80027da: 0018 movs r0, r3 80027dc: f7fe fea0 bl 8001520 } 80027e0: 46c0 nop ; (mov r8, r8) 80027e2: 46bd mov sp, r7 80027e4: b008 add sp, #32 80027e6: bd80 pop {r7, pc} 080027e8 : #include "my_code.h" #define HT1621_addrbit 6 void WriteClockHT1621(void) { 80027e8: b580 push {r7, lr} 80027ea: af00 add r7, sp, #0 HC595_SCK(0); 80027ec: 2390 movs r3, #144 ; 0x90 80027ee: 05db lsls r3, r3, #23 80027f0: 2200 movs r2, #0 80027f2: 2140 movs r1, #64 ; 0x40 80027f4: 0018 movs r0, r3 80027f6: f7ff f820 bl 800183a HC595_SCK(1); 80027fa: 2390 movs r3, #144 ; 0x90 80027fc: 05db lsls r3, r3, #23 80027fe: 2201 movs r2, #1 8002800: 2140 movs r1, #64 ; 0x40 8002802: 0018 movs r0, r3 8002804: f7ff f819 bl 800183a } 8002808: 46c0 nop ; (mov r8, r8) 800280a: 46bd mov sp, r7 800280c: bd80 pop {r7, pc} 0800280e : void WriteCommandHT1621(unsigned char FunctonCode) { 800280e: b580 push {r7, lr} 8002810: b084 sub sp, #16 8002812: af00 add r7, sp, #0 8002814: 0002 movs r2, r0 8002816: 1dfb adds r3, r7, #7 8002818: 701a strb r2, [r3, #0] unsigned char Shift = 0x80; 800281a: 230f movs r3, #15 800281c: 18fb adds r3, r7, r3 800281e: 2280 movs r2, #128 ; 0x80 8002820: 701a strb r2, [r3, #0] unsigned char i; HC595_RCK(0); 8002822: 2390 movs r3, #144 ; 0x90 8002824: 05db lsls r3, r3, #23 8002826: 2200 movs r2, #0 8002828: 2180 movs r1, #128 ; 0x80 800282a: 0018 movs r0, r3 800282c: f7ff f805 bl 800183a HC595_DCK(1); 8002830: 2390 movs r3, #144 ; 0x90 8002832: 05db lsls r3, r3, #23 8002834: 2201 movs r2, #1 8002836: 2120 movs r1, #32 8002838: 0018 movs r0, r3 800283a: f7fe fffe bl 800183a WriteClockHT1621(); 800283e: f7ff ffd3 bl 80027e8 HC595_DCK(0); 8002842: 2390 movs r3, #144 ; 0x90 8002844: 05db lsls r3, r3, #23 8002846: 2200 movs r2, #0 8002848: 2120 movs r1, #32 800284a: 0018 movs r0, r3 800284c: f7fe fff5 bl 800183a WriteClockHT1621(); 8002850: f7ff ffca bl 80027e8 HC595_DCK(0); 8002854: 2390 movs r3, #144 ; 0x90 8002856: 05db lsls r3, r3, #23 8002858: 2200 movs r2, #0 800285a: 2120 movs r1, #32 800285c: 0018 movs r0, r3 800285e: f7fe ffec bl 800183a WriteClockHT1621(); 8002862: f7ff ffc1 bl 80027e8 for(i = 0; i < 8; i++) 8002866: 230e movs r3, #14 8002868: 18fb adds r3, r7, r3 800286a: 2200 movs r2, #0 800286c: 701a strb r2, [r3, #0] 800286e: e025 b.n 80028bc { if(Shift & FunctonCode) 8002870: 230f movs r3, #15 8002872: 18fb adds r3, r7, r3 8002874: 1dfa adds r2, r7, #7 8002876: 781b ldrb r3, [r3, #0] 8002878: 7812 ldrb r2, [r2, #0] 800287a: 4013 ands r3, r2 800287c: b2db uxtb r3, r3 800287e: 2b00 cmp r3, #0 8002880: d007 beq.n 8002892 {HC595_DCK(1);} 8002882: 2390 movs r3, #144 ; 0x90 8002884: 05db lsls r3, r3, #23 8002886: 2201 movs r2, #1 8002888: 2120 movs r1, #32 800288a: 0018 movs r0, r3 800288c: f7fe ffd5 bl 800183a 8002890: e006 b.n 80028a0 else {HC595_DCK(0);} 8002892: 2390 movs r3, #144 ; 0x90 8002894: 05db lsls r3, r3, #23 8002896: 2200 movs r2, #0 8002898: 2120 movs r1, #32 800289a: 0018 movs r0, r3 800289c: f7fe ffcd bl 800183a WriteClockHT1621(); 80028a0: f7ff ffa2 bl 80027e8 Shift = Shift >> 1; 80028a4: 220f movs r2, #15 80028a6: 18bb adds r3, r7, r2 80028a8: 18ba adds r2, r7, r2 80028aa: 7812 ldrb r2, [r2, #0] 80028ac: 0852 lsrs r2, r2, #1 80028ae: 701a strb r2, [r3, #0] for(i = 0; i < 8; i++) 80028b0: 210e movs r1, #14 80028b2: 187b adds r3, r7, r1 80028b4: 781a ldrb r2, [r3, #0] 80028b6: 187b adds r3, r7, r1 80028b8: 3201 adds r2, #1 80028ba: 701a strb r2, [r3, #0] 80028bc: 230e movs r3, #14 80028be: 18fb adds r3, r7, r3 80028c0: 781b ldrb r3, [r3, #0] 80028c2: 2b07 cmp r3, #7 80028c4: d9d4 bls.n 8002870 } {HC595_DCK(0);} 80028c6: 2390 movs r3, #144 ; 0x90 80028c8: 05db lsls r3, r3, #23 80028ca: 2200 movs r2, #0 80028cc: 2120 movs r1, #32 80028ce: 0018 movs r0, r3 80028d0: f7fe ffb3 bl 800183a WriteClockHT1621(); 80028d4: f7ff ff88 bl 80027e8 HC595_RCK(1); 80028d8: 2390 movs r3, #144 ; 0x90 80028da: 05db lsls r3, r3, #23 80028dc: 2201 movs r2, #1 80028de: 2180 movs r1, #128 ; 0x80 80028e0: 0018 movs r0, r3 80028e2: f7fe ffaa bl 800183a HC595_DCK(1); 80028e6: 2390 movs r3, #144 ; 0x90 80028e8: 05db lsls r3, r3, #23 80028ea: 2201 movs r2, #1 80028ec: 2120 movs r1, #32 80028ee: 0018 movs r0, r3 80028f0: f7fe ffa3 bl 800183a } 80028f4: 46c0 nop ; (mov r8, r8) 80028f6: 46bd mov sp, r7 80028f8: b004 add sp, #16 80028fa: bd80 pop {r7, pc} 080028fc : void WritenDataHT1621(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt) { 80028fc: b580 push {r7, lr} 80028fe: b084 sub sp, #16 8002900: af00 add r7, sp, #0 8002902: 6039 str r1, [r7, #0] 8002904: 0011 movs r1, r2 8002906: 1dfb adds r3, r7, #7 8002908: 1c02 adds r2, r0, #0 800290a: 701a strb r2, [r3, #0] 800290c: 1dbb adds r3, r7, #6 800290e: 1c0a adds r2, r1, #0 8002910: 701a strb r2, [r3, #0] unsigned char i,j; unsigned char Shift; unsigned char dataval; HC595_RCK(0); 8002912: 2390 movs r3, #144 ; 0x90 8002914: 05db lsls r3, r3, #23 8002916: 2200 movs r2, #0 8002918: 2180 movs r1, #128 ; 0x80 800291a: 0018 movs r0, r3 800291c: f7fe ff8d bl 800183a HC595_DCK(1); //101 8002920: 2390 movs r3, #144 ; 0x90 8002922: 05db lsls r3, r3, #23 8002924: 2201 movs r2, #1 8002926: 2120 movs r1, #32 8002928: 0018 movs r0, r3 800292a: f7fe ff86 bl 800183a WriteClockHT1621(); 800292e: f7ff ff5b bl 80027e8 HC595_DCK(0); 8002932: 2390 movs r3, #144 ; 0x90 8002934: 05db lsls r3, r3, #23 8002936: 2200 movs r2, #0 8002938: 2120 movs r1, #32 800293a: 0018 movs r0, r3 800293c: f7fe ff7d bl 800183a WriteClockHT1621(); 8002940: f7ff ff52 bl 80027e8 HC595_DCK(1); 8002944: 2390 movs r3, #144 ; 0x90 8002946: 05db lsls r3, r3, #23 8002948: 2201 movs r2, #1 800294a: 2120 movs r1, #32 800294c: 0018 movs r0, r3 800294e: f7fe ff74 bl 800183a WriteClockHT1621(); 8002952: f7ff ff49 bl 80027e8 Shift = 0x20; 8002956: 230d movs r3, #13 8002958: 18fb adds r3, r7, r3 800295a: 2220 movs r2, #32 800295c: 701a strb r2, [r3, #0] for( i = 0; i < HT1621_addrbit; i++) 800295e: 230f movs r3, #15 8002960: 18fb adds r3, r7, r3 8002962: 2200 movs r2, #0 8002964: 701a strb r2, [r3, #0] 8002966: e025 b.n 80029b4 { if (Addr & Shift) 8002968: 1dfb adds r3, r7, #7 800296a: 220d movs r2, #13 800296c: 18ba adds r2, r7, r2 800296e: 781b ldrb r3, [r3, #0] 8002970: 7812 ldrb r2, [r2, #0] 8002972: 4013 ands r3, r2 8002974: b2db uxtb r3, r3 8002976: 2b00 cmp r3, #0 8002978: d007 beq.n 800298a {HC595_DCK(1);} 800297a: 2390 movs r3, #144 ; 0x90 800297c: 05db lsls r3, r3, #23 800297e: 2201 movs r2, #1 8002980: 2120 movs r1, #32 8002982: 0018 movs r0, r3 8002984: f7fe ff59 bl 800183a 8002988: e006 b.n 8002998 else {HC595_DCK(0);} 800298a: 2390 movs r3, #144 ; 0x90 800298c: 05db lsls r3, r3, #23 800298e: 2200 movs r2, #0 8002990: 2120 movs r1, #32 8002992: 0018 movs r0, r3 8002994: f7fe ff51 bl 800183a WriteClockHT1621(); 8002998: f7ff ff26 bl 80027e8 Shift = Shift >> 1; 800299c: 220d movs r2, #13 800299e: 18bb adds r3, r7, r2 80029a0: 18ba adds r2, r7, r2 80029a2: 7812 ldrb r2, [r2, #0] 80029a4: 0852 lsrs r2, r2, #1 80029a6: 701a strb r2, [r3, #0] for( i = 0; i < HT1621_addrbit; i++) 80029a8: 210f movs r1, #15 80029aa: 187b adds r3, r7, r1 80029ac: 781a ldrb r2, [r3, #0] 80029ae: 187b adds r3, r7, r1 80029b0: 3201 adds r2, #1 80029b2: 701a strb r2, [r3, #0] 80029b4: 230f movs r3, #15 80029b6: 18fb adds r3, r7, r3 80029b8: 781b ldrb r3, [r3, #0] 80029ba: 2b05 cmp r3, #5 80029bc: d9d4 bls.n 8002968 } for (j = 0; j < Cnt; j++) 80029be: 230e movs r3, #14 80029c0: 18fb adds r3, r7, r3 80029c2: 2200 movs r2, #0 80029c4: 701a strb r2, [r3, #0] 80029c6: e041 b.n 8002a4c { Shift = 0x01; 80029c8: 230d movs r3, #13 80029ca: 18fb adds r3, r7, r3 80029cc: 2201 movs r2, #1 80029ce: 701a strb r2, [r3, #0] dataval=*Databuf++; 80029d0: 683b ldr r3, [r7, #0] 80029d2: 1c5a adds r2, r3, #1 80029d4: 603a str r2, [r7, #0] 80029d6: 220c movs r2, #12 80029d8: 18ba adds r2, r7, r2 80029da: 781b ldrb r3, [r3, #0] 80029dc: 7013 strb r3, [r2, #0] for (i = 0; i < 4; i++) 80029de: 230f movs r3, #15 80029e0: 18fb adds r3, r7, r3 80029e2: 2200 movs r2, #0 80029e4: 701a strb r2, [r3, #0] 80029e6: e026 b.n 8002a36 { if( dataval & Shift) 80029e8: 230c movs r3, #12 80029ea: 18fb adds r3, r7, r3 80029ec: 220d movs r2, #13 80029ee: 18ba adds r2, r7, r2 80029f0: 781b ldrb r3, [r3, #0] 80029f2: 7812 ldrb r2, [r2, #0] 80029f4: 4013 ands r3, r2 80029f6: b2db uxtb r3, r3 80029f8: 2b00 cmp r3, #0 80029fa: d007 beq.n 8002a0c {HC595_DCK(1);} 80029fc: 2390 movs r3, #144 ; 0x90 80029fe: 05db lsls r3, r3, #23 8002a00: 2201 movs r2, #1 8002a02: 2120 movs r1, #32 8002a04: 0018 movs r0, r3 8002a06: f7fe ff18 bl 800183a 8002a0a: e006 b.n 8002a1a else {HC595_DCK(0);} 8002a0c: 2390 movs r3, #144 ; 0x90 8002a0e: 05db lsls r3, r3, #23 8002a10: 2200 movs r2, #0 8002a12: 2120 movs r1, #32 8002a14: 0018 movs r0, r3 8002a16: f7fe ff10 bl 800183a WriteClockHT1621(); 8002a1a: f7ff fee5 bl 80027e8 Shift = Shift << 1; 8002a1e: 230d movs r3, #13 8002a20: 18fa adds r2, r7, r3 8002a22: 18fb adds r3, r7, r3 8002a24: 781b ldrb r3, [r3, #0] 8002a26: 18db adds r3, r3, r3 8002a28: 7013 strb r3, [r2, #0] for (i = 0; i < 4; i++) 8002a2a: 210f movs r1, #15 8002a2c: 187b adds r3, r7, r1 8002a2e: 781a ldrb r2, [r3, #0] 8002a30: 187b adds r3, r7, r1 8002a32: 3201 adds r2, #1 8002a34: 701a strb r2, [r3, #0] 8002a36: 230f movs r3, #15 8002a38: 18fb adds r3, r7, r3 8002a3a: 781b ldrb r3, [r3, #0] 8002a3c: 2b03 cmp r3, #3 8002a3e: d9d3 bls.n 80029e8 for (j = 0; j < Cnt; j++) 8002a40: 210e movs r1, #14 8002a42: 187b adds r3, r7, r1 8002a44: 781a ldrb r2, [r3, #0] 8002a46: 187b adds r3, r7, r1 8002a48: 3201 adds r2, #1 8002a4a: 701a strb r2, [r3, #0] 8002a4c: 230e movs r3, #14 8002a4e: 18fa adds r2, r7, r3 8002a50: 1dbb adds r3, r7, #6 8002a52: 7812 ldrb r2, [r2, #0] 8002a54: 781b ldrb r3, [r3, #0] 8002a56: 429a cmp r2, r3 8002a58: d3b6 bcc.n 80029c8 } } HC595_RCK(1); 8002a5a: 2390 movs r3, #144 ; 0x90 8002a5c: 05db lsls r3, r3, #23 8002a5e: 2201 movs r2, #1 8002a60: 2180 movs r1, #128 ; 0x80 8002a62: 0018 movs r0, r3 8002a64: f7fe fee9 bl 800183a HC595_DCK(1); 8002a68: 2390 movs r3, #144 ; 0x90 8002a6a: 05db lsls r3, r3, #23 8002a6c: 2201 movs r2, #1 8002a6e: 2120 movs r1, #32 8002a70: 0018 movs r0, r3 8002a72: f7fe fee2 bl 800183a } 8002a76: 46c0 nop ; (mov r8, r8) 8002a78: 46bd mov sp, r7 8002a7a: b004 add sp, #16 8002a7c: bd80 pop {r7, pc} 08002a7e : void HT1621_Init(void) { 8002a7e: b580 push {r7, lr} 8002a80: af00 add r7, sp, #0 HC595_RCK(1); 8002a82: 2390 movs r3, #144 ; 0x90 8002a84: 05db lsls r3, r3, #23 8002a86: 2201 movs r2, #1 8002a88: 2180 movs r1, #128 ; 0x80 8002a8a: 0018 movs r0, r3 8002a8c: f7fe fed5 bl 800183a HC595_SCK(1); 8002a90: 2390 movs r3, #144 ; 0x90 8002a92: 05db lsls r3, r3, #23 8002a94: 2201 movs r2, #1 8002a96: 2140 movs r1, #64 ; 0x40 8002a98: 0018 movs r0, r3 8002a9a: f7fe fece bl 800183a HC595_DCK(1); 8002a9e: 2390 movs r3, #144 ; 0x90 8002aa0: 05db lsls r3, r3, #23 8002aa2: 2201 movs r2, #1 8002aa4: 2120 movs r1, #32 8002aa6: 0018 movs r0, r3 8002aa8: f7fe fec7 bl 800183a WriteCommandHT1621(OSC_ON); 8002aac: 2001 movs r0, #1 8002aae: f7ff feae bl 800280e WriteCommandHT1621(DISP_ON); 8002ab2: 2003 movs r0, #3 8002ab4: f7ff feab bl 800280e WriteCommandHT1621(COM_1_3__4); 8002ab8: 2029 movs r0, #41 ; 0x29 8002aba: f7ff fea8 bl 800280e WriteCommandHT1621(TIMER_DIS); 8002abe: 2004 movs r0, #4 8002ac0: f7ff fea5 bl 800280e WriteCommandHT1621(WDT_DIS); 8002ac4: 2005 movs r0, #5 8002ac6: f7ff fea2 bl 800280e WriteCommandHT1621(BUZZ_OFF); 8002aca: 2008 movs r0, #8 8002acc: f7ff fe9f bl 800280e WriteCommandHT1621(IRQ_DIS); 8002ad0: 2080 movs r0, #128 ; 0x80 8002ad2: f7ff fe9c bl 800280e } 8002ad6: 46c0 nop ; (mov r8, r8) 8002ad8: 46bd mov sp, r7 8002ada: bd80 pop {r7, pc} 08002adc : #define iic_scl(x) HAL_GPIO_WritePin(iic_scl_GPIO_Port, iic_scl_Pin, x) #define read_iic_sda HAL_GPIO_ReadPin(iic_sda_GPIO_Port, iic_sda_Pin) void iic_start() { 8002adc: b580 push {r7, lr} 8002ade: af00 add r7, sp, #0 iic_sda(1); 8002ae0: 4b0f ldr r3, [pc, #60] ; (8002b20 ) 8002ae2: 2201 movs r2, #1 8002ae4: 2102 movs r1, #2 8002ae6: 0018 movs r0, r3 8002ae8: f7fe fea7 bl 800183a iic_scl(1); 8002aec: 2380 movs r3, #128 ; 0x80 8002aee: 00d9 lsls r1, r3, #3 8002af0: 2390 movs r3, #144 ; 0x90 8002af2: 05db lsls r3, r3, #23 8002af4: 2201 movs r2, #1 8002af6: 0018 movs r0, r3 8002af8: f7fe fe9f bl 800183a iic_sda(0); 8002afc: 4b08 ldr r3, [pc, #32] ; (8002b20 ) 8002afe: 2200 movs r2, #0 8002b00: 2102 movs r1, #2 8002b02: 0018 movs r0, r3 8002b04: f7fe fe99 bl 800183a iic_scl(0); 8002b08: 2380 movs r3, #128 ; 0x80 8002b0a: 00d9 lsls r1, r3, #3 8002b0c: 2390 movs r3, #144 ; 0x90 8002b0e: 05db lsls r3, r3, #23 8002b10: 2200 movs r2, #0 8002b12: 0018 movs r0, r3 8002b14: f7fe fe91 bl 800183a } 8002b18: 46c0 nop ; (mov r8, r8) 8002b1a: 46bd mov sp, r7 8002b1c: bd80 pop {r7, pc} 8002b1e: 46c0 nop ; (mov r8, r8) 8002b20: 48000400 .word 0x48000400 08002b24 : void iic_stop() { 8002b24: b580 push {r7, lr} 8002b26: af00 add r7, sp, #0 iic_sda(0); 8002b28: 4b0b ldr r3, [pc, #44] ; (8002b58 ) 8002b2a: 2200 movs r2, #0 8002b2c: 2102 movs r1, #2 8002b2e: 0018 movs r0, r3 8002b30: f7fe fe83 bl 800183a iic_scl(1); 8002b34: 2380 movs r3, #128 ; 0x80 8002b36: 00d9 lsls r1, r3, #3 8002b38: 2390 movs r3, #144 ; 0x90 8002b3a: 05db lsls r3, r3, #23 8002b3c: 2201 movs r2, #1 8002b3e: 0018 movs r0, r3 8002b40: f7fe fe7b bl 800183a iic_sda(1); 8002b44: 4b04 ldr r3, [pc, #16] ; (8002b58 ) 8002b46: 2201 movs r2, #1 8002b48: 2102 movs r1, #2 8002b4a: 0018 movs r0, r3 8002b4c: f7fe fe75 bl 800183a } 8002b50: 46c0 nop ; (mov r8, r8) 8002b52: 46bd mov sp, r7 8002b54: bd80 pop {r7, pc} 8002b56: 46c0 nop ; (mov r8, r8) 8002b58: 48000400 .word 0x48000400 08002b5c : void iic_ack() { 8002b5c: b580 push {r7, lr} 8002b5e: af00 add r7, sp, #0 iic_scl(1); 8002b60: 2380 movs r3, #128 ; 0x80 8002b62: 00d9 lsls r1, r3, #3 8002b64: 2390 movs r3, #144 ; 0x90 8002b66: 05db lsls r3, r3, #23 8002b68: 2201 movs r2, #1 8002b6a: 0018 movs r0, r3 8002b6c: f7fe fe65 bl 800183a iic_scl(0); 8002b70: 2380 movs r3, #128 ; 0x80 8002b72: 00d9 lsls r1, r3, #3 8002b74: 2390 movs r3, #144 ; 0x90 8002b76: 05db lsls r3, r3, #23 8002b78: 2200 movs r2, #0 8002b7a: 0018 movs r0, r3 8002b7c: f7fe fe5d bl 800183a } 8002b80: 46c0 nop ; (mov r8, r8) 8002b82: 46bd mov sp, r7 8002b84: bd80 pop {r7, pc} ... 08002b88 : void IIC_Write_Byte(unsigned char IIC_Byte){ 8002b88: b580 push {r7, lr} 8002b8a: b084 sub sp, #16 8002b8c: af00 add r7, sp, #0 8002b8e: 0002 movs r2, r0 8002b90: 1dfb adds r3, r7, #7 8002b92: 701a strb r2, [r3, #0] iic_scl(0); 8002b94: 2380 movs r3, #128 ; 0x80 8002b96: 00d9 lsls r1, r3, #3 8002b98: 2390 movs r3, #144 ; 0x90 8002b9a: 05db lsls r3, r3, #23 8002b9c: 2200 movs r2, #0 8002b9e: 0018 movs r0, r3 8002ba0: f7fe fe4b bl 800183a change_io_function(iic_sda_GPIO_Port, iic_sda_Pin,0); 8002ba4: 4b20 ldr r3, [pc, #128] ; (8002c28 ) 8002ba6: 2200 movs r2, #0 8002ba8: 2102 movs r1, #2 8002baa: 0018 movs r0, r3 8002bac: f7ff fde8 bl 8002780 for(unsigned char i=0;i<8;i++) 8002bb0: 230f movs r3, #15 8002bb2: 18fb adds r3, r7, r3 8002bb4: 2200 movs r2, #0 8002bb6: 701a strb r2, [r3, #0] 8002bb8: e02c b.n 8002c14 { if(IIC_Byte & 0x80) 8002bba: 1dfb adds r3, r7, #7 8002bbc: 781b ldrb r3, [r3, #0] 8002bbe: b25b sxtb r3, r3 8002bc0: 2b00 cmp r3, #0 8002bc2: da06 bge.n 8002bd2 { iic_sda(1); 8002bc4: 4b18 ldr r3, [pc, #96] ; (8002c28 ) 8002bc6: 2201 movs r2, #1 8002bc8: 2102 movs r1, #2 8002bca: 0018 movs r0, r3 8002bcc: f7fe fe35 bl 800183a 8002bd0: e005 b.n 8002bde }else{ iic_sda(0); 8002bd2: 4b15 ldr r3, [pc, #84] ; (8002c28 ) 8002bd4: 2200 movs r2, #0 8002bd6: 2102 movs r1, #2 8002bd8: 0018 movs r0, r3 8002bda: f7fe fe2e bl 800183a } IIC_Byte<<=1; 8002bde: 1dfa adds r2, r7, #7 8002be0: 1dfb adds r3, r7, #7 8002be2: 781b ldrb r3, [r3, #0] 8002be4: 18db adds r3, r3, r3 8002be6: 7013 strb r3, [r2, #0] iic_scl(1); 8002be8: 2380 movs r3, #128 ; 0x80 8002bea: 00d9 lsls r1, r3, #3 8002bec: 2390 movs r3, #144 ; 0x90 8002bee: 05db lsls r3, r3, #23 8002bf0: 2201 movs r2, #1 8002bf2: 0018 movs r0, r3 8002bf4: f7fe fe21 bl 800183a iic_scl(0); 8002bf8: 2380 movs r3, #128 ; 0x80 8002bfa: 00d9 lsls r1, r3, #3 8002bfc: 2390 movs r3, #144 ; 0x90 8002bfe: 05db lsls r3, r3, #23 8002c00: 2200 movs r2, #0 8002c02: 0018 movs r0, r3 8002c04: f7fe fe19 bl 800183a for(unsigned char i=0;i<8;i++) 8002c08: 210f movs r1, #15 8002c0a: 187b adds r3, r7, r1 8002c0c: 781a ldrb r2, [r3, #0] 8002c0e: 187b adds r3, r7, r1 8002c10: 3201 adds r2, #1 8002c12: 701a strb r2, [r3, #0] 8002c14: 230f movs r3, #15 8002c16: 18fb adds r3, r7, r3 8002c18: 781b ldrb r3, [r3, #0] 8002c1a: 2b07 cmp r3, #7 8002c1c: d9cd bls.n 8002bba } } 8002c1e: 46c0 nop ; (mov r8, r8) 8002c20: 46c0 nop ; (mov r8, r8) 8002c22: 46bd mov sp, r7 8002c24: b004 add sp, #16 8002c26: bd80 pop {r7, pc} 8002c28: 48000400 .word 0x48000400 08002c2c : unsigned char IIC_Read_Byte() { 8002c2c: b580 push {r7, lr} 8002c2e: b082 sub sp, #8 8002c30: af00 add r7, sp, #0 unsigned char k=0; 8002c32: 1dfb adds r3, r7, #7 8002c34: 2200 movs r2, #0 8002c36: 701a strb r2, [r3, #0] iic_scl(0); 8002c38: 2380 movs r3, #128 ; 0x80 8002c3a: 00d9 lsls r1, r3, #3 8002c3c: 2390 movs r3, #144 ; 0x90 8002c3e: 05db lsls r3, r3, #23 8002c40: 2200 movs r2, #0 8002c42: 0018 movs r0, r3 8002c44: f7fe fdf9 bl 800183a change_io_function(iic_sda_GPIO_Port, iic_sda_Pin,1); 8002c48: 4b1d ldr r3, [pc, #116] ; (8002cc0 ) 8002c4a: 2201 movs r2, #1 8002c4c: 2102 movs r1, #2 8002c4e: 0018 movs r0, r3 8002c50: f7ff fd96 bl 8002780 for(unsigned char i=0; i<8; i++) 8002c54: 1dbb adds r3, r7, #6 8002c56: 2200 movs r2, #0 8002c58: 701a strb r2, [r3, #0] 8002c5a: e027 b.n 8002cac { iic_scl(1); 8002c5c: 2380 movs r3, #128 ; 0x80 8002c5e: 00d9 lsls r1, r3, #3 8002c60: 2390 movs r3, #144 ; 0x90 8002c62: 05db lsls r3, r3, #23 8002c64: 2201 movs r2, #1 8002c66: 0018 movs r0, r3 8002c68: f7fe fde7 bl 800183a if(read_iic_sda==1) 8002c6c: 4b14 ldr r3, [pc, #80] ; (8002cc0 ) 8002c6e: 2102 movs r1, #2 8002c70: 0018 movs r0, r3 8002c72: f7fe fdc5 bl 8001800 8002c76: 0003 movs r3, r0 8002c78: 2b01 cmp r3, #1 8002c7a: d105 bne.n 8002c88 { k|=0x01; 8002c7c: 1dfb adds r3, r7, #7 8002c7e: 1dfa adds r2, r7, #7 8002c80: 7812 ldrb r2, [r2, #0] 8002c82: 2101 movs r1, #1 8002c84: 430a orrs r2, r1 8002c86: 701a strb r2, [r3, #0] } k<<=1; 8002c88: 1dfa adds r2, r7, #7 8002c8a: 1dfb adds r3, r7, #7 8002c8c: 781b ldrb r3, [r3, #0] 8002c8e: 18db adds r3, r3, r3 8002c90: 7013 strb r3, [r2, #0] iic_scl(0); 8002c92: 2380 movs r3, #128 ; 0x80 8002c94: 00d9 lsls r1, r3, #3 8002c96: 2390 movs r3, #144 ; 0x90 8002c98: 05db lsls r3, r3, #23 8002c9a: 2200 movs r2, #0 8002c9c: 0018 movs r0, r3 8002c9e: f7fe fdcc bl 800183a for(unsigned char i=0; i<8; i++) 8002ca2: 1dbb adds r3, r7, #6 8002ca4: 781a ldrb r2, [r3, #0] 8002ca6: 1dbb adds r3, r7, #6 8002ca8: 3201 adds r2, #1 8002caa: 701a strb r2, [r3, #0] 8002cac: 1dbb adds r3, r7, #6 8002cae: 781b ldrb r3, [r3, #0] 8002cb0: 2b07 cmp r3, #7 8002cb2: d9d3 bls.n 8002c5c } return(k); 8002cb4: 1dfb adds r3, r7, #7 8002cb6: 781b ldrb r3, [r3, #0] } 8002cb8: 0018 movs r0, r3 8002cba: 46bd mov sp, r7 8002cbc: b002 add sp, #8 8002cbe: bd80 pop {r7, pc} 8002cc0: 48000400 .word 0x48000400 08002cc4 : void IIC_SAND_DATE(unsigned char DEVICE_ADD,unsigned char IN_DEVICE_ADD,char *DATAS,uint16_t LONG) { 8002cc4: b590 push {r4, r7, lr} 8002cc6: b085 sub sp, #20 8002cc8: af00 add r7, sp, #0 8002cca: 0004 movs r4, r0 8002ccc: 0008 movs r0, r1 8002cce: 603a str r2, [r7, #0] 8002cd0: 0019 movs r1, r3 8002cd2: 1dfb adds r3, r7, #7 8002cd4: 1c22 adds r2, r4, #0 8002cd6: 701a strb r2, [r3, #0] 8002cd8: 1dbb adds r3, r7, #6 8002cda: 1c02 adds r2, r0, #0 8002cdc: 701a strb r2, [r3, #0] 8002cde: 1d3b adds r3, r7, #4 8002ce0: 1c0a adds r2, r1, #0 8002ce2: 801a strh r2, [r3, #0] iic_start(); 8002ce4: f7ff fefa bl 8002adc IIC_Write_Byte(DEVICE_ADD); 8002ce8: 1dfb adds r3, r7, #7 8002cea: 781b ldrb r3, [r3, #0] 8002cec: 0018 movs r0, r3 8002cee: f7ff ff4b bl 8002b88 iic_ack(); 8002cf2: f7ff ff33 bl 8002b5c IIC_Write_Byte(IN_DEVICE_ADD); 8002cf6: 1dbb adds r3, r7, #6 8002cf8: 781b ldrb r3, [r3, #0] 8002cfa: 0018 movs r0, r3 8002cfc: f7ff ff44 bl 8002b88 iic_ack(); 8002d00: f7ff ff2c bl 8002b5c for(int a=0;a { IIC_Write_Byte(*DATAS); 8002d0a: 683b ldr r3, [r7, #0] 8002d0c: 781b ldrb r3, [r3, #0] 8002d0e: 0018 movs r0, r3 8002d10: f7ff ff3a bl 8002b88 DATAS++; 8002d14: 683b ldr r3, [r7, #0] 8002d16: 3301 adds r3, #1 8002d18: 603b str r3, [r7, #0] for(int a=0;a } iic_ack(); 8002d2a: f7ff ff17 bl 8002b5c iic_stop(); 8002d2e: f7ff fef9 bl 8002b24 } 8002d32: 46c0 nop ; (mov r8, r8) 8002d34: 46bd mov sp, r7 8002d36: b005 add sp, #20 8002d38: bd90 pop {r4, r7, pc} 08002d3a : void IIC_READ_DATE(unsigned char DEVICE_ADD,unsigned char IN_DEVICE_ADD,char *DATAS,uint16_t LONG) { 8002d3a: b590 push {r4, r7, lr} 8002d3c: b085 sub sp, #20 8002d3e: af00 add r7, sp, #0 8002d40: 0004 movs r4, r0 8002d42: 0008 movs r0, r1 8002d44: 603a str r2, [r7, #0] 8002d46: 0019 movs r1, r3 8002d48: 1dfb adds r3, r7, #7 8002d4a: 1c22 adds r2, r4, #0 8002d4c: 701a strb r2, [r3, #0] 8002d4e: 1dbb adds r3, r7, #6 8002d50: 1c02 adds r2, r0, #0 8002d52: 701a strb r2, [r3, #0] 8002d54: 1d3b adds r3, r7, #4 8002d56: 1c0a adds r2, r1, #0 8002d58: 801a strh r2, [r3, #0] iic_start(); 8002d5a: f7ff febf bl 8002adc IIC_Write_Byte(DEVICE_ADD); 8002d5e: 1dfb adds r3, r7, #7 8002d60: 781b ldrb r3, [r3, #0] 8002d62: 0018 movs r0, r3 8002d64: f7ff ff10 bl 8002b88 iic_ack(); 8002d68: f7ff fef8 bl 8002b5c IIC_Write_Byte(IN_DEVICE_ADD); 8002d6c: 1dbb adds r3, r7, #6 8002d6e: 781b ldrb r3, [r3, #0] 8002d70: 0018 movs r0, r3 8002d72: f7ff ff09 bl 8002b88 iic_ack(); 8002d76: f7ff fef1 bl 8002b5c iic_start(); 8002d7a: f7ff feaf bl 8002adc IIC_Write_Byte(IN_DEVICE_ADD+1); 8002d7e: 1dbb adds r3, r7, #6 8002d80: 781b ldrb r3, [r3, #0] 8002d82: 3301 adds r3, #1 8002d84: b2db uxtb r3, r3 8002d86: 0018 movs r0, r3 8002d88: f7ff fefe bl 8002b88 iic_ack(); 8002d8c: f7ff fee6 bl 8002b5c for(int a=0;a { *DATAS=IIC_Read_Byte(); 8002d96: f7ff ff49 bl 8002c2c 8002d9a: 0003 movs r3, r0 8002d9c: 001a movs r2, r3 8002d9e: 683b ldr r3, [r7, #0] 8002da0: 701a strb r2, [r3, #0] DATAS++; 8002da2: 683b ldr r3, [r7, #0] 8002da4: 3301 adds r3, #1 8002da6: 603b str r3, [r7, #0] for(int a=0;a } iic_ack(); 8002db8: f7ff fed0 bl 8002b5c iic_stop(); 8002dbc: f7ff feb2 bl 8002b24 } 8002dc0: 46c0 nop ; (mov r8, r8) 8002dc2: 46bd mov sp, r7 8002dc4: b005 add sp, #20 8002dc6: bd90 pop {r4, r7, pc} 08002dc8 : //return READ_HC595_DCK; } //send data to 959 void Sand_Byte_to_595_2(uint8_t h) { 8002dc8: b580 push {r7, lr} 8002dca: b084 sub sp, #16 8002dcc: af00 add r7, sp, #0 8002dce: 0002 movs r2, r0 8002dd0: 1dfb adds r3, r7, #7 8002dd2: 701a strb r2, [r3, #0] change_io_function(HC595_DLK_GPIO_Port,HC595_DLK_Pin,0); 8002dd4: 2390 movs r3, #144 ; 0x90 8002dd6: 05db lsls r3, r3, #23 8002dd8: 2200 movs r2, #0 8002dda: 2120 movs r1, #32 8002ddc: 0018 movs r0, r3 8002dde: f7ff fccf bl 8002780 HC595_DCK(0); 8002de2: 2390 movs r3, #144 ; 0x90 8002de4: 05db lsls r3, r3, #23 8002de6: 2200 movs r2, #0 8002de8: 2120 movs r1, #32 8002dea: 0018 movs r0, r3 8002dec: f7fe fd25 bl 800183a HC595_SCK2(0); 8002df0: 2380 movs r3, #128 ; 0x80 8002df2: 0099 lsls r1, r3, #2 8002df4: 2390 movs r3, #144 ; 0x90 8002df6: 05db lsls r3, r3, #23 8002df8: 2200 movs r2, #0 8002dfa: 0018 movs r0, r3 8002dfc: f7fe fd1d bl 800183a HC595_RCK(0); 8002e00: 2390 movs r3, #144 ; 0x90 8002e02: 05db lsls r3, r3, #23 8002e04: 2200 movs r2, #0 8002e06: 2180 movs r1, #128 ; 0x80 8002e08: 0018 movs r0, r3 8002e0a: f7fe fd16 bl 800183a for(char a=0;a<8;a++) 8002e0e: 230f movs r3, #15 8002e10: 18fb adds r3, r7, r3 8002e12: 2200 movs r2, #0 8002e14: 701a strb r2, [r3, #0] 8002e16: e02e b.n 8002e76 { if((h< { HC595_DCK(1); 8002e2c: 2390 movs r3, #144 ; 0x90 8002e2e: 05db lsls r3, r3, #23 8002e30: 2201 movs r2, #1 8002e32: 2120 movs r1, #32 8002e34: 0018 movs r0, r3 8002e36: f7fe fd00 bl 800183a 8002e3a: e006 b.n 8002e4a }else { HC595_DCK(0); 8002e3c: 2390 movs r3, #144 ; 0x90 8002e3e: 05db lsls r3, r3, #23 8002e40: 2200 movs r2, #0 8002e42: 2120 movs r1, #32 8002e44: 0018 movs r0, r3 8002e46: f7fe fcf8 bl 800183a } HC595_SCK2(1); 8002e4a: 2380 movs r3, #128 ; 0x80 8002e4c: 0099 lsls r1, r3, #2 8002e4e: 2390 movs r3, #144 ; 0x90 8002e50: 05db lsls r3, r3, #23 8002e52: 2201 movs r2, #1 8002e54: 0018 movs r0, r3 8002e56: f7fe fcf0 bl 800183a HC595_SCK2(0); 8002e5a: 2380 movs r3, #128 ; 0x80 8002e5c: 0099 lsls r1, r3, #2 8002e5e: 2390 movs r3, #144 ; 0x90 8002e60: 05db lsls r3, r3, #23 8002e62: 2200 movs r2, #0 8002e64: 0018 movs r0, r3 8002e66: f7fe fce8 bl 800183a for(char a=0;a<8;a++) 8002e6a: 210f movs r1, #15 8002e6c: 187b adds r3, r7, r1 8002e6e: 781a ldrb r2, [r3, #0] 8002e70: 187b adds r3, r7, r1 8002e72: 3201 adds r2, #1 8002e74: 701a strb r2, [r3, #0] 8002e76: 230f movs r3, #15 8002e78: 18fb adds r3, r7, r3 8002e7a: 781b ldrb r3, [r3, #0] 8002e7c: 2b07 cmp r3, #7 8002e7e: d9cb bls.n 8002e18 } HC595_RCK(1); 8002e80: 2390 movs r3, #144 ; 0x90 8002e82: 05db lsls r3, r3, #23 8002e84: 2201 movs r2, #1 8002e86: 2180 movs r1, #128 ; 0x80 8002e88: 0018 movs r0, r3 8002e8a: f7fe fcd6 bl 800183a HC595_RCK(0); 8002e8e: 2390 movs r3, #144 ; 0x90 8002e90: 05db lsls r3, r3, #23 8002e92: 2200 movs r2, #0 8002e94: 2180 movs r1, #128 ; 0x80 8002e96: 0018 movs r0, r3 8002e98: f7fe fccf bl 800183a } 8002e9c: 46c0 nop ; (mov r8, r8) 8002e9e: 46bd mov sp, r7 8002ea0: b004 add sp, #16 8002ea2: bd80 pop {r7, pc} 08002ea4 : void hc2_sever() { 8002ea4: b580 push {r7, lr} 8002ea6: b082 sub sp, #8 8002ea8: af00 add r7, sp, #0 char h=0; 8002eaa: 1dfb adds r3, r7, #7 8002eac: 2200 movs r2, #0 8002eae: 701a strb r2, [r3, #0] if(dis_buff.led_run==1) 8002eb0: 4b1d ldr r3, [pc, #116] ; (8002f28 ) 8002eb2: 7b1b ldrb r3, [r3, #12] 8002eb4: 2b01 cmp r3, #1 8002eb6: d105 bne.n 8002ec4 { h|=0x01; 8002eb8: 1dfb adds r3, r7, #7 8002eba: 1dfa adds r2, r7, #7 8002ebc: 7812 ldrb r2, [r2, #0] 8002ebe: 2101 movs r1, #1 8002ec0: 430a orrs r2, r1 8002ec2: 701a strb r2, [r3, #0] } if(dis_buff.moto1a==1) 8002ec4: 4b18 ldr r3, [pc, #96] ; (8002f28 ) 8002ec6: 7b5b ldrb r3, [r3, #13] 8002ec8: 2b01 cmp r3, #1 8002eca: d105 bne.n 8002ed8 { h|=0x02; 8002ecc: 1dfb adds r3, r7, #7 8002ece: 1dfa adds r2, r7, #7 8002ed0: 7812 ldrb r2, [r2, #0] 8002ed2: 2102 movs r1, #2 8002ed4: 430a orrs r2, r1 8002ed6: 701a strb r2, [r3, #0] } if(dis_buff.moto1b==1) 8002ed8: 4b13 ldr r3, [pc, #76] ; (8002f28 ) 8002eda: 7b9b ldrb r3, [r3, #14] 8002edc: 2b01 cmp r3, #1 8002ede: d105 bne.n 8002eec { h|=0x04; 8002ee0: 1dfb adds r3, r7, #7 8002ee2: 1dfa adds r2, r7, #7 8002ee4: 7812 ldrb r2, [r2, #0] 8002ee6: 2104 movs r1, #4 8002ee8: 430a orrs r2, r1 8002eea: 701a strb r2, [r3, #0] } if(dis_buff.moto2a==1) 8002eec: 4b0e ldr r3, [pc, #56] ; (8002f28 ) 8002eee: 7bdb ldrb r3, [r3, #15] 8002ef0: 2b01 cmp r3, #1 8002ef2: d105 bne.n 8002f00 { h|=0x08; 8002ef4: 1dfb adds r3, r7, #7 8002ef6: 1dfa adds r2, r7, #7 8002ef8: 7812 ldrb r2, [r2, #0] 8002efa: 2108 movs r1, #8 8002efc: 430a orrs r2, r1 8002efe: 701a strb r2, [r3, #0] } if(dis_buff.moto2b==1) 8002f00: 4b09 ldr r3, [pc, #36] ; (8002f28 ) 8002f02: 7c1b ldrb r3, [r3, #16] 8002f04: 2b01 cmp r3, #1 8002f06: d105 bne.n 8002f14 { h|=0x10; 8002f08: 1dfb adds r3, r7, #7 8002f0a: 1dfa adds r2, r7, #7 8002f0c: 7812 ldrb r2, [r2, #0] 8002f0e: 2110 movs r1, #16 8002f10: 430a orrs r2, r1 8002f12: 701a strb r2, [r3, #0] } Sand_Byte_to_595_2(h); 8002f14: 1dfb adds r3, r7, #7 8002f16: 781b ldrb r3, [r3, #0] 8002f18: 0018 movs r0, r3 8002f1a: f7ff ff55 bl 8002dc8 } 8002f1e: 46c0 nop ; (mov r8, r8) 8002f20: 46bd mov sp, r7 8002f22: b002 add sp, #8 8002f24: bd80 pop {r7, pc} 8002f26: 46c0 nop ; (mov r8, r8) 8002f28: 200000a0 .word 0x200000a0 08002f2c : //motor cool start void moto_server() { 8002f2c: b580 push {r7, lr} 8002f2e: af00 add r7, sp, #0 if(HAL_GetTick()>moto.moto_run) 8002f30: f7fd fd5e bl 80009f0 8002f34: 0002 movs r2, r0 8002f36: 4b63 ldr r3, [pc, #396] ; (80030c4 ) 8002f38: 681b ldr r3, [r3, #0] 8002f3a: 429a cmp r2, r3 8002f3c: d800 bhi.n 8002f40 8002f3e: e07e b.n 800303e { moto.moto_run=HAL_GetTick()+10; 8002f40: f7fd fd56 bl 80009f0 8002f44: 0003 movs r3, r0 8002f46: 330a adds r3, #10 8002f48: 001a movs r2, r3 8002f4a: 4b5e ldr r3, [pc, #376] ; (80030c4 ) 8002f4c: 601a str r2, [r3, #0] if(moto.moto1a!=moto.moto1a_) 8002f4e: 4b5d ldr r3, [pc, #372] ; (80030c4 ) 8002f50: 7a1a ldrb r2, [r3, #8] 8002f52: 4b5c ldr r3, [pc, #368] ; (80030c4 ) 8002f54: 7b1b ldrb r3, [r3, #12] 8002f56: 429a cmp r2, r3 8002f58: d017 beq.n 8002f8a { if(moto.moto1a>moto.moto1a_) 8002f5a: 4b5a ldr r3, [pc, #360] ; (80030c4 ) 8002f5c: 7a1a ldrb r2, [r3, #8] 8002f5e: 4b59 ldr r3, [pc, #356] ; (80030c4 ) 8002f60: 7b1b ldrb r3, [r3, #12] 8002f62: 429a cmp r2, r3 8002f64: d905 bls.n 8002f72 { moto.moto1a_++; 8002f66: 4b57 ldr r3, [pc, #348] ; (80030c4 ) 8002f68: 7b1b ldrb r3, [r3, #12] 8002f6a: 3301 adds r3, #1 8002f6c: b2da uxtb r2, r3 8002f6e: 4b55 ldr r3, [pc, #340] ; (80030c4 ) 8002f70: 731a strb r2, [r3, #12] } if(moto.moto1a) 8002f74: 7a1a ldrb r2, [r3, #8] 8002f76: 4b53 ldr r3, [pc, #332] ; (80030c4 ) 8002f78: 7b1b ldrb r3, [r3, #12] 8002f7a: 429a cmp r2, r3 8002f7c: d205 bcs.n 8002f8a { moto.moto1a_--; 8002f7e: 4b51 ldr r3, [pc, #324] ; (80030c4 ) 8002f80: 7b1b ldrb r3, [r3, #12] 8002f82: 3b01 subs r3, #1 8002f84: b2da uxtb r2, r3 8002f86: 4b4f ldr r3, [pc, #316] ; (80030c4 ) 8002f88: 731a strb r2, [r3, #12] } } if(moto.moto1b!=moto.moto1b_) 8002f8a: 4b4e ldr r3, [pc, #312] ; (80030c4 ) 8002f8c: 7a5a ldrb r2, [r3, #9] 8002f8e: 4b4d ldr r3, [pc, #308] ; (80030c4 ) 8002f90: 7b5b ldrb r3, [r3, #13] 8002f92: 429a cmp r2, r3 8002f94: d017 beq.n 8002fc6 { if(moto.moto1b>moto.moto1b_) 8002f96: 4b4b ldr r3, [pc, #300] ; (80030c4 ) 8002f98: 7a5a ldrb r2, [r3, #9] 8002f9a: 4b4a ldr r3, [pc, #296] ; (80030c4 ) 8002f9c: 7b5b ldrb r3, [r3, #13] 8002f9e: 429a cmp r2, r3 8002fa0: d905 bls.n 8002fae { moto.moto1b_++; 8002fa2: 4b48 ldr r3, [pc, #288] ; (80030c4 ) 8002fa4: 7b5b ldrb r3, [r3, #13] 8002fa6: 3301 adds r3, #1 8002fa8: b2da uxtb r2, r3 8002faa: 4b46 ldr r3, [pc, #280] ; (80030c4 ) 8002fac: 735a strb r2, [r3, #13] } if(moto.moto1b) 8002fb0: 7a5a ldrb r2, [r3, #9] 8002fb2: 4b44 ldr r3, [pc, #272] ; (80030c4 ) 8002fb4: 7b5b ldrb r3, [r3, #13] 8002fb6: 429a cmp r2, r3 8002fb8: d205 bcs.n 8002fc6 { moto.moto1b_--; 8002fba: 4b42 ldr r3, [pc, #264] ; (80030c4 ) 8002fbc: 7b5b ldrb r3, [r3, #13] 8002fbe: 3b01 subs r3, #1 8002fc0: b2da uxtb r2, r3 8002fc2: 4b40 ldr r3, [pc, #256] ; (80030c4 ) 8002fc4: 735a strb r2, [r3, #13] } } if(moto.moto2a!=moto.moto2a_) 8002fc6: 4b3f ldr r3, [pc, #252] ; (80030c4 ) 8002fc8: 7a9a ldrb r2, [r3, #10] 8002fca: 4b3e ldr r3, [pc, #248] ; (80030c4 ) 8002fcc: 7b9b ldrb r3, [r3, #14] 8002fce: 429a cmp r2, r3 8002fd0: d017 beq.n 8003002 { if(moto.moto2a>moto.moto2a_) 8002fd2: 4b3c ldr r3, [pc, #240] ; (80030c4 ) 8002fd4: 7a9a ldrb r2, [r3, #10] 8002fd6: 4b3b ldr r3, [pc, #236] ; (80030c4 ) 8002fd8: 7b9b ldrb r3, [r3, #14] 8002fda: 429a cmp r2, r3 8002fdc: d905 bls.n 8002fea { moto.moto2a_++; 8002fde: 4b39 ldr r3, [pc, #228] ; (80030c4 ) 8002fe0: 7b9b ldrb r3, [r3, #14] 8002fe2: 3301 adds r3, #1 8002fe4: b2da uxtb r2, r3 8002fe6: 4b37 ldr r3, [pc, #220] ; (80030c4 ) 8002fe8: 739a strb r2, [r3, #14] } if(moto.moto2a) 8002fec: 7a9a ldrb r2, [r3, #10] 8002fee: 4b35 ldr r3, [pc, #212] ; (80030c4 ) 8002ff0: 7b9b ldrb r3, [r3, #14] 8002ff2: 429a cmp r2, r3 8002ff4: d205 bcs.n 8003002 { moto.moto2a_--; 8002ff6: 4b33 ldr r3, [pc, #204] ; (80030c4 ) 8002ff8: 7b9b ldrb r3, [r3, #14] 8002ffa: 3b01 subs r3, #1 8002ffc: b2da uxtb r2, r3 8002ffe: 4b31 ldr r3, [pc, #196] ; (80030c4 ) 8003000: 739a strb r2, [r3, #14] } } if(moto.moto2b!=moto.moto2b_) 8003002: 4b30 ldr r3, [pc, #192] ; (80030c4 ) 8003004: 7ada ldrb r2, [r3, #11] 8003006: 4b2f ldr r3, [pc, #188] ; (80030c4 ) 8003008: 7bdb ldrb r3, [r3, #15] 800300a: 429a cmp r2, r3 800300c: d017 beq.n 800303e { if(moto.moto2b>moto.moto2b_) 800300e: 4b2d ldr r3, [pc, #180] ; (80030c4 ) 8003010: 7ada ldrb r2, [r3, #11] 8003012: 4b2c ldr r3, [pc, #176] ; (80030c4 ) 8003014: 7bdb ldrb r3, [r3, #15] 8003016: 429a cmp r2, r3 8003018: d905 bls.n 8003026 { moto.moto2b_++; 800301a: 4b2a ldr r3, [pc, #168] ; (80030c4 ) 800301c: 7bdb ldrb r3, [r3, #15] 800301e: 3301 adds r3, #1 8003020: b2da uxtb r2, r3 8003022: 4b28 ldr r3, [pc, #160] ; (80030c4 ) 8003024: 73da strb r2, [r3, #15] } if(moto.moto2b) 8003028: 7ada ldrb r2, [r3, #11] 800302a: 4b26 ldr r3, [pc, #152] ; (80030c4 ) 800302c: 7bdb ldrb r3, [r3, #15] 800302e: 429a cmp r2, r3 8003030: d205 bcs.n 800303e { moto.moto2b_--; 8003032: 4b24 ldr r3, [pc, #144] ; (80030c4 ) 8003034: 7bdb ldrb r3, [r3, #15] 8003036: 3b01 subs r3, #1 8003038: b2da uxtb r2, r3 800303a: 4b22 ldr r3, [pc, #136] ; (80030c4 ) 800303c: 73da strb r2, [r3, #15] moto.pwm_run++; 800303e: 4b21 ldr r3, [pc, #132] ; (80030c4 ) 8003040: 685b ldr r3, [r3, #4] 8003042: 1c5a adds r2, r3, #1 8003044: 4b1f ldr r3, [pc, #124] ; (80030c4 ) 8003046: 605a str r2, [r3, #4] if(moto.pwm_run==10) 8003048: 4b1e ldr r3, [pc, #120] ; (80030c4 ) 800304a: 685b ldr r3, [r3, #4] 800304c: 2b0a cmp r3, #10 800304e: d102 bne.n 8003056 { moto.pwm_run=0; 8003050: 4b1c ldr r3, [pc, #112] ; (80030c4 ) 8003052: 2200 movs r2, #0 8003054: 605a str r2, [r3, #4] } if(moto.pwm_run) 8003058: 685b ldr r3, [r3, #4] 800305a: 4a1a ldr r2, [pc, #104] ; (80030c4 ) 800305c: 7b12 ldrb r2, [r2, #12] 800305e: 4293 cmp r3, r2 8003060: da03 bge.n 800306a { dis_buff.moto1a=1; 8003062: 4b19 ldr r3, [pc, #100] ; (80030c8 ) 8003064: 2201 movs r2, #1 8003066: 735a strb r2, [r3, #13] 8003068: e002 b.n 8003070 }else { dis_buff.moto1a=0; 800306a: 4b17 ldr r3, [pc, #92] ; (80030c8 ) 800306c: 2200 movs r2, #0 800306e: 735a strb r2, [r3, #13] } if(moto.pwm_run) 8003072: 685b ldr r3, [r3, #4] 8003074: 4a13 ldr r2, [pc, #76] ; (80030c4 ) 8003076: 7b52 ldrb r2, [r2, #13] 8003078: 4293 cmp r3, r2 800307a: da03 bge.n 8003084 { dis_buff.moto1b=1; 800307c: 4b12 ldr r3, [pc, #72] ; (80030c8 ) 800307e: 2201 movs r2, #1 8003080: 739a strb r2, [r3, #14] 8003082: e002 b.n 800308a }else { dis_buff.moto1b=0; 8003084: 4b10 ldr r3, [pc, #64] ; (80030c8 ) 8003086: 2200 movs r2, #0 8003088: 739a strb r2, [r3, #14] } if(moto.pwm_run) 800308c: 685b ldr r3, [r3, #4] 800308e: 4a0d ldr r2, [pc, #52] ; (80030c4 ) 8003090: 7b92 ldrb r2, [r2, #14] 8003092: 4293 cmp r3, r2 8003094: da03 bge.n 800309e { dis_buff.moto2a=1; 8003096: 4b0c ldr r3, [pc, #48] ; (80030c8 ) 8003098: 2201 movs r2, #1 800309a: 73da strb r2, [r3, #15] 800309c: e002 b.n 80030a4 }else { dis_buff.moto2a=0; 800309e: 4b0a ldr r3, [pc, #40] ; (80030c8 ) 80030a0: 2200 movs r2, #0 80030a2: 73da strb r2, [r3, #15] } if(moto.pwm_run) 80030a6: 685b ldr r3, [r3, #4] 80030a8: 4a06 ldr r2, [pc, #24] ; (80030c4 ) 80030aa: 7bd2 ldrb r2, [r2, #15] 80030ac: 4293 cmp r3, r2 80030ae: da03 bge.n 80030b8 { dis_buff.moto2b=1; 80030b0: 4b05 ldr r3, [pc, #20] ; (80030c8 ) 80030b2: 2201 movs r2, #1 80030b4: 741a strb r2, [r3, #16] }else { dis_buff.moto2b=0; } } 80030b6: e002 b.n 80030be dis_buff.moto2b=0; 80030b8: 4b03 ldr r3, [pc, #12] ; (80030c8 ) 80030ba: 2200 movs r2, #0 80030bc: 741a strb r2, [r3, #16] } 80030be: 46c0 nop ; (mov r8, r8) 80030c0: 46bd mov sp, r7 80030c2: bd80 pop {r7, pc} 80030c4: 200001c0 .word 0x200001c0 80030c8: 200000a0 .word 0x200000a0 080030cc : #define E 0x08 #define F 0x04 #define G 0x02 #define H 0x01 void HT1621_Display_GetButton(void) { 80030cc: b580 push {r7, lr} 80030ce: b084 sub sp, #16 80030d0: af00 add r7, sp, #0 unsigned char send_buff[8]; unsigned char lcd_buff[4]; //WritenDataHT1621(0,send_buff,8); lcd_buff[0]=LED_Tab[dis_buff.d_num[0]]; 80030d2: 4b45 ldr r3, [pc, #276] ; (80031e8 ) 80030d4: 781b ldrb r3, [r3, #0] 80030d6: 001a movs r2, r3 80030d8: 4b44 ldr r3, [pc, #272] ; (80031ec ) 80030da: 5c9a ldrb r2, [r3, r2] 80030dc: 1d3b adds r3, r7, #4 80030de: 701a strb r2, [r3, #0] if(dis_buff.dot1==1) 80030e0: 4b41 ldr r3, [pc, #260] ; (80031e8 ) 80030e2: 7a1b ldrb r3, [r3, #8] 80030e4: 2b01 cmp r3, #1 80030e6: d107 bne.n 80030f8 { lcd_buff[0]|=0x80; 80030e8: 1d3b adds r3, r7, #4 80030ea: 781b ldrb r3, [r3, #0] 80030ec: 2280 movs r2, #128 ; 0x80 80030ee: 4252 negs r2, r2 80030f0: 4313 orrs r3, r2 80030f2: b2da uxtb r2, r3 80030f4: 1d3b adds r3, r7, #4 80030f6: 701a strb r2, [r3, #0] } lcd_buff[1]=LED_Tab[dis_buff.d_num[1]]; 80030f8: 4b3b ldr r3, [pc, #236] ; (80031e8 ) 80030fa: 785b ldrb r3, [r3, #1] 80030fc: 001a movs r2, r3 80030fe: 4b3b ldr r3, [pc, #236] ; (80031ec ) 8003100: 5c9a ldrb r2, [r3, r2] 8003102: 1d3b adds r3, r7, #4 8003104: 705a strb r2, [r3, #1] if(dis_buff.dot2==1) 8003106: 4b38 ldr r3, [pc, #224] ; (80031e8 ) 8003108: 7a5b ldrb r3, [r3, #9] 800310a: 2b01 cmp r3, #1 800310c: d107 bne.n 800311e { lcd_buff[1]|=0x80; 800310e: 1d3b adds r3, r7, #4 8003110: 785b ldrb r3, [r3, #1] 8003112: 2280 movs r2, #128 ; 0x80 8003114: 4252 negs r2, r2 8003116: 4313 orrs r3, r2 8003118: b2da uxtb r2, r3 800311a: 1d3b adds r3, r7, #4 800311c: 705a strb r2, [r3, #1] } lcd_buff[2]=LED_Tab[dis_buff.d_num[2]]; 800311e: 4b32 ldr r3, [pc, #200] ; (80031e8 ) 8003120: 789b ldrb r3, [r3, #2] 8003122: 001a movs r2, r3 8003124: 4b31 ldr r3, [pc, #196] ; (80031ec ) 8003126: 5c9a ldrb r2, [r3, r2] 8003128: 1d3b adds r3, r7, #4 800312a: 709a strb r2, [r3, #2] if(dis_buff.dot3==1) 800312c: 4b2e ldr r3, [pc, #184] ; (80031e8 ) 800312e: 7a9b ldrb r3, [r3, #10] 8003130: 2b01 cmp r3, #1 8003132: d107 bne.n 8003144 { lcd_buff[2]|=0x80; 8003134: 1d3b adds r3, r7, #4 8003136: 789b ldrb r3, [r3, #2] 8003138: 2280 movs r2, #128 ; 0x80 800313a: 4252 negs r2, r2 800313c: 4313 orrs r3, r2 800313e: b2da uxtb r2, r3 8003140: 1d3b adds r3, r7, #4 8003142: 709a strb r2, [r3, #2] } lcd_buff[3]=LED_Tab[dis_buff.d_num[3]]; 8003144: 4b28 ldr r3, [pc, #160] ; (80031e8 ) 8003146: 78db ldrb r3, [r3, #3] 8003148: 001a movs r2, r3 800314a: 4b28 ldr r3, [pc, #160] ; (80031ec ) 800314c: 5c9a ldrb r2, [r3, r2] 800314e: 1d3b adds r3, r7, #4 8003150: 70da strb r2, [r3, #3] if(dis_buff.dot4==1) 8003152: 4b25 ldr r3, [pc, #148] ; (80031e8 ) 8003154: 7adb ldrb r3, [r3, #11] 8003156: 2b01 cmp r3, #1 8003158: d107 bne.n 800316a { lcd_buff[3]|=0x80; 800315a: 1d3b adds r3, r7, #4 800315c: 78db ldrb r3, [r3, #3] 800315e: 2280 movs r2, #128 ; 0x80 8003160: 4252 negs r2, r2 8003162: 4313 orrs r3, r2 8003164: b2da uxtb r2, r3 8003166: 1d3b adds r3, r7, #4 8003168: 70da strb r2, [r3, #3] } send_buff[0]=lcd_buff[0]>>4; 800316a: 1d3b adds r3, r7, #4 800316c: 781b ldrb r3, [r3, #0] 800316e: 091b lsrs r3, r3, #4 8003170: b2da uxtb r2, r3 8003172: 2108 movs r1, #8 8003174: 187b adds r3, r7, r1 8003176: 701a strb r2, [r3, #0] send_buff[1]=lcd_buff[0]&0x0f; 8003178: 1d3b adds r3, r7, #4 800317a: 781b ldrb r3, [r3, #0] 800317c: 220f movs r2, #15 800317e: 4013 ands r3, r2 8003180: b2da uxtb r2, r3 8003182: 187b adds r3, r7, r1 8003184: 705a strb r2, [r3, #1] send_buff[2]=lcd_buff[1]>>4; 8003186: 1d3b adds r3, r7, #4 8003188: 785b ldrb r3, [r3, #1] 800318a: 091b lsrs r3, r3, #4 800318c: b2da uxtb r2, r3 800318e: 187b adds r3, r7, r1 8003190: 709a strb r2, [r3, #2] send_buff[3]=lcd_buff[1]&0x0f; 8003192: 1d3b adds r3, r7, #4 8003194: 785b ldrb r3, [r3, #1] 8003196: 220f movs r2, #15 8003198: 4013 ands r3, r2 800319a: b2da uxtb r2, r3 800319c: 187b adds r3, r7, r1 800319e: 70da strb r2, [r3, #3] send_buff[4]=lcd_buff[2]>>4; 80031a0: 1d3b adds r3, r7, #4 80031a2: 789b ldrb r3, [r3, #2] 80031a4: 091b lsrs r3, r3, #4 80031a6: b2da uxtb r2, r3 80031a8: 187b adds r3, r7, r1 80031aa: 711a strb r2, [r3, #4] send_buff[5]=lcd_buff[2]&0x0f; 80031ac: 1d3b adds r3, r7, #4 80031ae: 789b ldrb r3, [r3, #2] 80031b0: 220f movs r2, #15 80031b2: 4013 ands r3, r2 80031b4: b2da uxtb r2, r3 80031b6: 187b adds r3, r7, r1 80031b8: 715a strb r2, [r3, #5] send_buff[6]=lcd_buff[3]>>4; 80031ba: 1d3b adds r3, r7, #4 80031bc: 78db ldrb r3, [r3, #3] 80031be: 091b lsrs r3, r3, #4 80031c0: b2da uxtb r2, r3 80031c2: 187b adds r3, r7, r1 80031c4: 719a strb r2, [r3, #6] send_buff[7]=lcd_buff[3]&0x0f; 80031c6: 1d3b adds r3, r7, #4 80031c8: 78db ldrb r3, [r3, #3] 80031ca: 220f movs r2, #15 80031cc: 4013 ands r3, r2 80031ce: b2da uxtb r2, r3 80031d0: 187b adds r3, r7, r1 80031d2: 71da strb r2, [r3, #7] WritenDataHT1621(0,send_buff,8); 80031d4: 187b adds r3, r7, r1 80031d6: 2208 movs r2, #8 80031d8: 0019 movs r1, r3 80031da: 2000 movs r0, #0 80031dc: f7ff fb8e bl 80028fc } 80031e0: 46c0 nop ; (mov r8, r8) 80031e2: 46bd mov sp, r7 80031e4: b004 add sp, #16 80031e6: bd80 pop {r7, pc} 80031e8: 200000a0 .word 0x200000a0 80031ec: 08003d6c .word 0x08003d6c 080031f0 : void my_code() { 80031f0: b590 push {r4, r7, lr} 80031f2: b087 sub sp, #28 80031f4: af00 add r7, sp, #0 uint32_t runtime=0,move=0; 80031f6: 2300 movs r3, #0 80031f8: 617b str r3, [r7, #20] 80031fa: 2300 movs r3, #0 80031fc: 613b str r3, [r7, #16] uint8_t mode=0,overload_mode=0; 80031fe: 240f movs r4, #15 8003200: 193b adds r3, r7, r4 8003202: 2200 movs r2, #0 8003204: 701a strb r2, [r3, #0] 8003206: 230e movs r3, #14 8003208: 18fb adds r3, r7, r3 800320a: 2200 movs r2, #0 800320c: 701a strb r2, [r3, #0] uint16_t overload_times=0; 800320e: 230c movs r3, #12 8003210: 18fb adds r3, r7, r3 8003212: 2200 movs r2, #0 8003214: 801a strh r2, [r3, #0] long countdown=1000; 8003216: 23fa movs r3, #250 ; 0xfa 8003218: 009b lsls r3, r3, #2 800321a: 60bb str r3, [r7, #8] long countdown_set=15000; 800321c: 4be6 ldr r3, [pc, #920] ; (80035b8 ) 800321e: 607b str r3, [r7, #4] HT1621_Init(); 8003220: f7ff fc2d bl 8002a7e r480_init(); 8003224: f000 fc1a bl 8003a5c EPPROM_SLOWWRITE_INIT(); 8003228: f7ff fa32 bl 8002690 EEPROM_READ_BATY(16,(char *)&config,sizeof(config_setting)); 800322c: 4be3 ldr r3, [pc, #908] ; (80035bc ) 800322e: 220c movs r2, #12 8003230: 0019 movs r1, r3 8003232: 2010 movs r0, #16 8003234: f7ff fa8c bl 8002750 if(config.begin!=0xab) 8003238: 4be0 ldr r3, [pc, #896] ; (80035bc ) 800323a: 781b ldrb r3, [r3, #0] 800323c: 2bab cmp r3, #171 ; 0xab 800323e: d002 beq.n 8003246 { mode=6; 8003240: 193b adds r3, r7, r4 8003242: 2206 movs r2, #6 8003244: 701a strb r2, [r3, #0] } while(1) { //get ADC for(char a=0;a<2;a++) 8003246: 1cfb adds r3, r7, #3 8003248: 2200 movs r2, #0 800324a: 701a strb r2, [r3, #0] 800324c: e025 b.n 800329a { HAL_ADC_Start(&hadc); 800324e: 4bdc ldr r3, [pc, #880] ; (80035c0 ) 8003250: 0018 movs r0, r3 8003252: f7fd fd17 bl 8000c84 while(HAL_ADC_PollForConversion(&hadc,0xffff)!=HAL_OK); 8003256: 46c0 nop ; (mov r8, r8) 8003258: 4ada ldr r2, [pc, #872] ; (80035c4 ) 800325a: 4bd9 ldr r3, [pc, #868] ; (80035c0 ) 800325c: 0011 movs r1, r2 800325e: 0018 movs r0, r3 8003260: f7fd fda4 bl 8000dac 8003264: 1e03 subs r3, r0, #0 8003266: d1f7 bne.n 8003258 ADCC.adc_filtering[a]+=HAL_ADC_GetValue(&hadc); 8003268: 4bd5 ldr r3, [pc, #852] ; (80035c0 ) 800326a: 0018 movs r0, r3 800326c: f7fd fe36 bl 8000edc 8003270: 0001 movs r1, r0 8003272: 1cfb adds r3, r7, #3 8003274: 781b ldrb r3, [r3, #0] 8003276: 4ad4 ldr r2, [pc, #848] ; (80035c8 ) 8003278: 009b lsls r3, r3, #2 800327a: 18d3 adds r3, r2, r3 800327c: 3304 adds r3, #4 800327e: 681a ldr r2, [r3, #0] 8003280: 1cfb adds r3, r7, #3 8003282: 781b ldrb r3, [r3, #0] 8003284: 188a adds r2, r1, r2 8003286: 49d0 ldr r1, [pc, #832] ; (80035c8 ) 8003288: 009b lsls r3, r3, #2 800328a: 18cb adds r3, r1, r3 800328c: 3304 adds r3, #4 800328e: 601a str r2, [r3, #0] for(char a=0;a<2;a++) 8003290: 1cfb adds r3, r7, #3 8003292: 781a ldrb r2, [r3, #0] 8003294: 1cfb adds r3, r7, #3 8003296: 3201 adds r2, #1 8003298: 701a strb r2, [r3, #0] 800329a: 1cfb adds r3, r7, #3 800329c: 781b ldrb r3, [r3, #0] 800329e: 2b01 cmp r3, #1 80032a0: d9d5 bls.n 800324e } HAL_ADC_Stop(&hadc); 80032a2: 4bc7 ldr r3, [pc, #796] ; (80035c0 ) 80032a4: 0018 movs r0, r3 80032a6: f7fd fd41 bl 8000d2c ADCC.filtering_times+=1; 80032aa: 4bc7 ldr r3, [pc, #796] ; (80035c8 ) 80032ac: 681b ldr r3, [r3, #0] 80032ae: 1c5a adds r2, r3, #1 80032b0: 4bc5 ldr r3, [pc, #788] ; (80035c8 ) 80032b2: 601a str r2, [r3, #0] if(ADCC.filtering_times==set_filtering_times) 80032b4: 4bc4 ldr r3, [pc, #784] ; (80035c8 ) 80032b6: 681b ldr r3, [r3, #0] 80032b8: 2b32 cmp r3, #50 ; 0x32 80032ba: d11c bne.n 80032f6 { ADCC.filtering_times=0; 80032bc: 4bc2 ldr r3, [pc, #776] ; (80035c8 ) 80032be: 2200 movs r2, #0 80032c0: 601a str r2, [r3, #0] ADCC.adc_value[0]=ADCC.adc_filtering[0]/set_filtering_times; 80032c2: 4bc1 ldr r3, [pc, #772] ; (80035c8 ) 80032c4: 685b ldr r3, [r3, #4] 80032c6: 2132 movs r1, #50 ; 0x32 80032c8: 0018 movs r0, r3 80032ca: f7fc ff1d bl 8000108 <__udivsi3> 80032ce: 0003 movs r3, r0 80032d0: 001a movs r2, r3 80032d2: 4bbd ldr r3, [pc, #756] ; (80035c8 ) 80032d4: 60da str r2, [r3, #12] ADCC.adc_filtering[0]=0; 80032d6: 4bbc ldr r3, [pc, #752] ; (80035c8 ) 80032d8: 2200 movs r2, #0 80032da: 605a str r2, [r3, #4] ADCC.adc_value[1]=ADCC.adc_filtering[1]/set_filtering_times; 80032dc: 4bba ldr r3, [pc, #744] ; (80035c8 ) 80032de: 689b ldr r3, [r3, #8] 80032e0: 2132 movs r1, #50 ; 0x32 80032e2: 0018 movs r0, r3 80032e4: f7fc ff10 bl 8000108 <__udivsi3> 80032e8: 0003 movs r3, r0 80032ea: 001a movs r2, r3 80032ec: 4bb6 ldr r3, [pc, #728] ; (80035c8 ) 80032ee: 611a str r2, [r3, #16] ADCC.adc_filtering[1]=0; 80032f0: 4bb5 ldr r3, [pc, #724] ; (80035c8 ) 80032f2: 2200 movs r2, #0 80032f4: 609a str r2, [r3, #8] } switch(mode) 80032f6: 230f movs r3, #15 80032f8: 18fb adds r3, r7, r3 80032fa: 781b ldrb r3, [r3, #0] 80032fc: 2b06 cmp r3, #6 80032fe: d900 bls.n 8003302 8003300: e333 b.n 800396a 8003302: 009a lsls r2, r3, #2 8003304: 4bb1 ldr r3, [pc, #708] ; (80035cc ) 8003306: 18d3 adds r3, r2, r3 8003308: 681b ldr r3, [r3, #0] 800330a: 469f mov pc, r3 { case 0: //Startup if(HAL_GetTick()>move) 800330c: f7fd fb70 bl 80009f0 8003310: 0002 movs r2, r0 8003312: 693b ldr r3, [r7, #16] 8003314: 4293 cmp r3, r2 8003316: d300 bcc.n 800331a 8003318: e30a b.n 8003930 { move=HAL_GetTick()+100; 800331a: f7fd fb69 bl 80009f0 800331e: 0003 movs r3, r0 8003320: 3364 adds r3, #100 ; 0x64 8003322: 613b str r3, [r7, #16] countdown-=100; 8003324: 68bb ldr r3, [r7, #8] 8003326: 3b64 subs r3, #100 ; 0x64 8003328: 60bb str r3, [r7, #8] if(countdown<0) 800332a: 68bb ldr r3, [r7, #8] 800332c: 2b00 cmp r3, #0 800332e: da03 bge.n 8003338 { mode=1; 8003330: 230f movs r3, #15 8003332: 18fb adds r3, r7, r3 8003334: 2201 movs r2, #1 8003336: 701a strb r2, [r3, #0] } dis_buff.d_num[0]=((countdown/100)%10); 8003338: 68bb ldr r3, [r7, #8] 800333a: 2164 movs r1, #100 ; 0x64 800333c: 0018 movs r0, r3 800333e: f7fc ff6d bl 800021c <__divsi3> 8003342: 0003 movs r3, r0 8003344: 210a movs r1, #10 8003346: 0018 movs r0, r3 8003348: f7fd f84e bl 80003e8 <__aeabi_idivmod> 800334c: 000b movs r3, r1 800334e: b2da uxtb r2, r3 8003350: 4b9f ldr r3, [pc, #636] ; (80035d0 ) 8003352: 701a strb r2, [r3, #0] dis_buff.d_num[1]=((countdown/100)%10); 8003354: 68bb ldr r3, [r7, #8] 8003356: 2164 movs r1, #100 ; 0x64 8003358: 0018 movs r0, r3 800335a: f7fc ff5f bl 800021c <__divsi3> 800335e: 0003 movs r3, r0 8003360: 210a movs r1, #10 8003362: 0018 movs r0, r3 8003364: f7fd f840 bl 80003e8 <__aeabi_idivmod> 8003368: 000b movs r3, r1 800336a: b2da uxtb r2, r3 800336c: 4b98 ldr r3, [pc, #608] ; (80035d0 ) 800336e: 705a strb r2, [r3, #1] dis_buff.d_num[2]=((countdown/100)%10); 8003370: 68bb ldr r3, [r7, #8] 8003372: 2164 movs r1, #100 ; 0x64 8003374: 0018 movs r0, r3 8003376: f7fc ff51 bl 800021c <__divsi3> 800337a: 0003 movs r3, r0 800337c: 210a movs r1, #10 800337e: 0018 movs r0, r3 8003380: f7fd f832 bl 80003e8 <__aeabi_idivmod> 8003384: 000b movs r3, r1 8003386: b2da uxtb r2, r3 8003388: 4b91 ldr r3, [pc, #580] ; (80035d0 ) 800338a: 709a strb r2, [r3, #2] dis_buff.d_num[3]=((countdown/100)%10); 800338c: 68bb ldr r3, [r7, #8] 800338e: 2164 movs r1, #100 ; 0x64 8003390: 0018 movs r0, r3 8003392: f7fc ff43 bl 800021c <__divsi3> 8003396: 0003 movs r3, r0 8003398: 210a movs r1, #10 800339a: 0018 movs r0, r3 800339c: f7fd f824 bl 80003e8 <__aeabi_idivmod> 80033a0: 000b movs r3, r1 80033a2: b2da uxtb r2, r3 80033a4: 4b8a ldr r3, [pc, #552] ; (80035d0 ) 80033a6: 70da strb r2, [r3, #3] dis_buff.dot1=countdown>>3; 80033a8: 68bb ldr r3, [r7, #8] 80033aa: 10db asrs r3, r3, #3 80033ac: b2da uxtb r2, r3 80033ae: 4b88 ldr r3, [pc, #544] ; (80035d0 ) 80033b0: 721a strb r2, [r3, #8] dis_buff.dot2=countdown>>4; 80033b2: 68bb ldr r3, [r7, #8] 80033b4: 111b asrs r3, r3, #4 80033b6: b2da uxtb r2, r3 80033b8: 4b85 ldr r3, [pc, #532] ; (80035d0 ) 80033ba: 725a strb r2, [r3, #9] dis_buff.dot3=countdown>>5; 80033bc: 68bb ldr r3, [r7, #8] 80033be: 115b asrs r3, r3, #5 80033c0: b2da uxtb r2, r3 80033c2: 4b83 ldr r3, [pc, #524] ; (80035d0 ) 80033c4: 729a strb r2, [r3, #10] dis_buff.dot4=countdown>>6; 80033c6: 68bb ldr r3, [r7, #8] 80033c8: 119b asrs r3, r3, #6 80033ca: b2da uxtb r2, r3 80033cc: 4b80 ldr r3, [pc, #512] ; (80035d0 ) 80033ce: 72da strb r2, [r3, #11] } break; 80033d0: e2ae b.n 8003930 case 1: //standby moto.moto1a=0; 80033d2: 4b80 ldr r3, [pc, #512] ; (80035d4 ) 80033d4: 2200 movs r2, #0 80033d6: 721a strb r2, [r3, #8] moto.moto1b=0; 80033d8: 4b7e ldr r3, [pc, #504] ; (80035d4 ) 80033da: 2200 movs r2, #0 80033dc: 725a strb r2, [r3, #9] moto.moto2a=0; 80033de: 4b7d ldr r3, [pc, #500] ; (80035d4 ) 80033e0: 2200 movs r2, #0 80033e2: 729a strb r2, [r3, #10] moto.moto2b=0; 80033e4: 4b7b ldr r3, [pc, #492] ; (80035d4 ) 80033e6: 2200 movs r2, #0 80033e8: 72da strb r2, [r3, #11] dis_buff.d_num[0]=16; 80033ea: 4b79 ldr r3, [pc, #484] ; (80035d0 ) 80033ec: 2210 movs r2, #16 80033ee: 701a strb r2, [r3, #0] dis_buff.d_num[1]=16; 80033f0: 4b77 ldr r3, [pc, #476] ; (80035d0 ) 80033f2: 2210 movs r2, #16 80033f4: 705a strb r2, [r3, #1] dis_buff.d_num[2]=16; 80033f6: 4b76 ldr r3, [pc, #472] ; (80035d0 ) 80033f8: 2210 movs r2, #16 80033fa: 709a strb r2, [r3, #2] dis_buff.d_num[3]=16; 80033fc: 4b74 ldr r3, [pc, #464] ; (80035d0 ) 80033fe: 2210 movs r2, #16 8003400: 70da strb r2, [r3, #3] dis_buff.dot1=0; 8003402: 4b73 ldr r3, [pc, #460] ; (80035d0 ) 8003404: 2200 movs r2, #0 8003406: 721a strb r2, [r3, #8] dis_buff.dot2=0; 8003408: 4b71 ldr r3, [pc, #452] ; (80035d0 ) 800340a: 2200 movs r2, #0 800340c: 725a strb r2, [r3, #9] dis_buff.dot3=0; 800340e: 4b70 ldr r3, [pc, #448] ; (80035d0 ) 8003410: 2200 movs r2, #0 8003412: 729a strb r2, [r3, #10] if(HAL_GetTick()>runtime) 8003414: f7fd faec bl 80009f0 8003418: 0002 movs r2, r0 800341a: 697b ldr r3, [r7, #20] 800341c: 4293 cmp r3, r2 800341e: d216 bcs.n 800344e { runtime+=1000; 8003420: 697b ldr r3, [r7, #20] 8003422: 22fa movs r2, #250 ; 0xfa 8003424: 0092 lsls r2, r2, #2 8003426: 4694 mov ip, r2 8003428: 4463 add r3, ip 800342a: 617b str r3, [r7, #20] if(dis_buff.led_run==1) 800342c: 4b68 ldr r3, [pc, #416] ; (80035d0 ) 800342e: 7b1b ldrb r3, [r3, #12] 8003430: 2b01 cmp r3, #1 8003432: d106 bne.n 8003442 { dis_buff.led_run=0; 8003434: 4b66 ldr r3, [pc, #408] ; (80035d0 ) 8003436: 2200 movs r2, #0 8003438: 731a strb r2, [r3, #12] dis_buff.dot4=1; 800343a: 4b65 ldr r3, [pc, #404] ; (80035d0 ) 800343c: 2201 movs r2, #1 800343e: 72da strb r2, [r3, #11] 8003440: e005 b.n 800344e }else { dis_buff.led_run=1; 8003442: 4b63 ldr r3, [pc, #396] ; (80035d0 ) 8003444: 2201 movs r2, #1 8003446: 731a strb r2, [r3, #12] dis_buff.dot4=0; 8003448: 4b61 ldr r3, [pc, #388] ; (80035d0 ) 800344a: 2200 movs r2, #0 800344c: 72da strb r2, [r3, #11] } } overload_times=0; 800344e: 230c movs r3, #12 8003450: 18fb adds r3, r7, r3 8003452: 2200 movs r2, #0 8003454: 801a strh r2, [r3, #0] if(key2.code!=0) 8003456: 4b60 ldr r3, [pc, #384] ; (80035d8 ) 8003458: 681b ldr r3, [r3, #0] 800345a: 2b00 cmp r3, #0 800345c: d005 beq.n 800346a { mode=2; 800345e: 230f movs r3, #15 8003460: 18fb adds r3, r7, r3 8003462: 2202 movs r2, #2 8003464: 701a strb r2, [r3, #0] countdown=countdown_set; 8003466: 687b ldr r3, [r7, #4] 8003468: 60bb str r3, [r7, #8] } if(key3.code!=0) 800346a: 4b5c ldr r3, [pc, #368] ; (80035dc ) 800346c: 681b ldr r3, [r3, #0] 800346e: 2b00 cmp r3, #0 8003470: d005 beq.n 800347e { mode=3; 8003472: 230f movs r3, #15 8003474: 18fb adds r3, r7, r3 8003476: 2203 movs r2, #3 8003478: 701a strb r2, [r3, #0] countdown=countdown_set; 800347a: 687b ldr r3, [r7, #4] 800347c: 60bb str r3, [r7, #8] } if(key1.code!=0) 800347e: 4b58 ldr r3, [pc, #352] ; (80035e0 ) 8003480: 681b ldr r3, [r3, #0] 8003482: 2b00 cmp r3, #0 8003484: d100 bne.n 8003488 8003486: e255 b.n 8003934 { mode=4; 8003488: 230f movs r3, #15 800348a: 18fb adds r3, r7, r3 800348c: 2204 movs r2, #4 800348e: 701a strb r2, [r3, #0] countdown=10000; 8003490: 4b54 ldr r3, [pc, #336] ; (80035e4 ) 8003492: 60bb str r3, [r7, #8] } break; 8003494: e24e b.n 8003934 case 2: moto.moto1a=10; 8003496: 4b4f ldr r3, [pc, #316] ; (80035d4 ) 8003498: 220a movs r2, #10 800349a: 721a strb r2, [r3, #8] moto.moto1b=0; 800349c: 4b4d ldr r3, [pc, #308] ; (80035d4 ) 800349e: 2200 movs r2, #0 80034a0: 725a strb r2, [r3, #9] moto.moto2a=10; 80034a2: 4b4c ldr r3, [pc, #304] ; (80035d4 ) 80034a4: 220a movs r2, #10 80034a6: 729a strb r2, [r3, #10] moto.moto2b=0; 80034a8: 4b4a ldr r3, [pc, #296] ; (80035d4 ) 80034aa: 2200 movs r2, #0 80034ac: 72da strb r2, [r3, #11] if(HAL_GetTick()>move) 80034ae: f7fd fa9f bl 80009f0 80034b2: 0002 movs r2, r0 80034b4: 693b ldr r3, [r7, #16] 80034b6: 4293 cmp r3, r2 80034b8: d219 bcs.n 80034ee { move=HAL_GetTick()+100; 80034ba: f7fd fa99 bl 80009f0 80034be: 0003 movs r3, r0 80034c0: 3364 adds r3, #100 ; 0x64 80034c2: 613b str r3, [r7, #16] if(dis_buff.led_run==1) 80034c4: 4b42 ldr r3, [pc, #264] ; (80035d0 ) 80034c6: 7b1b ldrb r3, [r3, #12] 80034c8: 2b01 cmp r3, #1 80034ca: d103 bne.n 80034d4 { dis_buff.led_run=0; 80034cc: 4b40 ldr r3, [pc, #256] ; (80035d0 ) 80034ce: 2200 movs r2, #0 80034d0: 731a strb r2, [r3, #12] 80034d2: e002 b.n 80034da }else { dis_buff.led_run=1; 80034d4: 4b3e ldr r3, [pc, #248] ; (80035d0 ) 80034d6: 2201 movs r2, #1 80034d8: 731a strb r2, [r3, #12] } countdown-=100; 80034da: 68bb ldr r3, [r7, #8] 80034dc: 3b64 subs r3, #100 ; 0x64 80034de: 60bb str r3, [r7, #8] if(countdown<0) 80034e0: 68bb ldr r3, [r7, #8] 80034e2: 2b00 cmp r3, #0 80034e4: da03 bge.n 80034ee { mode=1; 80034e6: 230f movs r3, #15 80034e8: 18fb adds r3, r7, r3 80034ea: 2201 movs r2, #1 80034ec: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 80034ee: 68bb ldr r3, [r7, #8] 80034f0: 2164 movs r1, #100 ; 0x64 80034f2: 0018 movs r0, r3 80034f4: f7fc fe92 bl 800021c <__divsi3> 80034f8: 0003 movs r3, r0 80034fa: 210a movs r1, #10 80034fc: 0018 movs r0, r3 80034fe: f7fc ff73 bl 80003e8 <__aeabi_idivmod> 8003502: 000b movs r3, r1 8003504: b2da uxtb r2, r3 8003506: 4b32 ldr r3, [pc, #200] ; (80035d0 ) 8003508: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 800350a: 68bb ldr r3, [r7, #8] 800350c: 22fa movs r2, #250 ; 0xfa 800350e: 0091 lsls r1, r2, #2 8003510: 0018 movs r0, r3 8003512: f7fc fe83 bl 800021c <__divsi3> 8003516: 0003 movs r3, r0 8003518: 210a movs r1, #10 800351a: 0018 movs r0, r3 800351c: f7fc ff64 bl 80003e8 <__aeabi_idivmod> 8003520: 000b movs r3, r1 8003522: b2da uxtb r2, r3 8003524: 4b2a ldr r3, [pc, #168] ; (80035d0 ) 8003526: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 8003528: 68bb ldr r3, [r7, #8] 800352a: 492e ldr r1, [pc, #184] ; (80035e4 ) 800352c: 0018 movs r0, r3 800352e: f7fc fe75 bl 800021c <__divsi3> 8003532: 0003 movs r3, r0 8003534: 210a movs r1, #10 8003536: 0018 movs r0, r3 8003538: f7fc ff56 bl 80003e8 <__aeabi_idivmod> 800353c: 000b movs r3, r1 800353e: b2da uxtb r2, r3 8003540: 4b23 ldr r3, [pc, #140] ; (80035d0 ) 8003542: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 8003544: 4b22 ldr r3, [pc, #136] ; (80035d0 ) 8003546: 785b ldrb r3, [r3, #1] 8003548: 2b00 cmp r3, #0 800354a: d002 beq.n 8003552 800354c: 4b20 ldr r3, [pc, #128] ; (80035d0 ) 800354e: 785a ldrb r2, [r3, #1] 8003550: e000 b.n 8003554 8003552: 2210 movs r2, #16 8003554: 4b1e ldr r3, [pc, #120] ; (80035d0 ) 8003556: 705a strb r2, [r3, #1] dis_buff.dot4=1; 8003558: 4b1d ldr r3, [pc, #116] ; (80035d0 ) 800355a: 2201 movs r2, #1 800355c: 72da strb r2, [r3, #11] if(key3.code!=0) 800355e: 4b1f ldr r3, [pc, #124] ; (80035dc ) 8003560: 681b ldr r3, [r3, #0] 8003562: 2b00 cmp r3, #0 8003564: d007 beq.n 8003576 { mode=3; 8003566: 230f movs r3, #15 8003568: 18fb adds r3, r7, r3 800356a: 2203 movs r2, #3 800356c: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 800356e: 687a ldr r2, [r7, #4] 8003570: 68bb ldr r3, [r7, #8] 8003572: 1ad3 subs r3, r2, r3 8003574: 60bb str r3, [r7, #8] } if(key4.code!=0) 8003576: 4b1c ldr r3, [pc, #112] ; (80035e8 ) 8003578: 681b ldr r3, [r3, #0] 800357a: 2b00 cmp r3, #0 800357c: d003 beq.n 8003586 { mode=1; 800357e: 230f movs r3, #15 8003580: 18fb adds r3, r7, r3 8003582: 2201 movs r2, #1 8003584: 701a strb r2, [r3, #0] } if(overload.code!=0) 8003586: 4b19 ldr r3, [pc, #100] ; (80035ec ) 8003588: 681b ldr r3, [r3, #0] 800358a: 2b00 cmp r3, #0 800358c: d005 beq.n 800359a { overload_times+=1; 800358e: 220c movs r2, #12 8003590: 18bb adds r3, r7, r2 8003592: 18ba adds r2, r7, r2 8003594: 8812 ldrh r2, [r2, #0] 8003596: 3201 adds r2, #1 8003598: 801a strh r2, [r3, #0] } if(overload_times>2) 800359a: 230c movs r3, #12 800359c: 18fb adds r3, r7, r3 800359e: 881b ldrh r3, [r3, #0] 80035a0: 2b02 cmp r3, #2 80035a2: d800 bhi.n 80035a6 80035a4: e1c8 b.n 8003938 { overload_mode=2; 80035a6: 230e movs r3, #14 80035a8: 18fb adds r3, r7, r3 80035aa: 2202 movs r2, #2 80035ac: 701a strb r2, [r3, #0] mode=5; 80035ae: 230f movs r3, #15 80035b0: 18fb adds r3, r7, r3 80035b2: 2205 movs r2, #5 80035b4: 701a strb r2, [r3, #0] } break; 80035b6: e1bf b.n 8003938 80035b8: 00003a98 .word 0x00003a98 80035bc: 200001d0 .word 0x200001d0 80035c0: 200000fc .word 0x200000fc 80035c4: 0000ffff .word 0x0000ffff 80035c8: 2000019c .word 0x2000019c 80035cc: 08003d80 .word 0x08003d80 80035d0: 200000a0 .word 0x200000a0 80035d4: 200001c0 .word 0x200001c0 80035d8: 200001b0 .word 0x200001b0 80035dc: 2000018c .word 0x2000018c 80035e0: 2000016c .word 0x2000016c 80035e4: 00002710 .word 0x00002710 80035e8: 20000154 .word 0x20000154 80035ec: 2000017c .word 0x2000017c case 3: moto.moto1a=0; 80035f0: 4bd3 ldr r3, [pc, #844] ; (8003940 ) 80035f2: 2200 movs r2, #0 80035f4: 721a strb r2, [r3, #8] moto.moto1b=10; 80035f6: 4bd2 ldr r3, [pc, #840] ; (8003940 ) 80035f8: 220a movs r2, #10 80035fa: 725a strb r2, [r3, #9] moto.moto2a=0; 80035fc: 4bd0 ldr r3, [pc, #832] ; (8003940 ) 80035fe: 2200 movs r2, #0 8003600: 729a strb r2, [r3, #10] moto.moto2b=10; 8003602: 4bcf ldr r3, [pc, #828] ; (8003940 ) 8003604: 220a movs r2, #10 8003606: 72da strb r2, [r3, #11] if(HAL_GetTick()>move) 8003608: f7fd f9f2 bl 80009f0 800360c: 0002 movs r2, r0 800360e: 693b ldr r3, [r7, #16] 8003610: 4293 cmp r3, r2 8003612: d219 bcs.n 8003648 { move=HAL_GetTick()+100; 8003614: f7fd f9ec bl 80009f0 8003618: 0003 movs r3, r0 800361a: 3364 adds r3, #100 ; 0x64 800361c: 613b str r3, [r7, #16] if(dis_buff.led_run==1) 800361e: 4bc9 ldr r3, [pc, #804] ; (8003944 ) 8003620: 7b1b ldrb r3, [r3, #12] 8003622: 2b01 cmp r3, #1 8003624: d103 bne.n 800362e { dis_buff.led_run=0; 8003626: 4bc7 ldr r3, [pc, #796] ; (8003944 ) 8003628: 2200 movs r2, #0 800362a: 731a strb r2, [r3, #12] 800362c: e002 b.n 8003634 }else { dis_buff.led_run=1; 800362e: 4bc5 ldr r3, [pc, #788] ; (8003944 ) 8003630: 2201 movs r2, #1 8003632: 731a strb r2, [r3, #12] } countdown-=100; 8003634: 68bb ldr r3, [r7, #8] 8003636: 3b64 subs r3, #100 ; 0x64 8003638: 60bb str r3, [r7, #8] if(countdown<0) 800363a: 68bb ldr r3, [r7, #8] 800363c: 2b00 cmp r3, #0 800363e: da03 bge.n 8003648 { mode=1; 8003640: 230f movs r3, #15 8003642: 18fb adds r3, r7, r3 8003644: 2201 movs r2, #1 8003646: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 8003648: 68bb ldr r3, [r7, #8] 800364a: 2164 movs r1, #100 ; 0x64 800364c: 0018 movs r0, r3 800364e: f7fc fde5 bl 800021c <__divsi3> 8003652: 0003 movs r3, r0 8003654: 210a movs r1, #10 8003656: 0018 movs r0, r3 8003658: f7fc fec6 bl 80003e8 <__aeabi_idivmod> 800365c: 000b movs r3, r1 800365e: b2da uxtb r2, r3 8003660: 4bb8 ldr r3, [pc, #736] ; (8003944 ) 8003662: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 8003664: 68bb ldr r3, [r7, #8] 8003666: 22fa movs r2, #250 ; 0xfa 8003668: 0091 lsls r1, r2, #2 800366a: 0018 movs r0, r3 800366c: f7fc fdd6 bl 800021c <__divsi3> 8003670: 0003 movs r3, r0 8003672: 210a movs r1, #10 8003674: 0018 movs r0, r3 8003676: f7fc feb7 bl 80003e8 <__aeabi_idivmod> 800367a: 000b movs r3, r1 800367c: b2da uxtb r2, r3 800367e: 4bb1 ldr r3, [pc, #708] ; (8003944 ) 8003680: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 8003682: 68bb ldr r3, [r7, #8] 8003684: 49b0 ldr r1, [pc, #704] ; (8003948 ) 8003686: 0018 movs r0, r3 8003688: f7fc fdc8 bl 800021c <__divsi3> 800368c: 0003 movs r3, r0 800368e: 210a movs r1, #10 8003690: 0018 movs r0, r3 8003692: f7fc fea9 bl 80003e8 <__aeabi_idivmod> 8003696: 000b movs r3, r1 8003698: b2da uxtb r2, r3 800369a: 4baa ldr r3, [pc, #680] ; (8003944 ) 800369c: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 800369e: 4ba9 ldr r3, [pc, #676] ; (8003944 ) 80036a0: 785b ldrb r3, [r3, #1] 80036a2: 2b00 cmp r3, #0 80036a4: d002 beq.n 80036ac 80036a6: 4ba7 ldr r3, [pc, #668] ; (8003944 ) 80036a8: 785a ldrb r2, [r3, #1] 80036aa: e000 b.n 80036ae 80036ac: 2210 movs r2, #16 80036ae: 4ba5 ldr r3, [pc, #660] ; (8003944 ) 80036b0: 705a strb r2, [r3, #1] dis_buff.dot4=1; 80036b2: 4ba4 ldr r3, [pc, #656] ; (8003944 ) 80036b4: 2201 movs r2, #1 80036b6: 72da strb r2, [r3, #11] if(key2.code!=0) 80036b8: 4ba4 ldr r3, [pc, #656] ; (800394c ) 80036ba: 681b ldr r3, [r3, #0] 80036bc: 2b00 cmp r3, #0 80036be: d007 beq.n 80036d0 { mode=2; 80036c0: 230f movs r3, #15 80036c2: 18fb adds r3, r7, r3 80036c4: 2202 movs r2, #2 80036c6: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 80036c8: 687a ldr r2, [r7, #4] 80036ca: 68bb ldr r3, [r7, #8] 80036cc: 1ad3 subs r3, r2, r3 80036ce: 60bb str r3, [r7, #8] } if(key4.code!=0) 80036d0: 4b9f ldr r3, [pc, #636] ; (8003950 ) 80036d2: 681b ldr r3, [r3, #0] 80036d4: 2b00 cmp r3, #0 80036d6: d003 beq.n 80036e0 { mode=1; 80036d8: 230f movs r3, #15 80036da: 18fb adds r3, r7, r3 80036dc: 2201 movs r2, #1 80036de: 701a strb r2, [r3, #0] } if(overload.code!=0) 80036e0: 4b9c ldr r3, [pc, #624] ; (8003954 ) 80036e2: 681b ldr r3, [r3, #0] 80036e4: 2b00 cmp r3, #0 80036e6: d005 beq.n 80036f4 { overload_times+=1; 80036e8: 220c movs r2, #12 80036ea: 18bb adds r3, r7, r2 80036ec: 18ba adds r2, r7, r2 80036ee: 8812 ldrh r2, [r2, #0] 80036f0: 3201 adds r2, #1 80036f2: 801a strh r2, [r3, #0] } if(overload_times>2) 80036f4: 230c movs r3, #12 80036f6: 18fb adds r3, r7, r3 80036f8: 881b ldrh r3, [r3, #0] 80036fa: 2b02 cmp r3, #2 80036fc: d800 bhi.n 8003700 80036fe: e11d b.n 800393c { overload_mode=3; 8003700: 230e movs r3, #14 8003702: 18fb adds r3, r7, r3 8003704: 2203 movs r2, #3 8003706: 701a strb r2, [r3, #0] mode=5; 8003708: 230f movs r3, #15 800370a: 18fb adds r3, r7, r3 800370c: 2205 movs r2, #5 800370e: 701a strb r2, [r3, #0] } break; 8003710: e114 b.n 800393c case 4: //setting mode dis_buff.led_run=0; 8003712: 4b8c ldr r3, [pc, #560] ; (8003944 ) 8003714: 2200 movs r2, #0 8003716: 731a strb r2, [r3, #12] if(HAL_GetTick()>move) 8003718: f7fd f96a bl 80009f0 800371c: 0002 movs r2, r0 800371e: 693b ldr r3, [r7, #16] 8003720: 4293 cmp r3, r2 8003722: d230 bcs.n 8003786 { move=HAL_GetTick()+100; 8003724: f7fd f964 bl 80009f0 8003728: 0003 movs r3, r0 800372a: 3364 adds r3, #100 ; 0x64 800372c: 613b str r3, [r7, #16] if(dis_buff.dot4==1) 800372e: 4b85 ldr r3, [pc, #532] ; (8003944 ) 8003730: 7adb ldrb r3, [r3, #11] 8003732: 2b01 cmp r3, #1 8003734: d103 bne.n 800373e { dis_buff.dot4=0; 8003736: 4b83 ldr r3, [pc, #524] ; (8003944 ) 8003738: 2200 movs r2, #0 800373a: 72da strb r2, [r3, #11] 800373c: e002 b.n 8003744 }else { dis_buff.dot4=1; 800373e: 4b81 ldr r3, [pc, #516] ; (8003944 ) 8003740: 2201 movs r2, #1 8003742: 72da strb r2, [r3, #11] } countdown-=100; 8003744: 68bb ldr r3, [r7, #8] 8003746: 3b64 subs r3, #100 ; 0x64 8003748: 60bb str r3, [r7, #8] if(countdown<0) 800374a: 68bb ldr r3, [r7, #8] 800374c: 2b00 cmp r3, #0 800374e: da03 bge.n 8003758 { mode=1; 8003750: 230f movs r3, #15 8003752: 18fb adds r3, r7, r3 8003754: 2201 movs r2, #1 8003756: 701a strb r2, [r3, #0] } if(key2.code<0){countdown_set+=1000;countdown=10000;} 8003758: 4b7c ldr r3, [pc, #496] ; (800394c ) 800375a: 681b ldr r3, [r3, #0] 800375c: 2b00 cmp r3, #0 800375e: da07 bge.n 8003770 8003760: 687b ldr r3, [r7, #4] 8003762: 22fa movs r2, #250 ; 0xfa 8003764: 0092 lsls r2, r2, #2 8003766: 4694 mov ip, r2 8003768: 4463 add r3, ip 800376a: 607b str r3, [r7, #4] 800376c: 4b76 ldr r3, [pc, #472] ; (8003948 ) 800376e: 60bb str r3, [r7, #8] if(key3.code<0){countdown_set-=1000;countdown=10000;} 8003770: 4b79 ldr r3, [pc, #484] ; (8003958 ) 8003772: 681b ldr r3, [r3, #0] 8003774: 2b00 cmp r3, #0 8003776: da06 bge.n 8003786 8003778: 687b ldr r3, [r7, #4] 800377a: 4a78 ldr r2, [pc, #480] ; (800395c ) 800377c: 4694 mov ip, r2 800377e: 4463 add r3, ip 8003780: 607b str r3, [r7, #4] 8003782: 4b71 ldr r3, [pc, #452] ; (8003948 ) 8003784: 60bb str r3, [r7, #8] } if(key2.code>0){countdown_set+=100;countdown=10000;} 8003786: 4b71 ldr r3, [pc, #452] ; (800394c ) 8003788: 681b ldr r3, [r3, #0] 800378a: 2b00 cmp r3, #0 800378c: dd04 ble.n 8003798 800378e: 687b ldr r3, [r7, #4] 8003790: 3364 adds r3, #100 ; 0x64 8003792: 607b str r3, [r7, #4] 8003794: 4b6c ldr r3, [pc, #432] ; (8003948 ) 8003796: 60bb str r3, [r7, #8] if(key3.code>0){countdown_set-=100;countdown=10000;} 8003798: 4b6f ldr r3, [pc, #444] ; (8003958 ) 800379a: 681b ldr r3, [r3, #0] 800379c: 2b00 cmp r3, #0 800379e: dd04 ble.n 80037aa 80037a0: 687b ldr r3, [r7, #4] 80037a2: 3b64 subs r3, #100 ; 0x64 80037a4: 607b str r3, [r7, #4] 80037a6: 4b68 ldr r3, [pc, #416] ; (8003948 ) 80037a8: 60bb str r3, [r7, #8] if(countdown_set<100){countdown_set=100;} 80037aa: 687b ldr r3, [r7, #4] 80037ac: 2b63 cmp r3, #99 ; 0x63 80037ae: dc01 bgt.n 80037b4 80037b0: 2364 movs r3, #100 ; 0x64 80037b2: 607b str r3, [r7, #4] if(countdown_set>60000){countdown_set=60000;} 80037b4: 687b ldr r3, [r7, #4] 80037b6: 4a6a ldr r2, [pc, #424] ; (8003960 ) 80037b8: 4293 cmp r3, r2 80037ba: dd01 ble.n 80037c0 80037bc: 4b68 ldr r3, [pc, #416] ; (8003960 ) 80037be: 607b str r3, [r7, #4] if(key4.code!=0){mode=1;} 80037c0: 4b63 ldr r3, [pc, #396] ; (8003950 ) 80037c2: 681b ldr r3, [r3, #0] 80037c4: 2b00 cmp r3, #0 80037c6: d003 beq.n 80037d0 80037c8: 230f movs r3, #15 80037ca: 18fb adds r3, r7, r3 80037cc: 2201 movs r2, #1 80037ce: 701a strb r2, [r3, #0] dis_buff.d_num[3]=(countdown_set/100)%10; 80037d0: 687b ldr r3, [r7, #4] 80037d2: 2164 movs r1, #100 ; 0x64 80037d4: 0018 movs r0, r3 80037d6: f7fc fd21 bl 800021c <__divsi3> 80037da: 0003 movs r3, r0 80037dc: 210a movs r1, #10 80037de: 0018 movs r0, r3 80037e0: f7fc fe02 bl 80003e8 <__aeabi_idivmod> 80037e4: 000b movs r3, r1 80037e6: b2da uxtb r2, r3 80037e8: 4b56 ldr r3, [pc, #344] ; (8003944 ) 80037ea: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown_set/1000)%10; 80037ec: 687b ldr r3, [r7, #4] 80037ee: 22fa movs r2, #250 ; 0xfa 80037f0: 0091 lsls r1, r2, #2 80037f2: 0018 movs r0, r3 80037f4: f7fc fd12 bl 800021c <__divsi3> 80037f8: 0003 movs r3, r0 80037fa: 210a movs r1, #10 80037fc: 0018 movs r0, r3 80037fe: f7fc fdf3 bl 80003e8 <__aeabi_idivmod> 8003802: 000b movs r3, r1 8003804: b2da uxtb r2, r3 8003806: 4b4f ldr r3, [pc, #316] ; (8003944 ) 8003808: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown_set/10000)%10); 800380a: 687b ldr r3, [r7, #4] 800380c: 494e ldr r1, [pc, #312] ; (8003948 ) 800380e: 0018 movs r0, r3 8003810: f7fc fd04 bl 800021c <__divsi3> 8003814: 0003 movs r3, r0 8003816: 210a movs r1, #10 8003818: 0018 movs r0, r3 800381a: f7fc fde5 bl 80003e8 <__aeabi_idivmod> 800381e: 000b movs r3, r1 8003820: b2da uxtb r2, r3 8003822: 4b48 ldr r3, [pc, #288] ; (8003944 ) 8003824: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 8003826: 4b47 ldr r3, [pc, #284] ; (8003944 ) 8003828: 785b ldrb r3, [r3, #1] 800382a: 2b00 cmp r3, #0 800382c: d002 beq.n 8003834 800382e: 4b45 ldr r3, [pc, #276] ; (8003944 ) 8003830: 785a ldrb r2, [r3, #1] 8003832: e000 b.n 8003836 8003834: 2210 movs r2, #16 8003836: 4b43 ldr r3, [pc, #268] ; (8003944 ) 8003838: 705a strb r2, [r3, #1] break; 800383a: e096 b.n 800396a case 5: //overload moto.moto1a=0; 800383c: 4b40 ldr r3, [pc, #256] ; (8003940 ) 800383e: 2200 movs r2, #0 8003840: 721a strb r2, [r3, #8] moto.moto1b=0; 8003842: 4b3f ldr r3, [pc, #252] ; (8003940 ) 8003844: 2200 movs r2, #0 8003846: 725a strb r2, [r3, #9] moto.moto2a=0; 8003848: 4b3d ldr r3, [pc, #244] ; (8003940 ) 800384a: 2200 movs r2, #0 800384c: 729a strb r2, [r3, #10] moto.moto2b=0; 800384e: 4b3c ldr r3, [pc, #240] ; (8003940 ) 8003850: 2200 movs r2, #0 8003852: 72da strb r2, [r3, #11] dis_buff.led_run=1; 8003854: 4b3b ldr r3, [pc, #236] ; (8003944 ) 8003856: 2201 movs r2, #1 8003858: 731a strb r2, [r3, #12] overload_times=0; 800385a: 230c movs r3, #12 800385c: 18fb adds r3, r7, r3 800385e: 2200 movs r2, #0 8003860: 801a strh r2, [r3, #0] dis_buff.d_num[3]=(countdown/100)%10; 8003862: 68bb ldr r3, [r7, #8] 8003864: 2164 movs r1, #100 ; 0x64 8003866: 0018 movs r0, r3 8003868: f7fc fcd8 bl 800021c <__divsi3> 800386c: 0003 movs r3, r0 800386e: 210a movs r1, #10 8003870: 0018 movs r0, r3 8003872: f7fc fdb9 bl 80003e8 <__aeabi_idivmod> 8003876: 000b movs r3, r1 8003878: b2da uxtb r2, r3 800387a: 4b32 ldr r3, [pc, #200] ; (8003944 ) 800387c: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 800387e: 68bb ldr r3, [r7, #8] 8003880: 22fa movs r2, #250 ; 0xfa 8003882: 0091 lsls r1, r2, #2 8003884: 0018 movs r0, r3 8003886: f7fc fcc9 bl 800021c <__divsi3> 800388a: 0003 movs r3, r0 800388c: 210a movs r1, #10 800388e: 0018 movs r0, r3 8003890: f7fc fdaa bl 80003e8 <__aeabi_idivmod> 8003894: 000b movs r3, r1 8003896: b2da uxtb r2, r3 8003898: 4b2a ldr r3, [pc, #168] ; (8003944 ) 800389a: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 800389c: 68bb ldr r3, [r7, #8] 800389e: 492a ldr r1, [pc, #168] ; (8003948 ) 80038a0: 0018 movs r0, r3 80038a2: f7fc fcbb bl 800021c <__divsi3> 80038a6: 0003 movs r3, r0 80038a8: 210a movs r1, #10 80038aa: 0018 movs r0, r3 80038ac: f7fc fd9c bl 80003e8 <__aeabi_idivmod> 80038b0: 000b movs r3, r1 80038b2: b2da uxtb r2, r3 80038b4: 4b23 ldr r3, [pc, #140] ; (8003944 ) 80038b6: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 80038b8: 4b22 ldr r3, [pc, #136] ; (8003944 ) 80038ba: 785b ldrb r3, [r3, #1] 80038bc: 2b00 cmp r3, #0 80038be: d002 beq.n 80038c6 80038c0: 4b20 ldr r3, [pc, #128] ; (8003944 ) 80038c2: 785a ldrb r2, [r3, #1] 80038c4: e000 b.n 80038c8 80038c6: 2210 movs r2, #16 80038c8: 4b1e ldr r3, [pc, #120] ; (8003944 ) 80038ca: 705a strb r2, [r3, #1] dis_buff.dot3=1; 80038cc: 4b1d ldr r3, [pc, #116] ; (8003944 ) 80038ce: 2201 movs r2, #1 80038d0: 729a strb r2, [r3, #10] if(key4.code!=0){mode=1;} 80038d2: 4b1f ldr r3, [pc, #124] ; (8003950 ) 80038d4: 681b ldr r3, [r3, #0] 80038d6: 2b00 cmp r3, #0 80038d8: d003 beq.n 80038e2 80038da: 230f movs r3, #15 80038dc: 18fb adds r3, r7, r3 80038de: 2201 movs r2, #1 80038e0: 701a strb r2, [r3, #0] if(key2.code!=0) 80038e2: 4b1a ldr r3, [pc, #104] ; (800394c ) 80038e4: 681b ldr r3, [r3, #0] 80038e6: 2b00 cmp r3, #0 80038e8: d00c beq.n 8003904 { mode=2; 80038ea: 230f movs r3, #15 80038ec: 18fb adds r3, r7, r3 80038ee: 2202 movs r2, #2 80038f0: 701a strb r2, [r3, #0] if(overload_mode==2) 80038f2: 230e movs r3, #14 80038f4: 18fb adds r3, r7, r3 80038f6: 781b ldrb r3, [r3, #0] 80038f8: 2b02 cmp r3, #2 80038fa: d003 beq.n 8003904 { }else { countdown=countdown_set-countdown; 80038fc: 687a ldr r2, [r7, #4] 80038fe: 68bb ldr r3, [r7, #8] 8003900: 1ad3 subs r3, r2, r3 8003902: 60bb str r3, [r7, #8] } } if(key3.code!=0) 8003904: 4b14 ldr r3, [pc, #80] ; (8003958 ) 8003906: 681b ldr r3, [r3, #0] 8003908: 2b00 cmp r3, #0 800390a: d02d beq.n 8003968 { mode=3; 800390c: 230f movs r3, #15 800390e: 18fb adds r3, r7, r3 8003910: 2203 movs r2, #3 8003912: 701a strb r2, [r3, #0] if(overload_mode==3) 8003914: 230e movs r3, #14 8003916: 18fb adds r3, r7, r3 8003918: 781b ldrb r3, [r3, #0] 800391a: 2b03 cmp r3, #3 800391c: d024 beq.n 8003968 { }else { countdown=countdown_set-countdown; 800391e: 687a ldr r2, [r7, #4] 8003920: 68bb ldr r3, [r7, #8] 8003922: 1ad3 subs r3, r2, r3 8003924: 60bb str r3, [r7, #8] } } break; 8003926: e01f b.n 8003968 case 6: //stady mode config.begin=0xab; 8003928: 4b0e ldr r3, [pc, #56] ; (8003964 ) 800392a: 22ab movs r2, #171 ; 0xab 800392c: 701a strb r2, [r3, #0] //EEPROM_WRITE_BATY(16,(char *)&config,sizeof(config_setting)); //mode=0; break; 800392e: e01c b.n 800396a break; 8003930: 46c0 nop ; (mov r8, r8) 8003932: e01a b.n 800396a break; 8003934: 46c0 nop ; (mov r8, r8) 8003936: e018 b.n 800396a break; 8003938: 46c0 nop ; (mov r8, r8) 800393a: e016 b.n 800396a break; 800393c: 46c0 nop ; (mov r8, r8) 800393e: e014 b.n 800396a 8003940: 200001c0 .word 0x200001c0 8003944: 200000a0 .word 0x200000a0 8003948: 00002710 .word 0x00002710 800394c: 200001b0 .word 0x200001b0 8003950: 20000154 .word 0x20000154 8003954: 2000017c .word 0x2000017c 8003958: 2000018c .word 0x2000018c 800395c: fffffc18 .word 0xfffffc18 8003960: 0000ea60 .word 0x0000ea60 8003964: 200001d0 .word 0x200001d0 break; 8003968: 46c0 nop ; (mov r8, r8) } if(ADCC.adc_value[0]>600||ADCC.adc_value[1]>600) 800396a: 4b34 ldr r3, [pc, #208] ; (8003a3c ) 800396c: 68da ldr r2, [r3, #12] 800396e: 2396 movs r3, #150 ; 0x96 8003970: 009b lsls r3, r3, #2 8003972: 429a cmp r2, r3 8003974: dc05 bgt.n 8003982 8003976: 4b31 ldr r3, [pc, #196] ; (8003a3c ) 8003978: 691a ldr r2, [r3, #16] 800397a: 2396 movs r3, #150 ; 0x96 800397c: 009b lsls r3, r3, #2 800397e: 429a cmp r2, r3 8003980: dd05 ble.n 800398e { GEI_BUTTON_CODE(&overload,1); 8003982: 4b2f ldr r3, [pc, #188] ; (8003a40 ) 8003984: 2101 movs r1, #1 8003986: 0018 movs r0, r3 8003988: f7fe fe24 bl 80025d4 800398c: e004 b.n 8003998 }else { GEI_BUTTON_CODE(&overload,0); 800398e: 4b2c ldr r3, [pc, #176] ; (8003a40 ) 8003990: 2100 movs r1, #0 8003992: 0018 movs r0, r3 8003994: f7fe fe1e bl 80025d4 } switch(r480.key) 8003998: 4b2a ldr r3, [pc, #168] ; (8003a44 ) 800399a: 789b ldrb r3, [r3, #2] 800399c: 2bde cmp r3, #222 ; 0xde 800399e: d014 beq.n 80039ca 80039a0: dc17 bgt.n 80039d2 80039a2: 2bdd cmp r3, #221 ; 0xdd 80039a4: d00d beq.n 80039c2 80039a6: dc14 bgt.n 80039d2 80039a8: 2bd7 cmp r3, #215 ; 0xd7 80039aa: d002 beq.n 80039b2 80039ac: 2bdb cmp r3, #219 ; 0xdb 80039ae: d004 beq.n 80039ba 80039b0: e00f b.n 80039d2 { case 0xd7: dis_buff.button_flag[0]=1; 80039b2: 4b25 ldr r3, [pc, #148] ; (8003a48 ) 80039b4: 2201 movs r2, #1 80039b6: 711a strb r2, [r3, #4] break; 80039b8: e00b b.n 80039d2 case 0xdb: dis_buff.button_flag[1]=1; 80039ba: 4b23 ldr r3, [pc, #140] ; (8003a48 ) 80039bc: 2201 movs r2, #1 80039be: 715a strb r2, [r3, #5] break; 80039c0: e007 b.n 80039d2 case 0xdd: dis_buff.button_flag[2]=1; 80039c2: 4b21 ldr r3, [pc, #132] ; (8003a48 ) 80039c4: 2201 movs r2, #1 80039c6: 719a strb r2, [r3, #6] break; 80039c8: e003 b.n 80039d2 case 0xde: dis_buff.button_flag[3]=1; 80039ca: 4b1f ldr r3, [pc, #124] ; (8003a48 ) 80039cc: 2201 movs r2, #1 80039ce: 71da strb r2, [r3, #7] break; 80039d0: 46c0 nop ; (mov r8, r8) } r480.key=0; 80039d2: 4b1c ldr r3, [pc, #112] ; (8003a44 ) 80039d4: 2200 movs r2, #0 80039d6: 709a strb r2, [r3, #2] GEI_BUTTON_CODE(&key1,dis_buff.button_flag[0]); 80039d8: 4b1b ldr r3, [pc, #108] ; (8003a48 ) 80039da: 791a ldrb r2, [r3, #4] 80039dc: 4b1b ldr r3, [pc, #108] ; (8003a4c ) 80039de: 0011 movs r1, r2 80039e0: 0018 movs r0, r3 80039e2: f7fe fdf7 bl 80025d4 GEI_BUTTON_CODE(&key2,dis_buff.button_flag[1]); 80039e6: 4b18 ldr r3, [pc, #96] ; (8003a48 ) 80039e8: 795a ldrb r2, [r3, #5] 80039ea: 4b19 ldr r3, [pc, #100] ; (8003a50 ) 80039ec: 0011 movs r1, r2 80039ee: 0018 movs r0, r3 80039f0: f7fe fdf0 bl 80025d4 GEI_BUTTON_CODE(&key3,dis_buff.button_flag[2]); 80039f4: 4b14 ldr r3, [pc, #80] ; (8003a48 ) 80039f6: 799a ldrb r2, [r3, #6] 80039f8: 4b16 ldr r3, [pc, #88] ; (8003a54 ) 80039fa: 0011 movs r1, r2 80039fc: 0018 movs r0, r3 80039fe: f7fe fde9 bl 80025d4 GEI_BUTTON_CODE(&key4,dis_buff.button_flag[3]); 8003a02: 4b11 ldr r3, [pc, #68] ; (8003a48 ) 8003a04: 79da ldrb r2, [r3, #7] 8003a06: 4b14 ldr r3, [pc, #80] ; (8003a58 ) 8003a08: 0011 movs r1, r2 8003a0a: 0018 movs r0, r3 8003a0c: f7fe fde2 bl 80025d4 dis_buff.button_flag[0]=0; 8003a10: 4b0d ldr r3, [pc, #52] ; (8003a48 ) 8003a12: 2200 movs r2, #0 8003a14: 711a strb r2, [r3, #4] dis_buff.button_flag[1]=0; 8003a16: 4b0c ldr r3, [pc, #48] ; (8003a48 ) 8003a18: 2200 movs r2, #0 8003a1a: 715a strb r2, [r3, #5] dis_buff.button_flag[2]=0; 8003a1c: 4b0a ldr r3, [pc, #40] ; (8003a48 ) 8003a1e: 2200 movs r2, #0 8003a20: 719a strb r2, [r3, #6] dis_buff.button_flag[3]=0; 8003a22: 4b09 ldr r3, [pc, #36] ; (8003a48 ) 8003a24: 2200 movs r2, #0 8003a26: 71da strb r2, [r3, #7] EEPROM_SLOWWRITE_SERVER(); 8003a28: f7fe fe4a bl 80026c0 HT1621_Display_GetButton(); 8003a2c: f7ff fb4e bl 80030cc hc2_sever(); 8003a30: f7ff fa38 bl 8002ea4 moto_server(); 8003a34: f7ff fa7a bl 8002f2c for(char a=0;a<2;a++) 8003a38: f7ff fc05 bl 8003246 8003a3c: 2000019c .word 0x2000019c 8003a40: 2000017c .word 0x2000017c 8003a44: 20000164 .word 0x20000164 8003a48: 200000a0 .word 0x200000a0 8003a4c: 2000016c .word 0x2000016c 8003a50: 200001b0 .word 0x200001b0 8003a54: 2000018c .word 0x2000018c 8003a58: 20000154 .word 0x20000154 08003a5c : int read_char_flag=0; char read_data_buffer[3]; char read_begin=0; void r480_init() { 8003a5c: b580 push {r7, lr} 8003a5e: af00 add r7, sp, #0 HAL_TIM_Base_Start_IT(&htim14); 8003a60: 4b04 ldr r3, [pc, #16] ; (8003a74 ) 8003a62: 0018 movs r0, r3 8003a64: f7fe fbbe bl 80021e4 r480.times=0; 8003a68: 4b03 ldr r3, [pc, #12] ; (8003a78 ) 8003a6a: 2200 movs r2, #0 8003a6c: 809a strh r2, [r3, #4] } 8003a6e: 46c0 nop ; (mov r8, r8) 8003a70: 46bd mov sp, r7 8003a72: bd80 pop {r7, pc} 8003a74: 200000b4 .word 0x200000b4 8003a78: 20000164 .word 0x20000164 08003a7c : void read_433_exit() { 8003a7c: b590 push {r4, r7, lr} 8003a7e: b083 sub sp, #12 8003a80: af00 add r7, sp, #0 char a=read_infrared; 8003a82: 1dfc adds r4, r7, #7 8003a84: 2390 movs r3, #144 ; 0x90 8003a86: 05db lsls r3, r3, #23 8003a88: 2108 movs r1, #8 8003a8a: 0018 movs r0, r3 8003a8c: f7fd feb8 bl 8001800 8003a90: 0003 movs r3, r0 8003a92: 7023 strb r3, [r4, #0] int b; if(read_begin==0) 8003a94: 4b41 ldr r3, [pc, #260] ; (8003b9c ) 8003a96: 781b ldrb r3, [r3, #0] 8003a98: 2b00 cmp r3, #0 8003a9a: d123 bne.n 8003ae4 { if(a==0) 8003a9c: 1dfb adds r3, r7, #7 8003a9e: 781b ldrb r3, [r3, #0] 8003aa0: 2b00 cmp r3, #0 8003aa2: d103 bne.n 8003aac { timer_100us_tick=0; 8003aa4: 4b3e ldr r3, [pc, #248] ; (8003ba0 ) 8003aa6: 2200 movs r2, #0 8003aa8: 801a strh r2, [r3, #0] return ; 8003aaa: e073 b.n 8003b94 }else { if(timer_100us_tick>70&&timer_100us_tick<100) 8003aac: 4b3c ldr r3, [pc, #240] ; (8003ba0 ) 8003aae: 881b ldrh r3, [r3, #0] 8003ab0: 2b46 cmp r3, #70 ; 0x46 8003ab2: d800 bhi.n 8003ab6 8003ab4: e06e b.n 8003b94 8003ab6: 4b3a ldr r3, [pc, #232] ; (8003ba0 ) 8003ab8: 881b ldrh r3, [r3, #0] 8003aba: 2b63 cmp r3, #99 ; 0x63 8003abc: d86a bhi.n 8003b94 { read_begin=1; 8003abe: 4b37 ldr r3, [pc, #220] ; (8003b9c ) 8003ac0: 2201 movs r2, #1 8003ac2: 701a strb r2, [r3, #0] r480.times++; 8003ac4: 4b37 ldr r3, [pc, #220] ; (8003ba4 ) 8003ac6: 889b ldrh r3, [r3, #4] 8003ac8: 3301 adds r3, #1 8003aca: b29a uxth r2, r3 8003acc: 4b35 ldr r3, [pc, #212] ; (8003ba4 ) 8003ace: 809a strh r2, [r3, #4] read_bit_flag=0; 8003ad0: 4b35 ldr r3, [pc, #212] ; (8003ba8 ) 8003ad2: 2200 movs r2, #0 8003ad4: 601a str r2, [r3, #0] read_char_flag=0; 8003ad6: 4b35 ldr r3, [pc, #212] ; (8003bac ) 8003ad8: 2200 movs r2, #0 8003ada: 601a str r2, [r3, #0] timer_100us_tick=0; 8003adc: 4b30 ldr r3, [pc, #192] ; (8003ba0 ) 8003ade: 2200 movs r2, #0 8003ae0: 801a strh r2, [r3, #0] return ; 8003ae2: e057 b.n 8003b94 } } }else { if(timer_100us_tick<5) 8003ae4: 4b2e ldr r3, [pc, #184] ; (8003ba0 ) 8003ae6: 881b ldrh r3, [r3, #0] 8003ae8: 2b04 cmp r3, #4 8003aea: d803 bhi.n 8003af4 { timer_100us_tick=0; 8003aec: 4b2c ldr r3, [pc, #176] ; (8003ba0 ) 8003aee: 2200 movs r2, #0 8003af0: 801a strh r2, [r3, #0] return ; 8003af2: e04f b.n 8003b94 }else if(timer_100us_tick<12) 8003af4: 4b2a ldr r3, [pc, #168] ; (8003ba0 ) 8003af6: 881b ldrh r3, [r3, #0] 8003af8: 2b0b cmp r3, #11 8003afa: d844 bhi.n 8003b86 { read_data_buffer[read_char_flag]<<=1; 8003afc: 4b2b ldr r3, [pc, #172] ; (8003bac ) 8003afe: 681b ldr r3, [r3, #0] 8003b00: 4a2b ldr r2, [pc, #172] ; (8003bb0 ) 8003b02: 5cd1 ldrb r1, [r2, r3] 8003b04: 4b29 ldr r3, [pc, #164] ; (8003bac ) 8003b06: 681a ldr r2, [r3, #0] 8003b08: 1c0b adds r3, r1, #0 8003b0a: 18db adds r3, r3, r3 8003b0c: b2d9 uxtb r1, r3 8003b0e: 4b28 ldr r3, [pc, #160] ; (8003bb0 ) 8003b10: 5499 strb r1, [r3, r2] if(a==1) 8003b12: 1dfb adds r3, r7, #7 8003b14: 781b ldrb r3, [r3, #0] 8003b16: 2b01 cmp r3, #1 8003b18: d10a bne.n 8003b30 { read_data_buffer[read_char_flag]|=0x01; 8003b1a: 4b24 ldr r3, [pc, #144] ; (8003bac ) 8003b1c: 681b ldr r3, [r3, #0] 8003b1e: 4a24 ldr r2, [pc, #144] ; (8003bb0 ) 8003b20: 5cd2 ldrb r2, [r2, r3] 8003b22: 4b22 ldr r3, [pc, #136] ; (8003bac ) 8003b24: 681b ldr r3, [r3, #0] 8003b26: 2101 movs r1, #1 8003b28: 430a orrs r2, r1 8003b2a: b2d1 uxtb r1, r2 8003b2c: 4a20 ldr r2, [pc, #128] ; (8003bb0 ) 8003b2e: 54d1 strb r1, [r2, r3] } read_bit_flag++; 8003b30: 4b1d ldr r3, [pc, #116] ; (8003ba8 ) 8003b32: 681b ldr r3, [r3, #0] 8003b34: 1c5a adds r2, r3, #1 8003b36: 4b1c ldr r3, [pc, #112] ; (8003ba8 ) 8003b38: 601a str r2, [r3, #0] if(read_bit_flag==8) 8003b3a: 4b1b ldr r3, [pc, #108] ; (8003ba8 ) 8003b3c: 681b ldr r3, [r3, #0] 8003b3e: 2b08 cmp r3, #8 8003b40: d11d bne.n 8003b7e { read_bit_flag=0; 8003b42: 4b19 ldr r3, [pc, #100] ; (8003ba8 ) 8003b44: 2200 movs r2, #0 8003b46: 601a str r2, [r3, #0] read_char_flag++; 8003b48: 4b18 ldr r3, [pc, #96] ; (8003bac ) 8003b4a: 681b ldr r3, [r3, #0] 8003b4c: 1c5a adds r2, r3, #1 8003b4e: 4b17 ldr r3, [pc, #92] ; (8003bac ) 8003b50: 601a str r2, [r3, #0] if(read_char_flag==3) 8003b52: 4b16 ldr r3, [pc, #88] ; (8003bac ) 8003b54: 681b ldr r3, [r3, #0] 8003b56: 2b03 cmp r3, #3 8003b58: d111 bne.n 8003b7e { //got data read_char_flag=0; 8003b5a: 4b14 ldr r3, [pc, #80] ; (8003bac ) 8003b5c: 2200 movs r2, #0 8003b5e: 601a str r2, [r3, #0] timer_100us_tick=0; 8003b60: 4b0f ldr r3, [pc, #60] ; (8003ba0 ) 8003b62: 2200 movs r2, #0 8003b64: 801a strh r2, [r3, #0] r480.add[0]=read_data_buffer[0]; 8003b66: 4b12 ldr r3, [pc, #72] ; (8003bb0 ) 8003b68: 781a ldrb r2, [r3, #0] 8003b6a: 4b0e ldr r3, [pc, #56] ; (8003ba4 ) 8003b6c: 701a strb r2, [r3, #0] r480.add[1]=read_data_buffer[1]; 8003b6e: 4b10 ldr r3, [pc, #64] ; (8003bb0 ) 8003b70: 785a ldrb r2, [r3, #1] 8003b72: 4b0c ldr r3, [pc, #48] ; (8003ba4 ) 8003b74: 705a strb r2, [r3, #1] r480.key=read_data_buffer[2]; 8003b76: 4b0e ldr r3, [pc, #56] ; (8003bb0 ) 8003b78: 789a ldrb r2, [r3, #2] 8003b7a: 4b0a ldr r3, [pc, #40] ; (8003ba4 ) 8003b7c: 709a strb r2, [r3, #2] } } timer_100us_tick=0; 8003b7e: 4b08 ldr r3, [pc, #32] ; (8003ba0 ) 8003b80: 2200 movs r2, #0 8003b82: 801a strh r2, [r3, #0] return ; 8003b84: e006 b.n 8003b94 }else//time out { read_begin=0; 8003b86: 4b05 ldr r3, [pc, #20] ; (8003b9c ) 8003b88: 2200 movs r2, #0 8003b8a: 701a strb r2, [r3, #0] timer_100us_tick=0; 8003b8c: 4b04 ldr r3, [pc, #16] ; (8003ba0 ) 8003b8e: 2200 movs r2, #0 8003b90: 801a strh r2, [r3, #0] return ; 8003b92: 46c0 nop ; (mov r8, r8) } } } 8003b94: 46bd mov sp, r7 8003b96: b003 add sp, #12 8003b98: bd90 pop {r4, r7, pc} 8003b9a: 46c0 nop ; (mov r8, r8) 8003b9c: 20000098 .word 0x20000098 8003ba0: 2000008c .word 0x2000008c 8003ba4: 20000164 .word 0x20000164 8003ba8: 20000090 .word 0x20000090 8003bac: 20000094 .word 0x20000094 8003bb0: 200001dc .word 0x200001dc 08003bb4 : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8003bb4: b580 push {r7, lr} 8003bb6: b082 sub sp, #8 8003bb8: af00 add r7, sp, #0 8003bba: 0002 movs r2, r0 8003bbc: 1dbb adds r3, r7, #6 8003bbe: 801a strh r2, [r3, #0] switch(GPIO_Pin) 8003bc0: 1dbb adds r3, r7, #6 8003bc2: 881b ldrh r3, [r3, #0] 8003bc4: 2b08 cmp r3, #8 8003bc6: d102 bne.n 8003bce { case infeaed_Pin: read_433_exit(); 8003bc8: f7ff ff58 bl 8003a7c return ; 8003bcc: 46c0 nop ; (mov r8, r8) break; } } 8003bce: 46bd mov sp, r7 8003bd0: b002 add sp, #8 8003bd2: bd80 pop {r7, pc} 08003bd4 : void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)//100us { 8003bd4: b580 push {r7, lr} 8003bd6: b082 sub sp, #8 8003bd8: af00 add r7, sp, #0 8003bda: 6078 str r0, [r7, #4] if (htim == (&htim14)) 8003bdc: 687a ldr r2, [r7, #4] 8003bde: 4b06 ldr r3, [pc, #24] ; (8003bf8 ) 8003be0: 429a cmp r2, r3 8003be2: d105 bne.n 8003bf0 { timer_100us_tick++; 8003be4: 4b05 ldr r3, [pc, #20] ; (8003bfc ) 8003be6: 881b ldrh r3, [r3, #0] 8003be8: 3301 adds r3, #1 8003bea: b29a uxth r2, r3 8003bec: 4b03 ldr r3, [pc, #12] ; (8003bfc ) 8003bee: 801a strh r2, [r3, #0] } } 8003bf0: 46c0 nop ; (mov r8, r8) 8003bf2: 46bd mov sp, r7 8003bf4: b002 add sp, #8 8003bf6: bd80 pop {r7, pc} 8003bf8: 200000b4 .word 0x200000b4 8003bfc: 2000008c .word 0x2000008c 08003c00 <__libc_init_array>: 8003c00: b570 push {r4, r5, r6, lr} 8003c02: 2600 movs r6, #0 8003c04: 4d0c ldr r5, [pc, #48] ; (8003c38 <__libc_init_array+0x38>) 8003c06: 4c0d ldr r4, [pc, #52] ; (8003c3c <__libc_init_array+0x3c>) 8003c08: 1b64 subs r4, r4, r5 8003c0a: 10a4 asrs r4, r4, #2 8003c0c: 42a6 cmp r6, r4 8003c0e: d109 bne.n 8003c24 <__libc_init_array+0x24> 8003c10: 2600 movs r6, #0 8003c12: f000 f887 bl 8003d24 <_init> 8003c16: 4d0a ldr r5, [pc, #40] ; (8003c40 <__libc_init_array+0x40>) 8003c18: 4c0a ldr r4, [pc, #40] ; (8003c44 <__libc_init_array+0x44>) 8003c1a: 1b64 subs r4, r4, r5 8003c1c: 10a4 asrs r4, r4, #2 8003c1e: 42a6 cmp r6, r4 8003c20: d105 bne.n 8003c2e <__libc_init_array+0x2e> 8003c22: bd70 pop {r4, r5, r6, pc} 8003c24: 00b3 lsls r3, r6, #2 8003c26: 58eb ldr r3, [r5, r3] 8003c28: 4798 blx r3 8003c2a: 3601 adds r6, #1 8003c2c: e7ee b.n 8003c0c <__libc_init_array+0xc> 8003c2e: 00b3 lsls r3, r6, #2 8003c30: 58eb ldr r3, [r5, r3] 8003c32: 4798 blx r3 8003c34: 3601 adds r6, #1 8003c36: e7f2 b.n 8003c1e <__libc_init_array+0x1e> 8003c38: 08003d9c .word 0x08003d9c 8003c3c: 08003d9c .word 0x08003d9c 8003c40: 08003d9c .word 0x08003d9c 8003c44: 08003da0 .word 0x08003da0 08003c48 : 8003c48: b510 push {r4, lr} 8003c4a: 4b03 ldr r3, [pc, #12] ; (8003c58 ) 8003c4c: 0001 movs r1, r0 8003c4e: 6818 ldr r0, [r3, #0] 8003c50: f000 f80c bl 8003c6c <_free_r> 8003c54: bd10 pop {r4, pc} 8003c56: 46c0 nop ; (mov r8, r8) 8003c58: 2000000c .word 0x2000000c 08003c5c : 8003c5c: 0003 movs r3, r0 8003c5e: 1882 adds r2, r0, r2 8003c60: 4293 cmp r3, r2 8003c62: d100 bne.n 8003c66 8003c64: 4770 bx lr 8003c66: 7019 strb r1, [r3, #0] 8003c68: 3301 adds r3, #1 8003c6a: e7f9 b.n 8003c60 08003c6c <_free_r>: 8003c6c: b570 push {r4, r5, r6, lr} 8003c6e: 0005 movs r5, r0 8003c70: 2900 cmp r1, #0 8003c72: d010 beq.n 8003c96 <_free_r+0x2a> 8003c74: 1f0c subs r4, r1, #4 8003c76: 6823 ldr r3, [r4, #0] 8003c78: 2b00 cmp r3, #0 8003c7a: da00 bge.n 8003c7e <_free_r+0x12> 8003c7c: 18e4 adds r4, r4, r3 8003c7e: 0028 movs r0, r5 8003c80: f000 f83e bl 8003d00 <__malloc_lock> 8003c84: 4a1d ldr r2, [pc, #116] ; (8003cfc <_free_r+0x90>) 8003c86: 6813 ldr r3, [r2, #0] 8003c88: 2b00 cmp r3, #0 8003c8a: d105 bne.n 8003c98 <_free_r+0x2c> 8003c8c: 6063 str r3, [r4, #4] 8003c8e: 6014 str r4, [r2, #0] 8003c90: 0028 movs r0, r5 8003c92: f000 f83d bl 8003d10 <__malloc_unlock> 8003c96: bd70 pop {r4, r5, r6, pc} 8003c98: 42a3 cmp r3, r4 8003c9a: d908 bls.n 8003cae <_free_r+0x42> 8003c9c: 6821 ldr r1, [r4, #0] 8003c9e: 1860 adds r0, r4, r1 8003ca0: 4283 cmp r3, r0 8003ca2: d1f3 bne.n 8003c8c <_free_r+0x20> 8003ca4: 6818 ldr r0, [r3, #0] 8003ca6: 685b ldr r3, [r3, #4] 8003ca8: 1841 adds r1, r0, r1 8003caa: 6021 str r1, [r4, #0] 8003cac: e7ee b.n 8003c8c <_free_r+0x20> 8003cae: 001a movs r2, r3 8003cb0: 685b ldr r3, [r3, #4] 8003cb2: 2b00 cmp r3, #0 8003cb4: d001 beq.n 8003cba <_free_r+0x4e> 8003cb6: 42a3 cmp r3, r4 8003cb8: d9f9 bls.n 8003cae <_free_r+0x42> 8003cba: 6811 ldr r1, [r2, #0] 8003cbc: 1850 adds r0, r2, r1 8003cbe: 42a0 cmp r0, r4 8003cc0: d10b bne.n 8003cda <_free_r+0x6e> 8003cc2: 6820 ldr r0, [r4, #0] 8003cc4: 1809 adds r1, r1, r0 8003cc6: 1850 adds r0, r2, r1 8003cc8: 6011 str r1, [r2, #0] 8003cca: 4283 cmp r3, r0 8003ccc: d1e0 bne.n 8003c90 <_free_r+0x24> 8003cce: 6818 ldr r0, [r3, #0] 8003cd0: 685b ldr r3, [r3, #4] 8003cd2: 1841 adds r1, r0, r1 8003cd4: 6011 str r1, [r2, #0] 8003cd6: 6053 str r3, [r2, #4] 8003cd8: e7da b.n 8003c90 <_free_r+0x24> 8003cda: 42a0 cmp r0, r4 8003cdc: d902 bls.n 8003ce4 <_free_r+0x78> 8003cde: 230c movs r3, #12 8003ce0: 602b str r3, [r5, #0] 8003ce2: e7d5 b.n 8003c90 <_free_r+0x24> 8003ce4: 6821 ldr r1, [r4, #0] 8003ce6: 1860 adds r0, r4, r1 8003ce8: 4283 cmp r3, r0 8003cea: d103 bne.n 8003cf4 <_free_r+0x88> 8003cec: 6818 ldr r0, [r3, #0] 8003cee: 685b ldr r3, [r3, #4] 8003cf0: 1841 adds r1, r0, r1 8003cf2: 6021 str r1, [r4, #0] 8003cf4: 6063 str r3, [r4, #4] 8003cf6: 6054 str r4, [r2, #4] 8003cf8: e7ca b.n 8003c90 <_free_r+0x24> 8003cfa: 46c0 nop ; (mov r8, r8) 8003cfc: 2000009c .word 0x2000009c 08003d00 <__malloc_lock>: 8003d00: b510 push {r4, lr} 8003d02: 4802 ldr r0, [pc, #8] ; (8003d0c <__malloc_lock+0xc>) 8003d04: f000 f80c bl 8003d20 <__retarget_lock_acquire_recursive> 8003d08: bd10 pop {r4, pc} 8003d0a: 46c0 nop ; (mov r8, r8) 8003d0c: 200001e3 .word 0x200001e3 08003d10 <__malloc_unlock>: 8003d10: b510 push {r4, lr} 8003d12: 4802 ldr r0, [pc, #8] ; (8003d1c <__malloc_unlock+0xc>) 8003d14: f000 f805 bl 8003d22 <__retarget_lock_release_recursive> 8003d18: bd10 pop {r4, pc} 8003d1a: 46c0 nop ; (mov r8, r8) 8003d1c: 200001e3 .word 0x200001e3 08003d20 <__retarget_lock_acquire_recursive>: 8003d20: 4770 bx lr 08003d22 <__retarget_lock_release_recursive>: 8003d22: 4770 bx lr 08003d24 <_init>: 8003d24: b5f8 push {r3, r4, r5, r6, r7, lr} 8003d26: 46c0 nop ; (mov r8, r8) 8003d28: bcf8 pop {r3, r4, r5, r6, r7} 8003d2a: bc08 pop {r3} 8003d2c: 469e mov lr, r3 8003d2e: 4770 bx lr 08003d30 <_fini>: 8003d30: b5f8 push {r3, r4, r5, r6, r7, lr} 8003d32: 46c0 nop ; (mov r8, r8) 8003d34: bcf8 pop {r3, r4, r5, r6, r7} 8003d36: bc08 pop {r3} 8003d38: 469e mov lr, r3 8003d3a: 4770 bx lr