Motor_Controller2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00003e00 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000058 08003ec0 08003ec0 00013ec0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08003f18 08003f18 0002000c 2**0 CONTENTS 4 .ARM 00000000 08003f18 08003f18 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 08003f18 08003f18 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08003f18 08003f18 00013f18 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08003f1c 08003f1c 00013f1c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 08003f20 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000144 2000000c 08003f2c 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000600 20000150 08003f2c 00020150 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 0000be6e 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000022ae 00000000 00000000 0002bea2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000b88 00000000 00000000 0002e150 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000a50 00000000 00000000 0002ecd8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00010442 00000000 00000000 0002f728 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000f273 00000000 00000000 0003fb6a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0005f5c4 00000000 00000000 0004eddd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 000ae3a1 2**0 CONTENTS, READONLY 20 .debug_frame 00002790 00000000 00000000 000ae3f4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 2000000c .word 0x2000000c 80000e0: 00000000 .word 0x00000000 80000e4: 08003ea8 .word 0x08003ea8 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000010 .word 0x20000010 8000104: 08003ea8 .word 0x08003ea8 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__divsi3>: 800021c: 4603 mov r3, r0 800021e: 430b orrs r3, r1 8000220: d47f bmi.n 8000322 <__divsi3+0x106> 8000222: 2200 movs r2, #0 8000224: 0843 lsrs r3, r0, #1 8000226: 428b cmp r3, r1 8000228: d374 bcc.n 8000314 <__divsi3+0xf8> 800022a: 0903 lsrs r3, r0, #4 800022c: 428b cmp r3, r1 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4> 8000230: 0a03 lsrs r3, r0, #8 8000232: 428b cmp r3, r1 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4> 8000236: 0b03 lsrs r3, r0, #12 8000238: 428b cmp r3, r1 800023a: d328 bcc.n 800028e <__divsi3+0x72> 800023c: 0c03 lsrs r3, r0, #16 800023e: 428b cmp r3, r1 8000240: d30d bcc.n 800025e <__divsi3+0x42> 8000242: 22ff movs r2, #255 ; 0xff 8000244: 0209 lsls r1, r1, #8 8000246: ba12 rev r2, r2 8000248: 0c03 lsrs r3, r0, #16 800024a: 428b cmp r3, r1 800024c: d302 bcc.n 8000254 <__divsi3+0x38> 800024e: 1212 asrs r2, r2, #8 8000250: 0209 lsls r1, r1, #8 8000252: d065 beq.n 8000320 <__divsi3+0x104> 8000254: 0b03 lsrs r3, r0, #12 8000256: 428b cmp r3, r1 8000258: d319 bcc.n 800028e <__divsi3+0x72> 800025a: e000 b.n 800025e <__divsi3+0x42> 800025c: 0a09 lsrs r1, r1, #8 800025e: 0bc3 lsrs r3, r0, #15 8000260: 428b cmp r3, r1 8000262: d301 bcc.n 8000268 <__divsi3+0x4c> 8000264: 03cb lsls r3, r1, #15 8000266: 1ac0 subs r0, r0, r3 8000268: 4152 adcs r2, r2 800026a: 0b83 lsrs r3, r0, #14 800026c: 428b cmp r3, r1 800026e: d301 bcc.n 8000274 <__divsi3+0x58> 8000270: 038b lsls r3, r1, #14 8000272: 1ac0 subs r0, r0, r3 8000274: 4152 adcs r2, r2 8000276: 0b43 lsrs r3, r0, #13 8000278: 428b cmp r3, r1 800027a: d301 bcc.n 8000280 <__divsi3+0x64> 800027c: 034b lsls r3, r1, #13 800027e: 1ac0 subs r0, r0, r3 8000280: 4152 adcs r2, r2 8000282: 0b03 lsrs r3, r0, #12 8000284: 428b cmp r3, r1 8000286: d301 bcc.n 800028c <__divsi3+0x70> 8000288: 030b lsls r3, r1, #12 800028a: 1ac0 subs r0, r0, r3 800028c: 4152 adcs r2, r2 800028e: 0ac3 lsrs r3, r0, #11 8000290: 428b cmp r3, r1 8000292: d301 bcc.n 8000298 <__divsi3+0x7c> 8000294: 02cb lsls r3, r1, #11 8000296: 1ac0 subs r0, r0, r3 8000298: 4152 adcs r2, r2 800029a: 0a83 lsrs r3, r0, #10 800029c: 428b cmp r3, r1 800029e: d301 bcc.n 80002a4 <__divsi3+0x88> 80002a0: 028b lsls r3, r1, #10 80002a2: 1ac0 subs r0, r0, r3 80002a4: 4152 adcs r2, r2 80002a6: 0a43 lsrs r3, r0, #9 80002a8: 428b cmp r3, r1 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94> 80002ac: 024b lsls r3, r1, #9 80002ae: 1ac0 subs r0, r0, r3 80002b0: 4152 adcs r2, r2 80002b2: 0a03 lsrs r3, r0, #8 80002b4: 428b cmp r3, r1 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0> 80002b8: 020b lsls r3, r1, #8 80002ba: 1ac0 subs r0, r0, r3 80002bc: 4152 adcs r2, r2 80002be: d2cd bcs.n 800025c <__divsi3+0x40> 80002c0: 09c3 lsrs r3, r0, #7 80002c2: 428b cmp r3, r1 80002c4: d301 bcc.n 80002ca <__divsi3+0xae> 80002c6: 01cb lsls r3, r1, #7 80002c8: 1ac0 subs r0, r0, r3 80002ca: 4152 adcs r2, r2 80002cc: 0983 lsrs r3, r0, #6 80002ce: 428b cmp r3, r1 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba> 80002d2: 018b lsls r3, r1, #6 80002d4: 1ac0 subs r0, r0, r3 80002d6: 4152 adcs r2, r2 80002d8: 0943 lsrs r3, r0, #5 80002da: 428b cmp r3, r1 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6> 80002de: 014b lsls r3, r1, #5 80002e0: 1ac0 subs r0, r0, r3 80002e2: 4152 adcs r2, r2 80002e4: 0903 lsrs r3, r0, #4 80002e6: 428b cmp r3, r1 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2> 80002ea: 010b lsls r3, r1, #4 80002ec: 1ac0 subs r0, r0, r3 80002ee: 4152 adcs r2, r2 80002f0: 08c3 lsrs r3, r0, #3 80002f2: 428b cmp r3, r1 80002f4: d301 bcc.n 80002fa <__divsi3+0xde> 80002f6: 00cb lsls r3, r1, #3 80002f8: 1ac0 subs r0, r0, r3 80002fa: 4152 adcs r2, r2 80002fc: 0883 lsrs r3, r0, #2 80002fe: 428b cmp r3, r1 8000300: d301 bcc.n 8000306 <__divsi3+0xea> 8000302: 008b lsls r3, r1, #2 8000304: 1ac0 subs r0, r0, r3 8000306: 4152 adcs r2, r2 8000308: 0843 lsrs r3, r0, #1 800030a: 428b cmp r3, r1 800030c: d301 bcc.n 8000312 <__divsi3+0xf6> 800030e: 004b lsls r3, r1, #1 8000310: 1ac0 subs r0, r0, r3 8000312: 4152 adcs r2, r2 8000314: 1a41 subs r1, r0, r1 8000316: d200 bcs.n 800031a <__divsi3+0xfe> 8000318: 4601 mov r1, r0 800031a: 4152 adcs r2, r2 800031c: 4610 mov r0, r2 800031e: 4770 bx lr 8000320: e05d b.n 80003de <__divsi3+0x1c2> 8000322: 0fca lsrs r2, r1, #31 8000324: d000 beq.n 8000328 <__divsi3+0x10c> 8000326: 4249 negs r1, r1 8000328: 1003 asrs r3, r0, #32 800032a: d300 bcc.n 800032e <__divsi3+0x112> 800032c: 4240 negs r0, r0 800032e: 4053 eors r3, r2 8000330: 2200 movs r2, #0 8000332: 469c mov ip, r3 8000334: 0903 lsrs r3, r0, #4 8000336: 428b cmp r3, r1 8000338: d32d bcc.n 8000396 <__divsi3+0x17a> 800033a: 0a03 lsrs r3, r0, #8 800033c: 428b cmp r3, r1 800033e: d312 bcc.n 8000366 <__divsi3+0x14a> 8000340: 22fc movs r2, #252 ; 0xfc 8000342: 0189 lsls r1, r1, #6 8000344: ba12 rev r2, r2 8000346: 0a03 lsrs r3, r0, #8 8000348: 428b cmp r3, r1 800034a: d30c bcc.n 8000366 <__divsi3+0x14a> 800034c: 0189 lsls r1, r1, #6 800034e: 1192 asrs r2, r2, #6 8000350: 428b cmp r3, r1 8000352: d308 bcc.n 8000366 <__divsi3+0x14a> 8000354: 0189 lsls r1, r1, #6 8000356: 1192 asrs r2, r2, #6 8000358: 428b cmp r3, r1 800035a: d304 bcc.n 8000366 <__divsi3+0x14a> 800035c: 0189 lsls r1, r1, #6 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba> 8000360: 1192 asrs r2, r2, #6 8000362: e000 b.n 8000366 <__divsi3+0x14a> 8000364: 0989 lsrs r1, r1, #6 8000366: 09c3 lsrs r3, r0, #7 8000368: 428b cmp r3, r1 800036a: d301 bcc.n 8000370 <__divsi3+0x154> 800036c: 01cb lsls r3, r1, #7 800036e: 1ac0 subs r0, r0, r3 8000370: 4152 adcs r2, r2 8000372: 0983 lsrs r3, r0, #6 8000374: 428b cmp r3, r1 8000376: d301 bcc.n 800037c <__divsi3+0x160> 8000378: 018b lsls r3, r1, #6 800037a: 1ac0 subs r0, r0, r3 800037c: 4152 adcs r2, r2 800037e: 0943 lsrs r3, r0, #5 8000380: 428b cmp r3, r1 8000382: d301 bcc.n 8000388 <__divsi3+0x16c> 8000384: 014b lsls r3, r1, #5 8000386: 1ac0 subs r0, r0, r3 8000388: 4152 adcs r2, r2 800038a: 0903 lsrs r3, r0, #4 800038c: 428b cmp r3, r1 800038e: d301 bcc.n 8000394 <__divsi3+0x178> 8000390: 010b lsls r3, r1, #4 8000392: 1ac0 subs r0, r0, r3 8000394: 4152 adcs r2, r2 8000396: 08c3 lsrs r3, r0, #3 8000398: 428b cmp r3, r1 800039a: d301 bcc.n 80003a0 <__divsi3+0x184> 800039c: 00cb lsls r3, r1, #3 800039e: 1ac0 subs r0, r0, r3 80003a0: 4152 adcs r2, r2 80003a2: 0883 lsrs r3, r0, #2 80003a4: 428b cmp r3, r1 80003a6: d301 bcc.n 80003ac <__divsi3+0x190> 80003a8: 008b lsls r3, r1, #2 80003aa: 1ac0 subs r0, r0, r3 80003ac: 4152 adcs r2, r2 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148> 80003b0: 0843 lsrs r3, r0, #1 80003b2: 428b cmp r3, r1 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e> 80003b6: 004b lsls r3, r1, #1 80003b8: 1ac0 subs r0, r0, r3 80003ba: 4152 adcs r2, r2 80003bc: 1a41 subs r1, r0, r1 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6> 80003c0: 4601 mov r1, r0 80003c2: 4663 mov r3, ip 80003c4: 4152 adcs r2, r2 80003c6: 105b asrs r3, r3, #1 80003c8: 4610 mov r0, r2 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4> 80003cc: 4240 negs r0, r0 80003ce: 2b00 cmp r3, #0 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8> 80003d2: 4249 negs r1, r1 80003d4: 4770 bx lr 80003d6: 4663 mov r3, ip 80003d8: 105b asrs r3, r3, #1 80003da: d300 bcc.n 80003de <__divsi3+0x1c2> 80003dc: 4240 negs r0, r0 80003de: b501 push {r0, lr} 80003e0: 2000 movs r0, #0 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0> 80003e6: bd02 pop {r1, pc} 080003e8 <__aeabi_idivmod>: 80003e8: 2900 cmp r1, #0 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2> 80003ec: e716 b.n 800021c <__divsi3> 80003ee: 4770 bx lr 080003f0 <__aeabi_idiv0>: 80003f0: 4770 bx lr 80003f2: 46c0 nop ; (mov r8, r8) 080003f4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003f4: b580 push {r7, lr} 80003f6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80003f8: f000 faac bl 8000954 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80003fc: f000 f809 bl 8000412 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000400: f000 f8e4 bl 80005cc MX_ADC_Init(); 8000404: f000 f856 bl 80004b4 MX_TIM14_Init(); 8000408: f000 f8bc bl 8000584 /* USER CODE BEGIN 2 */ my_code(); 800040c: f003 f804 bl 8003418 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000410: e7fe b.n 8000410 08000412 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000412: b590 push {r4, r7, lr} 8000414: b091 sub sp, #68 ; 0x44 8000416: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000418: 2410 movs r4, #16 800041a: 193b adds r3, r7, r4 800041c: 0018 movs r0, r3 800041e: 2330 movs r3, #48 ; 0x30 8000420: 001a movs r2, r3 8000422: 2100 movs r1, #0 8000424: f003 fd38 bl 8003e98 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000428: 003b movs r3, r7 800042a: 0018 movs r0, r3 800042c: 2310 movs r3, #16 800042e: 001a movs r2, r3 8000430: 2100 movs r1, #0 8000432: f003 fd31 bl 8003e98 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14; 8000436: 0021 movs r1, r4 8000438: 187b adds r3, r7, r1 800043a: 2212 movs r2, #18 800043c: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800043e: 187b adds r3, r7, r1 8000440: 2201 movs r2, #1 8000442: 60da str r2, [r3, #12] RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; 8000444: 187b adds r3, r7, r1 8000446: 2201 movs r2, #1 8000448: 615a str r2, [r3, #20] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800044a: 187b adds r3, r7, r1 800044c: 2210 movs r2, #16 800044e: 611a str r2, [r3, #16] RCC_OscInitStruct.HSI14CalibrationValue = 16; 8000450: 187b adds r3, r7, r1 8000452: 2210 movs r2, #16 8000454: 619a str r2, [r3, #24] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000456: 187b adds r3, r7, r1 8000458: 2202 movs r2, #2 800045a: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 800045c: 187b adds r3, r7, r1 800045e: 2200 movs r2, #0 8000460: 625a str r2, [r3, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; 8000462: 187b adds r3, r7, r1 8000464: 22a0 movs r2, #160 ; 0xa0 8000466: 0392 lsls r2, r2, #14 8000468: 629a str r2, [r3, #40] ; 0x28 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; 800046a: 187b adds r3, r7, r1 800046c: 2200 movs r2, #0 800046e: 62da str r2, [r3, #44] ; 0x2c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000470: 187b adds r3, r7, r1 8000472: 0018 movs r0, r3 8000474: f001 fa68 bl 8001948 8000478: 1e03 subs r3, r0, #0 800047a: d001 beq.n 8000480 { Error_Handler(); 800047c: f000 f976 bl 800076c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000480: 003b movs r3, r7 8000482: 2207 movs r2, #7 8000484: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000486: 003b movs r3, r7 8000488: 2202 movs r2, #2 800048a: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800048c: 003b movs r3, r7 800048e: 2200 movs r2, #0 8000490: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000492: 003b movs r3, r7 8000494: 2200 movs r2, #0 8000496: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000498: 003b movs r3, r7 800049a: 2101 movs r1, #1 800049c: 0018 movs r0, r3 800049e: f001 fd6d bl 8001f7c 80004a2: 1e03 subs r3, r0, #0 80004a4: d001 beq.n 80004aa { Error_Handler(); 80004a6: f000 f961 bl 800076c } } 80004aa: 46c0 nop ; (mov r8, r8) 80004ac: 46bd mov sp, r7 80004ae: b011 add sp, #68 ; 0x44 80004b0: bd90 pop {r4, r7, pc} ... 080004b4 : * @brief ADC Initialization Function * @param None * @retval None */ static void MX_ADC_Init(void) { 80004b4: b580 push {r7, lr} 80004b6: b084 sub sp, #16 80004b8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC_Init 0 */ /* USER CODE END ADC_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80004ba: 1d3b adds r3, r7, #4 80004bc: 0018 movs r0, r3 80004be: 230c movs r3, #12 80004c0: 001a movs r2, r3 80004c2: 2100 movs r1, #0 80004c4: f003 fce8 bl 8003e98 /* USER CODE BEGIN ADC_Init 1 */ /* USER CODE END ADC_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc.Instance = ADC1; 80004c8: 4b2c ldr r3, [pc, #176] ; (800057c ) 80004ca: 4a2d ldr r2, [pc, #180] ; (8000580 ) 80004cc: 601a str r2, [r3, #0] hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80004ce: 4b2b ldr r3, [pc, #172] ; (800057c ) 80004d0: 2200 movs r2, #0 80004d2: 605a str r2, [r3, #4] hadc.Init.Resolution = ADC_RESOLUTION_12B; 80004d4: 4b29 ldr r3, [pc, #164] ; (800057c ) 80004d6: 2200 movs r2, #0 80004d8: 609a str r2, [r3, #8] hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80004da: 4b28 ldr r3, [pc, #160] ; (800057c ) 80004dc: 2200 movs r2, #0 80004de: 60da str r2, [r3, #12] hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; 80004e0: 4b26 ldr r3, [pc, #152] ; (800057c ) 80004e2: 2201 movs r2, #1 80004e4: 611a str r2, [r3, #16] hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80004e6: 4b25 ldr r3, [pc, #148] ; (800057c ) 80004e8: 2204 movs r2, #4 80004ea: 615a str r2, [r3, #20] hadc.Init.LowPowerAutoWait = DISABLE; 80004ec: 4b23 ldr r3, [pc, #140] ; (800057c ) 80004ee: 2200 movs r2, #0 80004f0: 761a strb r2, [r3, #24] hadc.Init.LowPowerAutoPowerOff = DISABLE; 80004f2: 4b22 ldr r3, [pc, #136] ; (800057c ) 80004f4: 2200 movs r2, #0 80004f6: 765a strb r2, [r3, #25] hadc.Init.ContinuousConvMode = DISABLE; 80004f8: 4b20 ldr r3, [pc, #128] ; (800057c ) 80004fa: 2200 movs r2, #0 80004fc: 769a strb r2, [r3, #26] hadc.Init.DiscontinuousConvMode = ENABLE; 80004fe: 4b1f ldr r3, [pc, #124] ; (800057c ) 8000500: 2201 movs r2, #1 8000502: 76da strb r2, [r3, #27] hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000504: 4b1d ldr r3, [pc, #116] ; (800057c ) 8000506: 22c2 movs r2, #194 ; 0xc2 8000508: 32ff adds r2, #255 ; 0xff 800050a: 61da str r2, [r3, #28] hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 800050c: 4b1b ldr r3, [pc, #108] ; (800057c ) 800050e: 2200 movs r2, #0 8000510: 621a str r2, [r3, #32] hadc.Init.DMAContinuousRequests = DISABLE; 8000512: 4b1a ldr r3, [pc, #104] ; (800057c ) 8000514: 2224 movs r2, #36 ; 0x24 8000516: 2100 movs r1, #0 8000518: 5499 strb r1, [r3, r2] hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; 800051a: 4b18 ldr r3, [pc, #96] ; (800057c ) 800051c: 2201 movs r2, #1 800051e: 629a str r2, [r3, #40] ; 0x28 if (HAL_ADC_Init(&hadc) != HAL_OK) 8000520: 4b16 ldr r3, [pc, #88] ; (800057c ) 8000522: 0018 movs r0, r3 8000524: f000 fa9e bl 8000a64 8000528: 1e03 subs r3, r0, #0 800052a: d001 beq.n 8000530 { Error_Handler(); 800052c: f000 f91e bl 800076c } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_0; 8000530: 1d3b adds r3, r7, #4 8000532: 2200 movs r2, #0 8000534: 601a str r2, [r3, #0] sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; 8000536: 1d3b adds r3, r7, #4 8000538: 2280 movs r2, #128 ; 0x80 800053a: 0152 lsls r2, r2, #5 800053c: 605a str r2, [r3, #4] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800053e: 1d3b adds r3, r7, #4 8000540: 2280 movs r2, #128 ; 0x80 8000542: 0552 lsls r2, r2, #21 8000544: 609a str r2, [r3, #8] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000546: 1d3a adds r2, r7, #4 8000548: 4b0c ldr r3, [pc, #48] ; (800057c ) 800054a: 0011 movs r1, r2 800054c: 0018 movs r0, r3 800054e: f000 fd01 bl 8000f54 8000552: 1e03 subs r3, r0, #0 8000554: d001 beq.n 800055a { Error_Handler(); 8000556: f000 f909 bl 800076c } /** Configure for the selected ADC regular channel to be converted. */ sConfig.Channel = ADC_CHANNEL_1; 800055a: 1d3b adds r3, r7, #4 800055c: 2201 movs r2, #1 800055e: 601a str r2, [r3, #0] if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) 8000560: 1d3a adds r2, r7, #4 8000562: 4b06 ldr r3, [pc, #24] ; (800057c ) 8000564: 0011 movs r1, r2 8000566: 0018 movs r0, r3 8000568: f000 fcf4 bl 8000f54 800056c: 1e03 subs r3, r0, #0 800056e: d001 beq.n 8000574 { Error_Handler(); 8000570: f000 f8fc bl 800076c } /* USER CODE BEGIN ADC_Init 2 */ /* USER CODE END ADC_Init 2 */ } 8000574: 46c0 nop ; (mov r8, r8) 8000576: 46bd mov sp, r7 8000578: b004 add sp, #16 800057a: bd80 pop {r7, pc} 800057c: 20000094 .word 0x20000094 8000580: 40012400 .word 0x40012400 08000584 : * @brief TIM14 Initialization Function * @param None * @retval None */ static void MX_TIM14_Init(void) { 8000584: b580 push {r7, lr} 8000586: af00 add r7, sp, #0 /* USER CODE END TIM14_Init 0 */ /* USER CODE BEGIN TIM14_Init 1 */ /* USER CODE END TIM14_Init 1 */ htim14.Instance = TIM14; 8000588: 4b0e ldr r3, [pc, #56] ; (80005c4 ) 800058a: 4a0f ldr r2, [pc, #60] ; (80005c8 ) 800058c: 601a str r2, [r3, #0] htim14.Init.Prescaler = 48-1; 800058e: 4b0d ldr r3, [pc, #52] ; (80005c4 ) 8000590: 222f movs r2, #47 ; 0x2f 8000592: 605a str r2, [r3, #4] htim14.Init.CounterMode = TIM_COUNTERMODE_UP; 8000594: 4b0b ldr r3, [pc, #44] ; (80005c4 ) 8000596: 2200 movs r2, #0 8000598: 609a str r2, [r3, #8] htim14.Init.Period = 100-1; 800059a: 4b0a ldr r3, [pc, #40] ; (80005c4 ) 800059c: 2263 movs r2, #99 ; 0x63 800059e: 60da str r2, [r3, #12] htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80005a0: 4b08 ldr r3, [pc, #32] ; (80005c4 ) 80005a2: 2200 movs r2, #0 80005a4: 611a str r2, [r3, #16] htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80005a6: 4b07 ldr r3, [pc, #28] ; (80005c4 ) 80005a8: 2200 movs r2, #0 80005aa: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim14) != HAL_OK) 80005ac: 4b05 ldr r3, [pc, #20] ; (80005c4 ) 80005ae: 0018 movs r0, r3 80005b0: f001 fe16 bl 80021e0 80005b4: 1e03 subs r3, r0, #0 80005b6: d001 beq.n 80005bc { Error_Handler(); 80005b8: f000 f8d8 bl 800076c } /* USER CODE BEGIN TIM14_Init 2 */ /* USER CODE END TIM14_Init 2 */ } 80005bc: 46c0 nop ; (mov r8, r8) 80005be: 46bd mov sp, r7 80005c0: bd80 pop {r7, pc} 80005c2: 46c0 nop ; (mov r8, r8) 80005c4: 2000004c .word 0x2000004c 80005c8: 40002000 .word 0x40002000 080005cc : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80005cc: b590 push {r4, r7, lr} 80005ce: b089 sub sp, #36 ; 0x24 80005d0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80005d2: 240c movs r4, #12 80005d4: 193b adds r3, r7, r4 80005d6: 0018 movs r0, r3 80005d8: 2314 movs r3, #20 80005da: 001a movs r2, r3 80005dc: 2100 movs r1, #0 80005de: f003 fc5b bl 8003e98 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80005e2: 4b5f ldr r3, [pc, #380] ; (8000760 ) 80005e4: 695a ldr r2, [r3, #20] 80005e6: 4b5e ldr r3, [pc, #376] ; (8000760 ) 80005e8: 2180 movs r1, #128 ; 0x80 80005ea: 03c9 lsls r1, r1, #15 80005ec: 430a orrs r2, r1 80005ee: 615a str r2, [r3, #20] 80005f0: 4b5b ldr r3, [pc, #364] ; (8000760 ) 80005f2: 695a ldr r2, [r3, #20] 80005f4: 2380 movs r3, #128 ; 0x80 80005f6: 03db lsls r3, r3, #15 80005f8: 4013 ands r3, r2 80005fa: 60bb str r3, [r7, #8] 80005fc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80005fe: 4b58 ldr r3, [pc, #352] ; (8000760 ) 8000600: 695a ldr r2, [r3, #20] 8000602: 4b57 ldr r3, [pc, #348] ; (8000760 ) 8000604: 2180 movs r1, #128 ; 0x80 8000606: 0289 lsls r1, r1, #10 8000608: 430a orrs r2, r1 800060a: 615a str r2, [r3, #20] 800060c: 4b54 ldr r3, [pc, #336] ; (8000760 ) 800060e: 695a ldr r2, [r3, #20] 8000610: 2380 movs r3, #128 ; 0x80 8000612: 029b lsls r3, r3, #10 8000614: 4013 ands r3, r2 8000616: 607b str r3, [r7, #4] 8000618: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 800061a: 4b51 ldr r3, [pc, #324] ; (8000760 ) 800061c: 695a ldr r2, [r3, #20] 800061e: 4b50 ldr r3, [pc, #320] ; (8000760 ) 8000620: 2180 movs r1, #128 ; 0x80 8000622: 02c9 lsls r1, r1, #11 8000624: 430a orrs r2, r1 8000626: 615a str r2, [r3, #20] 8000628: 4b4d ldr r3, [pc, #308] ; (8000760 ) 800062a: 695a ldr r2, [r3, #20] 800062c: 2380 movs r3, #128 ; 0x80 800062e: 02db lsls r3, r3, #11 8000630: 4013 ands r3, r2 8000632: 603b str r3, [r7, #0] 8000634: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin 8000636: 23b9 movs r3, #185 ; 0xb9 8000638: 0099 lsls r1, r3, #2 800063a: 2390 movs r3, #144 ; 0x90 800063c: 05db lsls r3, r3, #23 800063e: 2200 movs r2, #0 8000640: 0018 movs r0, r3 8000642: f001 f92a bl 800189a |HC595_SLK2_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(iic_sda_GPIO_Port, iic_sda_Pin, GPIO_PIN_SET); 8000646: 4b47 ldr r3, [pc, #284] ; (8000764 ) 8000648: 2201 movs r2, #1 800064a: 2102 movs r1, #2 800064c: 0018 movs r0, r3 800064e: f001 f924 bl 800189a /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(iic_scl_GPIO_Port, iic_scl_Pin, GPIO_PIN_SET); 8000652: 2380 movs r3, #128 ; 0x80 8000654: 00d9 lsls r1, r3, #3 8000656: 2390 movs r3, #144 ; 0x90 8000658: 05db lsls r3, r3, #23 800065a: 2201 movs r2, #1 800065c: 0018 movs r0, r3 800065e: f001 f91c bl 800189a /*Configure GPIO pins : MOT_IN1_Pin MOT_IN2_Pin */ GPIO_InitStruct.Pin = MOT_IN1_Pin|MOT_IN2_Pin; 8000662: 193b adds r3, r7, r4 8000664: 2203 movs r2, #3 8000666: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000668: 193b adds r3, r7, r4 800066a: 2200 movs r2, #0 800066c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800066e: 193b adds r3, r7, r4 8000670: 2202 movs r2, #2 8000672: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8000674: 193b adds r3, r7, r4 8000676: 4a3c ldr r2, [pc, #240] ; (8000768 ) 8000678: 0019 movs r1, r3 800067a: 0010 movs r0, r2 800067c: f000 ff80 bl 8001580 /*Configure GPIO pins : U_T_Pin HC595_DLK_Pin HC595_SLK_Pin HC595_RLK_Pin HC595_SLK2_Pin */ GPIO_InitStruct.Pin = U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin 8000680: 0021 movs r1, r4 8000682: 187b adds r3, r7, r1 8000684: 22b9 movs r2, #185 ; 0xb9 8000686: 0092 lsls r2, r2, #2 8000688: 601a str r2, [r3, #0] |HC595_SLK2_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800068a: 000c movs r4, r1 800068c: 193b adds r3, r7, r4 800068e: 2201 movs r2, #1 8000690: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 8000692: 193b adds r3, r7, r4 8000694: 2202 movs r2, #2 8000696: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000698: 193b adds r3, r7, r4 800069a: 2203 movs r2, #3 800069c: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800069e: 193a adds r2, r7, r4 80006a0: 2390 movs r3, #144 ; 0x90 80006a2: 05db lsls r3, r3, #23 80006a4: 0011 movs r1, r2 80006a6: 0018 movs r0, r3 80006a8: f000 ff6a bl 8001580 /*Configure GPIO pin : infeaed_Pin */ GPIO_InitStruct.Pin = infeaed_Pin; 80006ac: 193b adds r3, r7, r4 80006ae: 2208 movs r2, #8 80006b0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80006b2: 193b adds r3, r7, r4 80006b4: 22c4 movs r2, #196 ; 0xc4 80006b6: 0392 lsls r2, r2, #14 80006b8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006ba: 193b adds r3, r7, r4 80006bc: 2201 movs r2, #1 80006be: 609a str r2, [r3, #8] HAL_GPIO_Init(infeaed_GPIO_Port, &GPIO_InitStruct); 80006c0: 193a adds r2, r7, r4 80006c2: 2390 movs r3, #144 ; 0x90 80006c4: 05db lsls r3, r3, #23 80006c6: 0011 movs r1, r2 80006c8: 0018 movs r0, r3 80006ca: f000 ff59 bl 8001580 /*Configure GPIO pin : I_R_Pin */ GPIO_InitStruct.Pin = I_R_Pin; 80006ce: 193b adds r3, r7, r4 80006d0: 2210 movs r2, #16 80006d2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 193b adds r3, r7, r4 80006d6: 2200 movs r2, #0 80006d8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006da: 193b adds r3, r7, r4 80006dc: 2202 movs r2, #2 80006de: 609a str r2, [r3, #8] HAL_GPIO_Init(I_R_GPIO_Port, &GPIO_InitStruct); 80006e0: 193a adds r2, r7, r4 80006e2: 2390 movs r3, #144 ; 0x90 80006e4: 05db lsls r3, r3, #23 80006e6: 0011 movs r1, r2 80006e8: 0018 movs r0, r3 80006ea: f000 ff49 bl 8001580 /*Configure GPIO pin : iic_sda_Pin */ GPIO_InitStruct.Pin = iic_sda_Pin; 80006ee: 193b adds r3, r7, r4 80006f0: 2202 movs r2, #2 80006f2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006f4: 193b adds r3, r7, r4 80006f6: 2201 movs r2, #1 80006f8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006fa: 193b adds r3, r7, r4 80006fc: 2201 movs r2, #1 80006fe: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000700: 193b adds r3, r7, r4 8000702: 2203 movs r2, #3 8000704: 60da str r2, [r3, #12] HAL_GPIO_Init(iic_sda_GPIO_Port, &GPIO_InitStruct); 8000706: 193b adds r3, r7, r4 8000708: 4a16 ldr r2, [pc, #88] ; (8000764 ) 800070a: 0019 movs r1, r3 800070c: 0010 movs r0, r2 800070e: f000 ff37 bl 8001580 /*Configure GPIO pin : iic_scl_Pin */ GPIO_InitStruct.Pin = iic_scl_Pin; 8000712: 0021 movs r1, r4 8000714: 187b adds r3, r7, r1 8000716: 2280 movs r2, #128 ; 0x80 8000718: 00d2 lsls r2, r2, #3 800071a: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800071c: 187b adds r3, r7, r1 800071e: 2201 movs r2, #1 8000720: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000722: 187b adds r3, r7, r1 8000724: 2201 movs r2, #1 8000726: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000728: 187b adds r3, r7, r1 800072a: 2203 movs r2, #3 800072c: 60da str r2, [r3, #12] HAL_GPIO_Init(iic_scl_GPIO_Port, &GPIO_InitStruct); 800072e: 187a adds r2, r7, r1 8000730: 2390 movs r3, #144 ; 0x90 8000732: 05db lsls r3, r3, #23 8000734: 0011 movs r1, r2 8000736: 0018 movs r0, r3 8000738: f000 ff22 bl 8001580 /**/ HAL_I2CEx_EnableFastModePlus(SYSCFG_CFGR1_I2C_FMP_PA10); 800073c: 2380 movs r3, #128 ; 0x80 800073e: 041b lsls r3, r3, #16 8000740: 0018 movs r0, r3 8000742: f001 f8e3 bl 800190c /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI2_3_IRQn, 0, 0); 8000746: 2200 movs r2, #0 8000748: 2100 movs r1, #0 800074a: 2006 movs r0, #6 800074c: f000 fee6 bl 800151c HAL_NVIC_EnableIRQ(EXTI2_3_IRQn); 8000750: 2006 movs r0, #6 8000752: f000 fef8 bl 8001546 } 8000756: 46c0 nop ; (mov r8, r8) 8000758: 46bd mov sp, r7 800075a: b009 add sp, #36 ; 0x24 800075c: bd90 pop {r4, r7, pc} 800075e: 46c0 nop ; (mov r8, r8) 8000760: 40021000 .word 0x40021000 8000764: 48000400 .word 0x48000400 8000768: 48001400 .word 0x48001400 0800076c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800076c: b580 push {r7, lr} 800076e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000770: b672 cpsid i } 8000772: 46c0 nop ; (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000774: e7fe b.n 8000774 ... 08000778 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000778: b580 push {r7, lr} 800077a: b082 sub sp, #8 800077c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800077e: 4b0f ldr r3, [pc, #60] ; (80007bc ) 8000780: 699a ldr r2, [r3, #24] 8000782: 4b0e ldr r3, [pc, #56] ; (80007bc ) 8000784: 2101 movs r1, #1 8000786: 430a orrs r2, r1 8000788: 619a str r2, [r3, #24] 800078a: 4b0c ldr r3, [pc, #48] ; (80007bc ) 800078c: 699b ldr r3, [r3, #24] 800078e: 2201 movs r2, #1 8000790: 4013 ands r3, r2 8000792: 607b str r3, [r7, #4] 8000794: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000796: 4b09 ldr r3, [pc, #36] ; (80007bc ) 8000798: 69da ldr r2, [r3, #28] 800079a: 4b08 ldr r3, [pc, #32] ; (80007bc ) 800079c: 2180 movs r1, #128 ; 0x80 800079e: 0549 lsls r1, r1, #21 80007a0: 430a orrs r2, r1 80007a2: 61da str r2, [r3, #28] 80007a4: 4b05 ldr r3, [pc, #20] ; (80007bc ) 80007a6: 69da ldr r2, [r3, #28] 80007a8: 2380 movs r3, #128 ; 0x80 80007aa: 055b lsls r3, r3, #21 80007ac: 4013 ands r3, r2 80007ae: 603b str r3, [r7, #0] 80007b0: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80007b2: 46c0 nop ; (mov r8, r8) 80007b4: 46bd mov sp, r7 80007b6: b002 add sp, #8 80007b8: bd80 pop {r7, pc} 80007ba: 46c0 nop ; (mov r8, r8) 80007bc: 40021000 .word 0x40021000 080007c0 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 80007c0: b590 push {r4, r7, lr} 80007c2: b08b sub sp, #44 ; 0x2c 80007c4: af00 add r7, sp, #0 80007c6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007c8: 2414 movs r4, #20 80007ca: 193b adds r3, r7, r4 80007cc: 0018 movs r0, r3 80007ce: 2314 movs r3, #20 80007d0: 001a movs r2, r3 80007d2: 2100 movs r1, #0 80007d4: f003 fb60 bl 8003e98 if(hadc->Instance==ADC1) 80007d8: 687b ldr r3, [r7, #4] 80007da: 681b ldr r3, [r3, #0] 80007dc: 4a19 ldr r2, [pc, #100] ; (8000844 ) 80007de: 4293 cmp r3, r2 80007e0: d12b bne.n 800083a { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80007e2: 4b19 ldr r3, [pc, #100] ; (8000848 ) 80007e4: 699a ldr r2, [r3, #24] 80007e6: 4b18 ldr r3, [pc, #96] ; (8000848 ) 80007e8: 2180 movs r1, #128 ; 0x80 80007ea: 0089 lsls r1, r1, #2 80007ec: 430a orrs r2, r1 80007ee: 619a str r2, [r3, #24] 80007f0: 4b15 ldr r3, [pc, #84] ; (8000848 ) 80007f2: 699a ldr r2, [r3, #24] 80007f4: 2380 movs r3, #128 ; 0x80 80007f6: 009b lsls r3, r3, #2 80007f8: 4013 ands r3, r2 80007fa: 613b str r3, [r7, #16] 80007fc: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80007fe: 4b12 ldr r3, [pc, #72] ; (8000848 ) 8000800: 695a ldr r2, [r3, #20] 8000802: 4b11 ldr r3, [pc, #68] ; (8000848 ) 8000804: 2180 movs r1, #128 ; 0x80 8000806: 0289 lsls r1, r1, #10 8000808: 430a orrs r2, r1 800080a: 615a str r2, [r3, #20] 800080c: 4b0e ldr r3, [pc, #56] ; (8000848 ) 800080e: 695a ldr r2, [r3, #20] 8000810: 2380 movs r3, #128 ; 0x80 8000812: 029b lsls r3, r3, #10 8000814: 4013 ands r3, r2 8000816: 60fb str r3, [r7, #12] 8000818: 68fb ldr r3, [r7, #12] /**ADC GPIO Configuration PA0 ------> ADC_IN0 PA1 ------> ADC_IN1 */ GPIO_InitStruct.Pin = ADC_CH0_Pin|ADC_CH1_Pin; 800081a: 193b adds r3, r7, r4 800081c: 2203 movs r2, #3 800081e: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000820: 193b adds r3, r7, r4 8000822: 2203 movs r2, #3 8000824: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000826: 193b adds r3, r7, r4 8000828: 2200 movs r2, #0 800082a: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800082c: 193a adds r2, r7, r4 800082e: 2390 movs r3, #144 ; 0x90 8000830: 05db lsls r3, r3, #23 8000832: 0011 movs r1, r2 8000834: 0018 movs r0, r3 8000836: f000 fea3 bl 8001580 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 800083a: 46c0 nop ; (mov r8, r8) 800083c: 46bd mov sp, r7 800083e: b00b add sp, #44 ; 0x2c 8000840: bd90 pop {r4, r7, pc} 8000842: 46c0 nop ; (mov r8, r8) 8000844: 40012400 .word 0x40012400 8000848: 40021000 .word 0x40021000 0800084c : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 800084c: b580 push {r7, lr} 800084e: b084 sub sp, #16 8000850: af00 add r7, sp, #0 8000852: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM14) 8000854: 687b ldr r3, [r7, #4] 8000856: 681b ldr r3, [r3, #0] 8000858: 4a0e ldr r2, [pc, #56] ; (8000894 ) 800085a: 4293 cmp r3, r2 800085c: d115 bne.n 800088a { /* USER CODE BEGIN TIM14_MspInit 0 */ /* USER CODE END TIM14_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM14_CLK_ENABLE(); 800085e: 4b0e ldr r3, [pc, #56] ; (8000898 ) 8000860: 69da ldr r2, [r3, #28] 8000862: 4b0d ldr r3, [pc, #52] ; (8000898 ) 8000864: 2180 movs r1, #128 ; 0x80 8000866: 0049 lsls r1, r1, #1 8000868: 430a orrs r2, r1 800086a: 61da str r2, [r3, #28] 800086c: 4b0a ldr r3, [pc, #40] ; (8000898 ) 800086e: 69da ldr r2, [r3, #28] 8000870: 2380 movs r3, #128 ; 0x80 8000872: 005b lsls r3, r3, #1 8000874: 4013 ands r3, r2 8000876: 60fb str r3, [r7, #12] 8000878: 68fb ldr r3, [r7, #12] /* TIM14 interrupt Init */ HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0); 800087a: 2200 movs r2, #0 800087c: 2100 movs r1, #0 800087e: 2013 movs r0, #19 8000880: f000 fe4c bl 800151c HAL_NVIC_EnableIRQ(TIM14_IRQn); 8000884: 2013 movs r0, #19 8000886: f000 fe5e bl 8001546 /* USER CODE BEGIN TIM14_MspInit 1 */ /* USER CODE END TIM14_MspInit 1 */ } } 800088a: 46c0 nop ; (mov r8, r8) 800088c: 46bd mov sp, r7 800088e: b004 add sp, #16 8000890: bd80 pop {r7, pc} 8000892: 46c0 nop ; (mov r8, r8) 8000894: 40002000 .word 0x40002000 8000898: 40021000 .word 0x40021000 0800089c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800089c: b580 push {r7, lr} 800089e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80008a0: e7fe b.n 80008a0 080008a2 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80008a2: b580 push {r7, lr} 80008a4: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80008a6: e7fe b.n 80008a6 080008a8 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80008a8: b580 push {r7, lr} 80008aa: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 80008ac: 46c0 nop ; (mov r8, r8) 80008ae: 46bd mov sp, r7 80008b0: bd80 pop {r7, pc} 080008b2 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80008b2: b580 push {r7, lr} 80008b4: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80008b6: 46c0 nop ; (mov r8, r8) 80008b8: 46bd mov sp, r7 80008ba: bd80 pop {r7, pc} 080008bc : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80008bc: b580 push {r7, lr} 80008be: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80008c0: f000 f890 bl 80009e4 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80008c4: 46c0 nop ; (mov r8, r8) 80008c6: 46bd mov sp, r7 80008c8: bd80 pop {r7, pc} 080008ca : /** * @brief This function handles EXTI line 2 and 3 interrupts. */ void EXTI2_3_IRQHandler(void) { 80008ca: b580 push {r7, lr} 80008cc: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI2_3_IRQn 0 */ /* USER CODE END EXTI2_3_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); 80008ce: 2008 movs r0, #8 80008d0: f001 f800 bl 80018d4 /* USER CODE BEGIN EXTI2_3_IRQn 1 */ /* USER CODE END EXTI2_3_IRQn 1 */ } 80008d4: 46c0 nop ; (mov r8, r8) 80008d6: 46bd mov sp, r7 80008d8: bd80 pop {r7, pc} ... 080008dc : /** * @brief This function handles TIM14 global interrupt. */ void TIM14_IRQHandler(void) { 80008dc: b580 push {r7, lr} 80008de: af00 add r7, sp, #0 /* USER CODE BEGIN TIM14_IRQn 0 */ /* USER CODE END TIM14_IRQn 0 */ HAL_TIM_IRQHandler(&htim14); 80008e0: 4b03 ldr r3, [pc, #12] ; (80008f0 ) 80008e2: 0018 movs r0, r3 80008e4: f001 fd12 bl 800230c /* USER CODE BEGIN TIM14_IRQn 1 */ /* USER CODE END TIM14_IRQn 1 */ } 80008e8: 46c0 nop ; (mov r8, r8) 80008ea: 46bd mov sp, r7 80008ec: bd80 pop {r7, pc} 80008ee: 46c0 nop ; (mov r8, r8) 80008f0: 2000004c .word 0x2000004c 080008f4 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 80008f4: b580 push {r7, lr} 80008f6: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 80008f8: 46c0 nop ; (mov r8, r8) 80008fa: 46bd mov sp, r7 80008fc: bd80 pop {r7, pc} ... 08000900 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000900: 480d ldr r0, [pc, #52] ; (8000938 ) mov sp, r0 /* set stack pointer */ 8000902: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000904: 480d ldr r0, [pc, #52] ; (800093c ) ldr r1, =_edata 8000906: 490e ldr r1, [pc, #56] ; (8000940 ) ldr r2, =_sidata 8000908: 4a0e ldr r2, [pc, #56] ; (8000944 ) movs r3, #0 800090a: 2300 movs r3, #0 b LoopCopyDataInit 800090c: e002 b.n 8000914 0800090e : CopyDataInit: ldr r4, [r2, r3] 800090e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000910: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000912: 3304 adds r3, #4 08000914 : LoopCopyDataInit: adds r4, r0, r3 8000914: 18c4 adds r4, r0, r3 cmp r4, r1 8000916: 428c cmp r4, r1 bcc CopyDataInit 8000918: d3f9 bcc.n 800090e /* Zero fill the bss segment. */ ldr r2, =_sbss 800091a: 4a0b ldr r2, [pc, #44] ; (8000948 ) ldr r4, =_ebss 800091c: 4c0b ldr r4, [pc, #44] ; (800094c ) movs r3, #0 800091e: 2300 movs r3, #0 b LoopFillZerobss 8000920: e001 b.n 8000926 08000922 : FillZerobss: str r3, [r2] 8000922: 6013 str r3, [r2, #0] adds r2, r2, #4 8000924: 3204 adds r2, #4 08000926 : LoopFillZerobss: cmp r2, r4 8000926: 42a2 cmp r2, r4 bcc FillZerobss 8000928: d3fb bcc.n 8000922 /* Call the clock system intitialization function.*/ bl SystemInit 800092a: f7ff ffe3 bl 80008f4 /* Call static constructors */ bl __libc_init_array 800092e: f003 fa8f bl 8003e50 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000932: f7ff fd5f bl 80003f4
08000936 : LoopForever: b LoopForever 8000936: e7fe b.n 8000936 ldr r0, =_estack 8000938: 20001000 .word 0x20001000 ldr r0, =_sdata 800093c: 20000000 .word 0x20000000 ldr r1, =_edata 8000940: 2000000c .word 0x2000000c ldr r2, =_sidata 8000944: 08003f20 .word 0x08003f20 ldr r2, =_sbss 8000948: 2000000c .word 0x2000000c ldr r4, =_ebss 800094c: 20000150 .word 0x20000150 08000950 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000950: e7fe b.n 8000950 ... 08000954 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000954: b580 push {r7, lr} 8000956: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000958: 4b07 ldr r3, [pc, #28] ; (8000978 ) 800095a: 681a ldr r2, [r3, #0] 800095c: 4b06 ldr r3, [pc, #24] ; (8000978 ) 800095e: 2110 movs r1, #16 8000960: 430a orrs r2, r1 8000962: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000964: 2003 movs r0, #3 8000966: f000 f809 bl 800097c /* Init the low level hardware */ HAL_MspInit(); 800096a: f7ff ff05 bl 8000778 /* Return function status */ return HAL_OK; 800096e: 2300 movs r3, #0 } 8000970: 0018 movs r0, r3 8000972: 46bd mov sp, r7 8000974: bd80 pop {r7, pc} 8000976: 46c0 nop ; (mov r8, r8) 8000978: 40022000 .word 0x40022000 0800097c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800097c: b590 push {r4, r7, lr} 800097e: b083 sub sp, #12 8000980: af00 add r7, sp, #0 8000982: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000984: 4b14 ldr r3, [pc, #80] ; (80009d8 ) 8000986: 681c ldr r4, [r3, #0] 8000988: 4b14 ldr r3, [pc, #80] ; (80009dc ) 800098a: 781b ldrb r3, [r3, #0] 800098c: 0019 movs r1, r3 800098e: 23fa movs r3, #250 ; 0xfa 8000990: 0098 lsls r0, r3, #2 8000992: f7ff fbb9 bl 8000108 <__udivsi3> 8000996: 0003 movs r3, r0 8000998: 0019 movs r1, r3 800099a: 0020 movs r0, r4 800099c: f7ff fbb4 bl 8000108 <__udivsi3> 80009a0: 0003 movs r3, r0 80009a2: 0018 movs r0, r3 80009a4: f000 fddf bl 8001566 80009a8: 1e03 subs r3, r0, #0 80009aa: d001 beq.n 80009b0 { return HAL_ERROR; 80009ac: 2301 movs r3, #1 80009ae: e00f b.n 80009d0 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80009b0: 687b ldr r3, [r7, #4] 80009b2: 2b03 cmp r3, #3 80009b4: d80b bhi.n 80009ce { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80009b6: 6879 ldr r1, [r7, #4] 80009b8: 2301 movs r3, #1 80009ba: 425b negs r3, r3 80009bc: 2200 movs r2, #0 80009be: 0018 movs r0, r3 80009c0: f000 fdac bl 800151c uwTickPrio = TickPriority; 80009c4: 4b06 ldr r3, [pc, #24] ; (80009e0 ) 80009c6: 687a ldr r2, [r7, #4] 80009c8: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80009ca: 2300 movs r3, #0 80009cc: e000 b.n 80009d0 return HAL_ERROR; 80009ce: 2301 movs r3, #1 } 80009d0: 0018 movs r0, r3 80009d2: 46bd mov sp, r7 80009d4: b003 add sp, #12 80009d6: bd90 pop {r4, r7, pc} 80009d8: 20000000 .word 0x20000000 80009dc: 20000008 .word 0x20000008 80009e0: 20000004 .word 0x20000004 080009e4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80009e4: b580 push {r7, lr} 80009e6: af00 add r7, sp, #0 uwTick += uwTickFreq; 80009e8: 4b05 ldr r3, [pc, #20] ; (8000a00 ) 80009ea: 781b ldrb r3, [r3, #0] 80009ec: 001a movs r2, r3 80009ee: 4b05 ldr r3, [pc, #20] ; (8000a04 ) 80009f0: 681b ldr r3, [r3, #0] 80009f2: 18d2 adds r2, r2, r3 80009f4: 4b03 ldr r3, [pc, #12] ; (8000a04 ) 80009f6: 601a str r2, [r3, #0] } 80009f8: 46c0 nop ; (mov r8, r8) 80009fa: 46bd mov sp, r7 80009fc: bd80 pop {r7, pc} 80009fe: 46c0 nop ; (mov r8, r8) 8000a00: 20000008 .word 0x20000008 8000a04: 200000d4 .word 0x200000d4 08000a08 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000a08: b580 push {r7, lr} 8000a0a: af00 add r7, sp, #0 return uwTick; 8000a0c: 4b02 ldr r3, [pc, #8] ; (8000a18 ) 8000a0e: 681b ldr r3, [r3, #0] } 8000a10: 0018 movs r0, r3 8000a12: 46bd mov sp, r7 8000a14: bd80 pop {r7, pc} 8000a16: 46c0 nop ; (mov r8, r8) 8000a18: 200000d4 .word 0x200000d4 08000a1c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000a1c: b580 push {r7, lr} 8000a1e: b084 sub sp, #16 8000a20: af00 add r7, sp, #0 8000a22: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000a24: f7ff fff0 bl 8000a08 8000a28: 0003 movs r3, r0 8000a2a: 60bb str r3, [r7, #8] uint32_t wait = Delay; 8000a2c: 687b ldr r3, [r7, #4] 8000a2e: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000a30: 68fb ldr r3, [r7, #12] 8000a32: 3301 adds r3, #1 8000a34: d005 beq.n 8000a42 { wait += (uint32_t)(uwTickFreq); 8000a36: 4b0a ldr r3, [pc, #40] ; (8000a60 ) 8000a38: 781b ldrb r3, [r3, #0] 8000a3a: 001a movs r2, r3 8000a3c: 68fb ldr r3, [r7, #12] 8000a3e: 189b adds r3, r3, r2 8000a40: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8000a42: 46c0 nop ; (mov r8, r8) 8000a44: f7ff ffe0 bl 8000a08 8000a48: 0002 movs r2, r0 8000a4a: 68bb ldr r3, [r7, #8] 8000a4c: 1ad3 subs r3, r2, r3 8000a4e: 68fa ldr r2, [r7, #12] 8000a50: 429a cmp r2, r3 8000a52: d8f7 bhi.n 8000a44 { } } 8000a54: 46c0 nop ; (mov r8, r8) 8000a56: 46c0 nop ; (mov r8, r8) 8000a58: 46bd mov sp, r7 8000a5a: b004 add sp, #16 8000a5c: bd80 pop {r7, pc} 8000a5e: 46c0 nop ; (mov r8, r8) 8000a60: 20000008 .word 0x20000008 08000a64 : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8000a64: b580 push {r7, lr} 8000a66: b084 sub sp, #16 8000a68: af00 add r7, sp, #0 8000a6a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000a6c: 230f movs r3, #15 8000a6e: 18fb adds r3, r7, r3 8000a70: 2200 movs r2, #0 8000a72: 701a strb r2, [r3, #0] uint32_t tmpCFGR1 = 0U; 8000a74: 2300 movs r3, #0 8000a76: 60bb str r3, [r7, #8] /* Check ADC handle */ if(hadc == NULL) 8000a78: 687b ldr r3, [r7, #4] 8000a7a: 2b00 cmp r3, #0 8000a7c: d101 bne.n 8000a82 { return HAL_ERROR; 8000a7e: 2301 movs r3, #1 8000a80: e125 b.n 8000cce /* Refer to header of this file for more details on clock enabling procedure*/ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) 8000a82: 687b ldr r3, [r7, #4] 8000a84: 6b9b ldr r3, [r3, #56] ; 0x38 8000a86: 2b00 cmp r3, #0 8000a88: d10a bne.n 8000aa0 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8000a8a: 687b ldr r3, [r7, #4] 8000a8c: 2200 movs r2, #0 8000a8e: 63da str r2, [r3, #60] ; 0x3c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8000a90: 687b ldr r3, [r7, #4] 8000a92: 2234 movs r2, #52 ; 0x34 8000a94: 2100 movs r1, #0 8000a96: 5499 strb r1, [r3, r2] /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8000a98: 687b ldr r3, [r7, #4] 8000a9a: 0018 movs r0, r3 8000a9c: f7ff fe90 bl 80007c0 /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ /* and if there is no conversion on going on regular group (ADC can be */ /* enabled anyway, in case of call of this function to update a parameter */ /* on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8000aa0: 687b ldr r3, [r7, #4] 8000aa2: 6b9b ldr r3, [r3, #56] ; 0x38 8000aa4: 2210 movs r2, #16 8000aa6: 4013 ands r3, r2 8000aa8: d000 beq.n 8000aac 8000aaa: e103 b.n 8000cb4 8000aac: 230f movs r3, #15 8000aae: 18fb adds r3, r7, r3 8000ab0: 781b ldrb r3, [r3, #0] 8000ab2: 2b00 cmp r3, #0 8000ab4: d000 beq.n 8000ab8 8000ab6: e0fd b.n 8000cb4 (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 8000ab8: 687b ldr r3, [r7, #4] 8000aba: 681b ldr r3, [r3, #0] 8000abc: 689b ldr r3, [r3, #8] 8000abe: 2204 movs r2, #4 8000ac0: 4013 ands r3, r2 (tmp_hal_status == HAL_OK) && 8000ac2: d000 beq.n 8000ac6 8000ac4: e0f6 b.n 8000cb4 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000ac6: 687b ldr r3, [r7, #4] 8000ac8: 6b9b ldr r3, [r3, #56] ; 0x38 8000aca: 4a83 ldr r2, [pc, #524] ; (8000cd8 ) 8000acc: 4013 ands r3, r2 8000ace: 2202 movs r2, #2 8000ad0: 431a orrs r2, r3 8000ad2: 687b ldr r3, [r7, #4] 8000ad4: 639a str r2, [r3, #56] ; 0x38 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - ADC clock mode */ /* - ADC clock prescaler */ /* - ADC resolution */ if (ADC_IS_ENABLE(hadc) == RESET) 8000ad6: 687b ldr r3, [r7, #4] 8000ad8: 681b ldr r3, [r3, #0] 8000ada: 689b ldr r3, [r3, #8] 8000adc: 2203 movs r2, #3 8000ade: 4013 ands r3, r2 8000ae0: 2b01 cmp r3, #1 8000ae2: d112 bne.n 8000b0a 8000ae4: 687b ldr r3, [r7, #4] 8000ae6: 681b ldr r3, [r3, #0] 8000ae8: 681b ldr r3, [r3, #0] 8000aea: 2201 movs r2, #1 8000aec: 4013 ands r3, r2 8000aee: 2b01 cmp r3, #1 8000af0: d009 beq.n 8000b06 8000af2: 687b ldr r3, [r7, #4] 8000af4: 681b ldr r3, [r3, #0] 8000af6: 68da ldr r2, [r3, #12] 8000af8: 2380 movs r3, #128 ; 0x80 8000afa: 021b lsls r3, r3, #8 8000afc: 401a ands r2, r3 8000afe: 2380 movs r3, #128 ; 0x80 8000b00: 021b lsls r3, r3, #8 8000b02: 429a cmp r2, r3 8000b04: d101 bne.n 8000b0a 8000b06: 2301 movs r3, #1 8000b08: e000 b.n 8000b0c 8000b0a: 2300 movs r3, #0 8000b0c: 2b00 cmp r3, #0 8000b0e: d116 bne.n 8000b3e /* parameters): */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ MODIFY_REG(hadc->Instance->CFGR1, 8000b10: 687b ldr r3, [r7, #4] 8000b12: 681b ldr r3, [r3, #0] 8000b14: 68db ldr r3, [r3, #12] 8000b16: 2218 movs r2, #24 8000b18: 4393 bics r3, r2 8000b1a: 0019 movs r1, r3 8000b1c: 687b ldr r3, [r7, #4] 8000b1e: 689a ldr r2, [r3, #8] 8000b20: 687b ldr r3, [r7, #4] 8000b22: 681b ldr r3, [r3, #0] 8000b24: 430a orrs r2, r1 8000b26: 60da str r2, [r3, #12] ADC_CFGR1_RES , hadc->Init.Resolution ); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler */ MODIFY_REG(hadc->Instance->CFGR2 , 8000b28: 687b ldr r3, [r7, #4] 8000b2a: 681b ldr r3, [r3, #0] 8000b2c: 691b ldr r3, [r3, #16] 8000b2e: 009b lsls r3, r3, #2 8000b30: 0899 lsrs r1, r3, #2 8000b32: 687b ldr r3, [r7, #4] 8000b34: 685a ldr r2, [r3, #4] 8000b36: 687b ldr r3, [r7, #4] 8000b38: 681b ldr r3, [r3, #0] 8000b3a: 430a orrs r2, r1 8000b3c: 611a str r2, [r3, #16] /* - external trigger polarity */ /* - data alignment */ /* - resolution */ /* - scan direction */ /* - DMA continuous request */ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | 8000b3e: 687b ldr r3, [r7, #4] 8000b40: 681b ldr r3, [r3, #0] 8000b42: 68da ldr r2, [r3, #12] 8000b44: 687b ldr r3, [r7, #4] 8000b46: 681b ldr r3, [r3, #0] 8000b48: 4964 ldr r1, [pc, #400] ; (8000cdc ) 8000b4a: 400a ands r2, r1 8000b4c: 60da str r2, [r3, #12] ADC_CFGR1_EXTEN | ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG ); tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b4e: 687b ldr r3, [r7, #4] 8000b50: 7e1b ldrb r3, [r3, #24] 8000b52: 039a lsls r2, r3, #14 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b54: 687b ldr r3, [r7, #4] 8000b56: 7e5b ldrb r3, [r3, #25] 8000b58: 03db lsls r3, r3, #15 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b5a: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b5c: 687b ldr r3, [r7, #4] 8000b5e: 7e9b ldrb r3, [r3, #26] 8000b60: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | 8000b62: 431a orrs r2, r3 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b64: 687b ldr r3, [r7, #4] 8000b66: 6a9b ldr r3, [r3, #40] ; 0x28 8000b68: 2b01 cmp r3, #1 8000b6a: d002 beq.n 8000b72 8000b6c: 2380 movs r3, #128 ; 0x80 8000b6e: 015b lsls r3, r3, #5 8000b70: e000 b.n 8000b74 8000b72: 2300 movs r3, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8000b74: 431a orrs r2, r3 hadc->Init.DataAlign | 8000b76: 687b ldr r3, [r7, #4] 8000b78: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | 8000b7a: 431a orrs r2, r3 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b7c: 687b ldr r3, [r7, #4] 8000b7e: 691b ldr r3, [r3, #16] 8000b80: 2b02 cmp r3, #2 8000b82: d101 bne.n 8000b88 8000b84: 2304 movs r3, #4 8000b86: e000 b.n 8000b8a 8000b88: 2300 movs r3, #0 hadc->Init.DataAlign | 8000b8a: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); 8000b8c: 687b ldr r3, [r7, #4] 8000b8e: 2124 movs r1, #36 ; 0x24 8000b90: 5c5b ldrb r3, [r3, r1] 8000b92: 005b lsls r3, r3, #1 ADC_SCANDIR(hadc->Init.ScanConvMode) | 8000b94: 4313 orrs r3, r2 tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8000b96: 68ba ldr r2, [r7, #8] 8000b98: 4313 orrs r3, r2 8000b9a: 60bb str r3, [r7, #8] /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8000b9c: 687b ldr r3, [r7, #4] 8000b9e: 7edb ldrb r3, [r3, #27] 8000ba0: 2b01 cmp r3, #1 8000ba2: d115 bne.n 8000bd0 { if (hadc->Init.ContinuousConvMode == DISABLE) 8000ba4: 687b ldr r3, [r7, #4] 8000ba6: 7e9b ldrb r3, [r3, #26] 8000ba8: 2b00 cmp r3, #0 8000baa: d105 bne.n 8000bb8 { /* Enable the selected ADC group regular discontinuous mode */ tmpCFGR1 |= ADC_CFGR1_DISCEN; 8000bac: 68bb ldr r3, [r7, #8] 8000bae: 2280 movs r2, #128 ; 0x80 8000bb0: 0252 lsls r2, r2, #9 8000bb2: 4313 orrs r3, r2 8000bb4: 60bb str r3, [r7, #8] 8000bb6: e00b b.n 8000bd0 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000bb8: 687b ldr r3, [r7, #4] 8000bba: 6b9b ldr r3, [r3, #56] ; 0x38 8000bbc: 2220 movs r2, #32 8000bbe: 431a orrs r2, r3 8000bc0: 687b ldr r3, [r7, #4] 8000bc2: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000bc4: 687b ldr r3, [r7, #4] 8000bc6: 6bdb ldr r3, [r3, #60] ; 0x3c 8000bc8: 2201 movs r2, #1 8000bca: 431a orrs r2, r3 8000bcc: 687b ldr r3, [r7, #4] 8000bce: 63da str r2, [r3, #60] ; 0x3c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8000bd0: 687b ldr r3, [r7, #4] 8000bd2: 69da ldr r2, [r3, #28] 8000bd4: 23c2 movs r3, #194 ; 0xc2 8000bd6: 33ff adds r3, #255 ; 0xff 8000bd8: 429a cmp r2, r3 8000bda: d007 beq.n 8000bec { tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000bdc: 687b ldr r3, [r7, #4] 8000bde: 69da ldr r2, [r3, #28] hadc->Init.ExternalTrigConvEdge ); 8000be0: 687b ldr r3, [r7, #4] 8000be2: 6a1b ldr r3, [r3, #32] tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | 8000be4: 4313 orrs r3, r2 8000be6: 68ba ldr r2, [r7, #8] 8000be8: 4313 orrs r3, r2 8000bea: 60bb str r3, [r7, #8] } /* Update ADC configuration register with previous settings */ hadc->Instance->CFGR1 |= tmpCFGR1; 8000bec: 687b ldr r3, [r7, #4] 8000bee: 681b ldr r3, [r3, #0] 8000bf0: 68d9 ldr r1, [r3, #12] 8000bf2: 687b ldr r3, [r7, #4] 8000bf4: 681b ldr r3, [r3, #0] 8000bf6: 68ba ldr r2, [r7, #8] 8000bf8: 430a orrs r2, r1 8000bfa: 60da str r2, [r3, #12] /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function if parameter */ /* "SamplingTimeCommon" has been set to a valid sampling time. */ /* Otherwise, sampling time is set into ADC channel initialization */ /* structure with parameter "SamplingTime" (obsolete). */ if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000bfc: 687b ldr r3, [r7, #4] 8000bfe: 6ada ldr r2, [r3, #44] ; 0x2c 8000c00: 2380 movs r3, #128 ; 0x80 8000c02: 055b lsls r3, r3, #21 8000c04: 429a cmp r2, r3 8000c06: d01b beq.n 8000c40 8000c08: 687b ldr r3, [r7, #4] 8000c0a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c0c: 2b01 cmp r3, #1 8000c0e: d017 beq.n 8000c40 8000c10: 687b ldr r3, [r7, #4] 8000c12: 6adb ldr r3, [r3, #44] ; 0x2c 8000c14: 2b02 cmp r3, #2 8000c16: d013 beq.n 8000c40 8000c18: 687b ldr r3, [r7, #4] 8000c1a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c1c: 2b03 cmp r3, #3 8000c1e: d00f beq.n 8000c40 8000c20: 687b ldr r3, [r7, #4] 8000c22: 6adb ldr r3, [r3, #44] ; 0x2c 8000c24: 2b04 cmp r3, #4 8000c26: d00b beq.n 8000c40 8000c28: 687b ldr r3, [r7, #4] 8000c2a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c2c: 2b05 cmp r3, #5 8000c2e: d007 beq.n 8000c40 8000c30: 687b ldr r3, [r7, #4] 8000c32: 6adb ldr r3, [r3, #44] ; 0x2c 8000c34: 2b06 cmp r3, #6 8000c36: d003 beq.n 8000c40 8000c38: 687b ldr r3, [r7, #4] 8000c3a: 6adb ldr r3, [r3, #44] ; 0x2c 8000c3c: 2b07 cmp r3, #7 8000c3e: d112 bne.n 8000c66 { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8000c40: 687b ldr r3, [r7, #4] 8000c42: 681b ldr r3, [r3, #0] 8000c44: 695a ldr r2, [r3, #20] 8000c46: 687b ldr r3, [r7, #4] 8000c48: 681b ldr r3, [r3, #0] 8000c4a: 2107 movs r1, #7 8000c4c: 438a bics r2, r1 8000c4e: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); 8000c50: 687b ldr r3, [r7, #4] 8000c52: 681b ldr r3, [r3, #0] 8000c54: 6959 ldr r1, [r3, #20] 8000c56: 687b ldr r3, [r7, #4] 8000c58: 6adb ldr r3, [r3, #44] ; 0x2c 8000c5a: 2207 movs r2, #7 8000c5c: 401a ands r2, r3 8000c5e: 687b ldr r3, [r7, #4] 8000c60: 681b ldr r3, [r3, #0] 8000c62: 430a orrs r2, r1 8000c64: 615a str r2, [r3, #20] /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ /* set into separate dedicated function, and bits of ADC resolution set */ /* out of temporary variable 'tmpCFGR1'). */ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c66: 687b ldr r3, [r7, #4] 8000c68: 681b ldr r3, [r3, #0] 8000c6a: 68db ldr r3, [r3, #12] 8000c6c: 4a1c ldr r2, [pc, #112] ; (8000ce0 ) 8000c6e: 4013 ands r3, r2 8000c70: 68ba ldr r2, [r7, #8] 8000c72: 429a cmp r2, r3 8000c74: d10b bne.n 8000c8e == tmpCFGR1) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8000c76: 687b ldr r3, [r7, #4] 8000c78: 2200 movs r2, #0 8000c7a: 63da str r2, [r3, #60] ; 0x3c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000c7c: 687b ldr r3, [r7, #4] 8000c7e: 6b9b ldr r3, [r3, #56] ; 0x38 8000c80: 2203 movs r2, #3 8000c82: 4393 bics r3, r2 8000c84: 2201 movs r2, #1 8000c86: 431a orrs r2, r3 8000c88: 687b ldr r3, [r7, #4] 8000c8a: 639a str r2, [r3, #56] ; 0x38 if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000c8c: e01c b.n 8000cc8 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8000c8e: 687b ldr r3, [r7, #4] 8000c90: 6b9b ldr r3, [r3, #56] ; 0x38 8000c92: 2212 movs r2, #18 8000c94: 4393 bics r3, r2 8000c96: 2210 movs r2, #16 8000c98: 431a orrs r2, r3 8000c9a: 687b ldr r3, [r7, #4] 8000c9c: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000c9e: 687b ldr r3, [r7, #4] 8000ca0: 6bdb ldr r3, [r3, #60] ; 0x3c 8000ca2: 2201 movs r2, #1 8000ca4: 431a orrs r2, r3 8000ca6: 687b ldr r3, [r7, #4] 8000ca8: 63da str r2, [r3, #60] ; 0x3c tmp_hal_status = HAL_ERROR; 8000caa: 230f movs r3, #15 8000cac: 18fb adds r3, r7, r3 8000cae: 2201 movs r2, #1 8000cb0: 701a strb r2, [r3, #0] if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) 8000cb2: e009 b.n 8000cc8 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000cb4: 687b ldr r3, [r7, #4] 8000cb6: 6b9b ldr r3, [r3, #56] ; 0x38 8000cb8: 2210 movs r2, #16 8000cba: 431a orrs r2, r3 8000cbc: 687b ldr r3, [r7, #4] 8000cbe: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 8000cc0: 230f movs r3, #15 8000cc2: 18fb adds r3, r7, r3 8000cc4: 2201 movs r2, #1 8000cc6: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000cc8: 230f movs r3, #15 8000cca: 18fb adds r3, r7, r3 8000ccc: 781b ldrb r3, [r3, #0] } 8000cce: 0018 movs r0, r3 8000cd0: 46bd mov sp, r7 8000cd2: b004 add sp, #16 8000cd4: bd80 pop {r7, pc} 8000cd6: 46c0 nop ; (mov r8, r8) 8000cd8: fffffefd .word 0xfffffefd 8000cdc: fffe0219 .word 0xfffe0219 8000ce0: 833fffe7 .word 0x833fffe7 08000ce4 : * Interruptions enabled in this function: None. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 8000ce4: b590 push {r4, r7, lr} 8000ce6: b085 sub sp, #20 8000ce8: af00 add r7, sp, #0 8000cea: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000cec: 230f movs r3, #15 8000cee: 18fb adds r3, r7, r3 8000cf0: 2200 movs r2, #0 8000cf2: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000cf4: 687b ldr r3, [r7, #4] 8000cf6: 681b ldr r3, [r3, #0] 8000cf8: 689b ldr r3, [r3, #8] 8000cfa: 2204 movs r2, #4 8000cfc: 4013 ands r3, r2 8000cfe: d138 bne.n 8000d72 { /* Process locked */ __HAL_LOCK(hadc); 8000d00: 687b ldr r3, [r7, #4] 8000d02: 2234 movs r2, #52 ; 0x34 8000d04: 5c9b ldrb r3, [r3, r2] 8000d06: 2b01 cmp r3, #1 8000d08: d101 bne.n 8000d0e 8000d0a: 2302 movs r3, #2 8000d0c: e038 b.n 8000d80 8000d0e: 687b ldr r3, [r7, #4] 8000d10: 2234 movs r2, #52 ; 0x34 8000d12: 2101 movs r1, #1 8000d14: 5499 strb r1, [r3, r2] /* Enable the ADC peripheral */ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) 8000d16: 687b ldr r3, [r7, #4] 8000d18: 7e5b ldrb r3, [r3, #25] 8000d1a: 2b01 cmp r3, #1 8000d1c: d007 beq.n 8000d2e { tmp_hal_status = ADC_Enable(hadc); 8000d1e: 230f movs r3, #15 8000d20: 18fc adds r4, r7, r3 8000d22: 687b ldr r3, [r7, #4] 8000d24: 0018 movs r0, r3 8000d26: f000 fa0b bl 8001140 8000d2a: 0003 movs r3, r0 8000d2c: 7023 strb r3, [r4, #0] } /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8000d2e: 230f movs r3, #15 8000d30: 18fb adds r3, r7, r3 8000d32: 781b ldrb r3, [r3, #0] 8000d34: 2b00 cmp r3, #0 8000d36: d120 bne.n 8000d7a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8000d38: 687b ldr r3, [r7, #4] 8000d3a: 6b9b ldr r3, [r3, #56] ; 0x38 8000d3c: 4a12 ldr r2, [pc, #72] ; (8000d88 ) 8000d3e: 4013 ands r3, r2 8000d40: 2280 movs r2, #128 ; 0x80 8000d42: 0052 lsls r2, r2, #1 8000d44: 431a orrs r2, r3 8000d46: 687b ldr r3, [r7, #4] 8000d48: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8000d4a: 687b ldr r3, [r7, #4] 8000d4c: 2200 movs r2, #0 8000d4e: 63da str r2, [r3, #60] ; 0x3c /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8000d50: 687b ldr r3, [r7, #4] 8000d52: 2234 movs r2, #52 ; 0x34 8000d54: 2100 movs r1, #0 8000d56: 5499 strb r1, [r3, r2] /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8000d58: 687b ldr r3, [r7, #4] 8000d5a: 681b ldr r3, [r3, #0] 8000d5c: 221c movs r2, #28 8000d5e: 601a str r2, [r3, #0] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ hadc->Instance->CR |= ADC_CR_ADSTART; 8000d60: 687b ldr r3, [r7, #4] 8000d62: 681b ldr r3, [r3, #0] 8000d64: 689a ldr r2, [r3, #8] 8000d66: 687b ldr r3, [r7, #4] 8000d68: 681b ldr r3, [r3, #0] 8000d6a: 2104 movs r1, #4 8000d6c: 430a orrs r2, r1 8000d6e: 609a str r2, [r3, #8] 8000d70: e003 b.n 8000d7a } } else { tmp_hal_status = HAL_BUSY; 8000d72: 230f movs r3, #15 8000d74: 18fb adds r3, r7, r3 8000d76: 2202 movs r2, #2 8000d78: 701a strb r2, [r3, #0] } /* Return function status */ return tmp_hal_status; 8000d7a: 230f movs r3, #15 8000d7c: 18fb adds r3, r7, r3 8000d7e: 781b ldrb r3, [r3, #0] } 8000d80: 0018 movs r0, r3 8000d82: 46bd mov sp, r7 8000d84: b005 add sp, #20 8000d86: bd90 pop {r4, r7, pc} 8000d88: fffff0fe .word 0xfffff0fe 08000d8c : * @brief Stop ADC conversion of regular group, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 8000d8c: b5b0 push {r4, r5, r7, lr} 8000d8e: b084 sub sp, #16 8000d90: af00 add r7, sp, #0 8000d92: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000d94: 230f movs r3, #15 8000d96: 18fb adds r3, r7, r3 8000d98: 2200 movs r2, #0 8000d9a: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8000d9c: 687b ldr r3, [r7, #4] 8000d9e: 2234 movs r2, #52 ; 0x34 8000da0: 5c9b ldrb r3, [r3, r2] 8000da2: 2b01 cmp r3, #1 8000da4: d101 bne.n 8000daa 8000da6: 2302 movs r3, #2 8000da8: e029 b.n 8000dfe 8000daa: 687b ldr r3, [r7, #4] 8000dac: 2234 movs r2, #52 ; 0x34 8000dae: 2101 movs r1, #1 8000db0: 5499 strb r1, [r3, r2] /* 1. Stop potential conversion on going, on regular group */ tmp_hal_status = ADC_ConversionStop(hadc); 8000db2: 250f movs r5, #15 8000db4: 197c adds r4, r7, r5 8000db6: 687b ldr r3, [r7, #4] 8000db8: 0018 movs r0, r3 8000dba: f000 fab6 bl 800132a 8000dbe: 0003 movs r3, r0 8000dc0: 7023 strb r3, [r4, #0] /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) 8000dc2: 197b adds r3, r7, r5 8000dc4: 781b ldrb r3, [r3, #0] 8000dc6: 2b00 cmp r3, #0 8000dc8: d112 bne.n 8000df0 { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); 8000dca: 197c adds r4, r7, r5 8000dcc: 687b ldr r3, [r7, #4] 8000dce: 0018 movs r0, r3 8000dd0: f000 fa3a bl 8001248 8000dd4: 0003 movs r3, r0 8000dd6: 7023 strb r3, [r4, #0] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8000dd8: 197b adds r3, r7, r5 8000dda: 781b ldrb r3, [r3, #0] 8000ddc: 2b00 cmp r3, #0 8000dde: d107 bne.n 8000df0 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000de0: 687b ldr r3, [r7, #4] 8000de2: 6b9b ldr r3, [r3, #56] ; 0x38 8000de4: 4a08 ldr r2, [pc, #32] ; (8000e08 ) 8000de6: 4013 ands r3, r2 8000de8: 2201 movs r2, #1 8000dea: 431a orrs r2, r3 8000dec: 687b ldr r3, [r7, #4] 8000dee: 639a str r2, [r3, #56] ; 0x38 HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000df0: 687b ldr r3, [r7, #4] 8000df2: 2234 movs r2, #52 ; 0x34 8000df4: 2100 movs r1, #0 8000df6: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 8000df8: 230f movs r3, #15 8000dfa: 18fb adds r3, r7, r3 8000dfc: 781b ldrb r3, [r3, #0] } 8000dfe: 0018 movs r0, r3 8000e00: 46bd mov sp, r7 8000e02: b004 add sp, #16 8000e04: bdb0 pop {r4, r5, r7, pc} 8000e06: 46c0 nop ; (mov r8, r8) 8000e08: fffffefe .word 0xfffffefe 08000e0c : * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8000e0c: b580 push {r7, lr} 8000e0e: b084 sub sp, #16 8000e10: af00 add r7, sp, #0 8000e12: 6078 str r0, [r7, #4] 8000e14: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) 8000e16: 687b ldr r3, [r7, #4] 8000e18: 695b ldr r3, [r3, #20] 8000e1a: 2b08 cmp r3, #8 8000e1c: d102 bne.n 8000e24 { tmp_Flag_EOC = ADC_FLAG_EOS; 8000e1e: 2308 movs r3, #8 8000e20: 60fb str r3, [r7, #12] 8000e22: e014 b.n 8000e4e /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) 8000e24: 687b ldr r3, [r7, #4] 8000e26: 681b ldr r3, [r3, #0] 8000e28: 68db ldr r3, [r3, #12] 8000e2a: 2201 movs r2, #1 8000e2c: 4013 ands r3, r2 8000e2e: 2b01 cmp r3, #1 8000e30: d10b bne.n 8000e4a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000e32: 687b ldr r3, [r7, #4] 8000e34: 6b9b ldr r3, [r3, #56] ; 0x38 8000e36: 2220 movs r2, #32 8000e38: 431a orrs r2, r3 8000e3a: 687b ldr r3, [r7, #4] 8000e3c: 639a str r2, [r3, #56] ; 0x38 /* Process unlocked */ __HAL_UNLOCK(hadc); 8000e3e: 687b ldr r3, [r7, #4] 8000e40: 2234 movs r2, #52 ; 0x34 8000e42: 2100 movs r1, #0 8000e44: 5499 strb r1, [r3, r2] return HAL_ERROR; 8000e46: 2301 movs r3, #1 8000e48: e071 b.n 8000f2e } else { tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); 8000e4a: 230c movs r3, #12 8000e4c: 60fb str r3, [r7, #12] } } /* Get tick count */ tickstart = HAL_GetTick(); 8000e4e: f7ff fddb bl 8000a08 8000e52: 0003 movs r3, r0 8000e54: 60bb str r3, [r7, #8] /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e56: e01f b.n 8000e98 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8000e58: 683b ldr r3, [r7, #0] 8000e5a: 3301 adds r3, #1 8000e5c: d01c beq.n 8000e98 { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) 8000e5e: 683b ldr r3, [r7, #0] 8000e60: 2b00 cmp r3, #0 8000e62: d007 beq.n 8000e74 8000e64: f7ff fdd0 bl 8000a08 8000e68: 0002 movs r2, r0 8000e6a: 68bb ldr r3, [r7, #8] 8000e6c: 1ad3 subs r3, r2, r3 8000e6e: 683a ldr r2, [r7, #0] 8000e70: 429a cmp r2, r3 8000e72: d211 bcs.n 8000e98 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e74: 687b ldr r3, [r7, #4] 8000e76: 681b ldr r3, [r3, #0] 8000e78: 681b ldr r3, [r3, #0] 8000e7a: 68fa ldr r2, [r7, #12] 8000e7c: 4013 ands r3, r2 8000e7e: d10b bne.n 8000e98 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8000e80: 687b ldr r3, [r7, #4] 8000e82: 6b9b ldr r3, [r3, #56] ; 0x38 8000e84: 2204 movs r2, #4 8000e86: 431a orrs r2, r3 8000e88: 687b ldr r3, [r7, #4] 8000e8a: 639a str r2, [r3, #56] ; 0x38 /* Process unlocked */ __HAL_UNLOCK(hadc); 8000e8c: 687b ldr r3, [r7, #4] 8000e8e: 2234 movs r2, #52 ; 0x34 8000e90: 2100 movs r1, #0 8000e92: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 8000e94: 2303 movs r3, #3 8000e96: e04a b.n 8000f2e while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) 8000e98: 687b ldr r3, [r7, #4] 8000e9a: 681b ldr r3, [r3, #0] 8000e9c: 681b ldr r3, [r3, #0] 8000e9e: 68fa ldr r2, [r7, #12] 8000ea0: 4013 ands r3, r2 8000ea2: d0d9 beq.n 8000e58 } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8000ea4: 687b ldr r3, [r7, #4] 8000ea6: 6b9b ldr r3, [r3, #56] ; 0x38 8000ea8: 2280 movs r2, #128 ; 0x80 8000eaa: 0092 lsls r2, r2, #2 8000eac: 431a orrs r2, r3 8000eae: 687b ldr r3, [r7, #4] 8000eb0: 639a str r2, [r3, #56] ; 0x38 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000eb2: 687b ldr r3, [r7, #4] 8000eb4: 681b ldr r3, [r3, #0] 8000eb6: 68da ldr r2, [r3, #12] 8000eb8: 23c0 movs r3, #192 ; 0xc0 8000eba: 011b lsls r3, r3, #4 8000ebc: 4013 ands r3, r2 8000ebe: d12d bne.n 8000f1c (hadc->Init.ContinuousConvMode == DISABLE) ) 8000ec0: 687b ldr r3, [r7, #4] 8000ec2: 7e9b ldrb r3, [r3, #26] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000ec4: 2b00 cmp r3, #0 8000ec6: d129 bne.n 8000f1c { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 681b ldr r3, [r3, #0] 8000ecc: 681b ldr r3, [r3, #0] 8000ece: 2208 movs r2, #8 8000ed0: 4013 ands r3, r2 8000ed2: 2b08 cmp r3, #8 8000ed4: d122 bne.n 8000f1c { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000ed6: 687b ldr r3, [r7, #4] 8000ed8: 681b ldr r3, [r3, #0] 8000eda: 689b ldr r3, [r3, #8] 8000edc: 2204 movs r2, #4 8000ede: 4013 ands r3, r2 8000ee0: d110 bne.n 8000f04 { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 8000ee2: 687b ldr r3, [r7, #4] 8000ee4: 681b ldr r3, [r3, #0] 8000ee6: 685a ldr r2, [r3, #4] 8000ee8: 687b ldr r3, [r7, #4] 8000eea: 681b ldr r3, [r3, #0] 8000eec: 210c movs r1, #12 8000eee: 438a bics r2, r1 8000ef0: 605a str r2, [r3, #4] /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8000ef2: 687b ldr r3, [r7, #4] 8000ef4: 6b9b ldr r3, [r3, #56] ; 0x38 8000ef6: 4a10 ldr r2, [pc, #64] ; (8000f38 ) 8000ef8: 4013 ands r3, r2 8000efa: 2201 movs r2, #1 8000efc: 431a orrs r2, r3 8000efe: 687b ldr r3, [r7, #4] 8000f00: 639a str r2, [r3, #56] ; 0x38 8000f02: e00b b.n 8000f1c HAL_ADC_STATE_READY); } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000f04: 687b ldr r3, [r7, #4] 8000f06: 6b9b ldr r3, [r3, #56] ; 0x38 8000f08: 2220 movs r2, #32 8000f0a: 431a orrs r2, r3 8000f0c: 687b ldr r3, [r7, #4] 8000f0e: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000f10: 687b ldr r3, [r7, #4] 8000f12: 6bdb ldr r3, [r3, #60] ; 0x3c 8000f14: 2201 movs r2, #1 8000f16: 431a orrs r2, r3 8000f18: 687b ldr r3, [r7, #4] 8000f1a: 63da str r2, [r3, #60] ; 0x3c } /* Clear end of conversion flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (hadc->Init.LowPowerAutoWait == DISABLE) 8000f1c: 687b ldr r3, [r7, #4] 8000f1e: 7e1b ldrb r3, [r3, #24] 8000f20: 2b00 cmp r3, #0 8000f22: d103 bne.n 8000f2c { /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); 8000f24: 687b ldr r3, [r7, #4] 8000f26: 681b ldr r3, [r3, #0] 8000f28: 220c movs r2, #12 8000f2a: 601a str r2, [r3, #0] } /* Return ADC state */ return HAL_OK; 8000f2c: 2300 movs r3, #0 } 8000f2e: 0018 movs r0, r3 8000f30: 46bd mov sp, r7 8000f32: b004 add sp, #16 8000f34: bd80 pop {r7, pc} 8000f36: 46c0 nop ; (mov r8, r8) 8000f38: fffffefe .word 0xfffffefe 08000f3c : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8000f3c: b580 push {r7, lr} 8000f3e: b082 sub sp, #8 8000f40: af00 add r7, sp, #0 8000f42: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8000f44: 687b ldr r3, [r7, #4] 8000f46: 681b ldr r3, [r3, #0] 8000f48: 6c1b ldr r3, [r3, #64] ; 0x40 } 8000f4a: 0018 movs r0, r3 8000f4c: 46bd mov sp, r7 8000f4e: b002 add sp, #8 8000f50: bd80 pop {r7, pc} ... 08000f54 : * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8000f54: b580 push {r7, lr} 8000f56: b084 sub sp, #16 8000f58: af00 add r7, sp, #0 8000f5a: 6078 str r0, [r7, #4] 8000f5c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000f5e: 230f movs r3, #15 8000f60: 18fb adds r3, r7, r3 8000f62: 2200 movs r2, #0 8000f64: 701a strb r2, [r3, #0] __IO uint32_t wait_loop_index = 0U; 8000f66: 2300 movs r3, #0 8000f68: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_RANK(sConfig->Rank)); if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000f6a: 687b ldr r3, [r7, #4] 8000f6c: 6ada ldr r2, [r3, #44] ; 0x2c 8000f6e: 2380 movs r3, #128 ; 0x80 8000f70: 055b lsls r3, r3, #21 8000f72: 429a cmp r2, r3 8000f74: d011 beq.n 8000f9a 8000f76: 687b ldr r3, [r7, #4] 8000f78: 6adb ldr r3, [r3, #44] ; 0x2c 8000f7a: 2b01 cmp r3, #1 8000f7c: d00d beq.n 8000f9a 8000f7e: 687b ldr r3, [r7, #4] 8000f80: 6adb ldr r3, [r3, #44] ; 0x2c 8000f82: 2b02 cmp r3, #2 8000f84: d009 beq.n 8000f9a 8000f86: 687b ldr r3, [r7, #4] 8000f88: 6adb ldr r3, [r3, #44] ; 0x2c 8000f8a: 2b03 cmp r3, #3 8000f8c: d005 beq.n 8000f9a 8000f8e: 687b ldr r3, [r7, #4] 8000f90: 6adb ldr r3, [r3, #44] ; 0x2c 8000f92: 2b04 cmp r3, #4 8000f94: d001 beq.n 8000f9a 8000f96: 687b ldr r3, [r7, #4] 8000f98: 6adb ldr r3, [r3, #44] ; 0x2c { assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); } /* Process locked */ __HAL_LOCK(hadc); 8000f9a: 687b ldr r3, [r7, #4] 8000f9c: 2234 movs r2, #52 ; 0x34 8000f9e: 5c9b ldrb r3, [r3, r2] 8000fa0: 2b01 cmp r3, #1 8000fa2: d101 bne.n 8000fa8 8000fa4: 2302 movs r3, #2 8000fa6: e0bb b.n 8001120 8000fa8: 687b ldr r3, [r7, #4] 8000faa: 2234 movs r2, #52 ; 0x34 8000fac: 2101 movs r1, #1 8000fae: 5499 strb r1, [r3, r2] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8000fb0: 687b ldr r3, [r7, #4] 8000fb2: 681b ldr r3, [r3, #0] 8000fb4: 689b ldr r3, [r3, #8] 8000fb6: 2204 movs r2, #4 8000fb8: 4013 ands r3, r2 8000fba: d000 beq.n 8000fbe 8000fbc: e09f b.n 80010fe { /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC conversion sequencer. */ if (sConfig->Rank != ADC_RANK_NONE) 8000fbe: 683b ldr r3, [r7, #0] 8000fc0: 685b ldr r3, [r3, #4] 8000fc2: 4a59 ldr r2, [pc, #356] ; (8001128 ) 8000fc4: 4293 cmp r3, r2 8000fc6: d100 bne.n 8000fca 8000fc8: e077 b.n 80010ba { /* Regular sequence configuration */ /* Set the channel selection register from the selected channel */ hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); 8000fca: 687b ldr r3, [r7, #4] 8000fcc: 681b ldr r3, [r3, #0] 8000fce: 6a99 ldr r1, [r3, #40] ; 0x28 8000fd0: 683b ldr r3, [r7, #0] 8000fd2: 681b ldr r3, [r3, #0] 8000fd4: 2201 movs r2, #1 8000fd6: 409a lsls r2, r3 8000fd8: 687b ldr r3, [r7, #4] 8000fda: 681b ldr r3, [r3, #0] 8000fdc: 430a orrs r2, r1 8000fde: 629a str r2, [r3, #40] ; 0x28 /* Channel sampling time configuration */ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ /* (obsolete): sampling time set in this function with */ /* parameter "SamplingTime" (obsolete) only if not already set into */ /* ADC initialization structure with parameter "SamplingTimeCommon". */ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) 8000fe0: 687b ldr r3, [r7, #4] 8000fe2: 6ada ldr r2, [r3, #44] ; 0x2c 8000fe4: 2380 movs r3, #128 ; 0x80 8000fe6: 055b lsls r3, r3, #21 8000fe8: 429a cmp r2, r3 8000fea: d037 beq.n 800105c 8000fec: 687b ldr r3, [r7, #4] 8000fee: 6adb ldr r3, [r3, #44] ; 0x2c 8000ff0: 2b01 cmp r3, #1 8000ff2: d033 beq.n 800105c 8000ff4: 687b ldr r3, [r7, #4] 8000ff6: 6adb ldr r3, [r3, #44] ; 0x2c 8000ff8: 2b02 cmp r3, #2 8000ffa: d02f beq.n 800105c 8000ffc: 687b ldr r3, [r7, #4] 8000ffe: 6adb ldr r3, [r3, #44] ; 0x2c 8001000: 2b03 cmp r3, #3 8001002: d02b beq.n 800105c 8001004: 687b ldr r3, [r7, #4] 8001006: 6adb ldr r3, [r3, #44] ; 0x2c 8001008: 2b04 cmp r3, #4 800100a: d027 beq.n 800105c 800100c: 687b ldr r3, [r7, #4] 800100e: 6adb ldr r3, [r3, #44] ; 0x2c 8001010: 2b05 cmp r3, #5 8001012: d023 beq.n 800105c 8001014: 687b ldr r3, [r7, #4] 8001016: 6adb ldr r3, [r3, #44] ; 0x2c 8001018: 2b06 cmp r3, #6 800101a: d01f beq.n 800105c 800101c: 687b ldr r3, [r7, #4] 800101e: 6adb ldr r3, [r3, #44] ; 0x2c 8001020: 2b07 cmp r3, #7 8001022: d01b beq.n 800105c { /* Modify sampling time if needed (not needed in case of reoccurrence */ /* for several channels programmed consecutively into the sequencer) */ if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) 8001024: 683b ldr r3, [r7, #0] 8001026: 689a ldr r2, [r3, #8] 8001028: 687b ldr r3, [r7, #4] 800102a: 681b ldr r3, [r3, #0] 800102c: 695b ldr r3, [r3, #20] 800102e: 2107 movs r1, #7 8001030: 400b ands r3, r1 8001032: 429a cmp r2, r3 8001034: d012 beq.n 800105c { /* Channel sampling time configuration */ /* Clear the old sample time */ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); 8001036: 687b ldr r3, [r7, #4] 8001038: 681b ldr r3, [r3, #0] 800103a: 695a ldr r2, [r3, #20] 800103c: 687b ldr r3, [r7, #4] 800103e: 681b ldr r3, [r3, #0] 8001040: 2107 movs r1, #7 8001042: 438a bics r2, r1 8001044: 615a str r2, [r3, #20] /* Set the new sample time */ hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); 8001046: 687b ldr r3, [r7, #4] 8001048: 681b ldr r3, [r3, #0] 800104a: 6959 ldr r1, [r3, #20] 800104c: 683b ldr r3, [r7, #0] 800104e: 689b ldr r3, [r3, #8] 8001050: 2207 movs r2, #7 8001052: 401a ands r2, r3 8001054: 687b ldr r3, [r7, #4] 8001056: 681b ldr r3, [r3, #0] 8001058: 430a orrs r2, r1 800105a: 615a str r2, [r3, #20] /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 800105c: 683b ldr r3, [r7, #0] 800105e: 681b ldr r3, [r3, #0] 8001060: 2b10 cmp r3, #16 8001062: d003 beq.n 800106c 8001064: 683b ldr r3, [r7, #0] 8001066: 681b ldr r3, [r3, #0] 8001068: 2b11 cmp r3, #17 800106a: d152 bne.n 8001112 { /* If Channel_16 is selected, enable Temp. sensor measurement path. */ /* If Channel_17 is selected, enable VREFINT measurement path. */ /* If Channel_18 is selected, enable VBAT measurement path. */ ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 800106c: 4b2f ldr r3, [pc, #188] ; (800112c ) 800106e: 6819 ldr r1, [r3, #0] 8001070: 683b ldr r3, [r7, #0] 8001072: 681b ldr r3, [r3, #0] 8001074: 2b10 cmp r3, #16 8001076: d102 bne.n 800107e 8001078: 2380 movs r3, #128 ; 0x80 800107a: 041b lsls r3, r3, #16 800107c: e001 b.n 8001082 800107e: 2380 movs r3, #128 ; 0x80 8001080: 03db lsls r3, r3, #15 8001082: 4a2a ldr r2, [pc, #168] ; (800112c ) 8001084: 430b orrs r3, r1 8001086: 6013 str r3, [r2, #0] /* If Temp. sensor is selected, wait for stabilization delay */ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8001088: 683b ldr r3, [r7, #0] 800108a: 681b ldr r3, [r3, #0] 800108c: 2b10 cmp r3, #16 800108e: d140 bne.n 8001112 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001090: 4b27 ldr r3, [pc, #156] ; (8001130 ) 8001092: 681b ldr r3, [r3, #0] 8001094: 4927 ldr r1, [pc, #156] ; (8001134 ) 8001096: 0018 movs r0, r3 8001098: f7ff f836 bl 8000108 <__udivsi3> 800109c: 0003 movs r3, r0 800109e: 001a movs r2, r3 80010a0: 0013 movs r3, r2 80010a2: 009b lsls r3, r3, #2 80010a4: 189b adds r3, r3, r2 80010a6: 005b lsls r3, r3, #1 80010a8: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80010aa: e002 b.n 80010b2 { wait_loop_index--; 80010ac: 68bb ldr r3, [r7, #8] 80010ae: 3b01 subs r3, #1 80010b0: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80010b2: 68bb ldr r3, [r7, #8] 80010b4: 2b00 cmp r3, #0 80010b6: d1f9 bne.n 80010ac 80010b8: e02b b.n 8001112 } else { /* Regular sequence configuration */ /* Reset the channel selection register from the selected channel */ hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); 80010ba: 687b ldr r3, [r7, #4] 80010bc: 681b ldr r3, [r3, #0] 80010be: 6a9a ldr r2, [r3, #40] ; 0x28 80010c0: 683b ldr r3, [r7, #0] 80010c2: 681b ldr r3, [r3, #0] 80010c4: 2101 movs r1, #1 80010c6: 4099 lsls r1, r3 80010c8: 000b movs r3, r1 80010ca: 43d9 mvns r1, r3 80010cc: 687b ldr r3, [r7, #4] 80010ce: 681b ldr r3, [r3, #0] 80010d0: 400a ands r2, r1 80010d2: 629a str r2, [r3, #40] ; 0x28 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths disable: If internal channel selected, */ /* disable dedicated internal buffers and path. */ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 80010d4: 683b ldr r3, [r7, #0] 80010d6: 681b ldr r3, [r3, #0] 80010d8: 2b10 cmp r3, #16 80010da: d003 beq.n 80010e4 80010dc: 683b ldr r3, [r7, #0] 80010de: 681b ldr r3, [r3, #0] 80010e0: 2b11 cmp r3, #17 80010e2: d116 bne.n 8001112 { /* If Channel_16 is selected, disable Temp. sensor measurement path. */ /* If Channel_17 is selected, disable VREFINT measurement path. */ /* If Channel_18 is selected, disable VBAT measurement path. */ ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); 80010e4: 4b11 ldr r3, [pc, #68] ; (800112c ) 80010e6: 6819 ldr r1, [r3, #0] 80010e8: 683b ldr r3, [r7, #0] 80010ea: 681b ldr r3, [r3, #0] 80010ec: 2b10 cmp r3, #16 80010ee: d101 bne.n 80010f4 80010f0: 4a11 ldr r2, [pc, #68] ; (8001138 ) 80010f2: e000 b.n 80010f6 80010f4: 4a11 ldr r2, [pc, #68] ; (800113c ) 80010f6: 4b0d ldr r3, [pc, #52] ; (800112c ) 80010f8: 400a ands r2, r1 80010fa: 601a str r2, [r3, #0] 80010fc: e009 b.n 8001112 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80010fe: 687b ldr r3, [r7, #4] 8001100: 6b9b ldr r3, [r3, #56] ; 0x38 8001102: 2220 movs r2, #32 8001104: 431a orrs r2, r3 8001106: 687b ldr r3, [r7, #4] 8001108: 639a str r2, [r3, #56] ; 0x38 tmp_hal_status = HAL_ERROR; 800110a: 230f movs r3, #15 800110c: 18fb adds r3, r7, r3 800110e: 2201 movs r2, #1 8001110: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hadc); 8001112: 687b ldr r3, [r7, #4] 8001114: 2234 movs r2, #52 ; 0x34 8001116: 2100 movs r1, #0 8001118: 5499 strb r1, [r3, r2] /* Return function status */ return tmp_hal_status; 800111a: 230f movs r3, #15 800111c: 18fb adds r3, r7, r3 800111e: 781b ldrb r3, [r3, #0] } 8001120: 0018 movs r0, r3 8001122: 46bd mov sp, r7 8001124: b004 add sp, #16 8001126: bd80 pop {r7, pc} 8001128: 00001001 .word 0x00001001 800112c: 40012708 .word 0x40012708 8001130: 20000000 .word 0x20000000 8001134: 000f4240 .word 0x000f4240 8001138: ff7fffff .word 0xff7fffff 800113c: ffbfffff .word 0xffbfffff 08001140 : * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8001140: b580 push {r7, lr} 8001142: b084 sub sp, #16 8001144: af00 add r7, sp, #0 8001146: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001148: 2300 movs r3, #0 800114a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800114c: 2300 movs r3, #0 800114e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8001150: 687b ldr r3, [r7, #4] 8001152: 681b ldr r3, [r3, #0] 8001154: 689b ldr r3, [r3, #8] 8001156: 2203 movs r2, #3 8001158: 4013 ands r3, r2 800115a: 2b01 cmp r3, #1 800115c: d112 bne.n 8001184 800115e: 687b ldr r3, [r7, #4] 8001160: 681b ldr r3, [r3, #0] 8001162: 681b ldr r3, [r3, #0] 8001164: 2201 movs r2, #1 8001166: 4013 ands r3, r2 8001168: 2b01 cmp r3, #1 800116a: d009 beq.n 8001180 800116c: 687b ldr r3, [r7, #4] 800116e: 681b ldr r3, [r3, #0] 8001170: 68da ldr r2, [r3, #12] 8001172: 2380 movs r3, #128 ; 0x80 8001174: 021b lsls r3, r3, #8 8001176: 401a ands r2, r3 8001178: 2380 movs r3, #128 ; 0x80 800117a: 021b lsls r3, r3, #8 800117c: 429a cmp r2, r3 800117e: d101 bne.n 8001184 8001180: 2301 movs r3, #1 8001182: e000 b.n 8001186 8001184: 2300 movs r3, #0 8001186: 2b00 cmp r3, #0 8001188: d152 bne.n 8001230 { /* Check if conditions to enable the ADC are fulfilled */ if (ADC_ENABLING_CONDITIONS(hadc) == RESET) 800118a: 687b ldr r3, [r7, #4] 800118c: 681b ldr r3, [r3, #0] 800118e: 689b ldr r3, [r3, #8] 8001190: 4a2a ldr r2, [pc, #168] ; (800123c ) 8001192: 4013 ands r3, r2 8001194: d00d beq.n 80011b2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001196: 687b ldr r3, [r7, #4] 8001198: 6b9b ldr r3, [r3, #56] ; 0x38 800119a: 2210 movs r2, #16 800119c: 431a orrs r2, r3 800119e: 687b ldr r3, [r7, #4] 80011a0: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80011a2: 687b ldr r3, [r7, #4] 80011a4: 6bdb ldr r3, [r3, #60] ; 0x3c 80011a6: 2201 movs r2, #1 80011a8: 431a orrs r2, r3 80011aa: 687b ldr r3, [r7, #4] 80011ac: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80011ae: 2301 movs r3, #1 80011b0: e03f b.n 8001232 } /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); 80011b2: 687b ldr r3, [r7, #4] 80011b4: 681b ldr r3, [r3, #0] 80011b6: 689a ldr r2, [r3, #8] 80011b8: 687b ldr r3, [r7, #4] 80011ba: 681b ldr r3, [r3, #0] 80011bc: 2101 movs r1, #1 80011be: 430a orrs r2, r1 80011c0: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 80011c2: 4b1f ldr r3, [pc, #124] ; (8001240 ) 80011c4: 681b ldr r3, [r3, #0] 80011c6: 491f ldr r1, [pc, #124] ; (8001244 ) 80011c8: 0018 movs r0, r3 80011ca: f7fe ff9d bl 8000108 <__udivsi3> 80011ce: 0003 movs r3, r0 80011d0: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80011d2: e002 b.n 80011da { wait_loop_index--; 80011d4: 68bb ldr r3, [r7, #8] 80011d6: 3b01 subs r3, #1 80011d8: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80011da: 68bb ldr r3, [r7, #8] 80011dc: 2b00 cmp r3, #0 80011de: d1f9 bne.n 80011d4 } /* Get tick count */ tickstart = HAL_GetTick(); 80011e0: f7ff fc12 bl 8000a08 80011e4: 0003 movs r3, r0 80011e6: 60fb str r3, [r7, #12] /* Wait for ADC effectively enabled */ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80011e8: e01b b.n 8001222 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80011ea: f7ff fc0d bl 8000a08 80011ee: 0002 movs r2, r0 80011f0: 68fb ldr r3, [r7, #12] 80011f2: 1ad3 subs r3, r2, r3 80011f4: 2b02 cmp r3, #2 80011f6: d914 bls.n 8001222 { /* New check to avoid false timeout detection in case of preemption */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80011f8: 687b ldr r3, [r7, #4] 80011fa: 681b ldr r3, [r3, #0] 80011fc: 681b ldr r3, [r3, #0] 80011fe: 2201 movs r2, #1 8001200: 4013 ands r3, r2 8001202: 2b01 cmp r3, #1 8001204: d00d beq.n 8001222 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001206: 687b ldr r3, [r7, #4] 8001208: 6b9b ldr r3, [r3, #56] ; 0x38 800120a: 2210 movs r2, #16 800120c: 431a orrs r2, r3 800120e: 687b ldr r3, [r7, #4] 8001210: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001212: 687b ldr r3, [r7, #4] 8001214: 6bdb ldr r3, [r3, #60] ; 0x3c 8001216: 2201 movs r2, #1 8001218: 431a orrs r2, r3 800121a: 687b ldr r3, [r7, #4] 800121c: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 800121e: 2301 movs r3, #1 8001220: e007 b.n 8001232 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 8001222: 687b ldr r3, [r7, #4] 8001224: 681b ldr r3, [r3, #0] 8001226: 681b ldr r3, [r3, #0] 8001228: 2201 movs r2, #1 800122a: 4013 ands r3, r2 800122c: 2b01 cmp r3, #1 800122e: d1dc bne.n 80011ea } } } /* Return HAL status */ return HAL_OK; 8001230: 2300 movs r3, #0 } 8001232: 0018 movs r0, r3 8001234: 46bd mov sp, r7 8001236: b004 add sp, #16 8001238: bd80 pop {r7, pc} 800123a: 46c0 nop ; (mov r8, r8) 800123c: 80000017 .word 0x80000017 8001240: 20000000 .word 0x20000000 8001244: 000f4240 .word 0x000f4240 08001248 : * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { 8001248: b580 push {r7, lr} 800124a: b084 sub sp, #16 800124c: af00 add r7, sp, #0 800124e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001250: 2300 movs r3, #0 8001252: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET) 8001254: 687b ldr r3, [r7, #4] 8001256: 681b ldr r3, [r3, #0] 8001258: 689b ldr r3, [r3, #8] 800125a: 2203 movs r2, #3 800125c: 4013 ands r3, r2 800125e: 2b01 cmp r3, #1 8001260: d112 bne.n 8001288 8001262: 687b ldr r3, [r7, #4] 8001264: 681b ldr r3, [r3, #0] 8001266: 681b ldr r3, [r3, #0] 8001268: 2201 movs r2, #1 800126a: 4013 ands r3, r2 800126c: 2b01 cmp r3, #1 800126e: d009 beq.n 8001284 8001270: 687b ldr r3, [r7, #4] 8001272: 681b ldr r3, [r3, #0] 8001274: 68da ldr r2, [r3, #12] 8001276: 2380 movs r3, #128 ; 0x80 8001278: 021b lsls r3, r3, #8 800127a: 401a ands r2, r3 800127c: 2380 movs r3, #128 ; 0x80 800127e: 021b lsls r3, r3, #8 8001280: 429a cmp r2, r3 8001282: d101 bne.n 8001288 8001284: 2301 movs r3, #1 8001286: e000 b.n 800128a 8001288: 2300 movs r3, #0 800128a: 2b00 cmp r3, #0 800128c: d048 beq.n 8001320 { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) 800128e: 687b ldr r3, [r7, #4] 8001290: 681b ldr r3, [r3, #0] 8001292: 689b ldr r3, [r3, #8] 8001294: 2205 movs r2, #5 8001296: 4013 ands r3, r2 8001298: 2b01 cmp r3, #1 800129a: d110 bne.n 80012be { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800129c: 687b ldr r3, [r7, #4] 800129e: 681b ldr r3, [r3, #0] 80012a0: 689a ldr r2, [r3, #8] 80012a2: 687b ldr r3, [r7, #4] 80012a4: 681b ldr r3, [r3, #0] 80012a6: 2102 movs r1, #2 80012a8: 430a orrs r2, r1 80012aa: 609a str r2, [r3, #8] 80012ac: 687b ldr r3, [r7, #4] 80012ae: 681b ldr r3, [r3, #0] 80012b0: 2203 movs r2, #3 80012b2: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 80012b4: f7ff fba8 bl 8000a08 80012b8: 0003 movs r3, r0 80012ba: 60fb str r3, [r7, #12] while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80012bc: e029 b.n 8001312 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80012be: 687b ldr r3, [r7, #4] 80012c0: 6b9b ldr r3, [r3, #56] ; 0x38 80012c2: 2210 movs r2, #16 80012c4: 431a orrs r2, r3 80012c6: 687b ldr r3, [r7, #4] 80012c8: 639a str r2, [r3, #56] ; 0x38 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80012ca: 687b ldr r3, [r7, #4] 80012cc: 6bdb ldr r3, [r3, #60] ; 0x3c 80012ce: 2201 movs r2, #1 80012d0: 431a orrs r2, r3 80012d2: 687b ldr r3, [r7, #4] 80012d4: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80012d6: 2301 movs r3, #1 80012d8: e023 b.n 8001322 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 80012da: f7ff fb95 bl 8000a08 80012de: 0002 movs r2, r0 80012e0: 68fb ldr r3, [r7, #12] 80012e2: 1ad3 subs r3, r2, r3 80012e4: 2b02 cmp r3, #2 80012e6: d914 bls.n 8001312 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 80012e8: 687b ldr r3, [r7, #4] 80012ea: 681b ldr r3, [r3, #0] 80012ec: 689b ldr r3, [r3, #8] 80012ee: 2201 movs r2, #1 80012f0: 4013 ands r3, r2 80012f2: 2b01 cmp r3, #1 80012f4: d10d bne.n 8001312 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80012f6: 687b ldr r3, [r7, #4] 80012f8: 6b9b ldr r3, [r3, #56] ; 0x38 80012fa: 2210 movs r2, #16 80012fc: 431a orrs r2, r3 80012fe: 687b ldr r3, [r7, #4] 8001300: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001302: 687b ldr r3, [r7, #4] 8001304: 6bdb ldr r3, [r3, #60] ; 0x3c 8001306: 2201 movs r2, #1 8001308: 431a orrs r2, r3 800130a: 687b ldr r3, [r7, #4] 800130c: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 800130e: 2301 movs r3, #1 8001310: e007 b.n 8001322 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 8001312: 687b ldr r3, [r7, #4] 8001314: 681b ldr r3, [r3, #0] 8001316: 689b ldr r3, [r3, #8] 8001318: 2201 movs r2, #1 800131a: 4013 ands r3, r2 800131c: 2b01 cmp r3, #1 800131e: d0dc beq.n 80012da } } } /* Return HAL status */ return HAL_OK; 8001320: 2300 movs r3, #0 } 8001322: 0018 movs r0, r3 8001324: 46bd mov sp, r7 8001326: b004 add sp, #16 8001328: bd80 pop {r7, pc} 0800132a : * stopped to disable the ADC. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) { 800132a: b580 push {r7, lr} 800132c: b084 sub sp, #16 800132e: af00 add r7, sp, #0 8001330: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001332: 2300 movs r3, #0 8001334: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Verification if ADC is not already stopped on regular group to bypass */ /* this function if not needed. */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) 8001336: 687b ldr r3, [r7, #4] 8001338: 681b ldr r3, [r3, #0] 800133a: 689b ldr r3, [r3, #8] 800133c: 2204 movs r2, #4 800133e: 4013 ands r3, r2 8001340: d03a beq.n 80013b8 { /* Stop potential conversion on going on regular group */ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 8001342: 687b ldr r3, [r7, #4] 8001344: 681b ldr r3, [r3, #0] 8001346: 689b ldr r3, [r3, #8] 8001348: 2204 movs r2, #4 800134a: 4013 ands r3, r2 800134c: 2b04 cmp r3, #4 800134e: d10d bne.n 800136c HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) 8001350: 687b ldr r3, [r7, #4] 8001352: 681b ldr r3, [r3, #0] 8001354: 689b ldr r3, [r3, #8] 8001356: 2202 movs r2, #2 8001358: 4013 ands r3, r2 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 800135a: d107 bne.n 800136c { /* Stop conversions on regular group */ hadc->Instance->CR |= ADC_CR_ADSTP; 800135c: 687b ldr r3, [r7, #4] 800135e: 681b ldr r3, [r3, #0] 8001360: 689a ldr r2, [r3, #8] 8001362: 687b ldr r3, [r7, #4] 8001364: 681b ldr r3, [r3, #0] 8001366: 2110 movs r1, #16 8001368: 430a orrs r2, r1 800136a: 609a str r2, [r3, #8] } /* Wait for conversion effectively stopped */ /* Get tick count */ tickstart = HAL_GetTick(); 800136c: f7ff fb4c bl 8000a08 8001370: 0003 movs r3, r0 8001372: 60fb str r3, [r7, #12] while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 8001374: e01a b.n 80013ac { if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 8001376: f7ff fb47 bl 8000a08 800137a: 0002 movs r2, r0 800137c: 68fb ldr r3, [r7, #12] 800137e: 1ad3 subs r3, r2, r3 8001380: 2b02 cmp r3, #2 8001382: d913 bls.n 80013ac { /* New check to avoid false timeout detection in case of preemption */ if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 8001384: 687b ldr r3, [r7, #4] 8001386: 681b ldr r3, [r3, #0] 8001388: 689b ldr r3, [r3, #8] 800138a: 2204 movs r2, #4 800138c: 4013 ands r3, r2 800138e: d00d beq.n 80013ac { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001390: 687b ldr r3, [r7, #4] 8001392: 6b9b ldr r3, [r3, #56] ; 0x38 8001394: 2210 movs r2, #16 8001396: 431a orrs r2, r3 8001398: 687b ldr r3, [r7, #4] 800139a: 639a str r2, [r3, #56] ; 0x38 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800139c: 687b ldr r3, [r7, #4] 800139e: 6bdb ldr r3, [r3, #60] ; 0x3c 80013a0: 2201 movs r2, #1 80013a2: 431a orrs r2, r3 80013a4: 687b ldr r3, [r7, #4] 80013a6: 63da str r2, [r3, #60] ; 0x3c return HAL_ERROR; 80013a8: 2301 movs r3, #1 80013aa: e006 b.n 80013ba while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) 80013ac: 687b ldr r3, [r7, #4] 80013ae: 681b ldr r3, [r3, #0] 80013b0: 689b ldr r3, [r3, #8] 80013b2: 2204 movs r2, #4 80013b4: 4013 ands r3, r2 80013b6: d1de bne.n 8001376 } } } /* Return HAL status */ return HAL_OK; 80013b8: 2300 movs r3, #0 } 80013ba: 0018 movs r0, r3 80013bc: 46bd mov sp, r7 80013be: b004 add sp, #16 80013c0: bd80 pop {r7, pc} ... 080013c4 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80013c4: b580 push {r7, lr} 80013c6: b082 sub sp, #8 80013c8: af00 add r7, sp, #0 80013ca: 0002 movs r2, r0 80013cc: 1dfb adds r3, r7, #7 80013ce: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80013d0: 1dfb adds r3, r7, #7 80013d2: 781b ldrb r3, [r3, #0] 80013d4: 2b7f cmp r3, #127 ; 0x7f 80013d6: d809 bhi.n 80013ec <__NVIC_EnableIRQ+0x28> { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80013d8: 1dfb adds r3, r7, #7 80013da: 781b ldrb r3, [r3, #0] 80013dc: 001a movs r2, r3 80013de: 231f movs r3, #31 80013e0: 401a ands r2, r3 80013e2: 4b04 ldr r3, [pc, #16] ; (80013f4 <__NVIC_EnableIRQ+0x30>) 80013e4: 2101 movs r1, #1 80013e6: 4091 lsls r1, r2 80013e8: 000a movs r2, r1 80013ea: 601a str r2, [r3, #0] } } 80013ec: 46c0 nop ; (mov r8, r8) 80013ee: 46bd mov sp, r7 80013f0: b002 add sp, #8 80013f2: bd80 pop {r7, pc} 80013f4: e000e100 .word 0xe000e100 080013f8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80013f8: b590 push {r4, r7, lr} 80013fa: b083 sub sp, #12 80013fc: af00 add r7, sp, #0 80013fe: 0002 movs r2, r0 8001400: 6039 str r1, [r7, #0] 8001402: 1dfb adds r3, r7, #7 8001404: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8001406: 1dfb adds r3, r7, #7 8001408: 781b ldrb r3, [r3, #0] 800140a: 2b7f cmp r3, #127 ; 0x7f 800140c: d828 bhi.n 8001460 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800140e: 4a2f ldr r2, [pc, #188] ; (80014cc <__NVIC_SetPriority+0xd4>) 8001410: 1dfb adds r3, r7, #7 8001412: 781b ldrb r3, [r3, #0] 8001414: b25b sxtb r3, r3 8001416: 089b lsrs r3, r3, #2 8001418: 33c0 adds r3, #192 ; 0xc0 800141a: 009b lsls r3, r3, #2 800141c: 589b ldr r3, [r3, r2] 800141e: 1dfa adds r2, r7, #7 8001420: 7812 ldrb r2, [r2, #0] 8001422: 0011 movs r1, r2 8001424: 2203 movs r2, #3 8001426: 400a ands r2, r1 8001428: 00d2 lsls r2, r2, #3 800142a: 21ff movs r1, #255 ; 0xff 800142c: 4091 lsls r1, r2 800142e: 000a movs r2, r1 8001430: 43d2 mvns r2, r2 8001432: 401a ands r2, r3 8001434: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8001436: 683b ldr r3, [r7, #0] 8001438: 019b lsls r3, r3, #6 800143a: 22ff movs r2, #255 ; 0xff 800143c: 401a ands r2, r3 800143e: 1dfb adds r3, r7, #7 8001440: 781b ldrb r3, [r3, #0] 8001442: 0018 movs r0, r3 8001444: 2303 movs r3, #3 8001446: 4003 ands r3, r0 8001448: 00db lsls r3, r3, #3 800144a: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800144c: 481f ldr r0, [pc, #124] ; (80014cc <__NVIC_SetPriority+0xd4>) 800144e: 1dfb adds r3, r7, #7 8001450: 781b ldrb r3, [r3, #0] 8001452: b25b sxtb r3, r3 8001454: 089b lsrs r3, r3, #2 8001456: 430a orrs r2, r1 8001458: 33c0 adds r3, #192 ; 0xc0 800145a: 009b lsls r3, r3, #2 800145c: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 800145e: e031 b.n 80014c4 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001460: 4a1b ldr r2, [pc, #108] ; (80014d0 <__NVIC_SetPriority+0xd8>) 8001462: 1dfb adds r3, r7, #7 8001464: 781b ldrb r3, [r3, #0] 8001466: 0019 movs r1, r3 8001468: 230f movs r3, #15 800146a: 400b ands r3, r1 800146c: 3b08 subs r3, #8 800146e: 089b lsrs r3, r3, #2 8001470: 3306 adds r3, #6 8001472: 009b lsls r3, r3, #2 8001474: 18d3 adds r3, r2, r3 8001476: 3304 adds r3, #4 8001478: 681b ldr r3, [r3, #0] 800147a: 1dfa adds r2, r7, #7 800147c: 7812 ldrb r2, [r2, #0] 800147e: 0011 movs r1, r2 8001480: 2203 movs r2, #3 8001482: 400a ands r2, r1 8001484: 00d2 lsls r2, r2, #3 8001486: 21ff movs r1, #255 ; 0xff 8001488: 4091 lsls r1, r2 800148a: 000a movs r2, r1 800148c: 43d2 mvns r2, r2 800148e: 401a ands r2, r3 8001490: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8001492: 683b ldr r3, [r7, #0] 8001494: 019b lsls r3, r3, #6 8001496: 22ff movs r2, #255 ; 0xff 8001498: 401a ands r2, r3 800149a: 1dfb adds r3, r7, #7 800149c: 781b ldrb r3, [r3, #0] 800149e: 0018 movs r0, r3 80014a0: 2303 movs r3, #3 80014a2: 4003 ands r3, r0 80014a4: 00db lsls r3, r3, #3 80014a6: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80014a8: 4809 ldr r0, [pc, #36] ; (80014d0 <__NVIC_SetPriority+0xd8>) 80014aa: 1dfb adds r3, r7, #7 80014ac: 781b ldrb r3, [r3, #0] 80014ae: 001c movs r4, r3 80014b0: 230f movs r3, #15 80014b2: 4023 ands r3, r4 80014b4: 3b08 subs r3, #8 80014b6: 089b lsrs r3, r3, #2 80014b8: 430a orrs r2, r1 80014ba: 3306 adds r3, #6 80014bc: 009b lsls r3, r3, #2 80014be: 18c3 adds r3, r0, r3 80014c0: 3304 adds r3, #4 80014c2: 601a str r2, [r3, #0] } 80014c4: 46c0 nop ; (mov r8, r8) 80014c6: 46bd mov sp, r7 80014c8: b003 add sp, #12 80014ca: bd90 pop {r4, r7, pc} 80014cc: e000e100 .word 0xe000e100 80014d0: e000ed00 .word 0xe000ed00 080014d4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80014d4: b580 push {r7, lr} 80014d6: b082 sub sp, #8 80014d8: af00 add r7, sp, #0 80014da: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80014dc: 687b ldr r3, [r7, #4] 80014de: 1e5a subs r2, r3, #1 80014e0: 2380 movs r3, #128 ; 0x80 80014e2: 045b lsls r3, r3, #17 80014e4: 429a cmp r2, r3 80014e6: d301 bcc.n 80014ec { return (1UL); /* Reload value impossible */ 80014e8: 2301 movs r3, #1 80014ea: e010 b.n 800150e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80014ec: 4b0a ldr r3, [pc, #40] ; (8001518 ) 80014ee: 687a ldr r2, [r7, #4] 80014f0: 3a01 subs r2, #1 80014f2: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80014f4: 2301 movs r3, #1 80014f6: 425b negs r3, r3 80014f8: 2103 movs r1, #3 80014fa: 0018 movs r0, r3 80014fc: f7ff ff7c bl 80013f8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001500: 4b05 ldr r3, [pc, #20] ; (8001518 ) 8001502: 2200 movs r2, #0 8001504: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001506: 4b04 ldr r3, [pc, #16] ; (8001518 ) 8001508: 2207 movs r2, #7 800150a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800150c: 2300 movs r3, #0 } 800150e: 0018 movs r0, r3 8001510: 46bd mov sp, r7 8001512: b002 add sp, #8 8001514: bd80 pop {r7, pc} 8001516: 46c0 nop ; (mov r8, r8) 8001518: e000e010 .word 0xe000e010 0800151c : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800151c: b580 push {r7, lr} 800151e: b084 sub sp, #16 8001520: af00 add r7, sp, #0 8001522: 60b9 str r1, [r7, #8] 8001524: 607a str r2, [r7, #4] 8001526: 210f movs r1, #15 8001528: 187b adds r3, r7, r1 800152a: 1c02 adds r2, r0, #0 800152c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 800152e: 68ba ldr r2, [r7, #8] 8001530: 187b adds r3, r7, r1 8001532: 781b ldrb r3, [r3, #0] 8001534: b25b sxtb r3, r3 8001536: 0011 movs r1, r2 8001538: 0018 movs r0, r3 800153a: f7ff ff5d bl 80013f8 <__NVIC_SetPriority> } 800153e: 46c0 nop ; (mov r8, r8) 8001540: 46bd mov sp, r7 8001542: b004 add sp, #16 8001544: bd80 pop {r7, pc} 08001546 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001546: b580 push {r7, lr} 8001548: b082 sub sp, #8 800154a: af00 add r7, sp, #0 800154c: 0002 movs r2, r0 800154e: 1dfb adds r3, r7, #7 8001550: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001552: 1dfb adds r3, r7, #7 8001554: 781b ldrb r3, [r3, #0] 8001556: b25b sxtb r3, r3 8001558: 0018 movs r0, r3 800155a: f7ff ff33 bl 80013c4 <__NVIC_EnableIRQ> } 800155e: 46c0 nop ; (mov r8, r8) 8001560: 46bd mov sp, r7 8001562: b002 add sp, #8 8001564: bd80 pop {r7, pc} 08001566 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001566: b580 push {r7, lr} 8001568: b082 sub sp, #8 800156a: af00 add r7, sp, #0 800156c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800156e: 687b ldr r3, [r7, #4] 8001570: 0018 movs r0, r3 8001572: f7ff ffaf bl 80014d4 8001576: 0003 movs r3, r0 } 8001578: 0018 movs r0, r3 800157a: 46bd mov sp, r7 800157c: b002 add sp, #8 800157e: bd80 pop {r7, pc} 08001580 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001580: b580 push {r7, lr} 8001582: b086 sub sp, #24 8001584: af00 add r7, sp, #0 8001586: 6078 str r0, [r7, #4] 8001588: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800158a: 2300 movs r3, #0 800158c: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800158e: e14f b.n 8001830 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8001590: 683b ldr r3, [r7, #0] 8001592: 681b ldr r3, [r3, #0] 8001594: 2101 movs r1, #1 8001596: 697a ldr r2, [r7, #20] 8001598: 4091 lsls r1, r2 800159a: 000a movs r2, r1 800159c: 4013 ands r3, r2 800159e: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 80015a0: 68fb ldr r3, [r7, #12] 80015a2: 2b00 cmp r3, #0 80015a4: d100 bne.n 80015a8 80015a6: e140 b.n 800182a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 80015a8: 683b ldr r3, [r7, #0] 80015aa: 685b ldr r3, [r3, #4] 80015ac: 2203 movs r2, #3 80015ae: 4013 ands r3, r2 80015b0: 2b01 cmp r3, #1 80015b2: d005 beq.n 80015c0 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 80015b4: 683b ldr r3, [r7, #0] 80015b6: 685b ldr r3, [r3, #4] 80015b8: 2203 movs r2, #3 80015ba: 4013 ands r3, r2 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 80015bc: 2b02 cmp r3, #2 80015be: d130 bne.n 8001622 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80015c0: 687b ldr r3, [r7, #4] 80015c2: 689b ldr r3, [r3, #8] 80015c4: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 80015c6: 697b ldr r3, [r7, #20] 80015c8: 005b lsls r3, r3, #1 80015ca: 2203 movs r2, #3 80015cc: 409a lsls r2, r3 80015ce: 0013 movs r3, r2 80015d0: 43da mvns r2, r3 80015d2: 693b ldr r3, [r7, #16] 80015d4: 4013 ands r3, r2 80015d6: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 80015d8: 683b ldr r3, [r7, #0] 80015da: 68da ldr r2, [r3, #12] 80015dc: 697b ldr r3, [r7, #20] 80015de: 005b lsls r3, r3, #1 80015e0: 409a lsls r2, r3 80015e2: 0013 movs r3, r2 80015e4: 693a ldr r2, [r7, #16] 80015e6: 4313 orrs r3, r2 80015e8: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80015ea: 687b ldr r3, [r7, #4] 80015ec: 693a ldr r2, [r7, #16] 80015ee: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80015f0: 687b ldr r3, [r7, #4] 80015f2: 685b ldr r3, [r3, #4] 80015f4: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80015f6: 2201 movs r2, #1 80015f8: 697b ldr r3, [r7, #20] 80015fa: 409a lsls r2, r3 80015fc: 0013 movs r3, r2 80015fe: 43da mvns r2, r3 8001600: 693b ldr r3, [r7, #16] 8001602: 4013 ands r3, r2 8001604: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001606: 683b ldr r3, [r7, #0] 8001608: 685b ldr r3, [r3, #4] 800160a: 091b lsrs r3, r3, #4 800160c: 2201 movs r2, #1 800160e: 401a ands r2, r3 8001610: 697b ldr r3, [r7, #20] 8001612: 409a lsls r2, r3 8001614: 0013 movs r3, r2 8001616: 693a ldr r2, [r7, #16] 8001618: 4313 orrs r3, r2 800161a: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 800161c: 687b ldr r3, [r7, #4] 800161e: 693a ldr r2, [r7, #16] 8001620: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001622: 683b ldr r3, [r7, #0] 8001624: 685b ldr r3, [r3, #4] 8001626: 2203 movs r2, #3 8001628: 4013 ands r3, r2 800162a: 2b03 cmp r3, #3 800162c: d017 beq.n 800165e { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800162e: 687b ldr r3, [r7, #4] 8001630: 68db ldr r3, [r3, #12] 8001632: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 8001634: 697b ldr r3, [r7, #20] 8001636: 005b lsls r3, r3, #1 8001638: 2203 movs r2, #3 800163a: 409a lsls r2, r3 800163c: 0013 movs r3, r2 800163e: 43da mvns r2, r3 8001640: 693b ldr r3, [r7, #16] 8001642: 4013 ands r3, r2 8001644: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8001646: 683b ldr r3, [r7, #0] 8001648: 689a ldr r2, [r3, #8] 800164a: 697b ldr r3, [r7, #20] 800164c: 005b lsls r3, r3, #1 800164e: 409a lsls r2, r3 8001650: 0013 movs r3, r2 8001652: 693a ldr r2, [r7, #16] 8001654: 4313 orrs r3, r2 8001656: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001658: 687b ldr r3, [r7, #4] 800165a: 693a ldr r2, [r7, #16] 800165c: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800165e: 683b ldr r3, [r7, #0] 8001660: 685b ldr r3, [r3, #4] 8001662: 2203 movs r2, #3 8001664: 4013 ands r3, r2 8001666: 2b02 cmp r3, #2 8001668: d123 bne.n 80016b2 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 800166a: 697b ldr r3, [r7, #20] 800166c: 08da lsrs r2, r3, #3 800166e: 687b ldr r3, [r7, #4] 8001670: 3208 adds r2, #8 8001672: 0092 lsls r2, r2, #2 8001674: 58d3 ldr r3, [r2, r3] 8001676: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001678: 697b ldr r3, [r7, #20] 800167a: 2207 movs r2, #7 800167c: 4013 ands r3, r2 800167e: 009b lsls r3, r3, #2 8001680: 220f movs r2, #15 8001682: 409a lsls r2, r3 8001684: 0013 movs r3, r2 8001686: 43da mvns r2, r3 8001688: 693b ldr r3, [r7, #16] 800168a: 4013 ands r3, r2 800168c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 800168e: 683b ldr r3, [r7, #0] 8001690: 691a ldr r2, [r3, #16] 8001692: 697b ldr r3, [r7, #20] 8001694: 2107 movs r1, #7 8001696: 400b ands r3, r1 8001698: 009b lsls r3, r3, #2 800169a: 409a lsls r2, r3 800169c: 0013 movs r3, r2 800169e: 693a ldr r2, [r7, #16] 80016a0: 4313 orrs r3, r2 80016a2: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 80016a4: 697b ldr r3, [r7, #20] 80016a6: 08da lsrs r2, r3, #3 80016a8: 687b ldr r3, [r7, #4] 80016aa: 3208 adds r2, #8 80016ac: 0092 lsls r2, r2, #2 80016ae: 6939 ldr r1, [r7, #16] 80016b0: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80016b2: 687b ldr r3, [r7, #4] 80016b4: 681b ldr r3, [r3, #0] 80016b6: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 80016b8: 697b ldr r3, [r7, #20] 80016ba: 005b lsls r3, r3, #1 80016bc: 2203 movs r2, #3 80016be: 409a lsls r2, r3 80016c0: 0013 movs r3, r2 80016c2: 43da mvns r2, r3 80016c4: 693b ldr r3, [r7, #16] 80016c6: 4013 ands r3, r2 80016c8: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 80016ca: 683b ldr r3, [r7, #0] 80016cc: 685b ldr r3, [r3, #4] 80016ce: 2203 movs r2, #3 80016d0: 401a ands r2, r3 80016d2: 697b ldr r3, [r7, #20] 80016d4: 005b lsls r3, r3, #1 80016d6: 409a lsls r2, r3 80016d8: 0013 movs r3, r2 80016da: 693a ldr r2, [r7, #16] 80016dc: 4313 orrs r3, r2 80016de: 613b str r3, [r7, #16] GPIOx->MODER = temp; 80016e0: 687b ldr r3, [r7, #4] 80016e2: 693a ldr r2, [r7, #16] 80016e4: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 80016e6: 683b ldr r3, [r7, #0] 80016e8: 685a ldr r2, [r3, #4] 80016ea: 23c0 movs r3, #192 ; 0xc0 80016ec: 029b lsls r3, r3, #10 80016ee: 4013 ands r3, r2 80016f0: d100 bne.n 80016f4 80016f2: e09a b.n 800182a { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80016f4: 4b54 ldr r3, [pc, #336] ; (8001848 ) 80016f6: 699a ldr r2, [r3, #24] 80016f8: 4b53 ldr r3, [pc, #332] ; (8001848 ) 80016fa: 2101 movs r1, #1 80016fc: 430a orrs r2, r1 80016fe: 619a str r2, [r3, #24] 8001700: 4b51 ldr r3, [pc, #324] ; (8001848 ) 8001702: 699b ldr r3, [r3, #24] 8001704: 2201 movs r2, #1 8001706: 4013 ands r3, r2 8001708: 60bb str r3, [r7, #8] 800170a: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 800170c: 4a4f ldr r2, [pc, #316] ; (800184c ) 800170e: 697b ldr r3, [r7, #20] 8001710: 089b lsrs r3, r3, #2 8001712: 3302 adds r3, #2 8001714: 009b lsls r3, r3, #2 8001716: 589b ldr r3, [r3, r2] 8001718: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 800171a: 697b ldr r3, [r7, #20] 800171c: 2203 movs r2, #3 800171e: 4013 ands r3, r2 8001720: 009b lsls r3, r3, #2 8001722: 220f movs r2, #15 8001724: 409a lsls r2, r3 8001726: 0013 movs r3, r2 8001728: 43da mvns r2, r3 800172a: 693b ldr r3, [r7, #16] 800172c: 4013 ands r3, r2 800172e: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8001730: 687a ldr r2, [r7, #4] 8001732: 2390 movs r3, #144 ; 0x90 8001734: 05db lsls r3, r3, #23 8001736: 429a cmp r2, r3 8001738: d013 beq.n 8001762 800173a: 687b ldr r3, [r7, #4] 800173c: 4a44 ldr r2, [pc, #272] ; (8001850 ) 800173e: 4293 cmp r3, r2 8001740: d00d beq.n 800175e 8001742: 687b ldr r3, [r7, #4] 8001744: 4a43 ldr r2, [pc, #268] ; (8001854 ) 8001746: 4293 cmp r3, r2 8001748: d007 beq.n 800175a 800174a: 687b ldr r3, [r7, #4] 800174c: 4a42 ldr r2, [pc, #264] ; (8001858 ) 800174e: 4293 cmp r3, r2 8001750: d101 bne.n 8001756 8001752: 2303 movs r3, #3 8001754: e006 b.n 8001764 8001756: 2305 movs r3, #5 8001758: e004 b.n 8001764 800175a: 2302 movs r3, #2 800175c: e002 b.n 8001764 800175e: 2301 movs r3, #1 8001760: e000 b.n 8001764 8001762: 2300 movs r3, #0 8001764: 697a ldr r2, [r7, #20] 8001766: 2103 movs r1, #3 8001768: 400a ands r2, r1 800176a: 0092 lsls r2, r2, #2 800176c: 4093 lsls r3, r2 800176e: 693a ldr r2, [r7, #16] 8001770: 4313 orrs r3, r2 8001772: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8001774: 4935 ldr r1, [pc, #212] ; (800184c ) 8001776: 697b ldr r3, [r7, #20] 8001778: 089b lsrs r3, r3, #2 800177a: 3302 adds r3, #2 800177c: 009b lsls r3, r3, #2 800177e: 693a ldr r2, [r7, #16] 8001780: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001782: 4b36 ldr r3, [pc, #216] ; (800185c ) 8001784: 681b ldr r3, [r3, #0] 8001786: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001788: 68fb ldr r3, [r7, #12] 800178a: 43da mvns r2, r3 800178c: 693b ldr r3, [r7, #16] 800178e: 4013 ands r3, r2 8001790: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8001792: 683b ldr r3, [r7, #0] 8001794: 685a ldr r2, [r3, #4] 8001796: 2380 movs r3, #128 ; 0x80 8001798: 025b lsls r3, r3, #9 800179a: 4013 ands r3, r2 800179c: d003 beq.n 80017a6 { temp |= iocurrent; 800179e: 693a ldr r2, [r7, #16] 80017a0: 68fb ldr r3, [r7, #12] 80017a2: 4313 orrs r3, r2 80017a4: 613b str r3, [r7, #16] } EXTI->IMR = temp; 80017a6: 4b2d ldr r3, [pc, #180] ; (800185c ) 80017a8: 693a ldr r2, [r7, #16] 80017aa: 601a str r2, [r3, #0] temp = EXTI->EMR; 80017ac: 4b2b ldr r3, [pc, #172] ; (800185c ) 80017ae: 685b ldr r3, [r3, #4] 80017b0: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80017b2: 68fb ldr r3, [r7, #12] 80017b4: 43da mvns r2, r3 80017b6: 693b ldr r3, [r7, #16] 80017b8: 4013 ands r3, r2 80017ba: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 80017bc: 683b ldr r3, [r7, #0] 80017be: 685a ldr r2, [r3, #4] 80017c0: 2380 movs r3, #128 ; 0x80 80017c2: 029b lsls r3, r3, #10 80017c4: 4013 ands r3, r2 80017c6: d003 beq.n 80017d0 { temp |= iocurrent; 80017c8: 693a ldr r2, [r7, #16] 80017ca: 68fb ldr r3, [r7, #12] 80017cc: 4313 orrs r3, r2 80017ce: 613b str r3, [r7, #16] } EXTI->EMR = temp; 80017d0: 4b22 ldr r3, [pc, #136] ; (800185c ) 80017d2: 693a ldr r2, [r7, #16] 80017d4: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 80017d6: 4b21 ldr r3, [pc, #132] ; (800185c ) 80017d8: 689b ldr r3, [r3, #8] 80017da: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80017dc: 68fb ldr r3, [r7, #12] 80017de: 43da mvns r2, r3 80017e0: 693b ldr r3, [r7, #16] 80017e2: 4013 ands r3, r2 80017e4: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 80017e6: 683b ldr r3, [r7, #0] 80017e8: 685a ldr r2, [r3, #4] 80017ea: 2380 movs r3, #128 ; 0x80 80017ec: 035b lsls r3, r3, #13 80017ee: 4013 ands r3, r2 80017f0: d003 beq.n 80017fa { temp |= iocurrent; 80017f2: 693a ldr r2, [r7, #16] 80017f4: 68fb ldr r3, [r7, #12] 80017f6: 4313 orrs r3, r2 80017f8: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 80017fa: 4b18 ldr r3, [pc, #96] ; (800185c ) 80017fc: 693a ldr r2, [r7, #16] 80017fe: 609a str r2, [r3, #8] temp = EXTI->FTSR; 8001800: 4b16 ldr r3, [pc, #88] ; (800185c ) 8001802: 68db ldr r3, [r3, #12] 8001804: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001806: 68fb ldr r3, [r7, #12] 8001808: 43da mvns r2, r3 800180a: 693b ldr r3, [r7, #16] 800180c: 4013 ands r3, r2 800180e: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8001810: 683b ldr r3, [r7, #0] 8001812: 685a ldr r2, [r3, #4] 8001814: 2380 movs r3, #128 ; 0x80 8001816: 039b lsls r3, r3, #14 8001818: 4013 ands r3, r2 800181a: d003 beq.n 8001824 { temp |= iocurrent; 800181c: 693a ldr r2, [r7, #16] 800181e: 68fb ldr r3, [r7, #12] 8001820: 4313 orrs r3, r2 8001822: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8001824: 4b0d ldr r3, [pc, #52] ; (800185c ) 8001826: 693a ldr r2, [r7, #16] 8001828: 60da str r2, [r3, #12] } } position++; 800182a: 697b ldr r3, [r7, #20] 800182c: 3301 adds r3, #1 800182e: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8001830: 683b ldr r3, [r7, #0] 8001832: 681a ldr r2, [r3, #0] 8001834: 697b ldr r3, [r7, #20] 8001836: 40da lsrs r2, r3 8001838: 1e13 subs r3, r2, #0 800183a: d000 beq.n 800183e 800183c: e6a8 b.n 8001590 } } 800183e: 46c0 nop ; (mov r8, r8) 8001840: 46c0 nop ; (mov r8, r8) 8001842: 46bd mov sp, r7 8001844: b006 add sp, #24 8001846: bd80 pop {r7, pc} 8001848: 40021000 .word 0x40021000 800184c: 40010000 .word 0x40010000 8001850: 48000400 .word 0x48000400 8001854: 48000800 .word 0x48000800 8001858: 48000c00 .word 0x48000c00 800185c: 40010400 .word 0x40010400 08001860 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001860: b580 push {r7, lr} 8001862: b084 sub sp, #16 8001864: af00 add r7, sp, #0 8001866: 6078 str r0, [r7, #4] 8001868: 000a movs r2, r1 800186a: 1cbb adds r3, r7, #2 800186c: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800186e: 687b ldr r3, [r7, #4] 8001870: 691b ldr r3, [r3, #16] 8001872: 1cba adds r2, r7, #2 8001874: 8812 ldrh r2, [r2, #0] 8001876: 4013 ands r3, r2 8001878: d004 beq.n 8001884 { bitstatus = GPIO_PIN_SET; 800187a: 230f movs r3, #15 800187c: 18fb adds r3, r7, r3 800187e: 2201 movs r2, #1 8001880: 701a strb r2, [r3, #0] 8001882: e003 b.n 800188c } else { bitstatus = GPIO_PIN_RESET; 8001884: 230f movs r3, #15 8001886: 18fb adds r3, r7, r3 8001888: 2200 movs r2, #0 800188a: 701a strb r2, [r3, #0] } return bitstatus; 800188c: 230f movs r3, #15 800188e: 18fb adds r3, r7, r3 8001890: 781b ldrb r3, [r3, #0] } 8001892: 0018 movs r0, r3 8001894: 46bd mov sp, r7 8001896: b004 add sp, #16 8001898: bd80 pop {r7, pc} 0800189a : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800189a: b580 push {r7, lr} 800189c: b082 sub sp, #8 800189e: af00 add r7, sp, #0 80018a0: 6078 str r0, [r7, #4] 80018a2: 0008 movs r0, r1 80018a4: 0011 movs r1, r2 80018a6: 1cbb adds r3, r7, #2 80018a8: 1c02 adds r2, r0, #0 80018aa: 801a strh r2, [r3, #0] 80018ac: 1c7b adds r3, r7, #1 80018ae: 1c0a adds r2, r1, #0 80018b0: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80018b2: 1c7b adds r3, r7, #1 80018b4: 781b ldrb r3, [r3, #0] 80018b6: 2b00 cmp r3, #0 80018b8: d004 beq.n 80018c4 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 80018ba: 1cbb adds r3, r7, #2 80018bc: 881a ldrh r2, [r3, #0] 80018be: 687b ldr r3, [r7, #4] 80018c0: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 80018c2: e003 b.n 80018cc GPIOx->BRR = (uint32_t)GPIO_Pin; 80018c4: 1cbb adds r3, r7, #2 80018c6: 881a ldrh r2, [r3, #0] 80018c8: 687b ldr r3, [r7, #4] 80018ca: 629a str r2, [r3, #40] ; 0x28 } 80018cc: 46c0 nop ; (mov r8, r8) 80018ce: 46bd mov sp, r7 80018d0: b002 add sp, #8 80018d2: bd80 pop {r7, pc} 080018d4 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 80018d4: b580 push {r7, lr} 80018d6: b082 sub sp, #8 80018d8: af00 add r7, sp, #0 80018da: 0002 movs r2, r0 80018dc: 1dbb adds r3, r7, #6 80018de: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 80018e0: 4b09 ldr r3, [pc, #36] ; (8001908 ) 80018e2: 695b ldr r3, [r3, #20] 80018e4: 1dba adds r2, r7, #6 80018e6: 8812 ldrh r2, [r2, #0] 80018e8: 4013 ands r3, r2 80018ea: d008 beq.n 80018fe { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 80018ec: 4b06 ldr r3, [pc, #24] ; (8001908 ) 80018ee: 1dba adds r2, r7, #6 80018f0: 8812 ldrh r2, [r2, #0] 80018f2: 615a str r2, [r3, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 80018f4: 1dbb adds r3, r7, #6 80018f6: 881b ldrh r3, [r3, #0] 80018f8: 0018 movs r0, r3 80018fa: f002 fa83 bl 8003e04 } } 80018fe: 46c0 nop ; (mov r8, r8) 8001900: 46bd mov sp, r7 8001902: b002 add sp, #8 8001904: bd80 pop {r7, pc} 8001906: 46c0 nop ; (mov r8, r8) 8001908: 40010400 .word 0x40010400 0800190c : * @note For all I2C2 pins fast mode plus driving capability can be enabled * only by using I2C_FASTMODEPLUS_I2C2 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) { 800190c: b580 push {r7, lr} 800190e: b084 sub sp, #16 8001910: af00 add r7, sp, #0 8001912: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001914: 4b0a ldr r3, [pc, #40] ; (8001940 ) 8001916: 699a ldr r2, [r3, #24] 8001918: 4b09 ldr r3, [pc, #36] ; (8001940 ) 800191a: 2101 movs r1, #1 800191c: 430a orrs r2, r1 800191e: 619a str r2, [r3, #24] 8001920: 4b07 ldr r3, [pc, #28] ; (8001940 ) 8001922: 699b ldr r3, [r3, #24] 8001924: 2201 movs r2, #1 8001926: 4013 ands r3, r2 8001928: 60fb str r3, [r7, #12] 800192a: 68fb ldr r3, [r7, #12] /* Enable fast mode plus driving capability for selected pin */ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 800192c: 4b05 ldr r3, [pc, #20] ; (8001944 ) 800192e: 6819 ldr r1, [r3, #0] 8001930: 4b04 ldr r3, [pc, #16] ; (8001944 ) 8001932: 687a ldr r2, [r7, #4] 8001934: 430a orrs r2, r1 8001936: 601a str r2, [r3, #0] } 8001938: 46c0 nop ; (mov r8, r8) 800193a: 46bd mov sp, r7 800193c: b004 add sp, #16 800193e: bd80 pop {r7, pc} 8001940: 40021000 .word 0x40021000 8001944: 40010000 .word 0x40010000 08001948 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001948: b580 push {r7, lr} 800194a: b088 sub sp, #32 800194c: af00 add r7, sp, #0 800194e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8001950: 687b ldr r3, [r7, #4] 8001952: 2b00 cmp r3, #0 8001954: d101 bne.n 800195a { return HAL_ERROR; 8001956: 2301 movs r3, #1 8001958: e301 b.n 8001f5e /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800195a: 687b ldr r3, [r7, #4] 800195c: 681b ldr r3, [r3, #0] 800195e: 2201 movs r2, #1 8001960: 4013 ands r3, r2 8001962: d100 bne.n 8001966 8001964: e08d b.n 8001a82 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8001966: 4bc3 ldr r3, [pc, #780] ; (8001c74 ) 8001968: 685b ldr r3, [r3, #4] 800196a: 220c movs r2, #12 800196c: 4013 ands r3, r2 800196e: 2b04 cmp r3, #4 8001970: d00e beq.n 8001990 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001972: 4bc0 ldr r3, [pc, #768] ; (8001c74 ) 8001974: 685b ldr r3, [r3, #4] 8001976: 220c movs r2, #12 8001978: 4013 ands r3, r2 800197a: 2b08 cmp r3, #8 800197c: d116 bne.n 80019ac 800197e: 4bbd ldr r3, [pc, #756] ; (8001c74 ) 8001980: 685a ldr r2, [r3, #4] 8001982: 2380 movs r3, #128 ; 0x80 8001984: 025b lsls r3, r3, #9 8001986: 401a ands r2, r3 8001988: 2380 movs r3, #128 ; 0x80 800198a: 025b lsls r3, r3, #9 800198c: 429a cmp r2, r3 800198e: d10d bne.n 80019ac { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001990: 4bb8 ldr r3, [pc, #736] ; (8001c74 ) 8001992: 681a ldr r2, [r3, #0] 8001994: 2380 movs r3, #128 ; 0x80 8001996: 029b lsls r3, r3, #10 8001998: 4013 ands r3, r2 800199a: d100 bne.n 800199e 800199c: e070 b.n 8001a80 800199e: 687b ldr r3, [r7, #4] 80019a0: 685b ldr r3, [r3, #4] 80019a2: 2b00 cmp r3, #0 80019a4: d000 beq.n 80019a8 80019a6: e06b b.n 8001a80 { return HAL_ERROR; 80019a8: 2301 movs r3, #1 80019aa: e2d8 b.n 8001f5e } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80019ac: 687b ldr r3, [r7, #4] 80019ae: 685b ldr r3, [r3, #4] 80019b0: 2b01 cmp r3, #1 80019b2: d107 bne.n 80019c4 80019b4: 4baf ldr r3, [pc, #700] ; (8001c74 ) 80019b6: 681a ldr r2, [r3, #0] 80019b8: 4bae ldr r3, [pc, #696] ; (8001c74 ) 80019ba: 2180 movs r1, #128 ; 0x80 80019bc: 0249 lsls r1, r1, #9 80019be: 430a orrs r2, r1 80019c0: 601a str r2, [r3, #0] 80019c2: e02f b.n 8001a24 80019c4: 687b ldr r3, [r7, #4] 80019c6: 685b ldr r3, [r3, #4] 80019c8: 2b00 cmp r3, #0 80019ca: d10c bne.n 80019e6 80019cc: 4ba9 ldr r3, [pc, #676] ; (8001c74 ) 80019ce: 681a ldr r2, [r3, #0] 80019d0: 4ba8 ldr r3, [pc, #672] ; (8001c74 ) 80019d2: 49a9 ldr r1, [pc, #676] ; (8001c78 ) 80019d4: 400a ands r2, r1 80019d6: 601a str r2, [r3, #0] 80019d8: 4ba6 ldr r3, [pc, #664] ; (8001c74 ) 80019da: 681a ldr r2, [r3, #0] 80019dc: 4ba5 ldr r3, [pc, #660] ; (8001c74 ) 80019de: 49a7 ldr r1, [pc, #668] ; (8001c7c ) 80019e0: 400a ands r2, r1 80019e2: 601a str r2, [r3, #0] 80019e4: e01e b.n 8001a24 80019e6: 687b ldr r3, [r7, #4] 80019e8: 685b ldr r3, [r3, #4] 80019ea: 2b05 cmp r3, #5 80019ec: d10e bne.n 8001a0c 80019ee: 4ba1 ldr r3, [pc, #644] ; (8001c74 ) 80019f0: 681a ldr r2, [r3, #0] 80019f2: 4ba0 ldr r3, [pc, #640] ; (8001c74 ) 80019f4: 2180 movs r1, #128 ; 0x80 80019f6: 02c9 lsls r1, r1, #11 80019f8: 430a orrs r2, r1 80019fa: 601a str r2, [r3, #0] 80019fc: 4b9d ldr r3, [pc, #628] ; (8001c74 ) 80019fe: 681a ldr r2, [r3, #0] 8001a00: 4b9c ldr r3, [pc, #624] ; (8001c74 ) 8001a02: 2180 movs r1, #128 ; 0x80 8001a04: 0249 lsls r1, r1, #9 8001a06: 430a orrs r2, r1 8001a08: 601a str r2, [r3, #0] 8001a0a: e00b b.n 8001a24 8001a0c: 4b99 ldr r3, [pc, #612] ; (8001c74 ) 8001a0e: 681a ldr r2, [r3, #0] 8001a10: 4b98 ldr r3, [pc, #608] ; (8001c74 ) 8001a12: 4999 ldr r1, [pc, #612] ; (8001c78 ) 8001a14: 400a ands r2, r1 8001a16: 601a str r2, [r3, #0] 8001a18: 4b96 ldr r3, [pc, #600] ; (8001c74 ) 8001a1a: 681a ldr r2, [r3, #0] 8001a1c: 4b95 ldr r3, [pc, #596] ; (8001c74 ) 8001a1e: 4997 ldr r1, [pc, #604] ; (8001c7c ) 8001a20: 400a ands r2, r1 8001a22: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001a24: 687b ldr r3, [r7, #4] 8001a26: 685b ldr r3, [r3, #4] 8001a28: 2b00 cmp r3, #0 8001a2a: d014 beq.n 8001a56 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a2c: f7fe ffec bl 8000a08 8001a30: 0003 movs r3, r0 8001a32: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001a34: e008 b.n 8001a48 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001a36: f7fe ffe7 bl 8000a08 8001a3a: 0002 movs r2, r0 8001a3c: 69bb ldr r3, [r7, #24] 8001a3e: 1ad3 subs r3, r2, r3 8001a40: 2b64 cmp r3, #100 ; 0x64 8001a42: d901 bls.n 8001a48 { return HAL_TIMEOUT; 8001a44: 2303 movs r3, #3 8001a46: e28a b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001a48: 4b8a ldr r3, [pc, #552] ; (8001c74 ) 8001a4a: 681a ldr r2, [r3, #0] 8001a4c: 2380 movs r3, #128 ; 0x80 8001a4e: 029b lsls r3, r3, #10 8001a50: 4013 ands r3, r2 8001a52: d0f0 beq.n 8001a36 8001a54: e015 b.n 8001a82 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001a56: f7fe ffd7 bl 8000a08 8001a5a: 0003 movs r3, r0 8001a5c: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001a5e: e008 b.n 8001a72 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001a60: f7fe ffd2 bl 8000a08 8001a64: 0002 movs r2, r0 8001a66: 69bb ldr r3, [r7, #24] 8001a68: 1ad3 subs r3, r2, r3 8001a6a: 2b64 cmp r3, #100 ; 0x64 8001a6c: d901 bls.n 8001a72 { return HAL_TIMEOUT; 8001a6e: 2303 movs r3, #3 8001a70: e275 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001a72: 4b80 ldr r3, [pc, #512] ; (8001c74 ) 8001a74: 681a ldr r2, [r3, #0] 8001a76: 2380 movs r3, #128 ; 0x80 8001a78: 029b lsls r3, r3, #10 8001a7a: 4013 ands r3, r2 8001a7c: d1f0 bne.n 8001a60 8001a7e: e000 b.n 8001a82 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001a80: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001a82: 687b ldr r3, [r7, #4] 8001a84: 681b ldr r3, [r3, #0] 8001a86: 2202 movs r2, #2 8001a88: 4013 ands r3, r2 8001a8a: d100 bne.n 8001a8e 8001a8c: e069 b.n 8001b62 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001a8e: 4b79 ldr r3, [pc, #484] ; (8001c74 ) 8001a90: 685b ldr r3, [r3, #4] 8001a92: 220c movs r2, #12 8001a94: 4013 ands r3, r2 8001a96: d00b beq.n 8001ab0 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8001a98: 4b76 ldr r3, [pc, #472] ; (8001c74 ) 8001a9a: 685b ldr r3, [r3, #4] 8001a9c: 220c movs r2, #12 8001a9e: 4013 ands r3, r2 8001aa0: 2b08 cmp r3, #8 8001aa2: d11c bne.n 8001ade 8001aa4: 4b73 ldr r3, [pc, #460] ; (8001c74 ) 8001aa6: 685a ldr r2, [r3, #4] 8001aa8: 2380 movs r3, #128 ; 0x80 8001aaa: 025b lsls r3, r3, #9 8001aac: 4013 ands r3, r2 8001aae: d116 bne.n 8001ade { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001ab0: 4b70 ldr r3, [pc, #448] ; (8001c74 ) 8001ab2: 681b ldr r3, [r3, #0] 8001ab4: 2202 movs r2, #2 8001ab6: 4013 ands r3, r2 8001ab8: d005 beq.n 8001ac6 8001aba: 687b ldr r3, [r7, #4] 8001abc: 68db ldr r3, [r3, #12] 8001abe: 2b01 cmp r3, #1 8001ac0: d001 beq.n 8001ac6 { return HAL_ERROR; 8001ac2: 2301 movs r3, #1 8001ac4: e24b b.n 8001f5e } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001ac6: 4b6b ldr r3, [pc, #428] ; (8001c74 ) 8001ac8: 681b ldr r3, [r3, #0] 8001aca: 22f8 movs r2, #248 ; 0xf8 8001acc: 4393 bics r3, r2 8001ace: 0019 movs r1, r3 8001ad0: 687b ldr r3, [r7, #4] 8001ad2: 691b ldr r3, [r3, #16] 8001ad4: 00da lsls r2, r3, #3 8001ad6: 4b67 ldr r3, [pc, #412] ; (8001c74 ) 8001ad8: 430a orrs r2, r1 8001ada: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001adc: e041 b.n 8001b62 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001ade: 687b ldr r3, [r7, #4] 8001ae0: 68db ldr r3, [r3, #12] 8001ae2: 2b00 cmp r3, #0 8001ae4: d024 beq.n 8001b30 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001ae6: 4b63 ldr r3, [pc, #396] ; (8001c74 ) 8001ae8: 681a ldr r2, [r3, #0] 8001aea: 4b62 ldr r3, [pc, #392] ; (8001c74 ) 8001aec: 2101 movs r1, #1 8001aee: 430a orrs r2, r1 8001af0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001af2: f7fe ff89 bl 8000a08 8001af6: 0003 movs r3, r0 8001af8: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001afa: e008 b.n 8001b0e { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001afc: f7fe ff84 bl 8000a08 8001b00: 0002 movs r2, r0 8001b02: 69bb ldr r3, [r7, #24] 8001b04: 1ad3 subs r3, r2, r3 8001b06: 2b02 cmp r3, #2 8001b08: d901 bls.n 8001b0e { return HAL_TIMEOUT; 8001b0a: 2303 movs r3, #3 8001b0c: e227 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001b0e: 4b59 ldr r3, [pc, #356] ; (8001c74 ) 8001b10: 681b ldr r3, [r3, #0] 8001b12: 2202 movs r2, #2 8001b14: 4013 ands r3, r2 8001b16: d0f1 beq.n 8001afc } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001b18: 4b56 ldr r3, [pc, #344] ; (8001c74 ) 8001b1a: 681b ldr r3, [r3, #0] 8001b1c: 22f8 movs r2, #248 ; 0xf8 8001b1e: 4393 bics r3, r2 8001b20: 0019 movs r1, r3 8001b22: 687b ldr r3, [r7, #4] 8001b24: 691b ldr r3, [r3, #16] 8001b26: 00da lsls r2, r3, #3 8001b28: 4b52 ldr r3, [pc, #328] ; (8001c74 ) 8001b2a: 430a orrs r2, r1 8001b2c: 601a str r2, [r3, #0] 8001b2e: e018 b.n 8001b62 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001b30: 4b50 ldr r3, [pc, #320] ; (8001c74 ) 8001b32: 681a ldr r2, [r3, #0] 8001b34: 4b4f ldr r3, [pc, #316] ; (8001c74 ) 8001b36: 2101 movs r1, #1 8001b38: 438a bics r2, r1 8001b3a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b3c: f7fe ff64 bl 8000a08 8001b40: 0003 movs r3, r0 8001b42: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001b44: e008 b.n 8001b58 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001b46: f7fe ff5f bl 8000a08 8001b4a: 0002 movs r2, r0 8001b4c: 69bb ldr r3, [r7, #24] 8001b4e: 1ad3 subs r3, r2, r3 8001b50: 2b02 cmp r3, #2 8001b52: d901 bls.n 8001b58 { return HAL_TIMEOUT; 8001b54: 2303 movs r3, #3 8001b56: e202 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001b58: 4b46 ldr r3, [pc, #280] ; (8001c74 ) 8001b5a: 681b ldr r3, [r3, #0] 8001b5c: 2202 movs r2, #2 8001b5e: 4013 ands r3, r2 8001b60: d1f1 bne.n 8001b46 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001b62: 687b ldr r3, [r7, #4] 8001b64: 681b ldr r3, [r3, #0] 8001b66: 2208 movs r2, #8 8001b68: 4013 ands r3, r2 8001b6a: d036 beq.n 8001bda { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001b6c: 687b ldr r3, [r7, #4] 8001b6e: 69db ldr r3, [r3, #28] 8001b70: 2b00 cmp r3, #0 8001b72: d019 beq.n 8001ba8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001b74: 4b3f ldr r3, [pc, #252] ; (8001c74 ) 8001b76: 6a5a ldr r2, [r3, #36] ; 0x24 8001b78: 4b3e ldr r3, [pc, #248] ; (8001c74 ) 8001b7a: 2101 movs r1, #1 8001b7c: 430a orrs r2, r1 8001b7e: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b80: f7fe ff42 bl 8000a08 8001b84: 0003 movs r3, r0 8001b86: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001b88: e008 b.n 8001b9c { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001b8a: f7fe ff3d bl 8000a08 8001b8e: 0002 movs r2, r0 8001b90: 69bb ldr r3, [r7, #24] 8001b92: 1ad3 subs r3, r2, r3 8001b94: 2b02 cmp r3, #2 8001b96: d901 bls.n 8001b9c { return HAL_TIMEOUT; 8001b98: 2303 movs r3, #3 8001b9a: e1e0 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001b9c: 4b35 ldr r3, [pc, #212] ; (8001c74 ) 8001b9e: 6a5b ldr r3, [r3, #36] ; 0x24 8001ba0: 2202 movs r2, #2 8001ba2: 4013 ands r3, r2 8001ba4: d0f1 beq.n 8001b8a 8001ba6: e018 b.n 8001bda } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001ba8: 4b32 ldr r3, [pc, #200] ; (8001c74 ) 8001baa: 6a5a ldr r2, [r3, #36] ; 0x24 8001bac: 4b31 ldr r3, [pc, #196] ; (8001c74 ) 8001bae: 2101 movs r1, #1 8001bb0: 438a bics r2, r1 8001bb2: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001bb4: f7fe ff28 bl 8000a08 8001bb8: 0003 movs r3, r0 8001bba: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001bbc: e008 b.n 8001bd0 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001bbe: f7fe ff23 bl 8000a08 8001bc2: 0002 movs r2, r0 8001bc4: 69bb ldr r3, [r7, #24] 8001bc6: 1ad3 subs r3, r2, r3 8001bc8: 2b02 cmp r3, #2 8001bca: d901 bls.n 8001bd0 { return HAL_TIMEOUT; 8001bcc: 2303 movs r3, #3 8001bce: e1c6 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001bd0: 4b28 ldr r3, [pc, #160] ; (8001c74 ) 8001bd2: 6a5b ldr r3, [r3, #36] ; 0x24 8001bd4: 2202 movs r2, #2 8001bd6: 4013 ands r3, r2 8001bd8: d1f1 bne.n 8001bbe } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001bda: 687b ldr r3, [r7, #4] 8001bdc: 681b ldr r3, [r3, #0] 8001bde: 2204 movs r2, #4 8001be0: 4013 ands r3, r2 8001be2: d100 bne.n 8001be6 8001be4: e0b4 b.n 8001d50 { FlagStatus pwrclkchanged = RESET; 8001be6: 201f movs r0, #31 8001be8: 183b adds r3, r7, r0 8001bea: 2200 movs r2, #0 8001bec: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001bee: 4b21 ldr r3, [pc, #132] ; (8001c74 ) 8001bf0: 69da ldr r2, [r3, #28] 8001bf2: 2380 movs r3, #128 ; 0x80 8001bf4: 055b lsls r3, r3, #21 8001bf6: 4013 ands r3, r2 8001bf8: d110 bne.n 8001c1c { __HAL_RCC_PWR_CLK_ENABLE(); 8001bfa: 4b1e ldr r3, [pc, #120] ; (8001c74 ) 8001bfc: 69da ldr r2, [r3, #28] 8001bfe: 4b1d ldr r3, [pc, #116] ; (8001c74 ) 8001c00: 2180 movs r1, #128 ; 0x80 8001c02: 0549 lsls r1, r1, #21 8001c04: 430a orrs r2, r1 8001c06: 61da str r2, [r3, #28] 8001c08: 4b1a ldr r3, [pc, #104] ; (8001c74 ) 8001c0a: 69da ldr r2, [r3, #28] 8001c0c: 2380 movs r3, #128 ; 0x80 8001c0e: 055b lsls r3, r3, #21 8001c10: 4013 ands r3, r2 8001c12: 60fb str r3, [r7, #12] 8001c14: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8001c16: 183b adds r3, r7, r0 8001c18: 2201 movs r2, #1 8001c1a: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001c1c: 4b18 ldr r3, [pc, #96] ; (8001c80 ) 8001c1e: 681a ldr r2, [r3, #0] 8001c20: 2380 movs r3, #128 ; 0x80 8001c22: 005b lsls r3, r3, #1 8001c24: 4013 ands r3, r2 8001c26: d11a bne.n 8001c5e { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001c28: 4b15 ldr r3, [pc, #84] ; (8001c80 ) 8001c2a: 681a ldr r2, [r3, #0] 8001c2c: 4b14 ldr r3, [pc, #80] ; (8001c80 ) 8001c2e: 2180 movs r1, #128 ; 0x80 8001c30: 0049 lsls r1, r1, #1 8001c32: 430a orrs r2, r1 8001c34: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001c36: f7fe fee7 bl 8000a08 8001c3a: 0003 movs r3, r0 8001c3c: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001c3e: e008 b.n 8001c52 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001c40: f7fe fee2 bl 8000a08 8001c44: 0002 movs r2, r0 8001c46: 69bb ldr r3, [r7, #24] 8001c48: 1ad3 subs r3, r2, r3 8001c4a: 2b64 cmp r3, #100 ; 0x64 8001c4c: d901 bls.n 8001c52 { return HAL_TIMEOUT; 8001c4e: 2303 movs r3, #3 8001c50: e185 b.n 8001f5e while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001c52: 4b0b ldr r3, [pc, #44] ; (8001c80 ) 8001c54: 681a ldr r2, [r3, #0] 8001c56: 2380 movs r3, #128 ; 0x80 8001c58: 005b lsls r3, r3, #1 8001c5a: 4013 ands r3, r2 8001c5c: d0f0 beq.n 8001c40 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001c5e: 687b ldr r3, [r7, #4] 8001c60: 689b ldr r3, [r3, #8] 8001c62: 2b01 cmp r3, #1 8001c64: d10e bne.n 8001c84 8001c66: 4b03 ldr r3, [pc, #12] ; (8001c74 ) 8001c68: 6a1a ldr r2, [r3, #32] 8001c6a: 4b02 ldr r3, [pc, #8] ; (8001c74 ) 8001c6c: 2101 movs r1, #1 8001c6e: 430a orrs r2, r1 8001c70: 621a str r2, [r3, #32] 8001c72: e035 b.n 8001ce0 8001c74: 40021000 .word 0x40021000 8001c78: fffeffff .word 0xfffeffff 8001c7c: fffbffff .word 0xfffbffff 8001c80: 40007000 .word 0x40007000 8001c84: 687b ldr r3, [r7, #4] 8001c86: 689b ldr r3, [r3, #8] 8001c88: 2b00 cmp r3, #0 8001c8a: d10c bne.n 8001ca6 8001c8c: 4bb6 ldr r3, [pc, #728] ; (8001f68 ) 8001c8e: 6a1a ldr r2, [r3, #32] 8001c90: 4bb5 ldr r3, [pc, #724] ; (8001f68 ) 8001c92: 2101 movs r1, #1 8001c94: 438a bics r2, r1 8001c96: 621a str r2, [r3, #32] 8001c98: 4bb3 ldr r3, [pc, #716] ; (8001f68 ) 8001c9a: 6a1a ldr r2, [r3, #32] 8001c9c: 4bb2 ldr r3, [pc, #712] ; (8001f68 ) 8001c9e: 2104 movs r1, #4 8001ca0: 438a bics r2, r1 8001ca2: 621a str r2, [r3, #32] 8001ca4: e01c b.n 8001ce0 8001ca6: 687b ldr r3, [r7, #4] 8001ca8: 689b ldr r3, [r3, #8] 8001caa: 2b05 cmp r3, #5 8001cac: d10c bne.n 8001cc8 8001cae: 4bae ldr r3, [pc, #696] ; (8001f68 ) 8001cb0: 6a1a ldr r2, [r3, #32] 8001cb2: 4bad ldr r3, [pc, #692] ; (8001f68 ) 8001cb4: 2104 movs r1, #4 8001cb6: 430a orrs r2, r1 8001cb8: 621a str r2, [r3, #32] 8001cba: 4bab ldr r3, [pc, #684] ; (8001f68 ) 8001cbc: 6a1a ldr r2, [r3, #32] 8001cbe: 4baa ldr r3, [pc, #680] ; (8001f68 ) 8001cc0: 2101 movs r1, #1 8001cc2: 430a orrs r2, r1 8001cc4: 621a str r2, [r3, #32] 8001cc6: e00b b.n 8001ce0 8001cc8: 4ba7 ldr r3, [pc, #668] ; (8001f68 ) 8001cca: 6a1a ldr r2, [r3, #32] 8001ccc: 4ba6 ldr r3, [pc, #664] ; (8001f68 ) 8001cce: 2101 movs r1, #1 8001cd0: 438a bics r2, r1 8001cd2: 621a str r2, [r3, #32] 8001cd4: 4ba4 ldr r3, [pc, #656] ; (8001f68 ) 8001cd6: 6a1a ldr r2, [r3, #32] 8001cd8: 4ba3 ldr r3, [pc, #652] ; (8001f68 ) 8001cda: 2104 movs r1, #4 8001cdc: 438a bics r2, r1 8001cde: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001ce0: 687b ldr r3, [r7, #4] 8001ce2: 689b ldr r3, [r3, #8] 8001ce4: 2b00 cmp r3, #0 8001ce6: d014 beq.n 8001d12 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001ce8: f7fe fe8e bl 8000a08 8001cec: 0003 movs r3, r0 8001cee: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001cf0: e009 b.n 8001d06 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001cf2: f7fe fe89 bl 8000a08 8001cf6: 0002 movs r2, r0 8001cf8: 69bb ldr r3, [r7, #24] 8001cfa: 1ad3 subs r3, r2, r3 8001cfc: 4a9b ldr r2, [pc, #620] ; (8001f6c ) 8001cfe: 4293 cmp r3, r2 8001d00: d901 bls.n 8001d06 { return HAL_TIMEOUT; 8001d02: 2303 movs r3, #3 8001d04: e12b b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001d06: 4b98 ldr r3, [pc, #608] ; (8001f68 ) 8001d08: 6a1b ldr r3, [r3, #32] 8001d0a: 2202 movs r2, #2 8001d0c: 4013 ands r3, r2 8001d0e: d0f0 beq.n 8001cf2 8001d10: e013 b.n 8001d3a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001d12: f7fe fe79 bl 8000a08 8001d16: 0003 movs r3, r0 8001d18: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001d1a: e009 b.n 8001d30 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001d1c: f7fe fe74 bl 8000a08 8001d20: 0002 movs r2, r0 8001d22: 69bb ldr r3, [r7, #24] 8001d24: 1ad3 subs r3, r2, r3 8001d26: 4a91 ldr r2, [pc, #580] ; (8001f6c ) 8001d28: 4293 cmp r3, r2 8001d2a: d901 bls.n 8001d30 { return HAL_TIMEOUT; 8001d2c: 2303 movs r3, #3 8001d2e: e116 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001d30: 4b8d ldr r3, [pc, #564] ; (8001f68 ) 8001d32: 6a1b ldr r3, [r3, #32] 8001d34: 2202 movs r2, #2 8001d36: 4013 ands r3, r2 8001d38: d1f0 bne.n 8001d1c } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8001d3a: 231f movs r3, #31 8001d3c: 18fb adds r3, r7, r3 8001d3e: 781b ldrb r3, [r3, #0] 8001d40: 2b01 cmp r3, #1 8001d42: d105 bne.n 8001d50 { __HAL_RCC_PWR_CLK_DISABLE(); 8001d44: 4b88 ldr r3, [pc, #544] ; (8001f68 ) 8001d46: 69da ldr r2, [r3, #28] 8001d48: 4b87 ldr r3, [pc, #540] ; (8001f68 ) 8001d4a: 4989 ldr r1, [pc, #548] ; (8001f70 ) 8001d4c: 400a ands r2, r1 8001d4e: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8001d50: 687b ldr r3, [r7, #4] 8001d52: 681b ldr r3, [r3, #0] 8001d54: 2210 movs r2, #16 8001d56: 4013 ands r3, r2 8001d58: d063 beq.n 8001e22 /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 8001d5a: 687b ldr r3, [r7, #4] 8001d5c: 695b ldr r3, [r3, #20] 8001d5e: 2b01 cmp r3, #1 8001d60: d12a bne.n 8001db8 { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001d62: 4b81 ldr r3, [pc, #516] ; (8001f68 ) 8001d64: 6b5a ldr r2, [r3, #52] ; 0x34 8001d66: 4b80 ldr r3, [pc, #512] ; (8001f68 ) 8001d68: 2104 movs r1, #4 8001d6a: 430a orrs r2, r1 8001d6c: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 8001d6e: 4b7e ldr r3, [pc, #504] ; (8001f68 ) 8001d70: 6b5a ldr r2, [r3, #52] ; 0x34 8001d72: 4b7d ldr r3, [pc, #500] ; (8001f68 ) 8001d74: 2101 movs r1, #1 8001d76: 430a orrs r2, r1 8001d78: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001d7a: f7fe fe45 bl 8000a08 8001d7e: 0003 movs r3, r0 8001d80: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001d82: e008 b.n 8001d96 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001d84: f7fe fe40 bl 8000a08 8001d88: 0002 movs r2, r0 8001d8a: 69bb ldr r3, [r7, #24] 8001d8c: 1ad3 subs r3, r2, r3 8001d8e: 2b02 cmp r3, #2 8001d90: d901 bls.n 8001d96 { return HAL_TIMEOUT; 8001d92: 2303 movs r3, #3 8001d94: e0e3 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8001d96: 4b74 ldr r3, [pc, #464] ; (8001f68 ) 8001d98: 6b5b ldr r3, [r3, #52] ; 0x34 8001d9a: 2202 movs r2, #2 8001d9c: 4013 ands r3, r2 8001d9e: d0f1 beq.n 8001d84 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001da0: 4b71 ldr r3, [pc, #452] ; (8001f68 ) 8001da2: 6b5b ldr r3, [r3, #52] ; 0x34 8001da4: 22f8 movs r2, #248 ; 0xf8 8001da6: 4393 bics r3, r2 8001da8: 0019 movs r1, r3 8001daa: 687b ldr r3, [r7, #4] 8001dac: 699b ldr r3, [r3, #24] 8001dae: 00da lsls r2, r3, #3 8001db0: 4b6d ldr r3, [pc, #436] ; (8001f68 ) 8001db2: 430a orrs r2, r1 8001db4: 635a str r2, [r3, #52] ; 0x34 8001db6: e034 b.n 8001e22 } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8001db8: 687b ldr r3, [r7, #4] 8001dba: 695b ldr r3, [r3, #20] 8001dbc: 3305 adds r3, #5 8001dbe: d111 bne.n 8001de4 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8001dc0: 4b69 ldr r3, [pc, #420] ; (8001f68 ) 8001dc2: 6b5a ldr r2, [r3, #52] ; 0x34 8001dc4: 4b68 ldr r3, [pc, #416] ; (8001f68 ) 8001dc6: 2104 movs r1, #4 8001dc8: 438a bics r2, r1 8001dca: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8001dcc: 4b66 ldr r3, [pc, #408] ; (8001f68 ) 8001dce: 6b5b ldr r3, [r3, #52] ; 0x34 8001dd0: 22f8 movs r2, #248 ; 0xf8 8001dd2: 4393 bics r3, r2 8001dd4: 0019 movs r1, r3 8001dd6: 687b ldr r3, [r7, #4] 8001dd8: 699b ldr r3, [r3, #24] 8001dda: 00da lsls r2, r3, #3 8001ddc: 4b62 ldr r3, [pc, #392] ; (8001f68 ) 8001dde: 430a orrs r2, r1 8001de0: 635a str r2, [r3, #52] ; 0x34 8001de2: e01e b.n 8001e22 } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8001de4: 4b60 ldr r3, [pc, #384] ; (8001f68 ) 8001de6: 6b5a ldr r2, [r3, #52] ; 0x34 8001de8: 4b5f ldr r3, [pc, #380] ; (8001f68 ) 8001dea: 2104 movs r1, #4 8001dec: 430a orrs r2, r1 8001dee: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8001df0: 4b5d ldr r3, [pc, #372] ; (8001f68 ) 8001df2: 6b5a ldr r2, [r3, #52] ; 0x34 8001df4: 4b5c ldr r3, [pc, #368] ; (8001f68 ) 8001df6: 2101 movs r1, #1 8001df8: 438a bics r2, r1 8001dfa: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8001dfc: f7fe fe04 bl 8000a08 8001e00: 0003 movs r3, r0 8001e02: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001e04: e008 b.n 8001e18 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8001e06: f7fe fdff bl 8000a08 8001e0a: 0002 movs r2, r0 8001e0c: 69bb ldr r3, [r7, #24] 8001e0e: 1ad3 subs r3, r2, r3 8001e10: 2b02 cmp r3, #2 8001e12: d901 bls.n 8001e18 { return HAL_TIMEOUT; 8001e14: 2303 movs r3, #3 8001e16: e0a2 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8001e18: 4b53 ldr r3, [pc, #332] ; (8001f68 ) 8001e1a: 6b5b ldr r3, [r3, #52] ; 0x34 8001e1c: 2202 movs r2, #2 8001e1e: 4013 ands r3, r2 8001e20: d1f1 bne.n 8001e06 #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001e22: 687b ldr r3, [r7, #4] 8001e24: 6a1b ldr r3, [r3, #32] 8001e26: 2b00 cmp r3, #0 8001e28: d100 bne.n 8001e2c 8001e2a: e097 b.n 8001f5c { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001e2c: 4b4e ldr r3, [pc, #312] ; (8001f68 ) 8001e2e: 685b ldr r3, [r3, #4] 8001e30: 220c movs r2, #12 8001e32: 4013 ands r3, r2 8001e34: 2b08 cmp r3, #8 8001e36: d100 bne.n 8001e3a 8001e38: e06b b.n 8001f12 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8001e3a: 687b ldr r3, [r7, #4] 8001e3c: 6a1b ldr r3, [r3, #32] 8001e3e: 2b02 cmp r3, #2 8001e40: d14c bne.n 8001edc assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001e42: 4b49 ldr r3, [pc, #292] ; (8001f68 ) 8001e44: 681a ldr r2, [r3, #0] 8001e46: 4b48 ldr r3, [pc, #288] ; (8001f68 ) 8001e48: 494a ldr r1, [pc, #296] ; (8001f74 ) 8001e4a: 400a ands r2, r1 8001e4c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001e4e: f7fe fddb bl 8000a08 8001e52: 0003 movs r3, r0 8001e54: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e56: e008 b.n 8001e6a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001e58: f7fe fdd6 bl 8000a08 8001e5c: 0002 movs r2, r0 8001e5e: 69bb ldr r3, [r7, #24] 8001e60: 1ad3 subs r3, r2, r3 8001e62: 2b02 cmp r3, #2 8001e64: d901 bls.n 8001e6a { return HAL_TIMEOUT; 8001e66: 2303 movs r3, #3 8001e68: e079 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001e6a: 4b3f ldr r3, [pc, #252] ; (8001f68 ) 8001e6c: 681a ldr r2, [r3, #0] 8001e6e: 2380 movs r3, #128 ; 0x80 8001e70: 049b lsls r3, r3, #18 8001e72: 4013 ands r3, r2 8001e74: d1f0 bne.n 8001e58 } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8001e76: 4b3c ldr r3, [pc, #240] ; (8001f68 ) 8001e78: 6adb ldr r3, [r3, #44] ; 0x2c 8001e7a: 220f movs r2, #15 8001e7c: 4393 bics r3, r2 8001e7e: 0019 movs r1, r3 8001e80: 687b ldr r3, [r7, #4] 8001e82: 6ada ldr r2, [r3, #44] ; 0x2c 8001e84: 4b38 ldr r3, [pc, #224] ; (8001f68 ) 8001e86: 430a orrs r2, r1 8001e88: 62da str r2, [r3, #44] ; 0x2c 8001e8a: 4b37 ldr r3, [pc, #220] ; (8001f68 ) 8001e8c: 685b ldr r3, [r3, #4] 8001e8e: 4a3a ldr r2, [pc, #232] ; (8001f78 ) 8001e90: 4013 ands r3, r2 8001e92: 0019 movs r1, r3 8001e94: 687b ldr r3, [r7, #4] 8001e96: 6a9a ldr r2, [r3, #40] ; 0x28 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 6a5b ldr r3, [r3, #36] ; 0x24 8001e9c: 431a orrs r2, r3 8001e9e: 4b32 ldr r3, [pc, #200] ; (8001f68 ) 8001ea0: 430a orrs r2, r1 8001ea2: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001ea4: 4b30 ldr r3, [pc, #192] ; (8001f68 ) 8001ea6: 681a ldr r2, [r3, #0] 8001ea8: 4b2f ldr r3, [pc, #188] ; (8001f68 ) 8001eaa: 2180 movs r1, #128 ; 0x80 8001eac: 0449 lsls r1, r1, #17 8001eae: 430a orrs r2, r1 8001eb0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001eb2: f7fe fda9 bl 8000a08 8001eb6: 0003 movs r3, r0 8001eb8: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001eba: e008 b.n 8001ece { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001ebc: f7fe fda4 bl 8000a08 8001ec0: 0002 movs r2, r0 8001ec2: 69bb ldr r3, [r7, #24] 8001ec4: 1ad3 subs r3, r2, r3 8001ec6: 2b02 cmp r3, #2 8001ec8: d901 bls.n 8001ece { return HAL_TIMEOUT; 8001eca: 2303 movs r3, #3 8001ecc: e047 b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001ece: 4b26 ldr r3, [pc, #152] ; (8001f68 ) 8001ed0: 681a ldr r2, [r3, #0] 8001ed2: 2380 movs r3, #128 ; 0x80 8001ed4: 049b lsls r3, r3, #18 8001ed6: 4013 ands r3, r2 8001ed8: d0f0 beq.n 8001ebc 8001eda: e03f b.n 8001f5c } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001edc: 4b22 ldr r3, [pc, #136] ; (8001f68 ) 8001ede: 681a ldr r2, [r3, #0] 8001ee0: 4b21 ldr r3, [pc, #132] ; (8001f68 ) 8001ee2: 4924 ldr r1, [pc, #144] ; (8001f74 ) 8001ee4: 400a ands r2, r1 8001ee6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001ee8: f7fe fd8e bl 8000a08 8001eec: 0003 movs r3, r0 8001eee: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001ef0: e008 b.n 8001f04 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001ef2: f7fe fd89 bl 8000a08 8001ef6: 0002 movs r2, r0 8001ef8: 69bb ldr r3, [r7, #24] 8001efa: 1ad3 subs r3, r2, r3 8001efc: 2b02 cmp r3, #2 8001efe: d901 bls.n 8001f04 { return HAL_TIMEOUT; 8001f00: 2303 movs r3, #3 8001f02: e02c b.n 8001f5e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001f04: 4b18 ldr r3, [pc, #96] ; (8001f68 ) 8001f06: 681a ldr r2, [r3, #0] 8001f08: 2380 movs r3, #128 ; 0x80 8001f0a: 049b lsls r3, r3, #18 8001f0c: 4013 ands r3, r2 8001f0e: d1f0 bne.n 8001ef2 8001f10: e024 b.n 8001f5c } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001f12: 687b ldr r3, [r7, #4] 8001f14: 6a1b ldr r3, [r3, #32] 8001f16: 2b01 cmp r3, #1 8001f18: d101 bne.n 8001f1e { return HAL_ERROR; 8001f1a: 2301 movs r3, #1 8001f1c: e01f b.n 8001f5e } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001f1e: 4b12 ldr r3, [pc, #72] ; (8001f68 ) 8001f20: 685b ldr r3, [r3, #4] 8001f22: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001f24: 4b10 ldr r3, [pc, #64] ; (8001f68 ) 8001f26: 6adb ldr r3, [r3, #44] ; 0x2c 8001f28: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001f2a: 697a ldr r2, [r7, #20] 8001f2c: 2380 movs r3, #128 ; 0x80 8001f2e: 025b lsls r3, r3, #9 8001f30: 401a ands r2, r3 8001f32: 687b ldr r3, [r7, #4] 8001f34: 6a5b ldr r3, [r3, #36] ; 0x24 8001f36: 429a cmp r2, r3 8001f38: d10e bne.n 8001f58 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001f3a: 693b ldr r3, [r7, #16] 8001f3c: 220f movs r2, #15 8001f3e: 401a ands r2, r3 8001f40: 687b ldr r3, [r7, #4] 8001f42: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001f44: 429a cmp r2, r3 8001f46: d107 bne.n 8001f58 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 8001f48: 697a ldr r2, [r7, #20] 8001f4a: 23f0 movs r3, #240 ; 0xf0 8001f4c: 039b lsls r3, r3, #14 8001f4e: 401a ands r2, r3 8001f50: 687b ldr r3, [r7, #4] 8001f52: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 8001f54: 429a cmp r2, r3 8001f56: d001 beq.n 8001f5c { return HAL_ERROR; 8001f58: 2301 movs r3, #1 8001f5a: e000 b.n 8001f5e } } } } return HAL_OK; 8001f5c: 2300 movs r3, #0 } 8001f5e: 0018 movs r0, r3 8001f60: 46bd mov sp, r7 8001f62: b008 add sp, #32 8001f64: bd80 pop {r7, pc} 8001f66: 46c0 nop ; (mov r8, r8) 8001f68: 40021000 .word 0x40021000 8001f6c: 00001388 .word 0x00001388 8001f70: efffffff .word 0xefffffff 8001f74: feffffff .word 0xfeffffff 8001f78: ffc2ffff .word 0xffc2ffff 08001f7c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001f7c: b580 push {r7, lr} 8001f7e: b084 sub sp, #16 8001f80: af00 add r7, sp, #0 8001f82: 6078 str r0, [r7, #4] 8001f84: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8001f86: 687b ldr r3, [r7, #4] 8001f88: 2b00 cmp r3, #0 8001f8a: d101 bne.n 8001f90 { return HAL_ERROR; 8001f8c: 2301 movs r3, #1 8001f8e: e0b3 b.n 80020f8 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8001f90: 4b5b ldr r3, [pc, #364] ; (8002100 ) 8001f92: 681b ldr r3, [r3, #0] 8001f94: 2201 movs r2, #1 8001f96: 4013 ands r3, r2 8001f98: 683a ldr r2, [r7, #0] 8001f9a: 429a cmp r2, r3 8001f9c: d911 bls.n 8001fc2 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001f9e: 4b58 ldr r3, [pc, #352] ; (8002100 ) 8001fa0: 681b ldr r3, [r3, #0] 8001fa2: 2201 movs r2, #1 8001fa4: 4393 bics r3, r2 8001fa6: 0019 movs r1, r3 8001fa8: 4b55 ldr r3, [pc, #340] ; (8002100 ) 8001faa: 683a ldr r2, [r7, #0] 8001fac: 430a orrs r2, r1 8001fae: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001fb0: 4b53 ldr r3, [pc, #332] ; (8002100 ) 8001fb2: 681b ldr r3, [r3, #0] 8001fb4: 2201 movs r2, #1 8001fb6: 4013 ands r3, r2 8001fb8: 683a ldr r2, [r7, #0] 8001fba: 429a cmp r2, r3 8001fbc: d001 beq.n 8001fc2 { return HAL_ERROR; 8001fbe: 2301 movs r3, #1 8001fc0: e09a b.n 80020f8 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001fc2: 687b ldr r3, [r7, #4] 8001fc4: 681b ldr r3, [r3, #0] 8001fc6: 2202 movs r2, #2 8001fc8: 4013 ands r3, r2 8001fca: d015 beq.n 8001ff8 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001fcc: 687b ldr r3, [r7, #4] 8001fce: 681b ldr r3, [r3, #0] 8001fd0: 2204 movs r2, #4 8001fd2: 4013 ands r3, r2 8001fd4: d006 beq.n 8001fe4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001fd6: 4b4b ldr r3, [pc, #300] ; (8002104 ) 8001fd8: 685a ldr r2, [r3, #4] 8001fda: 4b4a ldr r3, [pc, #296] ; (8002104 ) 8001fdc: 21e0 movs r1, #224 ; 0xe0 8001fde: 00c9 lsls r1, r1, #3 8001fe0: 430a orrs r2, r1 8001fe2: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001fe4: 4b47 ldr r3, [pc, #284] ; (8002104 ) 8001fe6: 685b ldr r3, [r3, #4] 8001fe8: 22f0 movs r2, #240 ; 0xf0 8001fea: 4393 bics r3, r2 8001fec: 0019 movs r1, r3 8001fee: 687b ldr r3, [r7, #4] 8001ff0: 689a ldr r2, [r3, #8] 8001ff2: 4b44 ldr r3, [pc, #272] ; (8002104 ) 8001ff4: 430a orrs r2, r1 8001ff6: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001ff8: 687b ldr r3, [r7, #4] 8001ffa: 681b ldr r3, [r3, #0] 8001ffc: 2201 movs r2, #1 8001ffe: 4013 ands r3, r2 8002000: d040 beq.n 8002084 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8002002: 687b ldr r3, [r7, #4] 8002004: 685b ldr r3, [r3, #4] 8002006: 2b01 cmp r3, #1 8002008: d107 bne.n 800201a { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800200a: 4b3e ldr r3, [pc, #248] ; (8002104 ) 800200c: 681a ldr r2, [r3, #0] 800200e: 2380 movs r3, #128 ; 0x80 8002010: 029b lsls r3, r3, #10 8002012: 4013 ands r3, r2 8002014: d114 bne.n 8002040 { return HAL_ERROR; 8002016: 2301 movs r3, #1 8002018: e06e b.n 80020f8 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800201a: 687b ldr r3, [r7, #4] 800201c: 685b ldr r3, [r3, #4] 800201e: 2b02 cmp r3, #2 8002020: d107 bne.n 8002032 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8002022: 4b38 ldr r3, [pc, #224] ; (8002104 ) 8002024: 681a ldr r2, [r3, #0] 8002026: 2380 movs r3, #128 ; 0x80 8002028: 049b lsls r3, r3, #18 800202a: 4013 ands r3, r2 800202c: d108 bne.n 8002040 { return HAL_ERROR; 800202e: 2301 movs r3, #1 8002030: e062 b.n 80020f8 #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8002032: 4b34 ldr r3, [pc, #208] ; (8002104 ) 8002034: 681b ldr r3, [r3, #0] 8002036: 2202 movs r2, #2 8002038: 4013 ands r3, r2 800203a: d101 bne.n 8002040 { return HAL_ERROR; 800203c: 2301 movs r3, #1 800203e: e05b b.n 80020f8 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8002040: 4b30 ldr r3, [pc, #192] ; (8002104 ) 8002042: 685b ldr r3, [r3, #4] 8002044: 2203 movs r2, #3 8002046: 4393 bics r3, r2 8002048: 0019 movs r1, r3 800204a: 687b ldr r3, [r7, #4] 800204c: 685a ldr r2, [r3, #4] 800204e: 4b2d ldr r3, [pc, #180] ; (8002104 ) 8002050: 430a orrs r2, r1 8002052: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002054: f7fe fcd8 bl 8000a08 8002058: 0003 movs r3, r0 800205a: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800205c: e009 b.n 8002072 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 800205e: f7fe fcd3 bl 8000a08 8002062: 0002 movs r2, r0 8002064: 68fb ldr r3, [r7, #12] 8002066: 1ad3 subs r3, r2, r3 8002068: 4a27 ldr r2, [pc, #156] ; (8002108 ) 800206a: 4293 cmp r3, r2 800206c: d901 bls.n 8002072 { return HAL_TIMEOUT; 800206e: 2303 movs r3, #3 8002070: e042 b.n 80020f8 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002072: 4b24 ldr r3, [pc, #144] ; (8002104 ) 8002074: 685b ldr r3, [r3, #4] 8002076: 220c movs r2, #12 8002078: 401a ands r2, r3 800207a: 687b ldr r3, [r7, #4] 800207c: 685b ldr r3, [r3, #4] 800207e: 009b lsls r3, r3, #2 8002080: 429a cmp r2, r3 8002082: d1ec bne.n 800205e } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8002084: 4b1e ldr r3, [pc, #120] ; (8002100 ) 8002086: 681b ldr r3, [r3, #0] 8002088: 2201 movs r2, #1 800208a: 4013 ands r3, r2 800208c: 683a ldr r2, [r7, #0] 800208e: 429a cmp r2, r3 8002090: d211 bcs.n 80020b6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8002092: 4b1b ldr r3, [pc, #108] ; (8002100 ) 8002094: 681b ldr r3, [r3, #0] 8002096: 2201 movs r2, #1 8002098: 4393 bics r3, r2 800209a: 0019 movs r1, r3 800209c: 4b18 ldr r3, [pc, #96] ; (8002100 ) 800209e: 683a ldr r2, [r7, #0] 80020a0: 430a orrs r2, r1 80020a2: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 80020a4: 4b16 ldr r3, [pc, #88] ; (8002100 ) 80020a6: 681b ldr r3, [r3, #0] 80020a8: 2201 movs r2, #1 80020aa: 4013 ands r3, r2 80020ac: 683a ldr r2, [r7, #0] 80020ae: 429a cmp r2, r3 80020b0: d001 beq.n 80020b6 { return HAL_ERROR; 80020b2: 2301 movs r3, #1 80020b4: e020 b.n 80020f8 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80020b6: 687b ldr r3, [r7, #4] 80020b8: 681b ldr r3, [r3, #0] 80020ba: 2204 movs r2, #4 80020bc: 4013 ands r3, r2 80020be: d009 beq.n 80020d4 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 80020c0: 4b10 ldr r3, [pc, #64] ; (8002104 ) 80020c2: 685b ldr r3, [r3, #4] 80020c4: 4a11 ldr r2, [pc, #68] ; (800210c ) 80020c6: 4013 ands r3, r2 80020c8: 0019 movs r1, r3 80020ca: 687b ldr r3, [r7, #4] 80020cc: 68da ldr r2, [r3, #12] 80020ce: 4b0d ldr r3, [pc, #52] ; (8002104 ) 80020d0: 430a orrs r2, r1 80020d2: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 80020d4: f000 f820 bl 8002118 80020d8: 0001 movs r1, r0 80020da: 4b0a ldr r3, [pc, #40] ; (8002104 ) 80020dc: 685b ldr r3, [r3, #4] 80020de: 091b lsrs r3, r3, #4 80020e0: 220f movs r2, #15 80020e2: 4013 ands r3, r2 80020e4: 4a0a ldr r2, [pc, #40] ; (8002110 ) 80020e6: 5cd3 ldrb r3, [r2, r3] 80020e8: 000a movs r2, r1 80020ea: 40da lsrs r2, r3 80020ec: 4b09 ldr r3, [pc, #36] ; (8002114 ) 80020ee: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 80020f0: 2003 movs r0, #3 80020f2: f7fe fc43 bl 800097c return HAL_OK; 80020f6: 2300 movs r3, #0 } 80020f8: 0018 movs r0, r3 80020fa: 46bd mov sp, r7 80020fc: b004 add sp, #16 80020fe: bd80 pop {r7, pc} 8002100: 40022000 .word 0x40022000 8002104: 40021000 .word 0x40021000 8002108: 00001388 .word 0x00001388 800210c: fffff8ff .word 0xfffff8ff 8002110: 08003ee0 .word 0x08003ee0 8002114: 20000000 .word 0x20000000 08002118 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8002118: b590 push {r4, r7, lr} 800211a: b08f sub sp, #60 ; 0x3c 800211c: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 800211e: 2314 movs r3, #20 8002120: 18fb adds r3, r7, r3 8002122: 4a2b ldr r2, [pc, #172] ; (80021d0 ) 8002124: ca13 ldmia r2!, {r0, r1, r4} 8002126: c313 stmia r3!, {r0, r1, r4} 8002128: 6812 ldr r2, [r2, #0] 800212a: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 800212c: 1d3b adds r3, r7, #4 800212e: 4a29 ldr r2, [pc, #164] ; (80021d4 ) 8002130: ca13 ldmia r2!, {r0, r1, r4} 8002132: c313 stmia r3!, {r0, r1, r4} 8002134: 6812 ldr r2, [r2, #0] 8002136: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8002138: 2300 movs r3, #0 800213a: 62fb str r3, [r7, #44] ; 0x2c 800213c: 2300 movs r3, #0 800213e: 62bb str r3, [r7, #40] ; 0x28 8002140: 2300 movs r3, #0 8002142: 637b str r3, [r7, #52] ; 0x34 8002144: 2300 movs r3, #0 8002146: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8002148: 2300 movs r3, #0 800214a: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 800214c: 4b22 ldr r3, [pc, #136] ; (80021d8 ) 800214e: 685b ldr r3, [r3, #4] 8002150: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8002152: 6afb ldr r3, [r7, #44] ; 0x2c 8002154: 220c movs r2, #12 8002156: 4013 ands r3, r2 8002158: 2b04 cmp r3, #4 800215a: d002 beq.n 8002162 800215c: 2b08 cmp r3, #8 800215e: d003 beq.n 8002168 8002160: e02d b.n 80021be { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8002162: 4b1e ldr r3, [pc, #120] ; (80021dc ) 8002164: 633b str r3, [r7, #48] ; 0x30 break; 8002166: e02d b.n 80021c4 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 8002168: 6afb ldr r3, [r7, #44] ; 0x2c 800216a: 0c9b lsrs r3, r3, #18 800216c: 220f movs r2, #15 800216e: 4013 ands r3, r2 8002170: 2214 movs r2, #20 8002172: 18ba adds r2, r7, r2 8002174: 5cd3 ldrb r3, [r2, r3] 8002176: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 8002178: 4b17 ldr r3, [pc, #92] ; (80021d8 ) 800217a: 6adb ldr r3, [r3, #44] ; 0x2c 800217c: 220f movs r2, #15 800217e: 4013 ands r3, r2 8002180: 1d3a adds r2, r7, #4 8002182: 5cd3 ldrb r3, [r2, r3] 8002184: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 8002186: 6afa ldr r2, [r7, #44] ; 0x2c 8002188: 2380 movs r3, #128 ; 0x80 800218a: 025b lsls r3, r3, #9 800218c: 4013 ands r3, r2 800218e: d009 beq.n 80021a4 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 8002190: 6ab9 ldr r1, [r7, #40] ; 0x28 8002192: 4812 ldr r0, [pc, #72] ; (80021dc ) 8002194: f7fd ffb8 bl 8000108 <__udivsi3> 8002198: 0003 movs r3, r0 800219a: 001a movs r2, r3 800219c: 6a7b ldr r3, [r7, #36] ; 0x24 800219e: 4353 muls r3, r2 80021a0: 637b str r3, [r7, #52] ; 0x34 80021a2: e009 b.n 80021b8 #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 80021a4: 6a79 ldr r1, [r7, #36] ; 0x24 80021a6: 000a movs r2, r1 80021a8: 0152 lsls r2, r2, #5 80021aa: 1a52 subs r2, r2, r1 80021ac: 0193 lsls r3, r2, #6 80021ae: 1a9b subs r3, r3, r2 80021b0: 00db lsls r3, r3, #3 80021b2: 185b adds r3, r3, r1 80021b4: 021b lsls r3, r3, #8 80021b6: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 80021b8: 6b7b ldr r3, [r7, #52] ; 0x34 80021ba: 633b str r3, [r7, #48] ; 0x30 break; 80021bc: e002 b.n 80021c4 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80021be: 4b07 ldr r3, [pc, #28] ; (80021dc ) 80021c0: 633b str r3, [r7, #48] ; 0x30 break; 80021c2: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 80021c4: 6b3b ldr r3, [r7, #48] ; 0x30 } 80021c6: 0018 movs r0, r3 80021c8: 46bd mov sp, r7 80021ca: b00f add sp, #60 ; 0x3c 80021cc: bd90 pop {r4, r7, pc} 80021ce: 46c0 nop ; (mov r8, r8) 80021d0: 08003ec0 .word 0x08003ec0 80021d4: 08003ed0 .word 0x08003ed0 80021d8: 40021000 .word 0x40021000 80021dc: 007a1200 .word 0x007a1200 080021e0 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 80021e0: b580 push {r7, lr} 80021e2: b082 sub sp, #8 80021e4: af00 add r7, sp, #0 80021e6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80021e8: 687b ldr r3, [r7, #4] 80021ea: 2b00 cmp r3, #0 80021ec: d101 bne.n 80021f2 { return HAL_ERROR; 80021ee: 2301 movs r3, #1 80021f0: e042 b.n 8002278 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80021f2: 687b ldr r3, [r7, #4] 80021f4: 223d movs r2, #61 ; 0x3d 80021f6: 5c9b ldrb r3, [r3, r2] 80021f8: b2db uxtb r3, r3 80021fa: 2b00 cmp r3, #0 80021fc: d107 bne.n 800220e { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80021fe: 687b ldr r3, [r7, #4] 8002200: 223c movs r2, #60 ; 0x3c 8002202: 2100 movs r1, #0 8002204: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8002206: 687b ldr r3, [r7, #4] 8002208: 0018 movs r0, r3 800220a: f7fe fb1f bl 800084c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800220e: 687b ldr r3, [r7, #4] 8002210: 223d movs r2, #61 ; 0x3d 8002212: 2102 movs r1, #2 8002214: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8002216: 687b ldr r3, [r7, #4] 8002218: 681a ldr r2, [r3, #0] 800221a: 687b ldr r3, [r7, #4] 800221c: 3304 adds r3, #4 800221e: 0019 movs r1, r3 8002220: 0010 movs r0, r2 8002222: f000 f9a9 bl 8002578 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8002226: 687b ldr r3, [r7, #4] 8002228: 2246 movs r2, #70 ; 0x46 800222a: 2101 movs r1, #1 800222c: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800222e: 687b ldr r3, [r7, #4] 8002230: 223e movs r2, #62 ; 0x3e 8002232: 2101 movs r1, #1 8002234: 5499 strb r1, [r3, r2] 8002236: 687b ldr r3, [r7, #4] 8002238: 223f movs r2, #63 ; 0x3f 800223a: 2101 movs r1, #1 800223c: 5499 strb r1, [r3, r2] 800223e: 687b ldr r3, [r7, #4] 8002240: 2240 movs r2, #64 ; 0x40 8002242: 2101 movs r1, #1 8002244: 5499 strb r1, [r3, r2] 8002246: 687b ldr r3, [r7, #4] 8002248: 2241 movs r2, #65 ; 0x41 800224a: 2101 movs r1, #1 800224c: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800224e: 687b ldr r3, [r7, #4] 8002250: 2242 movs r2, #66 ; 0x42 8002252: 2101 movs r1, #1 8002254: 5499 strb r1, [r3, r2] 8002256: 687b ldr r3, [r7, #4] 8002258: 2243 movs r2, #67 ; 0x43 800225a: 2101 movs r1, #1 800225c: 5499 strb r1, [r3, r2] 800225e: 687b ldr r3, [r7, #4] 8002260: 2244 movs r2, #68 ; 0x44 8002262: 2101 movs r1, #1 8002264: 5499 strb r1, [r3, r2] 8002266: 687b ldr r3, [r7, #4] 8002268: 2245 movs r2, #69 ; 0x45 800226a: 2101 movs r1, #1 800226c: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800226e: 687b ldr r3, [r7, #4] 8002270: 223d movs r2, #61 ; 0x3d 8002272: 2101 movs r1, #1 8002274: 5499 strb r1, [r3, r2] return HAL_OK; 8002276: 2300 movs r3, #0 } 8002278: 0018 movs r0, r3 800227a: 46bd mov sp, r7 800227c: b002 add sp, #8 800227e: bd80 pop {r7, pc} 08002280 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8002280: b580 push {r7, lr} 8002282: b084 sub sp, #16 8002284: af00 add r7, sp, #0 8002286: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8002288: 687b ldr r3, [r7, #4] 800228a: 223d movs r2, #61 ; 0x3d 800228c: 5c9b ldrb r3, [r3, r2] 800228e: b2db uxtb r3, r3 8002290: 2b01 cmp r3, #1 8002292: d001 beq.n 8002298 { return HAL_ERROR; 8002294: 2301 movs r3, #1 8002296: e030 b.n 80022fa } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8002298: 687b ldr r3, [r7, #4] 800229a: 223d movs r2, #61 ; 0x3d 800229c: 2102 movs r1, #2 800229e: 5499 strb r1, [r3, r2] /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 80022a0: 687b ldr r3, [r7, #4] 80022a2: 681b ldr r3, [r3, #0] 80022a4: 68da ldr r2, [r3, #12] 80022a6: 687b ldr r3, [r7, #4] 80022a8: 681b ldr r3, [r3, #0] 80022aa: 2101 movs r1, #1 80022ac: 430a orrs r2, r1 80022ae: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80022b0: 687b ldr r3, [r7, #4] 80022b2: 681b ldr r3, [r3, #0] 80022b4: 4a13 ldr r2, [pc, #76] ; (8002304 ) 80022b6: 4293 cmp r3, r2 80022b8: d004 beq.n 80022c4 80022ba: 687b ldr r3, [r7, #4] 80022bc: 681b ldr r3, [r3, #0] 80022be: 4a12 ldr r2, [pc, #72] ; (8002308 ) 80022c0: 4293 cmp r3, r2 80022c2: d111 bne.n 80022e8 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80022c4: 687b ldr r3, [r7, #4] 80022c6: 681b ldr r3, [r3, #0] 80022c8: 689b ldr r3, [r3, #8] 80022ca: 2207 movs r2, #7 80022cc: 4013 ands r3, r2 80022ce: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80022d0: 68fb ldr r3, [r7, #12] 80022d2: 2b06 cmp r3, #6 80022d4: d010 beq.n 80022f8 { __HAL_TIM_ENABLE(htim); 80022d6: 687b ldr r3, [r7, #4] 80022d8: 681b ldr r3, [r3, #0] 80022da: 681a ldr r2, [r3, #0] 80022dc: 687b ldr r3, [r7, #4] 80022de: 681b ldr r3, [r3, #0] 80022e0: 2101 movs r1, #1 80022e2: 430a orrs r2, r1 80022e4: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80022e6: e007 b.n 80022f8 } } else { __HAL_TIM_ENABLE(htim); 80022e8: 687b ldr r3, [r7, #4] 80022ea: 681b ldr r3, [r3, #0] 80022ec: 681a ldr r2, [r3, #0] 80022ee: 687b ldr r3, [r7, #4] 80022f0: 681b ldr r3, [r3, #0] 80022f2: 2101 movs r1, #1 80022f4: 430a orrs r2, r1 80022f6: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80022f8: 2300 movs r3, #0 } 80022fa: 0018 movs r0, r3 80022fc: 46bd mov sp, r7 80022fe: b004 add sp, #16 8002300: bd80 pop {r7, pc} 8002302: 46c0 nop ; (mov r8, r8) 8002304: 40012c00 .word 0x40012c00 8002308: 40000400 .word 0x40000400 0800230c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800230c: b580 push {r7, lr} 800230e: b082 sub sp, #8 8002310: af00 add r7, sp, #0 8002312: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8002314: 687b ldr r3, [r7, #4] 8002316: 681b ldr r3, [r3, #0] 8002318: 691b ldr r3, [r3, #16] 800231a: 2202 movs r2, #2 800231c: 4013 ands r3, r2 800231e: 2b02 cmp r3, #2 8002320: d124 bne.n 800236c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 8002322: 687b ldr r3, [r7, #4] 8002324: 681b ldr r3, [r3, #0] 8002326: 68db ldr r3, [r3, #12] 8002328: 2202 movs r2, #2 800232a: 4013 ands r3, r2 800232c: 2b02 cmp r3, #2 800232e: d11d bne.n 800236c { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8002330: 687b ldr r3, [r7, #4] 8002332: 681b ldr r3, [r3, #0] 8002334: 2203 movs r2, #3 8002336: 4252 negs r2, r2 8002338: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800233a: 687b ldr r3, [r7, #4] 800233c: 2201 movs r2, #1 800233e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8002340: 687b ldr r3, [r7, #4] 8002342: 681b ldr r3, [r3, #0] 8002344: 699b ldr r3, [r3, #24] 8002346: 2203 movs r2, #3 8002348: 4013 ands r3, r2 800234a: d004 beq.n 8002356 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800234c: 687b ldr r3, [r7, #4] 800234e: 0018 movs r0, r3 8002350: f000 f8fa bl 8002548 8002354: e007 b.n 8002366 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002356: 687b ldr r3, [r7, #4] 8002358: 0018 movs r0, r3 800235a: f000 f8ed bl 8002538 HAL_TIM_PWM_PulseFinishedCallback(htim); 800235e: 687b ldr r3, [r7, #4] 8002360: 0018 movs r0, r3 8002362: f000 f8f9 bl 8002558 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002366: 687b ldr r3, [r7, #4] 8002368: 2200 movs r2, #0 800236a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 800236c: 687b ldr r3, [r7, #4] 800236e: 681b ldr r3, [r3, #0] 8002370: 691b ldr r3, [r3, #16] 8002372: 2204 movs r2, #4 8002374: 4013 ands r3, r2 8002376: 2b04 cmp r3, #4 8002378: d125 bne.n 80023c6 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 800237a: 687b ldr r3, [r7, #4] 800237c: 681b ldr r3, [r3, #0] 800237e: 68db ldr r3, [r3, #12] 8002380: 2204 movs r2, #4 8002382: 4013 ands r3, r2 8002384: 2b04 cmp r3, #4 8002386: d11e bne.n 80023c6 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8002388: 687b ldr r3, [r7, #4] 800238a: 681b ldr r3, [r3, #0] 800238c: 2205 movs r2, #5 800238e: 4252 negs r2, r2 8002390: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8002392: 687b ldr r3, [r7, #4] 8002394: 2202 movs r2, #2 8002396: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8002398: 687b ldr r3, [r7, #4] 800239a: 681b ldr r3, [r3, #0] 800239c: 699a ldr r2, [r3, #24] 800239e: 23c0 movs r3, #192 ; 0xc0 80023a0: 009b lsls r3, r3, #2 80023a2: 4013 ands r3, r2 80023a4: d004 beq.n 80023b0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80023a6: 687b ldr r3, [r7, #4] 80023a8: 0018 movs r0, r3 80023aa: f000 f8cd bl 8002548 80023ae: e007 b.n 80023c0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80023b0: 687b ldr r3, [r7, #4] 80023b2: 0018 movs r0, r3 80023b4: f000 f8c0 bl 8002538 HAL_TIM_PWM_PulseFinishedCallback(htim); 80023b8: 687b ldr r3, [r7, #4] 80023ba: 0018 movs r0, r3 80023bc: f000 f8cc bl 8002558 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80023c0: 687b ldr r3, [r7, #4] 80023c2: 2200 movs r2, #0 80023c4: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 80023c6: 687b ldr r3, [r7, #4] 80023c8: 681b ldr r3, [r3, #0] 80023ca: 691b ldr r3, [r3, #16] 80023cc: 2208 movs r2, #8 80023ce: 4013 ands r3, r2 80023d0: 2b08 cmp r3, #8 80023d2: d124 bne.n 800241e { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 80023d4: 687b ldr r3, [r7, #4] 80023d6: 681b ldr r3, [r3, #0] 80023d8: 68db ldr r3, [r3, #12] 80023da: 2208 movs r2, #8 80023dc: 4013 ands r3, r2 80023de: 2b08 cmp r3, #8 80023e0: d11d bne.n 800241e { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 80023e2: 687b ldr r3, [r7, #4] 80023e4: 681b ldr r3, [r3, #0] 80023e6: 2209 movs r2, #9 80023e8: 4252 negs r2, r2 80023ea: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80023ec: 687b ldr r3, [r7, #4] 80023ee: 2204 movs r2, #4 80023f0: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80023f2: 687b ldr r3, [r7, #4] 80023f4: 681b ldr r3, [r3, #0] 80023f6: 69db ldr r3, [r3, #28] 80023f8: 2203 movs r2, #3 80023fa: 4013 ands r3, r2 80023fc: d004 beq.n 8002408 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80023fe: 687b ldr r3, [r7, #4] 8002400: 0018 movs r0, r3 8002402: f000 f8a1 bl 8002548 8002406: e007 b.n 8002418 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002408: 687b ldr r3, [r7, #4] 800240a: 0018 movs r0, r3 800240c: f000 f894 bl 8002538 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002410: 687b ldr r3, [r7, #4] 8002412: 0018 movs r0, r3 8002414: f000 f8a0 bl 8002558 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002418: 687b ldr r3, [r7, #4] 800241a: 2200 movs r2, #0 800241c: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 800241e: 687b ldr r3, [r7, #4] 8002420: 681b ldr r3, [r3, #0] 8002422: 691b ldr r3, [r3, #16] 8002424: 2210 movs r2, #16 8002426: 4013 ands r3, r2 8002428: 2b10 cmp r3, #16 800242a: d125 bne.n 8002478 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 800242c: 687b ldr r3, [r7, #4] 800242e: 681b ldr r3, [r3, #0] 8002430: 68db ldr r3, [r3, #12] 8002432: 2210 movs r2, #16 8002434: 4013 ands r3, r2 8002436: 2b10 cmp r3, #16 8002438: d11e bne.n 8002478 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 800243a: 687b ldr r3, [r7, #4] 800243c: 681b ldr r3, [r3, #0] 800243e: 2211 movs r2, #17 8002440: 4252 negs r2, r2 8002442: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8002444: 687b ldr r3, [r7, #4] 8002446: 2208 movs r2, #8 8002448: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800244a: 687b ldr r3, [r7, #4] 800244c: 681b ldr r3, [r3, #0] 800244e: 69da ldr r2, [r3, #28] 8002450: 23c0 movs r3, #192 ; 0xc0 8002452: 009b lsls r3, r3, #2 8002454: 4013 ands r3, r2 8002456: d004 beq.n 8002462 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002458: 687b ldr r3, [r7, #4] 800245a: 0018 movs r0, r3 800245c: f000 f874 bl 8002548 8002460: e007 b.n 8002472 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002462: 687b ldr r3, [r7, #4] 8002464: 0018 movs r0, r3 8002466: f000 f867 bl 8002538 HAL_TIM_PWM_PulseFinishedCallback(htim); 800246a: 687b ldr r3, [r7, #4] 800246c: 0018 movs r0, r3 800246e: f000 f873 bl 8002558 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002472: 687b ldr r3, [r7, #4] 8002474: 2200 movs r2, #0 8002476: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8002478: 687b ldr r3, [r7, #4] 800247a: 681b ldr r3, [r3, #0] 800247c: 691b ldr r3, [r3, #16] 800247e: 2201 movs r2, #1 8002480: 4013 ands r3, r2 8002482: 2b01 cmp r3, #1 8002484: d10f bne.n 80024a6 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 8002486: 687b ldr r3, [r7, #4] 8002488: 681b ldr r3, [r3, #0] 800248a: 68db ldr r3, [r3, #12] 800248c: 2201 movs r2, #1 800248e: 4013 ands r3, r2 8002490: 2b01 cmp r3, #1 8002492: d108 bne.n 80024a6 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 8002494: 687b ldr r3, [r7, #4] 8002496: 681b ldr r3, [r3, #0] 8002498: 2202 movs r2, #2 800249a: 4252 negs r2, r2 800249c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800249e: 687b ldr r3, [r7, #4] 80024a0: 0018 movs r0, r3 80024a2: f001 fcbf bl 8003e24 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 80024a6: 687b ldr r3, [r7, #4] 80024a8: 681b ldr r3, [r3, #0] 80024aa: 691b ldr r3, [r3, #16] 80024ac: 2280 movs r2, #128 ; 0x80 80024ae: 4013 ands r3, r2 80024b0: 2b80 cmp r3, #128 ; 0x80 80024b2: d10f bne.n 80024d4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 80024b4: 687b ldr r3, [r7, #4] 80024b6: 681b ldr r3, [r3, #0] 80024b8: 68db ldr r3, [r3, #12] 80024ba: 2280 movs r2, #128 ; 0x80 80024bc: 4013 ands r3, r2 80024be: 2b80 cmp r3, #128 ; 0x80 80024c0: d108 bne.n 80024d4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 80024c2: 687b ldr r3, [r7, #4] 80024c4: 681b ldr r3, [r3, #0] 80024c6: 2281 movs r2, #129 ; 0x81 80024c8: 4252 negs r2, r2 80024ca: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80024cc: 687b ldr r3, [r7, #4] 80024ce: 0018 movs r0, r3 80024d0: f000 f8c6 bl 8002660 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 80024d4: 687b ldr r3, [r7, #4] 80024d6: 681b ldr r3, [r3, #0] 80024d8: 691b ldr r3, [r3, #16] 80024da: 2240 movs r2, #64 ; 0x40 80024dc: 4013 ands r3, r2 80024de: 2b40 cmp r3, #64 ; 0x40 80024e0: d10f bne.n 8002502 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 80024e2: 687b ldr r3, [r7, #4] 80024e4: 681b ldr r3, [r3, #0] 80024e6: 68db ldr r3, [r3, #12] 80024e8: 2240 movs r2, #64 ; 0x40 80024ea: 4013 ands r3, r2 80024ec: 2b40 cmp r3, #64 ; 0x40 80024ee: d108 bne.n 8002502 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80024f0: 687b ldr r3, [r7, #4] 80024f2: 681b ldr r3, [r3, #0] 80024f4: 2241 movs r2, #65 ; 0x41 80024f6: 4252 negs r2, r2 80024f8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80024fa: 687b ldr r3, [r7, #4] 80024fc: 0018 movs r0, r3 80024fe: f000 f833 bl 8002568 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 8002502: 687b ldr r3, [r7, #4] 8002504: 681b ldr r3, [r3, #0] 8002506: 691b ldr r3, [r3, #16] 8002508: 2220 movs r2, #32 800250a: 4013 ands r3, r2 800250c: 2b20 cmp r3, #32 800250e: d10f bne.n 8002530 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 8002510: 687b ldr r3, [r7, #4] 8002512: 681b ldr r3, [r3, #0] 8002514: 68db ldr r3, [r3, #12] 8002516: 2220 movs r2, #32 8002518: 4013 ands r3, r2 800251a: 2b20 cmp r3, #32 800251c: d108 bne.n 8002530 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 800251e: 687b ldr r3, [r7, #4] 8002520: 681b ldr r3, [r3, #0] 8002522: 2221 movs r2, #33 ; 0x21 8002524: 4252 negs r2, r2 8002526: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8002528: 687b ldr r3, [r7, #4] 800252a: 0018 movs r0, r3 800252c: f000 f890 bl 8002650 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8002530: 46c0 nop ; (mov r8, r8) 8002532: 46bd mov sp, r7 8002534: b002 add sp, #8 8002536: bd80 pop {r7, pc} 08002538 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8002538: b580 push {r7, lr} 800253a: b082 sub sp, #8 800253c: af00 add r7, sp, #0 800253e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8002540: 46c0 nop ; (mov r8, r8) 8002542: 46bd mov sp, r7 8002544: b002 add sp, #8 8002546: bd80 pop {r7, pc} 08002548 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8002548: b580 push {r7, lr} 800254a: b082 sub sp, #8 800254c: af00 add r7, sp, #0 800254e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8002550: 46c0 nop ; (mov r8, r8) 8002552: 46bd mov sp, r7 8002554: b002 add sp, #8 8002556: bd80 pop {r7, pc} 08002558 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8002558: b580 push {r7, lr} 800255a: b082 sub sp, #8 800255c: af00 add r7, sp, #0 800255e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8002560: 46c0 nop ; (mov r8, r8) 8002562: 46bd mov sp, r7 8002564: b002 add sp, #8 8002566: bd80 pop {r7, pc} 08002568 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8002568: b580 push {r7, lr} 800256a: b082 sub sp, #8 800256c: af00 add r7, sp, #0 800256e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8002570: 46c0 nop ; (mov r8, r8) 8002572: 46bd mov sp, r7 8002574: b002 add sp, #8 8002576: bd80 pop {r7, pc} 08002578 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 8002578: b580 push {r7, lr} 800257a: b084 sub sp, #16 800257c: af00 add r7, sp, #0 800257e: 6078 str r0, [r7, #4] 8002580: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8002582: 687b ldr r3, [r7, #4] 8002584: 681b ldr r3, [r3, #0] 8002586: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8002588: 687b ldr r3, [r7, #4] 800258a: 4a2b ldr r2, [pc, #172] ; (8002638 ) 800258c: 4293 cmp r3, r2 800258e: d003 beq.n 8002598 8002590: 687b ldr r3, [r7, #4] 8002592: 4a2a ldr r2, [pc, #168] ; (800263c ) 8002594: 4293 cmp r3, r2 8002596: d108 bne.n 80025aa { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8002598: 68fb ldr r3, [r7, #12] 800259a: 2270 movs r2, #112 ; 0x70 800259c: 4393 bics r3, r2 800259e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80025a0: 683b ldr r3, [r7, #0] 80025a2: 685b ldr r3, [r3, #4] 80025a4: 68fa ldr r2, [r7, #12] 80025a6: 4313 orrs r3, r2 80025a8: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80025aa: 687b ldr r3, [r7, #4] 80025ac: 4a22 ldr r2, [pc, #136] ; (8002638 ) 80025ae: 4293 cmp r3, r2 80025b0: d00f beq.n 80025d2 80025b2: 687b ldr r3, [r7, #4] 80025b4: 4a21 ldr r2, [pc, #132] ; (800263c ) 80025b6: 4293 cmp r3, r2 80025b8: d00b beq.n 80025d2 80025ba: 687b ldr r3, [r7, #4] 80025bc: 4a20 ldr r2, [pc, #128] ; (8002640 ) 80025be: 4293 cmp r3, r2 80025c0: d007 beq.n 80025d2 80025c2: 687b ldr r3, [r7, #4] 80025c4: 4a1f ldr r2, [pc, #124] ; (8002644 ) 80025c6: 4293 cmp r3, r2 80025c8: d003 beq.n 80025d2 80025ca: 687b ldr r3, [r7, #4] 80025cc: 4a1e ldr r2, [pc, #120] ; (8002648 ) 80025ce: 4293 cmp r3, r2 80025d0: d108 bne.n 80025e4 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80025d2: 68fb ldr r3, [r7, #12] 80025d4: 4a1d ldr r2, [pc, #116] ; (800264c ) 80025d6: 4013 ands r3, r2 80025d8: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80025da: 683b ldr r3, [r7, #0] 80025dc: 68db ldr r3, [r3, #12] 80025de: 68fa ldr r2, [r7, #12] 80025e0: 4313 orrs r3, r2 80025e2: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80025e4: 68fb ldr r3, [r7, #12] 80025e6: 2280 movs r2, #128 ; 0x80 80025e8: 4393 bics r3, r2 80025ea: 001a movs r2, r3 80025ec: 683b ldr r3, [r7, #0] 80025ee: 695b ldr r3, [r3, #20] 80025f0: 4313 orrs r3, r2 80025f2: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 80025f4: 687b ldr r3, [r7, #4] 80025f6: 68fa ldr r2, [r7, #12] 80025f8: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80025fa: 683b ldr r3, [r7, #0] 80025fc: 689a ldr r2, [r3, #8] 80025fe: 687b ldr r3, [r7, #4] 8002600: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8002602: 683b ldr r3, [r7, #0] 8002604: 681a ldr r2, [r3, #0] 8002606: 687b ldr r3, [r7, #4] 8002608: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800260a: 687b ldr r3, [r7, #4] 800260c: 4a0a ldr r2, [pc, #40] ; (8002638 ) 800260e: 4293 cmp r3, r2 8002610: d007 beq.n 8002622 8002612: 687b ldr r3, [r7, #4] 8002614: 4a0b ldr r2, [pc, #44] ; (8002644 ) 8002616: 4293 cmp r3, r2 8002618: d003 beq.n 8002622 800261a: 687b ldr r3, [r7, #4] 800261c: 4a0a ldr r2, [pc, #40] ; (8002648 ) 800261e: 4293 cmp r3, r2 8002620: d103 bne.n 800262a { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8002622: 683b ldr r3, [r7, #0] 8002624: 691a ldr r2, [r3, #16] 8002626: 687b ldr r3, [r7, #4] 8002628: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800262a: 687b ldr r3, [r7, #4] 800262c: 2201 movs r2, #1 800262e: 615a str r2, [r3, #20] } 8002630: 46c0 nop ; (mov r8, r8) 8002632: 46bd mov sp, r7 8002634: b004 add sp, #16 8002636: bd80 pop {r7, pc} 8002638: 40012c00 .word 0x40012c00 800263c: 40000400 .word 0x40000400 8002640: 40002000 .word 0x40002000 8002644: 40014400 .word 0x40014400 8002648: 40014800 .word 0x40014800 800264c: fffffcff .word 0xfffffcff 08002650 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8002650: b580 push {r7, lr} 8002652: b082 sub sp, #8 8002654: af00 add r7, sp, #0 8002656: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8002658: 46c0 nop ; (mov r8, r8) 800265a: 46bd mov sp, r7 800265c: b002 add sp, #8 800265e: bd80 pop {r7, pc} 08002660 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8002660: b580 push {r7, lr} 8002662: b082 sub sp, #8 8002664: af00 add r7, sp, #0 8002666: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8002668: 46c0 nop ; (mov r8, r8) 800266a: 46bd mov sp, r7 800266c: b002 add sp, #8 800266e: bd80 pop {r7, pc} 08002670 : */ #include "button.h" void GEI_BUTTON_CODE(struct button *bt,uint8_t in) { 8002670: b580 push {r7, lr} 8002672: b082 sub sp, #8 8002674: af00 add r7, sp, #0 8002676: 6078 str r0, [r7, #4] 8002678: 000a movs r2, r1 800267a: 1cfb adds r3, r7, #3 800267c: 701a strb r2, [r3, #0] #define t 250 bt->code=0; 800267e: 687b ldr r3, [r7, #4] 8002680: 2200 movs r2, #0 8002682: 601a str r2, [r3, #0] if(in==1) 8002684: 1cfb adds r3, r7, #3 8002686: 781b ldrb r3, [r3, #0] 8002688: 2b01 cmp r3, #1 800268a: d138 bne.n 80026fe { if(bt->lock==0) 800268c: 687b ldr r3, [r7, #4] 800268e: 791b ldrb r3, [r3, #4] 8002690: 2b00 cmp r3, #0 8002692: d120 bne.n 80026d6 { if(HAL_GetTick()time+t) 8002694: f7fe f9b8 bl 8000a08 8002698: 0002 movs r2, r0 800269a: 687b ldr r3, [r7, #4] 800269c: 689b ldr r3, [r3, #8] 800269e: 33fa adds r3, #250 ; 0xfa 80026a0: 429a cmp r2, r3 80026a2: d20d bcs.n 80026c0 { bt->times++; 80026a4: 687b ldr r3, [r7, #4] 80026a6: 68db ldr r3, [r3, #12] 80026a8: 1c5a adds r2, r3, #1 80026aa: 687b ldr r3, [r7, #4] 80026ac: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 80026ae: f7fe f9ab bl 8000a08 80026b2: 0002 movs r2, r0 80026b4: 687b ldr r3, [r7, #4] 80026b6: 609a str r2, [r3, #8] bt->lock=1; 80026b8: 687b ldr r3, [r7, #4] 80026ba: 2201 movs r2, #1 80026bc: 711a strb r2, [r3, #4] 80026be: e00a b.n 80026d6 }else { bt->times=1; 80026c0: 687b ldr r3, [r7, #4] 80026c2: 2201 movs r2, #1 80026c4: 60da str r2, [r3, #12] bt->time=HAL_GetTick(); 80026c6: f7fe f99f bl 8000a08 80026ca: 0002 movs r2, r0 80026cc: 687b ldr r3, [r7, #4] 80026ce: 609a str r2, [r3, #8] bt->lock=1; 80026d0: 687b ldr r3, [r7, #4] 80026d2: 2201 movs r2, #1 80026d4: 711a strb r2, [r3, #4] } } if(bt->lock==1) 80026d6: 687b ldr r3, [r7, #4] 80026d8: 791b ldrb r3, [r3, #4] 80026da: 2b01 cmp r3, #1 80026dc: d10f bne.n 80026fe { if(HAL_GetTick()>bt->time+t) 80026de: f7fe f993 bl 8000a08 80026e2: 0002 movs r2, r0 80026e4: 687b ldr r3, [r7, #4] 80026e6: 689b ldr r3, [r3, #8] 80026e8: 33fa adds r3, #250 ; 0xfa 80026ea: 429a cmp r2, r3 80026ec: d907 bls.n 80026fe { bt->code=-1; 80026ee: 687b ldr r3, [r7, #4] 80026f0: 2201 movs r2, #1 80026f2: 4252 negs r2, r2 80026f4: 601a str r2, [r3, #0] bt->times=-1; 80026f6: 687b ldr r3, [r7, #4] 80026f8: 2201 movs r2, #1 80026fa: 4252 negs r2, r2 80026fc: 60da str r2, [r3, #12] } } } if(in==0) 80026fe: 1cfb adds r3, r7, #3 8002700: 781b ldrb r3, [r3, #0] 8002702: 2b00 cmp r3, #0 8002704: d10e bne.n 8002724 { if(bt->lock==1) 8002706: 687b ldr r3, [r7, #4] 8002708: 791b ldrb r3, [r3, #4] 800270a: 2b01 cmp r3, #1 800270c: d10a bne.n 8002724 { if(bt->code==-1) 800270e: 687b ldr r3, [r7, #4] 8002710: 681b ldr r3, [r3, #0] 8002712: 3301 adds r3, #1 8002714: d003 beq.n 800271e { }else { bt->code=bt->times; 8002716: 687b ldr r3, [r7, #4] 8002718: 68da ldr r2, [r3, #12] 800271a: 687b ldr r3, [r7, #4] 800271c: 601a str r2, [r3, #0] } bt->lock=0; 800271e: 687b ldr r3, [r7, #4] 8002720: 2200 movs r2, #0 8002722: 711a strb r2, [r3, #4] } } } 8002724: 46c0 nop ; (mov r8, r8) 8002726: 46bd mov sp, r7 8002728: b002 add sp, #8 800272a: bd80 pop {r7, pc} 0800272c : //在AT24CXX指定地址读出一个数据 //ReadAddr:开始读数的地址 //返回值 :读到的数据 uint8_t AT24CXX_ReadOneByte(uint16_t ReadAddr) { 800272c: b5b0 push {r4, r5, r7, lr} 800272e: b084 sub sp, #16 8002730: af00 add r7, sp, #0 8002732: 0002 movs r2, r0 8002734: 1dbb adds r3, r7, #6 8002736: 801a strh r2, [r3, #0] uint8_t temp=0; 8002738: 240f movs r4, #15 800273a: 193b adds r3, r7, r4 800273c: 2200 movs r2, #0 800273e: 701a strb r2, [r3, #0] IIC_Start(); 8002740: f000 fa5a bl 8002bf8 { IIC_Send_Byte(0XA0); //发送写命令 IIC_Wait_Ack(); IIC_Send_Byte(ReadAddr>>8);//发送高地址 IIC_Wait_Ack(); }else IIC_Send_Byte(0XA0+((ReadAddr/256)<<1)); //发送器件地址0XA0,写数据 8002744: 1dbb adds r3, r7, #6 8002746: 881b ldrh r3, [r3, #0] 8002748: 0a1b lsrs r3, r3, #8 800274a: b29b uxth r3, r3 800274c: b2db uxtb r3, r3 800274e: 18db adds r3, r3, r3 8002750: b2db uxtb r3, r3 8002752: 3b60 subs r3, #96 ; 0x60 8002754: b2db uxtb r3, r3 8002756: 0018 movs r0, r3 8002758: f000 fb38 bl 8002dcc IIC_Wait_Ack(); 800275c: f000 faa0 bl 8002ca0 IIC_Send_Byte(ReadAddr%256); //发送低地址 8002760: 1dbb adds r3, r7, #6 8002762: 881b ldrh r3, [r3, #0] 8002764: b2db uxtb r3, r3 8002766: 0018 movs r0, r3 8002768: f000 fb30 bl 8002dcc IIC_Wait_Ack(); 800276c: f000 fa98 bl 8002ca0 IIC_Start(); 8002770: f000 fa42 bl 8002bf8 IIC_Send_Byte(0XA1); //进入接收模式 8002774: 20a1 movs r0, #161 ; 0xa1 8002776: f000 fb29 bl 8002dcc IIC_Wait_Ack(); 800277a: f000 fa91 bl 8002ca0 temp=IIC_Read_Byte(0); 800277e: 0025 movs r5, r4 8002780: 193c adds r4, r7, r4 8002782: 2000 movs r0, #0 8002784: f000 fb74 bl 8002e70 8002788: 0003 movs r3, r0 800278a: 7023 strb r3, [r4, #0] IIC_Stop();//产生一个停止条件 800278c: f000 fa5e bl 8002c4c return temp; 8002790: 197b adds r3, r7, r5 8002792: 781b ldrb r3, [r3, #0] } 8002794: 0018 movs r0, r3 8002796: 46bd mov sp, r7 8002798: b004 add sp, #16 800279a: bdb0 pop {r4, r5, r7, pc} 0800279c : //在AT24CXX指定地址写入一个数据 //WriteAddr :写入数据的目的地址 //DataToWrite:要写入的数据 void AT24CXX_WriteOneByte(uint16_t WriteAddr,uint8_t DataToWrite) { 800279c: b580 push {r7, lr} 800279e: b082 sub sp, #8 80027a0: af00 add r7, sp, #0 80027a2: 0002 movs r2, r0 80027a4: 1dbb adds r3, r7, #6 80027a6: 801a strh r2, [r3, #0] 80027a8: 1d7b adds r3, r7, #5 80027aa: 1c0a adds r2, r1, #0 80027ac: 701a strb r2, [r3, #0] IIC_Start(); 80027ae: f000 fa23 bl 8002bf8 IIC_Send_Byte(0XA0); //发送写命令 IIC_Wait_Ack(); IIC_Send_Byte(WriteAddr>>8);//发送高地址 }else { IIC_Send_Byte(0XA0+((WriteAddr/256)<<1)); //发送器件地址0XA0,写数据 80027b2: 1dbb adds r3, r7, #6 80027b4: 881b ldrh r3, [r3, #0] 80027b6: 0a1b lsrs r3, r3, #8 80027b8: b29b uxth r3, r3 80027ba: b2db uxtb r3, r3 80027bc: 18db adds r3, r3, r3 80027be: b2db uxtb r3, r3 80027c0: 3b60 subs r3, #96 ; 0x60 80027c2: b2db uxtb r3, r3 80027c4: 0018 movs r0, r3 80027c6: f000 fb01 bl 8002dcc } IIC_Wait_Ack(); 80027ca: f000 fa69 bl 8002ca0 IIC_Send_Byte(WriteAddr%256); //发送低地址 80027ce: 1dbb adds r3, r7, #6 80027d0: 881b ldrh r3, [r3, #0] 80027d2: b2db uxtb r3, r3 80027d4: 0018 movs r0, r3 80027d6: f000 faf9 bl 8002dcc IIC_Wait_Ack(); 80027da: f000 fa61 bl 8002ca0 IIC_Send_Byte(DataToWrite); //发送字节 80027de: 1d7b adds r3, r7, #5 80027e0: 781b ldrb r3, [r3, #0] 80027e2: 0018 movs r0, r3 80027e4: f000 faf2 bl 8002dcc IIC_Wait_Ack(); 80027e8: f000 fa5a bl 8002ca0 IIC_Stop();//产生一个停止条件 80027ec: f000 fa2e bl 8002c4c HAL_Delay(1); 80027f0: 2001 movs r0, #1 80027f2: f7fe f913 bl 8000a1c } 80027f6: 46c0 nop ; (mov r8, r8) 80027f8: 46bd mov sp, r7 80027fa: b002 add sp, #8 80027fc: bd80 pop {r7, pc} 080027fe : //在AT24CXX里面的指定地址开始读出指定个数的数据 //ReadAddr :开始读出的地址 对24c02为0~255 //pBuffer :数据数组首地址 //NumToRead:要读出数据的个数 void AT24CXX_Read(uint16_t ReadAddr,uint8_t *pBuffer,uint16_t NumToRead) { 80027fe: b590 push {r4, r7, lr} 8002800: b083 sub sp, #12 8002802: af00 add r7, sp, #0 8002804: 6039 str r1, [r7, #0] 8002806: 0011 movs r1, r2 8002808: 1dbb adds r3, r7, #6 800280a: 1c02 adds r2, r0, #0 800280c: 801a strh r2, [r3, #0] 800280e: 1d3b adds r3, r7, #4 8002810: 1c0a adds r2, r1, #0 8002812: 801a strh r2, [r3, #0] while(NumToRead) 8002814: e011 b.n 800283a { *pBuffer++=AT24CXX_ReadOneByte(ReadAddr++); 8002816: 1dbb adds r3, r7, #6 8002818: 881b ldrh r3, [r3, #0] 800281a: 1dba adds r2, r7, #6 800281c: 1c59 adds r1, r3, #1 800281e: 8011 strh r1, [r2, #0] 8002820: 683c ldr r4, [r7, #0] 8002822: 1c62 adds r2, r4, #1 8002824: 603a str r2, [r7, #0] 8002826: 0018 movs r0, r3 8002828: f7ff ff80 bl 800272c 800282c: 0003 movs r3, r0 800282e: 7023 strb r3, [r4, #0] NumToRead--; 8002830: 1d3b adds r3, r7, #4 8002832: 881a ldrh r2, [r3, #0] 8002834: 1d3b adds r3, r7, #4 8002836: 3a01 subs r2, #1 8002838: 801a strh r2, [r3, #0] while(NumToRead) 800283a: 1d3b adds r3, r7, #4 800283c: 881b ldrh r3, [r3, #0] 800283e: 2b00 cmp r3, #0 8002840: d1e9 bne.n 8002816 } } 8002842: 46c0 nop ; (mov r8, r8) 8002844: 46c0 nop ; (mov r8, r8) 8002846: 46bd mov sp, r7 8002848: b003 add sp, #12 800284a: bd90 pop {r4, r7, pc} 0800284c : //在AT24CXX里面的指定地址开始写入指定个数的数据 //WriteAddr :开始写入的地址 对24c02为0~255 //pBuffer :数据数组首地址 //NumToWrite:要写入数据的个数 void AT24CXX_Write(uint16_t WriteAddr,uint8_t *pBuffer,uint16_t NumToWrite) { 800284c: b580 push {r7, lr} 800284e: b082 sub sp, #8 8002850: af00 add r7, sp, #0 8002852: 6039 str r1, [r7, #0] 8002854: 0011 movs r1, r2 8002856: 1dbb adds r3, r7, #6 8002858: 1c02 adds r2, r0, #0 800285a: 801a strh r2, [r3, #0] 800285c: 1d3b adds r3, r7, #4 800285e: 1c0a adds r2, r1, #0 8002860: 801a strh r2, [r3, #0] while(NumToWrite--) 8002862: e00f b.n 8002884 { AT24CXX_WriteOneByte(WriteAddr,*pBuffer); 8002864: 683b ldr r3, [r7, #0] 8002866: 781a ldrb r2, [r3, #0] 8002868: 1dbb adds r3, r7, #6 800286a: 881b ldrh r3, [r3, #0] 800286c: 0011 movs r1, r2 800286e: 0018 movs r0, r3 8002870: f7ff ff94 bl 800279c WriteAddr++; 8002874: 1dbb adds r3, r7, #6 8002876: 881a ldrh r2, [r3, #0] 8002878: 1dbb adds r3, r7, #6 800287a: 3201 adds r2, #1 800287c: 801a strh r2, [r3, #0] pBuffer++; 800287e: 683b ldr r3, [r7, #0] 8002880: 3301 adds r3, #1 8002882: 603b str r3, [r7, #0] while(NumToWrite--) 8002884: 1d3b adds r3, r7, #4 8002886: 881b ldrh r3, [r3, #0] 8002888: 1d3a adds r2, r7, #4 800288a: 1e59 subs r1, r3, #1 800288c: 8011 strh r1, [r2, #0] 800288e: 2b00 cmp r3, #0 8002890: d1e8 bne.n 8002864 } } 8002892: 46c0 nop ; (mov r8, r8) 8002894: 46c0 nop ; (mov r8, r8) 8002896: 46bd mov sp, r7 8002898: b002 add sp, #8 800289a: bd80 pop {r7, pc} 0800289c : * Author: wuwenfeng */ #include "gpio.h" void change_io_function(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin,char a) { 800289c: b580 push {r7, lr} 800289e: b088 sub sp, #32 80028a0: af00 add r7, sp, #0 80028a2: 6078 str r0, [r7, #4] 80028a4: 0008 movs r0, r1 80028a6: 0011 movs r1, r2 80028a8: 1cbb adds r3, r7, #2 80028aa: 1c02 adds r2, r0, #0 80028ac: 801a strh r2, [r3, #0] 80028ae: 1c7b adds r3, r7, #1 80028b0: 1c0a adds r2, r1, #0 80028b2: 701a strb r2, [r3, #0] GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_Pin; 80028b4: 1cbb adds r3, r7, #2 80028b6: 881a ldrh r2, [r3, #0] 80028b8: 210c movs r1, #12 80028ba: 187b adds r3, r7, r1 80028bc: 601a str r2, [r3, #0] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80028be: 187b adds r3, r7, r1 80028c0: 2203 movs r2, #3 80028c2: 60da str r2, [r3, #12] if(a==1) 80028c4: 1c7b adds r3, r7, #1 80028c6: 781b ldrb r3, [r3, #0] 80028c8: 2b01 cmp r3, #1 80028ca: d105 bne.n 80028d8 { GPIO_InitStruct.Pull = GPIO_PULLUP; 80028cc: 187b adds r3, r7, r1 80028ce: 2201 movs r2, #1 80028d0: 609a str r2, [r3, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80028d2: 187b adds r3, r7, r1 80028d4: 2200 movs r2, #0 80028d6: 605a str r2, [r3, #4] } if(a==0) 80028d8: 1c7b adds r3, r7, #1 80028da: 781b ldrb r3, [r3, #0] 80028dc: 2b00 cmp r3, #0 80028de: d106 bne.n 80028ee { GPIO_InitStruct.Pull = GPIO_NOPULL; 80028e0: 210c movs r1, #12 80028e2: 187b adds r3, r7, r1 80028e4: 2200 movs r2, #0 80028e6: 609a str r2, [r3, #8] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80028e8: 187b adds r3, r7, r1 80028ea: 2201 movs r2, #1 80028ec: 605a str r2, [r3, #4] } HAL_GPIO_Init(GPIOx, &GPIO_InitStruct); 80028ee: 230c movs r3, #12 80028f0: 18fa adds r2, r7, r3 80028f2: 687b ldr r3, [r7, #4] 80028f4: 0011 movs r1, r2 80028f6: 0018 movs r0, r3 80028f8: f7fe fe42 bl 8001580 } 80028fc: 46c0 nop ; (mov r8, r8) 80028fe: 46bd mov sp, r7 8002900: b008 add sp, #32 8002902: bd80 pop {r7, pc} 08002904 : #include "my_code.h" #define HT1621_addrbit 6 void WriteClockHT1621(void) { 8002904: b580 push {r7, lr} 8002906: af00 add r7, sp, #0 HC595_SCK(0); 8002908: 2390 movs r3, #144 ; 0x90 800290a: 05db lsls r3, r3, #23 800290c: 2200 movs r2, #0 800290e: 2140 movs r1, #64 ; 0x40 8002910: 0018 movs r0, r3 8002912: f7fe ffc2 bl 800189a HC595_SCK(1); 8002916: 2390 movs r3, #144 ; 0x90 8002918: 05db lsls r3, r3, #23 800291a: 2201 movs r2, #1 800291c: 2140 movs r1, #64 ; 0x40 800291e: 0018 movs r0, r3 8002920: f7fe ffbb bl 800189a } 8002924: 46c0 nop ; (mov r8, r8) 8002926: 46bd mov sp, r7 8002928: bd80 pop {r7, pc} 0800292a : void WriteCommandHT1621(unsigned char FunctonCode) { 800292a: b580 push {r7, lr} 800292c: b084 sub sp, #16 800292e: af00 add r7, sp, #0 8002930: 0002 movs r2, r0 8002932: 1dfb adds r3, r7, #7 8002934: 701a strb r2, [r3, #0] unsigned char Shift = 0x80; 8002936: 230f movs r3, #15 8002938: 18fb adds r3, r7, r3 800293a: 2280 movs r2, #128 ; 0x80 800293c: 701a strb r2, [r3, #0] unsigned char i; HC595_RCK(0); 800293e: 2390 movs r3, #144 ; 0x90 8002940: 05db lsls r3, r3, #23 8002942: 2200 movs r2, #0 8002944: 2180 movs r1, #128 ; 0x80 8002946: 0018 movs r0, r3 8002948: f7fe ffa7 bl 800189a HC595_DCK(1); 800294c: 2390 movs r3, #144 ; 0x90 800294e: 05db lsls r3, r3, #23 8002950: 2201 movs r2, #1 8002952: 2120 movs r1, #32 8002954: 0018 movs r0, r3 8002956: f7fe ffa0 bl 800189a WriteClockHT1621(); 800295a: f7ff ffd3 bl 8002904 HC595_DCK(0); 800295e: 2390 movs r3, #144 ; 0x90 8002960: 05db lsls r3, r3, #23 8002962: 2200 movs r2, #0 8002964: 2120 movs r1, #32 8002966: 0018 movs r0, r3 8002968: f7fe ff97 bl 800189a WriteClockHT1621(); 800296c: f7ff ffca bl 8002904 HC595_DCK(0); 8002970: 2390 movs r3, #144 ; 0x90 8002972: 05db lsls r3, r3, #23 8002974: 2200 movs r2, #0 8002976: 2120 movs r1, #32 8002978: 0018 movs r0, r3 800297a: f7fe ff8e bl 800189a WriteClockHT1621(); 800297e: f7ff ffc1 bl 8002904 for(i = 0; i < 8; i++) 8002982: 230e movs r3, #14 8002984: 18fb adds r3, r7, r3 8002986: 2200 movs r2, #0 8002988: 701a strb r2, [r3, #0] 800298a: e025 b.n 80029d8 { if(Shift & FunctonCode) 800298c: 230f movs r3, #15 800298e: 18fb adds r3, r7, r3 8002990: 1dfa adds r2, r7, #7 8002992: 781b ldrb r3, [r3, #0] 8002994: 7812 ldrb r2, [r2, #0] 8002996: 4013 ands r3, r2 8002998: b2db uxtb r3, r3 800299a: 2b00 cmp r3, #0 800299c: d007 beq.n 80029ae {HC595_DCK(1);} 800299e: 2390 movs r3, #144 ; 0x90 80029a0: 05db lsls r3, r3, #23 80029a2: 2201 movs r2, #1 80029a4: 2120 movs r1, #32 80029a6: 0018 movs r0, r3 80029a8: f7fe ff77 bl 800189a 80029ac: e006 b.n 80029bc else {HC595_DCK(0);} 80029ae: 2390 movs r3, #144 ; 0x90 80029b0: 05db lsls r3, r3, #23 80029b2: 2200 movs r2, #0 80029b4: 2120 movs r1, #32 80029b6: 0018 movs r0, r3 80029b8: f7fe ff6f bl 800189a WriteClockHT1621(); 80029bc: f7ff ffa2 bl 8002904 Shift = Shift >> 1; 80029c0: 220f movs r2, #15 80029c2: 18bb adds r3, r7, r2 80029c4: 18ba adds r2, r7, r2 80029c6: 7812 ldrb r2, [r2, #0] 80029c8: 0852 lsrs r2, r2, #1 80029ca: 701a strb r2, [r3, #0] for(i = 0; i < 8; i++) 80029cc: 210e movs r1, #14 80029ce: 187b adds r3, r7, r1 80029d0: 781a ldrb r2, [r3, #0] 80029d2: 187b adds r3, r7, r1 80029d4: 3201 adds r2, #1 80029d6: 701a strb r2, [r3, #0] 80029d8: 230e movs r3, #14 80029da: 18fb adds r3, r7, r3 80029dc: 781b ldrb r3, [r3, #0] 80029de: 2b07 cmp r3, #7 80029e0: d9d4 bls.n 800298c } {HC595_DCK(0);} 80029e2: 2390 movs r3, #144 ; 0x90 80029e4: 05db lsls r3, r3, #23 80029e6: 2200 movs r2, #0 80029e8: 2120 movs r1, #32 80029ea: 0018 movs r0, r3 80029ec: f7fe ff55 bl 800189a WriteClockHT1621(); 80029f0: f7ff ff88 bl 8002904 HC595_RCK(1); 80029f4: 2390 movs r3, #144 ; 0x90 80029f6: 05db lsls r3, r3, #23 80029f8: 2201 movs r2, #1 80029fa: 2180 movs r1, #128 ; 0x80 80029fc: 0018 movs r0, r3 80029fe: f7fe ff4c bl 800189a HC595_DCK(1); 8002a02: 2390 movs r3, #144 ; 0x90 8002a04: 05db lsls r3, r3, #23 8002a06: 2201 movs r2, #1 8002a08: 2120 movs r1, #32 8002a0a: 0018 movs r0, r3 8002a0c: f7fe ff45 bl 800189a } 8002a10: 46c0 nop ; (mov r8, r8) 8002a12: 46bd mov sp, r7 8002a14: b004 add sp, #16 8002a16: bd80 pop {r7, pc} 08002a18 : void WritenDataHT1621(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt) { 8002a18: b580 push {r7, lr} 8002a1a: b084 sub sp, #16 8002a1c: af00 add r7, sp, #0 8002a1e: 6039 str r1, [r7, #0] 8002a20: 0011 movs r1, r2 8002a22: 1dfb adds r3, r7, #7 8002a24: 1c02 adds r2, r0, #0 8002a26: 701a strb r2, [r3, #0] 8002a28: 1dbb adds r3, r7, #6 8002a2a: 1c0a adds r2, r1, #0 8002a2c: 701a strb r2, [r3, #0] unsigned char i,j; unsigned char Shift; unsigned char dataval; HC595_RCK(0); 8002a2e: 2390 movs r3, #144 ; 0x90 8002a30: 05db lsls r3, r3, #23 8002a32: 2200 movs r2, #0 8002a34: 2180 movs r1, #128 ; 0x80 8002a36: 0018 movs r0, r3 8002a38: f7fe ff2f bl 800189a HC595_DCK(1); //101 8002a3c: 2390 movs r3, #144 ; 0x90 8002a3e: 05db lsls r3, r3, #23 8002a40: 2201 movs r2, #1 8002a42: 2120 movs r1, #32 8002a44: 0018 movs r0, r3 8002a46: f7fe ff28 bl 800189a WriteClockHT1621(); 8002a4a: f7ff ff5b bl 8002904 HC595_DCK(0); 8002a4e: 2390 movs r3, #144 ; 0x90 8002a50: 05db lsls r3, r3, #23 8002a52: 2200 movs r2, #0 8002a54: 2120 movs r1, #32 8002a56: 0018 movs r0, r3 8002a58: f7fe ff1f bl 800189a WriteClockHT1621(); 8002a5c: f7ff ff52 bl 8002904 HC595_DCK(1); 8002a60: 2390 movs r3, #144 ; 0x90 8002a62: 05db lsls r3, r3, #23 8002a64: 2201 movs r2, #1 8002a66: 2120 movs r1, #32 8002a68: 0018 movs r0, r3 8002a6a: f7fe ff16 bl 800189a WriteClockHT1621(); 8002a6e: f7ff ff49 bl 8002904 Shift = 0x20; 8002a72: 230d movs r3, #13 8002a74: 18fb adds r3, r7, r3 8002a76: 2220 movs r2, #32 8002a78: 701a strb r2, [r3, #0] for( i = 0; i < HT1621_addrbit; i++) 8002a7a: 230f movs r3, #15 8002a7c: 18fb adds r3, r7, r3 8002a7e: 2200 movs r2, #0 8002a80: 701a strb r2, [r3, #0] 8002a82: e025 b.n 8002ad0 { if (Addr & Shift) 8002a84: 1dfb adds r3, r7, #7 8002a86: 220d movs r2, #13 8002a88: 18ba adds r2, r7, r2 8002a8a: 781b ldrb r3, [r3, #0] 8002a8c: 7812 ldrb r2, [r2, #0] 8002a8e: 4013 ands r3, r2 8002a90: b2db uxtb r3, r3 8002a92: 2b00 cmp r3, #0 8002a94: d007 beq.n 8002aa6 {HC595_DCK(1);} 8002a96: 2390 movs r3, #144 ; 0x90 8002a98: 05db lsls r3, r3, #23 8002a9a: 2201 movs r2, #1 8002a9c: 2120 movs r1, #32 8002a9e: 0018 movs r0, r3 8002aa0: f7fe fefb bl 800189a 8002aa4: e006 b.n 8002ab4 else {HC595_DCK(0);} 8002aa6: 2390 movs r3, #144 ; 0x90 8002aa8: 05db lsls r3, r3, #23 8002aaa: 2200 movs r2, #0 8002aac: 2120 movs r1, #32 8002aae: 0018 movs r0, r3 8002ab0: f7fe fef3 bl 800189a WriteClockHT1621(); 8002ab4: f7ff ff26 bl 8002904 Shift = Shift >> 1; 8002ab8: 220d movs r2, #13 8002aba: 18bb adds r3, r7, r2 8002abc: 18ba adds r2, r7, r2 8002abe: 7812 ldrb r2, [r2, #0] 8002ac0: 0852 lsrs r2, r2, #1 8002ac2: 701a strb r2, [r3, #0] for( i = 0; i < HT1621_addrbit; i++) 8002ac4: 210f movs r1, #15 8002ac6: 187b adds r3, r7, r1 8002ac8: 781a ldrb r2, [r3, #0] 8002aca: 187b adds r3, r7, r1 8002acc: 3201 adds r2, #1 8002ace: 701a strb r2, [r3, #0] 8002ad0: 230f movs r3, #15 8002ad2: 18fb adds r3, r7, r3 8002ad4: 781b ldrb r3, [r3, #0] 8002ad6: 2b05 cmp r3, #5 8002ad8: d9d4 bls.n 8002a84 } for (j = 0; j < Cnt; j++) 8002ada: 230e movs r3, #14 8002adc: 18fb adds r3, r7, r3 8002ade: 2200 movs r2, #0 8002ae0: 701a strb r2, [r3, #0] 8002ae2: e041 b.n 8002b68 { Shift = 0x01; 8002ae4: 230d movs r3, #13 8002ae6: 18fb adds r3, r7, r3 8002ae8: 2201 movs r2, #1 8002aea: 701a strb r2, [r3, #0] dataval=*Databuf++; 8002aec: 683b ldr r3, [r7, #0] 8002aee: 1c5a adds r2, r3, #1 8002af0: 603a str r2, [r7, #0] 8002af2: 220c movs r2, #12 8002af4: 18ba adds r2, r7, r2 8002af6: 781b ldrb r3, [r3, #0] 8002af8: 7013 strb r3, [r2, #0] for (i = 0; i < 4; i++) 8002afa: 230f movs r3, #15 8002afc: 18fb adds r3, r7, r3 8002afe: 2200 movs r2, #0 8002b00: 701a strb r2, [r3, #0] 8002b02: e026 b.n 8002b52 { if( dataval & Shift) 8002b04: 230c movs r3, #12 8002b06: 18fb adds r3, r7, r3 8002b08: 220d movs r2, #13 8002b0a: 18ba adds r2, r7, r2 8002b0c: 781b ldrb r3, [r3, #0] 8002b0e: 7812 ldrb r2, [r2, #0] 8002b10: 4013 ands r3, r2 8002b12: b2db uxtb r3, r3 8002b14: 2b00 cmp r3, #0 8002b16: d007 beq.n 8002b28 {HC595_DCK(1);} 8002b18: 2390 movs r3, #144 ; 0x90 8002b1a: 05db lsls r3, r3, #23 8002b1c: 2201 movs r2, #1 8002b1e: 2120 movs r1, #32 8002b20: 0018 movs r0, r3 8002b22: f7fe feba bl 800189a 8002b26: e006 b.n 8002b36 else {HC595_DCK(0);} 8002b28: 2390 movs r3, #144 ; 0x90 8002b2a: 05db lsls r3, r3, #23 8002b2c: 2200 movs r2, #0 8002b2e: 2120 movs r1, #32 8002b30: 0018 movs r0, r3 8002b32: f7fe feb2 bl 800189a WriteClockHT1621(); 8002b36: f7ff fee5 bl 8002904 Shift = Shift << 1; 8002b3a: 230d movs r3, #13 8002b3c: 18fa adds r2, r7, r3 8002b3e: 18fb adds r3, r7, r3 8002b40: 781b ldrb r3, [r3, #0] 8002b42: 18db adds r3, r3, r3 8002b44: 7013 strb r3, [r2, #0] for (i = 0; i < 4; i++) 8002b46: 210f movs r1, #15 8002b48: 187b adds r3, r7, r1 8002b4a: 781a ldrb r2, [r3, #0] 8002b4c: 187b adds r3, r7, r1 8002b4e: 3201 adds r2, #1 8002b50: 701a strb r2, [r3, #0] 8002b52: 230f movs r3, #15 8002b54: 18fb adds r3, r7, r3 8002b56: 781b ldrb r3, [r3, #0] 8002b58: 2b03 cmp r3, #3 8002b5a: d9d3 bls.n 8002b04 for (j = 0; j < Cnt; j++) 8002b5c: 210e movs r1, #14 8002b5e: 187b adds r3, r7, r1 8002b60: 781a ldrb r2, [r3, #0] 8002b62: 187b adds r3, r7, r1 8002b64: 3201 adds r2, #1 8002b66: 701a strb r2, [r3, #0] 8002b68: 230e movs r3, #14 8002b6a: 18fa adds r2, r7, r3 8002b6c: 1dbb adds r3, r7, #6 8002b6e: 7812 ldrb r2, [r2, #0] 8002b70: 781b ldrb r3, [r3, #0] 8002b72: 429a cmp r2, r3 8002b74: d3b6 bcc.n 8002ae4 } } HC595_RCK(1); 8002b76: 2390 movs r3, #144 ; 0x90 8002b78: 05db lsls r3, r3, #23 8002b7a: 2201 movs r2, #1 8002b7c: 2180 movs r1, #128 ; 0x80 8002b7e: 0018 movs r0, r3 8002b80: f7fe fe8b bl 800189a HC595_DCK(1); 8002b84: 2390 movs r3, #144 ; 0x90 8002b86: 05db lsls r3, r3, #23 8002b88: 2201 movs r2, #1 8002b8a: 2120 movs r1, #32 8002b8c: 0018 movs r0, r3 8002b8e: f7fe fe84 bl 800189a } 8002b92: 46c0 nop ; (mov r8, r8) 8002b94: 46bd mov sp, r7 8002b96: b004 add sp, #16 8002b98: bd80 pop {r7, pc} 08002b9a : void HT1621_Init(void) { 8002b9a: b580 push {r7, lr} 8002b9c: af00 add r7, sp, #0 HC595_RCK(1); 8002b9e: 2390 movs r3, #144 ; 0x90 8002ba0: 05db lsls r3, r3, #23 8002ba2: 2201 movs r2, #1 8002ba4: 2180 movs r1, #128 ; 0x80 8002ba6: 0018 movs r0, r3 8002ba8: f7fe fe77 bl 800189a HC595_SCK(1); 8002bac: 2390 movs r3, #144 ; 0x90 8002bae: 05db lsls r3, r3, #23 8002bb0: 2201 movs r2, #1 8002bb2: 2140 movs r1, #64 ; 0x40 8002bb4: 0018 movs r0, r3 8002bb6: f7fe fe70 bl 800189a HC595_DCK(1); 8002bba: 2390 movs r3, #144 ; 0x90 8002bbc: 05db lsls r3, r3, #23 8002bbe: 2201 movs r2, #1 8002bc0: 2120 movs r1, #32 8002bc2: 0018 movs r0, r3 8002bc4: f7fe fe69 bl 800189a WriteCommandHT1621(OSC_ON); 8002bc8: 2001 movs r0, #1 8002bca: f7ff feae bl 800292a WriteCommandHT1621(DISP_ON); 8002bce: 2003 movs r0, #3 8002bd0: f7ff feab bl 800292a WriteCommandHT1621(COM_1_3__4); 8002bd4: 2029 movs r0, #41 ; 0x29 8002bd6: f7ff fea8 bl 800292a WriteCommandHT1621(TIMER_DIS); 8002bda: 2004 movs r0, #4 8002bdc: f7ff fea5 bl 800292a WriteCommandHT1621(WDT_DIS); 8002be0: 2005 movs r0, #5 8002be2: f7ff fea2 bl 800292a WriteCommandHT1621(BUZZ_OFF); 8002be6: 2008 movs r0, #8 8002be8: f7ff fe9f bl 800292a WriteCommandHT1621(IRQ_DIS); 8002bec: 2080 movs r0, #128 ; 0x80 8002bee: f7ff fe9c bl 800292a } 8002bf2: 46c0 nop ; (mov r8, r8) 8002bf4: 46bd mov sp, r7 8002bf6: bd80 pop {r7, pc} 08002bf8 : #define SDA_IN() change_io_function(iic_sda_GPIO_Port, iic_sda_Pin,1) #define READ_SDA read_iic_sda //产生IIC起始信号 void IIC_Start(void) { 8002bf8: b580 push {r7, lr} 8002bfa: af00 add r7, sp, #0 SDA_OUT(); //sda线输出 8002bfc: 4b12 ldr r3, [pc, #72] ; (8002c48 ) 8002bfe: 2200 movs r2, #0 8002c00: 2102 movs r1, #2 8002c02: 0018 movs r0, r3 8002c04: f7ff fe4a bl 800289c IIC_SDA_SET; 8002c08: 4b0f ldr r3, [pc, #60] ; (8002c48 ) 8002c0a: 2201 movs r2, #1 8002c0c: 2102 movs r1, #2 8002c0e: 0018 movs r0, r3 8002c10: f7fe fe43 bl 800189a IIC_SCL_SET; 8002c14: 2380 movs r3, #128 ; 0x80 8002c16: 00d9 lsls r1, r3, #3 8002c18: 2390 movs r3, #144 ; 0x90 8002c1a: 05db lsls r3, r3, #23 8002c1c: 2201 movs r2, #1 8002c1e: 0018 movs r0, r3 8002c20: f7fe fe3b bl 800189a IIC_SDA_CLR;//START:when CLK is high,DATA change form high to low 8002c24: 4b08 ldr r3, [pc, #32] ; (8002c48 ) 8002c26: 2200 movs r2, #0 8002c28: 2102 movs r1, #2 8002c2a: 0018 movs r0, r3 8002c2c: f7fe fe35 bl 800189a IIC_SCL_CLR;//钳住I2C总线，准备发送或接收数据 8002c30: 2380 movs r3, #128 ; 0x80 8002c32: 00d9 lsls r1, r3, #3 8002c34: 2390 movs r3, #144 ; 0x90 8002c36: 05db lsls r3, r3, #23 8002c38: 2200 movs r2, #0 8002c3a: 0018 movs r0, r3 8002c3c: f7fe fe2d bl 800189a } 8002c40: 46c0 nop ; (mov r8, r8) 8002c42: 46bd mov sp, r7 8002c44: bd80 pop {r7, pc} 8002c46: 46c0 nop ; (mov r8, r8) 8002c48: 48000400 .word 0x48000400 08002c4c : //产生IIC停止信号 void IIC_Stop(void) { 8002c4c: b580 push {r7, lr} 8002c4e: af00 add r7, sp, #0 SDA_OUT();//sda线输出 8002c50: 4b12 ldr r3, [pc, #72] ; (8002c9c ) 8002c52: 2200 movs r2, #0 8002c54: 2102 movs r1, #2 8002c56: 0018 movs r0, r3 8002c58: f7ff fe20 bl 800289c IIC_SCL_CLR; 8002c5c: 2380 movs r3, #128 ; 0x80 8002c5e: 00d9 lsls r1, r3, #3 8002c60: 2390 movs r3, #144 ; 0x90 8002c62: 05db lsls r3, r3, #23 8002c64: 2200 movs r2, #0 8002c66: 0018 movs r0, r3 8002c68: f7fe fe17 bl 800189a IIC_SDA_CLR;//STOP:when CLK is high DATA change form low to high 8002c6c: 4b0b ldr r3, [pc, #44] ; (8002c9c ) 8002c6e: 2200 movs r2, #0 8002c70: 2102 movs r1, #2 8002c72: 0018 movs r0, r3 8002c74: f7fe fe11 bl 800189a IIC_SCL_SET; 8002c78: 2380 movs r3, #128 ; 0x80 8002c7a: 00d9 lsls r1, r3, #3 8002c7c: 2390 movs r3, #144 ; 0x90 8002c7e: 05db lsls r3, r3, #23 8002c80: 2201 movs r2, #1 8002c82: 0018 movs r0, r3 8002c84: f7fe fe09 bl 800189a IIC_SDA_SET;//发送I2C总线结束信号 8002c88: 4b04 ldr r3, [pc, #16] ; (8002c9c ) 8002c8a: 2201 movs r2, #1 8002c8c: 2102 movs r1, #2 8002c8e: 0018 movs r0, r3 8002c90: f7fe fe03 bl 800189a } 8002c94: 46c0 nop ; (mov r8, r8) 8002c96: 46bd mov sp, r7 8002c98: bd80 pop {r7, pc} 8002c9a: 46c0 nop ; (mov r8, r8) 8002c9c: 48000400 .word 0x48000400 08002ca0 : //等待应答信号到来 //返回值：1，接收应答失败 // 0，接收应答成功 uint8_t IIC_Wait_Ack(void) { 8002ca0: b580 push {r7, lr} 8002ca2: b082 sub sp, #8 8002ca4: af00 add r7, sp, #0 uint8_t ucErrTime=0; 8002ca6: 1dfb adds r3, r7, #7 8002ca8: 2200 movs r2, #0 8002caa: 701a strb r2, [r3, #0] SDA_IN(); //SDA设置为输入 8002cac: 4b1a ldr r3, [pc, #104] ; (8002d18 ) 8002cae: 2201 movs r2, #1 8002cb0: 2102 movs r1, #2 8002cb2: 0018 movs r0, r3 8002cb4: f7ff fdf2 bl 800289c IIC_SDA_SET; 8002cb8: 4b17 ldr r3, [pc, #92] ; (8002d18 ) 8002cba: 2201 movs r2, #1 8002cbc: 2102 movs r1, #2 8002cbe: 0018 movs r0, r3 8002cc0: f7fe fdeb bl 800189a IIC_SCL_SET; 8002cc4: 2380 movs r3, #128 ; 0x80 8002cc6: 00d9 lsls r1, r3, #3 8002cc8: 2390 movs r3, #144 ; 0x90 8002cca: 05db lsls r3, r3, #23 8002ccc: 2201 movs r2, #1 8002cce: 0018 movs r0, r3 8002cd0: f7fe fde3 bl 800189a while(READ_SDA) 8002cd4: e00c b.n 8002cf0 { ucErrTime++; 8002cd6: 1dfb adds r3, r7, #7 8002cd8: 781a ldrb r2, [r3, #0] 8002cda: 1dfb adds r3, r7, #7 8002cdc: 3201 adds r2, #1 8002cde: 701a strb r2, [r3, #0] if(ucErrTime>250) 8002ce0: 1dfb adds r3, r7, #7 8002ce2: 781b ldrb r3, [r3, #0] 8002ce4: 2bfa cmp r3, #250 ; 0xfa 8002ce6: d903 bls.n 8002cf0 { IIC_Stop(); 8002ce8: f7ff ffb0 bl 8002c4c return 1; 8002cec: 2301 movs r3, #1 8002cee: e00f b.n 8002d10 while(READ_SDA) 8002cf0: 4b09 ldr r3, [pc, #36] ; (8002d18 ) 8002cf2: 2102 movs r1, #2 8002cf4: 0018 movs r0, r3 8002cf6: f7fe fdb3 bl 8001860 8002cfa: 1e03 subs r3, r0, #0 8002cfc: d1eb bne.n 8002cd6 } } IIC_SCL_CLR;//时钟输出0 8002cfe: 2380 movs r3, #128 ; 0x80 8002d00: 00d9 lsls r1, r3, #3 8002d02: 2390 movs r3, #144 ; 0x90 8002d04: 05db lsls r3, r3, #23 8002d06: 2200 movs r2, #0 8002d08: 0018 movs r0, r3 8002d0a: f7fe fdc6 bl 800189a return 0; 8002d0e: 2300 movs r3, #0 } 8002d10: 0018 movs r0, r3 8002d12: 46bd mov sp, r7 8002d14: b002 add sp, #8 8002d16: bd80 pop {r7, pc} 8002d18: 48000400 .word 0x48000400 08002d1c : //产生ACK应答 void IIC_Ack(void) { 8002d1c: b580 push {r7, lr} 8002d1e: af00 add r7, sp, #0 IIC_SCL_CLR; 8002d20: 2380 movs r3, #128 ; 0x80 8002d22: 00d9 lsls r1, r3, #3 8002d24: 2390 movs r3, #144 ; 0x90 8002d26: 05db lsls r3, r3, #23 8002d28: 2200 movs r2, #0 8002d2a: 0018 movs r0, r3 8002d2c: f7fe fdb5 bl 800189a SDA_OUT(); 8002d30: 4b0f ldr r3, [pc, #60] ; (8002d70 ) 8002d32: 2200 movs r2, #0 8002d34: 2102 movs r1, #2 8002d36: 0018 movs r0, r3 8002d38: f7ff fdb0 bl 800289c IIC_SDA_CLR; 8002d3c: 4b0c ldr r3, [pc, #48] ; (8002d70 ) 8002d3e: 2200 movs r2, #0 8002d40: 2102 movs r1, #2 8002d42: 0018 movs r0, r3 8002d44: f7fe fda9 bl 800189a IIC_SCL_SET; 8002d48: 2380 movs r3, #128 ; 0x80 8002d4a: 00d9 lsls r1, r3, #3 8002d4c: 2390 movs r3, #144 ; 0x90 8002d4e: 05db lsls r3, r3, #23 8002d50: 2201 movs r2, #1 8002d52: 0018 movs r0, r3 8002d54: f7fe fda1 bl 800189a IIC_SCL_CLR; 8002d58: 2380 movs r3, #128 ; 0x80 8002d5a: 00d9 lsls r1, r3, #3 8002d5c: 2390 movs r3, #144 ; 0x90 8002d5e: 05db lsls r3, r3, #23 8002d60: 2200 movs r2, #0 8002d62: 0018 movs r0, r3 8002d64: f7fe fd99 bl 800189a } 8002d68: 46c0 nop ; (mov r8, r8) 8002d6a: 46bd mov sp, r7 8002d6c: bd80 pop {r7, pc} 8002d6e: 46c0 nop ; (mov r8, r8) 8002d70: 48000400 .word 0x48000400 08002d74 : //不产生ACK应答 void IIC_NAck(void) { 8002d74: b580 push {r7, lr} 8002d76: af00 add r7, sp, #0 IIC_SCL_CLR; 8002d78: 2380 movs r3, #128 ; 0x80 8002d7a: 00d9 lsls r1, r3, #3 8002d7c: 2390 movs r3, #144 ; 0x90 8002d7e: 05db lsls r3, r3, #23 8002d80: 2200 movs r2, #0 8002d82: 0018 movs r0, r3 8002d84: f7fe fd89 bl 800189a SDA_OUT(); 8002d88: 4b0f ldr r3, [pc, #60] ; (8002dc8 ) 8002d8a: 2200 movs r2, #0 8002d8c: 2102 movs r1, #2 8002d8e: 0018 movs r0, r3 8002d90: f7ff fd84 bl 800289c IIC_SDA_SET; 8002d94: 4b0c ldr r3, [pc, #48] ; (8002dc8 ) 8002d96: 2201 movs r2, #1 8002d98: 2102 movs r1, #2 8002d9a: 0018 movs r0, r3 8002d9c: f7fe fd7d bl 800189a IIC_SCL_SET; 8002da0: 2380 movs r3, #128 ; 0x80 8002da2: 00d9 lsls r1, r3, #3 8002da4: 2390 movs r3, #144 ; 0x90 8002da6: 05db lsls r3, r3, #23 8002da8: 2201 movs r2, #1 8002daa: 0018 movs r0, r3 8002dac: f7fe fd75 bl 800189a IIC_SCL_CLR; 8002db0: 2380 movs r3, #128 ; 0x80 8002db2: 00d9 lsls r1, r3, #3 8002db4: 2390 movs r3, #144 ; 0x90 8002db6: 05db lsls r3, r3, #23 8002db8: 2200 movs r2, #0 8002dba: 0018 movs r0, r3 8002dbc: f7fe fd6d bl 800189a } 8002dc0: 46c0 nop ; (mov r8, r8) 8002dc2: 46bd mov sp, r7 8002dc4: bd80 pop {r7, pc} 8002dc6: 46c0 nop ; (mov r8, r8) 8002dc8: 48000400 .word 0x48000400 08002dcc : //IIC发送一个字节 //返回从机有无应答 //1，有应答 //0，无应答 void IIC_Send_Byte(uint8_t txd) { 8002dcc: b580 push {r7, lr} 8002dce: b084 sub sp, #16 8002dd0: af00 add r7, sp, #0 8002dd2: 0002 movs r2, r0 8002dd4: 1dfb adds r3, r7, #7 8002dd6: 701a strb r2, [r3, #0] uint8_t t; SDA_OUT(); 8002dd8: 4b24 ldr r3, [pc, #144] ; (8002e6c ) 8002dda: 2200 movs r2, #0 8002ddc: 2102 movs r1, #2 8002dde: 0018 movs r0, r3 8002de0: f7ff fd5c bl 800289c IIC_SCL_CLR;//拉低时钟开始数据传输 8002de4: 2380 movs r3, #128 ; 0x80 8002de6: 00d9 lsls r1, r3, #3 8002de8: 2390 movs r3, #144 ; 0x90 8002dea: 05db lsls r3, r3, #23 8002dec: 2200 movs r2, #0 8002dee: 0018 movs r0, r3 8002df0: f7fe fd53 bl 800189a for(t=0;t<8;t++) 8002df4: 230f movs r3, #15 8002df6: 18fb adds r3, r7, r3 8002df8: 2200 movs r2, #0 8002dfa: 701a strb r2, [r3, #0] 8002dfc: e02c b.n 8002e58 { //IIC_SDA=(txd&0x80)>>7; if((txd&0x80)>>7) 8002dfe: 1dfb adds r3, r7, #7 8002e00: 781b ldrb r3, [r3, #0] 8002e02: b25b sxtb r3, r3 8002e04: 2b00 cmp r3, #0 8002e06: da06 bge.n 8002e16 IIC_SDA_SET; 8002e08: 4b18 ldr r3, [pc, #96] ; (8002e6c ) 8002e0a: 2201 movs r2, #1 8002e0c: 2102 movs r1, #2 8002e0e: 0018 movs r0, r3 8002e10: f7fe fd43 bl 800189a 8002e14: e005 b.n 8002e22 else IIC_SDA_CLR; 8002e16: 4b15 ldr r3, [pc, #84] ; (8002e6c ) 8002e18: 2200 movs r2, #0 8002e1a: 2102 movs r1, #2 8002e1c: 0018 movs r0, r3 8002e1e: f7fe fd3c bl 800189a txd<<=1; 8002e22: 1dfa adds r2, r7, #7 8002e24: 1dfb adds r3, r7, #7 8002e26: 781b ldrb r3, [r3, #0] 8002e28: 18db adds r3, r3, r3 8002e2a: 7013 strb r3, [r2, #0] IIC_SCL_SET; 8002e2c: 2380 movs r3, #128 ; 0x80 8002e2e: 00d9 lsls r1, r3, #3 8002e30: 2390 movs r3, #144 ; 0x90 8002e32: 05db lsls r3, r3, #23 8002e34: 2201 movs r2, #1 8002e36: 0018 movs r0, r3 8002e38: f7fe fd2f bl 800189a IIC_SCL_CLR; 8002e3c: 2380 movs r3, #128 ; 0x80 8002e3e: 00d9 lsls r1, r3, #3 8002e40: 2390 movs r3, #144 ; 0x90 8002e42: 05db lsls r3, r3, #23 8002e44: 2200 movs r2, #0 8002e46: 0018 movs r0, r3 8002e48: f7fe fd27 bl 800189a for(t=0;t<8;t++) 8002e4c: 210f movs r1, #15 8002e4e: 187b adds r3, r7, r1 8002e50: 781a ldrb r2, [r3, #0] 8002e52: 187b adds r3, r7, r1 8002e54: 3201 adds r2, #1 8002e56: 701a strb r2, [r3, #0] 8002e58: 230f movs r3, #15 8002e5a: 18fb adds r3, r7, r3 8002e5c: 781b ldrb r3, [r3, #0] 8002e5e: 2b07 cmp r3, #7 8002e60: d9cd bls.n 8002dfe } } 8002e62: 46c0 nop ; (mov r8, r8) 8002e64: 46c0 nop ; (mov r8, r8) 8002e66: 46bd mov sp, r7 8002e68: b004 add sp, #16 8002e6a: bd80 pop {r7, pc} 8002e6c: 48000400 .word 0x48000400 08002e70 : //读1个字节，ack=1时，发送ACK，ack=0，发送nACK uint8_t IIC_Read_Byte(unsigned char ack) { 8002e70: b590 push {r4, r7, lr} 8002e72: b085 sub sp, #20 8002e74: af00 add r7, sp, #0 8002e76: 0002 movs r2, r0 8002e78: 1dfb adds r3, r7, #7 8002e7a: 701a strb r2, [r3, #0] unsigned char i,receive=0; 8002e7c: 230e movs r3, #14 8002e7e: 18fb adds r3, r7, r3 8002e80: 2200 movs r2, #0 8002e82: 701a strb r2, [r3, #0] SDA_IN();//SDA设置为输入 8002e84: 4b23 ldr r3, [pc, #140] ; (8002f14 ) 8002e86: 2201 movs r2, #1 8002e88: 2102 movs r1, #2 8002e8a: 0018 movs r0, r3 8002e8c: f7ff fd06 bl 800289c for(i=0;i<8;i++ ) 8002e90: 230f movs r3, #15 8002e92: 18fb adds r3, r7, r3 8002e94: 2200 movs r2, #0 8002e96: 701a strb r2, [r3, #0] 8002e98: e027 b.n 8002eea { IIC_SCL_CLR; 8002e9a: 2380 movs r3, #128 ; 0x80 8002e9c: 00d9 lsls r1, r3, #3 8002e9e: 2390 movs r3, #144 ; 0x90 8002ea0: 05db lsls r3, r3, #23 8002ea2: 2200 movs r2, #0 8002ea4: 0018 movs r0, r3 8002ea6: f7fe fcf8 bl 800189a IIC_SCL_SET; 8002eaa: 2380 movs r3, #128 ; 0x80 8002eac: 00d9 lsls r1, r3, #3 8002eae: 2390 movs r3, #144 ; 0x90 8002eb0: 05db lsls r3, r3, #23 8002eb2: 2201 movs r2, #1 8002eb4: 0018 movs r0, r3 8002eb6: f7fe fcf0 bl 800189a receive<<=1; 8002eba: 240e movs r4, #14 8002ebc: 193a adds r2, r7, r4 8002ebe: 193b adds r3, r7, r4 8002ec0: 781b ldrb r3, [r3, #0] 8002ec2: 18db adds r3, r3, r3 8002ec4: 7013 strb r3, [r2, #0] if(READ_SDA)receive++; 8002ec6: 4b13 ldr r3, [pc, #76] ; (8002f14 ) 8002ec8: 2102 movs r1, #2 8002eca: 0018 movs r0, r3 8002ecc: f7fe fcc8 bl 8001860 8002ed0: 1e03 subs r3, r0, #0 8002ed2: d004 beq.n 8002ede 8002ed4: 193b adds r3, r7, r4 8002ed6: 781a ldrb r2, [r3, #0] 8002ed8: 193b adds r3, r7, r4 8002eda: 3201 adds r2, #1 8002edc: 701a strb r2, [r3, #0] for(i=0;i<8;i++ ) 8002ede: 210f movs r1, #15 8002ee0: 187b adds r3, r7, r1 8002ee2: 781a ldrb r2, [r3, #0] 8002ee4: 187b adds r3, r7, r1 8002ee6: 3201 adds r2, #1 8002ee8: 701a strb r2, [r3, #0] 8002eea: 230f movs r3, #15 8002eec: 18fb adds r3, r7, r3 8002eee: 781b ldrb r3, [r3, #0] 8002ef0: 2b07 cmp r3, #7 8002ef2: d9d2 bls.n 8002e9a } if (!ack) 8002ef4: 1dfb adds r3, r7, #7 8002ef6: 781b ldrb r3, [r3, #0] 8002ef8: 2b00 cmp r3, #0 8002efa: d102 bne.n 8002f02 IIC_NAck();//发送nACK 8002efc: f7ff ff3a bl 8002d74 8002f00: e001 b.n 8002f06 else IIC_Ack(); //发送ACK 8002f02: f7ff ff0b bl 8002d1c return receive; 8002f06: 230e movs r3, #14 8002f08: 18fb adds r3, r7, r3 8002f0a: 781b ldrb r3, [r3, #0] } 8002f0c: 0018 movs r0, r3 8002f0e: 46bd mov sp, r7 8002f10: b005 add sp, #20 8002f12: bd90 pop {r4, r7, pc} 8002f14: 48000400 .word 0x48000400 08002f18 : // //return READ_HC595_DCK; //} //send data to 959 void Sand_Byte_to_595_2(uint8_t h) { 8002f18: b580 push {r7, lr} 8002f1a: b084 sub sp, #16 8002f1c: af00 add r7, sp, #0 8002f1e: 0002 movs r2, r0 8002f20: 1dfb adds r3, r7, #7 8002f22: 701a strb r2, [r3, #0] change_io_function(HC595_DLK_GPIO_Port,HC595_DLK_Pin,0); 8002f24: 2390 movs r3, #144 ; 0x90 8002f26: 05db lsls r3, r3, #23 8002f28: 2200 movs r2, #0 8002f2a: 2120 movs r1, #32 8002f2c: 0018 movs r0, r3 8002f2e: f7ff fcb5 bl 800289c HC595_DCK(0); 8002f32: 2390 movs r3, #144 ; 0x90 8002f34: 05db lsls r3, r3, #23 8002f36: 2200 movs r2, #0 8002f38: 2120 movs r1, #32 8002f3a: 0018 movs r0, r3 8002f3c: f7fe fcad bl 800189a HC595_SCK2(0); 8002f40: 2380 movs r3, #128 ; 0x80 8002f42: 0099 lsls r1, r3, #2 8002f44: 2390 movs r3, #144 ; 0x90 8002f46: 05db lsls r3, r3, #23 8002f48: 2200 movs r2, #0 8002f4a: 0018 movs r0, r3 8002f4c: f7fe fca5 bl 800189a HC595_RCK(0); 8002f50: 2390 movs r3, #144 ; 0x90 8002f52: 05db lsls r3, r3, #23 8002f54: 2200 movs r2, #0 8002f56: 2180 movs r1, #128 ; 0x80 8002f58: 0018 movs r0, r3 8002f5a: f7fe fc9e bl 800189a for(char a=0;a<8;a++) 8002f5e: 230f movs r3, #15 8002f60: 18fb adds r3, r7, r3 8002f62: 2200 movs r2, #0 8002f64: 701a strb r2, [r3, #0] 8002f66: e02e b.n 8002fc6 { if((h< { HC595_DCK(1); 8002f7c: 2390 movs r3, #144 ; 0x90 8002f7e: 05db lsls r3, r3, #23 8002f80: 2201 movs r2, #1 8002f82: 2120 movs r1, #32 8002f84: 0018 movs r0, r3 8002f86: f7fe fc88 bl 800189a 8002f8a: e006 b.n 8002f9a }else { HC595_DCK(0); 8002f8c: 2390 movs r3, #144 ; 0x90 8002f8e: 05db lsls r3, r3, #23 8002f90: 2200 movs r2, #0 8002f92: 2120 movs r1, #32 8002f94: 0018 movs r0, r3 8002f96: f7fe fc80 bl 800189a } HC595_SCK2(1); 8002f9a: 2380 movs r3, #128 ; 0x80 8002f9c: 0099 lsls r1, r3, #2 8002f9e: 2390 movs r3, #144 ; 0x90 8002fa0: 05db lsls r3, r3, #23 8002fa2: 2201 movs r2, #1 8002fa4: 0018 movs r0, r3 8002fa6: f7fe fc78 bl 800189a HC595_SCK2(0); 8002faa: 2380 movs r3, #128 ; 0x80 8002fac: 0099 lsls r1, r3, #2 8002fae: 2390 movs r3, #144 ; 0x90 8002fb0: 05db lsls r3, r3, #23 8002fb2: 2200 movs r2, #0 8002fb4: 0018 movs r0, r3 8002fb6: f7fe fc70 bl 800189a for(char a=0;a<8;a++) 8002fba: 210f movs r1, #15 8002fbc: 187b adds r3, r7, r1 8002fbe: 781a ldrb r2, [r3, #0] 8002fc0: 187b adds r3, r7, r1 8002fc2: 3201 adds r2, #1 8002fc4: 701a strb r2, [r3, #0] 8002fc6: 230f movs r3, #15 8002fc8: 18fb adds r3, r7, r3 8002fca: 781b ldrb r3, [r3, #0] 8002fcc: 2b07 cmp r3, #7 8002fce: d9cb bls.n 8002f68 } HC595_RCK(1); 8002fd0: 2390 movs r3, #144 ; 0x90 8002fd2: 05db lsls r3, r3, #23 8002fd4: 2201 movs r2, #1 8002fd6: 2180 movs r1, #128 ; 0x80 8002fd8: 0018 movs r0, r3 8002fda: f7fe fc5e bl 800189a HC595_RCK(0); 8002fde: 2390 movs r3, #144 ; 0x90 8002fe0: 05db lsls r3, r3, #23 8002fe2: 2200 movs r2, #0 8002fe4: 2180 movs r1, #128 ; 0x80 8002fe6: 0018 movs r0, r3 8002fe8: f7fe fc57 bl 800189a } 8002fec: 46c0 nop ; (mov r8, r8) 8002fee: 46bd mov sp, r7 8002ff0: b004 add sp, #16 8002ff2: bd80 pop {r7, pc} 08002ff4 : void hc2_sever() { 8002ff4: b580 push {r7, lr} 8002ff6: b082 sub sp, #8 8002ff8: af00 add r7, sp, #0 char h=0; 8002ffa: 1dfb adds r3, r7, #7 8002ffc: 2200 movs r2, #0 8002ffe: 701a strb r2, [r3, #0] if(dis_buff.led_run==1) 8003000: 4b1d ldr r3, [pc, #116] ; (8003078 ) 8003002: 7b1b ldrb r3, [r3, #12] 8003004: 2b01 cmp r3, #1 8003006: d105 bne.n 8003014 { h|=0x01; 8003008: 1dfb adds r3, r7, #7 800300a: 1dfa adds r2, r7, #7 800300c: 7812 ldrb r2, [r2, #0] 800300e: 2101 movs r1, #1 8003010: 430a orrs r2, r1 8003012: 701a strb r2, [r3, #0] } if(dis_buff.moto1a==1) 8003014: 4b18 ldr r3, [pc, #96] ; (8003078 ) 8003016: 7b5b ldrb r3, [r3, #13] 8003018: 2b01 cmp r3, #1 800301a: d105 bne.n 8003028 { h|=0x02; 800301c: 1dfb adds r3, r7, #7 800301e: 1dfa adds r2, r7, #7 8003020: 7812 ldrb r2, [r2, #0] 8003022: 2102 movs r1, #2 8003024: 430a orrs r2, r1 8003026: 701a strb r2, [r3, #0] } if(dis_buff.moto1b==1) 8003028: 4b13 ldr r3, [pc, #76] ; (8003078 ) 800302a: 7b9b ldrb r3, [r3, #14] 800302c: 2b01 cmp r3, #1 800302e: d105 bne.n 800303c { h|=0x04; 8003030: 1dfb adds r3, r7, #7 8003032: 1dfa adds r2, r7, #7 8003034: 7812 ldrb r2, [r2, #0] 8003036: 2104 movs r1, #4 8003038: 430a orrs r2, r1 800303a: 701a strb r2, [r3, #0] } if(dis_buff.moto2a==1) 800303c: 4b0e ldr r3, [pc, #56] ; (8003078 ) 800303e: 7bdb ldrb r3, [r3, #15] 8003040: 2b01 cmp r3, #1 8003042: d105 bne.n 8003050 { h|=0x08; 8003044: 1dfb adds r3, r7, #7 8003046: 1dfa adds r2, r7, #7 8003048: 7812 ldrb r2, [r2, #0] 800304a: 2108 movs r1, #8 800304c: 430a orrs r2, r1 800304e: 701a strb r2, [r3, #0] } if(dis_buff.moto2b==1) 8003050: 4b09 ldr r3, [pc, #36] ; (8003078 ) 8003052: 7c1b ldrb r3, [r3, #16] 8003054: 2b01 cmp r3, #1 8003056: d105 bne.n 8003064 { h|=0x10; 8003058: 1dfb adds r3, r7, #7 800305a: 1dfa adds r2, r7, #7 800305c: 7812 ldrb r2, [r2, #0] 800305e: 2110 movs r1, #16 8003060: 430a orrs r2, r1 8003062: 701a strb r2, [r3, #0] } Sand_Byte_to_595_2(h); 8003064: 1dfb adds r3, r7, #7 8003066: 781b ldrb r3, [r3, #0] 8003068: 0018 movs r0, r3 800306a: f7ff ff55 bl 8002f18 } 800306e: 46c0 nop ; (mov r8, r8) 8003070: 46bd mov sp, r7 8003072: b002 add sp, #8 8003074: bd80 pop {r7, pc} 8003076: 46c0 nop ; (mov r8, r8) 8003078: 20000038 .word 0x20000038 0800307c : //motor cool start void moto_server() { 800307c: b580 push {r7, lr} 800307e: af00 add r7, sp, #0 if(HAL_GetTick()>moto.moto_run) 8003080: f7fd fcc2 bl 8000a08 8003084: 0002 movs r2, r0 8003086: 4b63 ldr r3, [pc, #396] ; (8003214 ) 8003088: 681b ldr r3, [r3, #0] 800308a: 429a cmp r2, r3 800308c: d800 bhi.n 8003090 800308e: e07e b.n 800318e { moto.moto_run=HAL_GetTick()+10; 8003090: f7fd fcba bl 8000a08 8003094: 0003 movs r3, r0 8003096: 330a adds r3, #10 8003098: 001a movs r2, r3 800309a: 4b5e ldr r3, [pc, #376] ; (8003214 ) 800309c: 601a str r2, [r3, #0] if(moto.moto1a!=moto.moto1a_) 800309e: 4b5d ldr r3, [pc, #372] ; (8003214 ) 80030a0: 7a1a ldrb r2, [r3, #8] 80030a2: 4b5c ldr r3, [pc, #368] ; (8003214 ) 80030a4: 7b1b ldrb r3, [r3, #12] 80030a6: 429a cmp r2, r3 80030a8: d017 beq.n 80030da { if(moto.moto1a>moto.moto1a_) 80030aa: 4b5a ldr r3, [pc, #360] ; (8003214 ) 80030ac: 7a1a ldrb r2, [r3, #8] 80030ae: 4b59 ldr r3, [pc, #356] ; (8003214 ) 80030b0: 7b1b ldrb r3, [r3, #12] 80030b2: 429a cmp r2, r3 80030b4: d905 bls.n 80030c2 { moto.moto1a_++; 80030b6: 4b57 ldr r3, [pc, #348] ; (8003214 ) 80030b8: 7b1b ldrb r3, [r3, #12] 80030ba: 3301 adds r3, #1 80030bc: b2da uxtb r2, r3 80030be: 4b55 ldr r3, [pc, #340] ; (8003214 ) 80030c0: 731a strb r2, [r3, #12] } if(moto.moto1a) 80030c4: 7a1a ldrb r2, [r3, #8] 80030c6: 4b53 ldr r3, [pc, #332] ; (8003214 ) 80030c8: 7b1b ldrb r3, [r3, #12] 80030ca: 429a cmp r2, r3 80030cc: d205 bcs.n 80030da { moto.moto1a_--; 80030ce: 4b51 ldr r3, [pc, #324] ; (8003214 ) 80030d0: 7b1b ldrb r3, [r3, #12] 80030d2: 3b01 subs r3, #1 80030d4: b2da uxtb r2, r3 80030d6: 4b4f ldr r3, [pc, #316] ; (8003214 ) 80030d8: 731a strb r2, [r3, #12] } } if(moto.moto1b!=moto.moto1b_) 80030da: 4b4e ldr r3, [pc, #312] ; (8003214 ) 80030dc: 7a5a ldrb r2, [r3, #9] 80030de: 4b4d ldr r3, [pc, #308] ; (8003214 ) 80030e0: 7b5b ldrb r3, [r3, #13] 80030e2: 429a cmp r2, r3 80030e4: d017 beq.n 8003116 { if(moto.moto1b>moto.moto1b_) 80030e6: 4b4b ldr r3, [pc, #300] ; (8003214 ) 80030e8: 7a5a ldrb r2, [r3, #9] 80030ea: 4b4a ldr r3, [pc, #296] ; (8003214 ) 80030ec: 7b5b ldrb r3, [r3, #13] 80030ee: 429a cmp r2, r3 80030f0: d905 bls.n 80030fe { moto.moto1b_++; 80030f2: 4b48 ldr r3, [pc, #288] ; (8003214 ) 80030f4: 7b5b ldrb r3, [r3, #13] 80030f6: 3301 adds r3, #1 80030f8: b2da uxtb r2, r3 80030fa: 4b46 ldr r3, [pc, #280] ; (8003214 ) 80030fc: 735a strb r2, [r3, #13] } if(moto.moto1b) 8003100: 7a5a ldrb r2, [r3, #9] 8003102: 4b44 ldr r3, [pc, #272] ; (8003214 ) 8003104: 7b5b ldrb r3, [r3, #13] 8003106: 429a cmp r2, r3 8003108: d205 bcs.n 8003116 { moto.moto1b_--; 800310a: 4b42 ldr r3, [pc, #264] ; (8003214 ) 800310c: 7b5b ldrb r3, [r3, #13] 800310e: 3b01 subs r3, #1 8003110: b2da uxtb r2, r3 8003112: 4b40 ldr r3, [pc, #256] ; (8003214 ) 8003114: 735a strb r2, [r3, #13] } } if(moto.moto2a!=moto.moto2a_) 8003116: 4b3f ldr r3, [pc, #252] ; (8003214 ) 8003118: 7a9a ldrb r2, [r3, #10] 800311a: 4b3e ldr r3, [pc, #248] ; (8003214 ) 800311c: 7b9b ldrb r3, [r3, #14] 800311e: 429a cmp r2, r3 8003120: d017 beq.n 8003152 { if(moto.moto2a>moto.moto2a_) 8003122: 4b3c ldr r3, [pc, #240] ; (8003214 ) 8003124: 7a9a ldrb r2, [r3, #10] 8003126: 4b3b ldr r3, [pc, #236] ; (8003214 ) 8003128: 7b9b ldrb r3, [r3, #14] 800312a: 429a cmp r2, r3 800312c: d905 bls.n 800313a { moto.moto2a_++; 800312e: 4b39 ldr r3, [pc, #228] ; (8003214 ) 8003130: 7b9b ldrb r3, [r3, #14] 8003132: 3301 adds r3, #1 8003134: b2da uxtb r2, r3 8003136: 4b37 ldr r3, [pc, #220] ; (8003214 ) 8003138: 739a strb r2, [r3, #14] } if(moto.moto2a) 800313c: 7a9a ldrb r2, [r3, #10] 800313e: 4b35 ldr r3, [pc, #212] ; (8003214 ) 8003140: 7b9b ldrb r3, [r3, #14] 8003142: 429a cmp r2, r3 8003144: d205 bcs.n 8003152 { moto.moto2a_--; 8003146: 4b33 ldr r3, [pc, #204] ; (8003214 ) 8003148: 7b9b ldrb r3, [r3, #14] 800314a: 3b01 subs r3, #1 800314c: b2da uxtb r2, r3 800314e: 4b31 ldr r3, [pc, #196] ; (8003214 ) 8003150: 739a strb r2, [r3, #14] } } if(moto.moto2b!=moto.moto2b_) 8003152: 4b30 ldr r3, [pc, #192] ; (8003214 ) 8003154: 7ada ldrb r2, [r3, #11] 8003156: 4b2f ldr r3, [pc, #188] ; (8003214 ) 8003158: 7bdb ldrb r3, [r3, #15] 800315a: 429a cmp r2, r3 800315c: d017 beq.n 800318e { if(moto.moto2b>moto.moto2b_) 800315e: 4b2d ldr r3, [pc, #180] ; (8003214 ) 8003160: 7ada ldrb r2, [r3, #11] 8003162: 4b2c ldr r3, [pc, #176] ; (8003214 ) 8003164: 7bdb ldrb r3, [r3, #15] 8003166: 429a cmp r2, r3 8003168: d905 bls.n 8003176 { moto.moto2b_++; 800316a: 4b2a ldr r3, [pc, #168] ; (8003214 ) 800316c: 7bdb ldrb r3, [r3, #15] 800316e: 3301 adds r3, #1 8003170: b2da uxtb r2, r3 8003172: 4b28 ldr r3, [pc, #160] ; (8003214 ) 8003174: 73da strb r2, [r3, #15] } if(moto.moto2b) 8003178: 7ada ldrb r2, [r3, #11] 800317a: 4b26 ldr r3, [pc, #152] ; (8003214 ) 800317c: 7bdb ldrb r3, [r3, #15] 800317e: 429a cmp r2, r3 8003180: d205 bcs.n 800318e { moto.moto2b_--; 8003182: 4b24 ldr r3, [pc, #144] ; (8003214 ) 8003184: 7bdb ldrb r3, [r3, #15] 8003186: 3b01 subs r3, #1 8003188: b2da uxtb r2, r3 800318a: 4b22 ldr r3, [pc, #136] ; (8003214 ) 800318c: 73da strb r2, [r3, #15] moto.pwm_run++; 800318e: 4b21 ldr r3, [pc, #132] ; (8003214 ) 8003190: 685b ldr r3, [r3, #4] 8003192: 1c5a adds r2, r3, #1 8003194: 4b1f ldr r3, [pc, #124] ; (8003214 ) 8003196: 605a str r2, [r3, #4] if(moto.pwm_run==10) 8003198: 4b1e ldr r3, [pc, #120] ; (8003214 ) 800319a: 685b ldr r3, [r3, #4] 800319c: 2b0a cmp r3, #10 800319e: d102 bne.n 80031a6 { moto.pwm_run=0; 80031a0: 4b1c ldr r3, [pc, #112] ; (8003214 ) 80031a2: 2200 movs r2, #0 80031a4: 605a str r2, [r3, #4] } if(moto.pwm_run) 80031a8: 685b ldr r3, [r3, #4] 80031aa: 4a1a ldr r2, [pc, #104] ; (8003214 ) 80031ac: 7b12 ldrb r2, [r2, #12] 80031ae: 4293 cmp r3, r2 80031b0: da03 bge.n 80031ba { dis_buff.moto1a=1; 80031b2: 4b19 ldr r3, [pc, #100] ; (8003218 ) 80031b4: 2201 movs r2, #1 80031b6: 735a strb r2, [r3, #13] 80031b8: e002 b.n 80031c0 }else { dis_buff.moto1a=0; 80031ba: 4b17 ldr r3, [pc, #92] ; (8003218 ) 80031bc: 2200 movs r2, #0 80031be: 735a strb r2, [r3, #13] } if(moto.pwm_run) 80031c2: 685b ldr r3, [r3, #4] 80031c4: 4a13 ldr r2, [pc, #76] ; (8003214 ) 80031c6: 7b52 ldrb r2, [r2, #13] 80031c8: 4293 cmp r3, r2 80031ca: da03 bge.n 80031d4 { dis_buff.moto1b=1; 80031cc: 4b12 ldr r3, [pc, #72] ; (8003218 ) 80031ce: 2201 movs r2, #1 80031d0: 739a strb r2, [r3, #14] 80031d2: e002 b.n 80031da }else { dis_buff.moto1b=0; 80031d4: 4b10 ldr r3, [pc, #64] ; (8003218 ) 80031d6: 2200 movs r2, #0 80031d8: 739a strb r2, [r3, #14] } if(moto.pwm_run) 80031dc: 685b ldr r3, [r3, #4] 80031de: 4a0d ldr r2, [pc, #52] ; (8003214 ) 80031e0: 7b92 ldrb r2, [r2, #14] 80031e2: 4293 cmp r3, r2 80031e4: da03 bge.n 80031ee { dis_buff.moto2a=1; 80031e6: 4b0c ldr r3, [pc, #48] ; (8003218 ) 80031e8: 2201 movs r2, #1 80031ea: 73da strb r2, [r3, #15] 80031ec: e002 b.n 80031f4 }else { dis_buff.moto2a=0; 80031ee: 4b0a ldr r3, [pc, #40] ; (8003218 ) 80031f0: 2200 movs r2, #0 80031f2: 73da strb r2, [r3, #15] } if(moto.pwm_run) 80031f6: 685b ldr r3, [r3, #4] 80031f8: 4a06 ldr r2, [pc, #24] ; (8003214 ) 80031fa: 7bd2 ldrb r2, [r2, #15] 80031fc: 4293 cmp r3, r2 80031fe: da03 bge.n 8003208 { dis_buff.moto2b=1; 8003200: 4b05 ldr r3, [pc, #20] ; (8003218 ) 8003202: 2201 movs r2, #1 8003204: 741a strb r2, [r3, #16] }else { dis_buff.moto2b=0; } } 8003206: e002 b.n 800320e dis_buff.moto2b=0; 8003208: 4b03 ldr r3, [pc, #12] ; (8003218 ) 800320a: 2200 movs r2, #0 800320c: 741a strb r2, [r3, #16] } 800320e: 46c0 nop ; (mov r8, r8) 8003210: 46bd mov sp, r7 8003212: bd80 pop {r7, pc} 8003214: 20000134 .word 0x20000134 8003218: 20000038 .word 0x20000038 0800321c : #define E 0x08 #define F 0x04 #define G 0x02 #define H 0x01 void HT1621_Display_GetButton(void) { 800321c: b580 push {r7, lr} 800321e: b084 sub sp, #16 8003220: af00 add r7, sp, #0 unsigned char send_buff[8]; unsigned char lcd_buff[4]; //WritenDataHT1621(0,send_buff,8); lcd_buff[0]=LED_Tab[dis_buff.d_num[0]]; 8003222: 4b45 ldr r3, [pc, #276] ; (8003338 ) 8003224: 781b ldrb r3, [r3, #0] 8003226: 001a movs r2, r3 8003228: 4b44 ldr r3, [pc, #272] ; (800333c ) 800322a: 5c9a ldrb r2, [r3, r2] 800322c: 1d3b adds r3, r7, #4 800322e: 701a strb r2, [r3, #0] if(dis_buff.dot1==1) 8003230: 4b41 ldr r3, [pc, #260] ; (8003338 ) 8003232: 7a1b ldrb r3, [r3, #8] 8003234: 2b01 cmp r3, #1 8003236: d107 bne.n 8003248 { lcd_buff[0]|=0x80; 8003238: 1d3b adds r3, r7, #4 800323a: 781b ldrb r3, [r3, #0] 800323c: 2280 movs r2, #128 ; 0x80 800323e: 4252 negs r2, r2 8003240: 4313 orrs r3, r2 8003242: b2da uxtb r2, r3 8003244: 1d3b adds r3, r7, #4 8003246: 701a strb r2, [r3, #0] } lcd_buff[1]=LED_Tab[dis_buff.d_num[1]]; 8003248: 4b3b ldr r3, [pc, #236] ; (8003338 ) 800324a: 785b ldrb r3, [r3, #1] 800324c: 001a movs r2, r3 800324e: 4b3b ldr r3, [pc, #236] ; (800333c ) 8003250: 5c9a ldrb r2, [r3, r2] 8003252: 1d3b adds r3, r7, #4 8003254: 705a strb r2, [r3, #1] if(dis_buff.dot2==1) 8003256: 4b38 ldr r3, [pc, #224] ; (8003338 ) 8003258: 7a5b ldrb r3, [r3, #9] 800325a: 2b01 cmp r3, #1 800325c: d107 bne.n 800326e { lcd_buff[1]|=0x80; 800325e: 1d3b adds r3, r7, #4 8003260: 785b ldrb r3, [r3, #1] 8003262: 2280 movs r2, #128 ; 0x80 8003264: 4252 negs r2, r2 8003266: 4313 orrs r3, r2 8003268: b2da uxtb r2, r3 800326a: 1d3b adds r3, r7, #4 800326c: 705a strb r2, [r3, #1] } lcd_buff[2]=LED_Tab[dis_buff.d_num[2]]; 800326e: 4b32 ldr r3, [pc, #200] ; (8003338 ) 8003270: 789b ldrb r3, [r3, #2] 8003272: 001a movs r2, r3 8003274: 4b31 ldr r3, [pc, #196] ; (800333c ) 8003276: 5c9a ldrb r2, [r3, r2] 8003278: 1d3b adds r3, r7, #4 800327a: 709a strb r2, [r3, #2] if(dis_buff.dot3==1) 800327c: 4b2e ldr r3, [pc, #184] ; (8003338 ) 800327e: 7a9b ldrb r3, [r3, #10] 8003280: 2b01 cmp r3, #1 8003282: d107 bne.n 8003294 { lcd_buff[2]|=0x80; 8003284: 1d3b adds r3, r7, #4 8003286: 789b ldrb r3, [r3, #2] 8003288: 2280 movs r2, #128 ; 0x80 800328a: 4252 negs r2, r2 800328c: 4313 orrs r3, r2 800328e: b2da uxtb r2, r3 8003290: 1d3b adds r3, r7, #4 8003292: 709a strb r2, [r3, #2] } lcd_buff[3]=LED_Tab[dis_buff.d_num[3]]; 8003294: 4b28 ldr r3, [pc, #160] ; (8003338 ) 8003296: 78db ldrb r3, [r3, #3] 8003298: 001a movs r2, r3 800329a: 4b28 ldr r3, [pc, #160] ; (800333c ) 800329c: 5c9a ldrb r2, [r3, r2] 800329e: 1d3b adds r3, r7, #4 80032a0: 70da strb r2, [r3, #3] if(dis_buff.dot4==1) 80032a2: 4b25 ldr r3, [pc, #148] ; (8003338 ) 80032a4: 7adb ldrb r3, [r3, #11] 80032a6: 2b01 cmp r3, #1 80032a8: d107 bne.n 80032ba { lcd_buff[3]|=0x80; 80032aa: 1d3b adds r3, r7, #4 80032ac: 78db ldrb r3, [r3, #3] 80032ae: 2280 movs r2, #128 ; 0x80 80032b0: 4252 negs r2, r2 80032b2: 4313 orrs r3, r2 80032b4: b2da uxtb r2, r3 80032b6: 1d3b adds r3, r7, #4 80032b8: 70da strb r2, [r3, #3] } send_buff[0]=lcd_buff[0]>>4; 80032ba: 1d3b adds r3, r7, #4 80032bc: 781b ldrb r3, [r3, #0] 80032be: 091b lsrs r3, r3, #4 80032c0: b2da uxtb r2, r3 80032c2: 2108 movs r1, #8 80032c4: 187b adds r3, r7, r1 80032c6: 701a strb r2, [r3, #0] send_buff[1]=lcd_buff[0]&0x0f; 80032c8: 1d3b adds r3, r7, #4 80032ca: 781b ldrb r3, [r3, #0] 80032cc: 220f movs r2, #15 80032ce: 4013 ands r3, r2 80032d0: b2da uxtb r2, r3 80032d2: 187b adds r3, r7, r1 80032d4: 705a strb r2, [r3, #1] send_buff[2]=lcd_buff[1]>>4; 80032d6: 1d3b adds r3, r7, #4 80032d8: 785b ldrb r3, [r3, #1] 80032da: 091b lsrs r3, r3, #4 80032dc: b2da uxtb r2, r3 80032de: 187b adds r3, r7, r1 80032e0: 709a strb r2, [r3, #2] send_buff[3]=lcd_buff[1]&0x0f; 80032e2: 1d3b adds r3, r7, #4 80032e4: 785b ldrb r3, [r3, #1] 80032e6: 220f movs r2, #15 80032e8: 4013 ands r3, r2 80032ea: b2da uxtb r2, r3 80032ec: 187b adds r3, r7, r1 80032ee: 70da strb r2, [r3, #3] send_buff[4]=lcd_buff[2]>>4; 80032f0: 1d3b adds r3, r7, #4 80032f2: 789b ldrb r3, [r3, #2] 80032f4: 091b lsrs r3, r3, #4 80032f6: b2da uxtb r2, r3 80032f8: 187b adds r3, r7, r1 80032fa: 711a strb r2, [r3, #4] send_buff[5]=lcd_buff[2]&0x0f; 80032fc: 1d3b adds r3, r7, #4 80032fe: 789b ldrb r3, [r3, #2] 8003300: 220f movs r2, #15 8003302: 4013 ands r3, r2 8003304: b2da uxtb r2, r3 8003306: 187b adds r3, r7, r1 8003308: 715a strb r2, [r3, #5] send_buff[6]=lcd_buff[3]>>4; 800330a: 1d3b adds r3, r7, #4 800330c: 78db ldrb r3, [r3, #3] 800330e: 091b lsrs r3, r3, #4 8003310: b2da uxtb r2, r3 8003312: 187b adds r3, r7, r1 8003314: 719a strb r2, [r3, #6] send_buff[7]=lcd_buff[3]&0x0f; 8003316: 1d3b adds r3, r7, #4 8003318: 78db ldrb r3, [r3, #3] 800331a: 220f movs r2, #15 800331c: 4013 ands r3, r2 800331e: b2da uxtb r2, r3 8003320: 187b adds r3, r7, r1 8003322: 71da strb r2, [r3, #7] WritenDataHT1621(0,send_buff,8); 8003324: 187b adds r3, r7, r1 8003326: 2208 movs r2, #8 8003328: 0019 movs r1, r3 800332a: 2000 movs r0, #0 800332c: f7ff fb74 bl 8002a18 } 8003330: 46c0 nop ; (mov r8, r8) 8003332: 46bd mov sp, r7 8003334: b004 add sp, #16 8003336: bd80 pop {r7, pc} 8003338: 20000038 .word 0x20000038 800333c: 08003ef0 .word 0x08003ef0 08003340 : char check_need_reset() { 8003340: b580 push {r7, lr} 8003342: b082 sub sp, #8 8003344: af00 add r7, sp, #0 char a=0; 8003346: 1dfb adds r3, r7, #7 8003348: 2200 movs r2, #0 800334a: 701a strb r2, [r3, #0] change_io_function(MOT_IN1_GPIO_Port, MOT_IN1_Pin,1); 800334c: 4b31 ldr r3, [pc, #196] ; (8003414 ) 800334e: 2201 movs r2, #1 8003350: 2101 movs r1, #1 8003352: 0018 movs r0, r3 8003354: f7ff faa2 bl 800289c change_io_function(MOT_IN2_GPIO_Port, MOT_IN2_Pin,0); 8003358: 4b2e ldr r3, [pc, #184] ; (8003414 ) 800335a: 2200 movs r2, #0 800335c: 2102 movs r1, #2 800335e: 0018 movs r0, r3 8003360: f7ff fa9c bl 800289c MOT_IN2(0); 8003364: 4b2b ldr r3, [pc, #172] ; (8003414 ) 8003366: 2200 movs r2, #0 8003368: 2102 movs r1, #2 800336a: 0018 movs r0, r3 800336c: f7fe fa95 bl 800189a if(READ_MOT_IN1==0) 8003370: 4b28 ldr r3, [pc, #160] ; (8003414 ) 8003372: 2101 movs r1, #1 8003374: 0018 movs r0, r3 8003376: f7fe fa73 bl 8001860 800337a: 1e03 subs r3, r0, #0 800337c: d137 bne.n 80033ee { MOT_IN2(1); 800337e: 4b25 ldr r3, [pc, #148] ; (8003414 ) 8003380: 2201 movs r2, #1 8003382: 2102 movs r1, #2 8003384: 0018 movs r0, r3 8003386: f7fe fa88 bl 800189a if(READ_MOT_IN1==1) 800338a: 4b22 ldr r3, [pc, #136] ; (8003414 ) 800338c: 2101 movs r1, #1 800338e: 0018 movs r0, r3 8003390: f7fe fa66 bl 8001860 8003394: 0003 movs r3, r0 8003396: 2b01 cmp r3, #1 8003398: d129 bne.n 80033ee { change_io_function(MOT_IN1_GPIO_Port, MOT_IN1_Pin,0); 800339a: 4b1e ldr r3, [pc, #120] ; (8003414 ) 800339c: 2200 movs r2, #0 800339e: 2101 movs r1, #1 80033a0: 0018 movs r0, r3 80033a2: f7ff fa7b bl 800289c change_io_function(MOT_IN2_GPIO_Port, MOT_IN2_Pin,1); 80033a6: 4b1b ldr r3, [pc, #108] ; (8003414 ) 80033a8: 2201 movs r2, #1 80033aa: 2102 movs r1, #2 80033ac: 0018 movs r0, r3 80033ae: f7ff fa75 bl 800289c MOT_IN1(0); 80033b2: 4b18 ldr r3, [pc, #96] ; (8003414 ) 80033b4: 2200 movs r2, #0 80033b6: 2101 movs r1, #1 80033b8: 0018 movs r0, r3 80033ba: f7fe fa6e bl 800189a if(READ_MOT_IN2==0) 80033be: 4b15 ldr r3, [pc, #84] ; (8003414 ) 80033c0: 2102 movs r1, #2 80033c2: 0018 movs r0, r3 80033c4: f7fe fa4c bl 8001860 80033c8: 1e03 subs r3, r0, #0 80033ca: d110 bne.n 80033ee { MOT_IN1(1); 80033cc: 4b11 ldr r3, [pc, #68] ; (8003414 ) 80033ce: 2201 movs r2, #1 80033d0: 2101 movs r1, #1 80033d2: 0018 movs r0, r3 80033d4: f7fe fa61 bl 800189a if(READ_MOT_IN2==1) 80033d8: 4b0e ldr r3, [pc, #56] ; (8003414 ) 80033da: 2102 movs r1, #2 80033dc: 0018 movs r0, r3 80033de: f7fe fa3f bl 8001860 80033e2: 0003 movs r3, r0 80033e4: 2b01 cmp r3, #1 80033e6: d102 bne.n 80033ee { a=1; 80033e8: 1dfb adds r3, r7, #7 80033ea: 2201 movs r2, #1 80033ec: 701a strb r2, [r3, #0] } } } change_io_function(MOT_IN1_GPIO_Port, MOT_IN1_Pin,1); 80033ee: 4b09 ldr r3, [pc, #36] ; (8003414 ) 80033f0: 2201 movs r2, #1 80033f2: 2101 movs r1, #1 80033f4: 0018 movs r0, r3 80033f6: f7ff fa51 bl 800289c change_io_function(MOT_IN2_GPIO_Port, MOT_IN2_Pin,1); 80033fa: 4b06 ldr r3, [pc, #24] ; (8003414 ) 80033fc: 2201 movs r2, #1 80033fe: 2102 movs r1, #2 8003400: 0018 movs r0, r3 8003402: f7ff fa4b bl 800289c return a; 8003406: 1dfb adds r3, r7, #7 8003408: 781b ldrb r3, [r3, #0] } 800340a: 0018 movs r0, r3 800340c: 46bd mov sp, r7 800340e: b002 add sp, #8 8003410: bd80 pop {r7, pc} 8003412: 46c0 nop ; (mov r8, r8) 8003414: 48001400 .word 0x48001400 08003418 : void my_code() { 8003418: b590 push {r4, r7, lr} 800341a: b089 sub sp, #36 ; 0x24 800341c: af00 add r7, sp, #0 uint32_t runtime=0,move=0; 800341e: 2300 movs r3, #0 8003420: 61fb str r3, [r7, #28] 8003422: 2300 movs r3, #0 8003424: 61bb str r3, [r7, #24] uint8_t mode=1; 8003426: 2317 movs r3, #23 8003428: 18fb adds r3, r7, r3 800342a: 2201 movs r2, #1 800342c: 701a strb r2, [r3, #0] long countdown=1000; 800342e: 23fa movs r3, #250 ; 0xfa 8003430: 009b lsls r3, r3, #2 8003432: 613b str r3, [r7, #16] long countdown_set=15000; 8003434: 4bcb ldr r3, [pc, #812] ; (8003764 ) 8003436: 60fb str r3, [r7, #12] char moto_in1,moto_in2; uint16_t moto_in1_pp=0,moto_in2_pp=0; 8003438: 2308 movs r3, #8 800343a: 18fb adds r3, r7, r3 800343c: 2200 movs r2, #0 800343e: 801a strh r2, [r3, #0] 8003440: 1dbb adds r3, r7, #6 8003442: 2200 movs r2, #0 8003444: 801a strh r2, [r3, #0] HT1621_Init(); 8003446: f7ff fba8 bl 8002b9a r480_init(); 800344a: f000 fc2f bl 8003cac config.begin=0; 800344e: 4bc6 ldr r3, [pc, #792] ; (8003768 ) 8003450: 2200 movs r2, #0 8003452: 709a strb r2, [r3, #2] AT24CXX_Read(32,(char *)&config,sizeof(config_setting)); 8003454: 4bc4 ldr r3, [pc, #784] ; (8003768 ) 8003456: 2208 movs r2, #8 8003458: 0019 movs r1, r3 800345a: 2020 movs r0, #32 800345c: f7ff f9cf bl 80027fe if(config.begin!=0xab||check_need_reset()) 8003460: 4bc1 ldr r3, [pc, #772] ; (8003768 ) 8003462: 789b ldrb r3, [r3, #2] 8003464: 2bab cmp r3, #171 ; 0xab 8003466: d103 bne.n 8003470 8003468: f7ff ff6a bl 8003340 800346c: 1e03 subs r3, r0, #0 800346e: d006 beq.n 800347e { mode=0; 8003470: 2317 movs r3, #23 8003472: 18fb adds r3, r7, r3 8003474: 2200 movs r2, #0 8003476: 701a strb r2, [r3, #0] r480.key=0; 8003478: 4bbc ldr r3, [pc, #752] ; (800376c ) 800347a: 2200 movs r2, #0 800347c: 709a strb r2, [r3, #2] while(1) { //get ADC for(char a=0;a<2;a++) 800347e: 1d7b adds r3, r7, #5 8003480: 2200 movs r2, #0 8003482: 701a strb r2, [r3, #0] 8003484: e025 b.n 80034d2 { HAL_ADC_Start(&hadc); 8003486: 4bba ldr r3, [pc, #744] ; (8003770 ) 8003488: 0018 movs r0, r3 800348a: f7fd fc2b bl 8000ce4 while(HAL_ADC_PollForConversion(&hadc,0xffff)!=HAL_OK); 800348e: 46c0 nop ; (mov r8, r8) 8003490: 4ab8 ldr r2, [pc, #736] ; (8003774 ) 8003492: 4bb7 ldr r3, [pc, #732] ; (8003770 ) 8003494: 0011 movs r1, r2 8003496: 0018 movs r0, r3 8003498: f7fd fcb8 bl 8000e0c 800349c: 1e03 subs r3, r0, #0 800349e: d1f7 bne.n 8003490 ADCC.adc_filtering[a]+=HAL_ADC_GetValue(&hadc); 80034a0: 4bb3 ldr r3, [pc, #716] ; (8003770 ) 80034a2: 0018 movs r0, r3 80034a4: f7fd fd4a bl 8000f3c 80034a8: 0001 movs r1, r0 80034aa: 1d7b adds r3, r7, #5 80034ac: 781b ldrb r3, [r3, #0] 80034ae: 4ab2 ldr r2, [pc, #712] ; (8003778 ) 80034b0: 009b lsls r3, r3, #2 80034b2: 18d3 adds r3, r2, r3 80034b4: 3304 adds r3, #4 80034b6: 681a ldr r2, [r3, #0] 80034b8: 1d7b adds r3, r7, #5 80034ba: 781b ldrb r3, [r3, #0] 80034bc: 188a adds r2, r1, r2 80034be: 49ae ldr r1, [pc, #696] ; (8003778 ) 80034c0: 009b lsls r3, r3, #2 80034c2: 18cb adds r3, r1, r3 80034c4: 3304 adds r3, #4 80034c6: 601a str r2, [r3, #0] for(char a=0;a<2;a++) 80034c8: 1d7b adds r3, r7, #5 80034ca: 781a ldrb r2, [r3, #0] 80034cc: 1d7b adds r3, r7, #5 80034ce: 3201 adds r2, #1 80034d0: 701a strb r2, [r3, #0] 80034d2: 1d7b adds r3, r7, #5 80034d4: 781b ldrb r3, [r3, #0] 80034d6: 2b01 cmp r3, #1 80034d8: d9d5 bls.n 8003486 } HAL_ADC_Stop(&hadc); 80034da: 4ba5 ldr r3, [pc, #660] ; (8003770 ) 80034dc: 0018 movs r0, r3 80034de: f7fd fc55 bl 8000d8c ADCC.filtering_times+=1; 80034e2: 4ba5 ldr r3, [pc, #660] ; (8003778 ) 80034e4: 681b ldr r3, [r3, #0] 80034e6: 1c5a adds r2, r3, #1 80034e8: 4ba3 ldr r3, [pc, #652] ; (8003778 ) 80034ea: 601a str r2, [r3, #0] if(ADCC.filtering_times==set_filtering_times) 80034ec: 4ba2 ldr r3, [pc, #648] ; (8003778 ) 80034ee: 681b ldr r3, [r3, #0] 80034f0: 2b32 cmp r3, #50 ; 0x32 80034f2: d11c bne.n 800352e { ADCC.filtering_times=0; 80034f4: 4ba0 ldr r3, [pc, #640] ; (8003778 ) 80034f6: 2200 movs r2, #0 80034f8: 601a str r2, [r3, #0] ADCC.adc_value[0]=ADCC.adc_filtering[0]/set_filtering_times; 80034fa: 4b9f ldr r3, [pc, #636] ; (8003778 ) 80034fc: 685b ldr r3, [r3, #4] 80034fe: 2132 movs r1, #50 ; 0x32 8003500: 0018 movs r0, r3 8003502: f7fc fe01 bl 8000108 <__udivsi3> 8003506: 0003 movs r3, r0 8003508: 001a movs r2, r3 800350a: 4b9b ldr r3, [pc, #620] ; (8003778 ) 800350c: 60da str r2, [r3, #12] ADCC.adc_filtering[0]=0; 800350e: 4b9a ldr r3, [pc, #616] ; (8003778 ) 8003510: 2200 movs r2, #0 8003512: 605a str r2, [r3, #4] ADCC.adc_value[1]=ADCC.adc_filtering[1]/set_filtering_times; 8003514: 4b98 ldr r3, [pc, #608] ; (8003778 ) 8003516: 689b ldr r3, [r3, #8] 8003518: 2132 movs r1, #50 ; 0x32 800351a: 0018 movs r0, r3 800351c: f7fc fdf4 bl 8000108 <__udivsi3> 8003520: 0003 movs r3, r0 8003522: 001a movs r2, r3 8003524: 4b94 ldr r3, [pc, #592] ; (8003778 ) 8003526: 611a str r2, [r3, #16] ADCC.adc_filtering[1]=0; 8003528: 4b93 ldr r3, [pc, #588] ; (8003778 ) 800352a: 2200 movs r2, #0 800352c: 609a str r2, [r3, #8] } switch(mode) 800352e: 2317 movs r3, #23 8003530: 18fb adds r3, r7, r3 8003532: 781b ldrb r3, [r3, #0] 8003534: 2b04 cmp r3, #4 8003536: d900 bls.n 800353a 8003538: e2fe b.n 8003b38 800353a: 009a lsls r2, r3, #2 800353c: 4b8f ldr r3, [pc, #572] ; (800377c ) 800353e: 18d3 adds r3, r2, r3 8003540: 681b ldr r3, [r3, #0] 8003542: 469f mov pc, r3 { case 0: //Startup if(HAL_GetTick()>runtime) 8003544: f7fd fa60 bl 8000a08 8003548: 0002 movs r2, r0 800354a: 69fb ldr r3, [r7, #28] 800354c: 4293 cmp r3, r2 800354e: d21c bcs.n 800358a { runtime+=1000; 8003550: 69fb ldr r3, [r7, #28] 8003552: 22fa movs r2, #250 ; 0xfa 8003554: 0092 lsls r2, r2, #2 8003556: 4694 mov ip, r2 8003558: 4463 add r3, ip 800355a: 61fb str r3, [r7, #28] if(dis_buff.led_run==1) 800355c: 4b88 ldr r3, [pc, #544] ; (8003780 ) 800355e: 7b1b ldrb r3, [r3, #12] 8003560: 2b01 cmp r3, #1 8003562: d109 bne.n 8003578 { dis_buff.led_run=0; 8003564: 4b86 ldr r3, [pc, #536] ; (8003780 ) 8003566: 2200 movs r2, #0 8003568: 731a strb r2, [r3, #12] dis_buff.dot4=1; 800356a: 4b85 ldr r3, [pc, #532] ; (8003780 ) 800356c: 2201 movs r2, #1 800356e: 72da strb r2, [r3, #11] dis_buff.d_num[0]=16; 8003570: 4b83 ldr r3, [pc, #524] ; (8003780 ) 8003572: 2210 movs r2, #16 8003574: 701a strb r2, [r3, #0] 8003576: e008 b.n 800358a }else { dis_buff.led_run=1; 8003578: 4b81 ldr r3, [pc, #516] ; (8003780 ) 800357a: 2201 movs r2, #1 800357c: 731a strb r2, [r3, #12] dis_buff.dot4=0; 800357e: 4b80 ldr r3, [pc, #512] ; (8003780 ) 8003580: 2200 movs r2, #0 8003582: 72da strb r2, [r3, #11] dis_buff.d_num[0]=10; 8003584: 4b7e ldr r3, [pc, #504] ; (8003780 ) 8003586: 220a movs r2, #10 8003588: 701a strb r2, [r3, #0] } } if(r480.key==0xd7) 800358a: 4b78 ldr r3, [pc, #480] ; (800376c ) 800358c: 789b ldrb r3, [r3, #2] 800358e: 2bd7 cmp r3, #215 ; 0xd7 8003590: d000 beq.n 8003594 8003592: e2ca b.n 8003b2a { config.begin=0xab; 8003594: 4b74 ldr r3, [pc, #464] ; (8003768 ) 8003596: 22ab movs r2, #171 ; 0xab 8003598: 709a strb r2, [r3, #2] config.key_code[0]=r480.add[0]; 800359a: 4b74 ldr r3, [pc, #464] ; (800376c ) 800359c: 781a ldrb r2, [r3, #0] 800359e: 4b72 ldr r3, [pc, #456] ; (8003768 ) 80035a0: 701a strb r2, [r3, #0] config.key_code[1]=r480.add[1]; 80035a2: 4b72 ldr r3, [pc, #456] ; (800376c ) 80035a4: 785a ldrb r2, [r3, #1] 80035a6: 4b70 ldr r3, [pc, #448] ; (8003768 ) 80035a8: 705a strb r2, [r3, #1] r480.key=0; 80035aa: 4b70 ldr r3, [pc, #448] ; (800376c ) 80035ac: 2200 movs r2, #0 80035ae: 709a strb r2, [r3, #2] r480.add[0]=0; 80035b0: 4b6e ldr r3, [pc, #440] ; (800376c ) 80035b2: 2200 movs r2, #0 80035b4: 701a strb r2, [r3, #0] r480.add[1]=0; 80035b6: 4b6d ldr r3, [pc, #436] ; (800376c ) 80035b8: 2200 movs r2, #0 80035ba: 705a strb r2, [r3, #1] mode=1; 80035bc: 2317 movs r3, #23 80035be: 18fb adds r3, r7, r3 80035c0: 2201 movs r2, #1 80035c2: 701a strb r2, [r3, #0] AT24CXX_Write(32,(char *)&config,sizeof(config_setting)); 80035c4: 4b68 ldr r3, [pc, #416] ; (8003768 ) 80035c6: 2208 movs r2, #8 80035c8: 0019 movs r1, r3 80035ca: 2020 movs r0, #32 80035cc: f7ff f93e bl 800284c } break; 80035d0: e2ab b.n 8003b2a case 1: //standby moto.moto1a=0; 80035d2: 4b6c ldr r3, [pc, #432] ; (8003784 ) 80035d4: 2200 movs r2, #0 80035d6: 721a strb r2, [r3, #8] moto.moto1b=0; 80035d8: 4b6a ldr r3, [pc, #424] ; (8003784 ) 80035da: 2200 movs r2, #0 80035dc: 725a strb r2, [r3, #9] moto.moto2a=0; 80035de: 4b69 ldr r3, [pc, #420] ; (8003784 ) 80035e0: 2200 movs r2, #0 80035e2: 729a strb r2, [r3, #10] moto.moto2b=0; 80035e4: 4b67 ldr r3, [pc, #412] ; (8003784 ) 80035e6: 2200 movs r2, #0 80035e8: 72da strb r2, [r3, #11] dis_buff.d_num[0]=16; 80035ea: 4b65 ldr r3, [pc, #404] ; (8003780 ) 80035ec: 2210 movs r2, #16 80035ee: 701a strb r2, [r3, #0] dis_buff.d_num[1]=16; 80035f0: 4b63 ldr r3, [pc, #396] ; (8003780 ) 80035f2: 2210 movs r2, #16 80035f4: 705a strb r2, [r3, #1] dis_buff.d_num[2]=16; 80035f6: 4b62 ldr r3, [pc, #392] ; (8003780 ) 80035f8: 2210 movs r2, #16 80035fa: 709a strb r2, [r3, #2] dis_buff.d_num[3]=16; 80035fc: 4b60 ldr r3, [pc, #384] ; (8003780 ) 80035fe: 2210 movs r2, #16 8003600: 70da strb r2, [r3, #3] dis_buff.dot1=0; 8003602: 4b5f ldr r3, [pc, #380] ; (8003780 ) 8003604: 2200 movs r2, #0 8003606: 721a strb r2, [r3, #8] dis_buff.dot2=0; 8003608: 4b5d ldr r3, [pc, #372] ; (8003780 ) 800360a: 2200 movs r2, #0 800360c: 725a strb r2, [r3, #9] dis_buff.dot3=0; 800360e: 4b5c ldr r3, [pc, #368] ; (8003780 ) 8003610: 2200 movs r2, #0 8003612: 729a strb r2, [r3, #10] if(HAL_GetTick()>runtime) 8003614: f7fd f9f8 bl 8000a08 8003618: 0002 movs r2, r0 800361a: 69fb ldr r3, [r7, #28] 800361c: 4293 cmp r3, r2 800361e: d216 bcs.n 800364e { runtime+=1000; 8003620: 69fb ldr r3, [r7, #28] 8003622: 22fa movs r2, #250 ; 0xfa 8003624: 0092 lsls r2, r2, #2 8003626: 4694 mov ip, r2 8003628: 4463 add r3, ip 800362a: 61fb str r3, [r7, #28] if(dis_buff.led_run==1) 800362c: 4b54 ldr r3, [pc, #336] ; (8003780 ) 800362e: 7b1b ldrb r3, [r3, #12] 8003630: 2b01 cmp r3, #1 8003632: d106 bne.n 8003642 { dis_buff.led_run=0; 8003634: 4b52 ldr r3, [pc, #328] ; (8003780 ) 8003636: 2200 movs r2, #0 8003638: 731a strb r2, [r3, #12] dis_buff.dot4=1; 800363a: 4b51 ldr r3, [pc, #324] ; (8003780 ) 800363c: 2201 movs r2, #1 800363e: 72da strb r2, [r3, #11] 8003640: e005 b.n 800364e }else { dis_buff.led_run=1; 8003642: 4b4f ldr r3, [pc, #316] ; (8003780 ) 8003644: 2201 movs r2, #1 8003646: 731a strb r2, [r3, #12] dis_buff.dot4=0; 8003648: 4b4d ldr r3, [pc, #308] ; (8003780 ) 800364a: 2200 movs r2, #0 800364c: 72da strb r2, [r3, #11] } } if(key2.code!=0) 800364e: 4b4e ldr r3, [pc, #312] ; (8003788 ) 8003650: 681b ldr r3, [r3, #0] 8003652: 2b00 cmp r3, #0 8003654: d011 beq.n 800367a { mode=2; 8003656: 2317 movs r3, #23 8003658: 18fb adds r3, r7, r3 800365a: 2202 movs r2, #2 800365c: 701a strb r2, [r3, #0] countdown=countdown_set; 800365e: 68fb ldr r3, [r7, #12] 8003660: 613b str r3, [r7, #16] moto.moto1a=10; 8003662: 4b48 ldr r3, [pc, #288] ; (8003784 ) 8003664: 220a movs r2, #10 8003666: 721a strb r2, [r3, #8] moto.moto1b=0; 8003668: 4b46 ldr r3, [pc, #280] ; (8003784 ) 800366a: 2200 movs r2, #0 800366c: 725a strb r2, [r3, #9] moto.moto2a=10; 800366e: 4b45 ldr r3, [pc, #276] ; (8003784 ) 8003670: 220a movs r2, #10 8003672: 729a strb r2, [r3, #10] moto.moto2b=0; 8003674: 4b43 ldr r3, [pc, #268] ; (8003784 ) 8003676: 2200 movs r2, #0 8003678: 72da strb r2, [r3, #11] } if(key3.code!=0) 800367a: 4b44 ldr r3, [pc, #272] ; (800378c ) 800367c: 681b ldr r3, [r3, #0] 800367e: 2b00 cmp r3, #0 8003680: d011 beq.n 80036a6 { moto.moto1a=0; 8003682: 4b40 ldr r3, [pc, #256] ; (8003784 ) 8003684: 2200 movs r2, #0 8003686: 721a strb r2, [r3, #8] moto.moto1b=10; 8003688: 4b3e ldr r3, [pc, #248] ; (8003784 ) 800368a: 220a movs r2, #10 800368c: 725a strb r2, [r3, #9] moto.moto2a=0; 800368e: 4b3d ldr r3, [pc, #244] ; (8003784 ) 8003690: 2200 movs r2, #0 8003692: 729a strb r2, [r3, #10] moto.moto2b=10; 8003694: 4b3b ldr r3, [pc, #236] ; (8003784 ) 8003696: 220a movs r2, #10 8003698: 72da strb r2, [r3, #11] mode=3; 800369a: 2317 movs r3, #23 800369c: 18fb adds r3, r7, r3 800369e: 2203 movs r2, #3 80036a0: 701a strb r2, [r3, #0] countdown=countdown_set; 80036a2: 68fb ldr r3, [r7, #12] 80036a4: 613b str r3, [r7, #16] } if(key1.code!=0) 80036a6: 4b3a ldr r3, [pc, #232] ; (8003790 ) 80036a8: 681b ldr r3, [r3, #0] 80036aa: 2b00 cmp r3, #0 80036ac: d100 bne.n 80036b0 80036ae: e23e b.n 8003b2e { mode=4; 80036b0: 2317 movs r3, #23 80036b2: 18fb adds r3, r7, r3 80036b4: 2204 movs r2, #4 80036b6: 701a strb r2, [r3, #0] countdown=10000; 80036b8: 4b36 ldr r3, [pc, #216] ; (8003794 ) 80036ba: 613b str r3, [r7, #16] } break; 80036bc: e237 b.n 8003b2e case 2: if(HAL_GetTick()>move) 80036be: f7fd f9a3 bl 8000a08 80036c2: 0002 movs r2, r0 80036c4: 69bb ldr r3, [r7, #24] 80036c6: 4293 cmp r3, r2 80036c8: d219 bcs.n 80036fe { move=HAL_GetTick()+100; 80036ca: f7fd f99d bl 8000a08 80036ce: 0003 movs r3, r0 80036d0: 3364 adds r3, #100 ; 0x64 80036d2: 61bb str r3, [r7, #24] if(dis_buff.led_run==1) 80036d4: 4b2a ldr r3, [pc, #168] ; (8003780 ) 80036d6: 7b1b ldrb r3, [r3, #12] 80036d8: 2b01 cmp r3, #1 80036da: d103 bne.n 80036e4 { dis_buff.led_run=0; 80036dc: 4b28 ldr r3, [pc, #160] ; (8003780 ) 80036de: 2200 movs r2, #0 80036e0: 731a strb r2, [r3, #12] 80036e2: e002 b.n 80036ea }else { dis_buff.led_run=1; 80036e4: 4b26 ldr r3, [pc, #152] ; (8003780 ) 80036e6: 2201 movs r2, #1 80036e8: 731a strb r2, [r3, #12] } countdown-=100; 80036ea: 693b ldr r3, [r7, #16] 80036ec: 3b64 subs r3, #100 ; 0x64 80036ee: 613b str r3, [r7, #16] if(countdown<0) 80036f0: 693b ldr r3, [r7, #16] 80036f2: 2b00 cmp r3, #0 80036f4: da03 bge.n 80036fe { mode=1; 80036f6: 2317 movs r3, #23 80036f8: 18fb adds r3, r7, r3 80036fa: 2201 movs r2, #1 80036fc: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 80036fe: 693b ldr r3, [r7, #16] 8003700: 2164 movs r1, #100 ; 0x64 8003702: 0018 movs r0, r3 8003704: f7fc fd8a bl 800021c <__divsi3> 8003708: 0003 movs r3, r0 800370a: 210a movs r1, #10 800370c: 0018 movs r0, r3 800370e: f7fc fe6b bl 80003e8 <__aeabi_idivmod> 8003712: 000b movs r3, r1 8003714: b2da uxtb r2, r3 8003716: 4b1a ldr r3, [pc, #104] ; (8003780 ) 8003718: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 800371a: 693b ldr r3, [r7, #16] 800371c: 22fa movs r2, #250 ; 0xfa 800371e: 0091 lsls r1, r2, #2 8003720: 0018 movs r0, r3 8003722: f7fc fd7b bl 800021c <__divsi3> 8003726: 0003 movs r3, r0 8003728: 210a movs r1, #10 800372a: 0018 movs r0, r3 800372c: f7fc fe5c bl 80003e8 <__aeabi_idivmod> 8003730: 000b movs r3, r1 8003732: b2da uxtb r2, r3 8003734: 4b12 ldr r3, [pc, #72] ; (8003780 ) 8003736: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 8003738: 693b ldr r3, [r7, #16] 800373a: 4916 ldr r1, [pc, #88] ; (8003794 ) 800373c: 0018 movs r0, r3 800373e: f7fc fd6d bl 800021c <__divsi3> 8003742: 0003 movs r3, r0 8003744: 210a movs r1, #10 8003746: 0018 movs r0, r3 8003748: f7fc fe4e bl 80003e8 <__aeabi_idivmod> 800374c: 000b movs r3, r1 800374e: b2da uxtb r2, r3 8003750: 4b0b ldr r3, [pc, #44] ; (8003780 ) 8003752: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 8003754: 4b0a ldr r3, [pc, #40] ; (8003780 ) 8003756: 785b ldrb r3, [r3, #1] 8003758: 2b00 cmp r3, #0 800375a: d01d beq.n 8003798 800375c: 4b08 ldr r3, [pc, #32] ; (8003780 ) 800375e: 785a ldrb r2, [r3, #1] 8003760: e01b b.n 800379a 8003762: 46c0 nop ; (mov r8, r8) 8003764: 00003a98 .word 0x00003a98 8003768: 20000144 .word 0x20000144 800376c: 200000e8 .word 0x200000e8 8003770: 20000094 .word 0x20000094 8003774: 0000ffff .word 0x0000ffff 8003778: 20000110 .word 0x20000110 800377c: 08003f04 .word 0x08003f04 8003780: 20000038 .word 0x20000038 8003784: 20000134 .word 0x20000134 8003788: 20000124 .word 0x20000124 800378c: 20000100 .word 0x20000100 8003790: 200000f0 .word 0x200000f0 8003794: 00002710 .word 0x00002710 8003798: 2210 movs r2, #16 800379a: 4b9c ldr r3, [pc, #624] ; (8003a0c ) 800379c: 705a strb r2, [r3, #1] dis_buff.dot4=1; 800379e: 4b9b ldr r3, [pc, #620] ; (8003a0c ) 80037a0: 2201 movs r2, #1 80037a2: 72da strb r2, [r3, #11] if(key3.code!=0) 80037a4: 4b9a ldr r3, [pc, #616] ; (8003a10 ) 80037a6: 681b ldr r3, [r3, #0] 80037a8: 2b00 cmp r3, #0 80037aa: d013 beq.n 80037d4 { mode=3; 80037ac: 2317 movs r3, #23 80037ae: 18fb adds r3, r7, r3 80037b0: 2203 movs r2, #3 80037b2: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 80037b4: 68fa ldr r2, [r7, #12] 80037b6: 693b ldr r3, [r7, #16] 80037b8: 1ad3 subs r3, r2, r3 80037ba: 613b str r3, [r7, #16] moto.moto1a=0; 80037bc: 4b95 ldr r3, [pc, #596] ; (8003a14 ) 80037be: 2200 movs r2, #0 80037c0: 721a strb r2, [r3, #8] moto.moto1b=10; 80037c2: 4b94 ldr r3, [pc, #592] ; (8003a14 ) 80037c4: 220a movs r2, #10 80037c6: 725a strb r2, [r3, #9] moto.moto2a=0; 80037c8: 4b92 ldr r3, [pc, #584] ; (8003a14 ) 80037ca: 2200 movs r2, #0 80037cc: 729a strb r2, [r3, #10] moto.moto2b=10; 80037ce: 4b91 ldr r3, [pc, #580] ; (8003a14 ) 80037d0: 220a movs r2, #10 80037d2: 72da strb r2, [r3, #11] } if(key4.code!=0||(moto.moto1a==0&&moto.moto1b==0&&moto.moto2a==0&&moto.moto2b==0)) 80037d4: 4b90 ldr r3, [pc, #576] ; (8003a18 ) 80037d6: 681b ldr r3, [r3, #0] 80037d8: 2b00 cmp r3, #0 80037da: d10f bne.n 80037fc 80037dc: 4b8d ldr r3, [pc, #564] ; (8003a14 ) 80037de: 7a1b ldrb r3, [r3, #8] 80037e0: 2b00 cmp r3, #0 80037e2: d10f bne.n 8003804 80037e4: 4b8b ldr r3, [pc, #556] ; (8003a14 ) 80037e6: 7a5b ldrb r3, [r3, #9] 80037e8: 2b00 cmp r3, #0 80037ea: d10b bne.n 8003804 80037ec: 4b89 ldr r3, [pc, #548] ; (8003a14 ) 80037ee: 7a9b ldrb r3, [r3, #10] 80037f0: 2b00 cmp r3, #0 80037f2: d107 bne.n 8003804 80037f4: 4b87 ldr r3, [pc, #540] ; (8003a14 ) 80037f6: 7adb ldrb r3, [r3, #11] 80037f8: 2b00 cmp r3, #0 80037fa: d103 bne.n 8003804 { mode=1; 80037fc: 2317 movs r3, #23 80037fe: 18fb adds r3, r7, r3 8003800: 2201 movs r2, #1 8003802: 701a strb r2, [r3, #0] } if(ADCC.adc_value[1]>400||(moto_in1==1&&READ_MOT_IN1==0)) 8003804: 4b85 ldr r3, [pc, #532] ; (8003a1c ) 8003806: 691a ldr r2, [r3, #16] 8003808: 23c8 movs r3, #200 ; 0xc8 800380a: 005b lsls r3, r3, #1 800380c: 429a cmp r2, r3 800380e: dc0b bgt.n 8003828 8003810: 230b movs r3, #11 8003812: 18fb adds r3, r7, r3 8003814: 781b ldrb r3, [r3, #0] 8003816: 2b01 cmp r3, #1 8003818: d10c bne.n 8003834 800381a: 4b81 ldr r3, [pc, #516] ; (8003a20 ) 800381c: 2101 movs r1, #1 800381e: 0018 movs r0, r3 8003820: f7fe f81e bl 8001860 8003824: 1e03 subs r3, r0, #0 8003826: d105 bne.n 8003834 { //overload_times=0; moto.moto1a=0; 8003828: 4b7a ldr r3, [pc, #488] ; (8003a14 ) 800382a: 2200 movs r2, #0 800382c: 721a strb r2, [r3, #8] moto.moto1b=0; 800382e: 4b79 ldr r3, [pc, #484] ; (8003a14 ) 8003830: 2200 movs r2, #0 8003832: 725a strb r2, [r3, #9] } if(ADCC.adc_value[0]>400||(moto_in2==1&&READ_MOT_IN2==0)) 8003834: 4b79 ldr r3, [pc, #484] ; (8003a1c ) 8003836: 68da ldr r2, [r3, #12] 8003838: 23c8 movs r3, #200 ; 0xc8 800383a: 005b lsls r3, r3, #1 800383c: 429a cmp r2, r3 800383e: dc0d bgt.n 800385c 8003840: 230a movs r3, #10 8003842: 18fb adds r3, r7, r3 8003844: 781b ldrb r3, [r3, #0] 8003846: 2b01 cmp r3, #1 8003848: d000 beq.n 800384c 800384a: e172 b.n 8003b32 800384c: 4b74 ldr r3, [pc, #464] ; (8003a20 ) 800384e: 2102 movs r1, #2 8003850: 0018 movs r0, r3 8003852: f7fe f805 bl 8001860 8003856: 1e03 subs r3, r0, #0 8003858: d000 beq.n 800385c 800385a: e16a b.n 8003b32 { moto.moto2a=0; 800385c: 4b6d ldr r3, [pc, #436] ; (8003a14 ) 800385e: 2200 movs r2, #0 8003860: 729a strb r2, [r3, #10] moto.moto2b=0; 8003862: 4b6c ldr r3, [pc, #432] ; (8003a14 ) 8003864: 2200 movs r2, #0 8003866: 72da strb r2, [r3, #11] } break; 8003868: e163 b.n 8003b32 case 3: if(HAL_GetTick()>move) 800386a: f7fd f8cd bl 8000a08 800386e: 0002 movs r2, r0 8003870: 69bb ldr r3, [r7, #24] 8003872: 4293 cmp r3, r2 8003874: d219 bcs.n 80038aa { move=HAL_GetTick()+100; 8003876: f7fd f8c7 bl 8000a08 800387a: 0003 movs r3, r0 800387c: 3364 adds r3, #100 ; 0x64 800387e: 61bb str r3, [r7, #24] if(dis_buff.led_run==1) 8003880: 4b62 ldr r3, [pc, #392] ; (8003a0c ) 8003882: 7b1b ldrb r3, [r3, #12] 8003884: 2b01 cmp r3, #1 8003886: d103 bne.n 8003890 { dis_buff.led_run=0; 8003888: 4b60 ldr r3, [pc, #384] ; (8003a0c ) 800388a: 2200 movs r2, #0 800388c: 731a strb r2, [r3, #12] 800388e: e002 b.n 8003896 }else { dis_buff.led_run=1; 8003890: 4b5e ldr r3, [pc, #376] ; (8003a0c ) 8003892: 2201 movs r2, #1 8003894: 731a strb r2, [r3, #12] } countdown-=100; 8003896: 693b ldr r3, [r7, #16] 8003898: 3b64 subs r3, #100 ; 0x64 800389a: 613b str r3, [r7, #16] if(countdown<0) 800389c: 693b ldr r3, [r7, #16] 800389e: 2b00 cmp r3, #0 80038a0: da03 bge.n 80038aa { mode=1; 80038a2: 2317 movs r3, #23 80038a4: 18fb adds r3, r7, r3 80038a6: 2201 movs r2, #1 80038a8: 701a strb r2, [r3, #0] } } dis_buff.d_num[3]=(countdown/100)%10; 80038aa: 693b ldr r3, [r7, #16] 80038ac: 2164 movs r1, #100 ; 0x64 80038ae: 0018 movs r0, r3 80038b0: f7fc fcb4 bl 800021c <__divsi3> 80038b4: 0003 movs r3, r0 80038b6: 210a movs r1, #10 80038b8: 0018 movs r0, r3 80038ba: f7fc fd95 bl 80003e8 <__aeabi_idivmod> 80038be: 000b movs r3, r1 80038c0: b2da uxtb r2, r3 80038c2: 4b52 ldr r3, [pc, #328] ; (8003a0c ) 80038c4: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown/1000)%10; 80038c6: 693b ldr r3, [r7, #16] 80038c8: 22fa movs r2, #250 ; 0xfa 80038ca: 0091 lsls r1, r2, #2 80038cc: 0018 movs r0, r3 80038ce: f7fc fca5 bl 800021c <__divsi3> 80038d2: 0003 movs r3, r0 80038d4: 210a movs r1, #10 80038d6: 0018 movs r0, r3 80038d8: f7fc fd86 bl 80003e8 <__aeabi_idivmod> 80038dc: 000b movs r3, r1 80038de: b2da uxtb r2, r3 80038e0: 4b4a ldr r3, [pc, #296] ; (8003a0c ) 80038e2: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown/10000)%10); 80038e4: 693b ldr r3, [r7, #16] 80038e6: 494f ldr r1, [pc, #316] ; (8003a24 ) 80038e8: 0018 movs r0, r3 80038ea: f7fc fc97 bl 800021c <__divsi3> 80038ee: 0003 movs r3, r0 80038f0: 210a movs r1, #10 80038f2: 0018 movs r0, r3 80038f4: f7fc fd78 bl 80003e8 <__aeabi_idivmod> 80038f8: 000b movs r3, r1 80038fa: b2da uxtb r2, r3 80038fc: 4b43 ldr r3, [pc, #268] ; (8003a0c ) 80038fe: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 8003900: 4b42 ldr r3, [pc, #264] ; (8003a0c ) 8003902: 785b ldrb r3, [r3, #1] 8003904: 2b00 cmp r3, #0 8003906: d002 beq.n 800390e 8003908: 4b40 ldr r3, [pc, #256] ; (8003a0c ) 800390a: 785a ldrb r2, [r3, #1] 800390c: e000 b.n 8003910 800390e: 2210 movs r2, #16 8003910: 4b3e ldr r3, [pc, #248] ; (8003a0c ) 8003912: 705a strb r2, [r3, #1] dis_buff.dot4=1; 8003914: 4b3d ldr r3, [pc, #244] ; (8003a0c ) 8003916: 2201 movs r2, #1 8003918: 72da strb r2, [r3, #11] if(key2.code!=0) 800391a: 4b43 ldr r3, [pc, #268] ; (8003a28 ) 800391c: 681b ldr r3, [r3, #0] 800391e: 2b00 cmp r3, #0 8003920: d013 beq.n 800394a { mode=2; 8003922: 2317 movs r3, #23 8003924: 18fb adds r3, r7, r3 8003926: 2202 movs r2, #2 8003928: 701a strb r2, [r3, #0] countdown=countdown_set-countdown; 800392a: 68fa ldr r2, [r7, #12] 800392c: 693b ldr r3, [r7, #16] 800392e: 1ad3 subs r3, r2, r3 8003930: 613b str r3, [r7, #16] moto.moto1a=10; 8003932: 4b38 ldr r3, [pc, #224] ; (8003a14 ) 8003934: 220a movs r2, #10 8003936: 721a strb r2, [r3, #8] moto.moto1b=0; 8003938: 4b36 ldr r3, [pc, #216] ; (8003a14 ) 800393a: 2200 movs r2, #0 800393c: 725a strb r2, [r3, #9] moto.moto2a=10; 800393e: 4b35 ldr r3, [pc, #212] ; (8003a14 ) 8003940: 220a movs r2, #10 8003942: 729a strb r2, [r3, #10] moto.moto2b=0; 8003944: 4b33 ldr r3, [pc, #204] ; (8003a14 ) 8003946: 2200 movs r2, #0 8003948: 72da strb r2, [r3, #11] } if(key4.code!=0||(moto.moto1a==0&&moto.moto1b==0&&moto.moto2a==0&&moto.moto2b==0)) 800394a: 4b33 ldr r3, [pc, #204] ; (8003a18 ) 800394c: 681b ldr r3, [r3, #0] 800394e: 2b00 cmp r3, #0 8003950: d10f bne.n 8003972 8003952: 4b30 ldr r3, [pc, #192] ; (8003a14 ) 8003954: 7a1b ldrb r3, [r3, #8] 8003956: 2b00 cmp r3, #0 8003958: d10f bne.n 800397a 800395a: 4b2e ldr r3, [pc, #184] ; (8003a14 ) 800395c: 7a5b ldrb r3, [r3, #9] 800395e: 2b00 cmp r3, #0 8003960: d10b bne.n 800397a 8003962: 4b2c ldr r3, [pc, #176] ; (8003a14 ) 8003964: 7a9b ldrb r3, [r3, #10] 8003966: 2b00 cmp r3, #0 8003968: d107 bne.n 800397a 800396a: 4b2a ldr r3, [pc, #168] ; (8003a14 ) 800396c: 7adb ldrb r3, [r3, #11] 800396e: 2b00 cmp r3, #0 8003970: d103 bne.n 800397a { mode=1; 8003972: 2317 movs r3, #23 8003974: 18fb adds r3, r7, r3 8003976: 2201 movs r2, #1 8003978: 701a strb r2, [r3, #0] } if(ADCC.adc_value[1]>400||(moto_in1==1&&READ_MOT_IN1==0)) 800397a: 4b28 ldr r3, [pc, #160] ; (8003a1c ) 800397c: 691a ldr r2, [r3, #16] 800397e: 23c8 movs r3, #200 ; 0xc8 8003980: 005b lsls r3, r3, #1 8003982: 429a cmp r2, r3 8003984: dc0b bgt.n 800399e 8003986: 230b movs r3, #11 8003988: 18fb adds r3, r7, r3 800398a: 781b ldrb r3, [r3, #0] 800398c: 2b01 cmp r3, #1 800398e: d10c bne.n 80039aa 8003990: 4b23 ldr r3, [pc, #140] ; (8003a20 ) 8003992: 2101 movs r1, #1 8003994: 0018 movs r0, r3 8003996: f7fd ff63 bl 8001860 800399a: 1e03 subs r3, r0, #0 800399c: d105 bne.n 80039aa { //overload_times=0; moto.moto1a=0; 800399e: 4b1d ldr r3, [pc, #116] ; (8003a14 ) 80039a0: 2200 movs r2, #0 80039a2: 721a strb r2, [r3, #8] moto.moto1b=0; 80039a4: 4b1b ldr r3, [pc, #108] ; (8003a14 ) 80039a6: 2200 movs r2, #0 80039a8: 725a strb r2, [r3, #9] } if(ADCC.adc_value[0]>400||(moto_in2==1&&READ_MOT_IN2==0)) 80039aa: 4b1c ldr r3, [pc, #112] ; (8003a1c ) 80039ac: 68da ldr r2, [r3, #12] 80039ae: 23c8 movs r3, #200 ; 0xc8 80039b0: 005b lsls r3, r3, #1 80039b2: 429a cmp r2, r3 80039b4: dc0d bgt.n 80039d2 80039b6: 230a movs r3, #10 80039b8: 18fb adds r3, r7, r3 80039ba: 781b ldrb r3, [r3, #0] 80039bc: 2b01 cmp r3, #1 80039be: d000 beq.n 80039c2 80039c0: e0b9 b.n 8003b36 80039c2: 4b17 ldr r3, [pc, #92] ; (8003a20 ) 80039c4: 2102 movs r1, #2 80039c6: 0018 movs r0, r3 80039c8: f7fd ff4a bl 8001860 80039cc: 1e03 subs r3, r0, #0 80039ce: d000 beq.n 80039d2 80039d0: e0b1 b.n 8003b36 { //overload_times2=0; moto.moto2a=0; 80039d2: 4b10 ldr r3, [pc, #64] ; (8003a14 ) 80039d4: 2200 movs r2, #0 80039d6: 729a strb r2, [r3, #10] moto.moto2b=0; 80039d8: 4b0e ldr r3, [pc, #56] ; (8003a14 ) 80039da: 2200 movs r2, #0 80039dc: 72da strb r2, [r3, #11] } break; 80039de: e0aa b.n 8003b36 case 4: //setting mode dis_buff.led_run=0; 80039e0: 4b0a ldr r3, [pc, #40] ; (8003a0c ) 80039e2: 2200 movs r2, #0 80039e4: 731a strb r2, [r3, #12] if(HAL_GetTick()>move) 80039e6: f7fd f80f bl 8000a08 80039ea: 0002 movs r2, r0 80039ec: 69bb ldr r3, [r7, #24] 80039ee: 4293 cmp r3, r2 80039f0: d240 bcs.n 8003a74 { move=HAL_GetTick()+100; 80039f2: f7fd f809 bl 8000a08 80039f6: 0003 movs r3, r0 80039f8: 3364 adds r3, #100 ; 0x64 80039fa: 61bb str r3, [r7, #24] if(dis_buff.dot4==1) 80039fc: 4b03 ldr r3, [pc, #12] ; (8003a0c ) 80039fe: 7adb ldrb r3, [r3, #11] 8003a00: 2b01 cmp r3, #1 8003a02: d113 bne.n 8003a2c { dis_buff.dot4=0; 8003a04: 4b01 ldr r3, [pc, #4] ; (8003a0c ) 8003a06: 2200 movs r2, #0 8003a08: 72da strb r2, [r3, #11] 8003a0a: e012 b.n 8003a32 8003a0c: 20000038 .word 0x20000038 8003a10: 20000100 .word 0x20000100 8003a14: 20000134 .word 0x20000134 8003a18: 200000d8 .word 0x200000d8 8003a1c: 20000110 .word 0x20000110 8003a20: 48001400 .word 0x48001400 8003a24: 00002710 .word 0x00002710 8003a28: 20000124 .word 0x20000124 }else { dis_buff.dot4=1; 8003a2c: 4b94 ldr r3, [pc, #592] ; (8003c80 ) 8003a2e: 2201 movs r2, #1 8003a30: 72da strb r2, [r3, #11] } countdown-=100; 8003a32: 693b ldr r3, [r7, #16] 8003a34: 3b64 subs r3, #100 ; 0x64 8003a36: 613b str r3, [r7, #16] if(countdown<0) 8003a38: 693b ldr r3, [r7, #16] 8003a3a: 2b00 cmp r3, #0 8003a3c: da03 bge.n 8003a46 { mode=1; 8003a3e: 2317 movs r3, #23 8003a40: 18fb adds r3, r7, r3 8003a42: 2201 movs r2, #1 8003a44: 701a strb r2, [r3, #0] } if(key2.code<0){countdown_set+=1000;countdown=10000;} 8003a46: 4b8f ldr r3, [pc, #572] ; (8003c84 ) 8003a48: 681b ldr r3, [r3, #0] 8003a4a: 2b00 cmp r3, #0 8003a4c: da07 bge.n 8003a5e 8003a4e: 68fb ldr r3, [r7, #12] 8003a50: 22fa movs r2, #250 ; 0xfa 8003a52: 0092 lsls r2, r2, #2 8003a54: 4694 mov ip, r2 8003a56: 4463 add r3, ip 8003a58: 60fb str r3, [r7, #12] 8003a5a: 4b8b ldr r3, [pc, #556] ; (8003c88 ) 8003a5c: 613b str r3, [r7, #16] if(key3.code<0){countdown_set-=1000;countdown=10000;} 8003a5e: 4b8b ldr r3, [pc, #556] ; (8003c8c ) 8003a60: 681b ldr r3, [r3, #0] 8003a62: 2b00 cmp r3, #0 8003a64: da06 bge.n 8003a74 8003a66: 68fb ldr r3, [r7, #12] 8003a68: 4a89 ldr r2, [pc, #548] ; (8003c90 ) 8003a6a: 4694 mov ip, r2 8003a6c: 4463 add r3, ip 8003a6e: 60fb str r3, [r7, #12] 8003a70: 4b85 ldr r3, [pc, #532] ; (8003c88 ) 8003a72: 613b str r3, [r7, #16] } if(key2.code>0){countdown_set+=100;countdown=10000;} 8003a74: 4b83 ldr r3, [pc, #524] ; (8003c84 ) 8003a76: 681b ldr r3, [r3, #0] 8003a78: 2b00 cmp r3, #0 8003a7a: dd04 ble.n 8003a86 8003a7c: 68fb ldr r3, [r7, #12] 8003a7e: 3364 adds r3, #100 ; 0x64 8003a80: 60fb str r3, [r7, #12] 8003a82: 4b81 ldr r3, [pc, #516] ; (8003c88 ) 8003a84: 613b str r3, [r7, #16] if(key3.code>0){countdown_set-=100;countdown=10000;} 8003a86: 4b81 ldr r3, [pc, #516] ; (8003c8c ) 8003a88: 681b ldr r3, [r3, #0] 8003a8a: 2b00 cmp r3, #0 8003a8c: dd04 ble.n 8003a98 8003a8e: 68fb ldr r3, [r7, #12] 8003a90: 3b64 subs r3, #100 ; 0x64 8003a92: 60fb str r3, [r7, #12] 8003a94: 4b7c ldr r3, [pc, #496] ; (8003c88 ) 8003a96: 613b str r3, [r7, #16] if(countdown_set<100){countdown_set=100;} 8003a98: 68fb ldr r3, [r7, #12] 8003a9a: 2b63 cmp r3, #99 ; 0x63 8003a9c: dc01 bgt.n 8003aa2 8003a9e: 2364 movs r3, #100 ; 0x64 8003aa0: 60fb str r3, [r7, #12] if(countdown_set>60000){countdown_set=60000;} 8003aa2: 68fb ldr r3, [r7, #12] 8003aa4: 4a7b ldr r2, [pc, #492] ; (8003c94 ) 8003aa6: 4293 cmp r3, r2 8003aa8: dd01 ble.n 8003aae 8003aaa: 4b7a ldr r3, [pc, #488] ; (8003c94 ) 8003aac: 60fb str r3, [r7, #12] if(key4.code!=0){mode=1;} 8003aae: 4b7a ldr r3, [pc, #488] ; (8003c98 ) 8003ab0: 681b ldr r3, [r3, #0] 8003ab2: 2b00 cmp r3, #0 8003ab4: d003 beq.n 8003abe 8003ab6: 2317 movs r3, #23 8003ab8: 18fb adds r3, r7, r3 8003aba: 2201 movs r2, #1 8003abc: 701a strb r2, [r3, #0] dis_buff.d_num[3]=(countdown_set/100)%10; 8003abe: 68fb ldr r3, [r7, #12] 8003ac0: 2164 movs r1, #100 ; 0x64 8003ac2: 0018 movs r0, r3 8003ac4: f7fc fbaa bl 800021c <__divsi3> 8003ac8: 0003 movs r3, r0 8003aca: 210a movs r1, #10 8003acc: 0018 movs r0, r3 8003ace: f7fc fc8b bl 80003e8 <__aeabi_idivmod> 8003ad2: 000b movs r3, r1 8003ad4: b2da uxtb r2, r3 8003ad6: 4b6a ldr r3, [pc, #424] ; (8003c80 ) 8003ad8: 70da strb r2, [r3, #3] dis_buff.d_num[2]=(countdown_set/1000)%10; 8003ada: 68fb ldr r3, [r7, #12] 8003adc: 22fa movs r2, #250 ; 0xfa 8003ade: 0091 lsls r1, r2, #2 8003ae0: 0018 movs r0, r3 8003ae2: f7fc fb9b bl 800021c <__divsi3> 8003ae6: 0003 movs r3, r0 8003ae8: 210a movs r1, #10 8003aea: 0018 movs r0, r3 8003aec: f7fc fc7c bl 80003e8 <__aeabi_idivmod> 8003af0: 000b movs r3, r1 8003af2: b2da uxtb r2, r3 8003af4: 4b62 ldr r3, [pc, #392] ; (8003c80 ) 8003af6: 709a strb r2, [r3, #2] dis_buff.d_num[1]=((countdown_set/10000)%10); 8003af8: 68fb ldr r3, [r7, #12] 8003afa: 4963 ldr r1, [pc, #396] ; (8003c88 ) 8003afc: 0018 movs r0, r3 8003afe: f7fc fb8d bl 800021c <__divsi3> 8003b02: 0003 movs r3, r0 8003b04: 210a movs r1, #10 8003b06: 0018 movs r0, r3 8003b08: f7fc fc6e bl 80003e8 <__aeabi_idivmod> 8003b0c: 000b movs r3, r1 8003b0e: b2da uxtb r2, r3 8003b10: 4b5b ldr r3, [pc, #364] ; (8003c80 ) 8003b12: 705a strb r2, [r3, #1] dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1]; 8003b14: 4b5a ldr r3, [pc, #360] ; (8003c80 ) 8003b16: 785b ldrb r3, [r3, #1] 8003b18: 2b00 cmp r3, #0 8003b1a: d002 beq.n 8003b22 8003b1c: 4b58 ldr r3, [pc, #352] ; (8003c80 ) 8003b1e: 785a ldrb r2, [r3, #1] 8003b20: e000 b.n 8003b24 8003b22: 2210 movs r2, #16 8003b24: 4b56 ldr r3, [pc, #344] ; (8003c80 ) 8003b26: 705a strb r2, [r3, #1] break; 8003b28: e006 b.n 8003b38 break; 8003b2a: 46c0 nop ; (mov r8, r8) 8003b2c: e004 b.n 8003b38 break; 8003b2e: 46c0 nop ; (mov r8, r8) 8003b30: e002 b.n 8003b38 break; 8003b32: 46c0 nop ; (mov r8, r8) 8003b34: e000 b.n 8003b38 break; 8003b36: 46c0 nop ; (mov r8, r8) if(r480.add[0]==config.key_code[0]&&r480.add[1]==config.key_code[1]) 8003b38: 4b58 ldr r3, [pc, #352] ; (8003c9c ) 8003b3a: 781a ldrb r2, [r3, #0] 8003b3c: 4b58 ldr r3, [pc, #352] ; (8003ca0 ) 8003b3e: 781b ldrb r3, [r3, #0] 8003b40: 429a cmp r2, r3 8003b42: d122 bne.n 8003b8a 8003b44: 4b55 ldr r3, [pc, #340] ; (8003c9c ) 8003b46: 785a ldrb r2, [r3, #1] 8003b48: 4b55 ldr r3, [pc, #340] ; (8003ca0 ) 8003b4a: 785b ldrb r3, [r3, #1] 8003b4c: 429a cmp r2, r3 8003b4e: d11c bne.n 8003b8a { switch(r480.key) 8003b50: 4b52 ldr r3, [pc, #328] ; (8003c9c ) 8003b52: 789b ldrb r3, [r3, #2] 8003b54: 2bde cmp r3, #222 ; 0xde 8003b56: d014 beq.n 8003b82 8003b58: dc18 bgt.n 8003b8c 8003b5a: 2bdd cmp r3, #221 ; 0xdd 8003b5c: d00d beq.n 8003b7a 8003b5e: dc15 bgt.n 8003b8c 8003b60: 2bd7 cmp r3, #215 ; 0xd7 8003b62: d002 beq.n 8003b6a 8003b64: 2bdb cmp r3, #219 ; 0xdb 8003b66: d004 beq.n 8003b72 8003b68: e010 b.n 8003b8c { case 0xd7: dis_buff.button_flag[0]=1; 8003b6a: 4b45 ldr r3, [pc, #276] ; (8003c80 ) 8003b6c: 2201 movs r2, #1 8003b6e: 711a strb r2, [r3, #4] break; 8003b70: e00c b.n 8003b8c case 0xdb: dis_buff.button_flag[1]=1; 8003b72: 4b43 ldr r3, [pc, #268] ; (8003c80 ) 8003b74: 2201 movs r2, #1 8003b76: 715a strb r2, [r3, #5] break; 8003b78: e008 b.n 8003b8c case 0xdd: dis_buff.button_flag[2]=1; 8003b7a: 4b41 ldr r3, [pc, #260] ; (8003c80 ) 8003b7c: 2201 movs r2, #1 8003b7e: 719a strb r2, [r3, #6] break; 8003b80: e004 b.n 8003b8c case 0xde: dis_buff.button_flag[3]=1; 8003b82: 4b3f ldr r3, [pc, #252] ; (8003c80 ) 8003b84: 2201 movs r2, #1 8003b86: 71da strb r2, [r3, #7] break; 8003b88: e000 b.n 8003b8c } } 8003b8a: 46c0 nop ; (mov r8, r8) r480.key=0; 8003b8c: 4b43 ldr r3, [pc, #268] ; (8003c9c ) 8003b8e: 2200 movs r2, #0 8003b90: 709a strb r2, [r3, #2] r480.add[0]=0; 8003b92: 4b42 ldr r3, [pc, #264] ; (8003c9c ) 8003b94: 2200 movs r2, #0 8003b96: 701a strb r2, [r3, #0] r480.add[1]=0; 8003b98: 4b40 ldr r3, [pc, #256] ; (8003c9c ) 8003b9a: 2200 movs r2, #0 8003b9c: 705a strb r2, [r3, #1] GEI_BUTTON_CODE(&key1,dis_buff.button_flag[0]); 8003b9e: 4b38 ldr r3, [pc, #224] ; (8003c80 ) 8003ba0: 791a ldrb r2, [r3, #4] 8003ba2: 4b40 ldr r3, [pc, #256] ; (8003ca4 ) 8003ba4: 0011 movs r1, r2 8003ba6: 0018 movs r0, r3 8003ba8: f7fe fd62 bl 8002670 GEI_BUTTON_CODE(&key2,dis_buff.button_flag[1]); 8003bac: 4b34 ldr r3, [pc, #208] ; (8003c80 ) 8003bae: 795a ldrb r2, [r3, #5] 8003bb0: 4b34 ldr r3, [pc, #208] ; (8003c84 ) 8003bb2: 0011 movs r1, r2 8003bb4: 0018 movs r0, r3 8003bb6: f7fe fd5b bl 8002670 GEI_BUTTON_CODE(&key3,dis_buff.button_flag[2]); 8003bba: 4b31 ldr r3, [pc, #196] ; (8003c80 ) 8003bbc: 799a ldrb r2, [r3, #6] 8003bbe: 4b33 ldr r3, [pc, #204] ; (8003c8c ) 8003bc0: 0011 movs r1, r2 8003bc2: 0018 movs r0, r3 8003bc4: f7fe fd54 bl 8002670 GEI_BUTTON_CODE(&key4,dis_buff.button_flag[3]); 8003bc8: 4b2d ldr r3, [pc, #180] ; (8003c80 ) 8003bca: 79da ldrb r2, [r3, #7] 8003bcc: 4b32 ldr r3, [pc, #200] ; (8003c98 ) 8003bce: 0011 movs r1, r2 8003bd0: 0018 movs r0, r3 8003bd2: f7fe fd4d bl 8002670 dis_buff.button_flag[0]=0; 8003bd6: 4b2a ldr r3, [pc, #168] ; (8003c80 ) 8003bd8: 2200 movs r2, #0 8003bda: 711a strb r2, [r3, #4] dis_buff.button_flag[1]=0; 8003bdc: 4b28 ldr r3, [pc, #160] ; (8003c80 ) 8003bde: 2200 movs r2, #0 8003be0: 715a strb r2, [r3, #5] dis_buff.button_flag[2]=0; 8003be2: 4b27 ldr r3, [pc, #156] ; (8003c80 ) 8003be4: 2200 movs r2, #0 8003be6: 719a strb r2, [r3, #6] dis_buff.button_flag[3]=0; 8003be8: 4b25 ldr r3, [pc, #148] ; (8003c80 ) 8003bea: 2200 movs r2, #0 8003bec: 71da strb r2, [r3, #7] if(moto_in1!=READ_MOT_IN1) 8003bee: 4b2e ldr r3, [pc, #184] ; (8003ca8 ) 8003bf0: 2101 movs r1, #1 8003bf2: 0018 movs r0, r3 8003bf4: f7fd fe34 bl 8001860 8003bf8: 0003 movs r3, r0 8003bfa: 001a movs r2, r3 8003bfc: 200b movs r0, #11 8003bfe: 183b adds r3, r7, r0 8003c00: 781b ldrb r3, [r3, #0] 8003c02: 4293 cmp r3, r2 8003c04: d014 beq.n 8003c30 { moto_in1_pp++; 8003c06: 2108 movs r1, #8 8003c08: 187b adds r3, r7, r1 8003c0a: 881a ldrh r2, [r3, #0] 8003c0c: 187b adds r3, r7, r1 8003c0e: 3201 adds r2, #1 8003c10: 801a strh r2, [r3, #0] if(moto_in1_pp==100) 8003c12: 187b adds r3, r7, r1 8003c14: 881b ldrh r3, [r3, #0] 8003c16: 2b64 cmp r3, #100 ; 0x64 8003c18: d10a bne.n 8003c30 { moto_in1_pp=0; 8003c1a: 187b adds r3, r7, r1 8003c1c: 2200 movs r2, #0 8003c1e: 801a strh r2, [r3, #0] moto_in1=READ_MOT_IN1; 8003c20: 183c adds r4, r7, r0 8003c22: 4b21 ldr r3, [pc, #132] ; (8003ca8 ) 8003c24: 2101 movs r1, #1 8003c26: 0018 movs r0, r3 8003c28: f7fd fe1a bl 8001860 8003c2c: 0003 movs r3, r0 8003c2e: 7023 strb r3, [r4, #0] } } if(moto_in2!=READ_MOT_IN2) 8003c30: 4b1d ldr r3, [pc, #116] ; (8003ca8 ) 8003c32: 2102 movs r1, #2 8003c34: 0018 movs r0, r3 8003c36: f7fd fe13 bl 8001860 8003c3a: 0003 movs r3, r0 8003c3c: 001a movs r2, r3 8003c3e: 210a movs r1, #10 8003c40: 187b adds r3, r7, r1 8003c42: 781b ldrb r3, [r3, #0] 8003c44: 4293 cmp r3, r2 8003c46: d013 beq.n 8003c70 { moto_in2_pp++; 8003c48: 1dbb adds r3, r7, #6 8003c4a: 881a ldrh r2, [r3, #0] 8003c4c: 1dbb adds r3, r7, #6 8003c4e: 3201 adds r2, #1 8003c50: 801a strh r2, [r3, #0] if(moto_in2_pp==100) 8003c52: 1dbb adds r3, r7, #6 8003c54: 881b ldrh r3, [r3, #0] 8003c56: 2b64 cmp r3, #100 ; 0x64 8003c58: d10a bne.n 8003c70 { moto_in2_pp=0; 8003c5a: 1dbb adds r3, r7, #6 8003c5c: 2200 movs r2, #0 8003c5e: 801a strh r2, [r3, #0] moto_in2=READ_MOT_IN2; 8003c60: 187c adds r4, r7, r1 8003c62: 4b11 ldr r3, [pc, #68] ; (8003ca8 ) 8003c64: 2102 movs r1, #2 8003c66: 0018 movs r0, r3 8003c68: f7fd fdfa bl 8001860 8003c6c: 0003 movs r3, r0 8003c6e: 7023 strb r3, [r4, #0] } } HT1621_Display_GetButton(); 8003c70: f7ff fad4 bl 800321c hc2_sever(); 8003c74: f7ff f9be bl 8002ff4 moto_server(); 8003c78: f7ff fa00 bl 800307c for(char a=0;a<2;a++) 8003c7c: f7ff fbff bl 800347e 8003c80: 20000038 .word 0x20000038 8003c84: 20000124 .word 0x20000124 8003c88: 00002710 .word 0x00002710 8003c8c: 20000100 .word 0x20000100 8003c90: fffffc18 .word 0xfffffc18 8003c94: 0000ea60 .word 0x0000ea60 8003c98: 200000d8 .word 0x200000d8 8003c9c: 200000e8 .word 0x200000e8 8003ca0: 20000144 .word 0x20000144 8003ca4: 200000f0 .word 0x200000f0 8003ca8: 48001400 .word 0x48001400 08003cac : int read_char_flag=0; char read_data_buffer[3]; char read_begin=0; void r480_init() { 8003cac: b580 push {r7, lr} 8003cae: af00 add r7, sp, #0 HAL_TIM_Base_Start_IT(&htim14); 8003cb0: 4b04 ldr r3, [pc, #16] ; (8003cc4 ) 8003cb2: 0018 movs r0, r3 8003cb4: f7fe fae4 bl 8002280 r480.times=0; 8003cb8: 4b03 ldr r3, [pc, #12] ; (8003cc8 ) 8003cba: 2200 movs r2, #0 8003cbc: 809a strh r2, [r3, #4] } 8003cbe: 46c0 nop ; (mov r8, r8) 8003cc0: 46bd mov sp, r7 8003cc2: bd80 pop {r7, pc} 8003cc4: 2000004c .word 0x2000004c 8003cc8: 200000e8 .word 0x200000e8 08003ccc : void read_433_exit() { 8003ccc: b590 push {r4, r7, lr} 8003cce: b083 sub sp, #12 8003cd0: af00 add r7, sp, #0 char a=read_infrared; 8003cd2: 1dfc adds r4, r7, #7 8003cd4: 2390 movs r3, #144 ; 0x90 8003cd6: 05db lsls r3, r3, #23 8003cd8: 2108 movs r1, #8 8003cda: 0018 movs r0, r3 8003cdc: f7fd fdc0 bl 8001860 8003ce0: 0003 movs r3, r0 8003ce2: 7023 strb r3, [r4, #0] int b; if(read_begin==0) 8003ce4: 4b41 ldr r3, [pc, #260] ; (8003dec ) 8003ce6: 781b ldrb r3, [r3, #0] 8003ce8: 2b00 cmp r3, #0 8003cea: d123 bne.n 8003d34 { if(a==0) 8003cec: 1dfb adds r3, r7, #7 8003cee: 781b ldrb r3, [r3, #0] 8003cf0: 2b00 cmp r3, #0 8003cf2: d103 bne.n 8003cfc { timer_100us_tick=0; 8003cf4: 4b3e ldr r3, [pc, #248] ; (8003df0 ) 8003cf6: 2200 movs r2, #0 8003cf8: 801a strh r2, [r3, #0] return ; 8003cfa: e073 b.n 8003de4 }else { if(timer_100us_tick>70&&timer_100us_tick<100) 8003cfc: 4b3c ldr r3, [pc, #240] ; (8003df0 ) 8003cfe: 881b ldrh r3, [r3, #0] 8003d00: 2b46 cmp r3, #70 ; 0x46 8003d02: d800 bhi.n 8003d06 8003d04: e06e b.n 8003de4 8003d06: 4b3a ldr r3, [pc, #232] ; (8003df0 ) 8003d08: 881b ldrh r3, [r3, #0] 8003d0a: 2b63 cmp r3, #99 ; 0x63 8003d0c: d86a bhi.n 8003de4 { read_begin=1; 8003d0e: 4b37 ldr r3, [pc, #220] ; (8003dec ) 8003d10: 2201 movs r2, #1 8003d12: 701a strb r2, [r3, #0] r480.times++; 8003d14: 4b37 ldr r3, [pc, #220] ; (8003df4 ) 8003d16: 889b ldrh r3, [r3, #4] 8003d18: 3301 adds r3, #1 8003d1a: b29a uxth r2, r3 8003d1c: 4b35 ldr r3, [pc, #212] ; (8003df4 ) 8003d1e: 809a strh r2, [r3, #4] read_bit_flag=0; 8003d20: 4b35 ldr r3, [pc, #212] ; (8003df8 ) 8003d22: 2200 movs r2, #0 8003d24: 601a str r2, [r3, #0] read_char_flag=0; 8003d26: 4b35 ldr r3, [pc, #212] ; (8003dfc ) 8003d28: 2200 movs r2, #0 8003d2a: 601a str r2, [r3, #0] timer_100us_tick=0; 8003d2c: 4b30 ldr r3, [pc, #192] ; (8003df0 ) 8003d2e: 2200 movs r2, #0 8003d30: 801a strh r2, [r3, #0] return ; 8003d32: e057 b.n 8003de4 } } }else { if(timer_100us_tick<5) 8003d34: 4b2e ldr r3, [pc, #184] ; (8003df0 ) 8003d36: 881b ldrh r3, [r3, #0] 8003d38: 2b04 cmp r3, #4 8003d3a: d803 bhi.n 8003d44 { timer_100us_tick=0; 8003d3c: 4b2c ldr r3, [pc, #176] ; (8003df0 ) 8003d3e: 2200 movs r2, #0 8003d40: 801a strh r2, [r3, #0] return ; 8003d42: e04f b.n 8003de4 }else if(timer_100us_tick<12) 8003d44: 4b2a ldr r3, [pc, #168] ; (8003df0 ) 8003d46: 881b ldrh r3, [r3, #0] 8003d48: 2b0b cmp r3, #11 8003d4a: d844 bhi.n 8003dd6 { read_data_buffer[read_char_flag]<<=1; 8003d4c: 4b2b ldr r3, [pc, #172] ; (8003dfc ) 8003d4e: 681b ldr r3, [r3, #0] 8003d50: 4a2b ldr r2, [pc, #172] ; (8003e00 ) 8003d52: 5cd1 ldrb r1, [r2, r3] 8003d54: 4b29 ldr r3, [pc, #164] ; (8003dfc ) 8003d56: 681a ldr r2, [r3, #0] 8003d58: 1c0b adds r3, r1, #0 8003d5a: 18db adds r3, r3, r3 8003d5c: b2d9 uxtb r1, r3 8003d5e: 4b28 ldr r3, [pc, #160] ; (8003e00 ) 8003d60: 5499 strb r1, [r3, r2] if(a==1) 8003d62: 1dfb adds r3, r7, #7 8003d64: 781b ldrb r3, [r3, #0] 8003d66: 2b01 cmp r3, #1 8003d68: d10a bne.n 8003d80 { read_data_buffer[read_char_flag]|=0x01; 8003d6a: 4b24 ldr r3, [pc, #144] ; (8003dfc ) 8003d6c: 681b ldr r3, [r3, #0] 8003d6e: 4a24 ldr r2, [pc, #144] ; (8003e00 ) 8003d70: 5cd2 ldrb r2, [r2, r3] 8003d72: 4b22 ldr r3, [pc, #136] ; (8003dfc ) 8003d74: 681b ldr r3, [r3, #0] 8003d76: 2101 movs r1, #1 8003d78: 430a orrs r2, r1 8003d7a: b2d1 uxtb r1, r2 8003d7c: 4a20 ldr r2, [pc, #128] ; (8003e00 ) 8003d7e: 54d1 strb r1, [r2, r3] } read_bit_flag++; 8003d80: 4b1d ldr r3, [pc, #116] ; (8003df8 ) 8003d82: 681b ldr r3, [r3, #0] 8003d84: 1c5a adds r2, r3, #1 8003d86: 4b1c ldr r3, [pc, #112] ; (8003df8 ) 8003d88: 601a str r2, [r3, #0] if(read_bit_flag==8) 8003d8a: 4b1b ldr r3, [pc, #108] ; (8003df8 ) 8003d8c: 681b ldr r3, [r3, #0] 8003d8e: 2b08 cmp r3, #8 8003d90: d11d bne.n 8003dce { read_bit_flag=0; 8003d92: 4b19 ldr r3, [pc, #100] ; (8003df8 ) 8003d94: 2200 movs r2, #0 8003d96: 601a str r2, [r3, #0] read_char_flag++; 8003d98: 4b18 ldr r3, [pc, #96] ; (8003dfc ) 8003d9a: 681b ldr r3, [r3, #0] 8003d9c: 1c5a adds r2, r3, #1 8003d9e: 4b17 ldr r3, [pc, #92] ; (8003dfc ) 8003da0: 601a str r2, [r3, #0] if(read_char_flag==3) 8003da2: 4b16 ldr r3, [pc, #88] ; (8003dfc ) 8003da4: 681b ldr r3, [r3, #0] 8003da6: 2b03 cmp r3, #3 8003da8: d111 bne.n 8003dce { //got data read_char_flag=0; 8003daa: 4b14 ldr r3, [pc, #80] ; (8003dfc ) 8003dac: 2200 movs r2, #0 8003dae: 601a str r2, [r3, #0] timer_100us_tick=0; 8003db0: 4b0f ldr r3, [pc, #60] ; (8003df0 ) 8003db2: 2200 movs r2, #0 8003db4: 801a strh r2, [r3, #0] r480.add[0]=read_data_buffer[0]; 8003db6: 4b12 ldr r3, [pc, #72] ; (8003e00 ) 8003db8: 781a ldrb r2, [r3, #0] 8003dba: 4b0e ldr r3, [pc, #56] ; (8003df4 ) 8003dbc: 701a strb r2, [r3, #0] r480.add[1]=read_data_buffer[1]; 8003dbe: 4b10 ldr r3, [pc, #64] ; (8003e00 ) 8003dc0: 785a ldrb r2, [r3, #1] 8003dc2: 4b0c ldr r3, [pc, #48] ; (8003df4 ) 8003dc4: 705a strb r2, [r3, #1] r480.key=read_data_buffer[2]; 8003dc6: 4b0e ldr r3, [pc, #56] ; (8003e00 ) 8003dc8: 789a ldrb r2, [r3, #2] 8003dca: 4b0a ldr r3, [pc, #40] ; (8003df4 ) 8003dcc: 709a strb r2, [r3, #2] } } timer_100us_tick=0; 8003dce: 4b08 ldr r3, [pc, #32] ; (8003df0 ) 8003dd0: 2200 movs r2, #0 8003dd2: 801a strh r2, [r3, #0] return ; 8003dd4: e006 b.n 8003de4 }else//time out { read_begin=0; 8003dd6: 4b05 ldr r3, [pc, #20] ; (8003dec ) 8003dd8: 2200 movs r2, #0 8003dda: 701a strb r2, [r3, #0] timer_100us_tick=0; 8003ddc: 4b04 ldr r3, [pc, #16] ; (8003df0 ) 8003dde: 2200 movs r2, #0 8003de0: 801a strh r2, [r3, #0] return ; 8003de2: 46c0 nop ; (mov r8, r8) } } } 8003de4: 46bd mov sp, r7 8003de6: b003 add sp, #12 8003de8: bd90 pop {r4, r7, pc} 8003dea: 46c0 nop ; (mov r8, r8) 8003dec: 20000034 .word 0x20000034 8003df0: 20000028 .word 0x20000028 8003df4: 200000e8 .word 0x200000e8 8003df8: 2000002c .word 0x2000002c 8003dfc: 20000030 .word 0x20000030 8003e00: 2000014c .word 0x2000014c 08003e04 : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8003e04: b580 push {r7, lr} 8003e06: b082 sub sp, #8 8003e08: af00 add r7, sp, #0 8003e0a: 0002 movs r2, r0 8003e0c: 1dbb adds r3, r7, #6 8003e0e: 801a strh r2, [r3, #0] switch(GPIO_Pin) 8003e10: 1dbb adds r3, r7, #6 8003e12: 881b ldrh r3, [r3, #0] 8003e14: 2b08 cmp r3, #8 8003e16: d102 bne.n 8003e1e { case infeaed_Pin: read_433_exit(); 8003e18: f7ff ff58 bl 8003ccc return ; 8003e1c: 46c0 nop ; (mov r8, r8) break; } } 8003e1e: 46bd mov sp, r7 8003e20: b002 add sp, #8 8003e22: bd80 pop {r7, pc} 08003e24 : void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)//100us { 8003e24: b580 push {r7, lr} 8003e26: b082 sub sp, #8 8003e28: af00 add r7, sp, #0 8003e2a: 6078 str r0, [r7, #4] if (htim == (&htim14)) 8003e2c: 687a ldr r2, [r7, #4] 8003e2e: 4b06 ldr r3, [pc, #24] ; (8003e48 ) 8003e30: 429a cmp r2, r3 8003e32: d105 bne.n 8003e40 { timer_100us_tick++; 8003e34: 4b05 ldr r3, [pc, #20] ; (8003e4c ) 8003e36: 881b ldrh r3, [r3, #0] 8003e38: 3301 adds r3, #1 8003e3a: b29a uxth r2, r3 8003e3c: 4b03 ldr r3, [pc, #12] ; (8003e4c ) 8003e3e: 801a strh r2, [r3, #0] } } 8003e40: 46c0 nop ; (mov r8, r8) 8003e42: 46bd mov sp, r7 8003e44: b002 add sp, #8 8003e46: bd80 pop {r7, pc} 8003e48: 2000004c .word 0x2000004c 8003e4c: 20000028 .word 0x20000028 08003e50 <__libc_init_array>: 8003e50: b570 push {r4, r5, r6, lr} 8003e52: 2600 movs r6, #0 8003e54: 4d0c ldr r5, [pc, #48] ; (8003e88 <__libc_init_array+0x38>) 8003e56: 4c0d ldr r4, [pc, #52] ; (8003e8c <__libc_init_array+0x3c>) 8003e58: 1b64 subs r4, r4, r5 8003e5a: 10a4 asrs r4, r4, #2 8003e5c: 42a6 cmp r6, r4 8003e5e: d109 bne.n 8003e74 <__libc_init_array+0x24> 8003e60: 2600 movs r6, #0 8003e62: f000 f821 bl 8003ea8 <_init> 8003e66: 4d0a ldr r5, [pc, #40] ; (8003e90 <__libc_init_array+0x40>) 8003e68: 4c0a ldr r4, [pc, #40] ; (8003e94 <__libc_init_array+0x44>) 8003e6a: 1b64 subs r4, r4, r5 8003e6c: 10a4 asrs r4, r4, #2 8003e6e: 42a6 cmp r6, r4 8003e70: d105 bne.n 8003e7e <__libc_init_array+0x2e> 8003e72: bd70 pop {r4, r5, r6, pc} 8003e74: 00b3 lsls r3, r6, #2 8003e76: 58eb ldr r3, [r5, r3] 8003e78: 4798 blx r3 8003e7a: 3601 adds r6, #1 8003e7c: e7ee b.n 8003e5c <__libc_init_array+0xc> 8003e7e: 00b3 lsls r3, r6, #2 8003e80: 58eb ldr r3, [r5, r3] 8003e82: 4798 blx r3 8003e84: 3601 adds r6, #1 8003e86: e7f2 b.n 8003e6e <__libc_init_array+0x1e> 8003e88: 08003f18 .word 0x08003f18 8003e8c: 08003f18 .word 0x08003f18 8003e90: 08003f18 .word 0x08003f18 8003e94: 08003f1c .word 0x08003f1c 08003e98 : 8003e98: 0003 movs r3, r0 8003e9a: 1882 adds r2, r0, r2 8003e9c: 4293 cmp r3, r2 8003e9e: d100 bne.n 8003ea2 8003ea0: 4770 bx lr 8003ea2: 7019 strb r1, [r3, #0] 8003ea4: 3301 adds r3, #1 8003ea6: e7f9 b.n 8003e9c 08003ea8 <_init>: 8003ea8: b5f8 push {r3, r4, r5, r6, r7, lr} 8003eaa: 46c0 nop ; (mov r8, r8) 8003eac: bcf8 pop {r3, r4, r5, r6, r7} 8003eae: bc08 pop {r3} 8003eb0: 469e mov lr, r3 8003eb2: 4770 bx lr 08003eb4 <_fini>: 8003eb4: b5f8 push {r3, r4, r5, r6, r7, lr} 8003eb6: 46c0 nop ; (mov r8, r8) 8003eb8: bcf8 pop {r3, r4, r5, r6, r7} 8003eba: bc08 pop {r3} 8003ebc: 469e mov lr, r3 8003ebe: 4770 bx lr