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b8bf07f4cffbcc05dc2b622397dab8e97b207099
motor_controller2/Debug/Motor_Controller2.list
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kevin b8bf07f4cf 优化中，生成HEX文件
2021-10-24 11:04:21 +08:00

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Motor_Controller2.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000372c 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000005c 080037ec 080037ec 000137ec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08003848 08003848 0002000c 2**0
CONTENTS
4 .ARM 00000000 08003848 08003848 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08003848 08003848 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08003848 08003848 00013848 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 0800384c 0800384c 0001384c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08003850 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000014c 2000000c 0800385c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000158 0800385c 00020158 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 0000aea4 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001e10 00000000 00000000 0002aed8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000ab8 00000000 00000000 0002cce8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 000009b0 00000000 00000000 0002d7a0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0000fd9f 00000000 00000000 0002e150 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000d877 00000000 00000000 0003deef 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0005edcc 00000000 00000000 0004b766 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 000aa532 2**0
CONTENTS, READONLY
20 .debug_frame 00002548 00000000 00000000 000aa588 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 080037d4 .word 0x080037d4
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 080037d4 .word 0x080037d4
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__divsi3>:
800021c: 4603 mov r3, r0
800021e: 430b orrs r3, r1
8000220: d47f bmi.n 8000322 <__divsi3+0x106>
8000222: 2200 movs r2, #0
8000224: 0843 lsrs r3, r0, #1
8000226: 428b cmp r3, r1
8000228: d374 bcc.n 8000314 <__divsi3+0xf8>
800022a: 0903 lsrs r3, r0, #4
800022c: 428b cmp r3, r1
800022e: d35f bcc.n 80002f0 <__divsi3+0xd4>
8000230: 0a03 lsrs r3, r0, #8
8000232: 428b cmp r3, r1
8000234: d344 bcc.n 80002c0 <__divsi3+0xa4>
8000236: 0b03 lsrs r3, r0, #12
8000238: 428b cmp r3, r1
800023a: d328 bcc.n 800028e <__divsi3+0x72>
800023c: 0c03 lsrs r3, r0, #16
800023e: 428b cmp r3, r1
8000240: d30d bcc.n 800025e <__divsi3+0x42>
8000242: 22ff movs r2, #255 ; 0xff
8000244: 0209 lsls r1, r1, #8
8000246: ba12 rev r2, r2
8000248: 0c03 lsrs r3, r0, #16
800024a: 428b cmp r3, r1
800024c: d302 bcc.n 8000254 <__divsi3+0x38>
800024e: 1212 asrs r2, r2, #8
8000250: 0209 lsls r1, r1, #8
8000252: d065 beq.n 8000320 <__divsi3+0x104>
8000254: 0b03 lsrs r3, r0, #12
8000256: 428b cmp r3, r1
8000258: d319 bcc.n 800028e <__divsi3+0x72>
800025a: e000 b.n 800025e <__divsi3+0x42>
800025c: 0a09 lsrs r1, r1, #8
800025e: 0bc3 lsrs r3, r0, #15
8000260: 428b cmp r3, r1
8000262: d301 bcc.n 8000268 <__divsi3+0x4c>
8000264: 03cb lsls r3, r1, #15
8000266: 1ac0 subs r0, r0, r3
8000268: 4152 adcs r2, r2
800026a: 0b83 lsrs r3, r0, #14
800026c: 428b cmp r3, r1
800026e: d301 bcc.n 8000274 <__divsi3+0x58>
8000270: 038b lsls r3, r1, #14
8000272: 1ac0 subs r0, r0, r3
8000274: 4152 adcs r2, r2
8000276: 0b43 lsrs r3, r0, #13
8000278: 428b cmp r3, r1
800027a: d301 bcc.n 8000280 <__divsi3+0x64>
800027c: 034b lsls r3, r1, #13
800027e: 1ac0 subs r0, r0, r3
8000280: 4152 adcs r2, r2
8000282: 0b03 lsrs r3, r0, #12
8000284: 428b cmp r3, r1
8000286: d301 bcc.n 800028c <__divsi3+0x70>
8000288: 030b lsls r3, r1, #12
800028a: 1ac0 subs r0, r0, r3
800028c: 4152 adcs r2, r2
800028e: 0ac3 lsrs r3, r0, #11
8000290: 428b cmp r3, r1
8000292: d301 bcc.n 8000298 <__divsi3+0x7c>
8000294: 02cb lsls r3, r1, #11
8000296: 1ac0 subs r0, r0, r3
8000298: 4152 adcs r2, r2
800029a: 0a83 lsrs r3, r0, #10
800029c: 428b cmp r3, r1
800029e: d301 bcc.n 80002a4 <__divsi3+0x88>
80002a0: 028b lsls r3, r1, #10
80002a2: 1ac0 subs r0, r0, r3
80002a4: 4152 adcs r2, r2
80002a6: 0a43 lsrs r3, r0, #9
80002a8: 428b cmp r3, r1
80002aa: d301 bcc.n 80002b0 <__divsi3+0x94>
80002ac: 024b lsls r3, r1, #9
80002ae: 1ac0 subs r0, r0, r3
80002b0: 4152 adcs r2, r2
80002b2: 0a03 lsrs r3, r0, #8
80002b4: 428b cmp r3, r1
80002b6: d301 bcc.n 80002bc <__divsi3+0xa0>
80002b8: 020b lsls r3, r1, #8
80002ba: 1ac0 subs r0, r0, r3
80002bc: 4152 adcs r2, r2
80002be: d2cd bcs.n 800025c <__divsi3+0x40>
80002c0: 09c3 lsrs r3, r0, #7
80002c2: 428b cmp r3, r1
80002c4: d301 bcc.n 80002ca <__divsi3+0xae>
80002c6: 01cb lsls r3, r1, #7
80002c8: 1ac0 subs r0, r0, r3
80002ca: 4152 adcs r2, r2
80002cc: 0983 lsrs r3, r0, #6
80002ce: 428b cmp r3, r1
80002d0: d301 bcc.n 80002d6 <__divsi3+0xba>
80002d2: 018b lsls r3, r1, #6
80002d4: 1ac0 subs r0, r0, r3
80002d6: 4152 adcs r2, r2
80002d8: 0943 lsrs r3, r0, #5
80002da: 428b cmp r3, r1
80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6>
80002de: 014b lsls r3, r1, #5
80002e0: 1ac0 subs r0, r0, r3
80002e2: 4152 adcs r2, r2
80002e4: 0903 lsrs r3, r0, #4
80002e6: 428b cmp r3, r1
80002e8: d301 bcc.n 80002ee <__divsi3+0xd2>
80002ea: 010b lsls r3, r1, #4
80002ec: 1ac0 subs r0, r0, r3
80002ee: 4152 adcs r2, r2
80002f0: 08c3 lsrs r3, r0, #3
80002f2: 428b cmp r3, r1
80002f4: d301 bcc.n 80002fa <__divsi3+0xde>
80002f6: 00cb lsls r3, r1, #3
80002f8: 1ac0 subs r0, r0, r3
80002fa: 4152 adcs r2, r2
80002fc: 0883 lsrs r3, r0, #2
80002fe: 428b cmp r3, r1
8000300: d301 bcc.n 8000306 <__divsi3+0xea>
8000302: 008b lsls r3, r1, #2
8000304: 1ac0 subs r0, r0, r3
8000306: 4152 adcs r2, r2
8000308: 0843 lsrs r3, r0, #1
800030a: 428b cmp r3, r1
800030c: d301 bcc.n 8000312 <__divsi3+0xf6>
800030e: 004b lsls r3, r1, #1
8000310: 1ac0 subs r0, r0, r3
8000312: 4152 adcs r2, r2
8000314: 1a41 subs r1, r0, r1
8000316: d200 bcs.n 800031a <__divsi3+0xfe>
8000318: 4601 mov r1, r0
800031a: 4152 adcs r2, r2
800031c: 4610 mov r0, r2
800031e: 4770 bx lr
8000320: e05d b.n 80003de <__divsi3+0x1c2>
8000322: 0fca lsrs r2, r1, #31
8000324: d000 beq.n 8000328 <__divsi3+0x10c>
8000326: 4249 negs r1, r1
8000328: 1003 asrs r3, r0, #32
800032a: d300 bcc.n 800032e <__divsi3+0x112>
800032c: 4240 negs r0, r0
800032e: 4053 eors r3, r2
8000330: 2200 movs r2, #0
8000332: 469c mov ip, r3
8000334: 0903 lsrs r3, r0, #4
8000336: 428b cmp r3, r1
8000338: d32d bcc.n 8000396 <__divsi3+0x17a>
800033a: 0a03 lsrs r3, r0, #8
800033c: 428b cmp r3, r1
800033e: d312 bcc.n 8000366 <__divsi3+0x14a>
8000340: 22fc movs r2, #252 ; 0xfc
8000342: 0189 lsls r1, r1, #6
8000344: ba12 rev r2, r2
8000346: 0a03 lsrs r3, r0, #8
8000348: 428b cmp r3, r1
800034a: d30c bcc.n 8000366 <__divsi3+0x14a>
800034c: 0189 lsls r1, r1, #6
800034e: 1192 asrs r2, r2, #6
8000350: 428b cmp r3, r1
8000352: d308 bcc.n 8000366 <__divsi3+0x14a>
8000354: 0189 lsls r1, r1, #6
8000356: 1192 asrs r2, r2, #6
8000358: 428b cmp r3, r1
800035a: d304 bcc.n 8000366 <__divsi3+0x14a>
800035c: 0189 lsls r1, r1, #6
800035e: d03a beq.n 80003d6 <__divsi3+0x1ba>
8000360: 1192 asrs r2, r2, #6
8000362: e000 b.n 8000366 <__divsi3+0x14a>
8000364: 0989 lsrs r1, r1, #6
8000366: 09c3 lsrs r3, r0, #7
8000368: 428b cmp r3, r1
800036a: d301 bcc.n 8000370 <__divsi3+0x154>
800036c: 01cb lsls r3, r1, #7
800036e: 1ac0 subs r0, r0, r3
8000370: 4152 adcs r2, r2
8000372: 0983 lsrs r3, r0, #6
8000374: 428b cmp r3, r1
8000376: d301 bcc.n 800037c <__divsi3+0x160>
8000378: 018b lsls r3, r1, #6
800037a: 1ac0 subs r0, r0, r3
800037c: 4152 adcs r2, r2
800037e: 0943 lsrs r3, r0, #5
8000380: 428b cmp r3, r1
8000382: d301 bcc.n 8000388 <__divsi3+0x16c>
8000384: 014b lsls r3, r1, #5
8000386: 1ac0 subs r0, r0, r3
8000388: 4152 adcs r2, r2
800038a: 0903 lsrs r3, r0, #4
800038c: 428b cmp r3, r1
800038e: d301 bcc.n 8000394 <__divsi3+0x178>
8000390: 010b lsls r3, r1, #4
8000392: 1ac0 subs r0, r0, r3
8000394: 4152 adcs r2, r2
8000396: 08c3 lsrs r3, r0, #3
8000398: 428b cmp r3, r1
800039a: d301 bcc.n 80003a0 <__divsi3+0x184>
800039c: 00cb lsls r3, r1, #3
800039e: 1ac0 subs r0, r0, r3
80003a0: 4152 adcs r2, r2
80003a2: 0883 lsrs r3, r0, #2
80003a4: 428b cmp r3, r1
80003a6: d301 bcc.n 80003ac <__divsi3+0x190>
80003a8: 008b lsls r3, r1, #2
80003aa: 1ac0 subs r0, r0, r3
80003ac: 4152 adcs r2, r2
80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148>
80003b0: 0843 lsrs r3, r0, #1
80003b2: 428b cmp r3, r1
80003b4: d301 bcc.n 80003ba <__divsi3+0x19e>
80003b6: 004b lsls r3, r1, #1
80003b8: 1ac0 subs r0, r0, r3
80003ba: 4152 adcs r2, r2
80003bc: 1a41 subs r1, r0, r1
80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6>
80003c0: 4601 mov r1, r0
80003c2: 4663 mov r3, ip
80003c4: 4152 adcs r2, r2
80003c6: 105b asrs r3, r3, #1
80003c8: 4610 mov r0, r2
80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4>
80003cc: 4240 negs r0, r0
80003ce: 2b00 cmp r3, #0
80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8>
80003d2: 4249 negs r1, r1
80003d4: 4770 bx lr
80003d6: 4663 mov r3, ip
80003d8: 105b asrs r3, r3, #1
80003da: d300 bcc.n 80003de <__divsi3+0x1c2>
80003dc: 4240 negs r0, r0
80003de: b501 push {r0, lr}
80003e0: 2000 movs r0, #0
80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0>
80003e6: bd02 pop {r1, pc}
080003e8 <__aeabi_idivmod>:
80003e8: 2900 cmp r1, #0
80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2>
80003ec: e716 b.n 800021c <__divsi3>
80003ee: 4770 bx lr
080003f0 <__aeabi_idiv0>:
80003f0: 4770 bx lr
80003f2: 46c0 nop ; (mov r8, r8)
080003f4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80003f4: b580 push {r7, lr}
80003f6: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80003f8: f000 fa62 bl 80008c0 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80003fc: f000 f809 bl 8000412 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000400: f000 f8e4 bl 80005cc <MX_GPIO_Init>
MX_ADC_Init();
8000404: f000 f856 bl 80004b4 <MX_ADC_Init>
MX_TIM14_Init();
8000408: f000 f8bc bl 8000584 <MX_TIM14_Init>
/* USER CODE BEGIN 2 */
my_code();
800040c: f002 fcc4 bl 8002d98 <my_code>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000410: e7fe b.n 8000410 <main+0x1c>
08000412 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000412: b590 push {r4, r7, lr}
8000414: b091 sub sp, #68 ; 0x44
8000416: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000418: 2410 movs r4, #16
800041a: 193b adds r3, r7, r4
800041c: 0018 movs r0, r3
800041e: 2330 movs r3, #48 ; 0x30
8000420: 001a movs r2, r3
8000422: 2100 movs r1, #0
8000424: f003 f9ce bl 80037c4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000428: 003b movs r3, r7
800042a: 0018 movs r0, r3
800042c: 2310 movs r3, #16
800042e: 001a movs r2, r3
8000430: 2100 movs r1, #0
8000432: f003 f9c7 bl 80037c4 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14;
8000436: 0021 movs r1, r4
8000438: 187b adds r3, r7, r1
800043a: 2212 movs r2, #18
800043c: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
800043e: 187b adds r3, r7, r1
8000440: 2201 movs r2, #1
8000442: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
8000444: 187b adds r3, r7, r1
8000446: 2201 movs r2, #1
8000448: 615a str r2, [r3, #20]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800044a: 187b adds r3, r7, r1
800044c: 2210 movs r2, #16
800044e: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSI14CalibrationValue = 16;
8000450: 187b adds r3, r7, r1
8000452: 2210 movs r2, #16
8000454: 619a str r2, [r3, #24]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000456: 187b adds r3, r7, r1
8000458: 2202 movs r2, #2
800045a: 621a str r2, [r3, #32]
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
800045c: 187b adds r3, r7, r1
800045e: 2200 movs r2, #0
8000460: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
8000462: 187b adds r3, r7, r1
8000464: 22a0 movs r2, #160 ; 0xa0
8000466: 0392 lsls r2, r2, #14
8000468: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
800046a: 187b adds r3, r7, r1
800046c: 2200 movs r2, #0
800046e: 62da str r2, [r3, #44] ; 0x2c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000470: 187b adds r3, r7, r1
8000472: 0018 movs r0, r3
8000474: f001 f9dc bl 8001830 <HAL_RCC_OscConfig>
8000478: 1e03 subs r3, r0, #0
800047a: d001 beq.n 8000480 <SystemClock_Config+0x6e>
{
Error_Handler();
800047c: f000 f92c bl 80006d8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000480: 003b movs r3, r7
8000482: 2207 movs r2, #7
8000484: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000486: 003b movs r3, r7
8000488: 2202 movs r2, #2
800048a: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800048c: 003b movs r3, r7
800048e: 2200 movs r2, #0
8000490: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000492: 003b movs r3, r7
8000494: 2200 movs r2, #0
8000496: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
8000498: 003b movs r3, r7
800049a: 2101 movs r1, #1
800049c: 0018 movs r0, r3
800049e: f001 fce1 bl 8001e64 <HAL_RCC_ClockConfig>
80004a2: 1e03 subs r3, r0, #0
80004a4: d001 beq.n 80004aa <SystemClock_Config+0x98>
{
Error_Handler();
80004a6: f000 f917 bl 80006d8 <Error_Handler>
}
}
80004aa: 46c0 nop ; (mov r8, r8)
80004ac: 46bd mov sp, r7
80004ae: b011 add sp, #68 ; 0x44
80004b0: bd90 pop {r4, r7, pc}
...
080004b4 <MX_ADC_Init>:
* @brief ADC Initialization Function
* @param None
* @retval None
*/
static void MX_ADC_Init(void)
{
80004b4: b580 push {r7, lr}
80004b6: b084 sub sp, #16
80004b8: af00 add r7, sp, #0
/* USER CODE BEGIN ADC_Init 0 */
/* USER CODE END ADC_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80004ba: 1d3b adds r3, r7, #4
80004bc: 0018 movs r0, r3
80004be: 230c movs r3, #12
80004c0: 001a movs r2, r3
80004c2: 2100 movs r1, #0
80004c4: f003 f97e bl 80037c4 <memset>
/* USER CODE BEGIN ADC_Init 1 */
/* USER CODE END ADC_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc.Instance = ADC1;
80004c8: 4b2c ldr r3, [pc, #176] ; (800057c <MX_ADC_Init+0xc8>)
80004ca: 4a2d ldr r2, [pc, #180] ; (8000580 <MX_ADC_Init+0xcc>)
80004cc: 601a str r2, [r3, #0]
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
80004ce: 4b2b ldr r3, [pc, #172] ; (800057c <MX_ADC_Init+0xc8>)
80004d0: 2200 movs r2, #0
80004d2: 605a str r2, [r3, #4]
hadc.Init.Resolution = ADC_RESOLUTION_12B;
80004d4: 4b29 ldr r3, [pc, #164] ; (800057c <MX_ADC_Init+0xc8>)
80004d6: 2200 movs r2, #0
80004d8: 609a str r2, [r3, #8]
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80004da: 4b28 ldr r3, [pc, #160] ; (800057c <MX_ADC_Init+0xc8>)
80004dc: 2200 movs r2, #0
80004de: 60da str r2, [r3, #12]
hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
80004e0: 4b26 ldr r3, [pc, #152] ; (800057c <MX_ADC_Init+0xc8>)
80004e2: 2201 movs r2, #1
80004e4: 611a str r2, [r3, #16]
hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
80004e6: 4b25 ldr r3, [pc, #148] ; (800057c <MX_ADC_Init+0xc8>)
80004e8: 2204 movs r2, #4
80004ea: 615a str r2, [r3, #20]
hadc.Init.LowPowerAutoWait = DISABLE;
80004ec: 4b23 ldr r3, [pc, #140] ; (800057c <MX_ADC_Init+0xc8>)
80004ee: 2200 movs r2, #0
80004f0: 761a strb r2, [r3, #24]
hadc.Init.LowPowerAutoPowerOff = DISABLE;
80004f2: 4b22 ldr r3, [pc, #136] ; (800057c <MX_ADC_Init+0xc8>)
80004f4: 2200 movs r2, #0
80004f6: 765a strb r2, [r3, #25]
hadc.Init.ContinuousConvMode = DISABLE;
80004f8: 4b20 ldr r3, [pc, #128] ; (800057c <MX_ADC_Init+0xc8>)
80004fa: 2200 movs r2, #0
80004fc: 769a strb r2, [r3, #26]
hadc.Init.DiscontinuousConvMode = DISABLE;
80004fe: 4b1f ldr r3, [pc, #124] ; (800057c <MX_ADC_Init+0xc8>)
8000500: 2200 movs r2, #0
8000502: 76da strb r2, [r3, #27]
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000504: 4b1d ldr r3, [pc, #116] ; (800057c <MX_ADC_Init+0xc8>)
8000506: 22c2 movs r2, #194 ; 0xc2
8000508: 32ff adds r2, #255 ; 0xff
800050a: 61da str r2, [r3, #28]
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800050c: 4b1b ldr r3, [pc, #108] ; (800057c <MX_ADC_Init+0xc8>)
800050e: 2200 movs r2, #0
8000510: 621a str r2, [r3, #32]
hadc.Init.DMAContinuousRequests = DISABLE;
8000512: 4b1a ldr r3, [pc, #104] ; (800057c <MX_ADC_Init+0xc8>)
8000514: 2224 movs r2, #36 ; 0x24
8000516: 2100 movs r1, #0
8000518: 5499 strb r1, [r3, r2]
hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
800051a: 4b18 ldr r3, [pc, #96] ; (800057c <MX_ADC_Init+0xc8>)
800051c: 2201 movs r2, #1
800051e: 629a str r2, [r3, #40] ; 0x28
if (HAL_ADC_Init(&hadc) != HAL_OK)
8000520: 4b16 ldr r3, [pc, #88] ; (800057c <MX_ADC_Init+0xc8>)
8000522: 0018 movs r0, r3
8000524: f000 fa30 bl 8000988 <HAL_ADC_Init>
8000528: 1e03 subs r3, r0, #0
800052a: d001 beq.n 8000530 <MX_ADC_Init+0x7c>
{
Error_Handler();
800052c: f000 f8d4 bl 80006d8 <Error_Handler>
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000530: 1d3b adds r3, r7, #4
8000532: 2200 movs r2, #0
8000534: 601a str r2, [r3, #0]
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
8000536: 1d3b adds r3, r7, #4
8000538: 2280 movs r2, #128 ; 0x80
800053a: 0152 lsls r2, r2, #5
800053c: 605a str r2, [r3, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
800053e: 1d3b adds r3, r7, #4
8000540: 2280 movs r2, #128 ; 0x80
8000542: 0552 lsls r2, r2, #21
8000544: 609a str r2, [r3, #8]
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
8000546: 1d3a adds r2, r7, #4
8000548: 4b0c ldr r3, [pc, #48] ; (800057c <MX_ADC_Init+0xc8>)
800054a: 0011 movs r1, r2
800054c: 0018 movs r0, r3
800054e: f000 fc93 bl 8000e78 <HAL_ADC_ConfigChannel>
8000552: 1e03 subs r3, r0, #0
8000554: d001 beq.n 800055a <MX_ADC_Init+0xa6>
{
Error_Handler();
8000556: f000 f8bf bl 80006d8 <Error_Handler>
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_1;
800055a: 1d3b adds r3, r7, #4
800055c: 2201 movs r2, #1
800055e: 601a str r2, [r3, #0]
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
8000560: 1d3a adds r2, r7, #4
8000562: 4b06 ldr r3, [pc, #24] ; (800057c <MX_ADC_Init+0xc8>)
8000564: 0011 movs r1, r2
8000566: 0018 movs r0, r3
8000568: f000 fc86 bl 8000e78 <HAL_ADC_ConfigChannel>
800056c: 1e03 subs r3, r0, #0
800056e: d001 beq.n 8000574 <MX_ADC_Init+0xc0>
{
Error_Handler();
8000570: f000 f8b2 bl 80006d8 <Error_Handler>
}
/* USER CODE BEGIN ADC_Init 2 */
/* USER CODE END ADC_Init 2 */
}
8000574: 46c0 nop ; (mov r8, r8)
8000576: 46bd mov sp, r7
8000578: b004 add sp, #16
800057a: bd80 pop {r7, pc}
800057c: 20000094 .word 0x20000094
8000580: 40012400 .word 0x40012400
08000584 <MX_TIM14_Init>:
* @brief TIM14 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM14_Init(void)
{
8000584: b580 push {r7, lr}
8000586: af00 add r7, sp, #0
/* USER CODE END TIM14_Init 0 */
/* USER CODE BEGIN TIM14_Init 1 */
/* USER CODE END TIM14_Init 1 */
htim14.Instance = TIM14;
8000588: 4b0e ldr r3, [pc, #56] ; (80005c4 <MX_TIM14_Init+0x40>)
800058a: 4a0f ldr r2, [pc, #60] ; (80005c8 <MX_TIM14_Init+0x44>)
800058c: 601a str r2, [r3, #0]
htim14.Init.Prescaler = 48-1;
800058e: 4b0d ldr r3, [pc, #52] ; (80005c4 <MX_TIM14_Init+0x40>)
8000590: 222f movs r2, #47 ; 0x2f
8000592: 605a str r2, [r3, #4]
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
8000594: 4b0b ldr r3, [pc, #44] ; (80005c4 <MX_TIM14_Init+0x40>)
8000596: 2200 movs r2, #0
8000598: 609a str r2, [r3, #8]
htim14.Init.Period = 100-1;
800059a: 4b0a ldr r3, [pc, #40] ; (80005c4 <MX_TIM14_Init+0x40>)
800059c: 2263 movs r2, #99 ; 0x63
800059e: 60da str r2, [r3, #12]
htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80005a0: 4b08 ldr r3, [pc, #32] ; (80005c4 <MX_TIM14_Init+0x40>)
80005a2: 2200 movs r2, #0
80005a4: 611a str r2, [r3, #16]
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80005a6: 4b07 ldr r3, [pc, #28] ; (80005c4 <MX_TIM14_Init+0x40>)
80005a8: 2200 movs r2, #0
80005aa: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
80005ac: 4b05 ldr r3, [pc, #20] ; (80005c4 <MX_TIM14_Init+0x40>)
80005ae: 0018 movs r0, r3
80005b0: f001 fd8a bl 80020c8 <HAL_TIM_Base_Init>
80005b4: 1e03 subs r3, r0, #0
80005b6: d001 beq.n 80005bc <MX_TIM14_Init+0x38>
{
Error_Handler();
80005b8: f000 f88e bl 80006d8 <Error_Handler>
}
/* USER CODE BEGIN TIM14_Init 2 */
/* USER CODE END TIM14_Init 2 */
}
80005bc: 46c0 nop ; (mov r8, r8)
80005be: 46bd mov sp, r7
80005c0: bd80 pop {r7, pc}
80005c2: 46c0 nop ; (mov r8, r8)
80005c4: 2000004c .word 0x2000004c
80005c8: 40002000 .word 0x40002000
080005cc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80005cc: b590 push {r4, r7, lr}
80005ce: b089 sub sp, #36 ; 0x24
80005d0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80005d2: 240c movs r4, #12
80005d4: 193b adds r3, r7, r4
80005d6: 0018 movs r0, r3
80005d8: 2314 movs r3, #20
80005da: 001a movs r2, r3
80005dc: 2100 movs r1, #0
80005de: f003 f8f1 bl 80037c4 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80005e2: 4b3b ldr r3, [pc, #236] ; (80006d0 <MX_GPIO_Init+0x104>)
80005e4: 695a ldr r2, [r3, #20]
80005e6: 4b3a ldr r3, [pc, #232] ; (80006d0 <MX_GPIO_Init+0x104>)
80005e8: 2180 movs r1, #128 ; 0x80
80005ea: 03c9 lsls r1, r1, #15
80005ec: 430a orrs r2, r1
80005ee: 615a str r2, [r3, #20]
80005f0: 4b37 ldr r3, [pc, #220] ; (80006d0 <MX_GPIO_Init+0x104>)
80005f2: 695a ldr r2, [r3, #20]
80005f4: 2380 movs r3, #128 ; 0x80
80005f6: 03db lsls r3, r3, #15
80005f8: 4013 ands r3, r2
80005fa: 60bb str r3, [r7, #8]
80005fc: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80005fe: 4b34 ldr r3, [pc, #208] ; (80006d0 <MX_GPIO_Init+0x104>)
8000600: 695a ldr r2, [r3, #20]
8000602: 4b33 ldr r3, [pc, #204] ; (80006d0 <MX_GPIO_Init+0x104>)
8000604: 2180 movs r1, #128 ; 0x80
8000606: 0289 lsls r1, r1, #10
8000608: 430a orrs r2, r1
800060a: 615a str r2, [r3, #20]
800060c: 4b30 ldr r3, [pc, #192] ; (80006d0 <MX_GPIO_Init+0x104>)
800060e: 695a ldr r2, [r3, #20]
8000610: 2380 movs r3, #128 ; 0x80
8000612: 029b lsls r3, r3, #10
8000614: 4013 ands r3, r2
8000616: 607b str r3, [r7, #4]
8000618: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin
800061a: 23b9 movs r3, #185 ; 0xb9
800061c: 0099 lsls r1, r3, #2
800061e: 2390 movs r3, #144 ; 0x90
8000620: 05db lsls r3, r3, #23
8000622: 2200 movs r2, #0
8000624: 0018 movs r0, r3
8000626: f001 f8ca bl 80017be <HAL_GPIO_WritePin>
|HC595_SLK2_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : MOT_IN1_Pin MOT_IN2_Pin */
GPIO_InitStruct.Pin = MOT_IN1_Pin|MOT_IN2_Pin;
800062a: 193b adds r3, r7, r4
800062c: 2203 movs r2, #3
800062e: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000630: 193b adds r3, r7, r4
8000632: 2200 movs r2, #0
8000634: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8000636: 193b adds r3, r7, r4
8000638: 2202 movs r2, #2
800063a: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
800063c: 193b adds r3, r7, r4
800063e: 4a25 ldr r2, [pc, #148] ; (80006d4 <MX_GPIO_Init+0x108>)
8000640: 0019 movs r1, r3
8000642: 0010 movs r0, r2
8000644: f000 ff2e bl 80014a4 <HAL_GPIO_Init>
/*Configure GPIO pins : U_T_Pin HC595_DLK_Pin HC595_SLK_Pin HC595_RLK_Pin
HC595_SLK2_Pin */
GPIO_InitStruct.Pin = U_T_Pin|HC595_DLK_Pin|HC595_SLK_Pin|HC595_RLK_Pin
8000648: 0021 movs r1, r4
800064a: 187b adds r3, r7, r1
800064c: 22b9 movs r2, #185 ; 0xb9
800064e: 0092 lsls r2, r2, #2
8000650: 601a str r2, [r3, #0]
|HC595_SLK2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000652: 000c movs r4, r1
8000654: 193b adds r3, r7, r4
8000656: 2201 movs r2, #1
8000658: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
800065a: 193b adds r3, r7, r4
800065c: 2202 movs r2, #2
800065e: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000660: 193b adds r3, r7, r4
8000662: 2203 movs r2, #3
8000664: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000666: 193a adds r2, r7, r4
8000668: 2390 movs r3, #144 ; 0x90
800066a: 05db lsls r3, r3, #23
800066c: 0011 movs r1, r2
800066e: 0018 movs r0, r3
8000670: f000 ff18 bl 80014a4 <HAL_GPIO_Init>
/*Configure GPIO pin : infeaed_Pin */
GPIO_InitStruct.Pin = infeaed_Pin;
8000674: 193b adds r3, r7, r4
8000676: 2208 movs r2, #8
8000678: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
800067a: 193b adds r3, r7, r4
800067c: 22c4 movs r2, #196 ; 0xc4
800067e: 0392 lsls r2, r2, #14
8000680: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000682: 193b adds r3, r7, r4
8000684: 2201 movs r2, #1
8000686: 609a str r2, [r3, #8]
HAL_GPIO_Init(infeaed_GPIO_Port, &GPIO_InitStruct);
8000688: 193a adds r2, r7, r4
800068a: 2390 movs r3, #144 ; 0x90
800068c: 05db lsls r3, r3, #23
800068e: 0011 movs r1, r2
8000690: 0018 movs r0, r3
8000692: f000 ff07 bl 80014a4 <HAL_GPIO_Init>
/*Configure GPIO pin : I_R_Pin */
GPIO_InitStruct.Pin = I_R_Pin;
8000696: 193b adds r3, r7, r4
8000698: 2210 movs r2, #16
800069a: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800069c: 193b adds r3, r7, r4
800069e: 2200 movs r2, #0
80006a0: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
80006a2: 193b adds r3, r7, r4
80006a4: 2202 movs r2, #2
80006a6: 609a str r2, [r3, #8]
HAL_GPIO_Init(I_R_GPIO_Port, &GPIO_InitStruct);
80006a8: 193a adds r2, r7, r4
80006aa: 2390 movs r3, #144 ; 0x90
80006ac: 05db lsls r3, r3, #23
80006ae: 0011 movs r1, r2
80006b0: 0018 movs r0, r3
80006b2: f000 fef7 bl 80014a4 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI2_3_IRQn, 0, 0);
80006b6: 2200 movs r2, #0
80006b8: 2100 movs r1, #0
80006ba: 2006 movs r0, #6
80006bc: f000 fec0 bl 8001440 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI2_3_IRQn);
80006c0: 2006 movs r0, #6
80006c2: f000 fed2 bl 800146a <HAL_NVIC_EnableIRQ>
}
80006c6: 46c0 nop ; (mov r8, r8)
80006c8: 46bd mov sp, r7
80006ca: b009 add sp, #36 ; 0x24
80006cc: bd90 pop {r4, r7, pc}
80006ce: 46c0 nop ; (mov r8, r8)
80006d0: 40021000 .word 0x40021000
80006d4: 48001400 .word 0x48001400
080006d8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80006d8: b580 push {r7, lr}
80006da: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80006dc: b672 cpsid i
}
80006de: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80006e0: e7fe b.n 80006e0 <Error_Handler+0x8>
...
080006e4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80006e4: b580 push {r7, lr}
80006e6: b082 sub sp, #8
80006e8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80006ea: 4b0f ldr r3, [pc, #60] ; (8000728 <HAL_MspInit+0x44>)
80006ec: 699a ldr r2, [r3, #24]
80006ee: 4b0e ldr r3, [pc, #56] ; (8000728 <HAL_MspInit+0x44>)
80006f0: 2101 movs r1, #1
80006f2: 430a orrs r2, r1
80006f4: 619a str r2, [r3, #24]
80006f6: 4b0c ldr r3, [pc, #48] ; (8000728 <HAL_MspInit+0x44>)
80006f8: 699b ldr r3, [r3, #24]
80006fa: 2201 movs r2, #1
80006fc: 4013 ands r3, r2
80006fe: 607b str r3, [r7, #4]
8000700: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000702: 4b09 ldr r3, [pc, #36] ; (8000728 <HAL_MspInit+0x44>)
8000704: 69da ldr r2, [r3, #28]
8000706: 4b08 ldr r3, [pc, #32] ; (8000728 <HAL_MspInit+0x44>)
8000708: 2180 movs r1, #128 ; 0x80
800070a: 0549 lsls r1, r1, #21
800070c: 430a orrs r2, r1
800070e: 61da str r2, [r3, #28]
8000710: 4b05 ldr r3, [pc, #20] ; (8000728 <HAL_MspInit+0x44>)
8000712: 69da ldr r2, [r3, #28]
8000714: 2380 movs r3, #128 ; 0x80
8000716: 055b lsls r3, r3, #21
8000718: 4013 ands r3, r2
800071a: 603b str r3, [r7, #0]
800071c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800071e: 46c0 nop ; (mov r8, r8)
8000720: 46bd mov sp, r7
8000722: b002 add sp, #8
8000724: bd80 pop {r7, pc}
8000726: 46c0 nop ; (mov r8, r8)
8000728: 40021000 .word 0x40021000
0800072c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
800072c: b590 push {r4, r7, lr}
800072e: b08b sub sp, #44 ; 0x2c
8000730: af00 add r7, sp, #0
8000732: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000734: 2414 movs r4, #20
8000736: 193b adds r3, r7, r4
8000738: 0018 movs r0, r3
800073a: 2314 movs r3, #20
800073c: 001a movs r2, r3
800073e: 2100 movs r1, #0
8000740: f003 f840 bl 80037c4 <memset>
if(hadc->Instance==ADC1)
8000744: 687b ldr r3, [r7, #4]
8000746: 681b ldr r3, [r3, #0]
8000748: 4a19 ldr r2, [pc, #100] ; (80007b0 <HAL_ADC_MspInit+0x84>)
800074a: 4293 cmp r3, r2
800074c: d12b bne.n 80007a6 <HAL_ADC_MspInit+0x7a>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
800074e: 4b19 ldr r3, [pc, #100] ; (80007b4 <HAL_ADC_MspInit+0x88>)
8000750: 699a ldr r2, [r3, #24]
8000752: 4b18 ldr r3, [pc, #96] ; (80007b4 <HAL_ADC_MspInit+0x88>)
8000754: 2180 movs r1, #128 ; 0x80
8000756: 0089 lsls r1, r1, #2
8000758: 430a orrs r2, r1
800075a: 619a str r2, [r3, #24]
800075c: 4b15 ldr r3, [pc, #84] ; (80007b4 <HAL_ADC_MspInit+0x88>)
800075e: 699a ldr r2, [r3, #24]
8000760: 2380 movs r3, #128 ; 0x80
8000762: 009b lsls r3, r3, #2
8000764: 4013 ands r3, r2
8000766: 613b str r3, [r7, #16]
8000768: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800076a: 4b12 ldr r3, [pc, #72] ; (80007b4 <HAL_ADC_MspInit+0x88>)
800076c: 695a ldr r2, [r3, #20]
800076e: 4b11 ldr r3, [pc, #68] ; (80007b4 <HAL_ADC_MspInit+0x88>)
8000770: 2180 movs r1, #128 ; 0x80
8000772: 0289 lsls r1, r1, #10
8000774: 430a orrs r2, r1
8000776: 615a str r2, [r3, #20]
8000778: 4b0e ldr r3, [pc, #56] ; (80007b4 <HAL_ADC_MspInit+0x88>)
800077a: 695a ldr r2, [r3, #20]
800077c: 2380 movs r3, #128 ; 0x80
800077e: 029b lsls r3, r3, #10
8000780: 4013 ands r3, r2
8000782: 60fb str r3, [r7, #12]
8000784: 68fb ldr r3, [r7, #12]
/**ADC GPIO Configuration
PA0 ------> ADC_IN0
PA1 ------> ADC_IN1
*/
GPIO_InitStruct.Pin = ADC_CH0_Pin|ADC_CH1_Pin;
8000786: 193b adds r3, r7, r4
8000788: 2203 movs r2, #3
800078a: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800078c: 193b adds r3, r7, r4
800078e: 2203 movs r2, #3
8000790: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000792: 193b adds r3, r7, r4
8000794: 2200 movs r2, #0
8000796: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000798: 193a adds r2, r7, r4
800079a: 2390 movs r3, #144 ; 0x90
800079c: 05db lsls r3, r3, #23
800079e: 0011 movs r1, r2
80007a0: 0018 movs r0, r3
80007a2: f000 fe7f bl 80014a4 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
80007a6: 46c0 nop ; (mov r8, r8)
80007a8: 46bd mov sp, r7
80007aa: b00b add sp, #44 ; 0x2c
80007ac: bd90 pop {r4, r7, pc}
80007ae: 46c0 nop ; (mov r8, r8)
80007b0: 40012400 .word 0x40012400
80007b4: 40021000 .word 0x40021000
080007b8 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
80007b8: b580 push {r7, lr}
80007ba: b084 sub sp, #16
80007bc: af00 add r7, sp, #0
80007be: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM14)
80007c0: 687b ldr r3, [r7, #4]
80007c2: 681b ldr r3, [r3, #0]
80007c4: 4a0e ldr r2, [pc, #56] ; (8000800 <HAL_TIM_Base_MspInit+0x48>)
80007c6: 4293 cmp r3, r2
80007c8: d115 bne.n 80007f6 <HAL_TIM_Base_MspInit+0x3e>
{
/* USER CODE BEGIN TIM14_MspInit 0 */
/* USER CODE END TIM14_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM14_CLK_ENABLE();
80007ca: 4b0e ldr r3, [pc, #56] ; (8000804 <HAL_TIM_Base_MspInit+0x4c>)
80007cc: 69da ldr r2, [r3, #28]
80007ce: 4b0d ldr r3, [pc, #52] ; (8000804 <HAL_TIM_Base_MspInit+0x4c>)
80007d0: 2180 movs r1, #128 ; 0x80
80007d2: 0049 lsls r1, r1, #1
80007d4: 430a orrs r2, r1
80007d6: 61da str r2, [r3, #28]
80007d8: 4b0a ldr r3, [pc, #40] ; (8000804 <HAL_TIM_Base_MspInit+0x4c>)
80007da: 69da ldr r2, [r3, #28]
80007dc: 2380 movs r3, #128 ; 0x80
80007de: 005b lsls r3, r3, #1
80007e0: 4013 ands r3, r2
80007e2: 60fb str r3, [r7, #12]
80007e4: 68fb ldr r3, [r7, #12]
/* TIM14 interrupt Init */
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
80007e6: 2200 movs r2, #0
80007e8: 2100 movs r1, #0
80007ea: 2013 movs r0, #19
80007ec: f000 fe28 bl 8001440 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM14_IRQn);
80007f0: 2013 movs r0, #19
80007f2: f000 fe3a bl 800146a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM14_MspInit 1 */
/* USER CODE END TIM14_MspInit 1 */
}
}
80007f6: 46c0 nop ; (mov r8, r8)
80007f8: 46bd mov sp, r7
80007fa: b004 add sp, #16
80007fc: bd80 pop {r7, pc}
80007fe: 46c0 nop ; (mov r8, r8)
8000800: 40002000 .word 0x40002000
8000804: 40021000 .word 0x40021000
08000808 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000808: b580 push {r7, lr}
800080a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800080c: e7fe b.n 800080c <NMI_Handler+0x4>
0800080e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800080e: b580 push {r7, lr}
8000810: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000812: e7fe b.n 8000812 <HardFault_Handler+0x4>
08000814 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000814: b580 push {r7, lr}
8000816: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000818: 46c0 nop ; (mov r8, r8)
800081a: 46bd mov sp, r7
800081c: bd80 pop {r7, pc}
0800081e <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800081e: b580 push {r7, lr}
8000820: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000822: 46c0 nop ; (mov r8, r8)
8000824: 46bd mov sp, r7
8000826: bd80 pop {r7, pc}
08000828 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000828: b580 push {r7, lr}
800082a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800082c: f000 f890 bl 8000950 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000830: 46c0 nop ; (mov r8, r8)
8000832: 46bd mov sp, r7
8000834: bd80 pop {r7, pc}
08000836 <EXTI2_3_IRQHandler>:
/**
* @brief This function handles EXTI line 2 and 3 interrupts.
*/
void EXTI2_3_IRQHandler(void)
{
8000836: b580 push {r7, lr}
8000838: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI2_3_IRQn 0 */
/* USER CODE END EXTI2_3_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
800083a: 2008 movs r0, #8
800083c: f000 ffdc bl 80017f8 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI2_3_IRQn 1 */
/* USER CODE END EXTI2_3_IRQn 1 */
}
8000840: 46c0 nop ; (mov r8, r8)
8000842: 46bd mov sp, r7
8000844: bd80 pop {r7, pc}
...
08000848 <TIM14_IRQHandler>:
/**
* @brief This function handles TIM14 global interrupt.
*/
void TIM14_IRQHandler(void)
{
8000848: b580 push {r7, lr}
800084a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM14_IRQn 0 */
/* USER CODE END TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim14);
800084c: 4b03 ldr r3, [pc, #12] ; (800085c <TIM14_IRQHandler+0x14>)
800084e: 0018 movs r0, r3
8000850: f001 fcd0 bl 80021f4 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM14_IRQn 1 */
/* USER CODE END TIM14_IRQn 1 */
}
8000854: 46c0 nop ; (mov r8, r8)
8000856: 46bd mov sp, r7
8000858: bd80 pop {r7, pc}
800085a: 46c0 nop ; (mov r8, r8)
800085c: 2000004c .word 0x2000004c
08000860 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8000860: b580 push {r7, lr}
8000862: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
8000864: 46c0 nop ; (mov r8, r8)
8000866: 46bd mov sp, r7
8000868: bd80 pop {r7, pc}
...
0800086c <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
800086c: 480d ldr r0, [pc, #52] ; (80008a4 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
800086e: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000870: 480d ldr r0, [pc, #52] ; (80008a8 <LoopForever+0x6>)
ldr r1, =_edata
8000872: 490e ldr r1, [pc, #56] ; (80008ac <LoopForever+0xa>)
ldr r2, =_sidata
8000874: 4a0e ldr r2, [pc, #56] ; (80008b0 <LoopForever+0xe>)
movs r3, #0
8000876: 2300 movs r3, #0
b LoopCopyDataInit
8000878: e002 b.n 8000880 <LoopCopyDataInit>
0800087a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800087a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800087c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800087e: 3304 adds r3, #4
08000880 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000880: 18c4 adds r4, r0, r3
cmp r4, r1
8000882: 428c cmp r4, r1
bcc CopyDataInit
8000884: d3f9 bcc.n 800087a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000886: 4a0b ldr r2, [pc, #44] ; (80008b4 <LoopForever+0x12>)
ldr r4, =_ebss
8000888: 4c0b ldr r4, [pc, #44] ; (80008b8 <LoopForever+0x16>)
movs r3, #0
800088a: 2300 movs r3, #0
b LoopFillZerobss
800088c: e001 b.n 8000892 <LoopFillZerobss>
0800088e <FillZerobss>:
FillZerobss:
str r3, [r2]
800088e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000890: 3204 adds r2, #4
08000892 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000892: 42a2 cmp r2, r4
bcc FillZerobss
8000894: d3fb bcc.n 800088e <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000896: f7ff ffe3 bl 8000860 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800089a: f002 ff6f bl 800377c <__libc_init_array>
/* Call the application's entry point.*/
bl main
800089e: f7ff fda9 bl 80003f4 <main>
080008a2 <LoopForever>:
LoopForever:
b LoopForever
80008a2: e7fe b.n 80008a2 <LoopForever>
ldr r0, =_estack
80008a4: 20001000 .word 0x20001000
ldr r0, =_sdata
80008a8: 20000000 .word 0x20000000
ldr r1, =_edata
80008ac: 2000000c .word 0x2000000c
ldr r2, =_sidata
80008b0: 08003850 .word 0x08003850
ldr r2, =_sbss
80008b4: 2000000c .word 0x2000000c
ldr r4, =_ebss
80008b8: 20000158 .word 0x20000158
080008bc <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80008bc: e7fe b.n 80008bc <ADC1_IRQHandler>
...
080008c0 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80008c0: b580 push {r7, lr}
80008c2: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80008c4: 4b07 ldr r3, [pc, #28] ; (80008e4 <HAL_Init+0x24>)
80008c6: 681a ldr r2, [r3, #0]
80008c8: 4b06 ldr r3, [pc, #24] ; (80008e4 <HAL_Init+0x24>)
80008ca: 2110 movs r1, #16
80008cc: 430a orrs r2, r1
80008ce: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80008d0: 2003 movs r0, #3
80008d2: f000 f809 bl 80008e8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80008d6: f7ff ff05 bl 80006e4 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80008da: 2300 movs r3, #0
}
80008dc: 0018 movs r0, r3
80008de: 46bd mov sp, r7
80008e0: bd80 pop {r7, pc}
80008e2: 46c0 nop ; (mov r8, r8)
80008e4: 40022000 .word 0x40022000
080008e8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80008e8: b590 push {r4, r7, lr}
80008ea: b083 sub sp, #12
80008ec: af00 add r7, sp, #0
80008ee: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80008f0: 4b14 ldr r3, [pc, #80] ; (8000944 <HAL_InitTick+0x5c>)
80008f2: 681c ldr r4, [r3, #0]
80008f4: 4b14 ldr r3, [pc, #80] ; (8000948 <HAL_InitTick+0x60>)
80008f6: 781b ldrb r3, [r3, #0]
80008f8: 0019 movs r1, r3
80008fa: 23fa movs r3, #250 ; 0xfa
80008fc: 0098 lsls r0, r3, #2
80008fe: f7ff fc03 bl 8000108 <__udivsi3>
8000902: 0003 movs r3, r0
8000904: 0019 movs r1, r3
8000906: 0020 movs r0, r4
8000908: f7ff fbfe bl 8000108 <__udivsi3>
800090c: 0003 movs r3, r0
800090e: 0018 movs r0, r3
8000910: f000 fdbb bl 800148a <HAL_SYSTICK_Config>
8000914: 1e03 subs r3, r0, #0
8000916: d001 beq.n 800091c <HAL_InitTick+0x34>
{
return HAL_ERROR;
8000918: 2301 movs r3, #1
800091a: e00f b.n 800093c <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800091c: 687b ldr r3, [r7, #4]
800091e: 2b03 cmp r3, #3
8000920: d80b bhi.n 800093a <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000922: 6879 ldr r1, [r7, #4]
8000924: 2301 movs r3, #1
8000926: 425b negs r3, r3
8000928: 2200 movs r2, #0
800092a: 0018 movs r0, r3
800092c: f000 fd88 bl 8001440 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000930: 4b06 ldr r3, [pc, #24] ; (800094c <HAL_InitTick+0x64>)
8000932: 687a ldr r2, [r7, #4]
8000934: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000936: 2300 movs r3, #0
8000938: e000 b.n 800093c <HAL_InitTick+0x54>
return HAL_ERROR;
800093a: 2301 movs r3, #1
}
800093c: 0018 movs r0, r3
800093e: 46bd mov sp, r7
8000940: b003 add sp, #12
8000942: bd90 pop {r4, r7, pc}
8000944: 20000000 .word 0x20000000
8000948: 20000008 .word 0x20000008
800094c: 20000004 .word 0x20000004
08000950 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000950: b580 push {r7, lr}
8000952: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000954: 4b05 ldr r3, [pc, #20] ; (800096c <HAL_IncTick+0x1c>)
8000956: 781b ldrb r3, [r3, #0]
8000958: 001a movs r2, r3
800095a: 4b05 ldr r3, [pc, #20] ; (8000970 <HAL_IncTick+0x20>)
800095c: 681b ldr r3, [r3, #0]
800095e: 18d2 adds r2, r2, r3
8000960: 4b03 ldr r3, [pc, #12] ; (8000970 <HAL_IncTick+0x20>)
8000962: 601a str r2, [r3, #0]
}
8000964: 46c0 nop ; (mov r8, r8)
8000966: 46bd mov sp, r7
8000968: bd80 pop {r7, pc}
800096a: 46c0 nop ; (mov r8, r8)
800096c: 20000008 .word 0x20000008
8000970: 200000d4 .word 0x200000d4
08000974 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000974: b580 push {r7, lr}
8000976: af00 add r7, sp, #0
return uwTick;
8000978: 4b02 ldr r3, [pc, #8] ; (8000984 <HAL_GetTick+0x10>)
800097a: 681b ldr r3, [r3, #0]
}
800097c: 0018 movs r0, r3
800097e: 46bd mov sp, r7
8000980: bd80 pop {r7, pc}
8000982: 46c0 nop ; (mov r8, r8)
8000984: 200000d4 .word 0x200000d4
08000988 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8000988: b580 push {r7, lr}
800098a: b084 sub sp, #16
800098c: af00 add r7, sp, #0
800098e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000990: 230f movs r3, #15
8000992: 18fb adds r3, r7, r3
8000994: 2200 movs r2, #0
8000996: 701a strb r2, [r3, #0]
uint32_t tmpCFGR1 = 0U;
8000998: 2300 movs r3, #0
800099a: 60bb str r3, [r7, #8]
/* Check ADC handle */
if(hadc == NULL)
800099c: 687b ldr r3, [r7, #4]
800099e: 2b00 cmp r3, #0
80009a0: d101 bne.n 80009a6 <HAL_ADC_Init+0x1e>
{
return HAL_ERROR;
80009a2: 2301 movs r3, #1
80009a4: e125 b.n 8000bf2 <HAL_ADC_Init+0x26a>
/* Refer to header of this file for more details on clock enabling procedure*/
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
/* - ADC voltage regulator enable */
if (hadc->State == HAL_ADC_STATE_RESET)
80009a6: 687b ldr r3, [r7, #4]
80009a8: 6b9b ldr r3, [r3, #56] ; 0x38
80009aa: 2b00 cmp r3, #0
80009ac: d10a bne.n 80009c4 <HAL_ADC_Init+0x3c>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
80009ae: 687b ldr r3, [r7, #4]
80009b0: 2200 movs r2, #0
80009b2: 63da str r2, [r3, #60] ; 0x3c
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
80009b4: 687b ldr r3, [r7, #4]
80009b6: 2234 movs r2, #52 ; 0x34
80009b8: 2100 movs r1, #0
80009ba: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80009bc: 687b ldr r3, [r7, #4]
80009be: 0018 movs r0, r3
80009c0: f7ff feb4 bl 800072c <HAL_ADC_MspInit>
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
/* and if there is no conversion on going on regular group (ADC can be */
/* enabled anyway, in case of call of this function to update a parameter */
/* on the fly). */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
80009c4: 687b ldr r3, [r7, #4]
80009c6: 6b9b ldr r3, [r3, #56] ; 0x38
80009c8: 2210 movs r2, #16
80009ca: 4013 ands r3, r2
80009cc: d000 beq.n 80009d0 <HAL_ADC_Init+0x48>
80009ce: e103 b.n 8000bd8 <HAL_ADC_Init+0x250>
80009d0: 230f movs r3, #15
80009d2: 18fb adds r3, r7, r3
80009d4: 781b ldrb r3, [r3, #0]
80009d6: 2b00 cmp r3, #0
80009d8: d000 beq.n 80009dc <HAL_ADC_Init+0x54>
80009da: e0fd b.n 8000bd8 <HAL_ADC_Init+0x250>
(tmp_hal_status == HAL_OK) &&
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
80009dc: 687b ldr r3, [r7, #4]
80009de: 681b ldr r3, [r3, #0]
80009e0: 689b ldr r3, [r3, #8]
80009e2: 2204 movs r2, #4
80009e4: 4013 ands r3, r2
(tmp_hal_status == HAL_OK) &&
80009e6: d000 beq.n 80009ea <HAL_ADC_Init+0x62>
80009e8: e0f6 b.n 8000bd8 <HAL_ADC_Init+0x250>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80009ea: 687b ldr r3, [r7, #4]
80009ec: 6b9b ldr r3, [r3, #56] ; 0x38
80009ee: 4a83 ldr r2, [pc, #524] ; (8000bfc <HAL_ADC_Init+0x274>)
80009f0: 4013 ands r3, r2
80009f2: 2202 movs r2, #2
80009f4: 431a orrs r2, r3
80009f6: 687b ldr r3, [r7, #4]
80009f8: 639a str r2, [r3, #56] ; 0x38
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - ADC clock mode */
/* - ADC clock prescaler */
/* - ADC resolution */
if (ADC_IS_ENABLE(hadc) == RESET)
80009fa: 687b ldr r3, [r7, #4]
80009fc: 681b ldr r3, [r3, #0]
80009fe: 689b ldr r3, [r3, #8]
8000a00: 2203 movs r2, #3
8000a02: 4013 ands r3, r2
8000a04: 2b01 cmp r3, #1
8000a06: d112 bne.n 8000a2e <HAL_ADC_Init+0xa6>
8000a08: 687b ldr r3, [r7, #4]
8000a0a: 681b ldr r3, [r3, #0]
8000a0c: 681b ldr r3, [r3, #0]
8000a0e: 2201 movs r2, #1
8000a10: 4013 ands r3, r2
8000a12: 2b01 cmp r3, #1
8000a14: d009 beq.n 8000a2a <HAL_ADC_Init+0xa2>
8000a16: 687b ldr r3, [r7, #4]
8000a18: 681b ldr r3, [r3, #0]
8000a1a: 68da ldr r2, [r3, #12]
8000a1c: 2380 movs r3, #128 ; 0x80
8000a1e: 021b lsls r3, r3, #8
8000a20: 401a ands r2, r3
8000a22: 2380 movs r3, #128 ; 0x80
8000a24: 021b lsls r3, r3, #8
8000a26: 429a cmp r2, r3
8000a28: d101 bne.n 8000a2e <HAL_ADC_Init+0xa6>
8000a2a: 2301 movs r3, #1
8000a2c: e000 b.n 8000a30 <HAL_ADC_Init+0xa8>
8000a2e: 2300 movs r3, #0
8000a30: 2b00 cmp r3, #0
8000a32: d116 bne.n 8000a62 <HAL_ADC_Init+0xda>
/* parameters): */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() ) */
/* Configuration of ADC resolution */
MODIFY_REG(hadc->Instance->CFGR1,
8000a34: 687b ldr r3, [r7, #4]
8000a36: 681b ldr r3, [r3, #0]
8000a38: 68db ldr r3, [r3, #12]
8000a3a: 2218 movs r2, #24
8000a3c: 4393 bics r3, r2
8000a3e: 0019 movs r1, r3
8000a40: 687b ldr r3, [r7, #4]
8000a42: 689a ldr r2, [r3, #8]
8000a44: 687b ldr r3, [r7, #4]
8000a46: 681b ldr r3, [r3, #0]
8000a48: 430a orrs r2, r1
8000a4a: 60da str r2, [r3, #12]
ADC_CFGR1_RES ,
hadc->Init.Resolution );
/* Configuration of ADC clock mode: clock source AHB or HSI with */
/* selectable prescaler */
MODIFY_REG(hadc->Instance->CFGR2 ,
8000a4c: 687b ldr r3, [r7, #4]
8000a4e: 681b ldr r3, [r3, #0]
8000a50: 691b ldr r3, [r3, #16]
8000a52: 009b lsls r3, r3, #2
8000a54: 0899 lsrs r1, r3, #2
8000a56: 687b ldr r3, [r7, #4]
8000a58: 685a ldr r2, [r3, #4]
8000a5a: 687b ldr r3, [r7, #4]
8000a5c: 681b ldr r3, [r3, #0]
8000a5e: 430a orrs r2, r1
8000a60: 611a str r2, [r3, #16]
/* - external trigger polarity */
/* - data alignment */
/* - resolution */
/* - scan direction */
/* - DMA continuous request */
hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN |
8000a62: 687b ldr r3, [r7, #4]
8000a64: 681b ldr r3, [r3, #0]
8000a66: 68da ldr r2, [r3, #12]
8000a68: 687b ldr r3, [r7, #4]
8000a6a: 681b ldr r3, [r3, #0]
8000a6c: 4964 ldr r1, [pc, #400] ; (8000c00 <HAL_ADC_Init+0x278>)
8000a6e: 400a ands r2, r1
8000a70: 60da str r2, [r3, #12]
ADC_CFGR1_EXTEN |
ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG );
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000a72: 687b ldr r3, [r7, #4]
8000a74: 7e1b ldrb r3, [r3, #24]
8000a76: 039a lsls r2, r3, #14
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8000a78: 687b ldr r3, [r7, #4]
8000a7a: 7e5b ldrb r3, [r3, #25]
8000a7c: 03db lsls r3, r3, #15
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000a7e: 431a orrs r2, r3
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000a80: 687b ldr r3, [r7, #4]
8000a82: 7e9b ldrb r3, [r3, #26]
8000a84: 035b lsls r3, r3, #13
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8000a86: 431a orrs r2, r3
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8000a88: 687b ldr r3, [r7, #4]
8000a8a: 6a9b ldr r3, [r3, #40] ; 0x28
8000a8c: 2b01 cmp r3, #1
8000a8e: d002 beq.n 8000a96 <HAL_ADC_Init+0x10e>
8000a90: 2380 movs r3, #128 ; 0x80
8000a92: 015b lsls r3, r3, #5
8000a94: e000 b.n 8000a98 <HAL_ADC_Init+0x110>
8000a96: 2300 movs r3, #0
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000a98: 431a orrs r2, r3
hadc->Init.DataAlign |
8000a9a: 687b ldr r3, [r7, #4]
8000a9c: 68db ldr r3, [r3, #12]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8000a9e: 431a orrs r2, r3
ADC_SCANDIR(hadc->Init.ScanConvMode) |
8000aa0: 687b ldr r3, [r7, #4]
8000aa2: 691b ldr r3, [r3, #16]
8000aa4: 2b02 cmp r3, #2
8000aa6: d101 bne.n 8000aac <HAL_ADC_Init+0x124>
8000aa8: 2304 movs r3, #4
8000aaa: e000 b.n 8000aae <HAL_ADC_Init+0x126>
8000aac: 2300 movs r3, #0
hadc->Init.DataAlign |
8000aae: 431a orrs r2, r3
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
8000ab0: 687b ldr r3, [r7, #4]
8000ab2: 2124 movs r1, #36 ; 0x24
8000ab4: 5c5b ldrb r3, [r3, r1]
8000ab6: 005b lsls r3, r3, #1
ADC_SCANDIR(hadc->Init.ScanConvMode) |
8000ab8: 4313 orrs r3, r2
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000aba: 68ba ldr r2, [r7, #8]
8000abc: 4313 orrs r3, r2
8000abe: 60bb str r3, [r7, #8]
/* Enable discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8000ac0: 687b ldr r3, [r7, #4]
8000ac2: 7edb ldrb r3, [r3, #27]
8000ac4: 2b01 cmp r3, #1
8000ac6: d115 bne.n 8000af4 <HAL_ADC_Init+0x16c>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8000ac8: 687b ldr r3, [r7, #4]
8000aca: 7e9b ldrb r3, [r3, #26]
8000acc: 2b00 cmp r3, #0
8000ace: d105 bne.n 8000adc <HAL_ADC_Init+0x154>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
8000ad0: 68bb ldr r3, [r7, #8]
8000ad2: 2280 movs r2, #128 ; 0x80
8000ad4: 0252 lsls r2, r2, #9
8000ad6: 4313 orrs r3, r2
8000ad8: 60bb str r3, [r7, #8]
8000ada: e00b b.n 8000af4 <HAL_ADC_Init+0x16c>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000adc: 687b ldr r3, [r7, #4]
8000ade: 6b9b ldr r3, [r3, #56] ; 0x38
8000ae0: 2220 movs r2, #32
8000ae2: 431a orrs r2, r3
8000ae4: 687b ldr r3, [r7, #4]
8000ae6: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000ae8: 687b ldr r3, [r7, #4]
8000aea: 6bdb ldr r3, [r3, #60] ; 0x3c
8000aec: 2201 movs r2, #1
8000aee: 431a orrs r2, r3
8000af0: 687b ldr r3, [r7, #4]
8000af2: 63da str r2, [r3, #60] ; 0x3c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8000af4: 687b ldr r3, [r7, #4]
8000af6: 69da ldr r2, [r3, #28]
8000af8: 23c2 movs r3, #194 ; 0xc2
8000afa: 33ff adds r3, #255 ; 0xff
8000afc: 429a cmp r2, r3
8000afe: d007 beq.n 8000b10 <HAL_ADC_Init+0x188>
{
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000b00: 687b ldr r3, [r7, #4]
8000b02: 69da ldr r2, [r3, #28]
hadc->Init.ExternalTrigConvEdge );
8000b04: 687b ldr r3, [r7, #4]
8000b06: 6a1b ldr r3, [r3, #32]
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
8000b08: 4313 orrs r3, r2
8000b0a: 68ba ldr r2, [r7, #8]
8000b0c: 4313 orrs r3, r2
8000b0e: 60bb str r3, [r7, #8]
}
/* Update ADC configuration register with previous settings */
hadc->Instance->CFGR1 |= tmpCFGR1;
8000b10: 687b ldr r3, [r7, #4]
8000b12: 681b ldr r3, [r3, #0]
8000b14: 68d9 ldr r1, [r3, #12]
8000b16: 687b ldr r3, [r7, #4]
8000b18: 681b ldr r3, [r3, #0]
8000b1a: 68ba ldr r2, [r7, #8]
8000b1c: 430a orrs r2, r1
8000b1e: 60da str r2, [r3, #12]
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function if parameter */
/* "SamplingTimeCommon" has been set to a valid sampling time. */
/* Otherwise, sampling time is set into ADC channel initialization */
/* structure with parameter "SamplingTime" (obsolete). */
if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000b20: 687b ldr r3, [r7, #4]
8000b22: 6ada ldr r2, [r3, #44] ; 0x2c
8000b24: 2380 movs r3, #128 ; 0x80
8000b26: 055b lsls r3, r3, #21
8000b28: 429a cmp r2, r3
8000b2a: d01b beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b2c: 687b ldr r3, [r7, #4]
8000b2e: 6adb ldr r3, [r3, #44] ; 0x2c
8000b30: 2b01 cmp r3, #1
8000b32: d017 beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b34: 687b ldr r3, [r7, #4]
8000b36: 6adb ldr r3, [r3, #44] ; 0x2c
8000b38: 2b02 cmp r3, #2
8000b3a: d013 beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b3c: 687b ldr r3, [r7, #4]
8000b3e: 6adb ldr r3, [r3, #44] ; 0x2c
8000b40: 2b03 cmp r3, #3
8000b42: d00f beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b44: 687b ldr r3, [r7, #4]
8000b46: 6adb ldr r3, [r3, #44] ; 0x2c
8000b48: 2b04 cmp r3, #4
8000b4a: d00b beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b4c: 687b ldr r3, [r7, #4]
8000b4e: 6adb ldr r3, [r3, #44] ; 0x2c
8000b50: 2b05 cmp r3, #5
8000b52: d007 beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b54: 687b ldr r3, [r7, #4]
8000b56: 6adb ldr r3, [r3, #44] ; 0x2c
8000b58: 2b06 cmp r3, #6
8000b5a: d003 beq.n 8000b64 <HAL_ADC_Init+0x1dc>
8000b5c: 687b ldr r3, [r7, #4]
8000b5e: 6adb ldr r3, [r3, #44] ; 0x2c
8000b60: 2b07 cmp r3, #7
8000b62: d112 bne.n 8000b8a <HAL_ADC_Init+0x202>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000b64: 687b ldr r3, [r7, #4]
8000b66: 681b ldr r3, [r3, #0]
8000b68: 695a ldr r2, [r3, #20]
8000b6a: 687b ldr r3, [r7, #4]
8000b6c: 681b ldr r3, [r3, #0]
8000b6e: 2107 movs r1, #7
8000b70: 438a bics r2, r1
8000b72: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
8000b74: 687b ldr r3, [r7, #4]
8000b76: 681b ldr r3, [r3, #0]
8000b78: 6959 ldr r1, [r3, #20]
8000b7a: 687b ldr r3, [r7, #4]
8000b7c: 6adb ldr r3, [r3, #44] ; 0x2c
8000b7e: 2207 movs r2, #7
8000b80: 401a ands r2, r3
8000b82: 687b ldr r3, [r7, #4]
8000b84: 681b ldr r3, [r3, #0]
8000b86: 430a orrs r2, r1
8000b88: 615a str r2, [r3, #20]
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
/* set into separate dedicated function, and bits of ADC resolution set */
/* out of temporary variable 'tmpCFGR1'). */
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000b8a: 687b ldr r3, [r7, #4]
8000b8c: 681b ldr r3, [r3, #0]
8000b8e: 68db ldr r3, [r3, #12]
8000b90: 4a1c ldr r2, [pc, #112] ; (8000c04 <HAL_ADC_Init+0x27c>)
8000b92: 4013 ands r3, r2
8000b94: 68ba ldr r2, [r7, #8]
8000b96: 429a cmp r2, r3
8000b98: d10b bne.n 8000bb2 <HAL_ADC_Init+0x22a>
== tmpCFGR1)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8000b9a: 687b ldr r3, [r7, #4]
8000b9c: 2200 movs r2, #0
8000b9e: 63da str r2, [r3, #60] ; 0x3c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000ba0: 687b ldr r3, [r7, #4]
8000ba2: 6b9b ldr r3, [r3, #56] ; 0x38
8000ba4: 2203 movs r2, #3
8000ba6: 4393 bics r3, r2
8000ba8: 2201 movs r2, #1
8000baa: 431a orrs r2, r3
8000bac: 687b ldr r3, [r7, #4]
8000bae: 639a str r2, [r3, #56] ; 0x38
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000bb0: e01c b.n 8000bec <HAL_ADC_Init+0x264>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8000bb2: 687b ldr r3, [r7, #4]
8000bb4: 6b9b ldr r3, [r3, #56] ; 0x38
8000bb6: 2212 movs r2, #18
8000bb8: 4393 bics r3, r2
8000bba: 2210 movs r2, #16
8000bbc: 431a orrs r2, r3
8000bbe: 687b ldr r3, [r7, #4]
8000bc0: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000bc2: 687b ldr r3, [r7, #4]
8000bc4: 6bdb ldr r3, [r3, #60] ; 0x3c
8000bc6: 2201 movs r2, #1
8000bc8: 431a orrs r2, r3
8000bca: 687b ldr r3, [r7, #4]
8000bcc: 63da str r2, [r3, #60] ; 0x3c
tmp_hal_status = HAL_ERROR;
8000bce: 230f movs r3, #15
8000bd0: 18fb adds r3, r7, r3
8000bd2: 2201 movs r2, #1
8000bd4: 701a strb r2, [r3, #0]
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
8000bd6: e009 b.n 8000bec <HAL_ADC_Init+0x264>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000bd8: 687b ldr r3, [r7, #4]
8000bda: 6b9b ldr r3, [r3, #56] ; 0x38
8000bdc: 2210 movs r2, #16
8000bde: 431a orrs r2, r3
8000be0: 687b ldr r3, [r7, #4]
8000be2: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
8000be4: 230f movs r3, #15
8000be6: 18fb adds r3, r7, r3
8000be8: 2201 movs r2, #1
8000bea: 701a strb r2, [r3, #0]
}
/* Return function status */
return tmp_hal_status;
8000bec: 230f movs r3, #15
8000bee: 18fb adds r3, r7, r3
8000bf0: 781b ldrb r3, [r3, #0]
}
8000bf2: 0018 movs r0, r3
8000bf4: 46bd mov sp, r7
8000bf6: b004 add sp, #16
8000bf8: bd80 pop {r7, pc}
8000bfa: 46c0 nop ; (mov r8, r8)
8000bfc: fffffefd .word 0xfffffefd
8000c00: fffe0219 .word 0xfffe0219
8000c04: 833fffe7 .word 0x833fffe7
08000c08 <HAL_ADC_Start>:
* Interruptions enabled in this function: None.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
8000c08: b590 push {r4, r7, lr}
8000c0a: b085 sub sp, #20
8000c0c: af00 add r7, sp, #0
8000c0e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000c10: 230f movs r3, #15
8000c12: 18fb adds r3, r7, r3
8000c14: 2200 movs r2, #0
8000c16: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 681b ldr r3, [r3, #0]
8000c1c: 689b ldr r3, [r3, #8]
8000c1e: 2204 movs r2, #4
8000c20: 4013 ands r3, r2
8000c22: d138 bne.n 8000c96 <HAL_ADC_Start+0x8e>
{
/* Process locked */
__HAL_LOCK(hadc);
8000c24: 687b ldr r3, [r7, #4]
8000c26: 2234 movs r2, #52 ; 0x34
8000c28: 5c9b ldrb r3, [r3, r2]
8000c2a: 2b01 cmp r3, #1
8000c2c: d101 bne.n 8000c32 <HAL_ADC_Start+0x2a>
8000c2e: 2302 movs r3, #2
8000c30: e038 b.n 8000ca4 <HAL_ADC_Start+0x9c>
8000c32: 687b ldr r3, [r7, #4]
8000c34: 2234 movs r2, #52 ; 0x34
8000c36: 2101 movs r1, #1
8000c38: 5499 strb r1, [r3, r2]
/* Enable the ADC peripheral */
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
8000c3a: 687b ldr r3, [r7, #4]
8000c3c: 7e5b ldrb r3, [r3, #25]
8000c3e: 2b01 cmp r3, #1
8000c40: d007 beq.n 8000c52 <HAL_ADC_Start+0x4a>
{
tmp_hal_status = ADC_Enable(hadc);
8000c42: 230f movs r3, #15
8000c44: 18fc adds r4, r7, r3
8000c46: 687b ldr r3, [r7, #4]
8000c48: 0018 movs r0, r3
8000c4a: f000 fa0b bl 8001064 <ADC_Enable>
8000c4e: 0003 movs r3, r0
8000c50: 7023 strb r3, [r4, #0]
}
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
8000c52: 230f movs r3, #15
8000c54: 18fb adds r3, r7, r3
8000c56: 781b ldrb r3, [r3, #0]
8000c58: 2b00 cmp r3, #0
8000c5a: d120 bne.n 8000c9e <HAL_ADC_Start+0x96>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
8000c5c: 687b ldr r3, [r7, #4]
8000c5e: 6b9b ldr r3, [r3, #56] ; 0x38
8000c60: 4a12 ldr r2, [pc, #72] ; (8000cac <HAL_ADC_Start+0xa4>)
8000c62: 4013 ands r3, r2
8000c64: 2280 movs r2, #128 ; 0x80
8000c66: 0052 lsls r2, r2, #1
8000c68: 431a orrs r2, r3
8000c6a: 687b ldr r3, [r7, #4]
8000c6c: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8000c6e: 687b ldr r3, [r7, #4]
8000c70: 2200 movs r2, #0
8000c72: 63da str r2, [r3, #60] ; 0x3c
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8000c74: 687b ldr r3, [r7, #4]
8000c76: 2234 movs r2, #52 ; 0x34
8000c78: 2100 movs r1, #0
8000c7a: 5499 strb r1, [r3, r2]
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
8000c7c: 687b ldr r3, [r7, #4]
8000c7e: 681b ldr r3, [r3, #0]
8000c80: 221c movs r2, #28
8000c82: 601a str r2, [r3, #0]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
8000c84: 687b ldr r3, [r7, #4]
8000c86: 681b ldr r3, [r3, #0]
8000c88: 689a ldr r2, [r3, #8]
8000c8a: 687b ldr r3, [r7, #4]
8000c8c: 681b ldr r3, [r3, #0]
8000c8e: 2104 movs r1, #4
8000c90: 430a orrs r2, r1
8000c92: 609a str r2, [r3, #8]
8000c94: e003 b.n 8000c9e <HAL_ADC_Start+0x96>
}
}
else
{
tmp_hal_status = HAL_BUSY;
8000c96: 230f movs r3, #15
8000c98: 18fb adds r3, r7, r3
8000c9a: 2202 movs r2, #2
8000c9c: 701a strb r2, [r3, #0]
}
/* Return function status */
return tmp_hal_status;
8000c9e: 230f movs r3, #15
8000ca0: 18fb adds r3, r7, r3
8000ca2: 781b ldrb r3, [r3, #0]
}
8000ca4: 0018 movs r0, r3
8000ca6: 46bd mov sp, r7
8000ca8: b005 add sp, #20
8000caa: bd90 pop {r4, r7, pc}
8000cac: fffff0fe .word 0xfffff0fe
08000cb0 <HAL_ADC_Stop>:
* @brief Stop ADC conversion of regular group, disable ADC peripheral.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
8000cb0: b5b0 push {r4, r5, r7, lr}
8000cb2: b084 sub sp, #16
8000cb4: af00 add r7, sp, #0
8000cb6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000cb8: 230f movs r3, #15
8000cba: 18fb adds r3, r7, r3
8000cbc: 2200 movs r2, #0
8000cbe: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8000cc0: 687b ldr r3, [r7, #4]
8000cc2: 2234 movs r2, #52 ; 0x34
8000cc4: 5c9b ldrb r3, [r3, r2]
8000cc6: 2b01 cmp r3, #1
8000cc8: d101 bne.n 8000cce <HAL_ADC_Stop+0x1e>
8000cca: 2302 movs r3, #2
8000ccc: e029 b.n 8000d22 <HAL_ADC_Stop+0x72>
8000cce: 687b ldr r3, [r7, #4]
8000cd0: 2234 movs r2, #52 ; 0x34
8000cd2: 2101 movs r1, #1
8000cd4: 5499 strb r1, [r3, r2]
/* 1. Stop potential conversion on going, on regular group */
tmp_hal_status = ADC_ConversionStop(hadc);
8000cd6: 250f movs r5, #15
8000cd8: 197c adds r4, r7, r5
8000cda: 687b ldr r3, [r7, #4]
8000cdc: 0018 movs r0, r3
8000cde: f000 fab6 bl 800124e <ADC_ConversionStop>
8000ce2: 0003 movs r3, r0
8000ce4: 7023 strb r3, [r4, #0]
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
8000ce6: 197b adds r3, r7, r5
8000ce8: 781b ldrb r3, [r3, #0]
8000cea: 2b00 cmp r3, #0
8000cec: d112 bne.n 8000d14 <HAL_ADC_Stop+0x64>
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
8000cee: 197c adds r4, r7, r5
8000cf0: 687b ldr r3, [r7, #4]
8000cf2: 0018 movs r0, r3
8000cf4: f000 fa3a bl 800116c <ADC_Disable>
8000cf8: 0003 movs r3, r0
8000cfa: 7023 strb r3, [r4, #0]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
8000cfc: 197b adds r3, r7, r5
8000cfe: 781b ldrb r3, [r3, #0]
8000d00: 2b00 cmp r3, #0
8000d02: d107 bne.n 8000d14 <HAL_ADC_Stop+0x64>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000d04: 687b ldr r3, [r7, #4]
8000d06: 6b9b ldr r3, [r3, #56] ; 0x38
8000d08: 4a08 ldr r2, [pc, #32] ; (8000d2c <HAL_ADC_Stop+0x7c>)
8000d0a: 4013 ands r3, r2
8000d0c: 2201 movs r2, #1
8000d0e: 431a orrs r2, r3
8000d10: 687b ldr r3, [r7, #4]
8000d12: 639a str r2, [r3, #56] ; 0x38
HAL_ADC_STATE_READY);
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000d14: 687b ldr r3, [r7, #4]
8000d16: 2234 movs r2, #52 ; 0x34
8000d18: 2100 movs r1, #0
8000d1a: 5499 strb r1, [r3, r2]
/* Return function status */
return tmp_hal_status;
8000d1c: 230f movs r3, #15
8000d1e: 18fb adds r3, r7, r3
8000d20: 781b ldrb r3, [r3, #0]
}
8000d22: 0018 movs r0, r3
8000d24: 46bd mov sp, r7
8000d26: b004 add sp, #16
8000d28: bdb0 pop {r4, r5, r7, pc}
8000d2a: 46c0 nop ; (mov r8, r8)
8000d2c: fffffefe .word 0xfffffefe
08000d30 <HAL_ADC_PollForConversion>:
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
8000d30: b580 push {r7, lr}
8000d32: b084 sub sp, #16
8000d34: af00 add r7, sp, #0
8000d36: 6078 str r0, [r7, #4]
8000d38: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of conversion selected to end of sequence */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
8000d3a: 687b ldr r3, [r7, #4]
8000d3c: 695b ldr r3, [r3, #20]
8000d3e: 2b08 cmp r3, #8
8000d40: d102 bne.n 8000d48 <HAL_ADC_PollForConversion+0x18>
{
tmp_Flag_EOC = ADC_FLAG_EOS;
8000d42: 2308 movs r3, #8
8000d44: 60fb str r3, [r7, #12]
8000d46: e014 b.n 8000d72 <HAL_ADC_PollForConversion+0x42>
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
8000d48: 687b ldr r3, [r7, #4]
8000d4a: 681b ldr r3, [r3, #0]
8000d4c: 68db ldr r3, [r3, #12]
8000d4e: 2201 movs r2, #1
8000d50: 4013 ands r3, r2
8000d52: 2b01 cmp r3, #1
8000d54: d10b bne.n 8000d6e <HAL_ADC_PollForConversion+0x3e>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000d56: 687b ldr r3, [r7, #4]
8000d58: 6b9b ldr r3, [r3, #56] ; 0x38
8000d5a: 2220 movs r2, #32
8000d5c: 431a orrs r2, r3
8000d5e: 687b ldr r3, [r7, #4]
8000d60: 639a str r2, [r3, #56] ; 0x38
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000d62: 687b ldr r3, [r7, #4]
8000d64: 2234 movs r2, #52 ; 0x34
8000d66: 2100 movs r1, #0
8000d68: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8000d6a: 2301 movs r3, #1
8000d6c: e071 b.n 8000e52 <HAL_ADC_PollForConversion+0x122>
}
else
{
tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
8000d6e: 230c movs r3, #12
8000d70: 60fb str r3, [r7, #12]
}
}
/* Get tick count */
tickstart = HAL_GetTick();
8000d72: f7ff fdff bl 8000974 <HAL_GetTick>
8000d76: 0003 movs r3, r0
8000d78: 60bb str r3, [r7, #8]
/* Wait until End of Conversion flag is raised */
while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
8000d7a: e01f b.n 8000dbc <HAL_ADC_PollForConversion+0x8c>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
8000d7c: 683b ldr r3, [r7, #0]
8000d7e: 3301 adds r3, #1
8000d80: d01c beq.n 8000dbc <HAL_ADC_PollForConversion+0x8c>
{
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
8000d82: 683b ldr r3, [r7, #0]
8000d84: 2b00 cmp r3, #0
8000d86: d007 beq.n 8000d98 <HAL_ADC_PollForConversion+0x68>
8000d88: f7ff fdf4 bl 8000974 <HAL_GetTick>
8000d8c: 0002 movs r2, r0
8000d8e: 68bb ldr r3, [r7, #8]
8000d90: 1ad3 subs r3, r2, r3
8000d92: 683a ldr r2, [r7, #0]
8000d94: 429a cmp r2, r3
8000d96: d211 bcs.n 8000dbc <HAL_ADC_PollForConversion+0x8c>
{
/* New check to avoid false timeout detection in case of preemption */
if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
8000d98: 687b ldr r3, [r7, #4]
8000d9a: 681b ldr r3, [r3, #0]
8000d9c: 681b ldr r3, [r3, #0]
8000d9e: 68fa ldr r2, [r7, #12]
8000da0: 4013 ands r3, r2
8000da2: d10b bne.n 8000dbc <HAL_ADC_PollForConversion+0x8c>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
8000da4: 687b ldr r3, [r7, #4]
8000da6: 6b9b ldr r3, [r3, #56] ; 0x38
8000da8: 2204 movs r2, #4
8000daa: 431a orrs r2, r3
8000dac: 687b ldr r3, [r7, #4]
8000dae: 639a str r2, [r3, #56] ; 0x38
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000db0: 687b ldr r3, [r7, #4]
8000db2: 2234 movs r2, #52 ; 0x34
8000db4: 2100 movs r1, #0
8000db6: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
8000db8: 2303 movs r3, #3
8000dba: e04a b.n 8000e52 <HAL_ADC_PollForConversion+0x122>
while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
8000dbc: 687b ldr r3, [r7, #4]
8000dbe: 681b ldr r3, [r3, #0]
8000dc0: 681b ldr r3, [r3, #0]
8000dc2: 68fa ldr r2, [r7, #12]
8000dc4: 4013 ands r3, r2
8000dc6: d0d9 beq.n 8000d7c <HAL_ADC_PollForConversion+0x4c>
}
}
}
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8000dc8: 687b ldr r3, [r7, #4]
8000dca: 6b9b ldr r3, [r3, #56] ; 0x38
8000dcc: 2280 movs r2, #128 ; 0x80
8000dce: 0092 lsls r2, r2, #2
8000dd0: 431a orrs r2, r3
8000dd2: 687b ldr r3, [r7, #4]
8000dd4: 639a str r2, [r3, #56] ; 0x38
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 681b ldr r3, [r3, #0]
8000dda: 68da ldr r2, [r3, #12]
8000ddc: 23c0 movs r3, #192 ; 0xc0
8000dde: 011b lsls r3, r3, #4
8000de0: 4013 ands r3, r2
8000de2: d12d bne.n 8000e40 <HAL_ADC_PollForConversion+0x110>
(hadc->Init.ContinuousConvMode == DISABLE) )
8000de4: 687b ldr r3, [r7, #4]
8000de6: 7e9b ldrb r3, [r3, #26]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8000de8: 2b00 cmp r3, #0
8000dea: d129 bne.n 8000e40 <HAL_ADC_PollForConversion+0x110>
{
/* If End of Sequence is reached, disable interrupts */
if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
8000dec: 687b ldr r3, [r7, #4]
8000dee: 681b ldr r3, [r3, #0]
8000df0: 681b ldr r3, [r3, #0]
8000df2: 2208 movs r2, #8
8000df4: 4013 ands r3, r2
8000df6: 2b08 cmp r3, #8
8000df8: d122 bne.n 8000e40 <HAL_ADC_PollForConversion+0x110>
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8000dfa: 687b ldr r3, [r7, #4]
8000dfc: 681b ldr r3, [r3, #0]
8000dfe: 689b ldr r3, [r3, #8]
8000e00: 2204 movs r2, #4
8000e02: 4013 ands r3, r2
8000e04: d110 bne.n 8000e28 <HAL_ADC_PollForConversion+0xf8>
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
8000e06: 687b ldr r3, [r7, #4]
8000e08: 681b ldr r3, [r3, #0]
8000e0a: 685a ldr r2, [r3, #4]
8000e0c: 687b ldr r3, [r7, #4]
8000e0e: 681b ldr r3, [r3, #0]
8000e10: 210c movs r1, #12
8000e12: 438a bics r2, r1
8000e14: 605a str r2, [r3, #4]
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8000e16: 687b ldr r3, [r7, #4]
8000e18: 6b9b ldr r3, [r3, #56] ; 0x38
8000e1a: 4a10 ldr r2, [pc, #64] ; (8000e5c <HAL_ADC_PollForConversion+0x12c>)
8000e1c: 4013 ands r3, r2
8000e1e: 2201 movs r2, #1
8000e20: 431a orrs r2, r3
8000e22: 687b ldr r3, [r7, #4]
8000e24: 639a str r2, [r3, #56] ; 0x38
8000e26: e00b b.n 8000e40 <HAL_ADC_PollForConversion+0x110>
HAL_ADC_STATE_READY);
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000e28: 687b ldr r3, [r7, #4]
8000e2a: 6b9b ldr r3, [r3, #56] ; 0x38
8000e2c: 2220 movs r2, #32
8000e2e: 431a orrs r2, r3
8000e30: 687b ldr r3, [r7, #4]
8000e32: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000e34: 687b ldr r3, [r7, #4]
8000e36: 6bdb ldr r3, [r3, #60] ; 0x3c
8000e38: 2201 movs r2, #1
8000e3a: 431a orrs r2, r3
8000e3c: 687b ldr r3, [r7, #4]
8000e3e: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear end of conversion flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
if (hadc->Init.LowPowerAutoWait == DISABLE)
8000e40: 687b ldr r3, [r7, #4]
8000e42: 7e1b ldrb r3, [r3, #24]
8000e44: 2b00 cmp r3, #0
8000e46: d103 bne.n 8000e50 <HAL_ADC_PollForConversion+0x120>
{
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
8000e48: 687b ldr r3, [r7, #4]
8000e4a: 681b ldr r3, [r3, #0]
8000e4c: 220c movs r2, #12
8000e4e: 601a str r2, [r3, #0]
}
/* Return ADC state */
return HAL_OK;
8000e50: 2300 movs r3, #0
}
8000e52: 0018 movs r0, r3
8000e54: 46bd mov sp, r7
8000e56: b004 add sp, #16
8000e58: bd80 pop {r7, pc}
8000e5a: 46c0 nop ; (mov r8, r8)
8000e5c: fffffefe .word 0xfffffefe
08000e60 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
8000e60: b580 push {r7, lr}
8000e62: b082 sub sp, #8
8000e64: af00 add r7, sp, #0
8000e66: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8000e68: 687b ldr r3, [r7, #4]
8000e6a: 681b ldr r3, [r3, #0]
8000e6c: 6c1b ldr r3, [r3, #64] ; 0x40
}
8000e6e: 0018 movs r0, r3
8000e70: 46bd mov sp, r7
8000e72: b002 add sp, #8
8000e74: bd80 pop {r7, pc}
...
08000e78 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8000e78: b580 push {r7, lr}
8000e7a: b084 sub sp, #16
8000e7c: af00 add r7, sp, #0
8000e7e: 6078 str r0, [r7, #4]
8000e80: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000e82: 230f movs r3, #15
8000e84: 18fb adds r3, r7, r3
8000e86: 2200 movs r2, #0
8000e88: 701a strb r2, [r3, #0]
__IO uint32_t wait_loop_index = 0U;
8000e8a: 2300 movs r3, #0
8000e8c: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_RANK(sConfig->Rank));
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000e8e: 687b ldr r3, [r7, #4]
8000e90: 6ada ldr r2, [r3, #44] ; 0x2c
8000e92: 2380 movs r3, #128 ; 0x80
8000e94: 055b lsls r3, r3, #21
8000e96: 429a cmp r2, r3
8000e98: d011 beq.n 8000ebe <HAL_ADC_ConfigChannel+0x46>
8000e9a: 687b ldr r3, [r7, #4]
8000e9c: 6adb ldr r3, [r3, #44] ; 0x2c
8000e9e: 2b01 cmp r3, #1
8000ea0: d00d beq.n 8000ebe <HAL_ADC_ConfigChannel+0x46>
8000ea2: 687b ldr r3, [r7, #4]
8000ea4: 6adb ldr r3, [r3, #44] ; 0x2c
8000ea6: 2b02 cmp r3, #2
8000ea8: d009 beq.n 8000ebe <HAL_ADC_ConfigChannel+0x46>
8000eaa: 687b ldr r3, [r7, #4]
8000eac: 6adb ldr r3, [r3, #44] ; 0x2c
8000eae: 2b03 cmp r3, #3
8000eb0: d005 beq.n 8000ebe <HAL_ADC_ConfigChannel+0x46>
8000eb2: 687b ldr r3, [r7, #4]
8000eb4: 6adb ldr r3, [r3, #44] ; 0x2c
8000eb6: 2b04 cmp r3, #4
8000eb8: d001 beq.n 8000ebe <HAL_ADC_ConfigChannel+0x46>
8000eba: 687b ldr r3, [r7, #4]
8000ebc: 6adb ldr r3, [r3, #44] ; 0x2c
{
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
}
/* Process locked */
__HAL_LOCK(hadc);
8000ebe: 687b ldr r3, [r7, #4]
8000ec0: 2234 movs r2, #52 ; 0x34
8000ec2: 5c9b ldrb r3, [r3, r2]
8000ec4: 2b01 cmp r3, #1
8000ec6: d101 bne.n 8000ecc <HAL_ADC_ConfigChannel+0x54>
8000ec8: 2302 movs r3, #2
8000eca: e0bb b.n 8001044 <HAL_ADC_ConfigChannel+0x1cc>
8000ecc: 687b ldr r3, [r7, #4]
8000ece: 2234 movs r2, #52 ; 0x34
8000ed0: 2101 movs r1, #1
8000ed2: 5499 strb r1, [r3, r2]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8000ed4: 687b ldr r3, [r7, #4]
8000ed6: 681b ldr r3, [r3, #0]
8000ed8: 689b ldr r3, [r3, #8]
8000eda: 2204 movs r2, #4
8000edc: 4013 ands r3, r2
8000ede: d000 beq.n 8000ee2 <HAL_ADC_ConfigChannel+0x6a>
8000ee0: e09f b.n 8001022 <HAL_ADC_ConfigChannel+0x1aa>
{
/* Configure channel: depending on rank setting, add it or remove it from */
/* ADC conversion sequencer. */
if (sConfig->Rank != ADC_RANK_NONE)
8000ee2: 683b ldr r3, [r7, #0]
8000ee4: 685b ldr r3, [r3, #4]
8000ee6: 4a59 ldr r2, [pc, #356] ; (800104c <HAL_ADC_ConfigChannel+0x1d4>)
8000ee8: 4293 cmp r3, r2
8000eea: d100 bne.n 8000eee <HAL_ADC_ConfigChannel+0x76>
8000eec: e077 b.n 8000fde <HAL_ADC_ConfigChannel+0x166>
{
/* Regular sequence configuration */
/* Set the channel selection register from the selected channel */
hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
8000eee: 687b ldr r3, [r7, #4]
8000ef0: 681b ldr r3, [r3, #0]
8000ef2: 6a99 ldr r1, [r3, #40] ; 0x28
8000ef4: 683b ldr r3, [r7, #0]
8000ef6: 681b ldr r3, [r3, #0]
8000ef8: 2201 movs r2, #1
8000efa: 409a lsls r2, r3
8000efc: 687b ldr r3, [r7, #4]
8000efe: 681b ldr r3, [r3, #0]
8000f00: 430a orrs r2, r1
8000f02: 629a str r2, [r3, #40] ; 0x28
/* Channel sampling time configuration */
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
/* (obsolete): sampling time set in this function with */
/* parameter "SamplingTime" (obsolete) only if not already set into */
/* ADC initialization structure with parameter "SamplingTimeCommon". */
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
8000f04: 687b ldr r3, [r7, #4]
8000f06: 6ada ldr r2, [r3, #44] ; 0x2c
8000f08: 2380 movs r3, #128 ; 0x80
8000f0a: 055b lsls r3, r3, #21
8000f0c: 429a cmp r2, r3
8000f0e: d037 beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f10: 687b ldr r3, [r7, #4]
8000f12: 6adb ldr r3, [r3, #44] ; 0x2c
8000f14: 2b01 cmp r3, #1
8000f16: d033 beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f18: 687b ldr r3, [r7, #4]
8000f1a: 6adb ldr r3, [r3, #44] ; 0x2c
8000f1c: 2b02 cmp r3, #2
8000f1e: d02f beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f20: 687b ldr r3, [r7, #4]
8000f22: 6adb ldr r3, [r3, #44] ; 0x2c
8000f24: 2b03 cmp r3, #3
8000f26: d02b beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f28: 687b ldr r3, [r7, #4]
8000f2a: 6adb ldr r3, [r3, #44] ; 0x2c
8000f2c: 2b04 cmp r3, #4
8000f2e: d027 beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f30: 687b ldr r3, [r7, #4]
8000f32: 6adb ldr r3, [r3, #44] ; 0x2c
8000f34: 2b05 cmp r3, #5
8000f36: d023 beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f38: 687b ldr r3, [r7, #4]
8000f3a: 6adb ldr r3, [r3, #44] ; 0x2c
8000f3c: 2b06 cmp r3, #6
8000f3e: d01f beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
8000f40: 687b ldr r3, [r7, #4]
8000f42: 6adb ldr r3, [r3, #44] ; 0x2c
8000f44: 2b07 cmp r3, #7
8000f46: d01b beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
{
/* Modify sampling time if needed (not needed in case of reoccurrence */
/* for several channels programmed consecutively into the sequencer) */
if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
8000f48: 683b ldr r3, [r7, #0]
8000f4a: 689a ldr r2, [r3, #8]
8000f4c: 687b ldr r3, [r7, #4]
8000f4e: 681b ldr r3, [r3, #0]
8000f50: 695b ldr r3, [r3, #20]
8000f52: 2107 movs r1, #7
8000f54: 400b ands r3, r1
8000f56: 429a cmp r2, r3
8000f58: d012 beq.n 8000f80 <HAL_ADC_ConfigChannel+0x108>
{
/* Channel sampling time configuration */
/* Clear the old sample time */
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
8000f5a: 687b ldr r3, [r7, #4]
8000f5c: 681b ldr r3, [r3, #0]
8000f5e: 695a ldr r2, [r3, #20]
8000f60: 687b ldr r3, [r7, #4]
8000f62: 681b ldr r3, [r3, #0]
8000f64: 2107 movs r1, #7
8000f66: 438a bics r2, r1
8000f68: 615a str r2, [r3, #20]
/* Set the new sample time */
hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
8000f6a: 687b ldr r3, [r7, #4]
8000f6c: 681b ldr r3, [r3, #0]
8000f6e: 6959 ldr r1, [r3, #20]
8000f70: 683b ldr r3, [r7, #0]
8000f72: 689b ldr r3, [r3, #8]
8000f74: 2207 movs r2, #7
8000f76: 401a ands r2, r3
8000f78: 687b ldr r3, [r7, #4]
8000f7a: 681b ldr r3, [r3, #0]
8000f7c: 430a orrs r2, r1
8000f7e: 615a str r2, [r3, #20]
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000f80: 683b ldr r3, [r7, #0]
8000f82: 681b ldr r3, [r3, #0]
8000f84: 2b10 cmp r3, #16
8000f86: d003 beq.n 8000f90 <HAL_ADC_ConfigChannel+0x118>
8000f88: 683b ldr r3, [r7, #0]
8000f8a: 681b ldr r3, [r3, #0]
8000f8c: 2b11 cmp r3, #17
8000f8e: d152 bne.n 8001036 <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, enable Temp. sensor measurement path. */
/* If Channel_17 is selected, enable VREFINT measurement path. */
/* If Channel_18 is selected, enable VBAT measurement path. */
ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8000f90: 4b2f ldr r3, [pc, #188] ; (8001050 <HAL_ADC_ConfigChannel+0x1d8>)
8000f92: 6819 ldr r1, [r3, #0]
8000f94: 683b ldr r3, [r7, #0]
8000f96: 681b ldr r3, [r3, #0]
8000f98: 2b10 cmp r3, #16
8000f9a: d102 bne.n 8000fa2 <HAL_ADC_ConfigChannel+0x12a>
8000f9c: 2380 movs r3, #128 ; 0x80
8000f9e: 041b lsls r3, r3, #16
8000fa0: e001 b.n 8000fa6 <HAL_ADC_ConfigChannel+0x12e>
8000fa2: 2380 movs r3, #128 ; 0x80
8000fa4: 03db lsls r3, r3, #15
8000fa6: 4a2a ldr r2, [pc, #168] ; (8001050 <HAL_ADC_ConfigChannel+0x1d8>)
8000fa8: 430b orrs r3, r1
8000faa: 6013 str r3, [r2, #0]
/* If Temp. sensor is selected, wait for stabilization delay */
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8000fac: 683b ldr r3, [r7, #0]
8000fae: 681b ldr r3, [r3, #0]
8000fb0: 2b10 cmp r3, #16
8000fb2: d140 bne.n 8001036 <HAL_ADC_ConfigChannel+0x1be>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8000fb4: 4b27 ldr r3, [pc, #156] ; (8001054 <HAL_ADC_ConfigChannel+0x1dc>)
8000fb6: 681b ldr r3, [r3, #0]
8000fb8: 4927 ldr r1, [pc, #156] ; (8001058 <HAL_ADC_ConfigChannel+0x1e0>)
8000fba: 0018 movs r0, r3
8000fbc: f7ff f8a4 bl 8000108 <__udivsi3>
8000fc0: 0003 movs r3, r0
8000fc2: 001a movs r2, r3
8000fc4: 0013 movs r3, r2
8000fc6: 009b lsls r3, r3, #2
8000fc8: 189b adds r3, r3, r2
8000fca: 005b lsls r3, r3, #1
8000fcc: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000fce: e002 b.n 8000fd6 <HAL_ADC_ConfigChannel+0x15e>
{
wait_loop_index--;
8000fd0: 68bb ldr r3, [r7, #8]
8000fd2: 3b01 subs r3, #1
8000fd4: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8000fd6: 68bb ldr r3, [r7, #8]
8000fd8: 2b00 cmp r3, #0
8000fda: d1f9 bne.n 8000fd0 <HAL_ADC_ConfigChannel+0x158>
8000fdc: e02b b.n 8001036 <HAL_ADC_ConfigChannel+0x1be>
}
else
{
/* Regular sequence configuration */
/* Reset the channel selection register from the selected channel */
hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
8000fde: 687b ldr r3, [r7, #4]
8000fe0: 681b ldr r3, [r3, #0]
8000fe2: 6a9a ldr r2, [r3, #40] ; 0x28
8000fe4: 683b ldr r3, [r7, #0]
8000fe6: 681b ldr r3, [r3, #0]
8000fe8: 2101 movs r1, #1
8000fea: 4099 lsls r1, r3
8000fec: 000b movs r3, r1
8000fee: 43d9 mvns r1, r3
8000ff0: 687b ldr r3, [r7, #4]
8000ff2: 681b ldr r3, [r3, #0]
8000ff4: 400a ands r2, r1
8000ff6: 629a str r2, [r3, #40] ; 0x28
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths disable: If internal channel selected, */
/* disable dedicated internal buffers and path. */
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000ff8: 683b ldr r3, [r7, #0]
8000ffa: 681b ldr r3, [r3, #0]
8000ffc: 2b10 cmp r3, #16
8000ffe: d003 beq.n 8001008 <HAL_ADC_ConfigChannel+0x190>
8001000: 683b ldr r3, [r7, #0]
8001002: 681b ldr r3, [r3, #0]
8001004: 2b11 cmp r3, #17
8001006: d116 bne.n 8001036 <HAL_ADC_ConfigChannel+0x1be>
{
/* If Channel_16 is selected, disable Temp. sensor measurement path. */
/* If Channel_17 is selected, disable VREFINT measurement path. */
/* If Channel_18 is selected, disable VBAT measurement path. */
ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
8001008: 4b11 ldr r3, [pc, #68] ; (8001050 <HAL_ADC_ConfigChannel+0x1d8>)
800100a: 6819 ldr r1, [r3, #0]
800100c: 683b ldr r3, [r7, #0]
800100e: 681b ldr r3, [r3, #0]
8001010: 2b10 cmp r3, #16
8001012: d101 bne.n 8001018 <HAL_ADC_ConfigChannel+0x1a0>
8001014: 4a11 ldr r2, [pc, #68] ; (800105c <HAL_ADC_ConfigChannel+0x1e4>)
8001016: e000 b.n 800101a <HAL_ADC_ConfigChannel+0x1a2>
8001018: 4a11 ldr r2, [pc, #68] ; (8001060 <HAL_ADC_ConfigChannel+0x1e8>)
800101a: 4b0d ldr r3, [pc, #52] ; (8001050 <HAL_ADC_ConfigChannel+0x1d8>)
800101c: 400a ands r2, r1
800101e: 601a str r2, [r3, #0]
8001020: e009 b.n 8001036 <HAL_ADC_ConfigChannel+0x1be>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001022: 687b ldr r3, [r7, #4]
8001024: 6b9b ldr r3, [r3, #56] ; 0x38
8001026: 2220 movs r2, #32
8001028: 431a orrs r2, r3
800102a: 687b ldr r3, [r7, #4]
800102c: 639a str r2, [r3, #56] ; 0x38
tmp_hal_status = HAL_ERROR;
800102e: 230f movs r3, #15
8001030: 18fb adds r3, r7, r3
8001032: 2201 movs r2, #1
8001034: 701a strb r2, [r3, #0]
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8001036: 687b ldr r3, [r7, #4]
8001038: 2234 movs r2, #52 ; 0x34
800103a: 2100 movs r1, #0
800103c: 5499 strb r1, [r3, r2]
/* Return function status */
return tmp_hal_status;
800103e: 230f movs r3, #15
8001040: 18fb adds r3, r7, r3
8001042: 781b ldrb r3, [r3, #0]
}
8001044: 0018 movs r0, r3
8001046: 46bd mov sp, r7
8001048: b004 add sp, #16
800104a: bd80 pop {r7, pc}
800104c: 00001001 .word 0x00001001
8001050: 40012708 .word 0x40012708
8001054: 20000000 .word 0x20000000
8001058: 000f4240 .word 0x000f4240
800105c: ff7fffff .word 0xff7fffff
8001060: ffbfffff .word 0xffbfffff
08001064 <ADC_Enable>:
* "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
8001064: b580 push {r7, lr}
8001066: b084 sub sp, #16
8001068: af00 add r7, sp, #0
800106a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800106c: 2300 movs r3, #0
800106e: 60fb str r3, [r7, #12]
__IO uint32_t wait_loop_index = 0U;
8001070: 2300 movs r3, #0
8001072: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (ADC_IS_ENABLE(hadc) == RESET)
8001074: 687b ldr r3, [r7, #4]
8001076: 681b ldr r3, [r3, #0]
8001078: 689b ldr r3, [r3, #8]
800107a: 2203 movs r2, #3
800107c: 4013 ands r3, r2
800107e: 2b01 cmp r3, #1
8001080: d112 bne.n 80010a8 <ADC_Enable+0x44>
8001082: 687b ldr r3, [r7, #4]
8001084: 681b ldr r3, [r3, #0]
8001086: 681b ldr r3, [r3, #0]
8001088: 2201 movs r2, #1
800108a: 4013 ands r3, r2
800108c: 2b01 cmp r3, #1
800108e: d009 beq.n 80010a4 <ADC_Enable+0x40>
8001090: 687b ldr r3, [r7, #4]
8001092: 681b ldr r3, [r3, #0]
8001094: 68da ldr r2, [r3, #12]
8001096: 2380 movs r3, #128 ; 0x80
8001098: 021b lsls r3, r3, #8
800109a: 401a ands r2, r3
800109c: 2380 movs r3, #128 ; 0x80
800109e: 021b lsls r3, r3, #8
80010a0: 429a cmp r2, r3
80010a2: d101 bne.n 80010a8 <ADC_Enable+0x44>
80010a4: 2301 movs r3, #1
80010a6: e000 b.n 80010aa <ADC_Enable+0x46>
80010a8: 2300 movs r3, #0
80010aa: 2b00 cmp r3, #0
80010ac: d152 bne.n 8001154 <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
80010ae: 687b ldr r3, [r7, #4]
80010b0: 681b ldr r3, [r3, #0]
80010b2: 689b ldr r3, [r3, #8]
80010b4: 4a2a ldr r2, [pc, #168] ; (8001160 <ADC_Enable+0xfc>)
80010b6: 4013 ands r3, r2
80010b8: d00d beq.n 80010d6 <ADC_Enable+0x72>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80010ba: 687b ldr r3, [r7, #4]
80010bc: 6b9b ldr r3, [r3, #56] ; 0x38
80010be: 2210 movs r2, #16
80010c0: 431a orrs r2, r3
80010c2: 687b ldr r3, [r7, #4]
80010c4: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80010c6: 687b ldr r3, [r7, #4]
80010c8: 6bdb ldr r3, [r3, #60] ; 0x3c
80010ca: 2201 movs r2, #1
80010cc: 431a orrs r2, r3
80010ce: 687b ldr r3, [r7, #4]
80010d0: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
80010d2: 2301 movs r3, #1
80010d4: e03f b.n 8001156 <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
__HAL_ADC_ENABLE(hadc);
80010d6: 687b ldr r3, [r7, #4]
80010d8: 681b ldr r3, [r3, #0]
80010da: 689a ldr r2, [r3, #8]
80010dc: 687b ldr r3, [r7, #4]
80010de: 681b ldr r3, [r3, #0]
80010e0: 2101 movs r1, #1
80010e2: 430a orrs r2, r1
80010e4: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
80010e6: 4b1f ldr r3, [pc, #124] ; (8001164 <ADC_Enable+0x100>)
80010e8: 681b ldr r3, [r3, #0]
80010ea: 491f ldr r1, [pc, #124] ; (8001168 <ADC_Enable+0x104>)
80010ec: 0018 movs r0, r3
80010ee: f7ff f80b bl 8000108 <__udivsi3>
80010f2: 0003 movs r3, r0
80010f4: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80010f6: e002 b.n 80010fe <ADC_Enable+0x9a>
{
wait_loop_index--;
80010f8: 68bb ldr r3, [r7, #8]
80010fa: 3b01 subs r3, #1
80010fc: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80010fe: 68bb ldr r3, [r7, #8]
8001100: 2b00 cmp r3, #0
8001102: d1f9 bne.n 80010f8 <ADC_Enable+0x94>
}
/* Get tick count */
tickstart = HAL_GetTick();
8001104: f7ff fc36 bl 8000974 <HAL_GetTick>
8001108: 0003 movs r3, r0
800110a: 60fb str r3, [r7, #12]
/* Wait for ADC effectively enabled */
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
800110c: e01b b.n 8001146 <ADC_Enable+0xe2>
{
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
800110e: f7ff fc31 bl 8000974 <HAL_GetTick>
8001112: 0002 movs r2, r0
8001114: 68fb ldr r3, [r7, #12]
8001116: 1ad3 subs r3, r2, r3
8001118: 2b02 cmp r3, #2
800111a: d914 bls.n 8001146 <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
800111c: 687b ldr r3, [r7, #4]
800111e: 681b ldr r3, [r3, #0]
8001120: 681b ldr r3, [r3, #0]
8001122: 2201 movs r2, #1
8001124: 4013 ands r3, r2
8001126: 2b01 cmp r3, #1
8001128: d00d beq.n 8001146 <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800112a: 687b ldr r3, [r7, #4]
800112c: 6b9b ldr r3, [r3, #56] ; 0x38
800112e: 2210 movs r2, #16
8001130: 431a orrs r2, r3
8001132: 687b ldr r3, [r7, #4]
8001134: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001136: 687b ldr r3, [r7, #4]
8001138: 6bdb ldr r3, [r3, #60] ; 0x3c
800113a: 2201 movs r2, #1
800113c: 431a orrs r2, r3
800113e: 687b ldr r3, [r7, #4]
8001140: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8001142: 2301 movs r3, #1
8001144: e007 b.n 8001156 <ADC_Enable+0xf2>
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
8001146: 687b ldr r3, [r7, #4]
8001148: 681b ldr r3, [r3, #0]
800114a: 681b ldr r3, [r3, #0]
800114c: 2201 movs r2, #1
800114e: 4013 ands r3, r2
8001150: 2b01 cmp r3, #1
8001152: d1dc bne.n 800110e <ADC_Enable+0xaa>
}
}
}
/* Return HAL status */
return HAL_OK;
8001154: 2300 movs r3, #0
}
8001156: 0018 movs r0, r3
8001158: 46bd mov sp, r7
800115a: b004 add sp, #16
800115c: bd80 pop {r7, pc}
800115e: 46c0 nop ; (mov r8, r8)
8001160: 80000017 .word 0x80000017
8001164: 20000000 .word 0x20000000
8001168: 000f4240 .word 0x000f4240
0800116c <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
{
800116c: b580 push {r7, lr}
800116e: b084 sub sp, #16
8001170: af00 add r7, sp, #0
8001172: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8001174: 2300 movs r3, #0
8001176: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if (ADC_IS_ENABLE(hadc) != RESET)
8001178: 687b ldr r3, [r7, #4]
800117a: 681b ldr r3, [r3, #0]
800117c: 689b ldr r3, [r3, #8]
800117e: 2203 movs r2, #3
8001180: 4013 ands r3, r2
8001182: 2b01 cmp r3, #1
8001184: d112 bne.n 80011ac <ADC_Disable+0x40>
8001186: 687b ldr r3, [r7, #4]
8001188: 681b ldr r3, [r3, #0]
800118a: 681b ldr r3, [r3, #0]
800118c: 2201 movs r2, #1
800118e: 4013 ands r3, r2
8001190: 2b01 cmp r3, #1
8001192: d009 beq.n 80011a8 <ADC_Disable+0x3c>
8001194: 687b ldr r3, [r7, #4]
8001196: 681b ldr r3, [r3, #0]
8001198: 68da ldr r2, [r3, #12]
800119a: 2380 movs r3, #128 ; 0x80
800119c: 021b lsls r3, r3, #8
800119e: 401a ands r2, r3
80011a0: 2380 movs r3, #128 ; 0x80
80011a2: 021b lsls r3, r3, #8
80011a4: 429a cmp r2, r3
80011a6: d101 bne.n 80011ac <ADC_Disable+0x40>
80011a8: 2301 movs r3, #1
80011aa: e000 b.n 80011ae <ADC_Disable+0x42>
80011ac: 2300 movs r3, #0
80011ae: 2b00 cmp r3, #0
80011b0: d048 beq.n 8001244 <ADC_Disable+0xd8>
{
/* Check if conditions to disable the ADC are fulfilled */
if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
80011b2: 687b ldr r3, [r7, #4]
80011b4: 681b ldr r3, [r3, #0]
80011b6: 689b ldr r3, [r3, #8]
80011b8: 2205 movs r2, #5
80011ba: 4013 ands r3, r2
80011bc: 2b01 cmp r3, #1
80011be: d110 bne.n 80011e2 <ADC_Disable+0x76>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
80011c0: 687b ldr r3, [r7, #4]
80011c2: 681b ldr r3, [r3, #0]
80011c4: 689a ldr r2, [r3, #8]
80011c6: 687b ldr r3, [r7, #4]
80011c8: 681b ldr r3, [r3, #0]
80011ca: 2102 movs r1, #2
80011cc: 430a orrs r2, r1
80011ce: 609a str r2, [r3, #8]
80011d0: 687b ldr r3, [r7, #4]
80011d2: 681b ldr r3, [r3, #0]
80011d4: 2203 movs r2, #3
80011d6: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
80011d8: f7ff fbcc bl 8000974 <HAL_GetTick>
80011dc: 0003 movs r3, r0
80011de: 60fb str r3, [r7, #12]
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
80011e0: e029 b.n 8001236 <ADC_Disable+0xca>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80011e2: 687b ldr r3, [r7, #4]
80011e4: 6b9b ldr r3, [r3, #56] ; 0x38
80011e6: 2210 movs r2, #16
80011e8: 431a orrs r2, r3
80011ea: 687b ldr r3, [r7, #4]
80011ec: 639a str r2, [r3, #56] ; 0x38
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80011ee: 687b ldr r3, [r7, #4]
80011f0: 6bdb ldr r3, [r3, #60] ; 0x3c
80011f2: 2201 movs r2, #1
80011f4: 431a orrs r2, r3
80011f6: 687b ldr r3, [r7, #4]
80011f8: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
80011fa: 2301 movs r3, #1
80011fc: e023 b.n 8001246 <ADC_Disable+0xda>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
80011fe: f7ff fbb9 bl 8000974 <HAL_GetTick>
8001202: 0002 movs r2, r0
8001204: 68fb ldr r3, [r7, #12]
8001206: 1ad3 subs r3, r2, r3
8001208: 2b02 cmp r3, #2
800120a: d914 bls.n 8001236 <ADC_Disable+0xca>
{
/* New check to avoid false timeout detection in case of preemption */
if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
800120c: 687b ldr r3, [r7, #4]
800120e: 681b ldr r3, [r3, #0]
8001210: 689b ldr r3, [r3, #8]
8001212: 2201 movs r2, #1
8001214: 4013 ands r3, r2
8001216: 2b01 cmp r3, #1
8001218: d10d bne.n 8001236 <ADC_Disable+0xca>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800121a: 687b ldr r3, [r7, #4]
800121c: 6b9b ldr r3, [r3, #56] ; 0x38
800121e: 2210 movs r2, #16
8001220: 431a orrs r2, r3
8001222: 687b ldr r3, [r7, #4]
8001224: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001226: 687b ldr r3, [r7, #4]
8001228: 6bdb ldr r3, [r3, #60] ; 0x3c
800122a: 2201 movs r2, #1
800122c: 431a orrs r2, r3
800122e: 687b ldr r3, [r7, #4]
8001230: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8001232: 2301 movs r3, #1
8001234: e007 b.n 8001246 <ADC_Disable+0xda>
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
8001236: 687b ldr r3, [r7, #4]
8001238: 681b ldr r3, [r3, #0]
800123a: 689b ldr r3, [r3, #8]
800123c: 2201 movs r2, #1
800123e: 4013 ands r3, r2
8001240: 2b01 cmp r3, #1
8001242: d0dc beq.n 80011fe <ADC_Disable+0x92>
}
}
}
/* Return HAL status */
return HAL_OK;
8001244: 2300 movs r3, #0
}
8001246: 0018 movs r0, r3
8001248: 46bd mov sp, r7
800124a: b004 add sp, #16
800124c: bd80 pop {r7, pc}
0800124e <ADC_ConversionStop>:
* stopped to disable the ADC.
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
{
800124e: b580 push {r7, lr}
8001250: b084 sub sp, #16
8001252: af00 add r7, sp, #0
8001254: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8001256: 2300 movs r3, #0
8001258: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Verification if ADC is not already stopped on regular group to bypass */
/* this function if not needed. */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
800125a: 687b ldr r3, [r7, #4]
800125c: 681b ldr r3, [r3, #0]
800125e: 689b ldr r3, [r3, #8]
8001260: 2204 movs r2, #4
8001262: 4013 ands r3, r2
8001264: d03a beq.n 80012dc <ADC_ConversionStop+0x8e>
{
/* Stop potential conversion on going on regular group */
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
8001266: 687b ldr r3, [r7, #4]
8001268: 681b ldr r3, [r3, #0]
800126a: 689b ldr r3, [r3, #8]
800126c: 2204 movs r2, #4
800126e: 4013 ands r3, r2
8001270: 2b04 cmp r3, #4
8001272: d10d bne.n 8001290 <ADC_ConversionStop+0x42>
HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
8001274: 687b ldr r3, [r7, #4]
8001276: 681b ldr r3, [r3, #0]
8001278: 689b ldr r3, [r3, #8]
800127a: 2202 movs r2, #2
800127c: 4013 ands r3, r2
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
800127e: d107 bne.n 8001290 <ADC_ConversionStop+0x42>
{
/* Stop conversions on regular group */
hadc->Instance->CR |= ADC_CR_ADSTP;
8001280: 687b ldr r3, [r7, #4]
8001282: 681b ldr r3, [r3, #0]
8001284: 689a ldr r2, [r3, #8]
8001286: 687b ldr r3, [r7, #4]
8001288: 681b ldr r3, [r3, #0]
800128a: 2110 movs r1, #16
800128c: 430a orrs r2, r1
800128e: 609a str r2, [r3, #8]
}
/* Wait for conversion effectively stopped */
/* Get tick count */
tickstart = HAL_GetTick();
8001290: f7ff fb70 bl 8000974 <HAL_GetTick>
8001294: 0003 movs r3, r0
8001296: 60fb str r3, [r7, #12]
while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
8001298: e01a b.n 80012d0 <ADC_ConversionStop+0x82>
{
if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
800129a: f7ff fb6b bl 8000974 <HAL_GetTick>
800129e: 0002 movs r2, r0
80012a0: 68fb ldr r3, [r7, #12]
80012a2: 1ad3 subs r3, r2, r3
80012a4: 2b02 cmp r3, #2
80012a6: d913 bls.n 80012d0 <ADC_ConversionStop+0x82>
{
/* New check to avoid false timeout detection in case of preemption */
if((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
80012a8: 687b ldr r3, [r7, #4]
80012aa: 681b ldr r3, [r3, #0]
80012ac: 689b ldr r3, [r3, #8]
80012ae: 2204 movs r2, #4
80012b0: 4013 ands r3, r2
80012b2: d00d beq.n 80012d0 <ADC_ConversionStop+0x82>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80012b4: 687b ldr r3, [r7, #4]
80012b6: 6b9b ldr r3, [r3, #56] ; 0x38
80012b8: 2210 movs r2, #16
80012ba: 431a orrs r2, r3
80012bc: 687b ldr r3, [r7, #4]
80012be: 639a str r2, [r3, #56] ; 0x38
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80012c0: 687b ldr r3, [r7, #4]
80012c2: 6bdb ldr r3, [r3, #60] ; 0x3c
80012c4: 2201 movs r2, #1
80012c6: 431a orrs r2, r3
80012c8: 687b ldr r3, [r7, #4]
80012ca: 63da str r2, [r3, #60] ; 0x3c
return HAL_ERROR;
80012cc: 2301 movs r3, #1
80012ce: e006 b.n 80012de <ADC_ConversionStop+0x90>
while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
80012d0: 687b ldr r3, [r7, #4]
80012d2: 681b ldr r3, [r3, #0]
80012d4: 689b ldr r3, [r3, #8]
80012d6: 2204 movs r2, #4
80012d8: 4013 ands r3, r2
80012da: d1de bne.n 800129a <ADC_ConversionStop+0x4c>
}
}
}
/* Return HAL status */
return HAL_OK;
80012dc: 2300 movs r3, #0
}
80012de: 0018 movs r0, r3
80012e0: 46bd mov sp, r7
80012e2: b004 add sp, #16
80012e4: bd80 pop {r7, pc}
...
080012e8 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80012e8: b580 push {r7, lr}
80012ea: b082 sub sp, #8
80012ec: af00 add r7, sp, #0
80012ee: 0002 movs r2, r0
80012f0: 1dfb adds r3, r7, #7
80012f2: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80012f4: 1dfb adds r3, r7, #7
80012f6: 781b ldrb r3, [r3, #0]
80012f8: 2b7f cmp r3, #127 ; 0x7f
80012fa: d809 bhi.n 8001310 <__NVIC_EnableIRQ+0x28>
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80012fc: 1dfb adds r3, r7, #7
80012fe: 781b ldrb r3, [r3, #0]
8001300: 001a movs r2, r3
8001302: 231f movs r3, #31
8001304: 401a ands r2, r3
8001306: 4b04 ldr r3, [pc, #16] ; (8001318 <__NVIC_EnableIRQ+0x30>)
8001308: 2101 movs r1, #1
800130a: 4091 lsls r1, r2
800130c: 000a movs r2, r1
800130e: 601a str r2, [r3, #0]
}
}
8001310: 46c0 nop ; (mov r8, r8)
8001312: 46bd mov sp, r7
8001314: b002 add sp, #8
8001316: bd80 pop {r7, pc}
8001318: e000e100 .word 0xe000e100
0800131c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
800131c: b590 push {r4, r7, lr}
800131e: b083 sub sp, #12
8001320: af00 add r7, sp, #0
8001322: 0002 movs r2, r0
8001324: 6039 str r1, [r7, #0]
8001326: 1dfb adds r3, r7, #7
8001328: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
800132a: 1dfb adds r3, r7, #7
800132c: 781b ldrb r3, [r3, #0]
800132e: 2b7f cmp r3, #127 ; 0x7f
8001330: d828 bhi.n 8001384 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001332: 4a2f ldr r2, [pc, #188] ; (80013f0 <__NVIC_SetPriority+0xd4>)
8001334: 1dfb adds r3, r7, #7
8001336: 781b ldrb r3, [r3, #0]
8001338: b25b sxtb r3, r3
800133a: 089b lsrs r3, r3, #2
800133c: 33c0 adds r3, #192 ; 0xc0
800133e: 009b lsls r3, r3, #2
8001340: 589b ldr r3, [r3, r2]
8001342: 1dfa adds r2, r7, #7
8001344: 7812 ldrb r2, [r2, #0]
8001346: 0011 movs r1, r2
8001348: 2203 movs r2, #3
800134a: 400a ands r2, r1
800134c: 00d2 lsls r2, r2, #3
800134e: 21ff movs r1, #255 ; 0xff
8001350: 4091 lsls r1, r2
8001352: 000a movs r2, r1
8001354: 43d2 mvns r2, r2
8001356: 401a ands r2, r3
8001358: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800135a: 683b ldr r3, [r7, #0]
800135c: 019b lsls r3, r3, #6
800135e: 22ff movs r2, #255 ; 0xff
8001360: 401a ands r2, r3
8001362: 1dfb adds r3, r7, #7
8001364: 781b ldrb r3, [r3, #0]
8001366: 0018 movs r0, r3
8001368: 2303 movs r3, #3
800136a: 4003 ands r3, r0
800136c: 00db lsls r3, r3, #3
800136e: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001370: 481f ldr r0, [pc, #124] ; (80013f0 <__NVIC_SetPriority+0xd4>)
8001372: 1dfb adds r3, r7, #7
8001374: 781b ldrb r3, [r3, #0]
8001376: b25b sxtb r3, r3
8001378: 089b lsrs r3, r3, #2
800137a: 430a orrs r2, r1
800137c: 33c0 adds r3, #192 ; 0xc0
800137e: 009b lsls r3, r3, #2
8001380: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8001382: e031 b.n 80013e8 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001384: 4a1b ldr r2, [pc, #108] ; (80013f4 <__NVIC_SetPriority+0xd8>)
8001386: 1dfb adds r3, r7, #7
8001388: 781b ldrb r3, [r3, #0]
800138a: 0019 movs r1, r3
800138c: 230f movs r3, #15
800138e: 400b ands r3, r1
8001390: 3b08 subs r3, #8
8001392: 089b lsrs r3, r3, #2
8001394: 3306 adds r3, #6
8001396: 009b lsls r3, r3, #2
8001398: 18d3 adds r3, r2, r3
800139a: 3304 adds r3, #4
800139c: 681b ldr r3, [r3, #0]
800139e: 1dfa adds r2, r7, #7
80013a0: 7812 ldrb r2, [r2, #0]
80013a2: 0011 movs r1, r2
80013a4: 2203 movs r2, #3
80013a6: 400a ands r2, r1
80013a8: 00d2 lsls r2, r2, #3
80013aa: 21ff movs r1, #255 ; 0xff
80013ac: 4091 lsls r1, r2
80013ae: 000a movs r2, r1
80013b0: 43d2 mvns r2, r2
80013b2: 401a ands r2, r3
80013b4: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80013b6: 683b ldr r3, [r7, #0]
80013b8: 019b lsls r3, r3, #6
80013ba: 22ff movs r2, #255 ; 0xff
80013bc: 401a ands r2, r3
80013be: 1dfb adds r3, r7, #7
80013c0: 781b ldrb r3, [r3, #0]
80013c2: 0018 movs r0, r3
80013c4: 2303 movs r3, #3
80013c6: 4003 ands r3, r0
80013c8: 00db lsls r3, r3, #3
80013ca: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80013cc: 4809 ldr r0, [pc, #36] ; (80013f4 <__NVIC_SetPriority+0xd8>)
80013ce: 1dfb adds r3, r7, #7
80013d0: 781b ldrb r3, [r3, #0]
80013d2: 001c movs r4, r3
80013d4: 230f movs r3, #15
80013d6: 4023 ands r3, r4
80013d8: 3b08 subs r3, #8
80013da: 089b lsrs r3, r3, #2
80013dc: 430a orrs r2, r1
80013de: 3306 adds r3, #6
80013e0: 009b lsls r3, r3, #2
80013e2: 18c3 adds r3, r0, r3
80013e4: 3304 adds r3, #4
80013e6: 601a str r2, [r3, #0]
}
80013e8: 46c0 nop ; (mov r8, r8)
80013ea: 46bd mov sp, r7
80013ec: b003 add sp, #12
80013ee: bd90 pop {r4, r7, pc}
80013f0: e000e100 .word 0xe000e100
80013f4: e000ed00 .word 0xe000ed00
080013f8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80013f8: b580 push {r7, lr}
80013fa: b082 sub sp, #8
80013fc: af00 add r7, sp, #0
80013fe: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001400: 687b ldr r3, [r7, #4]
8001402: 1e5a subs r2, r3, #1
8001404: 2380 movs r3, #128 ; 0x80
8001406: 045b lsls r3, r3, #17
8001408: 429a cmp r2, r3
800140a: d301 bcc.n 8001410 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
800140c: 2301 movs r3, #1
800140e: e010 b.n 8001432 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001410: 4b0a ldr r3, [pc, #40] ; (800143c <SysTick_Config+0x44>)
8001412: 687a ldr r2, [r7, #4]
8001414: 3a01 subs r2, #1
8001416: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001418: 2301 movs r3, #1
800141a: 425b negs r3, r3
800141c: 2103 movs r1, #3
800141e: 0018 movs r0, r3
8001420: f7ff ff7c bl 800131c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001424: 4b05 ldr r3, [pc, #20] ; (800143c <SysTick_Config+0x44>)
8001426: 2200 movs r2, #0
8001428: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800142a: 4b04 ldr r3, [pc, #16] ; (800143c <SysTick_Config+0x44>)
800142c: 2207 movs r2, #7
800142e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001430: 2300 movs r3, #0
}
8001432: 0018 movs r0, r3
8001434: 46bd mov sp, r7
8001436: b002 add sp, #8
8001438: bd80 pop {r7, pc}
800143a: 46c0 nop ; (mov r8, r8)
800143c: e000e010 .word 0xe000e010
08001440 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001440: b580 push {r7, lr}
8001442: b084 sub sp, #16
8001444: af00 add r7, sp, #0
8001446: 60b9 str r1, [r7, #8]
8001448: 607a str r2, [r7, #4]
800144a: 210f movs r1, #15
800144c: 187b adds r3, r7, r1
800144e: 1c02 adds r2, r0, #0
8001450: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
8001452: 68ba ldr r2, [r7, #8]
8001454: 187b adds r3, r7, r1
8001456: 781b ldrb r3, [r3, #0]
8001458: b25b sxtb r3, r3
800145a: 0011 movs r1, r2
800145c: 0018 movs r0, r3
800145e: f7ff ff5d bl 800131c <__NVIC_SetPriority>
}
8001462: 46c0 nop ; (mov r8, r8)
8001464: 46bd mov sp, r7
8001466: b004 add sp, #16
8001468: bd80 pop {r7, pc}
0800146a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800146a: b580 push {r7, lr}
800146c: b082 sub sp, #8
800146e: af00 add r7, sp, #0
8001470: 0002 movs r2, r0
8001472: 1dfb adds r3, r7, #7
8001474: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001476: 1dfb adds r3, r7, #7
8001478: 781b ldrb r3, [r3, #0]
800147a: b25b sxtb r3, r3
800147c: 0018 movs r0, r3
800147e: f7ff ff33 bl 80012e8 <__NVIC_EnableIRQ>
}
8001482: 46c0 nop ; (mov r8, r8)
8001484: 46bd mov sp, r7
8001486: b002 add sp, #8
8001488: bd80 pop {r7, pc}
0800148a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800148a: b580 push {r7, lr}
800148c: b082 sub sp, #8
800148e: af00 add r7, sp, #0
8001490: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001492: 687b ldr r3, [r7, #4]
8001494: 0018 movs r0, r3
8001496: f7ff ffaf bl 80013f8 <SysTick_Config>
800149a: 0003 movs r3, r0
}
800149c: 0018 movs r0, r3
800149e: 46bd mov sp, r7
80014a0: b002 add sp, #8
80014a2: bd80 pop {r7, pc}
080014a4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80014a4: b580 push {r7, lr}
80014a6: b086 sub sp, #24
80014a8: af00 add r7, sp, #0
80014aa: 6078 str r0, [r7, #4]
80014ac: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80014ae: 2300 movs r3, #0
80014b0: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80014b2: e14f b.n 8001754 <HAL_GPIO_Init+0x2b0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80014b4: 683b ldr r3, [r7, #0]
80014b6: 681b ldr r3, [r3, #0]
80014b8: 2101 movs r1, #1
80014ba: 697a ldr r2, [r7, #20]
80014bc: 4091 lsls r1, r2
80014be: 000a movs r2, r1
80014c0: 4013 ands r3, r2
80014c2: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
80014c4: 68fb ldr r3, [r7, #12]
80014c6: 2b00 cmp r3, #0
80014c8: d100 bne.n 80014cc <HAL_GPIO_Init+0x28>
80014ca: e140 b.n 800174e <HAL_GPIO_Init+0x2aa>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
80014cc: 683b ldr r3, [r7, #0]
80014ce: 685b ldr r3, [r3, #4]
80014d0: 2203 movs r2, #3
80014d2: 4013 ands r3, r2
80014d4: 2b01 cmp r3, #1
80014d6: d005 beq.n 80014e4 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80014d8: 683b ldr r3, [r7, #0]
80014da: 685b ldr r3, [r3, #4]
80014dc: 2203 movs r2, #3
80014de: 4013 ands r3, r2
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
80014e0: 2b02 cmp r3, #2
80014e2: d130 bne.n 8001546 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80014e4: 687b ldr r3, [r7, #4]
80014e6: 689b ldr r3, [r3, #8]
80014e8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
80014ea: 697b ldr r3, [r7, #20]
80014ec: 005b lsls r3, r3, #1
80014ee: 2203 movs r2, #3
80014f0: 409a lsls r2, r3
80014f2: 0013 movs r3, r2
80014f4: 43da mvns r2, r3
80014f6: 693b ldr r3, [r7, #16]
80014f8: 4013 ands r3, r2
80014fa: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
80014fc: 683b ldr r3, [r7, #0]
80014fe: 68da ldr r2, [r3, #12]
8001500: 697b ldr r3, [r7, #20]
8001502: 005b lsls r3, r3, #1
8001504: 409a lsls r2, r3
8001506: 0013 movs r3, r2
8001508: 693a ldr r2, [r7, #16]
800150a: 4313 orrs r3, r2
800150c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800150e: 687b ldr r3, [r7, #4]
8001510: 693a ldr r2, [r7, #16]
8001512: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001514: 687b ldr r3, [r7, #4]
8001516: 685b ldr r3, [r3, #4]
8001518: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800151a: 2201 movs r2, #1
800151c: 697b ldr r3, [r7, #20]
800151e: 409a lsls r2, r3
8001520: 0013 movs r3, r2
8001522: 43da mvns r2, r3
8001524: 693b ldr r3, [r7, #16]
8001526: 4013 ands r3, r2
8001528: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800152a: 683b ldr r3, [r7, #0]
800152c: 685b ldr r3, [r3, #4]
800152e: 091b lsrs r3, r3, #4
8001530: 2201 movs r2, #1
8001532: 401a ands r2, r3
8001534: 697b ldr r3, [r7, #20]
8001536: 409a lsls r2, r3
8001538: 0013 movs r3, r2
800153a: 693a ldr r2, [r7, #16]
800153c: 4313 orrs r3, r2
800153e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001540: 687b ldr r3, [r7, #4]
8001542: 693a ldr r2, [r7, #16]
8001544: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001546: 683b ldr r3, [r7, #0]
8001548: 685b ldr r3, [r3, #4]
800154a: 2203 movs r2, #3
800154c: 4013 ands r3, r2
800154e: 2b03 cmp r3, #3
8001550: d017 beq.n 8001582 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001552: 687b ldr r3, [r7, #4]
8001554: 68db ldr r3, [r3, #12]
8001556: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8001558: 697b ldr r3, [r7, #20]
800155a: 005b lsls r3, r3, #1
800155c: 2203 movs r2, #3
800155e: 409a lsls r2, r3
8001560: 0013 movs r3, r2
8001562: 43da mvns r2, r3
8001564: 693b ldr r3, [r7, #16]
8001566: 4013 ands r3, r2
8001568: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
800156a: 683b ldr r3, [r7, #0]
800156c: 689a ldr r2, [r3, #8]
800156e: 697b ldr r3, [r7, #20]
8001570: 005b lsls r3, r3, #1
8001572: 409a lsls r2, r3
8001574: 0013 movs r3, r2
8001576: 693a ldr r2, [r7, #16]
8001578: 4313 orrs r3, r2
800157a: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
800157c: 687b ldr r3, [r7, #4]
800157e: 693a ldr r2, [r7, #16]
8001580: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001582: 683b ldr r3, [r7, #0]
8001584: 685b ldr r3, [r3, #4]
8001586: 2203 movs r2, #3
8001588: 4013 ands r3, r2
800158a: 2b02 cmp r3, #2
800158c: d123 bne.n 80015d6 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
800158e: 697b ldr r3, [r7, #20]
8001590: 08da lsrs r2, r3, #3
8001592: 687b ldr r3, [r7, #4]
8001594: 3208 adds r2, #8
8001596: 0092 lsls r2, r2, #2
8001598: 58d3 ldr r3, [r2, r3]
800159a: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
800159c: 697b ldr r3, [r7, #20]
800159e: 2207 movs r2, #7
80015a0: 4013 ands r3, r2
80015a2: 009b lsls r3, r3, #2
80015a4: 220f movs r2, #15
80015a6: 409a lsls r2, r3
80015a8: 0013 movs r3, r2
80015aa: 43da mvns r2, r3
80015ac: 693b ldr r3, [r7, #16]
80015ae: 4013 ands r3, r2
80015b0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80015b2: 683b ldr r3, [r7, #0]
80015b4: 691a ldr r2, [r3, #16]
80015b6: 697b ldr r3, [r7, #20]
80015b8: 2107 movs r1, #7
80015ba: 400b ands r3, r1
80015bc: 009b lsls r3, r3, #2
80015be: 409a lsls r2, r3
80015c0: 0013 movs r3, r2
80015c2: 693a ldr r2, [r7, #16]
80015c4: 4313 orrs r3, r2
80015c6: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
80015c8: 697b ldr r3, [r7, #20]
80015ca: 08da lsrs r2, r3, #3
80015cc: 687b ldr r3, [r7, #4]
80015ce: 3208 adds r2, #8
80015d0: 0092 lsls r2, r2, #2
80015d2: 6939 ldr r1, [r7, #16]
80015d4: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80015d6: 687b ldr r3, [r7, #4]
80015d8: 681b ldr r3, [r3, #0]
80015da: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
80015dc: 697b ldr r3, [r7, #20]
80015de: 005b lsls r3, r3, #1
80015e0: 2203 movs r2, #3
80015e2: 409a lsls r2, r3
80015e4: 0013 movs r3, r2
80015e6: 43da mvns r2, r3
80015e8: 693b ldr r3, [r7, #16]
80015ea: 4013 ands r3, r2
80015ec: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
80015ee: 683b ldr r3, [r7, #0]
80015f0: 685b ldr r3, [r3, #4]
80015f2: 2203 movs r2, #3
80015f4: 401a ands r2, r3
80015f6: 697b ldr r3, [r7, #20]
80015f8: 005b lsls r3, r3, #1
80015fa: 409a lsls r2, r3
80015fc: 0013 movs r3, r2
80015fe: 693a ldr r2, [r7, #16]
8001600: 4313 orrs r3, r2
8001602: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001604: 687b ldr r3, [r7, #4]
8001606: 693a ldr r2, [r7, #16]
8001608: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800160a: 683b ldr r3, [r7, #0]
800160c: 685a ldr r2, [r3, #4]
800160e: 23c0 movs r3, #192 ; 0xc0
8001610: 029b lsls r3, r3, #10
8001612: 4013 ands r3, r2
8001614: d100 bne.n 8001618 <HAL_GPIO_Init+0x174>
8001616: e09a b.n 800174e <HAL_GPIO_Init+0x2aa>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001618: 4b54 ldr r3, [pc, #336] ; (800176c <HAL_GPIO_Init+0x2c8>)
800161a: 699a ldr r2, [r3, #24]
800161c: 4b53 ldr r3, [pc, #332] ; (800176c <HAL_GPIO_Init+0x2c8>)
800161e: 2101 movs r1, #1
8001620: 430a orrs r2, r1
8001622: 619a str r2, [r3, #24]
8001624: 4b51 ldr r3, [pc, #324] ; (800176c <HAL_GPIO_Init+0x2c8>)
8001626: 699b ldr r3, [r3, #24]
8001628: 2201 movs r2, #1
800162a: 4013 ands r3, r2
800162c: 60bb str r3, [r7, #8]
800162e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001630: 4a4f ldr r2, [pc, #316] ; (8001770 <HAL_GPIO_Init+0x2cc>)
8001632: 697b ldr r3, [r7, #20]
8001634: 089b lsrs r3, r3, #2
8001636: 3302 adds r3, #2
8001638: 009b lsls r3, r3, #2
800163a: 589b ldr r3, [r3, r2]
800163c: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
800163e: 697b ldr r3, [r7, #20]
8001640: 2203 movs r2, #3
8001642: 4013 ands r3, r2
8001644: 009b lsls r3, r3, #2
8001646: 220f movs r2, #15
8001648: 409a lsls r2, r3
800164a: 0013 movs r3, r2
800164c: 43da mvns r2, r3
800164e: 693b ldr r3, [r7, #16]
8001650: 4013 ands r3, r2
8001652: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001654: 687a ldr r2, [r7, #4]
8001656: 2390 movs r3, #144 ; 0x90
8001658: 05db lsls r3, r3, #23
800165a: 429a cmp r2, r3
800165c: d013 beq.n 8001686 <HAL_GPIO_Init+0x1e2>
800165e: 687b ldr r3, [r7, #4]
8001660: 4a44 ldr r2, [pc, #272] ; (8001774 <HAL_GPIO_Init+0x2d0>)
8001662: 4293 cmp r3, r2
8001664: d00d beq.n 8001682 <HAL_GPIO_Init+0x1de>
8001666: 687b ldr r3, [r7, #4]
8001668: 4a43 ldr r2, [pc, #268] ; (8001778 <HAL_GPIO_Init+0x2d4>)
800166a: 4293 cmp r3, r2
800166c: d007 beq.n 800167e <HAL_GPIO_Init+0x1da>
800166e: 687b ldr r3, [r7, #4]
8001670: 4a42 ldr r2, [pc, #264] ; (800177c <HAL_GPIO_Init+0x2d8>)
8001672: 4293 cmp r3, r2
8001674: d101 bne.n 800167a <HAL_GPIO_Init+0x1d6>
8001676: 2303 movs r3, #3
8001678: e006 b.n 8001688 <HAL_GPIO_Init+0x1e4>
800167a: 2305 movs r3, #5
800167c: e004 b.n 8001688 <HAL_GPIO_Init+0x1e4>
800167e: 2302 movs r3, #2
8001680: e002 b.n 8001688 <HAL_GPIO_Init+0x1e4>
8001682: 2301 movs r3, #1
8001684: e000 b.n 8001688 <HAL_GPIO_Init+0x1e4>
8001686: 2300 movs r3, #0
8001688: 697a ldr r2, [r7, #20]
800168a: 2103 movs r1, #3
800168c: 400a ands r2, r1
800168e: 0092 lsls r2, r2, #2
8001690: 4093 lsls r3, r2
8001692: 693a ldr r2, [r7, #16]
8001694: 4313 orrs r3, r2
8001696: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001698: 4935 ldr r1, [pc, #212] ; (8001770 <HAL_GPIO_Init+0x2cc>)
800169a: 697b ldr r3, [r7, #20]
800169c: 089b lsrs r3, r3, #2
800169e: 3302 adds r3, #2
80016a0: 009b lsls r3, r3, #2
80016a2: 693a ldr r2, [r7, #16]
80016a4: 505a str r2, [r3, r1]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80016a6: 4b36 ldr r3, [pc, #216] ; (8001780 <HAL_GPIO_Init+0x2dc>)
80016a8: 681b ldr r3, [r3, #0]
80016aa: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80016ac: 68fb ldr r3, [r7, #12]
80016ae: 43da mvns r2, r3
80016b0: 693b ldr r3, [r7, #16]
80016b2: 4013 ands r3, r2
80016b4: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80016b6: 683b ldr r3, [r7, #0]
80016b8: 685a ldr r2, [r3, #4]
80016ba: 2380 movs r3, #128 ; 0x80
80016bc: 025b lsls r3, r3, #9
80016be: 4013 ands r3, r2
80016c0: d003 beq.n 80016ca <HAL_GPIO_Init+0x226>
{
temp |= iocurrent;
80016c2: 693a ldr r2, [r7, #16]
80016c4: 68fb ldr r3, [r7, #12]
80016c6: 4313 orrs r3, r2
80016c8: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
80016ca: 4b2d ldr r3, [pc, #180] ; (8001780 <HAL_GPIO_Init+0x2dc>)
80016cc: 693a ldr r2, [r7, #16]
80016ce: 601a str r2, [r3, #0]
temp = EXTI->EMR;
80016d0: 4b2b ldr r3, [pc, #172] ; (8001780 <HAL_GPIO_Init+0x2dc>)
80016d2: 685b ldr r3, [r3, #4]
80016d4: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80016d6: 68fb ldr r3, [r7, #12]
80016d8: 43da mvns r2, r3
80016da: 693b ldr r3, [r7, #16]
80016dc: 4013 ands r3, r2
80016de: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
80016e0: 683b ldr r3, [r7, #0]
80016e2: 685a ldr r2, [r3, #4]
80016e4: 2380 movs r3, #128 ; 0x80
80016e6: 029b lsls r3, r3, #10
80016e8: 4013 ands r3, r2
80016ea: d003 beq.n 80016f4 <HAL_GPIO_Init+0x250>
{
temp |= iocurrent;
80016ec: 693a ldr r2, [r7, #16]
80016ee: 68fb ldr r3, [r7, #12]
80016f0: 4313 orrs r3, r2
80016f2: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
80016f4: 4b22 ldr r3, [pc, #136] ; (8001780 <HAL_GPIO_Init+0x2dc>)
80016f6: 693a ldr r2, [r7, #16]
80016f8: 605a str r2, [r3, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80016fa: 4b21 ldr r3, [pc, #132] ; (8001780 <HAL_GPIO_Init+0x2dc>)
80016fc: 689b ldr r3, [r3, #8]
80016fe: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001700: 68fb ldr r3, [r7, #12]
8001702: 43da mvns r2, r3
8001704: 693b ldr r3, [r7, #16]
8001706: 4013 ands r3, r2
8001708: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
800170a: 683b ldr r3, [r7, #0]
800170c: 685a ldr r2, [r3, #4]
800170e: 2380 movs r3, #128 ; 0x80
8001710: 035b lsls r3, r3, #13
8001712: 4013 ands r3, r2
8001714: d003 beq.n 800171e <HAL_GPIO_Init+0x27a>
{
temp |= iocurrent;
8001716: 693a ldr r2, [r7, #16]
8001718: 68fb ldr r3, [r7, #12]
800171a: 4313 orrs r3, r2
800171c: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
800171e: 4b18 ldr r3, [pc, #96] ; (8001780 <HAL_GPIO_Init+0x2dc>)
8001720: 693a ldr r2, [r7, #16]
8001722: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
8001724: 4b16 ldr r3, [pc, #88] ; (8001780 <HAL_GPIO_Init+0x2dc>)
8001726: 68db ldr r3, [r3, #12]
8001728: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800172a: 68fb ldr r3, [r7, #12]
800172c: 43da mvns r2, r3
800172e: 693b ldr r3, [r7, #16]
8001730: 4013 ands r3, r2
8001732: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001734: 683b ldr r3, [r7, #0]
8001736: 685a ldr r2, [r3, #4]
8001738: 2380 movs r3, #128 ; 0x80
800173a: 039b lsls r3, r3, #14
800173c: 4013 ands r3, r2
800173e: d003 beq.n 8001748 <HAL_GPIO_Init+0x2a4>
{
temp |= iocurrent;
8001740: 693a ldr r2, [r7, #16]
8001742: 68fb ldr r3, [r7, #12]
8001744: 4313 orrs r3, r2
8001746: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8001748: 4b0d ldr r3, [pc, #52] ; (8001780 <HAL_GPIO_Init+0x2dc>)
800174a: 693a ldr r2, [r7, #16]
800174c: 60da str r2, [r3, #12]
}
}
position++;
800174e: 697b ldr r3, [r7, #20]
8001750: 3301 adds r3, #1
8001752: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001754: 683b ldr r3, [r7, #0]
8001756: 681a ldr r2, [r3, #0]
8001758: 697b ldr r3, [r7, #20]
800175a: 40da lsrs r2, r3
800175c: 1e13 subs r3, r2, #0
800175e: d000 beq.n 8001762 <HAL_GPIO_Init+0x2be>
8001760: e6a8 b.n 80014b4 <HAL_GPIO_Init+0x10>
}
}
8001762: 46c0 nop ; (mov r8, r8)
8001764: 46c0 nop ; (mov r8, r8)
8001766: 46bd mov sp, r7
8001768: b006 add sp, #24
800176a: bd80 pop {r7, pc}
800176c: 40021000 .word 0x40021000
8001770: 40010000 .word 0x40010000
8001774: 48000400 .word 0x48000400
8001778: 48000800 .word 0x48000800
800177c: 48000c00 .word 0x48000c00
8001780: 40010400 .word 0x40010400
08001784 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001784: b580 push {r7, lr}
8001786: b084 sub sp, #16
8001788: af00 add r7, sp, #0
800178a: 6078 str r0, [r7, #4]
800178c: 000a movs r2, r1
800178e: 1cbb adds r3, r7, #2
8001790: 801a strh r2, [r3, #0]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001792: 687b ldr r3, [r7, #4]
8001794: 691b ldr r3, [r3, #16]
8001796: 1cba adds r2, r7, #2
8001798: 8812 ldrh r2, [r2, #0]
800179a: 4013 ands r3, r2
800179c: d004 beq.n 80017a8 <HAL_GPIO_ReadPin+0x24>
{
bitstatus = GPIO_PIN_SET;
800179e: 230f movs r3, #15
80017a0: 18fb adds r3, r7, r3
80017a2: 2201 movs r2, #1
80017a4: 701a strb r2, [r3, #0]
80017a6: e003 b.n 80017b0 <HAL_GPIO_ReadPin+0x2c>
}
else
{
bitstatus = GPIO_PIN_RESET;
80017a8: 230f movs r3, #15
80017aa: 18fb adds r3, r7, r3
80017ac: 2200 movs r2, #0
80017ae: 701a strb r2, [r3, #0]
}
return bitstatus;
80017b0: 230f movs r3, #15
80017b2: 18fb adds r3, r7, r3
80017b4: 781b ldrb r3, [r3, #0]
}
80017b6: 0018 movs r0, r3
80017b8: 46bd mov sp, r7
80017ba: b004 add sp, #16
80017bc: bd80 pop {r7, pc}
080017be <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80017be: b580 push {r7, lr}
80017c0: b082 sub sp, #8
80017c2: af00 add r7, sp, #0
80017c4: 6078 str r0, [r7, #4]
80017c6: 0008 movs r0, r1
80017c8: 0011 movs r1, r2
80017ca: 1cbb adds r3, r7, #2
80017cc: 1c02 adds r2, r0, #0
80017ce: 801a strh r2, [r3, #0]
80017d0: 1c7b adds r3, r7, #1
80017d2: 1c0a adds r2, r1, #0
80017d4: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80017d6: 1c7b adds r3, r7, #1
80017d8: 781b ldrb r3, [r3, #0]
80017da: 2b00 cmp r3, #0
80017dc: d004 beq.n 80017e8 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
80017de: 1cbb adds r3, r7, #2
80017e0: 881a ldrh r2, [r3, #0]
80017e2: 687b ldr r3, [r7, #4]
80017e4: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
80017e6: e003 b.n 80017f0 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
80017e8: 1cbb adds r3, r7, #2
80017ea: 881a ldrh r2, [r3, #0]
80017ec: 687b ldr r3, [r7, #4]
80017ee: 629a str r2, [r3, #40] ; 0x28
}
80017f0: 46c0 nop ; (mov r8, r8)
80017f2: 46bd mov sp, r7
80017f4: b002 add sp, #8
80017f6: bd80 pop {r7, pc}
080017f8 <HAL_GPIO_EXTI_IRQHandler>:
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
80017f8: b580 push {r7, lr}
80017fa: b082 sub sp, #8
80017fc: af00 add r7, sp, #0
80017fe: 0002 movs r2, r0
8001800: 1dbb adds r3, r7, #6
8001802: 801a strh r2, [r3, #0]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
8001804: 4b09 ldr r3, [pc, #36] ; (800182c <HAL_GPIO_EXTI_IRQHandler+0x34>)
8001806: 695b ldr r3, [r3, #20]
8001808: 1dba adds r2, r7, #6
800180a: 8812 ldrh r2, [r2, #0]
800180c: 4013 ands r3, r2
800180e: d008 beq.n 8001822 <HAL_GPIO_EXTI_IRQHandler+0x2a>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8001810: 4b06 ldr r3, [pc, #24] ; (800182c <HAL_GPIO_EXTI_IRQHandler+0x34>)
8001812: 1dba adds r2, r7, #6
8001814: 8812 ldrh r2, [r2, #0]
8001816: 615a str r2, [r3, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8001818: 1dbb adds r3, r7, #6
800181a: 881b ldrh r3, [r3, #0]
800181c: 0018 movs r0, r3
800181e: f001 ff87 bl 8003730 <HAL_GPIO_EXTI_Callback>
}
}
8001822: 46c0 nop ; (mov r8, r8)
8001824: 46bd mov sp, r7
8001826: b002 add sp, #8
8001828: bd80 pop {r7, pc}
800182a: 46c0 nop ; (mov r8, r8)
800182c: 40010400 .word 0x40010400
08001830 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001830: b580 push {r7, lr}
8001832: b088 sub sp, #32
8001834: af00 add r7, sp, #0
8001836: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001838: 687b ldr r3, [r7, #4]
800183a: 2b00 cmp r3, #0
800183c: d101 bne.n 8001842 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800183e: 2301 movs r3, #1
8001840: e301 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001842: 687b ldr r3, [r7, #4]
8001844: 681b ldr r3, [r3, #0]
8001846: 2201 movs r2, #1
8001848: 4013 ands r3, r2
800184a: d100 bne.n 800184e <HAL_RCC_OscConfig+0x1e>
800184c: e08d b.n 800196a <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
800184e: 4bc3 ldr r3, [pc, #780] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001850: 685b ldr r3, [r3, #4]
8001852: 220c movs r2, #12
8001854: 4013 ands r3, r2
8001856: 2b04 cmp r3, #4
8001858: d00e beq.n 8001878 <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
800185a: 4bc0 ldr r3, [pc, #768] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
800185c: 685b ldr r3, [r3, #4]
800185e: 220c movs r2, #12
8001860: 4013 ands r3, r2
8001862: 2b08 cmp r3, #8
8001864: d116 bne.n 8001894 <HAL_RCC_OscConfig+0x64>
8001866: 4bbd ldr r3, [pc, #756] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001868: 685a ldr r2, [r3, #4]
800186a: 2380 movs r3, #128 ; 0x80
800186c: 025b lsls r3, r3, #9
800186e: 401a ands r2, r3
8001870: 2380 movs r3, #128 ; 0x80
8001872: 025b lsls r3, r3, #9
8001874: 429a cmp r2, r3
8001876: d10d bne.n 8001894 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001878: 4bb8 ldr r3, [pc, #736] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
800187a: 681a ldr r2, [r3, #0]
800187c: 2380 movs r3, #128 ; 0x80
800187e: 029b lsls r3, r3, #10
8001880: 4013 ands r3, r2
8001882: d100 bne.n 8001886 <HAL_RCC_OscConfig+0x56>
8001884: e070 b.n 8001968 <HAL_RCC_OscConfig+0x138>
8001886: 687b ldr r3, [r7, #4]
8001888: 685b ldr r3, [r3, #4]
800188a: 2b00 cmp r3, #0
800188c: d000 beq.n 8001890 <HAL_RCC_OscConfig+0x60>
800188e: e06b b.n 8001968 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
8001890: 2301 movs r3, #1
8001892: e2d8 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001894: 687b ldr r3, [r7, #4]
8001896: 685b ldr r3, [r3, #4]
8001898: 2b01 cmp r3, #1
800189a: d107 bne.n 80018ac <HAL_RCC_OscConfig+0x7c>
800189c: 4baf ldr r3, [pc, #700] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
800189e: 681a ldr r2, [r3, #0]
80018a0: 4bae ldr r3, [pc, #696] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018a2: 2180 movs r1, #128 ; 0x80
80018a4: 0249 lsls r1, r1, #9
80018a6: 430a orrs r2, r1
80018a8: 601a str r2, [r3, #0]
80018aa: e02f b.n 800190c <HAL_RCC_OscConfig+0xdc>
80018ac: 687b ldr r3, [r7, #4]
80018ae: 685b ldr r3, [r3, #4]
80018b0: 2b00 cmp r3, #0
80018b2: d10c bne.n 80018ce <HAL_RCC_OscConfig+0x9e>
80018b4: 4ba9 ldr r3, [pc, #676] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018b6: 681a ldr r2, [r3, #0]
80018b8: 4ba8 ldr r3, [pc, #672] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018ba: 49a9 ldr r1, [pc, #676] ; (8001b60 <HAL_RCC_OscConfig+0x330>)
80018bc: 400a ands r2, r1
80018be: 601a str r2, [r3, #0]
80018c0: 4ba6 ldr r3, [pc, #664] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018c2: 681a ldr r2, [r3, #0]
80018c4: 4ba5 ldr r3, [pc, #660] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018c6: 49a7 ldr r1, [pc, #668] ; (8001b64 <HAL_RCC_OscConfig+0x334>)
80018c8: 400a ands r2, r1
80018ca: 601a str r2, [r3, #0]
80018cc: e01e b.n 800190c <HAL_RCC_OscConfig+0xdc>
80018ce: 687b ldr r3, [r7, #4]
80018d0: 685b ldr r3, [r3, #4]
80018d2: 2b05 cmp r3, #5
80018d4: d10e bne.n 80018f4 <HAL_RCC_OscConfig+0xc4>
80018d6: 4ba1 ldr r3, [pc, #644] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018d8: 681a ldr r2, [r3, #0]
80018da: 4ba0 ldr r3, [pc, #640] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018dc: 2180 movs r1, #128 ; 0x80
80018de: 02c9 lsls r1, r1, #11
80018e0: 430a orrs r2, r1
80018e2: 601a str r2, [r3, #0]
80018e4: 4b9d ldr r3, [pc, #628] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018e6: 681a ldr r2, [r3, #0]
80018e8: 4b9c ldr r3, [pc, #624] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018ea: 2180 movs r1, #128 ; 0x80
80018ec: 0249 lsls r1, r1, #9
80018ee: 430a orrs r2, r1
80018f0: 601a str r2, [r3, #0]
80018f2: e00b b.n 800190c <HAL_RCC_OscConfig+0xdc>
80018f4: 4b99 ldr r3, [pc, #612] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018f6: 681a ldr r2, [r3, #0]
80018f8: 4b98 ldr r3, [pc, #608] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80018fa: 4999 ldr r1, [pc, #612] ; (8001b60 <HAL_RCC_OscConfig+0x330>)
80018fc: 400a ands r2, r1
80018fe: 601a str r2, [r3, #0]
8001900: 4b96 ldr r3, [pc, #600] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001902: 681a ldr r2, [r3, #0]
8001904: 4b95 ldr r3, [pc, #596] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001906: 4997 ldr r1, [pc, #604] ; (8001b64 <HAL_RCC_OscConfig+0x334>)
8001908: 400a ands r2, r1
800190a: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800190c: 687b ldr r3, [r7, #4]
800190e: 685b ldr r3, [r3, #4]
8001910: 2b00 cmp r3, #0
8001912: d014 beq.n 800193e <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001914: f7ff f82e bl 8000974 <HAL_GetTick>
8001918: 0003 movs r3, r0
800191a: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800191c: e008 b.n 8001930 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800191e: f7ff f829 bl 8000974 <HAL_GetTick>
8001922: 0002 movs r2, r0
8001924: 69bb ldr r3, [r7, #24]
8001926: 1ad3 subs r3, r2, r3
8001928: 2b64 cmp r3, #100 ; 0x64
800192a: d901 bls.n 8001930 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
800192c: 2303 movs r3, #3
800192e: e28a b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001930: 4b8a ldr r3, [pc, #552] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001932: 681a ldr r2, [r3, #0]
8001934: 2380 movs r3, #128 ; 0x80
8001936: 029b lsls r3, r3, #10
8001938: 4013 ands r3, r2
800193a: d0f0 beq.n 800191e <HAL_RCC_OscConfig+0xee>
800193c: e015 b.n 800196a <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800193e: f7ff f819 bl 8000974 <HAL_GetTick>
8001942: 0003 movs r3, r0
8001944: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001946: e008 b.n 800195a <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001948: f7ff f814 bl 8000974 <HAL_GetTick>
800194c: 0002 movs r2, r0
800194e: 69bb ldr r3, [r7, #24]
8001950: 1ad3 subs r3, r2, r3
8001952: 2b64 cmp r3, #100 ; 0x64
8001954: d901 bls.n 800195a <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
8001956: 2303 movs r3, #3
8001958: e275 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800195a: 4b80 ldr r3, [pc, #512] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
800195c: 681a ldr r2, [r3, #0]
800195e: 2380 movs r3, #128 ; 0x80
8001960: 029b lsls r3, r3, #10
8001962: 4013 ands r3, r2
8001964: d1f0 bne.n 8001948 <HAL_RCC_OscConfig+0x118>
8001966: e000 b.n 800196a <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001968: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800196a: 687b ldr r3, [r7, #4]
800196c: 681b ldr r3, [r3, #0]
800196e: 2202 movs r2, #2
8001970: 4013 ands r3, r2
8001972: d100 bne.n 8001976 <HAL_RCC_OscConfig+0x146>
8001974: e069 b.n 8001a4a <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001976: 4b79 ldr r3, [pc, #484] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001978: 685b ldr r3, [r3, #4]
800197a: 220c movs r2, #12
800197c: 4013 ands r3, r2
800197e: d00b beq.n 8001998 <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8001980: 4b76 ldr r3, [pc, #472] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001982: 685b ldr r3, [r3, #4]
8001984: 220c movs r2, #12
8001986: 4013 ands r3, r2
8001988: 2b08 cmp r3, #8
800198a: d11c bne.n 80019c6 <HAL_RCC_OscConfig+0x196>
800198c: 4b73 ldr r3, [pc, #460] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
800198e: 685a ldr r2, [r3, #4]
8001990: 2380 movs r3, #128 ; 0x80
8001992: 025b lsls r3, r3, #9
8001994: 4013 ands r3, r2
8001996: d116 bne.n 80019c6 <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001998: 4b70 ldr r3, [pc, #448] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
800199a: 681b ldr r3, [r3, #0]
800199c: 2202 movs r2, #2
800199e: 4013 ands r3, r2
80019a0: d005 beq.n 80019ae <HAL_RCC_OscConfig+0x17e>
80019a2: 687b ldr r3, [r7, #4]
80019a4: 68db ldr r3, [r3, #12]
80019a6: 2b01 cmp r3, #1
80019a8: d001 beq.n 80019ae <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
80019aa: 2301 movs r3, #1
80019ac: e24b b.n 8001e46 <HAL_RCC_OscConfig+0x616>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80019ae: 4b6b ldr r3, [pc, #428] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80019b0: 681b ldr r3, [r3, #0]
80019b2: 22f8 movs r2, #248 ; 0xf8
80019b4: 4393 bics r3, r2
80019b6: 0019 movs r1, r3
80019b8: 687b ldr r3, [r7, #4]
80019ba: 691b ldr r3, [r3, #16]
80019bc: 00da lsls r2, r3, #3
80019be: 4b67 ldr r3, [pc, #412] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80019c0: 430a orrs r2, r1
80019c2: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80019c4: e041 b.n 8001a4a <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80019c6: 687b ldr r3, [r7, #4]
80019c8: 68db ldr r3, [r3, #12]
80019ca: 2b00 cmp r3, #0
80019cc: d024 beq.n 8001a18 <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80019ce: 4b63 ldr r3, [pc, #396] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80019d0: 681a ldr r2, [r3, #0]
80019d2: 4b62 ldr r3, [pc, #392] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80019d4: 2101 movs r1, #1
80019d6: 430a orrs r2, r1
80019d8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80019da: f7fe ffcb bl 8000974 <HAL_GetTick>
80019de: 0003 movs r3, r0
80019e0: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80019e2: e008 b.n 80019f6 <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80019e4: f7fe ffc6 bl 8000974 <HAL_GetTick>
80019e8: 0002 movs r2, r0
80019ea: 69bb ldr r3, [r7, #24]
80019ec: 1ad3 subs r3, r2, r3
80019ee: 2b02 cmp r3, #2
80019f0: d901 bls.n 80019f6 <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
80019f2: 2303 movs r3, #3
80019f4: e227 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80019f6: 4b59 ldr r3, [pc, #356] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
80019f8: 681b ldr r3, [r3, #0]
80019fa: 2202 movs r2, #2
80019fc: 4013 ands r3, r2
80019fe: d0f1 beq.n 80019e4 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001a00: 4b56 ldr r3, [pc, #344] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a02: 681b ldr r3, [r3, #0]
8001a04: 22f8 movs r2, #248 ; 0xf8
8001a06: 4393 bics r3, r2
8001a08: 0019 movs r1, r3
8001a0a: 687b ldr r3, [r7, #4]
8001a0c: 691b ldr r3, [r3, #16]
8001a0e: 00da lsls r2, r3, #3
8001a10: 4b52 ldr r3, [pc, #328] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a12: 430a orrs r2, r1
8001a14: 601a str r2, [r3, #0]
8001a16: e018 b.n 8001a4a <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001a18: 4b50 ldr r3, [pc, #320] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a1a: 681a ldr r2, [r3, #0]
8001a1c: 4b4f ldr r3, [pc, #316] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a1e: 2101 movs r1, #1
8001a20: 438a bics r2, r1
8001a22: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a24: f7fe ffa6 bl 8000974 <HAL_GetTick>
8001a28: 0003 movs r3, r0
8001a2a: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001a2c: e008 b.n 8001a40 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001a2e: f7fe ffa1 bl 8000974 <HAL_GetTick>
8001a32: 0002 movs r2, r0
8001a34: 69bb ldr r3, [r7, #24]
8001a36: 1ad3 subs r3, r2, r3
8001a38: 2b02 cmp r3, #2
8001a3a: d901 bls.n 8001a40 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
8001a3c: 2303 movs r3, #3
8001a3e: e202 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001a40: 4b46 ldr r3, [pc, #280] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a42: 681b ldr r3, [r3, #0]
8001a44: 2202 movs r2, #2
8001a46: 4013 ands r3, r2
8001a48: d1f1 bne.n 8001a2e <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001a4a: 687b ldr r3, [r7, #4]
8001a4c: 681b ldr r3, [r3, #0]
8001a4e: 2208 movs r2, #8
8001a50: 4013 ands r3, r2
8001a52: d036 beq.n 8001ac2 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001a54: 687b ldr r3, [r7, #4]
8001a56: 69db ldr r3, [r3, #28]
8001a58: 2b00 cmp r3, #0
8001a5a: d019 beq.n 8001a90 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001a5c: 4b3f ldr r3, [pc, #252] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a5e: 6a5a ldr r2, [r3, #36] ; 0x24
8001a60: 4b3e ldr r3, [pc, #248] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a62: 2101 movs r1, #1
8001a64: 430a orrs r2, r1
8001a66: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a68: f7fe ff84 bl 8000974 <HAL_GetTick>
8001a6c: 0003 movs r3, r0
8001a6e: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001a70: e008 b.n 8001a84 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001a72: f7fe ff7f bl 8000974 <HAL_GetTick>
8001a76: 0002 movs r2, r0
8001a78: 69bb ldr r3, [r7, #24]
8001a7a: 1ad3 subs r3, r2, r3
8001a7c: 2b02 cmp r3, #2
8001a7e: d901 bls.n 8001a84 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
8001a80: 2303 movs r3, #3
8001a82: e1e0 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001a84: 4b35 ldr r3, [pc, #212] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a86: 6a5b ldr r3, [r3, #36] ; 0x24
8001a88: 2202 movs r2, #2
8001a8a: 4013 ands r3, r2
8001a8c: d0f1 beq.n 8001a72 <HAL_RCC_OscConfig+0x242>
8001a8e: e018 b.n 8001ac2 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001a90: 4b32 ldr r3, [pc, #200] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a92: 6a5a ldr r2, [r3, #36] ; 0x24
8001a94: 4b31 ldr r3, [pc, #196] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001a96: 2101 movs r1, #1
8001a98: 438a bics r2, r1
8001a9a: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8001a9c: f7fe ff6a bl 8000974 <HAL_GetTick>
8001aa0: 0003 movs r3, r0
8001aa2: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001aa4: e008 b.n 8001ab8 <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001aa6: f7fe ff65 bl 8000974 <HAL_GetTick>
8001aaa: 0002 movs r2, r0
8001aac: 69bb ldr r3, [r7, #24]
8001aae: 1ad3 subs r3, r2, r3
8001ab0: 2b02 cmp r3, #2
8001ab2: d901 bls.n 8001ab8 <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
8001ab4: 2303 movs r3, #3
8001ab6: e1c6 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001ab8: 4b28 ldr r3, [pc, #160] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001aba: 6a5b ldr r3, [r3, #36] ; 0x24
8001abc: 2202 movs r2, #2
8001abe: 4013 ands r3, r2
8001ac0: d1f1 bne.n 8001aa6 <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001ac2: 687b ldr r3, [r7, #4]
8001ac4: 681b ldr r3, [r3, #0]
8001ac6: 2204 movs r2, #4
8001ac8: 4013 ands r3, r2
8001aca: d100 bne.n 8001ace <HAL_RCC_OscConfig+0x29e>
8001acc: e0b4 b.n 8001c38 <HAL_RCC_OscConfig+0x408>
{
FlagStatus pwrclkchanged = RESET;
8001ace: 201f movs r0, #31
8001ad0: 183b adds r3, r7, r0
8001ad2: 2200 movs r2, #0
8001ad4: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001ad6: 4b21 ldr r3, [pc, #132] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001ad8: 69da ldr r2, [r3, #28]
8001ada: 2380 movs r3, #128 ; 0x80
8001adc: 055b lsls r3, r3, #21
8001ade: 4013 ands r3, r2
8001ae0: d110 bne.n 8001b04 <HAL_RCC_OscConfig+0x2d4>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001ae2: 4b1e ldr r3, [pc, #120] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001ae4: 69da ldr r2, [r3, #28]
8001ae6: 4b1d ldr r3, [pc, #116] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001ae8: 2180 movs r1, #128 ; 0x80
8001aea: 0549 lsls r1, r1, #21
8001aec: 430a orrs r2, r1
8001aee: 61da str r2, [r3, #28]
8001af0: 4b1a ldr r3, [pc, #104] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001af2: 69da ldr r2, [r3, #28]
8001af4: 2380 movs r3, #128 ; 0x80
8001af6: 055b lsls r3, r3, #21
8001af8: 4013 ands r3, r2
8001afa: 60fb str r3, [r7, #12]
8001afc: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8001afe: 183b adds r3, r7, r0
8001b00: 2201 movs r2, #1
8001b02: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001b04: 4b18 ldr r3, [pc, #96] ; (8001b68 <HAL_RCC_OscConfig+0x338>)
8001b06: 681a ldr r2, [r3, #0]
8001b08: 2380 movs r3, #128 ; 0x80
8001b0a: 005b lsls r3, r3, #1
8001b0c: 4013 ands r3, r2
8001b0e: d11a bne.n 8001b46 <HAL_RCC_OscConfig+0x316>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001b10: 4b15 ldr r3, [pc, #84] ; (8001b68 <HAL_RCC_OscConfig+0x338>)
8001b12: 681a ldr r2, [r3, #0]
8001b14: 4b14 ldr r3, [pc, #80] ; (8001b68 <HAL_RCC_OscConfig+0x338>)
8001b16: 2180 movs r1, #128 ; 0x80
8001b18: 0049 lsls r1, r1, #1
8001b1a: 430a orrs r2, r1
8001b1c: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001b1e: f7fe ff29 bl 8000974 <HAL_GetTick>
8001b22: 0003 movs r3, r0
8001b24: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001b26: e008 b.n 8001b3a <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001b28: f7fe ff24 bl 8000974 <HAL_GetTick>
8001b2c: 0002 movs r2, r0
8001b2e: 69bb ldr r3, [r7, #24]
8001b30: 1ad3 subs r3, r2, r3
8001b32: 2b64 cmp r3, #100 ; 0x64
8001b34: d901 bls.n 8001b3a <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8001b36: 2303 movs r3, #3
8001b38: e185 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001b3a: 4b0b ldr r3, [pc, #44] ; (8001b68 <HAL_RCC_OscConfig+0x338>)
8001b3c: 681a ldr r2, [r3, #0]
8001b3e: 2380 movs r3, #128 ; 0x80
8001b40: 005b lsls r3, r3, #1
8001b42: 4013 ands r3, r2
8001b44: d0f0 beq.n 8001b28 <HAL_RCC_OscConfig+0x2f8>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001b46: 687b ldr r3, [r7, #4]
8001b48: 689b ldr r3, [r3, #8]
8001b4a: 2b01 cmp r3, #1
8001b4c: d10e bne.n 8001b6c <HAL_RCC_OscConfig+0x33c>
8001b4e: 4b03 ldr r3, [pc, #12] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001b50: 6a1a ldr r2, [r3, #32]
8001b52: 4b02 ldr r3, [pc, #8] ; (8001b5c <HAL_RCC_OscConfig+0x32c>)
8001b54: 2101 movs r1, #1
8001b56: 430a orrs r2, r1
8001b58: 621a str r2, [r3, #32]
8001b5a: e035 b.n 8001bc8 <HAL_RCC_OscConfig+0x398>
8001b5c: 40021000 .word 0x40021000
8001b60: fffeffff .word 0xfffeffff
8001b64: fffbffff .word 0xfffbffff
8001b68: 40007000 .word 0x40007000
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 689b ldr r3, [r3, #8]
8001b70: 2b00 cmp r3, #0
8001b72: d10c bne.n 8001b8e <HAL_RCC_OscConfig+0x35e>
8001b74: 4bb6 ldr r3, [pc, #728] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001b76: 6a1a ldr r2, [r3, #32]
8001b78: 4bb5 ldr r3, [pc, #724] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001b7a: 2101 movs r1, #1
8001b7c: 438a bics r2, r1
8001b7e: 621a str r2, [r3, #32]
8001b80: 4bb3 ldr r3, [pc, #716] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001b82: 6a1a ldr r2, [r3, #32]
8001b84: 4bb2 ldr r3, [pc, #712] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001b86: 2104 movs r1, #4
8001b88: 438a bics r2, r1
8001b8a: 621a str r2, [r3, #32]
8001b8c: e01c b.n 8001bc8 <HAL_RCC_OscConfig+0x398>
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 689b ldr r3, [r3, #8]
8001b92: 2b05 cmp r3, #5
8001b94: d10c bne.n 8001bb0 <HAL_RCC_OscConfig+0x380>
8001b96: 4bae ldr r3, [pc, #696] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001b98: 6a1a ldr r2, [r3, #32]
8001b9a: 4bad ldr r3, [pc, #692] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001b9c: 2104 movs r1, #4
8001b9e: 430a orrs r2, r1
8001ba0: 621a str r2, [r3, #32]
8001ba2: 4bab ldr r3, [pc, #684] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001ba4: 6a1a ldr r2, [r3, #32]
8001ba6: 4baa ldr r3, [pc, #680] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001ba8: 2101 movs r1, #1
8001baa: 430a orrs r2, r1
8001bac: 621a str r2, [r3, #32]
8001bae: e00b b.n 8001bc8 <HAL_RCC_OscConfig+0x398>
8001bb0: 4ba7 ldr r3, [pc, #668] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001bb2: 6a1a ldr r2, [r3, #32]
8001bb4: 4ba6 ldr r3, [pc, #664] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001bb6: 2101 movs r1, #1
8001bb8: 438a bics r2, r1
8001bba: 621a str r2, [r3, #32]
8001bbc: 4ba4 ldr r3, [pc, #656] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001bbe: 6a1a ldr r2, [r3, #32]
8001bc0: 4ba3 ldr r3, [pc, #652] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001bc2: 2104 movs r1, #4
8001bc4: 438a bics r2, r1
8001bc6: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001bc8: 687b ldr r3, [r7, #4]
8001bca: 689b ldr r3, [r3, #8]
8001bcc: 2b00 cmp r3, #0
8001bce: d014 beq.n 8001bfa <HAL_RCC_OscConfig+0x3ca>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001bd0: f7fe fed0 bl 8000974 <HAL_GetTick>
8001bd4: 0003 movs r3, r0
8001bd6: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001bd8: e009 b.n 8001bee <HAL_RCC_OscConfig+0x3be>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001bda: f7fe fecb bl 8000974 <HAL_GetTick>
8001bde: 0002 movs r2, r0
8001be0: 69bb ldr r3, [r7, #24]
8001be2: 1ad3 subs r3, r2, r3
8001be4: 4a9b ldr r2, [pc, #620] ; (8001e54 <HAL_RCC_OscConfig+0x624>)
8001be6: 4293 cmp r3, r2
8001be8: d901 bls.n 8001bee <HAL_RCC_OscConfig+0x3be>
{
return HAL_TIMEOUT;
8001bea: 2303 movs r3, #3
8001bec: e12b b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001bee: 4b98 ldr r3, [pc, #608] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001bf0: 6a1b ldr r3, [r3, #32]
8001bf2: 2202 movs r2, #2
8001bf4: 4013 ands r3, r2
8001bf6: d0f0 beq.n 8001bda <HAL_RCC_OscConfig+0x3aa>
8001bf8: e013 b.n 8001c22 <HAL_RCC_OscConfig+0x3f2>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001bfa: f7fe febb bl 8000974 <HAL_GetTick>
8001bfe: 0003 movs r3, r0
8001c00: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001c02: e009 b.n 8001c18 <HAL_RCC_OscConfig+0x3e8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001c04: f7fe feb6 bl 8000974 <HAL_GetTick>
8001c08: 0002 movs r2, r0
8001c0a: 69bb ldr r3, [r7, #24]
8001c0c: 1ad3 subs r3, r2, r3
8001c0e: 4a91 ldr r2, [pc, #580] ; (8001e54 <HAL_RCC_OscConfig+0x624>)
8001c10: 4293 cmp r3, r2
8001c12: d901 bls.n 8001c18 <HAL_RCC_OscConfig+0x3e8>
{
return HAL_TIMEOUT;
8001c14: 2303 movs r3, #3
8001c16: e116 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001c18: 4b8d ldr r3, [pc, #564] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c1a: 6a1b ldr r3, [r3, #32]
8001c1c: 2202 movs r2, #2
8001c1e: 4013 ands r3, r2
8001c20: d1f0 bne.n 8001c04 <HAL_RCC_OscConfig+0x3d4>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8001c22: 231f movs r3, #31
8001c24: 18fb adds r3, r7, r3
8001c26: 781b ldrb r3, [r3, #0]
8001c28: 2b01 cmp r3, #1
8001c2a: d105 bne.n 8001c38 <HAL_RCC_OscConfig+0x408>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001c2c: 4b88 ldr r3, [pc, #544] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c2e: 69da ldr r2, [r3, #28]
8001c30: 4b87 ldr r3, [pc, #540] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c32: 4989 ldr r1, [pc, #548] ; (8001e58 <HAL_RCC_OscConfig+0x628>)
8001c34: 400a ands r2, r1
8001c36: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8001c38: 687b ldr r3, [r7, #4]
8001c3a: 681b ldr r3, [r3, #0]
8001c3c: 2210 movs r2, #16
8001c3e: 4013 ands r3, r2
8001c40: d063 beq.n 8001d0a <HAL_RCC_OscConfig+0x4da>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8001c42: 687b ldr r3, [r7, #4]
8001c44: 695b ldr r3, [r3, #20]
8001c46: 2b01 cmp r3, #1
8001c48: d12a bne.n 8001ca0 <HAL_RCC_OscConfig+0x470>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001c4a: 4b81 ldr r3, [pc, #516] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c4c: 6b5a ldr r2, [r3, #52] ; 0x34
8001c4e: 4b80 ldr r3, [pc, #512] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c50: 2104 movs r1, #4
8001c52: 430a orrs r2, r1
8001c54: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8001c56: 4b7e ldr r3, [pc, #504] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c58: 6b5a ldr r2, [r3, #52] ; 0x34
8001c5a: 4b7d ldr r3, [pc, #500] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c5c: 2101 movs r1, #1
8001c5e: 430a orrs r2, r1
8001c60: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001c62: f7fe fe87 bl 8000974 <HAL_GetTick>
8001c66: 0003 movs r3, r0
8001c68: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001c6a: e008 b.n 8001c7e <HAL_RCC_OscConfig+0x44e>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001c6c: f7fe fe82 bl 8000974 <HAL_GetTick>
8001c70: 0002 movs r2, r0
8001c72: 69bb ldr r3, [r7, #24]
8001c74: 1ad3 subs r3, r2, r3
8001c76: 2b02 cmp r3, #2
8001c78: d901 bls.n 8001c7e <HAL_RCC_OscConfig+0x44e>
{
return HAL_TIMEOUT;
8001c7a: 2303 movs r3, #3
8001c7c: e0e3 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8001c7e: 4b74 ldr r3, [pc, #464] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c80: 6b5b ldr r3, [r3, #52] ; 0x34
8001c82: 2202 movs r2, #2
8001c84: 4013 ands r3, r2
8001c86: d0f1 beq.n 8001c6c <HAL_RCC_OscConfig+0x43c>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8001c88: 4b71 ldr r3, [pc, #452] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c8a: 6b5b ldr r3, [r3, #52] ; 0x34
8001c8c: 22f8 movs r2, #248 ; 0xf8
8001c8e: 4393 bics r3, r2
8001c90: 0019 movs r1, r3
8001c92: 687b ldr r3, [r7, #4]
8001c94: 699b ldr r3, [r3, #24]
8001c96: 00da lsls r2, r3, #3
8001c98: 4b6d ldr r3, [pc, #436] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001c9a: 430a orrs r2, r1
8001c9c: 635a str r2, [r3, #52] ; 0x34
8001c9e: e034 b.n 8001d0a <HAL_RCC_OscConfig+0x4da>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8001ca0: 687b ldr r3, [r7, #4]
8001ca2: 695b ldr r3, [r3, #20]
8001ca4: 3305 adds r3, #5
8001ca6: d111 bne.n 8001ccc <HAL_RCC_OscConfig+0x49c>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
8001ca8: 4b69 ldr r3, [pc, #420] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001caa: 6b5a ldr r2, [r3, #52] ; 0x34
8001cac: 4b68 ldr r3, [pc, #416] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cae: 2104 movs r1, #4
8001cb0: 438a bics r2, r1
8001cb2: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8001cb4: 4b66 ldr r3, [pc, #408] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cb6: 6b5b ldr r3, [r3, #52] ; 0x34
8001cb8: 22f8 movs r2, #248 ; 0xf8
8001cba: 4393 bics r3, r2
8001cbc: 0019 movs r1, r3
8001cbe: 687b ldr r3, [r7, #4]
8001cc0: 699b ldr r3, [r3, #24]
8001cc2: 00da lsls r2, r3, #3
8001cc4: 4b62 ldr r3, [pc, #392] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cc6: 430a orrs r2, r1
8001cc8: 635a str r2, [r3, #52] ; 0x34
8001cca: e01e b.n 8001d0a <HAL_RCC_OscConfig+0x4da>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8001ccc: 4b60 ldr r3, [pc, #384] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cce: 6b5a ldr r2, [r3, #52] ; 0x34
8001cd0: 4b5f ldr r3, [pc, #380] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cd2: 2104 movs r1, #4
8001cd4: 430a orrs r2, r1
8001cd6: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8001cd8: 4b5d ldr r3, [pc, #372] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cda: 6b5a ldr r2, [r3, #52] ; 0x34
8001cdc: 4b5c ldr r3, [pc, #368] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001cde: 2101 movs r1, #1
8001ce0: 438a bics r2, r1
8001ce2: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ce4: f7fe fe46 bl 8000974 <HAL_GetTick>
8001ce8: 0003 movs r3, r0
8001cea: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001cec: e008 b.n 8001d00 <HAL_RCC_OscConfig+0x4d0>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8001cee: f7fe fe41 bl 8000974 <HAL_GetTick>
8001cf2: 0002 movs r2, r0
8001cf4: 69bb ldr r3, [r7, #24]
8001cf6: 1ad3 subs r3, r2, r3
8001cf8: 2b02 cmp r3, #2
8001cfa: d901 bls.n 8001d00 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_TIMEOUT;
8001cfc: 2303 movs r3, #3
8001cfe: e0a2 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8001d00: 4b53 ldr r3, [pc, #332] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d02: 6b5b ldr r3, [r3, #52] ; 0x34
8001d04: 2202 movs r2, #2
8001d06: 4013 ands r3, r2
8001d08: d1f1 bne.n 8001cee <HAL_RCC_OscConfig+0x4be>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001d0a: 687b ldr r3, [r7, #4]
8001d0c: 6a1b ldr r3, [r3, #32]
8001d0e: 2b00 cmp r3, #0
8001d10: d100 bne.n 8001d14 <HAL_RCC_OscConfig+0x4e4>
8001d12: e097 b.n 8001e44 <HAL_RCC_OscConfig+0x614>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001d14: 4b4e ldr r3, [pc, #312] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d16: 685b ldr r3, [r3, #4]
8001d18: 220c movs r2, #12
8001d1a: 4013 ands r3, r2
8001d1c: 2b08 cmp r3, #8
8001d1e: d100 bne.n 8001d22 <HAL_RCC_OscConfig+0x4f2>
8001d20: e06b b.n 8001dfa <HAL_RCC_OscConfig+0x5ca>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001d22: 687b ldr r3, [r7, #4]
8001d24: 6a1b ldr r3, [r3, #32]
8001d26: 2b02 cmp r3, #2
8001d28: d14c bne.n 8001dc4 <HAL_RCC_OscConfig+0x594>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001d2a: 4b49 ldr r3, [pc, #292] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d2c: 681a ldr r2, [r3, #0]
8001d2e: 4b48 ldr r3, [pc, #288] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d30: 494a ldr r1, [pc, #296] ; (8001e5c <HAL_RCC_OscConfig+0x62c>)
8001d32: 400a ands r2, r1
8001d34: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001d36: f7fe fe1d bl 8000974 <HAL_GetTick>
8001d3a: 0003 movs r3, r0
8001d3c: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001d3e: e008 b.n 8001d52 <HAL_RCC_OscConfig+0x522>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001d40: f7fe fe18 bl 8000974 <HAL_GetTick>
8001d44: 0002 movs r2, r0
8001d46: 69bb ldr r3, [r7, #24]
8001d48: 1ad3 subs r3, r2, r3
8001d4a: 2b02 cmp r3, #2
8001d4c: d901 bls.n 8001d52 <HAL_RCC_OscConfig+0x522>
{
return HAL_TIMEOUT;
8001d4e: 2303 movs r3, #3
8001d50: e079 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001d52: 4b3f ldr r3, [pc, #252] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d54: 681a ldr r2, [r3, #0]
8001d56: 2380 movs r3, #128 ; 0x80
8001d58: 049b lsls r3, r3, #18
8001d5a: 4013 ands r3, r2
8001d5c: d1f0 bne.n 8001d40 <HAL_RCC_OscConfig+0x510>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001d5e: 4b3c ldr r3, [pc, #240] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d60: 6adb ldr r3, [r3, #44] ; 0x2c
8001d62: 220f movs r2, #15
8001d64: 4393 bics r3, r2
8001d66: 0019 movs r1, r3
8001d68: 687b ldr r3, [r7, #4]
8001d6a: 6ada ldr r2, [r3, #44] ; 0x2c
8001d6c: 4b38 ldr r3, [pc, #224] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d6e: 430a orrs r2, r1
8001d70: 62da str r2, [r3, #44] ; 0x2c
8001d72: 4b37 ldr r3, [pc, #220] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d74: 685b ldr r3, [r3, #4]
8001d76: 4a3a ldr r2, [pc, #232] ; (8001e60 <HAL_RCC_OscConfig+0x630>)
8001d78: 4013 ands r3, r2
8001d7a: 0019 movs r1, r3
8001d7c: 687b ldr r3, [r7, #4]
8001d7e: 6a9a ldr r2, [r3, #40] ; 0x28
8001d80: 687b ldr r3, [r7, #4]
8001d82: 6a5b ldr r3, [r3, #36] ; 0x24
8001d84: 431a orrs r2, r3
8001d86: 4b32 ldr r3, [pc, #200] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d88: 430a orrs r2, r1
8001d8a: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001d8c: 4b30 ldr r3, [pc, #192] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d8e: 681a ldr r2, [r3, #0]
8001d90: 4b2f ldr r3, [pc, #188] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001d92: 2180 movs r1, #128 ; 0x80
8001d94: 0449 lsls r1, r1, #17
8001d96: 430a orrs r2, r1
8001d98: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001d9a: f7fe fdeb bl 8000974 <HAL_GetTick>
8001d9e: 0003 movs r3, r0
8001da0: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001da2: e008 b.n 8001db6 <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001da4: f7fe fde6 bl 8000974 <HAL_GetTick>
8001da8: 0002 movs r2, r0
8001daa: 69bb ldr r3, [r7, #24]
8001dac: 1ad3 subs r3, r2, r3
8001dae: 2b02 cmp r3, #2
8001db0: d901 bls.n 8001db6 <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001db2: 2303 movs r3, #3
8001db4: e047 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001db6: 4b26 ldr r3, [pc, #152] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001db8: 681a ldr r2, [r3, #0]
8001dba: 2380 movs r3, #128 ; 0x80
8001dbc: 049b lsls r3, r3, #18
8001dbe: 4013 ands r3, r2
8001dc0: d0f0 beq.n 8001da4 <HAL_RCC_OscConfig+0x574>
8001dc2: e03f b.n 8001e44 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001dc4: 4b22 ldr r3, [pc, #136] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001dc6: 681a ldr r2, [r3, #0]
8001dc8: 4b21 ldr r3, [pc, #132] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001dca: 4924 ldr r1, [pc, #144] ; (8001e5c <HAL_RCC_OscConfig+0x62c>)
8001dcc: 400a ands r2, r1
8001dce: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001dd0: f7fe fdd0 bl 8000974 <HAL_GetTick>
8001dd4: 0003 movs r3, r0
8001dd6: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001dd8: e008 b.n 8001dec <HAL_RCC_OscConfig+0x5bc>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001dda: f7fe fdcb bl 8000974 <HAL_GetTick>
8001dde: 0002 movs r2, r0
8001de0: 69bb ldr r3, [r7, #24]
8001de2: 1ad3 subs r3, r2, r3
8001de4: 2b02 cmp r3, #2
8001de6: d901 bls.n 8001dec <HAL_RCC_OscConfig+0x5bc>
{
return HAL_TIMEOUT;
8001de8: 2303 movs r3, #3
8001dea: e02c b.n 8001e46 <HAL_RCC_OscConfig+0x616>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001dec: 4b18 ldr r3, [pc, #96] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001dee: 681a ldr r2, [r3, #0]
8001df0: 2380 movs r3, #128 ; 0x80
8001df2: 049b lsls r3, r3, #18
8001df4: 4013 ands r3, r2
8001df6: d1f0 bne.n 8001dda <HAL_RCC_OscConfig+0x5aa>
8001df8: e024 b.n 8001e44 <HAL_RCC_OscConfig+0x614>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001dfa: 687b ldr r3, [r7, #4]
8001dfc: 6a1b ldr r3, [r3, #32]
8001dfe: 2b01 cmp r3, #1
8001e00: d101 bne.n 8001e06 <HAL_RCC_OscConfig+0x5d6>
{
return HAL_ERROR;
8001e02: 2301 movs r3, #1
8001e04: e01f b.n 8001e46 <HAL_RCC_OscConfig+0x616>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8001e06: 4b12 ldr r3, [pc, #72] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001e08: 685b ldr r3, [r3, #4]
8001e0a: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8001e0c: 4b10 ldr r3, [pc, #64] ; (8001e50 <HAL_RCC_OscConfig+0x620>)
8001e0e: 6adb ldr r3, [r3, #44] ; 0x2c
8001e10: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001e12: 697a ldr r2, [r7, #20]
8001e14: 2380 movs r3, #128 ; 0x80
8001e16: 025b lsls r3, r3, #9
8001e18: 401a ands r2, r3
8001e1a: 687b ldr r3, [r7, #4]
8001e1c: 6a5b ldr r3, [r3, #36] ; 0x24
8001e1e: 429a cmp r2, r3
8001e20: d10e bne.n 8001e40 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001e22: 693b ldr r3, [r7, #16]
8001e24: 220f movs r2, #15
8001e26: 401a ands r2, r3
8001e28: 687b ldr r3, [r7, #4]
8001e2a: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001e2c: 429a cmp r2, r3
8001e2e: d107 bne.n 8001e40 <HAL_RCC_OscConfig+0x610>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8001e30: 697a ldr r2, [r7, #20]
8001e32: 23f0 movs r3, #240 ; 0xf0
8001e34: 039b lsls r3, r3, #14
8001e36: 401a ands r2, r3
8001e38: 687b ldr r3, [r7, #4]
8001e3a: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8001e3c: 429a cmp r2, r3
8001e3e: d001 beq.n 8001e44 <HAL_RCC_OscConfig+0x614>
{
return HAL_ERROR;
8001e40: 2301 movs r3, #1
8001e42: e000 b.n 8001e46 <HAL_RCC_OscConfig+0x616>
}
}
}
}
return HAL_OK;
8001e44: 2300 movs r3, #0
}
8001e46: 0018 movs r0, r3
8001e48: 46bd mov sp, r7
8001e4a: b008 add sp, #32
8001e4c: bd80 pop {r7, pc}
8001e4e: 46c0 nop ; (mov r8, r8)
8001e50: 40021000 .word 0x40021000
8001e54: 00001388 .word 0x00001388
8001e58: efffffff .word 0xefffffff
8001e5c: feffffff .word 0xfeffffff
8001e60: ffc2ffff .word 0xffc2ffff
08001e64 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001e64: b580 push {r7, lr}
8001e66: b084 sub sp, #16
8001e68: af00 add r7, sp, #0
8001e6a: 6078 str r0, [r7, #4]
8001e6c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001e6e: 687b ldr r3, [r7, #4]
8001e70: 2b00 cmp r3, #0
8001e72: d101 bne.n 8001e78 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001e74: 2301 movs r3, #1
8001e76: e0b3 b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001e78: 4b5b ldr r3, [pc, #364] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001e7a: 681b ldr r3, [r3, #0]
8001e7c: 2201 movs r2, #1
8001e7e: 4013 ands r3, r2
8001e80: 683a ldr r2, [r7, #0]
8001e82: 429a cmp r2, r3
8001e84: d911 bls.n 8001eaa <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001e86: 4b58 ldr r3, [pc, #352] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001e88: 681b ldr r3, [r3, #0]
8001e8a: 2201 movs r2, #1
8001e8c: 4393 bics r3, r2
8001e8e: 0019 movs r1, r3
8001e90: 4b55 ldr r3, [pc, #340] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001e92: 683a ldr r2, [r7, #0]
8001e94: 430a orrs r2, r1
8001e96: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001e98: 4b53 ldr r3, [pc, #332] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001e9a: 681b ldr r3, [r3, #0]
8001e9c: 2201 movs r2, #1
8001e9e: 4013 ands r3, r2
8001ea0: 683a ldr r2, [r7, #0]
8001ea2: 429a cmp r2, r3
8001ea4: d001 beq.n 8001eaa <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
8001ea6: 2301 movs r3, #1
8001ea8: e09a b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001eaa: 687b ldr r3, [r7, #4]
8001eac: 681b ldr r3, [r3, #0]
8001eae: 2202 movs r2, #2
8001eb0: 4013 ands r3, r2
8001eb2: d015 beq.n 8001ee0 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 681b ldr r3, [r3, #0]
8001eb8: 2204 movs r2, #4
8001eba: 4013 ands r3, r2
8001ebc: d006 beq.n 8001ecc <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8001ebe: 4b4b ldr r3, [pc, #300] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001ec0: 685a ldr r2, [r3, #4]
8001ec2: 4b4a ldr r3, [pc, #296] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001ec4: 21e0 movs r1, #224 ; 0xe0
8001ec6: 00c9 lsls r1, r1, #3
8001ec8: 430a orrs r2, r1
8001eca: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001ecc: 4b47 ldr r3, [pc, #284] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001ece: 685b ldr r3, [r3, #4]
8001ed0: 22f0 movs r2, #240 ; 0xf0
8001ed2: 4393 bics r3, r2
8001ed4: 0019 movs r1, r3
8001ed6: 687b ldr r3, [r7, #4]
8001ed8: 689a ldr r2, [r3, #8]
8001eda: 4b44 ldr r3, [pc, #272] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001edc: 430a orrs r2, r1
8001ede: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001ee0: 687b ldr r3, [r7, #4]
8001ee2: 681b ldr r3, [r3, #0]
8001ee4: 2201 movs r2, #1
8001ee6: 4013 ands r3, r2
8001ee8: d040 beq.n 8001f6c <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001eea: 687b ldr r3, [r7, #4]
8001eec: 685b ldr r3, [r3, #4]
8001eee: 2b01 cmp r3, #1
8001ef0: d107 bne.n 8001f02 <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001ef2: 4b3e ldr r3, [pc, #248] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001ef4: 681a ldr r2, [r3, #0]
8001ef6: 2380 movs r3, #128 ; 0x80
8001ef8: 029b lsls r3, r3, #10
8001efa: 4013 ands r3, r2
8001efc: d114 bne.n 8001f28 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001efe: 2301 movs r3, #1
8001f00: e06e b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001f02: 687b ldr r3, [r7, #4]
8001f04: 685b ldr r3, [r3, #4]
8001f06: 2b02 cmp r3, #2
8001f08: d107 bne.n 8001f1a <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001f0a: 4b38 ldr r3, [pc, #224] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001f0c: 681a ldr r2, [r3, #0]
8001f0e: 2380 movs r3, #128 ; 0x80
8001f10: 049b lsls r3, r3, #18
8001f12: 4013 ands r3, r2
8001f14: d108 bne.n 8001f28 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001f16: 2301 movs r3, #1
8001f18: e062 b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001f1a: 4b34 ldr r3, [pc, #208] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001f1c: 681b ldr r3, [r3, #0]
8001f1e: 2202 movs r2, #2
8001f20: 4013 ands r3, r2
8001f22: d101 bne.n 8001f28 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001f24: 2301 movs r3, #1
8001f26: e05b b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001f28: 4b30 ldr r3, [pc, #192] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001f2a: 685b ldr r3, [r3, #4]
8001f2c: 2203 movs r2, #3
8001f2e: 4393 bics r3, r2
8001f30: 0019 movs r1, r3
8001f32: 687b ldr r3, [r7, #4]
8001f34: 685a ldr r2, [r3, #4]
8001f36: 4b2d ldr r3, [pc, #180] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001f38: 430a orrs r2, r1
8001f3a: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001f3c: f7fe fd1a bl 8000974 <HAL_GetTick>
8001f40: 0003 movs r3, r0
8001f42: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001f44: e009 b.n 8001f5a <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001f46: f7fe fd15 bl 8000974 <HAL_GetTick>
8001f4a: 0002 movs r2, r0
8001f4c: 68fb ldr r3, [r7, #12]
8001f4e: 1ad3 subs r3, r2, r3
8001f50: 4a27 ldr r2, [pc, #156] ; (8001ff0 <HAL_RCC_ClockConfig+0x18c>)
8001f52: 4293 cmp r3, r2
8001f54: d901 bls.n 8001f5a <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
8001f56: 2303 movs r3, #3
8001f58: e042 b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001f5a: 4b24 ldr r3, [pc, #144] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001f5c: 685b ldr r3, [r3, #4]
8001f5e: 220c movs r2, #12
8001f60: 401a ands r2, r3
8001f62: 687b ldr r3, [r7, #4]
8001f64: 685b ldr r3, [r3, #4]
8001f66: 009b lsls r3, r3, #2
8001f68: 429a cmp r2, r3
8001f6a: d1ec bne.n 8001f46 <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001f6c: 4b1e ldr r3, [pc, #120] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001f6e: 681b ldr r3, [r3, #0]
8001f70: 2201 movs r2, #1
8001f72: 4013 ands r3, r2
8001f74: 683a ldr r2, [r7, #0]
8001f76: 429a cmp r2, r3
8001f78: d211 bcs.n 8001f9e <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001f7a: 4b1b ldr r3, [pc, #108] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001f7c: 681b ldr r3, [r3, #0]
8001f7e: 2201 movs r2, #1
8001f80: 4393 bics r3, r2
8001f82: 0019 movs r1, r3
8001f84: 4b18 ldr r3, [pc, #96] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001f86: 683a ldr r2, [r7, #0]
8001f88: 430a orrs r2, r1
8001f8a: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001f8c: 4b16 ldr r3, [pc, #88] ; (8001fe8 <HAL_RCC_ClockConfig+0x184>)
8001f8e: 681b ldr r3, [r3, #0]
8001f90: 2201 movs r2, #1
8001f92: 4013 ands r3, r2
8001f94: 683a ldr r2, [r7, #0]
8001f96: 429a cmp r2, r3
8001f98: d001 beq.n 8001f9e <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
8001f9a: 2301 movs r3, #1
8001f9c: e020 b.n 8001fe0 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001f9e: 687b ldr r3, [r7, #4]
8001fa0: 681b ldr r3, [r3, #0]
8001fa2: 2204 movs r2, #4
8001fa4: 4013 ands r3, r2
8001fa6: d009 beq.n 8001fbc <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8001fa8: 4b10 ldr r3, [pc, #64] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001faa: 685b ldr r3, [r3, #4]
8001fac: 4a11 ldr r2, [pc, #68] ; (8001ff4 <HAL_RCC_ClockConfig+0x190>)
8001fae: 4013 ands r3, r2
8001fb0: 0019 movs r1, r3
8001fb2: 687b ldr r3, [r7, #4]
8001fb4: 68da ldr r2, [r3, #12]
8001fb6: 4b0d ldr r3, [pc, #52] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001fb8: 430a orrs r2, r1
8001fba: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8001fbc: f000 f820 bl 8002000 <HAL_RCC_GetSysClockFreq>
8001fc0: 0001 movs r1, r0
8001fc2: 4b0a ldr r3, [pc, #40] ; (8001fec <HAL_RCC_ClockConfig+0x188>)
8001fc4: 685b ldr r3, [r3, #4]
8001fc6: 091b lsrs r3, r3, #4
8001fc8: 220f movs r2, #15
8001fca: 4013 ands r3, r2
8001fcc: 4a0a ldr r2, [pc, #40] ; (8001ff8 <HAL_RCC_ClockConfig+0x194>)
8001fce: 5cd3 ldrb r3, [r2, r3]
8001fd0: 000a movs r2, r1
8001fd2: 40da lsrs r2, r3
8001fd4: 4b09 ldr r3, [pc, #36] ; (8001ffc <HAL_RCC_ClockConfig+0x198>)
8001fd6: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
8001fd8: 2003 movs r0, #3
8001fda: f7fe fc85 bl 80008e8 <HAL_InitTick>
return HAL_OK;
8001fde: 2300 movs r3, #0
}
8001fe0: 0018 movs r0, r3
8001fe2: 46bd mov sp, r7
8001fe4: b004 add sp, #16
8001fe6: bd80 pop {r7, pc}
8001fe8: 40022000 .word 0x40022000
8001fec: 40021000 .word 0x40021000
8001ff0: 00001388 .word 0x00001388
8001ff4: fffff8ff .word 0xfffff8ff
8001ff8: 0800380c .word 0x0800380c
8001ffc: 20000000 .word 0x20000000
08002000 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002000: b590 push {r4, r7, lr}
8002002: b08f sub sp, #60 ; 0x3c
8002004: af00 add r7, sp, #0
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
8002006: 2314 movs r3, #20
8002008: 18fb adds r3, r7, r3
800200a: 4a2b ldr r2, [pc, #172] ; (80020b8 <HAL_RCC_GetSysClockFreq+0xb8>)
800200c: ca13 ldmia r2!, {r0, r1, r4}
800200e: c313 stmia r3!, {r0, r1, r4}
8002010: 6812 ldr r2, [r2, #0]
8002012: 601a str r2, [r3, #0]
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
8002014: 1d3b adds r3, r7, #4
8002016: 4a29 ldr r2, [pc, #164] ; (80020bc <HAL_RCC_GetSysClockFreq+0xbc>)
8002018: ca13 ldmia r2!, {r0, r1, r4}
800201a: c313 stmia r3!, {r0, r1, r4}
800201c: 6812 ldr r2, [r2, #0]
800201e: 601a str r2, [r3, #0]
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8002020: 2300 movs r3, #0
8002022: 62fb str r3, [r7, #44] ; 0x2c
8002024: 2300 movs r3, #0
8002026: 62bb str r3, [r7, #40] ; 0x28
8002028: 2300 movs r3, #0
800202a: 637b str r3, [r7, #52] ; 0x34
800202c: 2300 movs r3, #0
800202e: 627b str r3, [r7, #36] ; 0x24
uint32_t sysclockfreq = 0U;
8002030: 2300 movs r3, #0
8002032: 633b str r3, [r7, #48] ; 0x30
tmpreg = RCC->CFGR;
8002034: 4b22 ldr r3, [pc, #136] ; (80020c0 <HAL_RCC_GetSysClockFreq+0xc0>)
8002036: 685b ldr r3, [r3, #4]
8002038: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800203a: 6afb ldr r3, [r7, #44] ; 0x2c
800203c: 220c movs r2, #12
800203e: 4013 ands r3, r2
8002040: 2b04 cmp r3, #4
8002042: d002 beq.n 800204a <HAL_RCC_GetSysClockFreq+0x4a>
8002044: 2b08 cmp r3, #8
8002046: d003 beq.n 8002050 <HAL_RCC_GetSysClockFreq+0x50>
8002048: e02d b.n 80020a6 <HAL_RCC_GetSysClockFreq+0xa6>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800204a: 4b1e ldr r3, [pc, #120] ; (80020c4 <HAL_RCC_GetSysClockFreq+0xc4>)
800204c: 633b str r3, [r7, #48] ; 0x30
break;
800204e: e02d b.n 80020ac <HAL_RCC_GetSysClockFreq+0xac>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
8002050: 6afb ldr r3, [r7, #44] ; 0x2c
8002052: 0c9b lsrs r3, r3, #18
8002054: 220f movs r2, #15
8002056: 4013 ands r3, r2
8002058: 2214 movs r2, #20
800205a: 18ba adds r2, r7, r2
800205c: 5cd3 ldrb r3, [r2, r3]
800205e: 627b str r3, [r7, #36] ; 0x24
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
8002060: 4b17 ldr r3, [pc, #92] ; (80020c0 <HAL_RCC_GetSysClockFreq+0xc0>)
8002062: 6adb ldr r3, [r3, #44] ; 0x2c
8002064: 220f movs r2, #15
8002066: 4013 ands r3, r2
8002068: 1d3a adds r2, r7, #4
800206a: 5cd3 ldrb r3, [r2, r3]
800206c: 62bb str r3, [r7, #40] ; 0x28
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
800206e: 6afa ldr r2, [r7, #44] ; 0x2c
8002070: 2380 movs r3, #128 ; 0x80
8002072: 025b lsls r3, r3, #9
8002074: 4013 ands r3, r2
8002076: d009 beq.n 800208c <HAL_RCC_GetSysClockFreq+0x8c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8002078: 6ab9 ldr r1, [r7, #40] ; 0x28
800207a: 4812 ldr r0, [pc, #72] ; (80020c4 <HAL_RCC_GetSysClockFreq+0xc4>)
800207c: f7fe f844 bl 8000108 <__udivsi3>
8002080: 0003 movs r3, r0
8002082: 001a movs r2, r3
8002084: 6a7b ldr r3, [r7, #36] ; 0x24
8002086: 4353 muls r3, r2
8002088: 637b str r3, [r7, #52] ; 0x34
800208a: e009 b.n 80020a0 <HAL_RCC_GetSysClockFreq+0xa0>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
800208c: 6a79 ldr r1, [r7, #36] ; 0x24
800208e: 000a movs r2, r1
8002090: 0152 lsls r2, r2, #5
8002092: 1a52 subs r2, r2, r1
8002094: 0193 lsls r3, r2, #6
8002096: 1a9b subs r3, r3, r2
8002098: 00db lsls r3, r3, #3
800209a: 185b adds r3, r3, r1
800209c: 021b lsls r3, r3, #8
800209e: 637b str r3, [r7, #52] ; 0x34
#endif
}
sysclockfreq = pllclk;
80020a0: 6b7b ldr r3, [r7, #52] ; 0x34
80020a2: 633b str r3, [r7, #48] ; 0x30
break;
80020a4: e002 b.n 80020ac <HAL_RCC_GetSysClockFreq+0xac>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80020a6: 4b07 ldr r3, [pc, #28] ; (80020c4 <HAL_RCC_GetSysClockFreq+0xc4>)
80020a8: 633b str r3, [r7, #48] ; 0x30
break;
80020aa: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
80020ac: 6b3b ldr r3, [r7, #48] ; 0x30
}
80020ae: 0018 movs r0, r3
80020b0: 46bd mov sp, r7
80020b2: b00f add sp, #60 ; 0x3c
80020b4: bd90 pop {r4, r7, pc}
80020b6: 46c0 nop ; (mov r8, r8)
80020b8: 080037ec .word 0x080037ec
80020bc: 080037fc .word 0x080037fc
80020c0: 40021000 .word 0x40021000
80020c4: 007a1200 .word 0x007a1200
080020c8 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80020c8: b580 push {r7, lr}
80020ca: b082 sub sp, #8
80020cc: af00 add r7, sp, #0
80020ce: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80020d0: 687b ldr r3, [r7, #4]
80020d2: 2b00 cmp r3, #0
80020d4: d101 bne.n 80020da <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80020d6: 2301 movs r3, #1
80020d8: e042 b.n 8002160 <HAL_TIM_Base_Init+0x98>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80020da: 687b ldr r3, [r7, #4]
80020dc: 223d movs r2, #61 ; 0x3d
80020de: 5c9b ldrb r3, [r3, r2]
80020e0: b2db uxtb r3, r3
80020e2: 2b00 cmp r3, #0
80020e4: d107 bne.n 80020f6 <HAL_TIM_Base_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80020e6: 687b ldr r3, [r7, #4]
80020e8: 223c movs r2, #60 ; 0x3c
80020ea: 2100 movs r1, #0
80020ec: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80020ee: 687b ldr r3, [r7, #4]
80020f0: 0018 movs r0, r3
80020f2: f7fe fb61 bl 80007b8 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80020f6: 687b ldr r3, [r7, #4]
80020f8: 223d movs r2, #61 ; 0x3d
80020fa: 2102 movs r1, #2
80020fc: 5499 strb r1, [r3, r2]
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80020fe: 687b ldr r3, [r7, #4]
8002100: 681a ldr r2, [r3, #0]
8002102: 687b ldr r3, [r7, #4]
8002104: 3304 adds r3, #4
8002106: 0019 movs r1, r3
8002108: 0010 movs r0, r2
800210a: f000 f9a9 bl 8002460 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800210e: 687b ldr r3, [r7, #4]
8002110: 2246 movs r2, #70 ; 0x46
8002112: 2101 movs r1, #1
8002114: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002116: 687b ldr r3, [r7, #4]
8002118: 223e movs r2, #62 ; 0x3e
800211a: 2101 movs r1, #1
800211c: 5499 strb r1, [r3, r2]
800211e: 687b ldr r3, [r7, #4]
8002120: 223f movs r2, #63 ; 0x3f
8002122: 2101 movs r1, #1
8002124: 5499 strb r1, [r3, r2]
8002126: 687b ldr r3, [r7, #4]
8002128: 2240 movs r2, #64 ; 0x40
800212a: 2101 movs r1, #1
800212c: 5499 strb r1, [r3, r2]
800212e: 687b ldr r3, [r7, #4]
8002130: 2241 movs r2, #65 ; 0x41
8002132: 2101 movs r1, #1
8002134: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002136: 687b ldr r3, [r7, #4]
8002138: 2242 movs r2, #66 ; 0x42
800213a: 2101 movs r1, #1
800213c: 5499 strb r1, [r3, r2]
800213e: 687b ldr r3, [r7, #4]
8002140: 2243 movs r2, #67 ; 0x43
8002142: 2101 movs r1, #1
8002144: 5499 strb r1, [r3, r2]
8002146: 687b ldr r3, [r7, #4]
8002148: 2244 movs r2, #68 ; 0x44
800214a: 2101 movs r1, #1
800214c: 5499 strb r1, [r3, r2]
800214e: 687b ldr r3, [r7, #4]
8002150: 2245 movs r2, #69 ; 0x45
8002152: 2101 movs r1, #1
8002154: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002156: 687b ldr r3, [r7, #4]
8002158: 223d movs r2, #61 ; 0x3d
800215a: 2101 movs r1, #1
800215c: 5499 strb r1, [r3, r2]
return HAL_OK;
800215e: 2300 movs r3, #0
}
8002160: 0018 movs r0, r3
8002162: 46bd mov sp, r7
8002164: b002 add sp, #8
8002166: bd80 pop {r7, pc}
08002168 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8002168: b580 push {r7, lr}
800216a: b084 sub sp, #16
800216c: af00 add r7, sp, #0
800216e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8002170: 687b ldr r3, [r7, #4]
8002172: 223d movs r2, #61 ; 0x3d
8002174: 5c9b ldrb r3, [r3, r2]
8002176: b2db uxtb r3, r3
8002178: 2b01 cmp r3, #1
800217a: d001 beq.n 8002180 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
800217c: 2301 movs r3, #1
800217e: e030 b.n 80021e2 <HAL_TIM_Base_Start_IT+0x7a>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002180: 687b ldr r3, [r7, #4]
8002182: 223d movs r2, #61 ; 0x3d
8002184: 2102 movs r1, #2
8002186: 5499 strb r1, [r3, r2]
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8002188: 687b ldr r3, [r7, #4]
800218a: 681b ldr r3, [r3, #0]
800218c: 68da ldr r2, [r3, #12]
800218e: 687b ldr r3, [r7, #4]
8002190: 681b ldr r3, [r3, #0]
8002192: 2101 movs r1, #1
8002194: 430a orrs r2, r1
8002196: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002198: 687b ldr r3, [r7, #4]
800219a: 681b ldr r3, [r3, #0]
800219c: 4a13 ldr r2, [pc, #76] ; (80021ec <HAL_TIM_Base_Start_IT+0x84>)
800219e: 4293 cmp r3, r2
80021a0: d004 beq.n 80021ac <HAL_TIM_Base_Start_IT+0x44>
80021a2: 687b ldr r3, [r7, #4]
80021a4: 681b ldr r3, [r3, #0]
80021a6: 4a12 ldr r2, [pc, #72] ; (80021f0 <HAL_TIM_Base_Start_IT+0x88>)
80021a8: 4293 cmp r3, r2
80021aa: d111 bne.n 80021d0 <HAL_TIM_Base_Start_IT+0x68>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80021ac: 687b ldr r3, [r7, #4]
80021ae: 681b ldr r3, [r3, #0]
80021b0: 689b ldr r3, [r3, #8]
80021b2: 2207 movs r2, #7
80021b4: 4013 ands r3, r2
80021b6: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80021b8: 68fb ldr r3, [r7, #12]
80021ba: 2b06 cmp r3, #6
80021bc: d010 beq.n 80021e0 <HAL_TIM_Base_Start_IT+0x78>
{
__HAL_TIM_ENABLE(htim);
80021be: 687b ldr r3, [r7, #4]
80021c0: 681b ldr r3, [r3, #0]
80021c2: 681a ldr r2, [r3, #0]
80021c4: 687b ldr r3, [r7, #4]
80021c6: 681b ldr r3, [r3, #0]
80021c8: 2101 movs r1, #1
80021ca: 430a orrs r2, r1
80021cc: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80021ce: e007 b.n 80021e0 <HAL_TIM_Base_Start_IT+0x78>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80021d0: 687b ldr r3, [r7, #4]
80021d2: 681b ldr r3, [r3, #0]
80021d4: 681a ldr r2, [r3, #0]
80021d6: 687b ldr r3, [r7, #4]
80021d8: 681b ldr r3, [r3, #0]
80021da: 2101 movs r1, #1
80021dc: 430a orrs r2, r1
80021de: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
80021e0: 2300 movs r3, #0
}
80021e2: 0018 movs r0, r3
80021e4: 46bd mov sp, r7
80021e6: b004 add sp, #16
80021e8: bd80 pop {r7, pc}
80021ea: 46c0 nop ; (mov r8, r8)
80021ec: 40012c00 .word 0x40012c00
80021f0: 40000400 .word 0x40000400
080021f4 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
80021f4: b580 push {r7, lr}
80021f6: b082 sub sp, #8
80021f8: af00 add r7, sp, #0
80021fa: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
80021fc: 687b ldr r3, [r7, #4]
80021fe: 681b ldr r3, [r3, #0]
8002200: 691b ldr r3, [r3, #16]
8002202: 2202 movs r2, #2
8002204: 4013 ands r3, r2
8002206: 2b02 cmp r3, #2
8002208: d124 bne.n 8002254 <HAL_TIM_IRQHandler+0x60>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
800220a: 687b ldr r3, [r7, #4]
800220c: 681b ldr r3, [r3, #0]
800220e: 68db ldr r3, [r3, #12]
8002210: 2202 movs r2, #2
8002212: 4013 ands r3, r2
8002214: 2b02 cmp r3, #2
8002216: d11d bne.n 8002254 <HAL_TIM_IRQHandler+0x60>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8002218: 687b ldr r3, [r7, #4]
800221a: 681b ldr r3, [r3, #0]
800221c: 2203 movs r2, #3
800221e: 4252 negs r2, r2
8002220: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002222: 687b ldr r3, [r7, #4]
8002224: 2201 movs r2, #1
8002226: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8002228: 687b ldr r3, [r7, #4]
800222a: 681b ldr r3, [r3, #0]
800222c: 699b ldr r3, [r3, #24]
800222e: 2203 movs r2, #3
8002230: 4013 ands r3, r2
8002232: d004 beq.n 800223e <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002234: 687b ldr r3, [r7, #4]
8002236: 0018 movs r0, r3
8002238: f000 f8fa bl 8002430 <HAL_TIM_IC_CaptureCallback>
800223c: e007 b.n 800224e <HAL_TIM_IRQHandler+0x5a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800223e: 687b ldr r3, [r7, #4]
8002240: 0018 movs r0, r3
8002242: f000 f8ed bl 8002420 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002246: 687b ldr r3, [r7, #4]
8002248: 0018 movs r0, r3
800224a: f000 f8f9 bl 8002440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800224e: 687b ldr r3, [r7, #4]
8002250: 2200 movs r2, #0
8002252: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8002254: 687b ldr r3, [r7, #4]
8002256: 681b ldr r3, [r3, #0]
8002258: 691b ldr r3, [r3, #16]
800225a: 2204 movs r2, #4
800225c: 4013 ands r3, r2
800225e: 2b04 cmp r3, #4
8002260: d125 bne.n 80022ae <HAL_TIM_IRQHandler+0xba>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8002262: 687b ldr r3, [r7, #4]
8002264: 681b ldr r3, [r3, #0]
8002266: 68db ldr r3, [r3, #12]
8002268: 2204 movs r2, #4
800226a: 4013 ands r3, r2
800226c: 2b04 cmp r3, #4
800226e: d11e bne.n 80022ae <HAL_TIM_IRQHandler+0xba>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8002270: 687b ldr r3, [r7, #4]
8002272: 681b ldr r3, [r3, #0]
8002274: 2205 movs r2, #5
8002276: 4252 negs r2, r2
8002278: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
800227a: 687b ldr r3, [r7, #4]
800227c: 2202 movs r2, #2
800227e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8002280: 687b ldr r3, [r7, #4]
8002282: 681b ldr r3, [r3, #0]
8002284: 699a ldr r2, [r3, #24]
8002286: 23c0 movs r3, #192 ; 0xc0
8002288: 009b lsls r3, r3, #2
800228a: 4013 ands r3, r2
800228c: d004 beq.n 8002298 <HAL_TIM_IRQHandler+0xa4>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800228e: 687b ldr r3, [r7, #4]
8002290: 0018 movs r0, r3
8002292: f000 f8cd bl 8002430 <HAL_TIM_IC_CaptureCallback>
8002296: e007 b.n 80022a8 <HAL_TIM_IRQHandler+0xb4>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002298: 687b ldr r3, [r7, #4]
800229a: 0018 movs r0, r3
800229c: f000 f8c0 bl 8002420 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80022a0: 687b ldr r3, [r7, #4]
80022a2: 0018 movs r0, r3
80022a4: f000 f8cc bl 8002440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80022a8: 687b ldr r3, [r7, #4]
80022aa: 2200 movs r2, #0
80022ac: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
80022ae: 687b ldr r3, [r7, #4]
80022b0: 681b ldr r3, [r3, #0]
80022b2: 691b ldr r3, [r3, #16]
80022b4: 2208 movs r2, #8
80022b6: 4013 ands r3, r2
80022b8: 2b08 cmp r3, #8
80022ba: d124 bne.n 8002306 <HAL_TIM_IRQHandler+0x112>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
80022bc: 687b ldr r3, [r7, #4]
80022be: 681b ldr r3, [r3, #0]
80022c0: 68db ldr r3, [r3, #12]
80022c2: 2208 movs r2, #8
80022c4: 4013 ands r3, r2
80022c6: 2b08 cmp r3, #8
80022c8: d11d bne.n 8002306 <HAL_TIM_IRQHandler+0x112>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
80022ca: 687b ldr r3, [r7, #4]
80022cc: 681b ldr r3, [r3, #0]
80022ce: 2209 movs r2, #9
80022d0: 4252 negs r2, r2
80022d2: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80022d4: 687b ldr r3, [r7, #4]
80022d6: 2204 movs r2, #4
80022d8: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
80022da: 687b ldr r3, [r7, #4]
80022dc: 681b ldr r3, [r3, #0]
80022de: 69db ldr r3, [r3, #28]
80022e0: 2203 movs r2, #3
80022e2: 4013 ands r3, r2
80022e4: d004 beq.n 80022f0 <HAL_TIM_IRQHandler+0xfc>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80022e6: 687b ldr r3, [r7, #4]
80022e8: 0018 movs r0, r3
80022ea: f000 f8a1 bl 8002430 <HAL_TIM_IC_CaptureCallback>
80022ee: e007 b.n 8002300 <HAL_TIM_IRQHandler+0x10c>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80022f0: 687b ldr r3, [r7, #4]
80022f2: 0018 movs r0, r3
80022f4: f000 f894 bl 8002420 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80022f8: 687b ldr r3, [r7, #4]
80022fa: 0018 movs r0, r3
80022fc: f000 f8a0 bl 8002440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002300: 687b ldr r3, [r7, #4]
8002302: 2200 movs r2, #0
8002304: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8002306: 687b ldr r3, [r7, #4]
8002308: 681b ldr r3, [r3, #0]
800230a: 691b ldr r3, [r3, #16]
800230c: 2210 movs r2, #16
800230e: 4013 ands r3, r2
8002310: 2b10 cmp r3, #16
8002312: d125 bne.n 8002360 <HAL_TIM_IRQHandler+0x16c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8002314: 687b ldr r3, [r7, #4]
8002316: 681b ldr r3, [r3, #0]
8002318: 68db ldr r3, [r3, #12]
800231a: 2210 movs r2, #16
800231c: 4013 ands r3, r2
800231e: 2b10 cmp r3, #16
8002320: d11e bne.n 8002360 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8002322: 687b ldr r3, [r7, #4]
8002324: 681b ldr r3, [r3, #0]
8002326: 2211 movs r2, #17
8002328: 4252 negs r2, r2
800232a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
800232c: 687b ldr r3, [r7, #4]
800232e: 2208 movs r2, #8
8002330: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002332: 687b ldr r3, [r7, #4]
8002334: 681b ldr r3, [r3, #0]
8002336: 69da ldr r2, [r3, #28]
8002338: 23c0 movs r3, #192 ; 0xc0
800233a: 009b lsls r3, r3, #2
800233c: 4013 ands r3, r2
800233e: d004 beq.n 800234a <HAL_TIM_IRQHandler+0x156>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002340: 687b ldr r3, [r7, #4]
8002342: 0018 movs r0, r3
8002344: f000 f874 bl 8002430 <HAL_TIM_IC_CaptureCallback>
8002348: e007 b.n 800235a <HAL_TIM_IRQHandler+0x166>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800234a: 687b ldr r3, [r7, #4]
800234c: 0018 movs r0, r3
800234e: f000 f867 bl 8002420 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002352: 687b ldr r3, [r7, #4]
8002354: 0018 movs r0, r3
8002356: f000 f873 bl 8002440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800235a: 687b ldr r3, [r7, #4]
800235c: 2200 movs r2, #0
800235e: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8002360: 687b ldr r3, [r7, #4]
8002362: 681b ldr r3, [r3, #0]
8002364: 691b ldr r3, [r3, #16]
8002366: 2201 movs r2, #1
8002368: 4013 ands r3, r2
800236a: 2b01 cmp r3, #1
800236c: d10f bne.n 800238e <HAL_TIM_IRQHandler+0x19a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
800236e: 687b ldr r3, [r7, #4]
8002370: 681b ldr r3, [r3, #0]
8002372: 68db ldr r3, [r3, #12]
8002374: 2201 movs r2, #1
8002376: 4013 ands r3, r2
8002378: 2b01 cmp r3, #1
800237a: d108 bne.n 800238e <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
800237c: 687b ldr r3, [r7, #4]
800237e: 681b ldr r3, [r3, #0]
8002380: 2202 movs r2, #2
8002382: 4252 negs r2, r2
8002384: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8002386: 687b ldr r3, [r7, #4]
8002388: 0018 movs r0, r3
800238a: f001 f9e1 bl 8003750 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
800238e: 687b ldr r3, [r7, #4]
8002390: 681b ldr r3, [r3, #0]
8002392: 691b ldr r3, [r3, #16]
8002394: 2280 movs r2, #128 ; 0x80
8002396: 4013 ands r3, r2
8002398: 2b80 cmp r3, #128 ; 0x80
800239a: d10f bne.n 80023bc <HAL_TIM_IRQHandler+0x1c8>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
800239c: 687b ldr r3, [r7, #4]
800239e: 681b ldr r3, [r3, #0]
80023a0: 68db ldr r3, [r3, #12]
80023a2: 2280 movs r2, #128 ; 0x80
80023a4: 4013 ands r3, r2
80023a6: 2b80 cmp r3, #128 ; 0x80
80023a8: d108 bne.n 80023bc <HAL_TIM_IRQHandler+0x1c8>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
80023aa: 687b ldr r3, [r7, #4]
80023ac: 681b ldr r3, [r3, #0]
80023ae: 2281 movs r2, #129 ; 0x81
80023b0: 4252 negs r2, r2
80023b2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80023b4: 687b ldr r3, [r7, #4]
80023b6: 0018 movs r0, r3
80023b8: f000 f8c6 bl 8002548 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
80023bc: 687b ldr r3, [r7, #4]
80023be: 681b ldr r3, [r3, #0]
80023c0: 691b ldr r3, [r3, #16]
80023c2: 2240 movs r2, #64 ; 0x40
80023c4: 4013 ands r3, r2
80023c6: 2b40 cmp r3, #64 ; 0x40
80023c8: d10f bne.n 80023ea <HAL_TIM_IRQHandler+0x1f6>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
80023ca: 687b ldr r3, [r7, #4]
80023cc: 681b ldr r3, [r3, #0]
80023ce: 68db ldr r3, [r3, #12]
80023d0: 2240 movs r2, #64 ; 0x40
80023d2: 4013 ands r3, r2
80023d4: 2b40 cmp r3, #64 ; 0x40
80023d6: d108 bne.n 80023ea <HAL_TIM_IRQHandler+0x1f6>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
80023d8: 687b ldr r3, [r7, #4]
80023da: 681b ldr r3, [r3, #0]
80023dc: 2241 movs r2, #65 ; 0x41
80023de: 4252 negs r2, r2
80023e0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80023e2: 687b ldr r3, [r7, #4]
80023e4: 0018 movs r0, r3
80023e6: f000 f833 bl 8002450 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
80023ea: 687b ldr r3, [r7, #4]
80023ec: 681b ldr r3, [r3, #0]
80023ee: 691b ldr r3, [r3, #16]
80023f0: 2220 movs r2, #32
80023f2: 4013 ands r3, r2
80023f4: 2b20 cmp r3, #32
80023f6: d10f bne.n 8002418 <HAL_TIM_IRQHandler+0x224>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
80023f8: 687b ldr r3, [r7, #4]
80023fa: 681b ldr r3, [r3, #0]
80023fc: 68db ldr r3, [r3, #12]
80023fe: 2220 movs r2, #32
8002400: 4013 ands r3, r2
8002402: 2b20 cmp r3, #32
8002404: d108 bne.n 8002418 <HAL_TIM_IRQHandler+0x224>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8002406: 687b ldr r3, [r7, #4]
8002408: 681b ldr r3, [r3, #0]
800240a: 2221 movs r2, #33 ; 0x21
800240c: 4252 negs r2, r2
800240e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8002410: 687b ldr r3, [r7, #4]
8002412: 0018 movs r0, r3
8002414: f000 f890 bl 8002538 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8002418: 46c0 nop ; (mov r8, r8)
800241a: 46bd mov sp, r7
800241c: b002 add sp, #8
800241e: bd80 pop {r7, pc}
08002420 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8002420: b580 push {r7, lr}
8002422: b082 sub sp, #8
8002424: af00 add r7, sp, #0
8002426: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8002428: 46c0 nop ; (mov r8, r8)
800242a: 46bd mov sp, r7
800242c: b002 add sp, #8
800242e: bd80 pop {r7, pc}
08002430 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8002430: b580 push {r7, lr}
8002432: b082 sub sp, #8
8002434: af00 add r7, sp, #0
8002436: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8002438: 46c0 nop ; (mov r8, r8)
800243a: 46bd mov sp, r7
800243c: b002 add sp, #8
800243e: bd80 pop {r7, pc}
08002440 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8002440: b580 push {r7, lr}
8002442: b082 sub sp, #8
8002444: af00 add r7, sp, #0
8002446: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8002448: 46c0 nop ; (mov r8, r8)
800244a: 46bd mov sp, r7
800244c: b002 add sp, #8
800244e: bd80 pop {r7, pc}
08002450 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8002450: b580 push {r7, lr}
8002452: b082 sub sp, #8
8002454: af00 add r7, sp, #0
8002456: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8002458: 46c0 nop ; (mov r8, r8)
800245a: 46bd mov sp, r7
800245c: b002 add sp, #8
800245e: bd80 pop {r7, pc}
08002460 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8002460: b580 push {r7, lr}
8002462: b084 sub sp, #16
8002464: af00 add r7, sp, #0
8002466: 6078 str r0, [r7, #4]
8002468: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800246a: 687b ldr r3, [r7, #4]
800246c: 681b ldr r3, [r3, #0]
800246e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8002470: 687b ldr r3, [r7, #4]
8002472: 4a2b ldr r2, [pc, #172] ; (8002520 <TIM_Base_SetConfig+0xc0>)
8002474: 4293 cmp r3, r2
8002476: d003 beq.n 8002480 <TIM_Base_SetConfig+0x20>
8002478: 687b ldr r3, [r7, #4]
800247a: 4a2a ldr r2, [pc, #168] ; (8002524 <TIM_Base_SetConfig+0xc4>)
800247c: 4293 cmp r3, r2
800247e: d108 bne.n 8002492 <TIM_Base_SetConfig+0x32>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8002480: 68fb ldr r3, [r7, #12]
8002482: 2270 movs r2, #112 ; 0x70
8002484: 4393 bics r3, r2
8002486: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8002488: 683b ldr r3, [r7, #0]
800248a: 685b ldr r3, [r3, #4]
800248c: 68fa ldr r2, [r7, #12]
800248e: 4313 orrs r3, r2
8002490: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8002492: 687b ldr r3, [r7, #4]
8002494: 4a22 ldr r2, [pc, #136] ; (8002520 <TIM_Base_SetConfig+0xc0>)
8002496: 4293 cmp r3, r2
8002498: d00f beq.n 80024ba <TIM_Base_SetConfig+0x5a>
800249a: 687b ldr r3, [r7, #4]
800249c: 4a21 ldr r2, [pc, #132] ; (8002524 <TIM_Base_SetConfig+0xc4>)
800249e: 4293 cmp r3, r2
80024a0: d00b beq.n 80024ba <TIM_Base_SetConfig+0x5a>
80024a2: 687b ldr r3, [r7, #4]
80024a4: 4a20 ldr r2, [pc, #128] ; (8002528 <TIM_Base_SetConfig+0xc8>)
80024a6: 4293 cmp r3, r2
80024a8: d007 beq.n 80024ba <TIM_Base_SetConfig+0x5a>
80024aa: 687b ldr r3, [r7, #4]
80024ac: 4a1f ldr r2, [pc, #124] ; (800252c <TIM_Base_SetConfig+0xcc>)
80024ae: 4293 cmp r3, r2
80024b0: d003 beq.n 80024ba <TIM_Base_SetConfig+0x5a>
80024b2: 687b ldr r3, [r7, #4]
80024b4: 4a1e ldr r2, [pc, #120] ; (8002530 <TIM_Base_SetConfig+0xd0>)
80024b6: 4293 cmp r3, r2
80024b8: d108 bne.n 80024cc <TIM_Base_SetConfig+0x6c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80024ba: 68fb ldr r3, [r7, #12]
80024bc: 4a1d ldr r2, [pc, #116] ; (8002534 <TIM_Base_SetConfig+0xd4>)
80024be: 4013 ands r3, r2
80024c0: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80024c2: 683b ldr r3, [r7, #0]
80024c4: 68db ldr r3, [r3, #12]
80024c6: 68fa ldr r2, [r7, #12]
80024c8: 4313 orrs r3, r2
80024ca: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80024cc: 68fb ldr r3, [r7, #12]
80024ce: 2280 movs r2, #128 ; 0x80
80024d0: 4393 bics r3, r2
80024d2: 001a movs r2, r3
80024d4: 683b ldr r3, [r7, #0]
80024d6: 695b ldr r3, [r3, #20]
80024d8: 4313 orrs r3, r2
80024da: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80024dc: 687b ldr r3, [r7, #4]
80024de: 68fa ldr r2, [r7, #12]
80024e0: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80024e2: 683b ldr r3, [r7, #0]
80024e4: 689a ldr r2, [r3, #8]
80024e6: 687b ldr r3, [r7, #4]
80024e8: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80024ea: 683b ldr r3, [r7, #0]
80024ec: 681a ldr r2, [r3, #0]
80024ee: 687b ldr r3, [r7, #4]
80024f0: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80024f2: 687b ldr r3, [r7, #4]
80024f4: 4a0a ldr r2, [pc, #40] ; (8002520 <TIM_Base_SetConfig+0xc0>)
80024f6: 4293 cmp r3, r2
80024f8: d007 beq.n 800250a <TIM_Base_SetConfig+0xaa>
80024fa: 687b ldr r3, [r7, #4]
80024fc: 4a0b ldr r2, [pc, #44] ; (800252c <TIM_Base_SetConfig+0xcc>)
80024fe: 4293 cmp r3, r2
8002500: d003 beq.n 800250a <TIM_Base_SetConfig+0xaa>
8002502: 687b ldr r3, [r7, #4]
8002504: 4a0a ldr r2, [pc, #40] ; (8002530 <TIM_Base_SetConfig+0xd0>)
8002506: 4293 cmp r3, r2
8002508: d103 bne.n 8002512 <TIM_Base_SetConfig+0xb2>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800250a: 683b ldr r3, [r7, #0]
800250c: 691a ldr r2, [r3, #16]
800250e: 687b ldr r3, [r7, #4]
8002510: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8002512: 687b ldr r3, [r7, #4]
8002514: 2201 movs r2, #1
8002516: 615a str r2, [r3, #20]
}
8002518: 46c0 nop ; (mov r8, r8)
800251a: 46bd mov sp, r7
800251c: b004 add sp, #16
800251e: bd80 pop {r7, pc}
8002520: 40012c00 .word 0x40012c00
8002524: 40000400 .word 0x40000400
8002528: 40002000 .word 0x40002000
800252c: 40014400 .word 0x40014400
8002530: 40014800 .word 0x40014800
8002534: fffffcff .word 0xfffffcff
08002538 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8002538: b580 push {r7, lr}
800253a: b082 sub sp, #8
800253c: af00 add r7, sp, #0
800253e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8002540: 46c0 nop ; (mov r8, r8)
8002542: 46bd mov sp, r7
8002544: b002 add sp, #8
8002546: bd80 pop {r7, pc}
08002548 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8002548: b580 push {r7, lr}
800254a: b082 sub sp, #8
800254c: af00 add r7, sp, #0
800254e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8002550: 46c0 nop ; (mov r8, r8)
8002552: 46bd mov sp, r7
8002554: b002 add sp, #8
8002556: bd80 pop {r7, pc}
08002558 <GEI_BUTTON_CODE>:
*/
#include "button.h"
void GEI_BUTTON_CODE(struct button *bt,uint8_t in)
{
8002558: b580 push {r7, lr}
800255a: b082 sub sp, #8
800255c: af00 add r7, sp, #0
800255e: 6078 str r0, [r7, #4]
8002560: 000a movs r2, r1
8002562: 1cfb adds r3, r7, #3
8002564: 701a strb r2, [r3, #0]
#define t 250
bt->code=0;
8002566: 687b ldr r3, [r7, #4]
8002568: 2200 movs r2, #0
800256a: 601a str r2, [r3, #0]
if(in==1)
800256c: 1cfb adds r3, r7, #3
800256e: 781b ldrb r3, [r3, #0]
8002570: 2b01 cmp r3, #1
8002572: d138 bne.n 80025e6 <GEI_BUTTON_CODE+0x8e>
{
if(bt->lock==0)
8002574: 687b ldr r3, [r7, #4]
8002576: 791b ldrb r3, [r3, #4]
8002578: 2b00 cmp r3, #0
800257a: d120 bne.n 80025be <GEI_BUTTON_CODE+0x66>
{
if(HAL_GetTick()<bt->time+t)
800257c: f7fe f9fa bl 8000974 <HAL_GetTick>
8002580: 0002 movs r2, r0
8002582: 687b ldr r3, [r7, #4]
8002584: 689b ldr r3, [r3, #8]
8002586: 33fa adds r3, #250 ; 0xfa
8002588: 429a cmp r2, r3
800258a: d20d bcs.n 80025a8 <GEI_BUTTON_CODE+0x50>
{
bt->times++;
800258c: 687b ldr r3, [r7, #4]
800258e: 68db ldr r3, [r3, #12]
8002590: 1c5a adds r2, r3, #1
8002592: 687b ldr r3, [r7, #4]
8002594: 60da str r2, [r3, #12]
bt->time=HAL_GetTick();
8002596: f7fe f9ed bl 8000974 <HAL_GetTick>
800259a: 0002 movs r2, r0
800259c: 687b ldr r3, [r7, #4]
800259e: 609a str r2, [r3, #8]
bt->lock=1;
80025a0: 687b ldr r3, [r7, #4]
80025a2: 2201 movs r2, #1
80025a4: 711a strb r2, [r3, #4]
80025a6: e00a b.n 80025be <GEI_BUTTON_CODE+0x66>
}else
{
bt->times=1;
80025a8: 687b ldr r3, [r7, #4]
80025aa: 2201 movs r2, #1
80025ac: 60da str r2, [r3, #12]
bt->time=HAL_GetTick();
80025ae: f7fe f9e1 bl 8000974 <HAL_GetTick>
80025b2: 0002 movs r2, r0
80025b4: 687b ldr r3, [r7, #4]
80025b6: 609a str r2, [r3, #8]
bt->lock=1;
80025b8: 687b ldr r3, [r7, #4]
80025ba: 2201 movs r2, #1
80025bc: 711a strb r2, [r3, #4]
}
}
if(bt->lock==1)
80025be: 687b ldr r3, [r7, #4]
80025c0: 791b ldrb r3, [r3, #4]
80025c2: 2b01 cmp r3, #1
80025c4: d10f bne.n 80025e6 <GEI_BUTTON_CODE+0x8e>
{
if(HAL_GetTick()>bt->time+t)
80025c6: f7fe f9d5 bl 8000974 <HAL_GetTick>
80025ca: 0002 movs r2, r0
80025cc: 687b ldr r3, [r7, #4]
80025ce: 689b ldr r3, [r3, #8]
80025d0: 33fa adds r3, #250 ; 0xfa
80025d2: 429a cmp r2, r3
80025d4: d907 bls.n 80025e6 <GEI_BUTTON_CODE+0x8e>
{
bt->code=-1;
80025d6: 687b ldr r3, [r7, #4]
80025d8: 2201 movs r2, #1
80025da: 4252 negs r2, r2
80025dc: 601a str r2, [r3, #0]
bt->times=-1;
80025de: 687b ldr r3, [r7, #4]
80025e0: 2201 movs r2, #1
80025e2: 4252 negs r2, r2
80025e4: 60da str r2, [r3, #12]
}
}
}
if(in==0)
80025e6: 1cfb adds r3, r7, #3
80025e8: 781b ldrb r3, [r3, #0]
80025ea: 2b00 cmp r3, #0
80025ec: d10e bne.n 800260c <GEI_BUTTON_CODE+0xb4>
{
if(bt->lock==1)
80025ee: 687b ldr r3, [r7, #4]
80025f0: 791b ldrb r3, [r3, #4]
80025f2: 2b01 cmp r3, #1
80025f4: d10a bne.n 800260c <GEI_BUTTON_CODE+0xb4>
{
if(bt->code==-1)
80025f6: 687b ldr r3, [r7, #4]
80025f8: 681b ldr r3, [r3, #0]
80025fa: 3301 adds r3, #1
80025fc: d003 beq.n 8002606 <GEI_BUTTON_CODE+0xae>
{
}else
{
bt->code=bt->times;
80025fe: 687b ldr r3, [r7, #4]
8002600: 68da ldr r2, [r3, #12]
8002602: 687b ldr r3, [r7, #4]
8002604: 601a str r2, [r3, #0]
}
bt->lock=0;
8002606: 687b ldr r3, [r7, #4]
8002608: 2200 movs r2, #0
800260a: 711a strb r2, [r3, #4]
}
}
}
800260c: 46c0 nop ; (mov r8, r8)
800260e: 46bd mov sp, r7
8002610: b002 add sp, #8
8002612: bd80 pop {r7, pc}
08002614 <change_io_function>:
* Author: wuwenfeng
*/
#include "gpio.h"
void change_io_function(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin,char a)
{
8002614: b580 push {r7, lr}
8002616: b088 sub sp, #32
8002618: af00 add r7, sp, #0
800261a: 6078 str r0, [r7, #4]
800261c: 0008 movs r0, r1
800261e: 0011 movs r1, r2
8002620: 1cbb adds r3, r7, #2
8002622: 1c02 adds r2, r0, #0
8002624: 801a strh r2, [r3, #0]
8002626: 1c7b adds r3, r7, #1
8002628: 1c0a adds r2, r1, #0
800262a: 701a strb r2, [r3, #0]
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = GPIO_Pin;
800262c: 1cbb adds r3, r7, #2
800262e: 881a ldrh r2, [r3, #0]
8002630: 210c movs r1, #12
8002632: 187b adds r3, r7, r1
8002634: 601a str r2, [r3, #0]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8002636: 187b adds r3, r7, r1
8002638: 2203 movs r2, #3
800263a: 60da str r2, [r3, #12]
if(a==1)
800263c: 1c7b adds r3, r7, #1
800263e: 781b ldrb r3, [r3, #0]
8002640: 2b01 cmp r3, #1
8002642: d105 bne.n 8002650 <change_io_function+0x3c>
{
GPIO_InitStruct.Pull = GPIO_PULLUP;
8002644: 187b adds r3, r7, r1
8002646: 2201 movs r2, #1
8002648: 609a str r2, [r3, #8]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800264a: 187b adds r3, r7, r1
800264c: 2200 movs r2, #0
800264e: 605a str r2, [r3, #4]
}
if(a==0)
8002650: 1c7b adds r3, r7, #1
8002652: 781b ldrb r3, [r3, #0]
8002654: 2b00 cmp r3, #0
8002656: d106 bne.n 8002666 <change_io_function+0x52>
{
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002658: 210c movs r1, #12
800265a: 187b adds r3, r7, r1
800265c: 2200 movs r2, #0
800265e: 609a str r2, [r3, #8]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8002660: 187b adds r3, r7, r1
8002662: 2201 movs r2, #1
8002664: 605a str r2, [r3, #4]
}
HAL_GPIO_Init(GPIOx, &GPIO_InitStruct);
8002666: 230c movs r3, #12
8002668: 18fa adds r2, r7, r3
800266a: 687b ldr r3, [r7, #4]
800266c: 0011 movs r1, r2
800266e: 0018 movs r0, r3
8002670: f7fe ff18 bl 80014a4 <HAL_GPIO_Init>
}
8002674: 46c0 nop ; (mov r8, r8)
8002676: 46bd mov sp, r7
8002678: b008 add sp, #32
800267a: bd80 pop {r7, pc}
0800267c <WriteClockHT1621>:
#include "my_code.h"
#define HT1621_addrbit 6
void WriteClockHT1621(void)
{
800267c: b580 push {r7, lr}
800267e: af00 add r7, sp, #0
HC595_SCK(0);
8002680: 2390 movs r3, #144 ; 0x90
8002682: 05db lsls r3, r3, #23
8002684: 2200 movs r2, #0
8002686: 2140 movs r1, #64 ; 0x40
8002688: 0018 movs r0, r3
800268a: f7ff f898 bl 80017be <HAL_GPIO_WritePin>
HC595_SCK(1);
800268e: 2390 movs r3, #144 ; 0x90
8002690: 05db lsls r3, r3, #23
8002692: 2201 movs r2, #1
8002694: 2140 movs r1, #64 ; 0x40
8002696: 0018 movs r0, r3
8002698: f7ff f891 bl 80017be <HAL_GPIO_WritePin>
}
800269c: 46c0 nop ; (mov r8, r8)
800269e: 46bd mov sp, r7
80026a0: bd80 pop {r7, pc}
080026a2 <WriteCommandHT1621>:
void WriteCommandHT1621(unsigned char FunctonCode)
{
80026a2: b580 push {r7, lr}
80026a4: b084 sub sp, #16
80026a6: af00 add r7, sp, #0
80026a8: 0002 movs r2, r0
80026aa: 1dfb adds r3, r7, #7
80026ac: 701a strb r2, [r3, #0]
unsigned char Shift = 0x80;
80026ae: 230f movs r3, #15
80026b0: 18fb adds r3, r7, r3
80026b2: 2280 movs r2, #128 ; 0x80
80026b4: 701a strb r2, [r3, #0]
unsigned char i;
HC595_RCK(0);
80026b6: 2390 movs r3, #144 ; 0x90
80026b8: 05db lsls r3, r3, #23
80026ba: 2200 movs r2, #0
80026bc: 2180 movs r1, #128 ; 0x80
80026be: 0018 movs r0, r3
80026c0: f7ff f87d bl 80017be <HAL_GPIO_WritePin>
HC595_DCK(1);
80026c4: 2390 movs r3, #144 ; 0x90
80026c6: 05db lsls r3, r3, #23
80026c8: 2201 movs r2, #1
80026ca: 2120 movs r1, #32
80026cc: 0018 movs r0, r3
80026ce: f7ff f876 bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80026d2: f7ff ffd3 bl 800267c <WriteClockHT1621>
HC595_DCK(0);
80026d6: 2390 movs r3, #144 ; 0x90
80026d8: 05db lsls r3, r3, #23
80026da: 2200 movs r2, #0
80026dc: 2120 movs r1, #32
80026de: 0018 movs r0, r3
80026e0: f7ff f86d bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80026e4: f7ff ffca bl 800267c <WriteClockHT1621>
HC595_DCK(0);
80026e8: 2390 movs r3, #144 ; 0x90
80026ea: 05db lsls r3, r3, #23
80026ec: 2200 movs r2, #0
80026ee: 2120 movs r1, #32
80026f0: 0018 movs r0, r3
80026f2: f7ff f864 bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80026f6: f7ff ffc1 bl 800267c <WriteClockHT1621>
for(i = 0; i < 8; i++)
80026fa: 230e movs r3, #14
80026fc: 18fb adds r3, r7, r3
80026fe: 2200 movs r2, #0
8002700: 701a strb r2, [r3, #0]
8002702: e025 b.n 8002750 <WriteCommandHT1621+0xae>
{
if(Shift & FunctonCode)
8002704: 230f movs r3, #15
8002706: 18fb adds r3, r7, r3
8002708: 1dfa adds r2, r7, #7
800270a: 781b ldrb r3, [r3, #0]
800270c: 7812 ldrb r2, [r2, #0]
800270e: 4013 ands r3, r2
8002710: b2db uxtb r3, r3
8002712: 2b00 cmp r3, #0
8002714: d007 beq.n 8002726 <WriteCommandHT1621+0x84>
{HC595_DCK(1);}
8002716: 2390 movs r3, #144 ; 0x90
8002718: 05db lsls r3, r3, #23
800271a: 2201 movs r2, #1
800271c: 2120 movs r1, #32
800271e: 0018 movs r0, r3
8002720: f7ff f84d bl 80017be <HAL_GPIO_WritePin>
8002724: e006 b.n 8002734 <WriteCommandHT1621+0x92>
else
{HC595_DCK(0);}
8002726: 2390 movs r3, #144 ; 0x90
8002728: 05db lsls r3, r3, #23
800272a: 2200 movs r2, #0
800272c: 2120 movs r1, #32
800272e: 0018 movs r0, r3
8002730: f7ff f845 bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
8002734: f7ff ffa2 bl 800267c <WriteClockHT1621>
Shift = Shift >> 1;
8002738: 220f movs r2, #15
800273a: 18bb adds r3, r7, r2
800273c: 18ba adds r2, r7, r2
800273e: 7812 ldrb r2, [r2, #0]
8002740: 0852 lsrs r2, r2, #1
8002742: 701a strb r2, [r3, #0]
for(i = 0; i < 8; i++)
8002744: 210e movs r1, #14
8002746: 187b adds r3, r7, r1
8002748: 781a ldrb r2, [r3, #0]
800274a: 187b adds r3, r7, r1
800274c: 3201 adds r2, #1
800274e: 701a strb r2, [r3, #0]
8002750: 230e movs r3, #14
8002752: 18fb adds r3, r7, r3
8002754: 781b ldrb r3, [r3, #0]
8002756: 2b07 cmp r3, #7
8002758: d9d4 bls.n 8002704 <WriteCommandHT1621+0x62>
}
{HC595_DCK(0);}
800275a: 2390 movs r3, #144 ; 0x90
800275c: 05db lsls r3, r3, #23
800275e: 2200 movs r2, #0
8002760: 2120 movs r1, #32
8002762: 0018 movs r0, r3
8002764: f7ff f82b bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
8002768: f7ff ff88 bl 800267c <WriteClockHT1621>
HC595_RCK(1);
800276c: 2390 movs r3, #144 ; 0x90
800276e: 05db lsls r3, r3, #23
8002770: 2201 movs r2, #1
8002772: 2180 movs r1, #128 ; 0x80
8002774: 0018 movs r0, r3
8002776: f7ff f822 bl 80017be <HAL_GPIO_WritePin>
HC595_DCK(1);
800277a: 2390 movs r3, #144 ; 0x90
800277c: 05db lsls r3, r3, #23
800277e: 2201 movs r2, #1
8002780: 2120 movs r1, #32
8002782: 0018 movs r0, r3
8002784: f7ff f81b bl 80017be <HAL_GPIO_WritePin>
}
8002788: 46c0 nop ; (mov r8, r8)
800278a: 46bd mov sp, r7
800278c: b004 add sp, #16
800278e: bd80 pop {r7, pc}
08002790 <WritenDataHT1621>:
void WritenDataHT1621(unsigned char Addr,unsigned char *Databuf,unsigned char Cnt)
{
8002790: b580 push {r7, lr}
8002792: b084 sub sp, #16
8002794: af00 add r7, sp, #0
8002796: 6039 str r1, [r7, #0]
8002798: 0011 movs r1, r2
800279a: 1dfb adds r3, r7, #7
800279c: 1c02 adds r2, r0, #0
800279e: 701a strb r2, [r3, #0]
80027a0: 1dbb adds r3, r7, #6
80027a2: 1c0a adds r2, r1, #0
80027a4: 701a strb r2, [r3, #0]
unsigned char i,j;
unsigned char Shift;
unsigned char dataval;
HC595_RCK(0);
80027a6: 2390 movs r3, #144 ; 0x90
80027a8: 05db lsls r3, r3, #23
80027aa: 2200 movs r2, #0
80027ac: 2180 movs r1, #128 ; 0x80
80027ae: 0018 movs r0, r3
80027b0: f7ff f805 bl 80017be <HAL_GPIO_WritePin>
HC595_DCK(1); //101
80027b4: 2390 movs r3, #144 ; 0x90
80027b6: 05db lsls r3, r3, #23
80027b8: 2201 movs r2, #1
80027ba: 2120 movs r1, #32
80027bc: 0018 movs r0, r3
80027be: f7fe fffe bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80027c2: f7ff ff5b bl 800267c <WriteClockHT1621>
HC595_DCK(0);
80027c6: 2390 movs r3, #144 ; 0x90
80027c8: 05db lsls r3, r3, #23
80027ca: 2200 movs r2, #0
80027cc: 2120 movs r1, #32
80027ce: 0018 movs r0, r3
80027d0: f7fe fff5 bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80027d4: f7ff ff52 bl 800267c <WriteClockHT1621>
HC595_DCK(1);
80027d8: 2390 movs r3, #144 ; 0x90
80027da: 05db lsls r3, r3, #23
80027dc: 2201 movs r2, #1
80027de: 2120 movs r1, #32
80027e0: 0018 movs r0, r3
80027e2: f7fe ffec bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80027e6: f7ff ff49 bl 800267c <WriteClockHT1621>
Shift = 0x20;
80027ea: 230d movs r3, #13
80027ec: 18fb adds r3, r7, r3
80027ee: 2220 movs r2, #32
80027f0: 701a strb r2, [r3, #0]
for( i = 0; i < HT1621_addrbit; i++)
80027f2: 230f movs r3, #15
80027f4: 18fb adds r3, r7, r3
80027f6: 2200 movs r2, #0
80027f8: 701a strb r2, [r3, #0]
80027fa: e025 b.n 8002848 <WritenDataHT1621+0xb8>
{
if (Addr & Shift)
80027fc: 1dfb adds r3, r7, #7
80027fe: 220d movs r2, #13
8002800: 18ba adds r2, r7, r2
8002802: 781b ldrb r3, [r3, #0]
8002804: 7812 ldrb r2, [r2, #0]
8002806: 4013 ands r3, r2
8002808: b2db uxtb r3, r3
800280a: 2b00 cmp r3, #0
800280c: d007 beq.n 800281e <WritenDataHT1621+0x8e>
{HC595_DCK(1);}
800280e: 2390 movs r3, #144 ; 0x90
8002810: 05db lsls r3, r3, #23
8002812: 2201 movs r2, #1
8002814: 2120 movs r1, #32
8002816: 0018 movs r0, r3
8002818: f7fe ffd1 bl 80017be <HAL_GPIO_WritePin>
800281c: e006 b.n 800282c <WritenDataHT1621+0x9c>
else
{HC595_DCK(0);}
800281e: 2390 movs r3, #144 ; 0x90
8002820: 05db lsls r3, r3, #23
8002822: 2200 movs r2, #0
8002824: 2120 movs r1, #32
8002826: 0018 movs r0, r3
8002828: f7fe ffc9 bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
800282c: f7ff ff26 bl 800267c <WriteClockHT1621>
Shift = Shift >> 1;
8002830: 220d movs r2, #13
8002832: 18bb adds r3, r7, r2
8002834: 18ba adds r2, r7, r2
8002836: 7812 ldrb r2, [r2, #0]
8002838: 0852 lsrs r2, r2, #1
800283a: 701a strb r2, [r3, #0]
for( i = 0; i < HT1621_addrbit; i++)
800283c: 210f movs r1, #15
800283e: 187b adds r3, r7, r1
8002840: 781a ldrb r2, [r3, #0]
8002842: 187b adds r3, r7, r1
8002844: 3201 adds r2, #1
8002846: 701a strb r2, [r3, #0]
8002848: 230f movs r3, #15
800284a: 18fb adds r3, r7, r3
800284c: 781b ldrb r3, [r3, #0]
800284e: 2b05 cmp r3, #5
8002850: d9d4 bls.n 80027fc <WritenDataHT1621+0x6c>
}
for (j = 0; j < Cnt; j++)
8002852: 230e movs r3, #14
8002854: 18fb adds r3, r7, r3
8002856: 2200 movs r2, #0
8002858: 701a strb r2, [r3, #0]
800285a: e041 b.n 80028e0 <WritenDataHT1621+0x150>
{
Shift = 0x01;
800285c: 230d movs r3, #13
800285e: 18fb adds r3, r7, r3
8002860: 2201 movs r2, #1
8002862: 701a strb r2, [r3, #0]
dataval=*Databuf++;
8002864: 683b ldr r3, [r7, #0]
8002866: 1c5a adds r2, r3, #1
8002868: 603a str r2, [r7, #0]
800286a: 220c movs r2, #12
800286c: 18ba adds r2, r7, r2
800286e: 781b ldrb r3, [r3, #0]
8002870: 7013 strb r3, [r2, #0]
for (i = 0; i < 4; i++)
8002872: 230f movs r3, #15
8002874: 18fb adds r3, r7, r3
8002876: 2200 movs r2, #0
8002878: 701a strb r2, [r3, #0]
800287a: e026 b.n 80028ca <WritenDataHT1621+0x13a>
{
if( dataval & Shift)
800287c: 230c movs r3, #12
800287e: 18fb adds r3, r7, r3
8002880: 220d movs r2, #13
8002882: 18ba adds r2, r7, r2
8002884: 781b ldrb r3, [r3, #0]
8002886: 7812 ldrb r2, [r2, #0]
8002888: 4013 ands r3, r2
800288a: b2db uxtb r3, r3
800288c: 2b00 cmp r3, #0
800288e: d007 beq.n 80028a0 <WritenDataHT1621+0x110>
{HC595_DCK(1);}
8002890: 2390 movs r3, #144 ; 0x90
8002892: 05db lsls r3, r3, #23
8002894: 2201 movs r2, #1
8002896: 2120 movs r1, #32
8002898: 0018 movs r0, r3
800289a: f7fe ff90 bl 80017be <HAL_GPIO_WritePin>
800289e: e006 b.n 80028ae <WritenDataHT1621+0x11e>
else
{HC595_DCK(0);}
80028a0: 2390 movs r3, #144 ; 0x90
80028a2: 05db lsls r3, r3, #23
80028a4: 2200 movs r2, #0
80028a6: 2120 movs r1, #32
80028a8: 0018 movs r0, r3
80028aa: f7fe ff88 bl 80017be <HAL_GPIO_WritePin>
WriteClockHT1621();
80028ae: f7ff fee5 bl 800267c <WriteClockHT1621>
Shift = Shift << 1;
80028b2: 230d movs r3, #13
80028b4: 18fa adds r2, r7, r3
80028b6: 18fb adds r3, r7, r3
80028b8: 781b ldrb r3, [r3, #0]
80028ba: 18db adds r3, r3, r3
80028bc: 7013 strb r3, [r2, #0]
for (i = 0; i < 4; i++)
80028be: 210f movs r1, #15
80028c0: 187b adds r3, r7, r1
80028c2: 781a ldrb r2, [r3, #0]
80028c4: 187b adds r3, r7, r1
80028c6: 3201 adds r2, #1
80028c8: 701a strb r2, [r3, #0]
80028ca: 230f movs r3, #15
80028cc: 18fb adds r3, r7, r3
80028ce: 781b ldrb r3, [r3, #0]
80028d0: 2b03 cmp r3, #3
80028d2: d9d3 bls.n 800287c <WritenDataHT1621+0xec>
for (j = 0; j < Cnt; j++)
80028d4: 210e movs r1, #14
80028d6: 187b adds r3, r7, r1
80028d8: 781a ldrb r2, [r3, #0]
80028da: 187b adds r3, r7, r1
80028dc: 3201 adds r2, #1
80028de: 701a strb r2, [r3, #0]
80028e0: 230e movs r3, #14
80028e2: 18fa adds r2, r7, r3
80028e4: 1dbb adds r3, r7, #6
80028e6: 7812 ldrb r2, [r2, #0]
80028e8: 781b ldrb r3, [r3, #0]
80028ea: 429a cmp r2, r3
80028ec: d3b6 bcc.n 800285c <WritenDataHT1621+0xcc>
}
}
HC595_RCK(1);
80028ee: 2390 movs r3, #144 ; 0x90
80028f0: 05db lsls r3, r3, #23
80028f2: 2201 movs r2, #1
80028f4: 2180 movs r1, #128 ; 0x80
80028f6: 0018 movs r0, r3
80028f8: f7fe ff61 bl 80017be <HAL_GPIO_WritePin>
HC595_DCK(1);
80028fc: 2390 movs r3, #144 ; 0x90
80028fe: 05db lsls r3, r3, #23
8002900: 2201 movs r2, #1
8002902: 2120 movs r1, #32
8002904: 0018 movs r0, r3
8002906: f7fe ff5a bl 80017be <HAL_GPIO_WritePin>
}
800290a: 46c0 nop ; (mov r8, r8)
800290c: 46bd mov sp, r7
800290e: b004 add sp, #16
8002910: bd80 pop {r7, pc}
08002912 <HT1621_Init>:
void HT1621_Init(void)
{
8002912: b580 push {r7, lr}
8002914: af00 add r7, sp, #0
HC595_RCK(1);
8002916: 2390 movs r3, #144 ; 0x90
8002918: 05db lsls r3, r3, #23
800291a: 2201 movs r2, #1
800291c: 2180 movs r1, #128 ; 0x80
800291e: 0018 movs r0, r3
8002920: f7fe ff4d bl 80017be <HAL_GPIO_WritePin>
HC595_SCK(1);
8002924: 2390 movs r3, #144 ; 0x90
8002926: 05db lsls r3, r3, #23
8002928: 2201 movs r2, #1
800292a: 2140 movs r1, #64 ; 0x40
800292c: 0018 movs r0, r3
800292e: f7fe ff46 bl 80017be <HAL_GPIO_WritePin>
HC595_DCK(1);
8002932: 2390 movs r3, #144 ; 0x90
8002934: 05db lsls r3, r3, #23
8002936: 2201 movs r2, #1
8002938: 2120 movs r1, #32
800293a: 0018 movs r0, r3
800293c: f7fe ff3f bl 80017be <HAL_GPIO_WritePin>
WriteCommandHT1621(OSC_ON);
8002940: 2001 movs r0, #1
8002942: f7ff feae bl 80026a2 <WriteCommandHT1621>
WriteCommandHT1621(DISP_ON);
8002946: 2003 movs r0, #3
8002948: f7ff feab bl 80026a2 <WriteCommandHT1621>
WriteCommandHT1621(COM_1_3__4);
800294c: 2029 movs r0, #41 ; 0x29
800294e: f7ff fea8 bl 80026a2 <WriteCommandHT1621>
WriteCommandHT1621(TIMER_DIS);
8002952: 2004 movs r0, #4
8002954: f7ff fea5 bl 80026a2 <WriteCommandHT1621>
WriteCommandHT1621(WDT_DIS);
8002958: 2005 movs r0, #5
800295a: f7ff fea2 bl 80026a2 <WriteCommandHT1621>
WriteCommandHT1621(BUZZ_OFF);
800295e: 2008 movs r0, #8
8002960: f7ff fe9f bl 80026a2 <WriteCommandHT1621>
WriteCommandHT1621(IRQ_DIS);
8002964: 2080 movs r0, #128 ; 0x80
8002966: f7ff fe9c bl 80026a2 <WriteCommandHT1621>
}
800296a: 46c0 nop ; (mov r8, r8)
800296c: 46bd mov sp, r7
800296e: bd80 pop {r7, pc}
08002970 <Sand_Byte_to_595_2>:
//return READ_HC595_DCK;
}
//send data to 959
void Sand_Byte_to_595_2(uint8_t h)
{
8002970: b580 push {r7, lr}
8002972: b084 sub sp, #16
8002974: af00 add r7, sp, #0
8002976: 0002 movs r2, r0
8002978: 1dfb adds r3, r7, #7
800297a: 701a strb r2, [r3, #0]
change_io_function(HC595_DLK_GPIO_Port,HC595_DLK_Pin,0);
800297c: 2390 movs r3, #144 ; 0x90
800297e: 05db lsls r3, r3, #23
8002980: 2200 movs r2, #0
8002982: 2120 movs r1, #32
8002984: 0018 movs r0, r3
8002986: f7ff fe45 bl 8002614 <change_io_function>
HC595_DCK(0);
800298a: 2390 movs r3, #144 ; 0x90
800298c: 05db lsls r3, r3, #23
800298e: 2200 movs r2, #0
8002990: 2120 movs r1, #32
8002992: 0018 movs r0, r3
8002994: f7fe ff13 bl 80017be <HAL_GPIO_WritePin>
HC595_SCK2(0);
8002998: 2380 movs r3, #128 ; 0x80
800299a: 0099 lsls r1, r3, #2
800299c: 2390 movs r3, #144 ; 0x90
800299e: 05db lsls r3, r3, #23
80029a0: 2200 movs r2, #0
80029a2: 0018 movs r0, r3
80029a4: f7fe ff0b bl 80017be <HAL_GPIO_WritePin>
HC595_RCK(0);
80029a8: 2390 movs r3, #144 ; 0x90
80029aa: 05db lsls r3, r3, #23
80029ac: 2200 movs r2, #0
80029ae: 2180 movs r1, #128 ; 0x80
80029b0: 0018 movs r0, r3
80029b2: f7fe ff04 bl 80017be <HAL_GPIO_WritePin>
for(char a=0;a<8;a++)
80029b6: 230f movs r3, #15
80029b8: 18fb adds r3, r7, r3
80029ba: 2200 movs r2, #0
80029bc: 701a strb r2, [r3, #0]
80029be: e02e b.n 8002a1e <Sand_Byte_to_595_2+0xae>
{
if((h<<a)&0x80)
80029c0: 1dfb adds r3, r7, #7
80029c2: 781a ldrb r2, [r3, #0]
80029c4: 230f movs r3, #15
80029c6: 18fb adds r3, r7, r3
80029c8: 781b ldrb r3, [r3, #0]
80029ca: 409a lsls r2, r3
80029cc: 0013 movs r3, r2
80029ce: 2280 movs r2, #128 ; 0x80
80029d0: 4013 ands r3, r2
80029d2: d007 beq.n 80029e4 <Sand_Byte_to_595_2+0x74>
{
HC595_DCK(1);
80029d4: 2390 movs r3, #144 ; 0x90
80029d6: 05db lsls r3, r3, #23
80029d8: 2201 movs r2, #1
80029da: 2120 movs r1, #32
80029dc: 0018 movs r0, r3
80029de: f7fe feee bl 80017be <HAL_GPIO_WritePin>
80029e2: e006 b.n 80029f2 <Sand_Byte_to_595_2+0x82>
}else
{
HC595_DCK(0);
80029e4: 2390 movs r3, #144 ; 0x90
80029e6: 05db lsls r3, r3, #23
80029e8: 2200 movs r2, #0
80029ea: 2120 movs r1, #32
80029ec: 0018 movs r0, r3
80029ee: f7fe fee6 bl 80017be <HAL_GPIO_WritePin>
}
HC595_SCK2(1);
80029f2: 2380 movs r3, #128 ; 0x80
80029f4: 0099 lsls r1, r3, #2
80029f6: 2390 movs r3, #144 ; 0x90
80029f8: 05db lsls r3, r3, #23
80029fa: 2201 movs r2, #1
80029fc: 0018 movs r0, r3
80029fe: f7fe fede bl 80017be <HAL_GPIO_WritePin>
HC595_SCK2(0);
8002a02: 2380 movs r3, #128 ; 0x80
8002a04: 0099 lsls r1, r3, #2
8002a06: 2390 movs r3, #144 ; 0x90
8002a08: 05db lsls r3, r3, #23
8002a0a: 2200 movs r2, #0
8002a0c: 0018 movs r0, r3
8002a0e: f7fe fed6 bl 80017be <HAL_GPIO_WritePin>
for(char a=0;a<8;a++)
8002a12: 210f movs r1, #15
8002a14: 187b adds r3, r7, r1
8002a16: 781a ldrb r2, [r3, #0]
8002a18: 187b adds r3, r7, r1
8002a1a: 3201 adds r2, #1
8002a1c: 701a strb r2, [r3, #0]
8002a1e: 230f movs r3, #15
8002a20: 18fb adds r3, r7, r3
8002a22: 781b ldrb r3, [r3, #0]
8002a24: 2b07 cmp r3, #7
8002a26: d9cb bls.n 80029c0 <Sand_Byte_to_595_2+0x50>
}
HC595_RCK(1);
8002a28: 2390 movs r3, #144 ; 0x90
8002a2a: 05db lsls r3, r3, #23
8002a2c: 2201 movs r2, #1
8002a2e: 2180 movs r1, #128 ; 0x80
8002a30: 0018 movs r0, r3
8002a32: f7fe fec4 bl 80017be <HAL_GPIO_WritePin>
HC595_RCK(0);
8002a36: 2390 movs r3, #144 ; 0x90
8002a38: 05db lsls r3, r3, #23
8002a3a: 2200 movs r2, #0
8002a3c: 2180 movs r1, #128 ; 0x80
8002a3e: 0018 movs r0, r3
8002a40: f7fe febd bl 80017be <HAL_GPIO_WritePin>
}
8002a44: 46c0 nop ; (mov r8, r8)
8002a46: 46bd mov sp, r7
8002a48: b004 add sp, #16
8002a4a: bd80 pop {r7, pc}
08002a4c <hc2_sever>:
void hc2_sever()
{
8002a4c: b580 push {r7, lr}
8002a4e: b082 sub sp, #8
8002a50: af00 add r7, sp, #0
char h=0;
8002a52: 1dfb adds r3, r7, #7
8002a54: 2200 movs r2, #0
8002a56: 701a strb r2, [r3, #0]
if(dis_buff.led_run==1)
8002a58: 4b1d ldr r3, [pc, #116] ; (8002ad0 <hc2_sever+0x84>)
8002a5a: 7b1b ldrb r3, [r3, #12]
8002a5c: 2b01 cmp r3, #1
8002a5e: d105 bne.n 8002a6c <hc2_sever+0x20>
{
h|=0x01;
8002a60: 1dfb adds r3, r7, #7
8002a62: 1dfa adds r2, r7, #7
8002a64: 7812 ldrb r2, [r2, #0]
8002a66: 2101 movs r1, #1
8002a68: 430a orrs r2, r1
8002a6a: 701a strb r2, [r3, #0]
}
if(dis_buff.moto1a==1)
8002a6c: 4b18 ldr r3, [pc, #96] ; (8002ad0 <hc2_sever+0x84>)
8002a6e: 7b5b ldrb r3, [r3, #13]
8002a70: 2b01 cmp r3, #1
8002a72: d105 bne.n 8002a80 <hc2_sever+0x34>
{
h|=0x02;
8002a74: 1dfb adds r3, r7, #7
8002a76: 1dfa adds r2, r7, #7
8002a78: 7812 ldrb r2, [r2, #0]
8002a7a: 2102 movs r1, #2
8002a7c: 430a orrs r2, r1
8002a7e: 701a strb r2, [r3, #0]
}
if(dis_buff.moto1b==1)
8002a80: 4b13 ldr r3, [pc, #76] ; (8002ad0 <hc2_sever+0x84>)
8002a82: 7b9b ldrb r3, [r3, #14]
8002a84: 2b01 cmp r3, #1
8002a86: d105 bne.n 8002a94 <hc2_sever+0x48>
{
h|=0x04;
8002a88: 1dfb adds r3, r7, #7
8002a8a: 1dfa adds r2, r7, #7
8002a8c: 7812 ldrb r2, [r2, #0]
8002a8e: 2104 movs r1, #4
8002a90: 430a orrs r2, r1
8002a92: 701a strb r2, [r3, #0]
}
if(dis_buff.moto2a==1)
8002a94: 4b0e ldr r3, [pc, #56] ; (8002ad0 <hc2_sever+0x84>)
8002a96: 7bdb ldrb r3, [r3, #15]
8002a98: 2b01 cmp r3, #1
8002a9a: d105 bne.n 8002aa8 <hc2_sever+0x5c>
{
h|=0x08;
8002a9c: 1dfb adds r3, r7, #7
8002a9e: 1dfa adds r2, r7, #7
8002aa0: 7812 ldrb r2, [r2, #0]
8002aa2: 2108 movs r1, #8
8002aa4: 430a orrs r2, r1
8002aa6: 701a strb r2, [r3, #0]
}
if(dis_buff.moto2b==1)
8002aa8: 4b09 ldr r3, [pc, #36] ; (8002ad0 <hc2_sever+0x84>)
8002aaa: 7c1b ldrb r3, [r3, #16]
8002aac: 2b01 cmp r3, #1
8002aae: d105 bne.n 8002abc <hc2_sever+0x70>
{
h|=0x10;
8002ab0: 1dfb adds r3, r7, #7
8002ab2: 1dfa adds r2, r7, #7
8002ab4: 7812 ldrb r2, [r2, #0]
8002ab6: 2110 movs r1, #16
8002ab8: 430a orrs r2, r1
8002aba: 701a strb r2, [r3, #0]
}
Sand_Byte_to_595_2(h);
8002abc: 1dfb adds r3, r7, #7
8002abe: 781b ldrb r3, [r3, #0]
8002ac0: 0018 movs r0, r3
8002ac2: f7ff ff55 bl 8002970 <Sand_Byte_to_595_2>
}
8002ac6: 46c0 nop ; (mov r8, r8)
8002ac8: 46bd mov sp, r7
8002aca: b002 add sp, #8
8002acc: bd80 pop {r7, pc}
8002ace: 46c0 nop ; (mov r8, r8)
8002ad0: 20000038 .word 0x20000038
08002ad4 <moto_server>:
//motor cool start
void moto_server()
{
8002ad4: b580 push {r7, lr}
8002ad6: af00 add r7, sp, #0
if(HAL_GetTick()>moto.moto_run)
8002ad8: f7fd ff4c bl 8000974 <HAL_GetTick>
8002adc: 0002 movs r2, r0
8002ade: 4b63 ldr r3, [pc, #396] ; (8002c6c <moto_server+0x198>)
8002ae0: 681b ldr r3, [r3, #0]
8002ae2: 429a cmp r2, r3
8002ae4: d800 bhi.n 8002ae8 <moto_server+0x14>
8002ae6: e07e b.n 8002be6 <moto_server+0x112>
{
moto.moto_run=HAL_GetTick()+10;
8002ae8: f7fd ff44 bl 8000974 <HAL_GetTick>
8002aec: 0003 movs r3, r0
8002aee: 330a adds r3, #10
8002af0: 001a movs r2, r3
8002af2: 4b5e ldr r3, [pc, #376] ; (8002c6c <moto_server+0x198>)
8002af4: 601a str r2, [r3, #0]
if(moto.moto1a!=moto.moto1a_)
8002af6: 4b5d ldr r3, [pc, #372] ; (8002c6c <moto_server+0x198>)
8002af8: 7a1a ldrb r2, [r3, #8]
8002afa: 4b5c ldr r3, [pc, #368] ; (8002c6c <moto_server+0x198>)
8002afc: 7b1b ldrb r3, [r3, #12]
8002afe: 429a cmp r2, r3
8002b00: d017 beq.n 8002b32 <moto_server+0x5e>
{
if(moto.moto1a>moto.moto1a_)
8002b02: 4b5a ldr r3, [pc, #360] ; (8002c6c <moto_server+0x198>)
8002b04: 7a1a ldrb r2, [r3, #8]
8002b06: 4b59 ldr r3, [pc, #356] ; (8002c6c <moto_server+0x198>)
8002b08: 7b1b ldrb r3, [r3, #12]
8002b0a: 429a cmp r2, r3
8002b0c: d905 bls.n 8002b1a <moto_server+0x46>
{
moto.moto1a_++;
8002b0e: 4b57 ldr r3, [pc, #348] ; (8002c6c <moto_server+0x198>)
8002b10: 7b1b ldrb r3, [r3, #12]
8002b12: 3301 adds r3, #1
8002b14: b2da uxtb r2, r3
8002b16: 4b55 ldr r3, [pc, #340] ; (8002c6c <moto_server+0x198>)
8002b18: 731a strb r2, [r3, #12]
}
if(moto.moto1a<moto.moto1a_)
8002b1a: 4b54 ldr r3, [pc, #336] ; (8002c6c <moto_server+0x198>)
8002b1c: 7a1a ldrb r2, [r3, #8]
8002b1e: 4b53 ldr r3, [pc, #332] ; (8002c6c <moto_server+0x198>)
8002b20: 7b1b ldrb r3, [r3, #12]
8002b22: 429a cmp r2, r3
8002b24: d205 bcs.n 8002b32 <moto_server+0x5e>
{
moto.moto1a_--;
8002b26: 4b51 ldr r3, [pc, #324] ; (8002c6c <moto_server+0x198>)
8002b28: 7b1b ldrb r3, [r3, #12]
8002b2a: 3b01 subs r3, #1
8002b2c: b2da uxtb r2, r3
8002b2e: 4b4f ldr r3, [pc, #316] ; (8002c6c <moto_server+0x198>)
8002b30: 731a strb r2, [r3, #12]
}
}
if(moto.moto1b!=moto.moto1b_)
8002b32: 4b4e ldr r3, [pc, #312] ; (8002c6c <moto_server+0x198>)
8002b34: 7a5a ldrb r2, [r3, #9]
8002b36: 4b4d ldr r3, [pc, #308] ; (8002c6c <moto_server+0x198>)
8002b38: 7b5b ldrb r3, [r3, #13]
8002b3a: 429a cmp r2, r3
8002b3c: d017 beq.n 8002b6e <moto_server+0x9a>
{
if(moto.moto1b>moto.moto1b_)
8002b3e: 4b4b ldr r3, [pc, #300] ; (8002c6c <moto_server+0x198>)
8002b40: 7a5a ldrb r2, [r3, #9]
8002b42: 4b4a ldr r3, [pc, #296] ; (8002c6c <moto_server+0x198>)
8002b44: 7b5b ldrb r3, [r3, #13]
8002b46: 429a cmp r2, r3
8002b48: d905 bls.n 8002b56 <moto_server+0x82>
{
moto.moto1b_++;
8002b4a: 4b48 ldr r3, [pc, #288] ; (8002c6c <moto_server+0x198>)
8002b4c: 7b5b ldrb r3, [r3, #13]
8002b4e: 3301 adds r3, #1
8002b50: b2da uxtb r2, r3
8002b52: 4b46 ldr r3, [pc, #280] ; (8002c6c <moto_server+0x198>)
8002b54: 735a strb r2, [r3, #13]
}
if(moto.moto1b<moto.moto1b_)
8002b56: 4b45 ldr r3, [pc, #276] ; (8002c6c <moto_server+0x198>)
8002b58: 7a5a ldrb r2, [r3, #9]
8002b5a: 4b44 ldr r3, [pc, #272] ; (8002c6c <moto_server+0x198>)
8002b5c: 7b5b ldrb r3, [r3, #13]
8002b5e: 429a cmp r2, r3
8002b60: d205 bcs.n 8002b6e <moto_server+0x9a>
{
moto.moto1b_--;
8002b62: 4b42 ldr r3, [pc, #264] ; (8002c6c <moto_server+0x198>)
8002b64: 7b5b ldrb r3, [r3, #13]
8002b66: 3b01 subs r3, #1
8002b68: b2da uxtb r2, r3
8002b6a: 4b40 ldr r3, [pc, #256] ; (8002c6c <moto_server+0x198>)
8002b6c: 735a strb r2, [r3, #13]
}
}
if(moto.moto2a!=moto.moto2a_)
8002b6e: 4b3f ldr r3, [pc, #252] ; (8002c6c <moto_server+0x198>)
8002b70: 7a9a ldrb r2, [r3, #10]
8002b72: 4b3e ldr r3, [pc, #248] ; (8002c6c <moto_server+0x198>)
8002b74: 7b9b ldrb r3, [r3, #14]
8002b76: 429a cmp r2, r3
8002b78: d017 beq.n 8002baa <moto_server+0xd6>
{
if(moto.moto2a>moto.moto2a_)
8002b7a: 4b3c ldr r3, [pc, #240] ; (8002c6c <moto_server+0x198>)
8002b7c: 7a9a ldrb r2, [r3, #10]
8002b7e: 4b3b ldr r3, [pc, #236] ; (8002c6c <moto_server+0x198>)
8002b80: 7b9b ldrb r3, [r3, #14]
8002b82: 429a cmp r2, r3
8002b84: d905 bls.n 8002b92 <moto_server+0xbe>
{
moto.moto2a_++;
8002b86: 4b39 ldr r3, [pc, #228] ; (8002c6c <moto_server+0x198>)
8002b88: 7b9b ldrb r3, [r3, #14]
8002b8a: 3301 adds r3, #1
8002b8c: b2da uxtb r2, r3
8002b8e: 4b37 ldr r3, [pc, #220] ; (8002c6c <moto_server+0x198>)
8002b90: 739a strb r2, [r3, #14]
}
if(moto.moto2a<moto.moto2a_)
8002b92: 4b36 ldr r3, [pc, #216] ; (8002c6c <moto_server+0x198>)
8002b94: 7a9a ldrb r2, [r3, #10]
8002b96: 4b35 ldr r3, [pc, #212] ; (8002c6c <moto_server+0x198>)
8002b98: 7b9b ldrb r3, [r3, #14]
8002b9a: 429a cmp r2, r3
8002b9c: d205 bcs.n 8002baa <moto_server+0xd6>
{
moto.moto2a_--;
8002b9e: 4b33 ldr r3, [pc, #204] ; (8002c6c <moto_server+0x198>)
8002ba0: 7b9b ldrb r3, [r3, #14]
8002ba2: 3b01 subs r3, #1
8002ba4: b2da uxtb r2, r3
8002ba6: 4b31 ldr r3, [pc, #196] ; (8002c6c <moto_server+0x198>)
8002ba8: 739a strb r2, [r3, #14]
}
}
if(moto.moto2b!=moto.moto2b_)
8002baa: 4b30 ldr r3, [pc, #192] ; (8002c6c <moto_server+0x198>)
8002bac: 7ada ldrb r2, [r3, #11]
8002bae: 4b2f ldr r3, [pc, #188] ; (8002c6c <moto_server+0x198>)
8002bb0: 7bdb ldrb r3, [r3, #15]
8002bb2: 429a cmp r2, r3
8002bb4: d017 beq.n 8002be6 <moto_server+0x112>
{
if(moto.moto2b>moto.moto2b_)
8002bb6: 4b2d ldr r3, [pc, #180] ; (8002c6c <moto_server+0x198>)
8002bb8: 7ada ldrb r2, [r3, #11]
8002bba: 4b2c ldr r3, [pc, #176] ; (8002c6c <moto_server+0x198>)
8002bbc: 7bdb ldrb r3, [r3, #15]
8002bbe: 429a cmp r2, r3
8002bc0: d905 bls.n 8002bce <moto_server+0xfa>
{
moto.moto2b_++;
8002bc2: 4b2a ldr r3, [pc, #168] ; (8002c6c <moto_server+0x198>)
8002bc4: 7bdb ldrb r3, [r3, #15]
8002bc6: 3301 adds r3, #1
8002bc8: b2da uxtb r2, r3
8002bca: 4b28 ldr r3, [pc, #160] ; (8002c6c <moto_server+0x198>)
8002bcc: 73da strb r2, [r3, #15]
}
if(moto.moto2b<moto.moto2b_)
8002bce: 4b27 ldr r3, [pc, #156] ; (8002c6c <moto_server+0x198>)
8002bd0: 7ada ldrb r2, [r3, #11]
8002bd2: 4b26 ldr r3, [pc, #152] ; (8002c6c <moto_server+0x198>)
8002bd4: 7bdb ldrb r3, [r3, #15]
8002bd6: 429a cmp r2, r3
8002bd8: d205 bcs.n 8002be6 <moto_server+0x112>
{
moto.moto2b_--;
8002bda: 4b24 ldr r3, [pc, #144] ; (8002c6c <moto_server+0x198>)
8002bdc: 7bdb ldrb r3, [r3, #15]
8002bde: 3b01 subs r3, #1
8002be0: b2da uxtb r2, r3
8002be2: 4b22 ldr r3, [pc, #136] ; (8002c6c <moto_server+0x198>)
8002be4: 73da strb r2, [r3, #15]
moto.pwm_run++;
8002be6: 4b21 ldr r3, [pc, #132] ; (8002c6c <moto_server+0x198>)
8002be8: 685b ldr r3, [r3, #4]
8002bea: 1c5a adds r2, r3, #1
8002bec: 4b1f ldr r3, [pc, #124] ; (8002c6c <moto_server+0x198>)
8002bee: 605a str r2, [r3, #4]
if(moto.pwm_run==10)
8002bf0: 4b1e ldr r3, [pc, #120] ; (8002c6c <moto_server+0x198>)
8002bf2: 685b ldr r3, [r3, #4]
8002bf4: 2b0a cmp r3, #10
8002bf6: d102 bne.n 8002bfe <moto_server+0x12a>
{
moto.pwm_run=0;
8002bf8: 4b1c ldr r3, [pc, #112] ; (8002c6c <moto_server+0x198>)
8002bfa: 2200 movs r2, #0
8002bfc: 605a str r2, [r3, #4]
}
if(moto.pwm_run<moto.moto1a_)
8002bfe: 4b1b ldr r3, [pc, #108] ; (8002c6c <moto_server+0x198>)
8002c00: 685b ldr r3, [r3, #4]
8002c02: 4a1a ldr r2, [pc, #104] ; (8002c6c <moto_server+0x198>)
8002c04: 7b12 ldrb r2, [r2, #12]
8002c06: 4293 cmp r3, r2
8002c08: da03 bge.n 8002c12 <moto_server+0x13e>
{
dis_buff.moto1a=1;
8002c0a: 4b19 ldr r3, [pc, #100] ; (8002c70 <moto_server+0x19c>)
8002c0c: 2201 movs r2, #1
8002c0e: 735a strb r2, [r3, #13]
8002c10: e002 b.n 8002c18 <moto_server+0x144>
}else
{
dis_buff.moto1a=0;
8002c12: 4b17 ldr r3, [pc, #92] ; (8002c70 <moto_server+0x19c>)
8002c14: 2200 movs r2, #0
8002c16: 735a strb r2, [r3, #13]
}
if(moto.pwm_run<moto.moto1b_)
8002c18: 4b14 ldr r3, [pc, #80] ; (8002c6c <moto_server+0x198>)
8002c1a: 685b ldr r3, [r3, #4]
8002c1c: 4a13 ldr r2, [pc, #76] ; (8002c6c <moto_server+0x198>)
8002c1e: 7b52 ldrb r2, [r2, #13]
8002c20: 4293 cmp r3, r2
8002c22: da03 bge.n 8002c2c <moto_server+0x158>
{
dis_buff.moto1b=1;
8002c24: 4b12 ldr r3, [pc, #72] ; (8002c70 <moto_server+0x19c>)
8002c26: 2201 movs r2, #1
8002c28: 739a strb r2, [r3, #14]
8002c2a: e002 b.n 8002c32 <moto_server+0x15e>
}else
{
dis_buff.moto1b=0;
8002c2c: 4b10 ldr r3, [pc, #64] ; (8002c70 <moto_server+0x19c>)
8002c2e: 2200 movs r2, #0
8002c30: 739a strb r2, [r3, #14]
}
if(moto.pwm_run<moto.moto2a_)
8002c32: 4b0e ldr r3, [pc, #56] ; (8002c6c <moto_server+0x198>)
8002c34: 685b ldr r3, [r3, #4]
8002c36: 4a0d ldr r2, [pc, #52] ; (8002c6c <moto_server+0x198>)
8002c38: 7b92 ldrb r2, [r2, #14]
8002c3a: 4293 cmp r3, r2
8002c3c: da03 bge.n 8002c46 <moto_server+0x172>
{
dis_buff.moto2a=1;
8002c3e: 4b0c ldr r3, [pc, #48] ; (8002c70 <moto_server+0x19c>)
8002c40: 2201 movs r2, #1
8002c42: 73da strb r2, [r3, #15]
8002c44: e002 b.n 8002c4c <moto_server+0x178>
}else
{
dis_buff.moto2a=0;
8002c46: 4b0a ldr r3, [pc, #40] ; (8002c70 <moto_server+0x19c>)
8002c48: 2200 movs r2, #0
8002c4a: 73da strb r2, [r3, #15]
}
if(moto.pwm_run<moto.moto2b_)
8002c4c: 4b07 ldr r3, [pc, #28] ; (8002c6c <moto_server+0x198>)
8002c4e: 685b ldr r3, [r3, #4]
8002c50: 4a06 ldr r2, [pc, #24] ; (8002c6c <moto_server+0x198>)
8002c52: 7bd2 ldrb r2, [r2, #15]
8002c54: 4293 cmp r3, r2
8002c56: da03 bge.n 8002c60 <moto_server+0x18c>
{
dis_buff.moto2b=1;
8002c58: 4b05 ldr r3, [pc, #20] ; (8002c70 <moto_server+0x19c>)
8002c5a: 2201 movs r2, #1
8002c5c: 741a strb r2, [r3, #16]
}else
{
dis_buff.moto2b=0;
}
}
8002c5e: e002 b.n 8002c66 <moto_server+0x192>
dis_buff.moto2b=0;
8002c60: 4b03 ldr r3, [pc, #12] ; (8002c70 <moto_server+0x19c>)
8002c62: 2200 movs r2, #0
8002c64: 741a strb r2, [r3, #16]
}
8002c66: 46c0 nop ; (mov r8, r8)
8002c68: 46bd mov sp, r7
8002c6a: bd80 pop {r7, pc}
8002c6c: 20000144 .word 0x20000144
8002c70: 20000038 .word 0x20000038
08002c74 <HT1621_Display_GetButton>:
#define E 0x08
#define F 0x04
#define G 0x02
#define H 0x01
void HT1621_Display_GetButton(void)
{
8002c74: b580 push {r7, lr}
8002c76: b084 sub sp, #16
8002c78: af00 add r7, sp, #0
unsigned char send_buff[8];
unsigned char lcd_buff[4];
//WritenDataHT1621(0,send_buff,8);
lcd_buff[0]=LED_Tab[dis_buff.d_num[0]];
8002c7a: 4b45 ldr r3, [pc, #276] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002c7c: 781b ldrb r3, [r3, #0]
8002c7e: 001a movs r2, r3
8002c80: 4b44 ldr r3, [pc, #272] ; (8002d94 <HT1621_Display_GetButton+0x120>)
8002c82: 5c9a ldrb r2, [r3, r2]
8002c84: 1d3b adds r3, r7, #4
8002c86: 701a strb r2, [r3, #0]
if(dis_buff.dot1==1)
8002c88: 4b41 ldr r3, [pc, #260] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002c8a: 7a1b ldrb r3, [r3, #8]
8002c8c: 2b01 cmp r3, #1
8002c8e: d107 bne.n 8002ca0 <HT1621_Display_GetButton+0x2c>
{
lcd_buff[0]|=0x80;
8002c90: 1d3b adds r3, r7, #4
8002c92: 781b ldrb r3, [r3, #0]
8002c94: 2280 movs r2, #128 ; 0x80
8002c96: 4252 negs r2, r2
8002c98: 4313 orrs r3, r2
8002c9a: b2da uxtb r2, r3
8002c9c: 1d3b adds r3, r7, #4
8002c9e: 701a strb r2, [r3, #0]
}
lcd_buff[1]=LED_Tab[dis_buff.d_num[1]];
8002ca0: 4b3b ldr r3, [pc, #236] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002ca2: 785b ldrb r3, [r3, #1]
8002ca4: 001a movs r2, r3
8002ca6: 4b3b ldr r3, [pc, #236] ; (8002d94 <HT1621_Display_GetButton+0x120>)
8002ca8: 5c9a ldrb r2, [r3, r2]
8002caa: 1d3b adds r3, r7, #4
8002cac: 705a strb r2, [r3, #1]
if(dis_buff.dot2==1)
8002cae: 4b38 ldr r3, [pc, #224] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002cb0: 7a5b ldrb r3, [r3, #9]
8002cb2: 2b01 cmp r3, #1
8002cb4: d107 bne.n 8002cc6 <HT1621_Display_GetButton+0x52>
{
lcd_buff[1]|=0x80;
8002cb6: 1d3b adds r3, r7, #4
8002cb8: 785b ldrb r3, [r3, #1]
8002cba: 2280 movs r2, #128 ; 0x80
8002cbc: 4252 negs r2, r2
8002cbe: 4313 orrs r3, r2
8002cc0: b2da uxtb r2, r3
8002cc2: 1d3b adds r3, r7, #4
8002cc4: 705a strb r2, [r3, #1]
}
lcd_buff[2]=LED_Tab[dis_buff.d_num[2]];
8002cc6: 4b32 ldr r3, [pc, #200] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002cc8: 789b ldrb r3, [r3, #2]
8002cca: 001a movs r2, r3
8002ccc: 4b31 ldr r3, [pc, #196] ; (8002d94 <HT1621_Display_GetButton+0x120>)
8002cce: 5c9a ldrb r2, [r3, r2]
8002cd0: 1d3b adds r3, r7, #4
8002cd2: 709a strb r2, [r3, #2]
if(dis_buff.dot3==1)
8002cd4: 4b2e ldr r3, [pc, #184] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002cd6: 7a9b ldrb r3, [r3, #10]
8002cd8: 2b01 cmp r3, #1
8002cda: d107 bne.n 8002cec <HT1621_Display_GetButton+0x78>
{
lcd_buff[2]|=0x80;
8002cdc: 1d3b adds r3, r7, #4
8002cde: 789b ldrb r3, [r3, #2]
8002ce0: 2280 movs r2, #128 ; 0x80
8002ce2: 4252 negs r2, r2
8002ce4: 4313 orrs r3, r2
8002ce6: b2da uxtb r2, r3
8002ce8: 1d3b adds r3, r7, #4
8002cea: 709a strb r2, [r3, #2]
}
lcd_buff[3]=LED_Tab[dis_buff.d_num[3]];
8002cec: 4b28 ldr r3, [pc, #160] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002cee: 78db ldrb r3, [r3, #3]
8002cf0: 001a movs r2, r3
8002cf2: 4b28 ldr r3, [pc, #160] ; (8002d94 <HT1621_Display_GetButton+0x120>)
8002cf4: 5c9a ldrb r2, [r3, r2]
8002cf6: 1d3b adds r3, r7, #4
8002cf8: 70da strb r2, [r3, #3]
if(dis_buff.dot4==1)
8002cfa: 4b25 ldr r3, [pc, #148] ; (8002d90 <HT1621_Display_GetButton+0x11c>)
8002cfc: 7adb ldrb r3, [r3, #11]
8002cfe: 2b01 cmp r3, #1
8002d00: d107 bne.n 8002d12 <HT1621_Display_GetButton+0x9e>
{
lcd_buff[3]|=0x80;
8002d02: 1d3b adds r3, r7, #4
8002d04: 78db ldrb r3, [r3, #3]
8002d06: 2280 movs r2, #128 ; 0x80
8002d08: 4252 negs r2, r2
8002d0a: 4313 orrs r3, r2
8002d0c: b2da uxtb r2, r3
8002d0e: 1d3b adds r3, r7, #4
8002d10: 70da strb r2, [r3, #3]
}
send_buff[0]=lcd_buff[0]>>4;
8002d12: 1d3b adds r3, r7, #4
8002d14: 781b ldrb r3, [r3, #0]
8002d16: 091b lsrs r3, r3, #4
8002d18: b2da uxtb r2, r3
8002d1a: 2108 movs r1, #8
8002d1c: 187b adds r3, r7, r1
8002d1e: 701a strb r2, [r3, #0]
send_buff[1]=lcd_buff[0]&0x0f;
8002d20: 1d3b adds r3, r7, #4
8002d22: 781b ldrb r3, [r3, #0]
8002d24: 220f movs r2, #15
8002d26: 4013 ands r3, r2
8002d28: b2da uxtb r2, r3
8002d2a: 187b adds r3, r7, r1
8002d2c: 705a strb r2, [r3, #1]
send_buff[2]=lcd_buff[1]>>4;
8002d2e: 1d3b adds r3, r7, #4
8002d30: 785b ldrb r3, [r3, #1]
8002d32: 091b lsrs r3, r3, #4
8002d34: b2da uxtb r2, r3
8002d36: 187b adds r3, r7, r1
8002d38: 709a strb r2, [r3, #2]
send_buff[3]=lcd_buff[1]&0x0f;
8002d3a: 1d3b adds r3, r7, #4
8002d3c: 785b ldrb r3, [r3, #1]
8002d3e: 220f movs r2, #15
8002d40: 4013 ands r3, r2
8002d42: b2da uxtb r2, r3
8002d44: 187b adds r3, r7, r1
8002d46: 70da strb r2, [r3, #3]
send_buff[4]=lcd_buff[2]>>4;
8002d48: 1d3b adds r3, r7, #4
8002d4a: 789b ldrb r3, [r3, #2]
8002d4c: 091b lsrs r3, r3, #4
8002d4e: b2da uxtb r2, r3
8002d50: 187b adds r3, r7, r1
8002d52: 711a strb r2, [r3, #4]
send_buff[5]=lcd_buff[2]&0x0f;
8002d54: 1d3b adds r3, r7, #4
8002d56: 789b ldrb r3, [r3, #2]
8002d58: 220f movs r2, #15
8002d5a: 4013 ands r3, r2
8002d5c: b2da uxtb r2, r3
8002d5e: 187b adds r3, r7, r1
8002d60: 715a strb r2, [r3, #5]
send_buff[6]=lcd_buff[3]>>4;
8002d62: 1d3b adds r3, r7, #4
8002d64: 78db ldrb r3, [r3, #3]
8002d66: 091b lsrs r3, r3, #4
8002d68: b2da uxtb r2, r3
8002d6a: 187b adds r3, r7, r1
8002d6c: 719a strb r2, [r3, #6]
send_buff[7]=lcd_buff[3]&0x0f;
8002d6e: 1d3b adds r3, r7, #4
8002d70: 78db ldrb r3, [r3, #3]
8002d72: 220f movs r2, #15
8002d74: 4013 ands r3, r2
8002d76: b2da uxtb r2, r3
8002d78: 187b adds r3, r7, r1
8002d7a: 71da strb r2, [r3, #7]
WritenDataHT1621(0,send_buff,8);
8002d7c: 187b adds r3, r7, r1
8002d7e: 2208 movs r2, #8
8002d80: 0019 movs r1, r3
8002d82: 2000 movs r0, #0
8002d84: f7ff fd04 bl 8002790 <WritenDataHT1621>
}
8002d88: 46c0 nop ; (mov r8, r8)
8002d8a: 46bd mov sp, r7
8002d8c: b004 add sp, #16
8002d8e: bd80 pop {r7, pc}
8002d90: 20000038 .word 0x20000038
8002d94: 0800381c .word 0x0800381c
08002d98 <my_code>:
void my_code()
{
8002d98: b580 push {r7, lr}
8002d9a: b086 sub sp, #24
8002d9c: af00 add r7, sp, #0
uint32_t runtime=0,move=0;
8002d9e: 2300 movs r3, #0
8002da0: 617b str r3, [r7, #20]
8002da2: 2300 movs r3, #0
8002da4: 613b str r3, [r7, #16]
uint8_t mode=0,overload_mode=0;
8002da6: 230f movs r3, #15
8002da8: 18fb adds r3, r7, r3
8002daa: 2200 movs r2, #0
8002dac: 701a strb r2, [r3, #0]
8002dae: 230e movs r3, #14
8002db0: 18fb adds r3, r7, r3
8002db2: 2200 movs r2, #0
8002db4: 701a strb r2, [r3, #0]
uint16_t overload_times=0;
8002db6: 230c movs r3, #12
8002db8: 18fb adds r3, r7, r3
8002dba: 2200 movs r2, #0
8002dbc: 801a strh r2, [r3, #0]
long countdown=1000;
8002dbe: 23fa movs r3, #250 ; 0xfa
8002dc0: 009b lsls r3, r3, #2
8002dc2: 60bb str r3, [r7, #8]
long countdown_set=15000;
8002dc4: 4bdf ldr r3, [pc, #892] ; (8003144 <my_code+0x3ac>)
8002dc6: 607b str r3, [r7, #4]
HT1621_Init();
8002dc8: f7ff fda3 bl 8002912 <HT1621_Init>
r480_init();
8002dcc: f000 fc04 bl 80035d8 <r480_init>
while(1)
{
//get ADC
for(char a=0;a<2;a++)
8002dd0: 1cfb adds r3, r7, #3
8002dd2: 2200 movs r2, #0
8002dd4: 701a strb r2, [r3, #0]
8002dd6: e025 b.n 8002e24 <my_code+0x8c>
{
HAL_ADC_Start(&hadc);
8002dd8: 4bdb ldr r3, [pc, #876] ; (8003148 <my_code+0x3b0>)
8002dda: 0018 movs r0, r3
8002ddc: f7fd ff14 bl 8000c08 <HAL_ADC_Start>
while(HAL_ADC_PollForConversion(&hadc,0xffff)!=HAL_OK);
8002de0: 46c0 nop ; (mov r8, r8)
8002de2: 4ada ldr r2, [pc, #872] ; (800314c <my_code+0x3b4>)
8002de4: 4bd8 ldr r3, [pc, #864] ; (8003148 <my_code+0x3b0>)
8002de6: 0011 movs r1, r2
8002de8: 0018 movs r0, r3
8002dea: f7fd ffa1 bl 8000d30 <HAL_ADC_PollForConversion>
8002dee: 1e03 subs r3, r0, #0
8002df0: d1f7 bne.n 8002de2 <my_code+0x4a>
ADCC.adc_filtering[a]+=HAL_ADC_GetValue(&hadc);
8002df2: 4bd5 ldr r3, [pc, #852] ; (8003148 <my_code+0x3b0>)
8002df4: 0018 movs r0, r3
8002df6: f7fe f833 bl 8000e60 <HAL_ADC_GetValue>
8002dfa: 0001 movs r1, r0
8002dfc: 1cfb adds r3, r7, #3
8002dfe: 781b ldrb r3, [r3, #0]
8002e00: 4ad3 ldr r2, [pc, #844] ; (8003150 <my_code+0x3b8>)
8002e02: 009b lsls r3, r3, #2
8002e04: 18d3 adds r3, r2, r3
8002e06: 3304 adds r3, #4
8002e08: 681a ldr r2, [r3, #0]
8002e0a: 1cfb adds r3, r7, #3
8002e0c: 781b ldrb r3, [r3, #0]
8002e0e: 188a adds r2, r1, r2
8002e10: 49cf ldr r1, [pc, #828] ; (8003150 <my_code+0x3b8>)
8002e12: 009b lsls r3, r3, #2
8002e14: 18cb adds r3, r1, r3
8002e16: 3304 adds r3, #4
8002e18: 601a str r2, [r3, #0]
for(char a=0;a<2;a++)
8002e1a: 1cfb adds r3, r7, #3
8002e1c: 781a ldrb r2, [r3, #0]
8002e1e: 1cfb adds r3, r7, #3
8002e20: 3201 adds r2, #1
8002e22: 701a strb r2, [r3, #0]
8002e24: 1cfb adds r3, r7, #3
8002e26: 781b ldrb r3, [r3, #0]
8002e28: 2b01 cmp r3, #1
8002e2a: d9d5 bls.n 8002dd8 <my_code+0x40>
}
HAL_ADC_Stop(&hadc);
8002e2c: 4bc6 ldr r3, [pc, #792] ; (8003148 <my_code+0x3b0>)
8002e2e: 0018 movs r0, r3
8002e30: f7fd ff3e bl 8000cb0 <HAL_ADC_Stop>
ADCC.filtering_times+=1;
8002e34: 4bc6 ldr r3, [pc, #792] ; (8003150 <my_code+0x3b8>)
8002e36: 681b ldr r3, [r3, #0]
8002e38: 1c5a adds r2, r3, #1
8002e3a: 4bc5 ldr r3, [pc, #788] ; (8003150 <my_code+0x3b8>)
8002e3c: 601a str r2, [r3, #0]
if(ADCC.filtering_times==set_filtering_times)
8002e3e: 4bc4 ldr r3, [pc, #784] ; (8003150 <my_code+0x3b8>)
8002e40: 681b ldr r3, [r3, #0]
8002e42: 2b32 cmp r3, #50 ; 0x32
8002e44: d11c bne.n 8002e80 <my_code+0xe8>
{
ADCC.filtering_times=0;
8002e46: 4bc2 ldr r3, [pc, #776] ; (8003150 <my_code+0x3b8>)
8002e48: 2200 movs r2, #0
8002e4a: 601a str r2, [r3, #0]
ADCC.adc_value[0]=ADCC.adc_filtering[0]/set_filtering_times;
8002e4c: 4bc0 ldr r3, [pc, #768] ; (8003150 <my_code+0x3b8>)
8002e4e: 685b ldr r3, [r3, #4]
8002e50: 2132 movs r1, #50 ; 0x32
8002e52: 0018 movs r0, r3
8002e54: f7fd f958 bl 8000108 <__udivsi3>
8002e58: 0003 movs r3, r0
8002e5a: 001a movs r2, r3
8002e5c: 4bbc ldr r3, [pc, #752] ; (8003150 <my_code+0x3b8>)
8002e5e: 60da str r2, [r3, #12]
ADCC.adc_filtering[0]=0;
8002e60: 4bbb ldr r3, [pc, #748] ; (8003150 <my_code+0x3b8>)
8002e62: 2200 movs r2, #0
8002e64: 605a str r2, [r3, #4]
ADCC.adc_value[1]=ADCC.adc_filtering[1]/set_filtering_times;
8002e66: 4bba ldr r3, [pc, #744] ; (8003150 <my_code+0x3b8>)
8002e68: 689b ldr r3, [r3, #8]
8002e6a: 2132 movs r1, #50 ; 0x32
8002e6c: 0018 movs r0, r3
8002e6e: f7fd f94b bl 8000108 <__udivsi3>
8002e72: 0003 movs r3, r0
8002e74: 001a movs r2, r3
8002e76: 4bb6 ldr r3, [pc, #728] ; (8003150 <my_code+0x3b8>)
8002e78: 611a str r2, [r3, #16]
ADCC.adc_filtering[1]=0;
8002e7a: 4bb5 ldr r3, [pc, #724] ; (8003150 <my_code+0x3b8>)
8002e7c: 2200 movs r2, #0
8002e7e: 609a str r2, [r3, #8]
}
switch(mode)
8002e80: 230f movs r3, #15
8002e82: 18fb adds r3, r7, r3
8002e84: 781b ldrb r3, [r3, #0]
8002e86: 2b05 cmp r3, #5
8002e88: d900 bls.n 8002e8c <my_code+0xf4>
8002e8a: e31a b.n 80034c2 <my_code+0x72a>
8002e8c: 009a lsls r2, r3, #2
8002e8e: 4bb1 ldr r3, [pc, #708] ; (8003154 <my_code+0x3bc>)
8002e90: 18d3 adds r3, r2, r3
8002e92: 681b ldr r3, [r3, #0]
8002e94: 469f mov pc, r3
{
case 0:
//Startup
if(HAL_GetTick()>move)
8002e96: f7fd fd6d bl 8000974 <HAL_GetTick>
8002e9a: 0002 movs r2, r0
8002e9c: 693b ldr r3, [r7, #16]
8002e9e: 4293 cmp r3, r2
8002ea0: d300 bcc.n 8002ea4 <my_code+0x10c>
8002ea2: e305 b.n 80034b0 <my_code+0x718>
{
move=HAL_GetTick()+100;
8002ea4: f7fd fd66 bl 8000974 <HAL_GetTick>
8002ea8: 0003 movs r3, r0
8002eaa: 3364 adds r3, #100 ; 0x64
8002eac: 613b str r3, [r7, #16]
countdown-=100;
8002eae: 68bb ldr r3, [r7, #8]
8002eb0: 3b64 subs r3, #100 ; 0x64
8002eb2: 60bb str r3, [r7, #8]
if(countdown<0)
8002eb4: 68bb ldr r3, [r7, #8]
8002eb6: 2b00 cmp r3, #0
8002eb8: da03 bge.n 8002ec2 <my_code+0x12a>
{
mode=1;
8002eba: 230f movs r3, #15
8002ebc: 18fb adds r3, r7, r3
8002ebe: 2201 movs r2, #1
8002ec0: 701a strb r2, [r3, #0]
}
dis_buff.d_num[0]=((countdown/100)%10);
8002ec2: 68bb ldr r3, [r7, #8]
8002ec4: 2164 movs r1, #100 ; 0x64
8002ec6: 0018 movs r0, r3
8002ec8: f7fd f9a8 bl 800021c <__divsi3>
8002ecc: 0003 movs r3, r0
8002ece: 210a movs r1, #10
8002ed0: 0018 movs r0, r3
8002ed2: f7fd fa89 bl 80003e8 <__aeabi_idivmod>
8002ed6: 000b movs r3, r1
8002ed8: b2da uxtb r2, r3
8002eda: 4b9f ldr r3, [pc, #636] ; (8003158 <my_code+0x3c0>)
8002edc: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=((countdown/100)%10);
8002ede: 68bb ldr r3, [r7, #8]
8002ee0: 2164 movs r1, #100 ; 0x64
8002ee2: 0018 movs r0, r3
8002ee4: f7fd f99a bl 800021c <__divsi3>
8002ee8: 0003 movs r3, r0
8002eea: 210a movs r1, #10
8002eec: 0018 movs r0, r3
8002eee: f7fd fa7b bl 80003e8 <__aeabi_idivmod>
8002ef2: 000b movs r3, r1
8002ef4: b2da uxtb r2, r3
8002ef6: 4b98 ldr r3, [pc, #608] ; (8003158 <my_code+0x3c0>)
8002ef8: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=((countdown/100)%10);
8002efa: 68bb ldr r3, [r7, #8]
8002efc: 2164 movs r1, #100 ; 0x64
8002efe: 0018 movs r0, r3
8002f00: f7fd f98c bl 800021c <__divsi3>
8002f04: 0003 movs r3, r0
8002f06: 210a movs r1, #10
8002f08: 0018 movs r0, r3
8002f0a: f7fd fa6d bl 80003e8 <__aeabi_idivmod>
8002f0e: 000b movs r3, r1
8002f10: b2da uxtb r2, r3
8002f12: 4b91 ldr r3, [pc, #580] ; (8003158 <my_code+0x3c0>)
8002f14: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=((countdown/100)%10);
8002f16: 68bb ldr r3, [r7, #8]
8002f18: 2164 movs r1, #100 ; 0x64
8002f1a: 0018 movs r0, r3
8002f1c: f7fd f97e bl 800021c <__divsi3>
8002f20: 0003 movs r3, r0
8002f22: 210a movs r1, #10
8002f24: 0018 movs r0, r3
8002f26: f7fd fa5f bl 80003e8 <__aeabi_idivmod>
8002f2a: 000b movs r3, r1
8002f2c: b2da uxtb r2, r3
8002f2e: 4b8a ldr r3, [pc, #552] ; (8003158 <my_code+0x3c0>)
8002f30: 70da strb r2, [r3, #3]
dis_buff.dot1=countdown>>3;
8002f32: 68bb ldr r3, [r7, #8]
8002f34: 10db asrs r3, r3, #3
8002f36: b2da uxtb r2, r3
8002f38: 4b87 ldr r3, [pc, #540] ; (8003158 <my_code+0x3c0>)
8002f3a: 721a strb r2, [r3, #8]
dis_buff.dot2=countdown>>4;
8002f3c: 68bb ldr r3, [r7, #8]
8002f3e: 111b asrs r3, r3, #4
8002f40: b2da uxtb r2, r3
8002f42: 4b85 ldr r3, [pc, #532] ; (8003158 <my_code+0x3c0>)
8002f44: 725a strb r2, [r3, #9]
dis_buff.dot3=countdown>>5;
8002f46: 68bb ldr r3, [r7, #8]
8002f48: 115b asrs r3, r3, #5
8002f4a: b2da uxtb r2, r3
8002f4c: 4b82 ldr r3, [pc, #520] ; (8003158 <my_code+0x3c0>)
8002f4e: 729a strb r2, [r3, #10]
dis_buff.dot4=countdown>>6;
8002f50: 68bb ldr r3, [r7, #8]
8002f52: 119b asrs r3, r3, #6
8002f54: b2da uxtb r2, r3
8002f56: 4b80 ldr r3, [pc, #512] ; (8003158 <my_code+0x3c0>)
8002f58: 72da strb r2, [r3, #11]
}
break;
8002f5a: e2a9 b.n 80034b0 <my_code+0x718>
case 1:
//standby
moto.moto1a=0;
8002f5c: 4b7f ldr r3, [pc, #508] ; (800315c <my_code+0x3c4>)
8002f5e: 2200 movs r2, #0
8002f60: 721a strb r2, [r3, #8]
moto.moto1b=0;
8002f62: 4b7e ldr r3, [pc, #504] ; (800315c <my_code+0x3c4>)
8002f64: 2200 movs r2, #0
8002f66: 725a strb r2, [r3, #9]
moto.moto2a=0;
8002f68: 4b7c ldr r3, [pc, #496] ; (800315c <my_code+0x3c4>)
8002f6a: 2200 movs r2, #0
8002f6c: 729a strb r2, [r3, #10]
moto.moto2b=0;
8002f6e: 4b7b ldr r3, [pc, #492] ; (800315c <my_code+0x3c4>)
8002f70: 2200 movs r2, #0
8002f72: 72da strb r2, [r3, #11]
dis_buff.d_num[0]=16;
8002f74: 4b78 ldr r3, [pc, #480] ; (8003158 <my_code+0x3c0>)
8002f76: 2210 movs r2, #16
8002f78: 701a strb r2, [r3, #0]
dis_buff.d_num[1]=16;
8002f7a: 4b77 ldr r3, [pc, #476] ; (8003158 <my_code+0x3c0>)
8002f7c: 2210 movs r2, #16
8002f7e: 705a strb r2, [r3, #1]
dis_buff.d_num[2]=16;
8002f80: 4b75 ldr r3, [pc, #468] ; (8003158 <my_code+0x3c0>)
8002f82: 2210 movs r2, #16
8002f84: 709a strb r2, [r3, #2]
dis_buff.d_num[3]=16;
8002f86: 4b74 ldr r3, [pc, #464] ; (8003158 <my_code+0x3c0>)
8002f88: 2210 movs r2, #16
8002f8a: 70da strb r2, [r3, #3]
dis_buff.dot1=0;
8002f8c: 4b72 ldr r3, [pc, #456] ; (8003158 <my_code+0x3c0>)
8002f8e: 2200 movs r2, #0
8002f90: 721a strb r2, [r3, #8]
dis_buff.dot2=0;
8002f92: 4b71 ldr r3, [pc, #452] ; (8003158 <my_code+0x3c0>)
8002f94: 2200 movs r2, #0
8002f96: 725a strb r2, [r3, #9]
dis_buff.dot3=0;
8002f98: 4b6f ldr r3, [pc, #444] ; (8003158 <my_code+0x3c0>)
8002f9a: 2200 movs r2, #0
8002f9c: 729a strb r2, [r3, #10]
if(HAL_GetTick()>runtime)
8002f9e: f7fd fce9 bl 8000974 <HAL_GetTick>
8002fa2: 0002 movs r2, r0
8002fa4: 697b ldr r3, [r7, #20]
8002fa6: 4293 cmp r3, r2
8002fa8: d216 bcs.n 8002fd8 <my_code+0x240>
{
runtime+=1000;
8002faa: 697b ldr r3, [r7, #20]
8002fac: 22fa movs r2, #250 ; 0xfa
8002fae: 0092 lsls r2, r2, #2
8002fb0: 4694 mov ip, r2
8002fb2: 4463 add r3, ip
8002fb4: 617b str r3, [r7, #20]
if(dis_buff.led_run==1)
8002fb6: 4b68 ldr r3, [pc, #416] ; (8003158 <my_code+0x3c0>)
8002fb8: 7b1b ldrb r3, [r3, #12]
8002fba: 2b01 cmp r3, #1
8002fbc: d106 bne.n 8002fcc <my_code+0x234>
{
dis_buff.led_run=0;
8002fbe: 4b66 ldr r3, [pc, #408] ; (8003158 <my_code+0x3c0>)
8002fc0: 2200 movs r2, #0
8002fc2: 731a strb r2, [r3, #12]
dis_buff.dot4=1;
8002fc4: 4b64 ldr r3, [pc, #400] ; (8003158 <my_code+0x3c0>)
8002fc6: 2201 movs r2, #1
8002fc8: 72da strb r2, [r3, #11]
8002fca: e005 b.n 8002fd8 <my_code+0x240>
}else
{
dis_buff.led_run=1;
8002fcc: 4b62 ldr r3, [pc, #392] ; (8003158 <my_code+0x3c0>)
8002fce: 2201 movs r2, #1
8002fd0: 731a strb r2, [r3, #12]
dis_buff.dot4=0;
8002fd2: 4b61 ldr r3, [pc, #388] ; (8003158 <my_code+0x3c0>)
8002fd4: 2200 movs r2, #0
8002fd6: 72da strb r2, [r3, #11]
}
}
overload_times=0;
8002fd8: 230c movs r3, #12
8002fda: 18fb adds r3, r7, r3
8002fdc: 2200 movs r2, #0
8002fde: 801a strh r2, [r3, #0]
if(key2.code!=0)
8002fe0: 4b5f ldr r3, [pc, #380] ; (8003160 <my_code+0x3c8>)
8002fe2: 681b ldr r3, [r3, #0]
8002fe4: 2b00 cmp r3, #0
8002fe6: d005 beq.n 8002ff4 <my_code+0x25c>
{
mode=2;
8002fe8: 230f movs r3, #15
8002fea: 18fb adds r3, r7, r3
8002fec: 2202 movs r2, #2
8002fee: 701a strb r2, [r3, #0]
countdown=countdown_set;
8002ff0: 687b ldr r3, [r7, #4]
8002ff2: 60bb str r3, [r7, #8]
}
if(key3.code!=0)
8002ff4: 4b5b ldr r3, [pc, #364] ; (8003164 <my_code+0x3cc>)
8002ff6: 681b ldr r3, [r3, #0]
8002ff8: 2b00 cmp r3, #0
8002ffa: d005 beq.n 8003008 <my_code+0x270>
{
mode=3;
8002ffc: 230f movs r3, #15
8002ffe: 18fb adds r3, r7, r3
8003000: 2203 movs r2, #3
8003002: 701a strb r2, [r3, #0]
countdown=countdown_set;
8003004: 687b ldr r3, [r7, #4]
8003006: 60bb str r3, [r7, #8]
}
if(key1.code!=0)
8003008: 4b57 ldr r3, [pc, #348] ; (8003168 <my_code+0x3d0>)
800300a: 681b ldr r3, [r3, #0]
800300c: 2b00 cmp r3, #0
800300e: d100 bne.n 8003012 <my_code+0x27a>
8003010: e250 b.n 80034b4 <my_code+0x71c>
{
mode=4;
8003012: 230f movs r3, #15
8003014: 18fb adds r3, r7, r3
8003016: 2204 movs r2, #4
8003018: 701a strb r2, [r3, #0]
countdown=10000;
800301a: 4b54 ldr r3, [pc, #336] ; (800316c <my_code+0x3d4>)
800301c: 60bb str r3, [r7, #8]
}
break;
800301e: e249 b.n 80034b4 <my_code+0x71c>
case 2:
moto.moto1a=10;
8003020: 4b4e ldr r3, [pc, #312] ; (800315c <my_code+0x3c4>)
8003022: 220a movs r2, #10
8003024: 721a strb r2, [r3, #8]
moto.moto1b=0;
8003026: 4b4d ldr r3, [pc, #308] ; (800315c <my_code+0x3c4>)
8003028: 2200 movs r2, #0
800302a: 725a strb r2, [r3, #9]
moto.moto2a=10;
800302c: 4b4b ldr r3, [pc, #300] ; (800315c <my_code+0x3c4>)
800302e: 220a movs r2, #10
8003030: 729a strb r2, [r3, #10]
moto.moto2b=0;
8003032: 4b4a ldr r3, [pc, #296] ; (800315c <my_code+0x3c4>)
8003034: 2200 movs r2, #0
8003036: 72da strb r2, [r3, #11]
if(HAL_GetTick()>move)
8003038: f7fd fc9c bl 8000974 <HAL_GetTick>
800303c: 0002 movs r2, r0
800303e: 693b ldr r3, [r7, #16]
8003040: 4293 cmp r3, r2
8003042: d219 bcs.n 8003078 <my_code+0x2e0>
{
move=HAL_GetTick()+100;
8003044: f7fd fc96 bl 8000974 <HAL_GetTick>
8003048: 0003 movs r3, r0
800304a: 3364 adds r3, #100 ; 0x64
800304c: 613b str r3, [r7, #16]
if(dis_buff.led_run==1)
800304e: 4b42 ldr r3, [pc, #264] ; (8003158 <my_code+0x3c0>)
8003050: 7b1b ldrb r3, [r3, #12]
8003052: 2b01 cmp r3, #1
8003054: d103 bne.n 800305e <my_code+0x2c6>
{
dis_buff.led_run=0;
8003056: 4b40 ldr r3, [pc, #256] ; (8003158 <my_code+0x3c0>)
8003058: 2200 movs r2, #0
800305a: 731a strb r2, [r3, #12]
800305c: e002 b.n 8003064 <my_code+0x2cc>
}else
{
dis_buff.led_run=1;
800305e: 4b3e ldr r3, [pc, #248] ; (8003158 <my_code+0x3c0>)
8003060: 2201 movs r2, #1
8003062: 731a strb r2, [r3, #12]
}
countdown-=100;
8003064: 68bb ldr r3, [r7, #8]
8003066: 3b64 subs r3, #100 ; 0x64
8003068: 60bb str r3, [r7, #8]
if(countdown<0)
800306a: 68bb ldr r3, [r7, #8]
800306c: 2b00 cmp r3, #0
800306e: da03 bge.n 8003078 <my_code+0x2e0>
{
mode=1;
8003070: 230f movs r3, #15
8003072: 18fb adds r3, r7, r3
8003074: 2201 movs r2, #1
8003076: 701a strb r2, [r3, #0]
}
}
dis_buff.d_num[3]=(countdown/100)%10;
8003078: 68bb ldr r3, [r7, #8]
800307a: 2164 movs r1, #100 ; 0x64
800307c: 0018 movs r0, r3
800307e: f7fd f8cd bl 800021c <__divsi3>
8003082: 0003 movs r3, r0
8003084: 210a movs r1, #10
8003086: 0018 movs r0, r3
8003088: f7fd f9ae bl 80003e8 <__aeabi_idivmod>
800308c: 000b movs r3, r1
800308e: b2da uxtb r2, r3
8003090: 4b31 ldr r3, [pc, #196] ; (8003158 <my_code+0x3c0>)
8003092: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown/1000)%10;
8003094: 68bb ldr r3, [r7, #8]
8003096: 22fa movs r2, #250 ; 0xfa
8003098: 0091 lsls r1, r2, #2
800309a: 0018 movs r0, r3
800309c: f7fd f8be bl 800021c <__divsi3>
80030a0: 0003 movs r3, r0
80030a2: 210a movs r1, #10
80030a4: 0018 movs r0, r3
80030a6: f7fd f99f bl 80003e8 <__aeabi_idivmod>
80030aa: 000b movs r3, r1
80030ac: b2da uxtb r2, r3
80030ae: 4b2a ldr r3, [pc, #168] ; (8003158 <my_code+0x3c0>)
80030b0: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown/10000)%10);
80030b2: 68bb ldr r3, [r7, #8]
80030b4: 492d ldr r1, [pc, #180] ; (800316c <my_code+0x3d4>)
80030b6: 0018 movs r0, r3
80030b8: f7fd f8b0 bl 800021c <__divsi3>
80030bc: 0003 movs r3, r0
80030be: 210a movs r1, #10
80030c0: 0018 movs r0, r3
80030c2: f7fd f991 bl 80003e8 <__aeabi_idivmod>
80030c6: 000b movs r3, r1
80030c8: b2da uxtb r2, r3
80030ca: 4b23 ldr r3, [pc, #140] ; (8003158 <my_code+0x3c0>)
80030cc: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1];
80030ce: 4b22 ldr r3, [pc, #136] ; (8003158 <my_code+0x3c0>)
80030d0: 785b ldrb r3, [r3, #1]
80030d2: 2b00 cmp r3, #0
80030d4: d002 beq.n 80030dc <my_code+0x344>
80030d6: 4b20 ldr r3, [pc, #128] ; (8003158 <my_code+0x3c0>)
80030d8: 785a ldrb r2, [r3, #1]
80030da: e000 b.n 80030de <my_code+0x346>
80030dc: 2210 movs r2, #16
80030de: 4b1e ldr r3, [pc, #120] ; (8003158 <my_code+0x3c0>)
80030e0: 705a strb r2, [r3, #1]
dis_buff.dot4=1;
80030e2: 4b1d ldr r3, [pc, #116] ; (8003158 <my_code+0x3c0>)
80030e4: 2201 movs r2, #1
80030e6: 72da strb r2, [r3, #11]
if(key3.code!=0)
80030e8: 4b1e ldr r3, [pc, #120] ; (8003164 <my_code+0x3cc>)
80030ea: 681b ldr r3, [r3, #0]
80030ec: 2b00 cmp r3, #0
80030ee: d007 beq.n 8003100 <my_code+0x368>
{
mode=3;
80030f0: 230f movs r3, #15
80030f2: 18fb adds r3, r7, r3
80030f4: 2203 movs r2, #3
80030f6: 701a strb r2, [r3, #0]
countdown=countdown_set-countdown;
80030f8: 687a ldr r2, [r7, #4]
80030fa: 68bb ldr r3, [r7, #8]
80030fc: 1ad3 subs r3, r2, r3
80030fe: 60bb str r3, [r7, #8]
}
if(key4.code!=0)
8003100: 4b1b ldr r3, [pc, #108] ; (8003170 <my_code+0x3d8>)
8003102: 681b ldr r3, [r3, #0]
8003104: 2b00 cmp r3, #0
8003106: d003 beq.n 8003110 <my_code+0x378>
{
mode=1;
8003108: 230f movs r3, #15
800310a: 18fb adds r3, r7, r3
800310c: 2201 movs r2, #1
800310e: 701a strb r2, [r3, #0]
}
if(overload.code!=0)
8003110: 4b18 ldr r3, [pc, #96] ; (8003174 <my_code+0x3dc>)
8003112: 681b ldr r3, [r3, #0]
8003114: 2b00 cmp r3, #0
8003116: d005 beq.n 8003124 <my_code+0x38c>
{
overload_times+=1;
8003118: 220c movs r2, #12
800311a: 18bb adds r3, r7, r2
800311c: 18ba adds r2, r7, r2
800311e: 8812 ldrh r2, [r2, #0]
8003120: 3201 adds r2, #1
8003122: 801a strh r2, [r3, #0]
}
if(overload_times>2)
8003124: 230c movs r3, #12
8003126: 18fb adds r3, r7, r3
8003128: 881b ldrh r3, [r3, #0]
800312a: 2b02 cmp r3, #2
800312c: d800 bhi.n 8003130 <my_code+0x398>
800312e: e1c3 b.n 80034b8 <my_code+0x720>
{
overload_mode=2;
8003130: 230e movs r3, #14
8003132: 18fb adds r3, r7, r3
8003134: 2202 movs r2, #2
8003136: 701a strb r2, [r3, #0]
mode=5;
8003138: 230f movs r3, #15
800313a: 18fb adds r3, r7, r3
800313c: 2205 movs r2, #5
800313e: 701a strb r2, [r3, #0]
}
break;
8003140: e1ba b.n 80034b8 <my_code+0x720>
8003142: 46c0 nop ; (mov r8, r8)
8003144: 00003a98 .word 0x00003a98
8003148: 20000094 .word 0x20000094
800314c: 0000ffff .word 0x0000ffff
8003150: 20000120 .word 0x20000120
8003154: 08003830 .word 0x08003830
8003158: 20000038 .word 0x20000038
800315c: 20000144 .word 0x20000144
8003160: 20000134 .word 0x20000134
8003164: 20000110 .word 0x20000110
8003168: 200000f0 .word 0x200000f0
800316c: 00002710 .word 0x00002710
8003170: 200000d8 .word 0x200000d8
8003174: 20000100 .word 0x20000100
case 3:
moto.moto1a=0;
8003178: 4bdb ldr r3, [pc, #876] ; (80034e8 <my_code+0x750>)
800317a: 2200 movs r2, #0
800317c: 721a strb r2, [r3, #8]
moto.moto1b=10;
800317e: 4bda ldr r3, [pc, #872] ; (80034e8 <my_code+0x750>)
8003180: 220a movs r2, #10
8003182: 725a strb r2, [r3, #9]
moto.moto2a=0;
8003184: 4bd8 ldr r3, [pc, #864] ; (80034e8 <my_code+0x750>)
8003186: 2200 movs r2, #0
8003188: 729a strb r2, [r3, #10]
moto.moto2b=10;
800318a: 4bd7 ldr r3, [pc, #860] ; (80034e8 <my_code+0x750>)
800318c: 220a movs r2, #10
800318e: 72da strb r2, [r3, #11]
if(HAL_GetTick()>move)
8003190: f7fd fbf0 bl 8000974 <HAL_GetTick>
8003194: 0002 movs r2, r0
8003196: 693b ldr r3, [r7, #16]
8003198: 4293 cmp r3, r2
800319a: d219 bcs.n 80031d0 <my_code+0x438>
{
move=HAL_GetTick()+100;
800319c: f7fd fbea bl 8000974 <HAL_GetTick>
80031a0: 0003 movs r3, r0
80031a2: 3364 adds r3, #100 ; 0x64
80031a4: 613b str r3, [r7, #16]
if(dis_buff.led_run==1)
80031a6: 4bd1 ldr r3, [pc, #836] ; (80034ec <my_code+0x754>)
80031a8: 7b1b ldrb r3, [r3, #12]
80031aa: 2b01 cmp r3, #1
80031ac: d103 bne.n 80031b6 <my_code+0x41e>
{
dis_buff.led_run=0;
80031ae: 4bcf ldr r3, [pc, #828] ; (80034ec <my_code+0x754>)
80031b0: 2200 movs r2, #0
80031b2: 731a strb r2, [r3, #12]
80031b4: e002 b.n 80031bc <my_code+0x424>
}else
{
dis_buff.led_run=1;
80031b6: 4bcd ldr r3, [pc, #820] ; (80034ec <my_code+0x754>)
80031b8: 2201 movs r2, #1
80031ba: 731a strb r2, [r3, #12]
}
countdown-=100;
80031bc: 68bb ldr r3, [r7, #8]
80031be: 3b64 subs r3, #100 ; 0x64
80031c0: 60bb str r3, [r7, #8]
if(countdown<0)
80031c2: 68bb ldr r3, [r7, #8]
80031c4: 2b00 cmp r3, #0
80031c6: da03 bge.n 80031d0 <my_code+0x438>
{
mode=1;
80031c8: 230f movs r3, #15
80031ca: 18fb adds r3, r7, r3
80031cc: 2201 movs r2, #1
80031ce: 701a strb r2, [r3, #0]
}
}
dis_buff.d_num[3]=(countdown/100)%10;
80031d0: 68bb ldr r3, [r7, #8]
80031d2: 2164 movs r1, #100 ; 0x64
80031d4: 0018 movs r0, r3
80031d6: f7fd f821 bl 800021c <__divsi3>
80031da: 0003 movs r3, r0
80031dc: 210a movs r1, #10
80031de: 0018 movs r0, r3
80031e0: f7fd f902 bl 80003e8 <__aeabi_idivmod>
80031e4: 000b movs r3, r1
80031e6: b2da uxtb r2, r3
80031e8: 4bc0 ldr r3, [pc, #768] ; (80034ec <my_code+0x754>)
80031ea: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown/1000)%10;
80031ec: 68bb ldr r3, [r7, #8]
80031ee: 22fa movs r2, #250 ; 0xfa
80031f0: 0091 lsls r1, r2, #2
80031f2: 0018 movs r0, r3
80031f4: f7fd f812 bl 800021c <__divsi3>
80031f8: 0003 movs r3, r0
80031fa: 210a movs r1, #10
80031fc: 0018 movs r0, r3
80031fe: f7fd f8f3 bl 80003e8 <__aeabi_idivmod>
8003202: 000b movs r3, r1
8003204: b2da uxtb r2, r3
8003206: 4bb9 ldr r3, [pc, #740] ; (80034ec <my_code+0x754>)
8003208: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown/10000)%10);
800320a: 68bb ldr r3, [r7, #8]
800320c: 49b8 ldr r1, [pc, #736] ; (80034f0 <my_code+0x758>)
800320e: 0018 movs r0, r3
8003210: f7fd f804 bl 800021c <__divsi3>
8003214: 0003 movs r3, r0
8003216: 210a movs r1, #10
8003218: 0018 movs r0, r3
800321a: f7fd f8e5 bl 80003e8 <__aeabi_idivmod>
800321e: 000b movs r3, r1
8003220: b2da uxtb r2, r3
8003222: 4bb2 ldr r3, [pc, #712] ; (80034ec <my_code+0x754>)
8003224: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1];
8003226: 4bb1 ldr r3, [pc, #708] ; (80034ec <my_code+0x754>)
8003228: 785b ldrb r3, [r3, #1]
800322a: 2b00 cmp r3, #0
800322c: d002 beq.n 8003234 <my_code+0x49c>
800322e: 4baf ldr r3, [pc, #700] ; (80034ec <my_code+0x754>)
8003230: 785a ldrb r2, [r3, #1]
8003232: e000 b.n 8003236 <my_code+0x49e>
8003234: 2210 movs r2, #16
8003236: 4bad ldr r3, [pc, #692] ; (80034ec <my_code+0x754>)
8003238: 705a strb r2, [r3, #1]
dis_buff.dot4=1;
800323a: 4bac ldr r3, [pc, #688] ; (80034ec <my_code+0x754>)
800323c: 2201 movs r2, #1
800323e: 72da strb r2, [r3, #11]
if(key2.code!=0)
8003240: 4bac ldr r3, [pc, #688] ; (80034f4 <my_code+0x75c>)
8003242: 681b ldr r3, [r3, #0]
8003244: 2b00 cmp r3, #0
8003246: d007 beq.n 8003258 <my_code+0x4c0>
{
mode=2;
8003248: 230f movs r3, #15
800324a: 18fb adds r3, r7, r3
800324c: 2202 movs r2, #2
800324e: 701a strb r2, [r3, #0]
countdown=countdown_set-countdown;
8003250: 687a ldr r2, [r7, #4]
8003252: 68bb ldr r3, [r7, #8]
8003254: 1ad3 subs r3, r2, r3
8003256: 60bb str r3, [r7, #8]
}
if(key4.code!=0)
8003258: 4ba7 ldr r3, [pc, #668] ; (80034f8 <my_code+0x760>)
800325a: 681b ldr r3, [r3, #0]
800325c: 2b00 cmp r3, #0
800325e: d003 beq.n 8003268 <my_code+0x4d0>
{
mode=1;
8003260: 230f movs r3, #15
8003262: 18fb adds r3, r7, r3
8003264: 2201 movs r2, #1
8003266: 701a strb r2, [r3, #0]
}
if(overload.code!=0)
8003268: 4ba4 ldr r3, [pc, #656] ; (80034fc <my_code+0x764>)
800326a: 681b ldr r3, [r3, #0]
800326c: 2b00 cmp r3, #0
800326e: d005 beq.n 800327c <my_code+0x4e4>
{
overload_times+=1;
8003270: 220c movs r2, #12
8003272: 18bb adds r3, r7, r2
8003274: 18ba adds r2, r7, r2
8003276: 8812 ldrh r2, [r2, #0]
8003278: 3201 adds r2, #1
800327a: 801a strh r2, [r3, #0]
}
if(overload_times>2)
800327c: 230c movs r3, #12
800327e: 18fb adds r3, r7, r3
8003280: 881b ldrh r3, [r3, #0]
8003282: 2b02 cmp r3, #2
8003284: d800 bhi.n 8003288 <my_code+0x4f0>
8003286: e119 b.n 80034bc <my_code+0x724>
{
overload_mode=3;
8003288: 230e movs r3, #14
800328a: 18fb adds r3, r7, r3
800328c: 2203 movs r2, #3
800328e: 701a strb r2, [r3, #0]
mode=5;
8003290: 230f movs r3, #15
8003292: 18fb adds r3, r7, r3
8003294: 2205 movs r2, #5
8003296: 701a strb r2, [r3, #0]
}
break;
8003298: e110 b.n 80034bc <my_code+0x724>
case 4:
//setting mode
dis_buff.led_run=0;
800329a: 4b94 ldr r3, [pc, #592] ; (80034ec <my_code+0x754>)
800329c: 2200 movs r2, #0
800329e: 731a strb r2, [r3, #12]
if(HAL_GetTick()>move)
80032a0: f7fd fb68 bl 8000974 <HAL_GetTick>
80032a4: 0002 movs r2, r0
80032a6: 693b ldr r3, [r7, #16]
80032a8: 4293 cmp r3, r2
80032aa: d230 bcs.n 800330e <my_code+0x576>
{
move=HAL_GetTick()+100;
80032ac: f7fd fb62 bl 8000974 <HAL_GetTick>
80032b0: 0003 movs r3, r0
80032b2: 3364 adds r3, #100 ; 0x64
80032b4: 613b str r3, [r7, #16]
if(dis_buff.dot4==1)
80032b6: 4b8d ldr r3, [pc, #564] ; (80034ec <my_code+0x754>)
80032b8: 7adb ldrb r3, [r3, #11]
80032ba: 2b01 cmp r3, #1
80032bc: d103 bne.n 80032c6 <my_code+0x52e>
{
dis_buff.dot4=0;
80032be: 4b8b ldr r3, [pc, #556] ; (80034ec <my_code+0x754>)
80032c0: 2200 movs r2, #0
80032c2: 72da strb r2, [r3, #11]
80032c4: e002 b.n 80032cc <my_code+0x534>
}else
{
dis_buff.dot4=1;
80032c6: 4b89 ldr r3, [pc, #548] ; (80034ec <my_code+0x754>)
80032c8: 2201 movs r2, #1
80032ca: 72da strb r2, [r3, #11]
}
countdown-=100;
80032cc: 68bb ldr r3, [r7, #8]
80032ce: 3b64 subs r3, #100 ; 0x64
80032d0: 60bb str r3, [r7, #8]
if(countdown<0)
80032d2: 68bb ldr r3, [r7, #8]
80032d4: 2b00 cmp r3, #0
80032d6: da03 bge.n 80032e0 <my_code+0x548>
{
mode=1;
80032d8: 230f movs r3, #15
80032da: 18fb adds r3, r7, r3
80032dc: 2201 movs r2, #1
80032de: 701a strb r2, [r3, #0]
}
if(key2.code<0){countdown_set+=1000;countdown=10000;}
80032e0: 4b84 ldr r3, [pc, #528] ; (80034f4 <my_code+0x75c>)
80032e2: 681b ldr r3, [r3, #0]
80032e4: 2b00 cmp r3, #0
80032e6: da07 bge.n 80032f8 <my_code+0x560>
80032e8: 687b ldr r3, [r7, #4]
80032ea: 22fa movs r2, #250 ; 0xfa
80032ec: 0092 lsls r2, r2, #2
80032ee: 4694 mov ip, r2
80032f0: 4463 add r3, ip
80032f2: 607b str r3, [r7, #4]
80032f4: 4b7e ldr r3, [pc, #504] ; (80034f0 <my_code+0x758>)
80032f6: 60bb str r3, [r7, #8]
if(key3.code<0){countdown_set-=1000;countdown=10000;}
80032f8: 4b81 ldr r3, [pc, #516] ; (8003500 <my_code+0x768>)
80032fa: 681b ldr r3, [r3, #0]
80032fc: 2b00 cmp r3, #0
80032fe: da06 bge.n 800330e <my_code+0x576>
8003300: 687b ldr r3, [r7, #4]
8003302: 4a80 ldr r2, [pc, #512] ; (8003504 <my_code+0x76c>)
8003304: 4694 mov ip, r2
8003306: 4463 add r3, ip
8003308: 607b str r3, [r7, #4]
800330a: 4b79 ldr r3, [pc, #484] ; (80034f0 <my_code+0x758>)
800330c: 60bb str r3, [r7, #8]
}
if(key2.code>0){countdown_set+=100;countdown=10000;}
800330e: 4b79 ldr r3, [pc, #484] ; (80034f4 <my_code+0x75c>)
8003310: 681b ldr r3, [r3, #0]
8003312: 2b00 cmp r3, #0
8003314: dd04 ble.n 8003320 <my_code+0x588>
8003316: 687b ldr r3, [r7, #4]
8003318: 3364 adds r3, #100 ; 0x64
800331a: 607b str r3, [r7, #4]
800331c: 4b74 ldr r3, [pc, #464] ; (80034f0 <my_code+0x758>)
800331e: 60bb str r3, [r7, #8]
if(key3.code>0){countdown_set-=100;countdown=10000;}
8003320: 4b77 ldr r3, [pc, #476] ; (8003500 <my_code+0x768>)
8003322: 681b ldr r3, [r3, #0]
8003324: 2b00 cmp r3, #0
8003326: dd04 ble.n 8003332 <my_code+0x59a>
8003328: 687b ldr r3, [r7, #4]
800332a: 3b64 subs r3, #100 ; 0x64
800332c: 607b str r3, [r7, #4]
800332e: 4b70 ldr r3, [pc, #448] ; (80034f0 <my_code+0x758>)
8003330: 60bb str r3, [r7, #8]
if(countdown_set<100){countdown_set=100;}
8003332: 687b ldr r3, [r7, #4]
8003334: 2b63 cmp r3, #99 ; 0x63
8003336: dc01 bgt.n 800333c <my_code+0x5a4>
8003338: 2364 movs r3, #100 ; 0x64
800333a: 607b str r3, [r7, #4]
if(countdown_set>60000){countdown_set=60000;}
800333c: 687b ldr r3, [r7, #4]
800333e: 4a72 ldr r2, [pc, #456] ; (8003508 <my_code+0x770>)
8003340: 4293 cmp r3, r2
8003342: dd01 ble.n 8003348 <my_code+0x5b0>
8003344: 4b70 ldr r3, [pc, #448] ; (8003508 <my_code+0x770>)
8003346: 607b str r3, [r7, #4]
if(key4.code!=0){mode=1;}
8003348: 4b6b ldr r3, [pc, #428] ; (80034f8 <my_code+0x760>)
800334a: 681b ldr r3, [r3, #0]
800334c: 2b00 cmp r3, #0
800334e: d003 beq.n 8003358 <my_code+0x5c0>
8003350: 230f movs r3, #15
8003352: 18fb adds r3, r7, r3
8003354: 2201 movs r2, #1
8003356: 701a strb r2, [r3, #0]
dis_buff.d_num[3]=(countdown_set/100)%10;
8003358: 687b ldr r3, [r7, #4]
800335a: 2164 movs r1, #100 ; 0x64
800335c: 0018 movs r0, r3
800335e: f7fc ff5d bl 800021c <__divsi3>
8003362: 0003 movs r3, r0
8003364: 210a movs r1, #10
8003366: 0018 movs r0, r3
8003368: f7fd f83e bl 80003e8 <__aeabi_idivmod>
800336c: 000b movs r3, r1
800336e: b2da uxtb r2, r3
8003370: 4b5e ldr r3, [pc, #376] ; (80034ec <my_code+0x754>)
8003372: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown_set/1000)%10;
8003374: 687b ldr r3, [r7, #4]
8003376: 22fa movs r2, #250 ; 0xfa
8003378: 0091 lsls r1, r2, #2
800337a: 0018 movs r0, r3
800337c: f7fc ff4e bl 800021c <__divsi3>
8003380: 0003 movs r3, r0
8003382: 210a movs r1, #10
8003384: 0018 movs r0, r3
8003386: f7fd f82f bl 80003e8 <__aeabi_idivmod>
800338a: 000b movs r3, r1
800338c: b2da uxtb r2, r3
800338e: 4b57 ldr r3, [pc, #348] ; (80034ec <my_code+0x754>)
8003390: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown_set/10000)%10);
8003392: 687b ldr r3, [r7, #4]
8003394: 4956 ldr r1, [pc, #344] ; (80034f0 <my_code+0x758>)
8003396: 0018 movs r0, r3
8003398: f7fc ff40 bl 800021c <__divsi3>
800339c: 0003 movs r3, r0
800339e: 210a movs r1, #10
80033a0: 0018 movs r0, r3
80033a2: f7fd f821 bl 80003e8 <__aeabi_idivmod>
80033a6: 000b movs r3, r1
80033a8: b2da uxtb r2, r3
80033aa: 4b50 ldr r3, [pc, #320] ; (80034ec <my_code+0x754>)
80033ac: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1];
80033ae: 4b4f ldr r3, [pc, #316] ; (80034ec <my_code+0x754>)
80033b0: 785b ldrb r3, [r3, #1]
80033b2: 2b00 cmp r3, #0
80033b4: d002 beq.n 80033bc <my_code+0x624>
80033b6: 4b4d ldr r3, [pc, #308] ; (80034ec <my_code+0x754>)
80033b8: 785a ldrb r2, [r3, #1]
80033ba: e000 b.n 80033be <my_code+0x626>
80033bc: 2210 movs r2, #16
80033be: 4b4b ldr r3, [pc, #300] ; (80034ec <my_code+0x754>)
80033c0: 705a strb r2, [r3, #1]
break;
80033c2: e07e b.n 80034c2 <my_code+0x72a>
case 5:
//overload
moto.moto1a=0;
80033c4: 4b48 ldr r3, [pc, #288] ; (80034e8 <my_code+0x750>)
80033c6: 2200 movs r2, #0
80033c8: 721a strb r2, [r3, #8]
moto.moto1b=0;
80033ca: 4b47 ldr r3, [pc, #284] ; (80034e8 <my_code+0x750>)
80033cc: 2200 movs r2, #0
80033ce: 725a strb r2, [r3, #9]
moto.moto2a=0;
80033d0: 4b45 ldr r3, [pc, #276] ; (80034e8 <my_code+0x750>)
80033d2: 2200 movs r2, #0
80033d4: 729a strb r2, [r3, #10]
moto.moto2b=0;
80033d6: 4b44 ldr r3, [pc, #272] ; (80034e8 <my_code+0x750>)
80033d8: 2200 movs r2, #0
80033da: 72da strb r2, [r3, #11]
dis_buff.led_run=1;
80033dc: 4b43 ldr r3, [pc, #268] ; (80034ec <my_code+0x754>)
80033de: 2201 movs r2, #1
80033e0: 731a strb r2, [r3, #12]
overload_times=0;
80033e2: 230c movs r3, #12
80033e4: 18fb adds r3, r7, r3
80033e6: 2200 movs r2, #0
80033e8: 801a strh r2, [r3, #0]
dis_buff.d_num[3]=(countdown/100)%10;
80033ea: 68bb ldr r3, [r7, #8]
80033ec: 2164 movs r1, #100 ; 0x64
80033ee: 0018 movs r0, r3
80033f0: f7fc ff14 bl 800021c <__divsi3>
80033f4: 0003 movs r3, r0
80033f6: 210a movs r1, #10
80033f8: 0018 movs r0, r3
80033fa: f7fc fff5 bl 80003e8 <__aeabi_idivmod>
80033fe: 000b movs r3, r1
8003400: b2da uxtb r2, r3
8003402: 4b3a ldr r3, [pc, #232] ; (80034ec <my_code+0x754>)
8003404: 70da strb r2, [r3, #3]
dis_buff.d_num[2]=(countdown/1000)%10;
8003406: 68bb ldr r3, [r7, #8]
8003408: 22fa movs r2, #250 ; 0xfa
800340a: 0091 lsls r1, r2, #2
800340c: 0018 movs r0, r3
800340e: f7fc ff05 bl 800021c <__divsi3>
8003412: 0003 movs r3, r0
8003414: 210a movs r1, #10
8003416: 0018 movs r0, r3
8003418: f7fc ffe6 bl 80003e8 <__aeabi_idivmod>
800341c: 000b movs r3, r1
800341e: b2da uxtb r2, r3
8003420: 4b32 ldr r3, [pc, #200] ; (80034ec <my_code+0x754>)
8003422: 709a strb r2, [r3, #2]
dis_buff.d_num[1]=((countdown/10000)%10);
8003424: 68bb ldr r3, [r7, #8]
8003426: 4932 ldr r1, [pc, #200] ; (80034f0 <my_code+0x758>)
8003428: 0018 movs r0, r3
800342a: f7fc fef7 bl 800021c <__divsi3>
800342e: 0003 movs r3, r0
8003430: 210a movs r1, #10
8003432: 0018 movs r0, r3
8003434: f7fc ffd8 bl 80003e8 <__aeabi_idivmod>
8003438: 000b movs r3, r1
800343a: b2da uxtb r2, r3
800343c: 4b2b ldr r3, [pc, #172] ; (80034ec <my_code+0x754>)
800343e: 705a strb r2, [r3, #1]
dis_buff.d_num[1]=dis_buff.d_num[1]==0?16:dis_buff.d_num[1];
8003440: 4b2a ldr r3, [pc, #168] ; (80034ec <my_code+0x754>)
8003442: 785b ldrb r3, [r3, #1]
8003444: 2b00 cmp r3, #0
8003446: d002 beq.n 800344e <my_code+0x6b6>
8003448: 4b28 ldr r3, [pc, #160] ; (80034ec <my_code+0x754>)
800344a: 785a ldrb r2, [r3, #1]
800344c: e000 b.n 8003450 <my_code+0x6b8>
800344e: 2210 movs r2, #16
8003450: 4b26 ldr r3, [pc, #152] ; (80034ec <my_code+0x754>)
8003452: 705a strb r2, [r3, #1]
dis_buff.dot3=1;
8003454: 4b25 ldr r3, [pc, #148] ; (80034ec <my_code+0x754>)
8003456: 2201 movs r2, #1
8003458: 729a strb r2, [r3, #10]
if(key4.code!=0){mode=1;}
800345a: 4b27 ldr r3, [pc, #156] ; (80034f8 <my_code+0x760>)
800345c: 681b ldr r3, [r3, #0]
800345e: 2b00 cmp r3, #0
8003460: d003 beq.n 800346a <my_code+0x6d2>
8003462: 230f movs r3, #15
8003464: 18fb adds r3, r7, r3
8003466: 2201 movs r2, #1
8003468: 701a strb r2, [r3, #0]
if(key2.code!=0)
800346a: 4b22 ldr r3, [pc, #136] ; (80034f4 <my_code+0x75c>)
800346c: 681b ldr r3, [r3, #0]
800346e: 2b00 cmp r3, #0
8003470: d00c beq.n 800348c <my_code+0x6f4>
{
mode=2;
8003472: 230f movs r3, #15
8003474: 18fb adds r3, r7, r3
8003476: 2202 movs r2, #2
8003478: 701a strb r2, [r3, #0]
if(overload_mode==2)
800347a: 230e movs r3, #14
800347c: 18fb adds r3, r7, r3
800347e: 781b ldrb r3, [r3, #0]
8003480: 2b02 cmp r3, #2
8003482: d003 beq.n 800348c <my_code+0x6f4>
{
}else
{
countdown=countdown_set-countdown;
8003484: 687a ldr r2, [r7, #4]
8003486: 68bb ldr r3, [r7, #8]
8003488: 1ad3 subs r3, r2, r3
800348a: 60bb str r3, [r7, #8]
}
}
if(key3.code!=0)
800348c: 4b1c ldr r3, [pc, #112] ; (8003500 <my_code+0x768>)
800348e: 681b ldr r3, [r3, #0]
8003490: 2b00 cmp r3, #0
8003492: d015 beq.n 80034c0 <my_code+0x728>
{
mode=3;
8003494: 230f movs r3, #15
8003496: 18fb adds r3, r7, r3
8003498: 2203 movs r2, #3
800349a: 701a strb r2, [r3, #0]
if(overload_mode==3)
800349c: 230e movs r3, #14
800349e: 18fb adds r3, r7, r3
80034a0: 781b ldrb r3, [r3, #0]
80034a2: 2b03 cmp r3, #3
80034a4: d00c beq.n 80034c0 <my_code+0x728>
{
}else
{
countdown=countdown_set-countdown;
80034a6: 687a ldr r2, [r7, #4]
80034a8: 68bb ldr r3, [r7, #8]
80034aa: 1ad3 subs r3, r2, r3
80034ac: 60bb str r3, [r7, #8]
}
}
break;
80034ae: e007 b.n 80034c0 <my_code+0x728>
break;
80034b0: 46c0 nop ; (mov r8, r8)
80034b2: e006 b.n 80034c2 <my_code+0x72a>
break;
80034b4: 46c0 nop ; (mov r8, r8)
80034b6: e004 b.n 80034c2 <my_code+0x72a>
break;
80034b8: 46c0 nop ; (mov r8, r8)
80034ba: e002 b.n 80034c2 <my_code+0x72a>
break;
80034bc: 46c0 nop ; (mov r8, r8)
80034be: e000 b.n 80034c2 <my_code+0x72a>
break;
80034c0: 46c0 nop ; (mov r8, r8)
}
if(ADCC.adc_value[0]>600||ADCC.adc_value[1]>600)
80034c2: 4b12 ldr r3, [pc, #72] ; (800350c <my_code+0x774>)
80034c4: 68da ldr r2, [r3, #12]
80034c6: 2396 movs r3, #150 ; 0x96
80034c8: 009b lsls r3, r3, #2
80034ca: 429a cmp r2, r3
80034cc: dc05 bgt.n 80034da <my_code+0x742>
80034ce: 4b0f ldr r3, [pc, #60] ; (800350c <my_code+0x774>)
80034d0: 691a ldr r2, [r3, #16]
80034d2: 2396 movs r3, #150 ; 0x96
80034d4: 009b lsls r3, r3, #2
80034d6: 429a cmp r2, r3
80034d8: dd1a ble.n 8003510 <my_code+0x778>
{
GEI_BUTTON_CODE(&overload,1);
80034da: 4b08 ldr r3, [pc, #32] ; (80034fc <my_code+0x764>)
80034dc: 2101 movs r1, #1
80034de: 0018 movs r0, r3
80034e0: f7ff f83a bl 8002558 <GEI_BUTTON_CODE>
80034e4: e019 b.n 800351a <my_code+0x782>
80034e6: 46c0 nop ; (mov r8, r8)
80034e8: 20000144 .word 0x20000144
80034ec: 20000038 .word 0x20000038
80034f0: 00002710 .word 0x00002710
80034f4: 20000134 .word 0x20000134
80034f8: 200000d8 .word 0x200000d8
80034fc: 20000100 .word 0x20000100
8003500: 20000110 .word 0x20000110
8003504: fffffc18 .word 0xfffffc18
8003508: 0000ea60 .word 0x0000ea60
800350c: 20000120 .word 0x20000120
}else
{
GEI_BUTTON_CODE(&overload,0);
8003510: 4b2a ldr r3, [pc, #168] ; (80035bc <my_code+0x824>)
8003512: 2100 movs r1, #0
8003514: 0018 movs r0, r3
8003516: f7ff f81f bl 8002558 <GEI_BUTTON_CODE>
}
switch(r480.key)
800351a: 4b29 ldr r3, [pc, #164] ; (80035c0 <my_code+0x828>)
800351c: 789b ldrb r3, [r3, #2]
800351e: 2bde cmp r3, #222 ; 0xde
8003520: d014 beq.n 800354c <my_code+0x7b4>
8003522: dc17 bgt.n 8003554 <my_code+0x7bc>
8003524: 2bdd cmp r3, #221 ; 0xdd
8003526: d00d beq.n 8003544 <my_code+0x7ac>
8003528: dc14 bgt.n 8003554 <my_code+0x7bc>
800352a: 2bd7 cmp r3, #215 ; 0xd7
800352c: d002 beq.n 8003534 <my_code+0x79c>
800352e: 2bdb cmp r3, #219 ; 0xdb
8003530: d004 beq.n 800353c <my_code+0x7a4>
8003532: e00f b.n 8003554 <my_code+0x7bc>
{
case 0xd7:
dis_buff.button_flag[0]=1;
8003534: 4b23 ldr r3, [pc, #140] ; (80035c4 <my_code+0x82c>)
8003536: 2201 movs r2, #1
8003538: 711a strb r2, [r3, #4]
break;
800353a: e00b b.n 8003554 <my_code+0x7bc>
case 0xdb:
dis_buff.button_flag[1]=1;
800353c: 4b21 ldr r3, [pc, #132] ; (80035c4 <my_code+0x82c>)
800353e: 2201 movs r2, #1
8003540: 715a strb r2, [r3, #5]
break;
8003542: e007 b.n 8003554 <my_code+0x7bc>
case 0xdd:
dis_buff.button_flag[2]=1;
8003544: 4b1f ldr r3, [pc, #124] ; (80035c4 <my_code+0x82c>)
8003546: 2201 movs r2, #1
8003548: 719a strb r2, [r3, #6]
break;
800354a: e003 b.n 8003554 <my_code+0x7bc>
case 0xde:
dis_buff.button_flag[3]=1;
800354c: 4b1d ldr r3, [pc, #116] ; (80035c4 <my_code+0x82c>)
800354e: 2201 movs r2, #1
8003550: 71da strb r2, [r3, #7]
break;
8003552: 46c0 nop ; (mov r8, r8)
}
r480.key=0;
8003554: 4b1a ldr r3, [pc, #104] ; (80035c0 <my_code+0x828>)
8003556: 2200 movs r2, #0
8003558: 709a strb r2, [r3, #2]
GEI_BUTTON_CODE(&key1,dis_buff.button_flag[0]);
800355a: 4b1a ldr r3, [pc, #104] ; (80035c4 <my_code+0x82c>)
800355c: 791a ldrb r2, [r3, #4]
800355e: 4b1a ldr r3, [pc, #104] ; (80035c8 <my_code+0x830>)
8003560: 0011 movs r1, r2
8003562: 0018 movs r0, r3
8003564: f7fe fff8 bl 8002558 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key2,dis_buff.button_flag[1]);
8003568: 4b16 ldr r3, [pc, #88] ; (80035c4 <my_code+0x82c>)
800356a: 795a ldrb r2, [r3, #5]
800356c: 4b17 ldr r3, [pc, #92] ; (80035cc <my_code+0x834>)
800356e: 0011 movs r1, r2
8003570: 0018 movs r0, r3
8003572: f7fe fff1 bl 8002558 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key3,dis_buff.button_flag[2]);
8003576: 4b13 ldr r3, [pc, #76] ; (80035c4 <my_code+0x82c>)
8003578: 799a ldrb r2, [r3, #6]
800357a: 4b15 ldr r3, [pc, #84] ; (80035d0 <my_code+0x838>)
800357c: 0011 movs r1, r2
800357e: 0018 movs r0, r3
8003580: f7fe ffea bl 8002558 <GEI_BUTTON_CODE>
GEI_BUTTON_CODE(&key4,dis_buff.button_flag[3]);
8003584: 4b0f ldr r3, [pc, #60] ; (80035c4 <my_code+0x82c>)
8003586: 79da ldrb r2, [r3, #7]
8003588: 4b12 ldr r3, [pc, #72] ; (80035d4 <my_code+0x83c>)
800358a: 0011 movs r1, r2
800358c: 0018 movs r0, r3
800358e: f7fe ffe3 bl 8002558 <GEI_BUTTON_CODE>
dis_buff.button_flag[0]=0;
8003592: 4b0c ldr r3, [pc, #48] ; (80035c4 <my_code+0x82c>)
8003594: 2200 movs r2, #0
8003596: 711a strb r2, [r3, #4]
dis_buff.button_flag[1]=0;
8003598: 4b0a ldr r3, [pc, #40] ; (80035c4 <my_code+0x82c>)
800359a: 2200 movs r2, #0
800359c: 715a strb r2, [r3, #5]
dis_buff.button_flag[2]=0;
800359e: 4b09 ldr r3, [pc, #36] ; (80035c4 <my_code+0x82c>)
80035a0: 2200 movs r2, #0
80035a2: 719a strb r2, [r3, #6]
dis_buff.button_flag[3]=0;
80035a4: 4b07 ldr r3, [pc, #28] ; (80035c4 <my_code+0x82c>)
80035a6: 2200 movs r2, #0
80035a8: 71da strb r2, [r3, #7]
HT1621_Display_GetButton();
80035aa: f7ff fb63 bl 8002c74 <HT1621_Display_GetButton>
hc2_sever();
80035ae: f7ff fa4d bl 8002a4c <hc2_sever>
moto_server();
80035b2: f7ff fa8f bl 8002ad4 <moto_server>
for(char a=0;a<2;a++)
80035b6: f7ff fc0b bl 8002dd0 <my_code+0x38>
80035ba: 46c0 nop ; (mov r8, r8)
80035bc: 20000100 .word 0x20000100
80035c0: 200000e8 .word 0x200000e8
80035c4: 20000038 .word 0x20000038
80035c8: 200000f0 .word 0x200000f0
80035cc: 20000134 .word 0x20000134
80035d0: 20000110 .word 0x20000110
80035d4: 200000d8 .word 0x200000d8
080035d8 <r480_init>:
int read_char_flag=0;
char read_data_buffer[3];
char read_begin=0;
void r480_init()
{
80035d8: b580 push {r7, lr}
80035da: af00 add r7, sp, #0
HAL_TIM_Base_Start_IT(&htim14);
80035dc: 4b04 ldr r3, [pc, #16] ; (80035f0 <r480_init+0x18>)
80035de: 0018 movs r0, r3
80035e0: f7fe fdc2 bl 8002168 <HAL_TIM_Base_Start_IT>
r480.times=0;
80035e4: 4b03 ldr r3, [pc, #12] ; (80035f4 <r480_init+0x1c>)
80035e6: 2200 movs r2, #0
80035e8: 809a strh r2, [r3, #4]
}
80035ea: 46c0 nop ; (mov r8, r8)
80035ec: 46bd mov sp, r7
80035ee: bd80 pop {r7, pc}
80035f0: 2000004c .word 0x2000004c
80035f4: 200000e8 .word 0x200000e8
080035f8 <read_433_exit>:
void read_433_exit()
{
80035f8: b590 push {r4, r7, lr}
80035fa: b083 sub sp, #12
80035fc: af00 add r7, sp, #0
char a=read_infrared;
80035fe: 1dfc adds r4, r7, #7
8003600: 2390 movs r3, #144 ; 0x90
8003602: 05db lsls r3, r3, #23
8003604: 2108 movs r1, #8
8003606: 0018 movs r0, r3
8003608: f7fe f8bc bl 8001784 <HAL_GPIO_ReadPin>
800360c: 0003 movs r3, r0
800360e: 7023 strb r3, [r4, #0]
int b;
if(read_begin==0)
8003610: 4b41 ldr r3, [pc, #260] ; (8003718 <read_433_exit+0x120>)
8003612: 781b ldrb r3, [r3, #0]
8003614: 2b00 cmp r3, #0
8003616: d123 bne.n 8003660 <read_433_exit+0x68>
{
if(a==0)
8003618: 1dfb adds r3, r7, #7
800361a: 781b ldrb r3, [r3, #0]
800361c: 2b00 cmp r3, #0
800361e: d103 bne.n 8003628 <read_433_exit+0x30>
{
timer_100us_tick=0;
8003620: 4b3e ldr r3, [pc, #248] ; (800371c <read_433_exit+0x124>)
8003622: 2200 movs r2, #0
8003624: 801a strh r2, [r3, #0]
return ;
8003626: e073 b.n 8003710 <read_433_exit+0x118>
}else
{
if(timer_100us_tick>70&&timer_100us_tick<100)
8003628: 4b3c ldr r3, [pc, #240] ; (800371c <read_433_exit+0x124>)
800362a: 881b ldrh r3, [r3, #0]
800362c: 2b46 cmp r3, #70 ; 0x46
800362e: d800 bhi.n 8003632 <read_433_exit+0x3a>
8003630: e06e b.n 8003710 <read_433_exit+0x118>
8003632: 4b3a ldr r3, [pc, #232] ; (800371c <read_433_exit+0x124>)
8003634: 881b ldrh r3, [r3, #0]
8003636: 2b63 cmp r3, #99 ; 0x63
8003638: d86a bhi.n 8003710 <read_433_exit+0x118>
{
read_begin=1;
800363a: 4b37 ldr r3, [pc, #220] ; (8003718 <read_433_exit+0x120>)
800363c: 2201 movs r2, #1
800363e: 701a strb r2, [r3, #0]
r480.times++;
8003640: 4b37 ldr r3, [pc, #220] ; (8003720 <read_433_exit+0x128>)
8003642: 889b ldrh r3, [r3, #4]
8003644: 3301 adds r3, #1
8003646: b29a uxth r2, r3
8003648: 4b35 ldr r3, [pc, #212] ; (8003720 <read_433_exit+0x128>)
800364a: 809a strh r2, [r3, #4]
read_bit_flag=0;
800364c: 4b35 ldr r3, [pc, #212] ; (8003724 <read_433_exit+0x12c>)
800364e: 2200 movs r2, #0
8003650: 601a str r2, [r3, #0]
read_char_flag=0;
8003652: 4b35 ldr r3, [pc, #212] ; (8003728 <read_433_exit+0x130>)
8003654: 2200 movs r2, #0
8003656: 601a str r2, [r3, #0]
timer_100us_tick=0;
8003658: 4b30 ldr r3, [pc, #192] ; (800371c <read_433_exit+0x124>)
800365a: 2200 movs r2, #0
800365c: 801a strh r2, [r3, #0]
return ;
800365e: e057 b.n 8003710 <read_433_exit+0x118>
}
}
}else
{
if(timer_100us_tick<5)
8003660: 4b2e ldr r3, [pc, #184] ; (800371c <read_433_exit+0x124>)
8003662: 881b ldrh r3, [r3, #0]
8003664: 2b04 cmp r3, #4
8003666: d803 bhi.n 8003670 <read_433_exit+0x78>
{
timer_100us_tick=0;
8003668: 4b2c ldr r3, [pc, #176] ; (800371c <read_433_exit+0x124>)
800366a: 2200 movs r2, #0
800366c: 801a strh r2, [r3, #0]
return ;
800366e: e04f b.n 8003710 <read_433_exit+0x118>
}else if(timer_100us_tick<12)
8003670: 4b2a ldr r3, [pc, #168] ; (800371c <read_433_exit+0x124>)
8003672: 881b ldrh r3, [r3, #0]
8003674: 2b0b cmp r3, #11
8003676: d844 bhi.n 8003702 <read_433_exit+0x10a>
{
read_data_buffer[read_char_flag]<<=1;
8003678: 4b2b ldr r3, [pc, #172] ; (8003728 <read_433_exit+0x130>)
800367a: 681b ldr r3, [r3, #0]
800367c: 4a2b ldr r2, [pc, #172] ; (800372c <read_433_exit+0x134>)
800367e: 5cd1 ldrb r1, [r2, r3]
8003680: 4b29 ldr r3, [pc, #164] ; (8003728 <read_433_exit+0x130>)
8003682: 681a ldr r2, [r3, #0]
8003684: 1c0b adds r3, r1, #0
8003686: 18db adds r3, r3, r3
8003688: b2d9 uxtb r1, r3
800368a: 4b28 ldr r3, [pc, #160] ; (800372c <read_433_exit+0x134>)
800368c: 5499 strb r1, [r3, r2]
if(a==1)
800368e: 1dfb adds r3, r7, #7
8003690: 781b ldrb r3, [r3, #0]
8003692: 2b01 cmp r3, #1
8003694: d10a bne.n 80036ac <read_433_exit+0xb4>
{
read_data_buffer[read_char_flag]|=0x01;
8003696: 4b24 ldr r3, [pc, #144] ; (8003728 <read_433_exit+0x130>)
8003698: 681b ldr r3, [r3, #0]
800369a: 4a24 ldr r2, [pc, #144] ; (800372c <read_433_exit+0x134>)
800369c: 5cd2 ldrb r2, [r2, r3]
800369e: 4b22 ldr r3, [pc, #136] ; (8003728 <read_433_exit+0x130>)
80036a0: 681b ldr r3, [r3, #0]
80036a2: 2101 movs r1, #1
80036a4: 430a orrs r2, r1
80036a6: b2d1 uxtb r1, r2
80036a8: 4a20 ldr r2, [pc, #128] ; (800372c <read_433_exit+0x134>)
80036aa: 54d1 strb r1, [r2, r3]
}
read_bit_flag++;
80036ac: 4b1d ldr r3, [pc, #116] ; (8003724 <read_433_exit+0x12c>)
80036ae: 681b ldr r3, [r3, #0]
80036b0: 1c5a adds r2, r3, #1
80036b2: 4b1c ldr r3, [pc, #112] ; (8003724 <read_433_exit+0x12c>)
80036b4: 601a str r2, [r3, #0]
if(read_bit_flag==8)
80036b6: 4b1b ldr r3, [pc, #108] ; (8003724 <read_433_exit+0x12c>)
80036b8: 681b ldr r3, [r3, #0]
80036ba: 2b08 cmp r3, #8
80036bc: d11d bne.n 80036fa <read_433_exit+0x102>
{
read_bit_flag=0;
80036be: 4b19 ldr r3, [pc, #100] ; (8003724 <read_433_exit+0x12c>)
80036c0: 2200 movs r2, #0
80036c2: 601a str r2, [r3, #0]
read_char_flag++;
80036c4: 4b18 ldr r3, [pc, #96] ; (8003728 <read_433_exit+0x130>)
80036c6: 681b ldr r3, [r3, #0]
80036c8: 1c5a adds r2, r3, #1
80036ca: 4b17 ldr r3, [pc, #92] ; (8003728 <read_433_exit+0x130>)
80036cc: 601a str r2, [r3, #0]
if(read_char_flag==3)
80036ce: 4b16 ldr r3, [pc, #88] ; (8003728 <read_433_exit+0x130>)
80036d0: 681b ldr r3, [r3, #0]
80036d2: 2b03 cmp r3, #3
80036d4: d111 bne.n 80036fa <read_433_exit+0x102>
{
//got data
read_char_flag=0;
80036d6: 4b14 ldr r3, [pc, #80] ; (8003728 <read_433_exit+0x130>)
80036d8: 2200 movs r2, #0
80036da: 601a str r2, [r3, #0]
timer_100us_tick=0;
80036dc: 4b0f ldr r3, [pc, #60] ; (800371c <read_433_exit+0x124>)
80036de: 2200 movs r2, #0
80036e0: 801a strh r2, [r3, #0]
r480.add[0]=read_data_buffer[0];
80036e2: 4b12 ldr r3, [pc, #72] ; (800372c <read_433_exit+0x134>)
80036e4: 781a ldrb r2, [r3, #0]
80036e6: 4b0e ldr r3, [pc, #56] ; (8003720 <read_433_exit+0x128>)
80036e8: 701a strb r2, [r3, #0]
r480.add[1]=read_data_buffer[1];
80036ea: 4b10 ldr r3, [pc, #64] ; (800372c <read_433_exit+0x134>)
80036ec: 785a ldrb r2, [r3, #1]
80036ee: 4b0c ldr r3, [pc, #48] ; (8003720 <read_433_exit+0x128>)
80036f0: 705a strb r2, [r3, #1]
r480.key=read_data_buffer[2];
80036f2: 4b0e ldr r3, [pc, #56] ; (800372c <read_433_exit+0x134>)
80036f4: 789a ldrb r2, [r3, #2]
80036f6: 4b0a ldr r3, [pc, #40] ; (8003720 <read_433_exit+0x128>)
80036f8: 709a strb r2, [r3, #2]
}
}
timer_100us_tick=0;
80036fa: 4b08 ldr r3, [pc, #32] ; (800371c <read_433_exit+0x124>)
80036fc: 2200 movs r2, #0
80036fe: 801a strh r2, [r3, #0]
return ;
8003700: e006 b.n 8003710 <read_433_exit+0x118>
}else//time out
{
read_begin=0;
8003702: 4b05 ldr r3, [pc, #20] ; (8003718 <read_433_exit+0x120>)
8003704: 2200 movs r2, #0
8003706: 701a strb r2, [r3, #0]
timer_100us_tick=0;
8003708: 4b04 ldr r3, [pc, #16] ; (800371c <read_433_exit+0x124>)
800370a: 2200 movs r2, #0
800370c: 801a strh r2, [r3, #0]
return ;
800370e: 46c0 nop ; (mov r8, r8)
}
}
}
8003710: 46bd mov sp, r7
8003712: b003 add sp, #12
8003714: bd90 pop {r4, r7, pc}
8003716: 46c0 nop ; (mov r8, r8)
8003718: 20000034 .word 0x20000034
800371c: 20000028 .word 0x20000028
8003720: 200000e8 .word 0x200000e8
8003724: 2000002c .word 0x2000002c
8003728: 20000030 .word 0x20000030
800372c: 20000154 .word 0x20000154
08003730 <HAL_GPIO_EXTI_Callback>:
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8003730: b580 push {r7, lr}
8003732: b082 sub sp, #8
8003734: af00 add r7, sp, #0
8003736: 0002 movs r2, r0
8003738: 1dbb adds r3, r7, #6
800373a: 801a strh r2, [r3, #0]
switch(GPIO_Pin)
800373c: 1dbb adds r3, r7, #6
800373e: 881b ldrh r3, [r3, #0]
8003740: 2b08 cmp r3, #8
8003742: d102 bne.n 800374a <HAL_GPIO_EXTI_Callback+0x1a>
{
case infeaed_Pin:
read_433_exit();
8003744: f7ff ff58 bl 80035f8 <read_433_exit>
return ;
8003748: 46c0 nop ; (mov r8, r8)
break;
}
}
800374a: 46bd mov sp, r7
800374c: b002 add sp, #8
800374e: bd80 pop {r7, pc}
08003750 <HAL_TIM_PeriodElapsedCallback>:
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)//100us
{
8003750: b580 push {r7, lr}
8003752: b082 sub sp, #8
8003754: af00 add r7, sp, #0
8003756: 6078 str r0, [r7, #4]
if (htim == (&htim14))
8003758: 687a ldr r2, [r7, #4]
800375a: 4b06 ldr r3, [pc, #24] ; (8003774 <HAL_TIM_PeriodElapsedCallback+0x24>)
800375c: 429a cmp r2, r3
800375e: d105 bne.n 800376c <HAL_TIM_PeriodElapsedCallback+0x1c>
{
timer_100us_tick++;
8003760: 4b05 ldr r3, [pc, #20] ; (8003778 <HAL_TIM_PeriodElapsedCallback+0x28>)
8003762: 881b ldrh r3, [r3, #0]
8003764: 3301 adds r3, #1
8003766: b29a uxth r2, r3
8003768: 4b03 ldr r3, [pc, #12] ; (8003778 <HAL_TIM_PeriodElapsedCallback+0x28>)
800376a: 801a strh r2, [r3, #0]
}
}
800376c: 46c0 nop ; (mov r8, r8)
800376e: 46bd mov sp, r7
8003770: b002 add sp, #8
8003772: bd80 pop {r7, pc}
8003774: 2000004c .word 0x2000004c
8003778: 20000028 .word 0x20000028
0800377c <__libc_init_array>:
800377c: b570 push {r4, r5, r6, lr}
800377e: 2600 movs r6, #0
8003780: 4d0c ldr r5, [pc, #48] ; (80037b4 <__libc_init_array+0x38>)
8003782: 4c0d ldr r4, [pc, #52] ; (80037b8 <__libc_init_array+0x3c>)
8003784: 1b64 subs r4, r4, r5
8003786: 10a4 asrs r4, r4, #2
8003788: 42a6 cmp r6, r4
800378a: d109 bne.n 80037a0 <__libc_init_array+0x24>
800378c: 2600 movs r6, #0
800378e: f000 f821 bl 80037d4 <_init>
8003792: 4d0a ldr r5, [pc, #40] ; (80037bc <__libc_init_array+0x40>)
8003794: 4c0a ldr r4, [pc, #40] ; (80037c0 <__libc_init_array+0x44>)
8003796: 1b64 subs r4, r4, r5
8003798: 10a4 asrs r4, r4, #2
800379a: 42a6 cmp r6, r4
800379c: d105 bne.n 80037aa <__libc_init_array+0x2e>
800379e: bd70 pop {r4, r5, r6, pc}
80037a0: 00b3 lsls r3, r6, #2
80037a2: 58eb ldr r3, [r5, r3]
80037a4: 4798 blx r3
80037a6: 3601 adds r6, #1
80037a8: e7ee b.n 8003788 <__libc_init_array+0xc>
80037aa: 00b3 lsls r3, r6, #2
80037ac: 58eb ldr r3, [r5, r3]
80037ae: 4798 blx r3
80037b0: 3601 adds r6, #1
80037b2: e7f2 b.n 800379a <__libc_init_array+0x1e>
80037b4: 08003848 .word 0x08003848
80037b8: 08003848 .word 0x08003848
80037bc: 08003848 .word 0x08003848
80037c0: 0800384c .word 0x0800384c
080037c4 <memset>:
80037c4: 0003 movs r3, r0
80037c6: 1882 adds r2, r0, r2
80037c8: 4293 cmp r3, r2
80037ca: d100 bne.n 80037ce <memset+0xa>
80037cc: 4770 bx lr
80037ce: 7019 strb r1, [r3, #0]
80037d0: 3301 adds r3, #1
80037d2: e7f9 b.n 80037c8 <memset+0x4>
080037d4 <_init>:
80037d4: b5f8 push {r3, r4, r5, r6, r7, lr}
80037d6: 46c0 nop ; (mov r8, r8)
80037d8: bcf8 pop {r3, r4, r5, r6, r7}
80037da: bc08 pop {r3}
80037dc: 469e mov lr, r3
80037de: 4770 bx lr
080037e0 <_fini>:
80037e0: b5f8 push {r3, r4, r5, r6, r7, lr}
80037e2: 46c0 nop ; (mov r8, r8)
80037e4: bcf8 pop {r3, r4, r5, r6, r7}
80037e6: bc08 pop {r3}
80037e8: 469e mov lr, r3
80037ea: 4770 bx lr
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