: /** * @brief The application entry point. * @retval int */ int main(void) { 8000224: b580 push {r7, lr} 8000226: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000228: f000 faa8 bl 800077c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800022c: f000 f80b bl 8000246 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000230: f000 f884 bl 800033c MX_FSMC_Init(); 8000234: f000 f908 bl 8000448 MX_SPI2_Init(); 8000238: f000 f84a bl 80002d0 MX_FATFS_Init(); 800023c: f002 f838 bl 80022b0 /* USER CODE BEGIN 2 */ my_main(); 8000240: f002 f90a bl 8002458 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000244: e7fe b.n 8000244 08000246 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000246: b580 push {r7, lr} 8000248: b090 sub sp, #64 ; 0x40 800024a: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800024c: f107 0318 add.w r3, r7, #24 8000250: 2228 movs r2, #40 ; 0x28 8000252: 2100 movs r1, #0 8000254: 4618 mov r0, r3 8000256: f003 fcf1 bl 8003c3c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800025a: 1d3b adds r3, r7, #4 800025c: 2200 movs r2, #0 800025e: 601a str r2, [r3, #0] 8000260: 605a str r2, [r3, #4] 8000262: 609a str r2, [r3, #8] 8000264: 60da str r2, [r3, #12] 8000266: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000268: 2301 movs r3, #1 800026a: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800026c: f44f 3380 mov.w r3, #65536 ; 0x10000 8000270: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8000272: 2300 movs r3, #0 8000274: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000276: 2301 movs r3, #1 8000278: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800027a: 2302 movs r3, #2 800027c: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800027e: f44f 3380 mov.w r3, #65536 ; 0x10000 8000282: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8000284: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8000288: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800028a: f107 0318 add.w r3, r7, #24 800028e: 4618 mov r0, r3 8000290: f000 fd8a bl 8000da8 8000294: 4603 mov r3, r0 8000296: 2b00 cmp r3, #0 8000298: d001 beq.n 800029e { Error_Handler(); 800029a: f000 f939 bl 8000510 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800029e: 230f movs r3, #15 80002a0: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80002a2: 2302 movs r3, #2 80002a4: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002a6: 2300 movs r3, #0 80002a8: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80002aa: f44f 6380 mov.w r3, #1024 ; 0x400 80002ae: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80002b0: 2300 movs r3, #0 80002b2: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80002b4: 1d3b adds r3, r7, #4 80002b6: 2102 movs r1, #2 80002b8: 4618 mov r0, r3 80002ba: f000 fff5 bl 80012a8 80002be: 4603 mov r3, r0 80002c0: 2b00 cmp r3, #0 80002c2: d001 beq.n 80002c8 { Error_Handler(); 80002c4: f000 f924 bl 8000510 } } 80002c8: bf00 nop 80002ca: 3740 adds r7, #64 ; 0x40 80002cc: 46bd mov sp, r7 80002ce: bd80 pop {r7, pc} 080002d0 : * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 80002d0: b580 push {r7, lr} 80002d2: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 80002d4: 4b17 ldr r3, [pc, #92] ; (8000334 ) 80002d6: 4a18 ldr r2, [pc, #96] ; (8000338 ) 80002d8: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_MASTER; 80002da: 4b16 ldr r3, [pc, #88] ; (8000334 ) 80002dc: f44f 7282 mov.w r2, #260 ; 0x104 80002e0: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 80002e2: 4b14 ldr r3, [pc, #80] ; (8000334 ) 80002e4: 2200 movs r2, #0 80002e6: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 80002e8: 4b12 ldr r3, [pc, #72] ; (8000334 ) 80002ea: 2200 movs r2, #0 80002ec: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 80002ee: 4b11 ldr r3, [pc, #68] ; (8000334 ) 80002f0: 2200 movs r2, #0 80002f2: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 80002f4: 4b0f ldr r3, [pc, #60] ; (8000334 ) 80002f6: 2200 movs r2, #0 80002f8: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 80002fa: 4b0e ldr r3, [pc, #56] ; (8000334 ) 80002fc: f44f 7200 mov.w r2, #512 ; 0x200 8000300: 619a str r2, [r3, #24] hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8000302: 4b0c ldr r3, [pc, #48] ; (8000334 ) 8000304: 2200 movs r2, #0 8000306: 61da str r2, [r3, #28] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 8000308: 4b0a ldr r3, [pc, #40] ; (8000334 ) 800030a: 2200 movs r2, #0 800030c: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 800030e: 4b09 ldr r3, [pc, #36] ; (8000334 ) 8000310: 2200 movs r2, #0 8000312: 625a str r2, [r3, #36] ; 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8000314: 4b07 ldr r3, [pc, #28] ; (8000334 ) 8000316: 2200 movs r2, #0 8000318: 629a str r2, [r3, #40] ; 0x28 hspi2.Init.CRCPolynomial = 10; 800031a: 4b06 ldr r3, [pc, #24] ; (8000334 ) 800031c: 220a movs r2, #10 800031e: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi2) != HAL_OK) 8000320: 4804 ldr r0, [pc, #16] ; (8000334 ) 8000322: f001 f929 bl 8001578 8000326: 4603 mov r3, r0 8000328: 2b00 cmp r3, #0 800032a: d001 beq.n 8000330 { Error_Handler(); 800032c: f000 f8f0 bl 8000510 } /* USER CODE BEGIN SPI2_Init 2 */ /* USER CODE END SPI2_Init 2 */ } 8000330: bf00 nop 8000332: bd80 pop {r7, pc} 8000334: 20000054 .word 0x20000054 8000338: 40003800 .word 0x40003800 0800033c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800033c: b580 push {r7, lr} 800033e: b08a sub sp, #40 ; 0x28 8000340: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000342: f107 0318 add.w r3, r7, #24 8000346: 2200 movs r2, #0 8000348: 601a str r2, [r3, #0] 800034a: 605a str r2, [r3, #4] 800034c: 609a str r2, [r3, #8] 800034e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8000350: 4b3a ldr r3, [pc, #232] ; (800043c ) 8000352: 699b ldr r3, [r3, #24] 8000354: 4a39 ldr r2, [pc, #228] ; (800043c ) 8000356: f043 0308 orr.w r3, r3, #8 800035a: 6193 str r3, [r2, #24] 800035c: 4b37 ldr r3, [pc, #220] ; (800043c ) 800035e: 699b ldr r3, [r3, #24] 8000360: f003 0308 and.w r3, r3, #8 8000364: 617b str r3, [r7, #20] 8000366: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000368: 4b34 ldr r3, [pc, #208] ; (800043c ) 800036a: 699b ldr r3, [r3, #24] 800036c: 4a33 ldr r2, [pc, #204] ; (800043c ) 800036e: f443 7380 orr.w r3, r3, #256 ; 0x100 8000372: 6193 str r3, [r2, #24] 8000374: 4b31 ldr r3, [pc, #196] ; (800043c ) 8000376: 699b ldr r3, [r3, #24] 8000378: f403 7380 and.w r3, r3, #256 ; 0x100 800037c: 613b str r3, [r7, #16] 800037e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000380: 4b2e ldr r3, [pc, #184] ; (800043c ) 8000382: 699b ldr r3, [r3, #24] 8000384: 4a2d ldr r2, [pc, #180] ; (800043c ) 8000386: f043 0340 orr.w r3, r3, #64 ; 0x40 800038a: 6193 str r3, [r2, #24] 800038c: 4b2b ldr r3, [pc, #172] ; (800043c ) 800038e: 699b ldr r3, [r3, #24] 8000390: f003 0340 and.w r3, r3, #64 ; 0x40 8000394: 60fb str r3, [r7, #12] 8000396: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000398: 4b28 ldr r3, [pc, #160] ; (800043c ) 800039a: 699b ldr r3, [r3, #24] 800039c: 4a27 ldr r2, [pc, #156] ; (800043c ) 800039e: f043 0320 orr.w r3, r3, #32 80003a2: 6193 str r3, [r2, #24] 80003a4: 4b25 ldr r3, [pc, #148] ; (800043c ) 80003a6: 699b ldr r3, [r3, #24] 80003a8: f003 0320 and.w r3, r3, #32 80003ac: 60bb str r3, [r7, #8] 80003ae: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80003b0: 4b22 ldr r3, [pc, #136] ; (800043c ) 80003b2: 699b ldr r3, [r3, #24] 80003b4: 4a21 ldr r2, [pc, #132] ; (800043c ) 80003b6: f043 0304 orr.w r3, r3, #4 80003ba: 6193 str r3, [r2, #24] 80003bc: 4b1f ldr r3, [pc, #124] ; (800043c ) 80003be: 699b ldr r3, [r3, #24] 80003c0: f003 0304 and.w r3, r3, #4 80003c4: 607b str r3, [r7, #4] 80003c6: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LCD_BL_Pin|FLASH_E_Pin, GPIO_PIN_RESET); 80003c8: 2200 movs r2, #0 80003ca: f241 0101 movw r1, #4097 ; 0x1001 80003ce: 481c ldr r0, [pc, #112] ; (8000440 ) 80003d0: f000 fcd2 bl 8000d78 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(SD_E_GPIO_Port, SD_E_Pin, GPIO_PIN_RESET); 80003d4: 2200 movs r2, #0 80003d6: 2104 movs r1, #4 80003d8: 481a ldr r0, [pc, #104] ; (8000444 ) 80003da: f000 fccd bl 8000d78 /*Configure GPIO pin : LCD_BL_Pin */ GPIO_InitStruct.Pin = LCD_BL_Pin; 80003de: 2301 movs r3, #1 80003e0: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80003e2: 2301 movs r3, #1 80003e4: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80003e6: 2300 movs r3, #0 80003e8: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80003ea: 2302 movs r3, #2 80003ec: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct); 80003ee: f107 0318 add.w r3, r7, #24 80003f2: 4619 mov r1, r3 80003f4: 4812 ldr r0, [pc, #72] ; (8000440 ) 80003f6: f000 fb2b bl 8000a50 /*Configure GPIO pin : FLASH_E_Pin */ GPIO_InitStruct.Pin = FLASH_E_Pin; 80003fa: f44f 5380 mov.w r3, #4096 ; 0x1000 80003fe: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000400: 2301 movs r3, #1 8000402: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000404: 2300 movs r3, #0 8000406: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000408: 2303 movs r3, #3 800040a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(FLASH_E_GPIO_Port, &GPIO_InitStruct); 800040c: f107 0318 add.w r3, r7, #24 8000410: 4619 mov r1, r3 8000412: 480b ldr r0, [pc, #44] ; (8000440 ) 8000414: f000 fb1c bl 8000a50 /*Configure GPIO pin : SD_E_Pin */ GPIO_InitStruct.Pin = SD_E_Pin; 8000418: 2304 movs r3, #4 800041a: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800041c: 2301 movs r3, #1 800041e: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000420: 2300 movs r3, #0 8000422: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000424: 2303 movs r3, #3 8000426: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(SD_E_GPIO_Port, &GPIO_InitStruct); 8000428: f107 0318 add.w r3, r7, #24 800042c: 4619 mov r1, r3 800042e: 4805 ldr r0, [pc, #20] ; (8000444 ) 8000430: f000 fb0e bl 8000a50 } 8000434: bf00 nop 8000436: 3728 adds r7, #40 ; 0x28 8000438: 46bd mov sp, r7 800043a: bd80 pop {r7, pc} 800043c: 40021000 .word 0x40021000 8000440: 40010c00 .word 0x40010c00 8000444: 40011400 .word 0x40011400 08000448 : /* FSMC initialization function */ static void MX_FSMC_Init(void) { 8000448: b580 push {r7, lr} 800044a: b088 sub sp, #32 800044c: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; 800044e: 1d3b adds r3, r7, #4 8000450: 2200 movs r2, #0 8000452: 601a str r2, [r3, #0] 8000454: 605a str r2, [r3, #4] 8000456: 609a str r2, [r3, #8] 8000458: 60da str r2, [r3, #12] 800045a: 611a str r2, [r3, #16] 800045c: 615a str r2, [r3, #20] 800045e: 619a str r2, [r3, #24] /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; 8000460: 4b28 ldr r3, [pc, #160] ; (8000504 ) 8000462: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000 8000466: 601a str r2, [r3, #0] hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 8000468: 4b26 ldr r3, [pc, #152] ; (8000504 ) 800046a: 4a27 ldr r2, [pc, #156] ; (8000508 ) 800046c: 605a str r2, [r3, #4] /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK4; 800046e: 4b25 ldr r3, [pc, #148] ; (8000504 ) 8000470: 2206 movs r2, #6 8000472: 609a str r2, [r3, #8] hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 8000474: 4b23 ldr r3, [pc, #140] ; (8000504 ) 8000476: 2200 movs r2, #0 8000478: 60da str r2, [r3, #12] hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 800047a: 4b22 ldr r3, [pc, #136] ; (8000504 ) 800047c: 2200 movs r2, #0 800047e: 611a str r2, [r3, #16] hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; 8000480: 4b20 ldr r3, [pc, #128] ; (8000504 ) 8000482: 2210 movs r2, #16 8000484: 615a str r2, [r3, #20] hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; 8000486: 4b1f ldr r3, [pc, #124] ; (8000504 ) 8000488: 2200 movs r2, #0 800048a: 619a str r2, [r3, #24] hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 800048c: 4b1d ldr r3, [pc, #116] ; (8000504 ) 800048e: 2200 movs r2, #0 8000490: 61da str r2, [r3, #28] hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 8000492: 4b1c ldr r3, [pc, #112] ; (8000504 ) 8000494: 2200 movs r2, #0 8000496: 621a str r2, [r3, #32] hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 8000498: 4b1a ldr r3, [pc, #104] ; (8000504 ) 800049a: 2200 movs r2, #0 800049c: 625a str r2, [r3, #36] ; 0x24 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 800049e: 4b19 ldr r3, [pc, #100] ; (8000504 ) 80004a0: f44f 5280 mov.w r2, #4096 ; 0x1000 80004a4: 629a str r2, [r3, #40] ; 0x28 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 80004a6: 4b17 ldr r3, [pc, #92] ; (8000504 ) 80004a8: 2200 movs r2, #0 80004aa: 62da str r2, [r3, #44] ; 0x2c hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 80004ac: 4b15 ldr r3, [pc, #84] ; (8000504 ) 80004ae: 2200 movs r2, #0 80004b0: 631a str r2, [r3, #48] ; 0x30 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 80004b2: 4b14 ldr r3, [pc, #80] ; (8000504 ) 80004b4: 2200 movs r2, #0 80004b6: 635a str r2, [r3, #52] ; 0x34 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; 80004b8: 4b12 ldr r3, [pc, #72] ; (8000504 ) 80004ba: 2200 movs r2, #0 80004bc: 639a str r2, [r3, #56] ; 0x38 /* Timing */ Timing.AddressSetupTime = 0; 80004be: 2300 movs r3, #0 80004c0: 607b str r3, [r7, #4] Timing.AddressHoldTime = 15; 80004c2: 230f movs r3, #15 80004c4: 60bb str r3, [r7, #8] Timing.DataSetupTime = 1; 80004c6: 2301 movs r3, #1 80004c8: 60fb str r3, [r7, #12] Timing.BusTurnAroundDuration = 15; 80004ca: 230f movs r3, #15 80004cc: 613b str r3, [r7, #16] Timing.CLKDivision = 16; 80004ce: 2310 movs r3, #16 80004d0: 617b str r3, [r7, #20] Timing.DataLatency = 17; 80004d2: 2311 movs r3, #17 80004d4: 61bb str r3, [r7, #24] Timing.AccessMode = FSMC_ACCESS_MODE_A; 80004d6: 2300 movs r3, #0 80004d8: 61fb str r3, [r7, #28] /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) 80004da: 1d3b adds r3, r7, #4 80004dc: 2200 movs r2, #0 80004de: 4619 mov r1, r3 80004e0: 4808 ldr r0, [pc, #32] ; (8000504 ) 80004e2: f001 fdc1 bl 8002068 80004e6: 4603 mov r3, r0 80004e8: 2b00 cmp r3, #0 80004ea: d001 beq.n 80004f0 { Error_Handler( ); 80004ec: f000 f810 bl 8000510 } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); 80004f0: 4b06 ldr r3, [pc, #24] ; (800050c ) 80004f2: 69db ldr r3, [r3, #28] 80004f4: 4a05 ldr r2, [pc, #20] ; (800050c ) 80004f6: f443 6380 orr.w r3, r3, #1024 ; 0x400 80004fa: 61d3 str r3, [r2, #28] /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } 80004fc: bf00 nop 80004fe: 3720 adds r7, #32 8000500: 46bd mov sp, r7 8000502: bd80 pop {r7, pc} 8000504: 200000ac .word 0x200000ac 8000508: a0000104 .word 0xa0000104 800050c: 40010000 .word 0x40010000 08000510 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000510: b480 push {r7} 8000512: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000514: b672 cpsid i } 8000516: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000518: e7fe b.n 8000518 ... 0800051c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800051c: b480 push {r7} 800051e: b085 sub sp, #20 8000520: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000522: 4b15 ldr r3, [pc, #84] ; (8000578 ) 8000524: 699b ldr r3, [r3, #24] 8000526: 4a14 ldr r2, [pc, #80] ; (8000578 ) 8000528: f043 0301 orr.w r3, r3, #1 800052c: 6193 str r3, [r2, #24] 800052e: 4b12 ldr r3, [pc, #72] ; (8000578 ) 8000530: 699b ldr r3, [r3, #24] 8000532: f003 0301 and.w r3, r3, #1 8000536: 60bb str r3, [r7, #8] 8000538: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800053a: 4b0f ldr r3, [pc, #60] ; (8000578 ) 800053c: 69db ldr r3, [r3, #28] 800053e: 4a0e ldr r2, [pc, #56] ; (8000578 ) 8000540: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000544: 61d3 str r3, [r2, #28] 8000546: 4b0c ldr r3, [pc, #48] ; (8000578 ) 8000548: 69db ldr r3, [r3, #28] 800054a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8000552: 4b0a ldr r3, [pc, #40] ; (800057c ) 8000554: 685b ldr r3, [r3, #4] 8000556: 60fb str r3, [r7, #12] 8000558: 68fb ldr r3, [r7, #12] 800055a: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 800055e: 60fb str r3, [r7, #12] 8000560: 68fb ldr r3, [r7, #12] 8000562: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8000566: 60fb str r3, [r7, #12] 8000568: 4a04 ldr r2, [pc, #16] ; (800057c ) 800056a: 68fb ldr r3, [r7, #12] 800056c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800056e: bf00 nop 8000570: 3714 adds r7, #20 8000572: 46bd mov sp, r7 8000574: bc80 pop {r7} 8000576: 4770 bx lr 8000578: 40021000 .word 0x40021000 800057c: 40010000 .word 0x40010000 08000580 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8000580: b580 push {r7, lr} 8000582: b088 sub sp, #32 8000584: af00 add r7, sp, #0 8000586: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000588: f107 0310 add.w r3, r7, #16 800058c: 2200 movs r2, #0 800058e: 601a str r2, [r3, #0] 8000590: 605a str r2, [r3, #4] 8000592: 609a str r2, [r3, #8] 8000594: 60da str r2, [r3, #12] if(hspi->Instance==SPI2) 8000596: 687b ldr r3, [r7, #4] 8000598: 681b ldr r3, [r3, #0] 800059a: 4a1c ldr r2, [pc, #112] ; (800060c ) 800059c: 4293 cmp r3, r2 800059e: d131 bne.n 8000604 { /* USER CODE BEGIN SPI2_MspInit 0 */ /* USER CODE END SPI2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); 80005a0: 4b1b ldr r3, [pc, #108] ; (8000610 ) 80005a2: 69db ldr r3, [r3, #28] 80005a4: 4a1a ldr r2, [pc, #104] ; (8000610 ) 80005a6: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80005aa: 61d3 str r3, [r2, #28] 80005ac: 4b18 ldr r3, [pc, #96] ; (8000610 ) 80005ae: 69db ldr r3, [r3, #28] 80005b0: f403 4380 and.w r3, r3, #16384 ; 0x4000 80005b4: 60fb str r3, [r7, #12] 80005b6: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 80005b8: 4b15 ldr r3, [pc, #84] ; (8000610 ) 80005ba: 699b ldr r3, [r3, #24] 80005bc: 4a14 ldr r2, [pc, #80] ; (8000610 ) 80005be: f043 0308 orr.w r3, r3, #8 80005c2: 6193 str r3, [r2, #24] 80005c4: 4b12 ldr r3, [pc, #72] ; (8000610 ) 80005c6: 699b ldr r3, [r3, #24] 80005c8: f003 0308 and.w r3, r3, #8 80005cc: 60bb str r3, [r7, #8] 80005ce: 68bb ldr r3, [r7, #8] /**SPI2 GPIO Configuration PB13 ------> SPI2_SCK PB14 ------> SPI2_MISO PB15 ------> SPI2_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; 80005d0: f44f 4320 mov.w r3, #40960 ; 0xa000 80005d4: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80005d6: 2302 movs r3, #2 80005d8: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80005da: 2303 movs r3, #3 80005dc: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80005de: f107 0310 add.w r3, r7, #16 80005e2: 4619 mov r1, r3 80005e4: 480b ldr r0, [pc, #44] ; (8000614 ) 80005e6: f000 fa33 bl 8000a50 GPIO_InitStruct.Pin = GPIO_PIN_14; 80005ea: f44f 4380 mov.w r3, #16384 ; 0x4000 80005ee: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80005f0: 2300 movs r3, #0 80005f2: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80005f4: 2300 movs r3, #0 80005f6: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80005f8: f107 0310 add.w r3, r7, #16 80005fc: 4619 mov r1, r3 80005fe: 4805 ldr r0, [pc, #20] ; (8000614 ) 8000600: f000 fa26 bl 8000a50 /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ } } 8000604: bf00 nop 8000606: 3720 adds r7, #32 8000608: 46bd mov sp, r7 800060a: bd80 pop {r7, pc} 800060c: 40003800 .word 0x40003800 8000610: 40021000 .word 0x40021000 8000614: 40010c00 .word 0x40010c00 08000618 : } static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ 8000618: b580 push {r7, lr} 800061a: b086 sub sp, #24 800061c: af00 add r7, sp, #0 /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 800061e: f107 0308 add.w r3, r7, #8 8000622: 2200 movs r2, #0 8000624: 601a str r2, [r3, #0] 8000626: 605a str r2, [r3, #4] 8000628: 609a str r2, [r3, #8] 800062a: 60da str r2, [r3, #12] if (FSMC_Initialized) { 800062c: 4b1f ldr r3, [pc, #124] ; (80006ac ) 800062e: 681b ldr r3, [r3, #0] 8000630: 2b00 cmp r3, #0 8000632: d136 bne.n 80006a2 return; } FSMC_Initialized = 1; 8000634: 4b1d ldr r3, [pc, #116] ; (80006ac ) 8000636: 2201 movs r2, #1 8000638: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); 800063a: 4b1d ldr r3, [pc, #116] ; (80006b0 ) 800063c: 695b ldr r3, [r3, #20] 800063e: 4a1c ldr r2, [pc, #112] ; (80006b0 ) 8000640: f443 7380 orr.w r3, r3, #256 ; 0x100 8000644: 6153 str r3, [r2, #20] 8000646: 4b1a ldr r3, [pc, #104] ; (80006b0 ) 8000648: 695b ldr r3, [r3, #20] 800064a: f403 7380 and.w r3, r3, #256 ; 0x100 800064e: 607b str r3, [r7, #4] 8000650: 687b ldr r3, [r7, #4] PD1 ------> FSMC_D3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PG12 ------> FSMC_NE4 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12; 8000652: f241 0301 movw r3, #4097 ; 0x1001 8000656: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000658: 2302 movs r3, #2 800065a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800065c: 2303 movs r3, #3 800065e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000660: f107 0308 add.w r3, r7, #8 8000664: 4619 mov r1, r3 8000666: 4813 ldr r0, [pc, #76] ; (80006b4 ) 8000668: f000 f9f2 bl 8000a50 GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800066c: f64f 7380 movw r3, #65408 ; 0xff80 8000670: 60bb str r3, [r7, #8] |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 |GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000672: 2302 movs r3, #2 8000674: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000676: 2303 movs r3, #3 8000678: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800067a: f107 0308 add.w r3, r7, #8 800067e: 4619 mov r1, r3 8000680: 480d ldr r0, [pc, #52] ; (80006b8 ) 8000682: f000 f9e5 bl 8000a50 GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 8000686: f24c 7333 movw r3, #50995 ; 0xc733 800068a: 60bb str r3, [r7, #8] |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4 |GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800068c: 2302 movs r3, #2 800068e: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000690: 2303 movs r3, #3 8000692: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000694: f107 0308 add.w r3, r7, #8 8000698: 4619 mov r1, r3 800069a: 4808 ldr r0, [pc, #32] ; (80006bc ) 800069c: f000 f9d8 bl 8000a50 80006a0: e000 b.n 80006a4 return; 80006a2: bf00 nop /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } 80006a4: 3718 adds r7, #24 80006a6: 46bd mov sp, r7 80006a8: bd80 pop {r7, pc} 80006aa: bf00 nop 80006ac: 20000040 .word 0x20000040 80006b0: 40021000 .word 0x40021000 80006b4: 40012000 .word 0x40012000 80006b8: 40011800 .word 0x40011800 80006bc: 40011400 .word 0x40011400 080006c0 : void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ 80006c0: b580 push {r7, lr} 80006c2: b082 sub sp, #8 80006c4: af00 add r7, sp, #0 80006c6: 6078 str r0, [r7, #4] /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); 80006c8: f7ff ffa6 bl 8000618 /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } 80006cc: bf00 nop 80006ce: 3708 adds r7, #8 80006d0: 46bd mov sp, r7 80006d2: bd80 pop {r7, pc} 080006d4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80006d4: b480 push {r7} 80006d6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80006d8: e7fe b.n 80006d8 080006da : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80006da: b480 push {r7} 80006dc: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80006de: e7fe b.n 80006de 080006e0 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80006e0: b480 push {r7} 80006e2: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80006e4: e7fe b.n 80006e4 080006e6 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80006e6: b480 push {r7} 80006e8: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80006ea: e7fe b.n 80006ea 080006ec : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80006ec: b480 push {r7} 80006ee: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80006f0: e7fe b.n 80006f0 080006f2 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80006f2: b480 push {r7} 80006f4: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80006f6: bf00 nop 80006f8: 46bd mov sp, r7 80006fa: bc80 pop {r7} 80006fc: 4770 bx lr 080006fe : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80006fe: b480 push {r7} 8000700: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000702: bf00 nop 8000704: 46bd mov sp, r7 8000706: bc80 pop {r7} 8000708: 4770 bx lr 0800070a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800070a: b480 push {r7} 800070c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800070e: bf00 nop 8000710: 46bd mov sp, r7 8000712: bc80 pop {r7} 8000714: 4770 bx lr 08000716 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000716: b580 push {r7, lr} 8000718: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800071a: f000 f875 bl 8000808 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800071e: bf00 nop 8000720: bd80 pop {r7, pc} 08000722 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8000722: b480 push {r7} 8000724: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000726: bf00 nop 8000728: 46bd mov sp, r7 800072a: bc80 pop {r7} 800072c: 4770 bx lr ... 08000730 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000730: 2100 movs r1, #0 b LoopCopyDataInit 8000732: e003 b.n 800073c 08000734 : CopyDataInit: ldr r3, =_sidata 8000734: 4b0b ldr r3, [pc, #44] ; (8000764 ) ldr r3, [r3, r1] 8000736: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8000738: 5043 str r3, [r0, r1] adds r1, r1, #4 800073a: 3104 adds r1, #4 0800073c : LoopCopyDataInit: ldr r0, =_sdata 800073c: 480a ldr r0, [pc, #40] ; (8000768 ) ldr r3, =_edata 800073e: 4b0b ldr r3, [pc, #44] ; (800076c ) adds r2, r0, r1 8000740: 1842 adds r2, r0, r1 cmp r2, r3 8000742: 429a cmp r2, r3 bcc CopyDataInit 8000744: d3f6 bcc.n 8000734 ldr r2, =_sbss 8000746: 4a0a ldr r2, [pc, #40] ; (8000770 ) b LoopFillZerobss 8000748: e002 b.n 8000750 0800074a : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800074a: 2300 movs r3, #0 str r3, [r2], #4 800074c: f842 3b04 str.w r3, [r2], #4 08000750 : LoopFillZerobss: ldr r3, = _ebss 8000750: 4b08 ldr r3, [pc, #32] ; (8000774 ) cmp r2, r3 8000752: 429a cmp r2, r3 bcc FillZerobss 8000754: d3f9 bcc.n 800074a /* Call the clock system intitialization function.*/ bl SystemInit 8000756: f7ff ffe4 bl 8000722 /* Call static constructors */ bl __libc_init_array 800075a: f003 fa4b bl 8003bf4 <__libc_init_array> /* Call the application's entry point.*/ bl main 800075e: f7ff fd61 bl 8000224

bx lr 8000762: 4770 bx lr ldr r3, =_sidata 8000764: 08004704 .word 0x08004704 ldr r0, =_sdata 8000768: 20000000 .word 0x20000000 ldr r3, =_edata 800076c: 20000024 .word 0x20000024 ldr r2, =_sbss 8000770: 20000024 .word 0x20000024 ldr r3, = _ebss 8000774: 20000590 .word 0x20000590 08000778 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000778: e7fe b.n 8000778 ... 0800077c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800077c: b580 push {r7, lr} 800077e: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000780: 4b08 ldr r3, [pc, #32] ; (80007a4 ) 8000782: 681b ldr r3, [r3, #0] 8000784: 4a07 ldr r2, [pc, #28] ; (80007a4 ) 8000786: f043 0310 orr.w r3, r3, #16 800078a: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800078c: 2003 movs r0, #3 800078e: f000 f92b bl 80009e8 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000792: 2000 movs r0, #0 8000794: f000 f808 bl 80007a8 /* Init the low level hardware */ HAL_MspInit(); 8000798: f7ff fec0 bl 800051c /* Return function status */ return HAL_OK; 800079c: 2300 movs r3, #0 } 800079e: 4618 mov r0, r3 80007a0: bd80 pop {r7, pc} 80007a2: bf00 nop 80007a4: 40022000 .word 0x40022000 080007a8 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80007a8: b580 push {r7, lr} 80007aa: b082 sub sp, #8 80007ac: af00 add r7, sp, #0 80007ae: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80007b0: 4b12 ldr r3, [pc, #72] ; (80007fc ) 80007b2: 681a ldr r2, [r3, #0] 80007b4: 4b12 ldr r3, [pc, #72] ; (8000800 ) 80007b6: 781b ldrb r3, [r3, #0] 80007b8: 4619 mov r1, r3 80007ba: f44f 737a mov.w r3, #1000 ; 0x3e8 80007be: fbb3 f3f1 udiv r3, r3, r1 80007c2: fbb2 f3f3 udiv r3, r2, r3 80007c6: 4618 mov r0, r3 80007c8: f000 f935 bl 8000a36 80007cc: 4603 mov r3, r0 80007ce: 2b00 cmp r3, #0 80007d0: d001 beq.n 80007d6 { return HAL_ERROR; 80007d2: 2301 movs r3, #1 80007d4: e00e b.n 80007f4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80007d6: 687b ldr r3, [r7, #4] 80007d8: 2b0f cmp r3, #15 80007da: d80a bhi.n 80007f2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80007dc: 2200 movs r2, #0 80007de: 6879 ldr r1, [r7, #4] 80007e0: f04f 30ff mov.w r0, #4294967295 80007e4: f000 f90b bl 80009fe uwTickPrio = TickPriority; 80007e8: 4a06 ldr r2, [pc, #24] ; (8000804 ) 80007ea: 687b ldr r3, [r7, #4] 80007ec: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80007ee: 2300 movs r3, #0 80007f0: e000 b.n 80007f4 return HAL_ERROR; 80007f2: 2301 movs r3, #1 } 80007f4: 4618 mov r0, r3 80007f6: 3708 adds r7, #8 80007f8: 46bd mov sp, r7 80007fa: bd80 pop {r7, pc} 80007fc: 20000000 .word 0x20000000 8000800: 20000008 .word 0x20000008 8000804: 20000004 .word 0x20000004 08000808 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000808: b480 push {r7} 800080a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800080c: 4b05 ldr r3, [pc, #20] ; (8000824 ) 800080e: 781b ldrb r3, [r3, #0] 8000810: 461a mov r2, r3 8000812: 4b05 ldr r3, [pc, #20] ; (8000828 ) 8000814: 681b ldr r3, [r3, #0] 8000816: 4413 add r3, r2 8000818: 4a03 ldr r2, [pc, #12] ; (8000828 ) 800081a: 6013 str r3, [r2, #0] } 800081c: bf00 nop 800081e: 46bd mov sp, r7 8000820: bc80 pop {r7} 8000822: 4770 bx lr 8000824: 20000008 .word 0x20000008 8000828: 200000f4 .word 0x200000f4 0800082c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800082c: b480 push {r7} 800082e: af00 add r7, sp, #0 return uwTick; 8000830: 4b02 ldr r3, [pc, #8] ; (800083c ) 8000832: 681b ldr r3, [r3, #0] } 8000834: 4618 mov r0, r3 8000836: 46bd mov sp, r7 8000838: bc80 pop {r7} 800083a: 4770 bx lr 800083c: 200000f4 .word 0x200000f4 08000840 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000840: b580 push {r7, lr} 8000842: b084 sub sp, #16 8000844: af00 add r7, sp, #0 8000846: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000848: f7ff fff0 bl 800082c 800084c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800084e: 687b ldr r3, [r7, #4] 8000850: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000852: 68fb ldr r3, [r7, #12] 8000854: f1b3 3fff cmp.w r3, #4294967295 8000858: d005 beq.n 8000866 { wait += (uint32_t)(uwTickFreq); 800085a: 4b0a ldr r3, [pc, #40] ; (8000884 ) 800085c: 781b ldrb r3, [r3, #0] 800085e: 461a mov r2, r3 8000860: 68fb ldr r3, [r7, #12] 8000862: 4413 add r3, r2 8000864: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8000866: bf00 nop 8000868: f7ff ffe0 bl 800082c 800086c: 4602 mov r2, r0 800086e: 68bb ldr r3, [r7, #8] 8000870: 1ad3 subs r3, r2, r3 8000872: 68fa ldr r2, [r7, #12] 8000874: 429a cmp r2, r3 8000876: d8f7 bhi.n 8000868 { } } 8000878: bf00 nop 800087a: bf00 nop 800087c: 3710 adds r7, #16 800087e: 46bd mov sp, r7 8000880: bd80 pop {r7, pc} 8000882: bf00 nop 8000884: 20000008 .word 0x20000008 08000888 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000888: b480 push {r7} 800088a: b085 sub sp, #20 800088c: af00 add r7, sp, #0 800088e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000890: 687b ldr r3, [r7, #4] 8000892: f003 0307 and.w r3, r3, #7 8000896: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000898: 4b0c ldr r3, [pc, #48] ; (80008cc <__NVIC_SetPriorityGrouping+0x44>) 800089a: 68db ldr r3, [r3, #12] 800089c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800089e: 68ba ldr r2, [r7, #8] 80008a0: f64f 03ff movw r3, #63743 ; 0xf8ff 80008a4: 4013 ands r3, r2 80008a6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80008a8: 68fb ldr r3, [r7, #12] 80008aa: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80008ac: 68bb ldr r3, [r7, #8] 80008ae: 4313 orrs r3, r2 reg_value = (reg_value | 80008b0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80008b4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80008b8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80008ba: 4a04 ldr r2, [pc, #16] ; (80008cc <__NVIC_SetPriorityGrouping+0x44>) 80008bc: 68bb ldr r3, [r7, #8] 80008be: 60d3 str r3, [r2, #12] } 80008c0: bf00 nop 80008c2: 3714 adds r7, #20 80008c4: 46bd mov sp, r7 80008c6: bc80 pop {r7} 80008c8: 4770 bx lr 80008ca: bf00 nop 80008cc: e000ed00 .word 0xe000ed00 080008d0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80008d0: b480 push {r7} 80008d2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80008d4: 4b04 ldr r3, [pc, #16] ; (80008e8 <__NVIC_GetPriorityGrouping+0x18>) 80008d6: 68db ldr r3, [r3, #12] 80008d8: 0a1b lsrs r3, r3, #8 80008da: f003 0307 and.w r3, r3, #7 } 80008de: 4618 mov r0, r3 80008e0: 46bd mov sp, r7 80008e2: bc80 pop {r7} 80008e4: 4770 bx lr 80008e6: bf00 nop 80008e8: e000ed00 .word 0xe000ed00 080008ec <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80008ec: b480 push {r7} 80008ee: b083 sub sp, #12 80008f0: af00 add r7, sp, #0 80008f2: 4603 mov r3, r0 80008f4: 6039 str r1, [r7, #0] 80008f6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80008f8: f997 3007 ldrsb.w r3, [r7, #7] 80008fc: 2b00 cmp r3, #0 80008fe: db0a blt.n 8000916 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000900: 683b ldr r3, [r7, #0] 8000902: b2da uxtb r2, r3 8000904: 490c ldr r1, [pc, #48] ; (8000938 <__NVIC_SetPriority+0x4c>) 8000906: f997 3007 ldrsb.w r3, [r7, #7] 800090a: 0112 lsls r2, r2, #4 800090c: b2d2 uxtb r2, r2 800090e: 440b add r3, r1 8000910: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000914: e00a b.n 800092c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000916: 683b ldr r3, [r7, #0] 8000918: b2da uxtb r2, r3 800091a: 4908 ldr r1, [pc, #32] ; (800093c <__NVIC_SetPriority+0x50>) 800091c: 79fb ldrb r3, [r7, #7] 800091e: f003 030f and.w r3, r3, #15 8000922: 3b04 subs r3, #4 8000924: 0112 lsls r2, r2, #4 8000926: b2d2 uxtb r2, r2 8000928: 440b add r3, r1 800092a: 761a strb r2, [r3, #24] } 800092c: bf00 nop 800092e: 370c adds r7, #12 8000930: 46bd mov sp, r7 8000932: bc80 pop {r7} 8000934: 4770 bx lr 8000936: bf00 nop 8000938: e000e100 .word 0xe000e100 800093c: e000ed00 .word 0xe000ed00 08000940 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000940: b480 push {r7} 8000942: b089 sub sp, #36 ; 0x24 8000944: af00 add r7, sp, #0 8000946: 60f8 str r0, [r7, #12] 8000948: 60b9 str r1, [r7, #8] 800094a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800094c: 68fb ldr r3, [r7, #12] 800094e: f003 0307 and.w r3, r3, #7 8000952: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000954: 69fb ldr r3, [r7, #28] 8000956: f1c3 0307 rsb r3, r3, #7 800095a: 2b04 cmp r3, #4 800095c: bf28 it cs 800095e: 2304 movcs r3, #4 8000960: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000962: 69fb ldr r3, [r7, #28] 8000964: 3304 adds r3, #4 8000966: 2b06 cmp r3, #6 8000968: d902 bls.n 8000970 800096a: 69fb ldr r3, [r7, #28] 800096c: 3b03 subs r3, #3 800096e: e000 b.n 8000972 8000970: 2300 movs r3, #0 8000972: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000974: f04f 32ff mov.w r2, #4294967295 8000978: 69bb ldr r3, [r7, #24] 800097a: fa02 f303 lsl.w r3, r2, r3 800097e: 43da mvns r2, r3 8000980: 68bb ldr r3, [r7, #8] 8000982: 401a ands r2, r3 8000984: 697b ldr r3, [r7, #20] 8000986: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000988: f04f 31ff mov.w r1, #4294967295 800098c: 697b ldr r3, [r7, #20] 800098e: fa01 f303 lsl.w r3, r1, r3 8000992: 43d9 mvns r1, r3 8000994: 687b ldr r3, [r7, #4] 8000996: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000998: 4313 orrs r3, r2 ); } 800099a: 4618 mov r0, r3 800099c: 3724 adds r7, #36 ; 0x24 800099e: 46bd mov sp, r7 80009a0: bc80 pop {r7} 80009a2: 4770 bx lr 080009a4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80009a4: b580 push {r7, lr} 80009a6: b082 sub sp, #8 80009a8: af00 add r7, sp, #0 80009aa: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80009ac: 687b ldr r3, [r7, #4] 80009ae: 3b01 subs r3, #1 80009b0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80009b4: d301 bcc.n 80009ba { return (1UL); /* Reload value impossible */ 80009b6: 2301 movs r3, #1 80009b8: e00f b.n 80009da } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80009ba: 4a0a ldr r2, [pc, #40] ; (80009e4 ) 80009bc: 687b ldr r3, [r7, #4] 80009be: 3b01 subs r3, #1 80009c0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80009c2: 210f movs r1, #15 80009c4: f04f 30ff mov.w r0, #4294967295 80009c8: f7ff ff90 bl 80008ec <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80009cc: 4b05 ldr r3, [pc, #20] ; (80009e4 ) 80009ce: 2200 movs r2, #0 80009d0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80009d2: 4b04 ldr r3, [pc, #16] ; (80009e4 ) 80009d4: 2207 movs r2, #7 80009d6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80009d8: 2300 movs r3, #0 } 80009da: 4618 mov r0, r3 80009dc: 3708 adds r7, #8 80009de: 46bd mov sp, r7 80009e0: bd80 pop {r7, pc} 80009e2: bf00 nop 80009e4: e000e010 .word 0xe000e010 080009e8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80009e8: b580 push {r7, lr} 80009ea: b082 sub sp, #8 80009ec: af00 add r7, sp, #0 80009ee: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80009f0: 6878 ldr r0, [r7, #4] 80009f2: f7ff ff49 bl 8000888 <__NVIC_SetPriorityGrouping> } 80009f6: bf00 nop 80009f8: 3708 adds r7, #8 80009fa: 46bd mov sp, r7 80009fc: bd80 pop {r7, pc} 080009fe : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80009fe: b580 push {r7, lr} 8000a00: b086 sub sp, #24 8000a02: af00 add r7, sp, #0 8000a04: 4603 mov r3, r0 8000a06: 60b9 str r1, [r7, #8] 8000a08: 607a str r2, [r7, #4] 8000a0a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000a0c: 2300 movs r3, #0 8000a0e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000a10: f7ff ff5e bl 80008d0 <__NVIC_GetPriorityGrouping> 8000a14: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000a16: 687a ldr r2, [r7, #4] 8000a18: 68b9 ldr r1, [r7, #8] 8000a1a: 6978 ldr r0, [r7, #20] 8000a1c: f7ff ff90 bl 8000940 8000a20: 4602 mov r2, r0 8000a22: f997 300f ldrsb.w r3, [r7, #15] 8000a26: 4611 mov r1, r2 8000a28: 4618 mov r0, r3 8000a2a: f7ff ff5f bl 80008ec <__NVIC_SetPriority> } 8000a2e: bf00 nop 8000a30: 3718 adds r7, #24 8000a32: 46bd mov sp, r7 8000a34: bd80 pop {r7, pc} 08000a36 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000a36: b580 push {r7, lr} 8000a38: b082 sub sp, #8 8000a3a: af00 add r7, sp, #0 8000a3c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000a3e: 6878 ldr r0, [r7, #4] 8000a40: f7ff ffb0 bl 80009a4 8000a44: 4603 mov r3, r0 } 8000a46: 4618 mov r0, r3 8000a48: 3708 adds r7, #8 8000a4a: 46bd mov sp, r7 8000a4c: bd80 pop {r7, pc} ... 08000a50 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000a50: b480 push {r7} 8000a52: b08b sub sp, #44 ; 0x2c 8000a54: af00 add r7, sp, #0 8000a56: 6078 str r0, [r7, #4] 8000a58: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000a5a: 2300 movs r3, #0 8000a5c: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8000a5e: 2300 movs r3, #0 8000a60: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000a62: e179 b.n 8000d58 { /* Get the IO position */ ioposition = (0x01uL << position); 8000a64: 2201 movs r2, #1 8000a66: 6a7b ldr r3, [r7, #36] ; 0x24 8000a68: fa02 f303 lsl.w r3, r2, r3 8000a6c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8000a6e: 683b ldr r3, [r7, #0] 8000a70: 681b ldr r3, [r3, #0] 8000a72: 69fa ldr r2, [r7, #28] 8000a74: 4013 ands r3, r2 8000a76: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8000a78: 69ba ldr r2, [r7, #24] 8000a7a: 69fb ldr r3, [r7, #28] 8000a7c: 429a cmp r2, r3 8000a7e: f040 8168 bne.w 8000d52 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8000a82: 683b ldr r3, [r7, #0] 8000a84: 685b ldr r3, [r3, #4] 8000a86: 4aa0 ldr r2, [pc, #640] ; (8000d08 ) 8000a88: 4293 cmp r3, r2 8000a8a: d05e beq.n 8000b4a 8000a8c: 4a9e ldr r2, [pc, #632] ; (8000d08 ) 8000a8e: 4293 cmp r3, r2 8000a90: d875 bhi.n 8000b7e 8000a92: 4a9e ldr r2, [pc, #632] ; (8000d0c ) 8000a94: 4293 cmp r3, r2 8000a96: d058 beq.n 8000b4a 8000a98: 4a9c ldr r2, [pc, #624] ; (8000d0c ) 8000a9a: 4293 cmp r3, r2 8000a9c: d86f bhi.n 8000b7e 8000a9e: 4a9c ldr r2, [pc, #624] ; (8000d10 ) 8000aa0: 4293 cmp r3, r2 8000aa2: d052 beq.n 8000b4a 8000aa4: 4a9a ldr r2, [pc, #616] ; (8000d10 ) 8000aa6: 4293 cmp r3, r2 8000aa8: d869 bhi.n 8000b7e 8000aaa: 4a9a ldr r2, [pc, #616] ; (8000d14 ) 8000aac: 4293 cmp r3, r2 8000aae: d04c beq.n 8000b4a 8000ab0: 4a98 ldr r2, [pc, #608] ; (8000d14 ) 8000ab2: 4293 cmp r3, r2 8000ab4: d863 bhi.n 8000b7e 8000ab6: 4a98 ldr r2, [pc, #608] ; (8000d18 ) 8000ab8: 4293 cmp r3, r2 8000aba: d046 beq.n 8000b4a 8000abc: 4a96 ldr r2, [pc, #600] ; (8000d18 ) 8000abe: 4293 cmp r3, r2 8000ac0: d85d bhi.n 8000b7e 8000ac2: 2b12 cmp r3, #18 8000ac4: d82a bhi.n 8000b1c 8000ac6: 2b12 cmp r3, #18 8000ac8: d859 bhi.n 8000b7e 8000aca: a201 add r2, pc, #4 ; (adr r2, 8000ad0 ) 8000acc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000ad0: 08000b4b .word 0x08000b4b 8000ad4: 08000b25 .word 0x08000b25 8000ad8: 08000b37 .word 0x08000b37 8000adc: 08000b79 .word 0x08000b79 8000ae0: 08000b7f .word 0x08000b7f 8000ae4: 08000b7f .word 0x08000b7f 8000ae8: 08000b7f .word 0x08000b7f 8000aec: 08000b7f .word 0x08000b7f 8000af0: 08000b7f .word 0x08000b7f 8000af4: 08000b7f .word 0x08000b7f 8000af8: 08000b7f .word 0x08000b7f 8000afc: 08000b7f .word 0x08000b7f 8000b00: 08000b7f .word 0x08000b7f 8000b04: 08000b7f .word 0x08000b7f 8000b08: 08000b7f .word 0x08000b7f 8000b0c: 08000b7f .word 0x08000b7f 8000b10: 08000b7f .word 0x08000b7f 8000b14: 08000b2d .word 0x08000b2d 8000b18: 08000b41 .word 0x08000b41 8000b1c: 4a7f ldr r2, [pc, #508] ; (8000d1c ) 8000b1e: 4293 cmp r3, r2 8000b20: d013 beq.n 8000b4a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8000b22: e02c b.n 8000b7e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8000b24: 683b ldr r3, [r7, #0] 8000b26: 68db ldr r3, [r3, #12] 8000b28: 623b str r3, [r7, #32] break; 8000b2a: e029 b.n 8000b80 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8000b2c: 683b ldr r3, [r7, #0] 8000b2e: 68db ldr r3, [r3, #12] 8000b30: 3304 adds r3, #4 8000b32: 623b str r3, [r7, #32] break; 8000b34: e024 b.n 8000b80 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8000b36: 683b ldr r3, [r7, #0] 8000b38: 68db ldr r3, [r3, #12] 8000b3a: 3308 adds r3, #8 8000b3c: 623b str r3, [r7, #32] break; 8000b3e: e01f b.n 8000b80 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8000b40: 683b ldr r3, [r7, #0] 8000b42: 68db ldr r3, [r3, #12] 8000b44: 330c adds r3, #12 8000b46: 623b str r3, [r7, #32] break; 8000b48: e01a b.n 8000b80 if (GPIO_Init->Pull == GPIO_NOPULL) 8000b4a: 683b ldr r3, [r7, #0] 8000b4c: 689b ldr r3, [r3, #8] 8000b4e: 2b00 cmp r3, #0 8000b50: d102 bne.n 8000b58 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8000b52: 2304 movs r3, #4 8000b54: 623b str r3, [r7, #32] break; 8000b56: e013 b.n 8000b80 else if (GPIO_Init->Pull == GPIO_PULLUP) 8000b58: 683b ldr r3, [r7, #0] 8000b5a: 689b ldr r3, [r3, #8] 8000b5c: 2b01 cmp r3, #1 8000b5e: d105 bne.n 8000b6c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8000b60: 2308 movs r3, #8 8000b62: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8000b64: 687b ldr r3, [r7, #4] 8000b66: 69fa ldr r2, [r7, #28] 8000b68: 611a str r2, [r3, #16] break; 8000b6a: e009 b.n 8000b80 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8000b6c: 2308 movs r3, #8 8000b6e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8000b70: 687b ldr r3, [r7, #4] 8000b72: 69fa ldr r2, [r7, #28] 8000b74: 615a str r2, [r3, #20] break; 8000b76: e003 b.n 8000b80 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8000b78: 2300 movs r3, #0 8000b7a: 623b str r3, [r7, #32] break; 8000b7c: e000 b.n 8000b80 break; 8000b7e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8000b80: 69bb ldr r3, [r7, #24] 8000b82: 2bff cmp r3, #255 ; 0xff 8000b84: d801 bhi.n 8000b8a 8000b86: 687b ldr r3, [r7, #4] 8000b88: e001 b.n 8000b8e 8000b8a: 687b ldr r3, [r7, #4] 8000b8c: 3304 adds r3, #4 8000b8e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8000b90: 69bb ldr r3, [r7, #24] 8000b92: 2bff cmp r3, #255 ; 0xff 8000b94: d802 bhi.n 8000b9c 8000b96: 6a7b ldr r3, [r7, #36] ; 0x24 8000b98: 009b lsls r3, r3, #2 8000b9a: e002 b.n 8000ba2 8000b9c: 6a7b ldr r3, [r7, #36] ; 0x24 8000b9e: 3b08 subs r3, #8 8000ba0: 009b lsls r3, r3, #2 8000ba2: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8000ba4: 697b ldr r3, [r7, #20] 8000ba6: 681a ldr r2, [r3, #0] 8000ba8: 210f movs r1, #15 8000baa: 693b ldr r3, [r7, #16] 8000bac: fa01 f303 lsl.w r3, r1, r3 8000bb0: 43db mvns r3, r3 8000bb2: 401a ands r2, r3 8000bb4: 6a39 ldr r1, [r7, #32] 8000bb6: 693b ldr r3, [r7, #16] 8000bb8: fa01 f303 lsl.w r3, r1, r3 8000bbc: 431a orrs r2, r3 8000bbe: 697b ldr r3, [r7, #20] 8000bc0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000bc2: 683b ldr r3, [r7, #0] 8000bc4: 685b ldr r3, [r3, #4] 8000bc6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000bca: 2b00 cmp r3, #0 8000bcc: f000 80c1 beq.w 8000d52 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000bd0: 4b53 ldr r3, [pc, #332] ; (8000d20 ) 8000bd2: 699b ldr r3, [r3, #24] 8000bd4: 4a52 ldr r2, [pc, #328] ; (8000d20 ) 8000bd6: f043 0301 orr.w r3, r3, #1 8000bda: 6193 str r3, [r2, #24] 8000bdc: 4b50 ldr r3, [pc, #320] ; (8000d20 ) 8000bde: 699b ldr r3, [r3, #24] 8000be0: f003 0301 and.w r3, r3, #1 8000be4: 60bb str r3, [r7, #8] 8000be6: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8000be8: 4a4e ldr r2, [pc, #312] ; (8000d24 ) 8000bea: 6a7b ldr r3, [r7, #36] ; 0x24 8000bec: 089b lsrs r3, r3, #2 8000bee: 3302 adds r3, #2 8000bf0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000bf4: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8000bf6: 6a7b ldr r3, [r7, #36] ; 0x24 8000bf8: f003 0303 and.w r3, r3, #3 8000bfc: 009b lsls r3, r3, #2 8000bfe: 220f movs r2, #15 8000c00: fa02 f303 lsl.w r3, r2, r3 8000c04: 43db mvns r3, r3 8000c06: 68fa ldr r2, [r7, #12] 8000c08: 4013 ands r3, r2 8000c0a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8000c0c: 687b ldr r3, [r7, #4] 8000c0e: 4a46 ldr r2, [pc, #280] ; (8000d28 ) 8000c10: 4293 cmp r3, r2 8000c12: d01f beq.n 8000c54 8000c14: 687b ldr r3, [r7, #4] 8000c16: 4a45 ldr r2, [pc, #276] ; (8000d2c ) 8000c18: 4293 cmp r3, r2 8000c1a: d019 beq.n 8000c50 8000c1c: 687b ldr r3, [r7, #4] 8000c1e: 4a44 ldr r2, [pc, #272] ; (8000d30 ) 8000c20: 4293 cmp r3, r2 8000c22: d013 beq.n 8000c4c 8000c24: 687b ldr r3, [r7, #4] 8000c26: 4a43 ldr r2, [pc, #268] ; (8000d34 ) 8000c28: 4293 cmp r3, r2 8000c2a: d00d beq.n 8000c48 8000c2c: 687b ldr r3, [r7, #4] 8000c2e: 4a42 ldr r2, [pc, #264] ; (8000d38 ) 8000c30: 4293 cmp r3, r2 8000c32: d007 beq.n 8000c44 8000c34: 687b ldr r3, [r7, #4] 8000c36: 4a41 ldr r2, [pc, #260] ; (8000d3c ) 8000c38: 4293 cmp r3, r2 8000c3a: d101 bne.n 8000c40 8000c3c: 2305 movs r3, #5 8000c3e: e00a b.n 8000c56 8000c40: 2306 movs r3, #6 8000c42: e008 b.n 8000c56 8000c44: 2304 movs r3, #4 8000c46: e006 b.n 8000c56 8000c48: 2303 movs r3, #3 8000c4a: e004 b.n 8000c56 8000c4c: 2302 movs r3, #2 8000c4e: e002 b.n 8000c56 8000c50: 2301 movs r3, #1 8000c52: e000 b.n 8000c56 8000c54: 2300 movs r3, #0 8000c56: 6a7a ldr r2, [r7, #36] ; 0x24 8000c58: f002 0203 and.w r2, r2, #3 8000c5c: 0092 lsls r2, r2, #2 8000c5e: 4093 lsls r3, r2 8000c60: 68fa ldr r2, [r7, #12] 8000c62: 4313 orrs r3, r2 8000c64: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8000c66: 492f ldr r1, [pc, #188] ; (8000d24 ) 8000c68: 6a7b ldr r3, [r7, #36] ; 0x24 8000c6a: 089b lsrs r3, r3, #2 8000c6c: 3302 adds r3, #2 8000c6e: 68fa ldr r2, [r7, #12] 8000c70: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000c74: 683b ldr r3, [r7, #0] 8000c76: 685b ldr r3, [r3, #4] 8000c78: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000c7c: 2b00 cmp r3, #0 8000c7e: d006 beq.n 8000c8e { SET_BIT(EXTI->IMR, iocurrent); 8000c80: 4b2f ldr r3, [pc, #188] ; (8000d40 ) 8000c82: 681a ldr r2, [r3, #0] 8000c84: 492e ldr r1, [pc, #184] ; (8000d40 ) 8000c86: 69bb ldr r3, [r7, #24] 8000c88: 4313 orrs r3, r2 8000c8a: 600b str r3, [r1, #0] 8000c8c: e006 b.n 8000c9c } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8000c8e: 4b2c ldr r3, [pc, #176] ; (8000d40 ) 8000c90: 681a ldr r2, [r3, #0] 8000c92: 69bb ldr r3, [r7, #24] 8000c94: 43db mvns r3, r3 8000c96: 492a ldr r1, [pc, #168] ; (8000d40 ) 8000c98: 4013 ands r3, r2 8000c9a: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000c9c: 683b ldr r3, [r7, #0] 8000c9e: 685b ldr r3, [r3, #4] 8000ca0: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000ca4: 2b00 cmp r3, #0 8000ca6: d006 beq.n 8000cb6 { SET_BIT(EXTI->EMR, iocurrent); 8000ca8: 4b25 ldr r3, [pc, #148] ; (8000d40 ) 8000caa: 685a ldr r2, [r3, #4] 8000cac: 4924 ldr r1, [pc, #144] ; (8000d40 ) 8000cae: 69bb ldr r3, [r7, #24] 8000cb0: 4313 orrs r3, r2 8000cb2: 604b str r3, [r1, #4] 8000cb4: e006 b.n 8000cc4 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8000cb6: 4b22 ldr r3, [pc, #136] ; (8000d40 ) 8000cb8: 685a ldr r2, [r3, #4] 8000cba: 69bb ldr r3, [r7, #24] 8000cbc: 43db mvns r3, r3 8000cbe: 4920 ldr r1, [pc, #128] ; (8000d40 ) 8000cc0: 4013 ands r3, r2 8000cc2: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000cc4: 683b ldr r3, [r7, #0] 8000cc6: 685b ldr r3, [r3, #4] 8000cc8: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000ccc: 2b00 cmp r3, #0 8000cce: d006 beq.n 8000cde { SET_BIT(EXTI->RTSR, iocurrent); 8000cd0: 4b1b ldr r3, [pc, #108] ; (8000d40 ) 8000cd2: 689a ldr r2, [r3, #8] 8000cd4: 491a ldr r1, [pc, #104] ; (8000d40 ) 8000cd6: 69bb ldr r3, [r7, #24] 8000cd8: 4313 orrs r3, r2 8000cda: 608b str r3, [r1, #8] 8000cdc: e006 b.n 8000cec } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8000cde: 4b18 ldr r3, [pc, #96] ; (8000d40 ) 8000ce0: 689a ldr r2, [r3, #8] 8000ce2: 69bb ldr r3, [r7, #24] 8000ce4: 43db mvns r3, r3 8000ce6: 4916 ldr r1, [pc, #88] ; (8000d40 ) 8000ce8: 4013 ands r3, r2 8000cea: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000cec: 683b ldr r3, [r7, #0] 8000cee: 685b ldr r3, [r3, #4] 8000cf0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000cf4: 2b00 cmp r3, #0 8000cf6: d025 beq.n 8000d44 { SET_BIT(EXTI->FTSR, iocurrent); 8000cf8: 4b11 ldr r3, [pc, #68] ; (8000d40 ) 8000cfa: 68da ldr r2, [r3, #12] 8000cfc: 4910 ldr r1, [pc, #64] ; (8000d40 ) 8000cfe: 69bb ldr r3, [r7, #24] 8000d00: 4313 orrs r3, r2 8000d02: 60cb str r3, [r1, #12] 8000d04: e025 b.n 8000d52 8000d06: bf00 nop 8000d08: 10320000 .word 0x10320000 8000d0c: 10310000 .word 0x10310000 8000d10: 10220000 .word 0x10220000 8000d14: 10210000 .word 0x10210000 8000d18: 10120000 .word 0x10120000 8000d1c: 10110000 .word 0x10110000 8000d20: 40021000 .word 0x40021000 8000d24: 40010000 .word 0x40010000 8000d28: 40010800 .word 0x40010800 8000d2c: 40010c00 .word 0x40010c00 8000d30: 40011000 .word 0x40011000 8000d34: 40011400 .word 0x40011400 8000d38: 40011800 .word 0x40011800 8000d3c: 40011c00 .word 0x40011c00 8000d40: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8000d44: 4b0b ldr r3, [pc, #44] ; (8000d74 ) 8000d46: 68da ldr r2, [r3, #12] 8000d48: 69bb ldr r3, [r7, #24] 8000d4a: 43db mvns r3, r3 8000d4c: 4909 ldr r1, [pc, #36] ; (8000d74 ) 8000d4e: 4013 ands r3, r2 8000d50: 60cb str r3, [r1, #12] } } } position++; 8000d52: 6a7b ldr r3, [r7, #36] ; 0x24 8000d54: 3301 adds r3, #1 8000d56: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8000d58: 683b ldr r3, [r7, #0] 8000d5a: 681a ldr r2, [r3, #0] 8000d5c: 6a7b ldr r3, [r7, #36] ; 0x24 8000d5e: fa22 f303 lsr.w r3, r2, r3 8000d62: 2b00 cmp r3, #0 8000d64: f47f ae7e bne.w 8000a64 } } 8000d68: bf00 nop 8000d6a: bf00 nop 8000d6c: 372c adds r7, #44 ; 0x2c 8000d6e: 46bd mov sp, r7 8000d70: bc80 pop {r7} 8000d72: 4770 bx lr 8000d74: 40010400 .word 0x40010400 08000d78 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8000d78: b480 push {r7} 8000d7a: b083 sub sp, #12 8000d7c: af00 add r7, sp, #0 8000d7e: 6078 str r0, [r7, #4] 8000d80: 460b mov r3, r1 8000d82: 807b strh r3, [r7, #2] 8000d84: 4613 mov r3, r2 8000d86: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8000d88: 787b ldrb r3, [r7, #1] 8000d8a: 2b00 cmp r3, #0 8000d8c: d003 beq.n 8000d96 { GPIOx->BSRR = GPIO_Pin; 8000d8e: 887a ldrh r2, [r7, #2] 8000d90: 687b ldr r3, [r7, #4] 8000d92: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8000d94: e003 b.n 8000d9e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8000d96: 887b ldrh r3, [r7, #2] 8000d98: 041a lsls r2, r3, #16 8000d9a: 687b ldr r3, [r7, #4] 8000d9c: 611a str r2, [r3, #16] } 8000d9e: bf00 nop 8000da0: 370c adds r7, #12 8000da2: 46bd mov sp, r7 8000da4: bc80 pop {r7} 8000da6: 4770 bx lr 08000da8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000da8: b580 push {r7, lr} 8000daa: b086 sub sp, #24 8000dac: af00 add r7, sp, #0 8000dae: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8000db0: 687b ldr r3, [r7, #4] 8000db2: 2b00 cmp r3, #0 8000db4: d101 bne.n 8000dba { return HAL_ERROR; 8000db6: 2301 movs r3, #1 8000db8: e26c b.n 8001294 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000dba: 687b ldr r3, [r7, #4] 8000dbc: 681b ldr r3, [r3, #0] 8000dbe: f003 0301 and.w r3, r3, #1 8000dc2: 2b00 cmp r3, #0 8000dc4: f000 8087 beq.w 8000ed6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000dc8: 4b92 ldr r3, [pc, #584] ; (8001014 ) 8000dca: 685b ldr r3, [r3, #4] 8000dcc: f003 030c and.w r3, r3, #12 8000dd0: 2b04 cmp r3, #4 8000dd2: d00c beq.n 8000dee || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000dd4: 4b8f ldr r3, [pc, #572] ; (8001014 ) 8000dd6: 685b ldr r3, [r3, #4] 8000dd8: f003 030c and.w r3, r3, #12 8000ddc: 2b08 cmp r3, #8 8000dde: d112 bne.n 8000e06 8000de0: 4b8c ldr r3, [pc, #560] ; (8001014 ) 8000de2: 685b ldr r3, [r3, #4] 8000de4: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000de8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000dec: d10b bne.n 8000e06 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000dee: 4b89 ldr r3, [pc, #548] ; (8001014 ) 8000df0: 681b ldr r3, [r3, #0] 8000df2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000df6: 2b00 cmp r3, #0 8000df8: d06c beq.n 8000ed4 8000dfa: 687b ldr r3, [r7, #4] 8000dfc: 685b ldr r3, [r3, #4] 8000dfe: 2b00 cmp r3, #0 8000e00: d168 bne.n 8000ed4 { return HAL_ERROR; 8000e02: 2301 movs r3, #1 8000e04: e246 b.n 8001294 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000e06: 687b ldr r3, [r7, #4] 8000e08: 685b ldr r3, [r3, #4] 8000e0a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000e0e: d106 bne.n 8000e1e 8000e10: 4b80 ldr r3, [pc, #512] ; (8001014 ) 8000e12: 681b ldr r3, [r3, #0] 8000e14: 4a7f ldr r2, [pc, #508] ; (8001014 ) 8000e16: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000e1a: 6013 str r3, [r2, #0] 8000e1c: e02e b.n 8000e7c 8000e1e: 687b ldr r3, [r7, #4] 8000e20: 685b ldr r3, [r3, #4] 8000e22: 2b00 cmp r3, #0 8000e24: d10c bne.n 8000e40 8000e26: 4b7b ldr r3, [pc, #492] ; (8001014 ) 8000e28: 681b ldr r3, [r3, #0] 8000e2a: 4a7a ldr r2, [pc, #488] ; (8001014 ) 8000e2c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000e30: 6013 str r3, [r2, #0] 8000e32: 4b78 ldr r3, [pc, #480] ; (8001014 ) 8000e34: 681b ldr r3, [r3, #0] 8000e36: 4a77 ldr r2, [pc, #476] ; (8001014 ) 8000e38: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000e3c: 6013 str r3, [r2, #0] 8000e3e: e01d b.n 8000e7c 8000e40: 687b ldr r3, [r7, #4] 8000e42: 685b ldr r3, [r3, #4] 8000e44: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000e48: d10c bne.n 8000e64 8000e4a: 4b72 ldr r3, [pc, #456] ; (8001014 ) 8000e4c: 681b ldr r3, [r3, #0] 8000e4e: 4a71 ldr r2, [pc, #452] ; (8001014 ) 8000e50: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000e54: 6013 str r3, [r2, #0] 8000e56: 4b6f ldr r3, [pc, #444] ; (8001014 ) 8000e58: 681b ldr r3, [r3, #0] 8000e5a: 4a6e ldr r2, [pc, #440] ; (8001014 ) 8000e5c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000e60: 6013 str r3, [r2, #0] 8000e62: e00b b.n 8000e7c 8000e64: 4b6b ldr r3, [pc, #428] ; (8001014 ) 8000e66: 681b ldr r3, [r3, #0] 8000e68: 4a6a ldr r2, [pc, #424] ; (8001014 ) 8000e6a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000e6e: 6013 str r3, [r2, #0] 8000e70: 4b68 ldr r3, [pc, #416] ; (8001014 ) 8000e72: 681b ldr r3, [r3, #0] 8000e74: 4a67 ldr r2, [pc, #412] ; (8001014 ) 8000e76: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000e7a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000e7c: 687b ldr r3, [r7, #4] 8000e7e: 685b ldr r3, [r3, #4] 8000e80: 2b00 cmp r3, #0 8000e82: d013 beq.n 8000eac { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e84: f7ff fcd2 bl 800082c 8000e88: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000e8a: e008 b.n 8000e9e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000e8c: f7ff fcce bl 800082c 8000e90: 4602 mov r2, r0 8000e92: 693b ldr r3, [r7, #16] 8000e94: 1ad3 subs r3, r2, r3 8000e96: 2b64 cmp r3, #100 ; 0x64 8000e98: d901 bls.n 8000e9e { return HAL_TIMEOUT; 8000e9a: 2303 movs r3, #3 8000e9c: e1fa b.n 8001294 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000e9e: 4b5d ldr r3, [pc, #372] ; (8001014 ) 8000ea0: 681b ldr r3, [r3, #0] 8000ea2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000ea6: 2b00 cmp r3, #0 8000ea8: d0f0 beq.n 8000e8c 8000eaa: e014 b.n 8000ed6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000eac: f7ff fcbe bl 800082c 8000eb0: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000eb2: e008 b.n 8000ec6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000eb4: f7ff fcba bl 800082c 8000eb8: 4602 mov r2, r0 8000eba: 693b ldr r3, [r7, #16] 8000ebc: 1ad3 subs r3, r2, r3 8000ebe: 2b64 cmp r3, #100 ; 0x64 8000ec0: d901 bls.n 8000ec6 { return HAL_TIMEOUT; 8000ec2: 2303 movs r3, #3 8000ec4: e1e6 b.n 8001294 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000ec6: 4b53 ldr r3, [pc, #332] ; (8001014 ) 8000ec8: 681b ldr r3, [r3, #0] 8000eca: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000ece: 2b00 cmp r3, #0 8000ed0: d1f0 bne.n 8000eb4 8000ed2: e000 b.n 8000ed6 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000ed4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000ed6: 687b ldr r3, [r7, #4] 8000ed8: 681b ldr r3, [r3, #0] 8000eda: f003 0302 and.w r3, r3, #2 8000ede: 2b00 cmp r3, #0 8000ee0: d063 beq.n 8000faa /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000ee2: 4b4c ldr r3, [pc, #304] ; (8001014 ) 8000ee4: 685b ldr r3, [r3, #4] 8000ee6: f003 030c and.w r3, r3, #12 8000eea: 2b00 cmp r3, #0 8000eec: d00b beq.n 8000f06 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000eee: 4b49 ldr r3, [pc, #292] ; (8001014 ) 8000ef0: 685b ldr r3, [r3, #4] 8000ef2: f003 030c and.w r3, r3, #12 8000ef6: 2b08 cmp r3, #8 8000ef8: d11c bne.n 8000f34 8000efa: 4b46 ldr r3, [pc, #280] ; (8001014 ) 8000efc: 685b ldr r3, [r3, #4] 8000efe: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000f02: 2b00 cmp r3, #0 8000f04: d116 bne.n 8000f34 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000f06: 4b43 ldr r3, [pc, #268] ; (8001014 ) 8000f08: 681b ldr r3, [r3, #0] 8000f0a: f003 0302 and.w r3, r3, #2 8000f0e: 2b00 cmp r3, #0 8000f10: d005 beq.n 8000f1e 8000f12: 687b ldr r3, [r7, #4] 8000f14: 691b ldr r3, [r3, #16] 8000f16: 2b01 cmp r3, #1 8000f18: d001 beq.n 8000f1e { return HAL_ERROR; 8000f1a: 2301 movs r3, #1 8000f1c: e1ba b.n 8001294 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000f1e: 4b3d ldr r3, [pc, #244] ; (8001014 ) 8000f20: 681b ldr r3, [r3, #0] 8000f22: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000f26: 687b ldr r3, [r7, #4] 8000f28: 695b ldr r3, [r3, #20] 8000f2a: 00db lsls r3, r3, #3 8000f2c: 4939 ldr r1, [pc, #228] ; (8001014 ) 8000f2e: 4313 orrs r3, r2 8000f30: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000f32: e03a b.n 8000faa } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000f34: 687b ldr r3, [r7, #4] 8000f36: 691b ldr r3, [r3, #16] 8000f38: 2b00 cmp r3, #0 8000f3a: d020 beq.n 8000f7e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000f3c: 4b36 ldr r3, [pc, #216] ; (8001018 ) 8000f3e: 2201 movs r2, #1 8000f40: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f42: f7ff fc73 bl 800082c 8000f46: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000f48: e008 b.n 8000f5c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000f4a: f7ff fc6f bl 800082c 8000f4e: 4602 mov r2, r0 8000f50: 693b ldr r3, [r7, #16] 8000f52: 1ad3 subs r3, r2, r3 8000f54: 2b02 cmp r3, #2 8000f56: d901 bls.n 8000f5c { return HAL_TIMEOUT; 8000f58: 2303 movs r3, #3 8000f5a: e19b b.n 8001294 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000f5c: 4b2d ldr r3, [pc, #180] ; (8001014 ) 8000f5e: 681b ldr r3, [r3, #0] 8000f60: f003 0302 and.w r3, r3, #2 8000f64: 2b00 cmp r3, #0 8000f66: d0f0 beq.n 8000f4a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000f68: 4b2a ldr r3, [pc, #168] ; (8001014 ) 8000f6a: 681b ldr r3, [r3, #0] 8000f6c: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000f70: 687b ldr r3, [r7, #4] 8000f72: 695b ldr r3, [r3, #20] 8000f74: 00db lsls r3, r3, #3 8000f76: 4927 ldr r1, [pc, #156] ; (8001014 ) 8000f78: 4313 orrs r3, r2 8000f7a: 600b str r3, [r1, #0] 8000f7c: e015 b.n 8000faa } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000f7e: 4b26 ldr r3, [pc, #152] ; (8001018 ) 8000f80: 2200 movs r2, #0 8000f82: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f84: f7ff fc52 bl 800082c 8000f88: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000f8a: e008 b.n 8000f9e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000f8c: f7ff fc4e bl 800082c 8000f90: 4602 mov r2, r0 8000f92: 693b ldr r3, [r7, #16] 8000f94: 1ad3 subs r3, r2, r3 8000f96: 2b02 cmp r3, #2 8000f98: d901 bls.n 8000f9e { return HAL_TIMEOUT; 8000f9a: 2303 movs r3, #3 8000f9c: e17a b.n 8001294 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000f9e: 4b1d ldr r3, [pc, #116] ; (8001014 ) 8000fa0: 681b ldr r3, [r3, #0] 8000fa2: f003 0302 and.w r3, r3, #2 8000fa6: 2b00 cmp r3, #0 8000fa8: d1f0 bne.n 8000f8c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000faa: 687b ldr r3, [r7, #4] 8000fac: 681b ldr r3, [r3, #0] 8000fae: f003 0308 and.w r3, r3, #8 8000fb2: 2b00 cmp r3, #0 8000fb4: d03a beq.n 800102c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000fb6: 687b ldr r3, [r7, #4] 8000fb8: 699b ldr r3, [r3, #24] 8000fba: 2b00 cmp r3, #0 8000fbc: d019 beq.n 8000ff2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000fbe: 4b17 ldr r3, [pc, #92] ; (800101c ) 8000fc0: 2201 movs r2, #1 8000fc2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000fc4: f7ff fc32 bl 800082c 8000fc8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000fca: e008 b.n 8000fde { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000fcc: f7ff fc2e bl 800082c 8000fd0: 4602 mov r2, r0 8000fd2: 693b ldr r3, [r7, #16] 8000fd4: 1ad3 subs r3, r2, r3 8000fd6: 2b02 cmp r3, #2 8000fd8: d901 bls.n 8000fde { return HAL_TIMEOUT; 8000fda: 2303 movs r3, #3 8000fdc: e15a b.n 8001294 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000fde: 4b0d ldr r3, [pc, #52] ; (8001014 ) 8000fe0: 6a5b ldr r3, [r3, #36] ; 0x24 8000fe2: f003 0302 and.w r3, r3, #2 8000fe6: 2b00 cmp r3, #0 8000fe8: d0f0 beq.n 8000fcc } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8000fea: 2001 movs r0, #1 8000fec: f000 faa6 bl 800153c 8000ff0: e01c b.n 800102c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000ff2: 4b0a ldr r3, [pc, #40] ; (800101c ) 8000ff4: 2200 movs r2, #0 8000ff6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ff8: f7ff fc18 bl 800082c 8000ffc: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000ffe: e00f b.n 8001020 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001000: f7ff fc14 bl 800082c 8001004: 4602 mov r2, r0 8001006: 693b ldr r3, [r7, #16] 8001008: 1ad3 subs r3, r2, r3 800100a: 2b02 cmp r3, #2 800100c: d908 bls.n 8001020 { return HAL_TIMEOUT; 800100e: 2303 movs r3, #3 8001010: e140 b.n 8001294 8001012: bf00 nop 8001014: 40021000 .word 0x40021000 8001018: 42420000 .word 0x42420000 800101c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001020: 4b9e ldr r3, [pc, #632] ; (800129c ) 8001022: 6a5b ldr r3, [r3, #36] ; 0x24 8001024: f003 0302 and.w r3, r3, #2 8001028: 2b00 cmp r3, #0 800102a: d1e9 bne.n 8001000 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800102c: 687b ldr r3, [r7, #4] 800102e: 681b ldr r3, [r3, #0] 8001030: f003 0304 and.w r3, r3, #4 8001034: 2b00 cmp r3, #0 8001036: f000 80a6 beq.w 8001186 { FlagStatus pwrclkchanged = RESET; 800103a: 2300 movs r3, #0 800103c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800103e: 4b97 ldr r3, [pc, #604] ; (800129c