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ff4edffc46f533402bff1ddb8e071ba15f388c54
smartbooks/103ze/Debug/103ze_code.list
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无闻风 ff4edffc46 103ze下的开发环境 
主要为内核开发

Signed-off-by: 无闻风 <53944749+wuwenfengmi1998@users.noreply.github.com>
2021-03-11 18:37:42 +08:00

2581 lines
97 KiB
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103ze_code.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001e4 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00000cec 080001e4 080001e4 000101e4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000020 08000ed0 08000ed0 00010ed0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08000ef0 08000ef0 0002000c 2**0
CONTENTS
4 .ARM 00000000 08000ef0 08000ef0 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08000ef0 08000ef0 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08000ef0 08000ef0 00010ef0 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08000ef4 08000ef4 00010ef4 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08000ef8 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000020 2000000c 08000f04 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000002c 08000f04 0002002c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 000028a8 00000000 00000000 00020035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00000c6a 00000000 00000000 000228dd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000378 00000000 00000000 00023548 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000300 00000000 00000000 000238c0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00017679 00000000 00000000 00023bc0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00003bac 00000000 00000000 0003b239 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008957f 00000000 00000000 0003ede5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 000c8364 2**0
CONTENTS, READONLY
20 .debug_frame 00000be8 00000000 00000000 000c83b8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001e4 <__do_global_dtors_aux>:
80001e4: b510 push {r4, lr}
80001e6: 4c05 ldr r4, [pc, #20] ; (80001fc <__do_global_dtors_aux+0x18>)
80001e8: 7823 ldrb r3, [r4, #0]
80001ea: b933 cbnz r3, 80001fa <__do_global_dtors_aux+0x16>
80001ec: 4b04 ldr r3, [pc, #16] ; (8000200 <__do_global_dtors_aux+0x1c>)
80001ee: b113 cbz r3, 80001f6 <__do_global_dtors_aux+0x12>
80001f0: 4804 ldr r0, [pc, #16] ; (8000204 <__do_global_dtors_aux+0x20>)
80001f2: f3af 8000 nop.w
80001f6: 2301 movs r3, #1
80001f8: 7023 strb r3, [r4, #0]
80001fa: bd10 pop {r4, pc}
80001fc: 2000000c .word 0x2000000c
8000200: 00000000 .word 0x00000000
8000204: 08000eb8 .word 0x08000eb8
08000208 <frame_dummy>:
8000208: b508 push {r3, lr}
800020a: 4b03 ldr r3, [pc, #12] ; (8000218 <frame_dummy+0x10>)
800020c: b11b cbz r3, 8000216 <frame_dummy+0xe>
800020e: 4903 ldr r1, [pc, #12] ; (800021c <frame_dummy+0x14>)
8000210: 4803 ldr r0, [pc, #12] ; (8000220 <frame_dummy+0x18>)
8000212: f3af 8000 nop.w
8000216: bd08 pop {r3, pc}
8000218: 00000000 .word 0x00000000
800021c: 20000010 .word 0x20000010
8000220: 08000eb8 .word 0x08000eb8
08000224 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000224: b580 push {r7, lr}
8000226: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000228: f000 f8ec bl 8000404 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800022c: f000 f803 bl 8000236 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000230: f000 f846 bl 80002c0 <MX_GPIO_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000234: e7fe b.n 8000234 <main+0x10>
08000236 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000236: b580 push {r7, lr}
8000238: b090 sub sp, #64 ; 0x40
800023a: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800023c: f107 0318 add.w r3, r7, #24
8000240: 2228 movs r2, #40 ; 0x28
8000242: 2100 movs r1, #0
8000244: 4618 mov r0, r3
8000246: f000 fe2f bl 8000ea8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800024a: 1d3b adds r3, r7, #4
800024c: 2200 movs r2, #0
800024e: 601a str r2, [r3, #0]
8000250: 605a str r2, [r3, #4]
8000252: 609a str r2, [r3, #8]
8000254: 60da str r2, [r3, #12]
8000256: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000258: 2301 movs r3, #1
800025a: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
800025c: f44f 3380 mov.w r3, #65536 ; 0x10000
8000260: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
8000262: 2300 movs r3, #0
8000264: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000266: 2301 movs r3, #1
8000268: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800026a: 2302 movs r3, #2
800026c: 637b str r3, [r7, #52] ; 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
800026e: f44f 3380 mov.w r3, #65536 ; 0x10000
8000272: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
8000274: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
8000278: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800027a: f107 0318 add.w r3, r7, #24
800027e: 4618 mov r0, r3
8000280: f000 fa06 bl 8000690 <HAL_RCC_OscConfig>
8000284: 4603 mov r3, r0
8000286: 2b00 cmp r3, #0
8000288: d001 beq.n 800028e <SystemClock_Config+0x58>
{
Error_Handler();
800028a: f000 f82f bl 80002ec <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800028e: 230f movs r3, #15
8000290: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000292: 2302 movs r3, #2
8000294: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000296: 2300 movs r3, #0
8000298: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
800029a: f44f 6380 mov.w r3, #1024 ; 0x400
800029e: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80002a0: 2300 movs r3, #0
80002a2: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80002a4: 1d3b adds r3, r7, #4
80002a6: 2102 movs r1, #2
80002a8: 4618 mov r0, r3
80002aa: f000 fc71 bl 8000b90 <HAL_RCC_ClockConfig>
80002ae: 4603 mov r3, r0
80002b0: 2b00 cmp r3, #0
80002b2: d001 beq.n 80002b8 <SystemClock_Config+0x82>
{
Error_Handler();
80002b4: f000 f81a bl 80002ec <Error_Handler>
}
}
80002b8: bf00 nop
80002ba: 3740 adds r7, #64 ; 0x40
80002bc: 46bd mov sp, r7
80002be: bd80 pop {r7, pc}
080002c0 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80002c0: b480 push {r7}
80002c2: b083 sub sp, #12
80002c4: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
80002c6: 4b08 ldr r3, [pc, #32] ; (80002e8 <MX_GPIO_Init+0x28>)
80002c8: 699b ldr r3, [r3, #24]
80002ca: 4a07 ldr r2, [pc, #28] ; (80002e8 <MX_GPIO_Init+0x28>)
80002cc: f043 0304 orr.w r3, r3, #4
80002d0: 6193 str r3, [r2, #24]
80002d2: 4b05 ldr r3, [pc, #20] ; (80002e8 <MX_GPIO_Init+0x28>)
80002d4: 699b ldr r3, [r3, #24]
80002d6: f003 0304 and.w r3, r3, #4
80002da: 607b str r3, [r7, #4]
80002dc: 687b ldr r3, [r7, #4]
}
80002de: bf00 nop
80002e0: 370c adds r7, #12
80002e2: 46bd mov sp, r7
80002e4: bc80 pop {r7}
80002e6: 4770 bx lr
80002e8: 40021000 .word 0x40021000
080002ec <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80002ec: b480 push {r7}
80002ee: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80002f0: b672 cpsid i
}
80002f2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80002f4: e7fe b.n 80002f4 <Error_Handler+0x8>
...
080002f8 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80002f8: b480 push {r7}
80002fa: b085 sub sp, #20
80002fc: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
80002fe: 4b15 ldr r3, [pc, #84] ; (8000354 <HAL_MspInit+0x5c>)
8000300: 699b ldr r3, [r3, #24]
8000302: 4a14 ldr r2, [pc, #80] ; (8000354 <HAL_MspInit+0x5c>)
8000304: f043 0301 orr.w r3, r3, #1
8000308: 6193 str r3, [r2, #24]
800030a: 4b12 ldr r3, [pc, #72] ; (8000354 <HAL_MspInit+0x5c>)
800030c: 699b ldr r3, [r3, #24]
800030e: f003 0301 and.w r3, r3, #1
8000312: 60bb str r3, [r7, #8]
8000314: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8000316: 4b0f ldr r3, [pc, #60] ; (8000354 <HAL_MspInit+0x5c>)
8000318: 69db ldr r3, [r3, #28]
800031a: 4a0e ldr r2, [pc, #56] ; (8000354 <HAL_MspInit+0x5c>)
800031c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000320: 61d3 str r3, [r2, #28]
8000322: 4b0c ldr r3, [pc, #48] ; (8000354 <HAL_MspInit+0x5c>)
8000324: 69db ldr r3, [r3, #28]
8000326: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800032a: 607b str r3, [r7, #4]
800032c: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
800032e: 4b0a ldr r3, [pc, #40] ; (8000358 <HAL_MspInit+0x60>)
8000330: 685b ldr r3, [r3, #4]
8000332: 60fb str r3, [r7, #12]
8000334: 68fb ldr r3, [r7, #12]
8000336: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
800033a: 60fb str r3, [r7, #12]
800033c: 68fb ldr r3, [r7, #12]
800033e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8000342: 60fb str r3, [r7, #12]
8000344: 4a04 ldr r2, [pc, #16] ; (8000358 <HAL_MspInit+0x60>)
8000346: 68fb ldr r3, [r7, #12]
8000348: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800034a: bf00 nop
800034c: 3714 adds r7, #20
800034e: 46bd mov sp, r7
8000350: bc80 pop {r7}
8000352: 4770 bx lr
8000354: 40021000 .word 0x40021000
8000358: 40010000 .word 0x40010000
0800035c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800035c: b480 push {r7}
800035e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000360: e7fe b.n 8000360 <NMI_Handler+0x4>
08000362 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000362: b480 push {r7}
8000364: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000366: e7fe b.n 8000366 <HardFault_Handler+0x4>
08000368 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000368: b480 push {r7}
800036a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
800036c: e7fe b.n 800036c <MemManage_Handler+0x4>
0800036e <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800036e: b480 push {r7}
8000370: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000372: e7fe b.n 8000372 <BusFault_Handler+0x4>
08000374 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000374: b480 push {r7}
8000376: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000378: e7fe b.n 8000378 <UsageFault_Handler+0x4>
0800037a <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800037a: b480 push {r7}
800037c: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800037e: bf00 nop
8000380: 46bd mov sp, r7
8000382: bc80 pop {r7}
8000384: 4770 bx lr
08000386 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000386: b480 push {r7}
8000388: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800038a: bf00 nop
800038c: 46bd mov sp, r7
800038e: bc80 pop {r7}
8000390: 4770 bx lr
08000392 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000392: b480 push {r7}
8000394: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000396: bf00 nop
8000398: 46bd mov sp, r7
800039a: bc80 pop {r7}
800039c: 4770 bx lr
0800039e <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800039e: b580 push {r7, lr}
80003a0: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80003a2: f000 f875 bl 8000490 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80003a6: bf00 nop
80003a8: bd80 pop {r7, pc}
080003aa <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80003aa: b480 push {r7}
80003ac: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80003ae: bf00 nop
80003b0: 46bd mov sp, r7
80003b2: bc80 pop {r7}
80003b4: 4770 bx lr
...
080003b8 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
80003b8: 2100 movs r1, #0
b LoopCopyDataInit
80003ba: e003 b.n 80003c4 <LoopCopyDataInit>
080003bc <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
80003bc: 4b0b ldr r3, [pc, #44] ; (80003ec <LoopFillZerobss+0x14>)
ldr r3, [r3, r1]
80003be: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
80003c0: 5043 str r3, [r0, r1]
adds r1, r1, #4
80003c2: 3104 adds r1, #4
080003c4 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
80003c4: 480a ldr r0, [pc, #40] ; (80003f0 <LoopFillZerobss+0x18>)
ldr r3, =_edata
80003c6: 4b0b ldr r3, [pc, #44] ; (80003f4 <LoopFillZerobss+0x1c>)
adds r2, r0, r1
80003c8: 1842 adds r2, r0, r1
cmp r2, r3
80003ca: 429a cmp r2, r3
bcc CopyDataInit
80003cc: d3f6 bcc.n 80003bc <CopyDataInit>
ldr r2, =_sbss
80003ce: 4a0a ldr r2, [pc, #40] ; (80003f8 <LoopFillZerobss+0x20>)
b LoopFillZerobss
80003d0: e002 b.n 80003d8 <LoopFillZerobss>
080003d2 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
80003d2: 2300 movs r3, #0
str r3, [r2], #4
80003d4: f842 3b04 str.w r3, [r2], #4
080003d8 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
80003d8: 4b08 ldr r3, [pc, #32] ; (80003fc <LoopFillZerobss+0x24>)
cmp r2, r3
80003da: 429a cmp r2, r3
bcc FillZerobss
80003dc: d3f9 bcc.n 80003d2 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80003de: f7ff ffe4 bl 80003aa <SystemInit>
/* Call static constructors */
bl __libc_init_array
80003e2: f000 fd3d bl 8000e60 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80003e6: f7ff ff1d bl 8000224 <main>
bx lr
80003ea: 4770 bx lr
ldr r3, =_sidata
80003ec: 08000ef8 .word 0x08000ef8
ldr r0, =_sdata
80003f0: 20000000 .word 0x20000000
ldr r3, =_edata
80003f4: 2000000c .word 0x2000000c
ldr r2, =_sbss
80003f8: 2000000c .word 0x2000000c
ldr r3, = _ebss
80003fc: 2000002c .word 0x2000002c
08000400 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000400: e7fe b.n 8000400 <ADC1_2_IRQHandler>
...
08000404 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000404: b580 push {r7, lr}
8000406: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000408: 4b08 ldr r3, [pc, #32] ; (800042c <HAL_Init+0x28>)
800040a: 681b ldr r3, [r3, #0]
800040c: 4a07 ldr r2, [pc, #28] ; (800042c <HAL_Init+0x28>)
800040e: f043 0310 orr.w r3, r3, #16
8000412: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000414: 2003 movs r0, #3
8000416: f000 f907 bl 8000628 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
800041a: 2000 movs r0, #0
800041c: f000 f808 bl 8000430 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000420: f7ff ff6a bl 80002f8 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000424: 2300 movs r3, #0
}
8000426: 4618 mov r0, r3
8000428: bd80 pop {r7, pc}
800042a: bf00 nop
800042c: 40022000 .word 0x40022000
08000430 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000430: b580 push {r7, lr}
8000432: b082 sub sp, #8
8000434: af00 add r7, sp, #0
8000436: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000438: 4b12 ldr r3, [pc, #72] ; (8000484 <HAL_InitTick+0x54>)
800043a: 681a ldr r2, [r3, #0]
800043c: 4b12 ldr r3, [pc, #72] ; (8000488 <HAL_InitTick+0x58>)
800043e: 781b ldrb r3, [r3, #0]
8000440: 4619 mov r1, r3
8000442: f44f 737a mov.w r3, #1000 ; 0x3e8
8000446: fbb3 f3f1 udiv r3, r3, r1
800044a: fbb2 f3f3 udiv r3, r2, r3
800044e: 4618 mov r0, r3
8000450: f000 f911 bl 8000676 <HAL_SYSTICK_Config>
8000454: 4603 mov r3, r0
8000456: 2b00 cmp r3, #0
8000458: d001 beq.n 800045e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800045a: 2301 movs r3, #1
800045c: e00e b.n 800047c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800045e: 687b ldr r3, [r7, #4]
8000460: 2b0f cmp r3, #15
8000462: d80a bhi.n 800047a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000464: 2200 movs r2, #0
8000466: 6879 ldr r1, [r7, #4]
8000468: f04f 30ff mov.w r0, #4294967295
800046c: f000 f8e7 bl 800063e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000470: 4a06 ldr r2, [pc, #24] ; (800048c <HAL_InitTick+0x5c>)
8000472: 687b ldr r3, [r7, #4]
8000474: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000476: 2300 movs r3, #0
8000478: e000 b.n 800047c <HAL_InitTick+0x4c>
return HAL_ERROR;
800047a: 2301 movs r3, #1
}
800047c: 4618 mov r0, r3
800047e: 3708 adds r7, #8
8000480: 46bd mov sp, r7
8000482: bd80 pop {r7, pc}
8000484: 20000000 .word 0x20000000
8000488: 20000008 .word 0x20000008
800048c: 20000004 .word 0x20000004
08000490 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000490: b480 push {r7}
8000492: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000494: 4b05 ldr r3, [pc, #20] ; (80004ac <HAL_IncTick+0x1c>)
8000496: 781b ldrb r3, [r3, #0]
8000498: 461a mov r2, r3
800049a: 4b05 ldr r3, [pc, #20] ; (80004b0 <HAL_IncTick+0x20>)
800049c: 681b ldr r3, [r3, #0]
800049e: 4413 add r3, r2
80004a0: 4a03 ldr r2, [pc, #12] ; (80004b0 <HAL_IncTick+0x20>)
80004a2: 6013 str r3, [r2, #0]
}
80004a4: bf00 nop
80004a6: 46bd mov sp, r7
80004a8: bc80 pop {r7}
80004aa: 4770 bx lr
80004ac: 20000008 .word 0x20000008
80004b0: 20000028 .word 0x20000028
080004b4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80004b4: b480 push {r7}
80004b6: af00 add r7, sp, #0
return uwTick;
80004b8: 4b02 ldr r3, [pc, #8] ; (80004c4 <HAL_GetTick+0x10>)
80004ba: 681b ldr r3, [r3, #0]
}
80004bc: 4618 mov r0, r3
80004be: 46bd mov sp, r7
80004c0: bc80 pop {r7}
80004c2: 4770 bx lr
80004c4: 20000028 .word 0x20000028
080004c8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80004c8: b480 push {r7}
80004ca: b085 sub sp, #20
80004cc: af00 add r7, sp, #0
80004ce: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80004d0: 687b ldr r3, [r7, #4]
80004d2: f003 0307 and.w r3, r3, #7
80004d6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80004d8: 4b0c ldr r3, [pc, #48] ; (800050c <__NVIC_SetPriorityGrouping+0x44>)
80004da: 68db ldr r3, [r3, #12]
80004dc: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80004de: 68ba ldr r2, [r7, #8]
80004e0: f64f 03ff movw r3, #63743 ; 0xf8ff
80004e4: 4013 ands r3, r2
80004e6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80004e8: 68fb ldr r3, [r7, #12]
80004ea: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80004ec: 68bb ldr r3, [r7, #8]
80004ee: 4313 orrs r3, r2
reg_value = (reg_value |
80004f0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80004f4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80004f8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80004fa: 4a04 ldr r2, [pc, #16] ; (800050c <__NVIC_SetPriorityGrouping+0x44>)
80004fc: 68bb ldr r3, [r7, #8]
80004fe: 60d3 str r3, [r2, #12]
}
8000500: bf00 nop
8000502: 3714 adds r7, #20
8000504: 46bd mov sp, r7
8000506: bc80 pop {r7}
8000508: 4770 bx lr
800050a: bf00 nop
800050c: e000ed00 .word 0xe000ed00
08000510 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000510: b480 push {r7}
8000512: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000514: 4b04 ldr r3, [pc, #16] ; (8000528 <__NVIC_GetPriorityGrouping+0x18>)
8000516: 68db ldr r3, [r3, #12]
8000518: 0a1b lsrs r3, r3, #8
800051a: f003 0307 and.w r3, r3, #7
}
800051e: 4618 mov r0, r3
8000520: 46bd mov sp, r7
8000522: bc80 pop {r7}
8000524: 4770 bx lr
8000526: bf00 nop
8000528: e000ed00 .word 0xe000ed00
0800052c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
800052c: b480 push {r7}
800052e: b083 sub sp, #12
8000530: af00 add r7, sp, #0
8000532: 4603 mov r3, r0
8000534: 6039 str r1, [r7, #0]
8000536: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000538: f997 3007 ldrsb.w r3, [r7, #7]
800053c: 2b00 cmp r3, #0
800053e: db0a blt.n 8000556 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000540: 683b ldr r3, [r7, #0]
8000542: b2da uxtb r2, r3
8000544: 490c ldr r1, [pc, #48] ; (8000578 <__NVIC_SetPriority+0x4c>)
8000546: f997 3007 ldrsb.w r3, [r7, #7]
800054a: 0112 lsls r2, r2, #4
800054c: b2d2 uxtb r2, r2
800054e: 440b add r3, r1
8000550: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000554: e00a b.n 800056c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000556: 683b ldr r3, [r7, #0]
8000558: b2da uxtb r2, r3
800055a: 4908 ldr r1, [pc, #32] ; (800057c <__NVIC_SetPriority+0x50>)
800055c: 79fb ldrb r3, [r7, #7]
800055e: f003 030f and.w r3, r3, #15
8000562: 3b04 subs r3, #4
8000564: 0112 lsls r2, r2, #4
8000566: b2d2 uxtb r2, r2
8000568: 440b add r3, r1
800056a: 761a strb r2, [r3, #24]
}
800056c: bf00 nop
800056e: 370c adds r7, #12
8000570: 46bd mov sp, r7
8000572: bc80 pop {r7}
8000574: 4770 bx lr
8000576: bf00 nop
8000578: e000e100 .word 0xe000e100
800057c: e000ed00 .word 0xe000ed00
08000580 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000580: b480 push {r7}
8000582: b089 sub sp, #36 ; 0x24
8000584: af00 add r7, sp, #0
8000586: 60f8 str r0, [r7, #12]
8000588: 60b9 str r1, [r7, #8]
800058a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800058c: 68fb ldr r3, [r7, #12]
800058e: f003 0307 and.w r3, r3, #7
8000592: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000594: 69fb ldr r3, [r7, #28]
8000596: f1c3 0307 rsb r3, r3, #7
800059a: 2b04 cmp r3, #4
800059c: bf28 it cs
800059e: 2304 movcs r3, #4
80005a0: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80005a2: 69fb ldr r3, [r7, #28]
80005a4: 3304 adds r3, #4
80005a6: 2b06 cmp r3, #6
80005a8: d902 bls.n 80005b0 <NVIC_EncodePriority+0x30>
80005aa: 69fb ldr r3, [r7, #28]
80005ac: 3b03 subs r3, #3
80005ae: e000 b.n 80005b2 <NVIC_EncodePriority+0x32>
80005b0: 2300 movs r3, #0
80005b2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80005b4: f04f 32ff mov.w r2, #4294967295
80005b8: 69bb ldr r3, [r7, #24]
80005ba: fa02 f303 lsl.w r3, r2, r3
80005be: 43da mvns r2, r3
80005c0: 68bb ldr r3, [r7, #8]
80005c2: 401a ands r2, r3
80005c4: 697b ldr r3, [r7, #20]
80005c6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80005c8: f04f 31ff mov.w r1, #4294967295
80005cc: 697b ldr r3, [r7, #20]
80005ce: fa01 f303 lsl.w r3, r1, r3
80005d2: 43d9 mvns r1, r3
80005d4: 687b ldr r3, [r7, #4]
80005d6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80005d8: 4313 orrs r3, r2
);
}
80005da: 4618 mov r0, r3
80005dc: 3724 adds r7, #36 ; 0x24
80005de: 46bd mov sp, r7
80005e0: bc80 pop {r7}
80005e2: 4770 bx lr
080005e4 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80005e4: b580 push {r7, lr}
80005e6: b082 sub sp, #8
80005e8: af00 add r7, sp, #0
80005ea: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80005ec: 687b ldr r3, [r7, #4]
80005ee: 3b01 subs r3, #1
80005f0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80005f4: d301 bcc.n 80005fa <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80005f6: 2301 movs r3, #1
80005f8: e00f b.n 800061a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80005fa: 4a0a ldr r2, [pc, #40] ; (8000624 <SysTick_Config+0x40>)
80005fc: 687b ldr r3, [r7, #4]
80005fe: 3b01 subs r3, #1
8000600: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000602: 210f movs r1, #15
8000604: f04f 30ff mov.w r0, #4294967295
8000608: f7ff ff90 bl 800052c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800060c: 4b05 ldr r3, [pc, #20] ; (8000624 <SysTick_Config+0x40>)
800060e: 2200 movs r2, #0
8000610: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000612: 4b04 ldr r3, [pc, #16] ; (8000624 <SysTick_Config+0x40>)
8000614: 2207 movs r2, #7
8000616: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000618: 2300 movs r3, #0
}
800061a: 4618 mov r0, r3
800061c: 3708 adds r7, #8
800061e: 46bd mov sp, r7
8000620: bd80 pop {r7, pc}
8000622: bf00 nop
8000624: e000e010 .word 0xe000e010
08000628 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000628: b580 push {r7, lr}
800062a: b082 sub sp, #8
800062c: af00 add r7, sp, #0
800062e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000630: 6878 ldr r0, [r7, #4]
8000632: f7ff ff49 bl 80004c8 <__NVIC_SetPriorityGrouping>
}
8000636: bf00 nop
8000638: 3708 adds r7, #8
800063a: 46bd mov sp, r7
800063c: bd80 pop {r7, pc}
0800063e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800063e: b580 push {r7, lr}
8000640: b086 sub sp, #24
8000642: af00 add r7, sp, #0
8000644: 4603 mov r3, r0
8000646: 60b9 str r1, [r7, #8]
8000648: 607a str r2, [r7, #4]
800064a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
800064c: 2300 movs r3, #0
800064e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000650: f7ff ff5e bl 8000510 <__NVIC_GetPriorityGrouping>
8000654: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000656: 687a ldr r2, [r7, #4]
8000658: 68b9 ldr r1, [r7, #8]
800065a: 6978 ldr r0, [r7, #20]
800065c: f7ff ff90 bl 8000580 <NVIC_EncodePriority>
8000660: 4602 mov r2, r0
8000662: f997 300f ldrsb.w r3, [r7, #15]
8000666: 4611 mov r1, r2
8000668: 4618 mov r0, r3
800066a: f7ff ff5f bl 800052c <__NVIC_SetPriority>
}
800066e: bf00 nop
8000670: 3718 adds r7, #24
8000672: 46bd mov sp, r7
8000674: bd80 pop {r7, pc}
08000676 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000676: b580 push {r7, lr}
8000678: b082 sub sp, #8
800067a: af00 add r7, sp, #0
800067c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
800067e: 6878 ldr r0, [r7, #4]
8000680: f7ff ffb0 bl 80005e4 <SysTick_Config>
8000684: 4603 mov r3, r0
}
8000686: 4618 mov r0, r3
8000688: 3708 adds r7, #8
800068a: 46bd mov sp, r7
800068c: bd80 pop {r7, pc}
...
08000690 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000690: b580 push {r7, lr}
8000692: b086 sub sp, #24
8000694: af00 add r7, sp, #0
8000696: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000698: 687b ldr r3, [r7, #4]
800069a: 2b00 cmp r3, #0
800069c: d101 bne.n 80006a2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800069e: 2301 movs r3, #1
80006a0: e26c b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80006a2: 687b ldr r3, [r7, #4]
80006a4: 681b ldr r3, [r3, #0]
80006a6: f003 0301 and.w r3, r3, #1
80006aa: 2b00 cmp r3, #0
80006ac: f000 8087 beq.w 80007be <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80006b0: 4b92 ldr r3, [pc, #584] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80006b2: 685b ldr r3, [r3, #4]
80006b4: f003 030c and.w r3, r3, #12
80006b8: 2b04 cmp r3, #4
80006ba: d00c beq.n 80006d6 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
80006bc: 4b8f ldr r3, [pc, #572] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80006be: 685b ldr r3, [r3, #4]
80006c0: f003 030c and.w r3, r3, #12
80006c4: 2b08 cmp r3, #8
80006c6: d112 bne.n 80006ee <HAL_RCC_OscConfig+0x5e>
80006c8: 4b8c ldr r3, [pc, #560] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80006ca: 685b ldr r3, [r3, #4]
80006cc: f403 3380 and.w r3, r3, #65536 ; 0x10000
80006d0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80006d4: d10b bne.n 80006ee <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80006d6: 4b89 ldr r3, [pc, #548] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80006d8: 681b ldr r3, [r3, #0]
80006da: f403 3300 and.w r3, r3, #131072 ; 0x20000
80006de: 2b00 cmp r3, #0
80006e0: d06c beq.n 80007bc <HAL_RCC_OscConfig+0x12c>
80006e2: 687b ldr r3, [r7, #4]
80006e4: 685b ldr r3, [r3, #4]
80006e6: 2b00 cmp r3, #0
80006e8: d168 bne.n 80007bc <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
80006ea: 2301 movs r3, #1
80006ec: e246 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80006ee: 687b ldr r3, [r7, #4]
80006f0: 685b ldr r3, [r3, #4]
80006f2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80006f6: d106 bne.n 8000706 <HAL_RCC_OscConfig+0x76>
80006f8: 4b80 ldr r3, [pc, #512] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80006fa: 681b ldr r3, [r3, #0]
80006fc: 4a7f ldr r2, [pc, #508] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80006fe: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000702: 6013 str r3, [r2, #0]
8000704: e02e b.n 8000764 <HAL_RCC_OscConfig+0xd4>
8000706: 687b ldr r3, [r7, #4]
8000708: 685b ldr r3, [r3, #4]
800070a: 2b00 cmp r3, #0
800070c: d10c bne.n 8000728 <HAL_RCC_OscConfig+0x98>
800070e: 4b7b ldr r3, [pc, #492] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000710: 681b ldr r3, [r3, #0]
8000712: 4a7a ldr r2, [pc, #488] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000714: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000718: 6013 str r3, [r2, #0]
800071a: 4b78 ldr r3, [pc, #480] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
800071c: 681b ldr r3, [r3, #0]
800071e: 4a77 ldr r2, [pc, #476] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000720: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000724: 6013 str r3, [r2, #0]
8000726: e01d b.n 8000764 <HAL_RCC_OscConfig+0xd4>
8000728: 687b ldr r3, [r7, #4]
800072a: 685b ldr r3, [r3, #4]
800072c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000730: d10c bne.n 800074c <HAL_RCC_OscConfig+0xbc>
8000732: 4b72 ldr r3, [pc, #456] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000734: 681b ldr r3, [r3, #0]
8000736: 4a71 ldr r2, [pc, #452] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000738: f443 2380 orr.w r3, r3, #262144 ; 0x40000
800073c: 6013 str r3, [r2, #0]
800073e: 4b6f ldr r3, [pc, #444] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000740: 681b ldr r3, [r3, #0]
8000742: 4a6e ldr r2, [pc, #440] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000744: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000748: 6013 str r3, [r2, #0]
800074a: e00b b.n 8000764 <HAL_RCC_OscConfig+0xd4>
800074c: 4b6b ldr r3, [pc, #428] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
800074e: 681b ldr r3, [r3, #0]
8000750: 4a6a ldr r2, [pc, #424] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000752: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000756: 6013 str r3, [r2, #0]
8000758: 4b68 ldr r3, [pc, #416] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
800075a: 681b ldr r3, [r3, #0]
800075c: 4a67 ldr r2, [pc, #412] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
800075e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000762: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000764: 687b ldr r3, [r7, #4]
8000766: 685b ldr r3, [r3, #4]
8000768: 2b00 cmp r3, #0
800076a: d013 beq.n 8000794 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800076c: f7ff fea2 bl 80004b4 <HAL_GetTick>
8000770: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000772: e008 b.n 8000786 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000774: f7ff fe9e bl 80004b4 <HAL_GetTick>
8000778: 4602 mov r2, r0
800077a: 693b ldr r3, [r7, #16]
800077c: 1ad3 subs r3, r2, r3
800077e: 2b64 cmp r3, #100 ; 0x64
8000780: d901 bls.n 8000786 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000782: 2303 movs r3, #3
8000784: e1fa b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000786: 4b5d ldr r3, [pc, #372] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000788: 681b ldr r3, [r3, #0]
800078a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800078e: 2b00 cmp r3, #0
8000790: d0f0 beq.n 8000774 <HAL_RCC_OscConfig+0xe4>
8000792: e014 b.n 80007be <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000794: f7ff fe8e bl 80004b4 <HAL_GetTick>
8000798: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800079a: e008 b.n 80007ae <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800079c: f7ff fe8a bl 80004b4 <HAL_GetTick>
80007a0: 4602 mov r2, r0
80007a2: 693b ldr r3, [r7, #16]
80007a4: 1ad3 subs r3, r2, r3
80007a6: 2b64 cmp r3, #100 ; 0x64
80007a8: d901 bls.n 80007ae <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
80007aa: 2303 movs r3, #3
80007ac: e1e6 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80007ae: 4b53 ldr r3, [pc, #332] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80007b0: 681b ldr r3, [r3, #0]
80007b2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80007b6: 2b00 cmp r3, #0
80007b8: d1f0 bne.n 800079c <HAL_RCC_OscConfig+0x10c>
80007ba: e000 b.n 80007be <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80007bc: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80007be: 687b ldr r3, [r7, #4]
80007c0: 681b ldr r3, [r3, #0]
80007c2: f003 0302 and.w r3, r3, #2
80007c6: 2b00 cmp r3, #0
80007c8: d063 beq.n 8000892 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80007ca: 4b4c ldr r3, [pc, #304] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80007cc: 685b ldr r3, [r3, #4]
80007ce: f003 030c and.w r3, r3, #12
80007d2: 2b00 cmp r3, #0
80007d4: d00b beq.n 80007ee <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
80007d6: 4b49 ldr r3, [pc, #292] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80007d8: 685b ldr r3, [r3, #4]
80007da: f003 030c and.w r3, r3, #12
80007de: 2b08 cmp r3, #8
80007e0: d11c bne.n 800081c <HAL_RCC_OscConfig+0x18c>
80007e2: 4b46 ldr r3, [pc, #280] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80007e4: 685b ldr r3, [r3, #4]
80007e6: f403 3380 and.w r3, r3, #65536 ; 0x10000
80007ea: 2b00 cmp r3, #0
80007ec: d116 bne.n 800081c <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80007ee: 4b43 ldr r3, [pc, #268] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80007f0: 681b ldr r3, [r3, #0]
80007f2: f003 0302 and.w r3, r3, #2
80007f6: 2b00 cmp r3, #0
80007f8: d005 beq.n 8000806 <HAL_RCC_OscConfig+0x176>
80007fa: 687b ldr r3, [r7, #4]
80007fc: 691b ldr r3, [r3, #16]
80007fe: 2b01 cmp r3, #1
8000800: d001 beq.n 8000806 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000802: 2301 movs r3, #1
8000804: e1ba b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000806: 4b3d ldr r3, [pc, #244] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000808: 681b ldr r3, [r3, #0]
800080a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
800080e: 687b ldr r3, [r7, #4]
8000810: 695b ldr r3, [r3, #20]
8000812: 00db lsls r3, r3, #3
8000814: 4939 ldr r1, [pc, #228] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000816: 4313 orrs r3, r2
8000818: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800081a: e03a b.n 8000892 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800081c: 687b ldr r3, [r7, #4]
800081e: 691b ldr r3, [r3, #16]
8000820: 2b00 cmp r3, #0
8000822: d020 beq.n 8000866 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000824: 4b36 ldr r3, [pc, #216] ; (8000900 <HAL_RCC_OscConfig+0x270>)
8000826: 2201 movs r2, #1
8000828: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800082a: f7ff fe43 bl 80004b4 <HAL_GetTick>
800082e: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000830: e008 b.n 8000844 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000832: f7ff fe3f bl 80004b4 <HAL_GetTick>
8000836: 4602 mov r2, r0
8000838: 693b ldr r3, [r7, #16]
800083a: 1ad3 subs r3, r2, r3
800083c: 2b02 cmp r3, #2
800083e: d901 bls.n 8000844 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000840: 2303 movs r3, #3
8000842: e19b b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000844: 4b2d ldr r3, [pc, #180] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000846: 681b ldr r3, [r3, #0]
8000848: f003 0302 and.w r3, r3, #2
800084c: 2b00 cmp r3, #0
800084e: d0f0 beq.n 8000832 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000850: 4b2a ldr r3, [pc, #168] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000852: 681b ldr r3, [r3, #0]
8000854: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000858: 687b ldr r3, [r7, #4]
800085a: 695b ldr r3, [r3, #20]
800085c: 00db lsls r3, r3, #3
800085e: 4927 ldr r1, [pc, #156] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000860: 4313 orrs r3, r2
8000862: 600b str r3, [r1, #0]
8000864: e015 b.n 8000892 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000866: 4b26 ldr r3, [pc, #152] ; (8000900 <HAL_RCC_OscConfig+0x270>)
8000868: 2200 movs r2, #0
800086a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800086c: f7ff fe22 bl 80004b4 <HAL_GetTick>
8000870: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000872: e008 b.n 8000886 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000874: f7ff fe1e bl 80004b4 <HAL_GetTick>
8000878: 4602 mov r2, r0
800087a: 693b ldr r3, [r7, #16]
800087c: 1ad3 subs r3, r2, r3
800087e: 2b02 cmp r3, #2
8000880: d901 bls.n 8000886 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000882: 2303 movs r3, #3
8000884: e17a b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000886: 4b1d ldr r3, [pc, #116] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
8000888: 681b ldr r3, [r3, #0]
800088a: f003 0302 and.w r3, r3, #2
800088e: 2b00 cmp r3, #0
8000890: d1f0 bne.n 8000874 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000892: 687b ldr r3, [r7, #4]
8000894: 681b ldr r3, [r3, #0]
8000896: f003 0308 and.w r3, r3, #8
800089a: 2b00 cmp r3, #0
800089c: d03a beq.n 8000914 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
800089e: 687b ldr r3, [r7, #4]
80008a0: 699b ldr r3, [r3, #24]
80008a2: 2b00 cmp r3, #0
80008a4: d019 beq.n 80008da <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80008a6: 4b17 ldr r3, [pc, #92] ; (8000904 <HAL_RCC_OscConfig+0x274>)
80008a8: 2201 movs r2, #1
80008aa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80008ac: f7ff fe02 bl 80004b4 <HAL_GetTick>
80008b0: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80008b2: e008 b.n 80008c6 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80008b4: f7ff fdfe bl 80004b4 <HAL_GetTick>
80008b8: 4602 mov r2, r0
80008ba: 693b ldr r3, [r7, #16]
80008bc: 1ad3 subs r3, r2, r3
80008be: 2b02 cmp r3, #2
80008c0: d901 bls.n 80008c6 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
80008c2: 2303 movs r3, #3
80008c4: e15a b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80008c6: 4b0d ldr r3, [pc, #52] ; (80008fc <HAL_RCC_OscConfig+0x26c>)
80008c8: 6a5b ldr r3, [r3, #36] ; 0x24
80008ca: f003 0302 and.w r3, r3, #2
80008ce: 2b00 cmp r3, #0
80008d0: d0f0 beq.n 80008b4 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
80008d2: 2001 movs r0, #1
80008d4: f000 faa6 bl 8000e24 <RCC_Delay>
80008d8: e01c b.n 8000914 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80008da: 4b0a ldr r3, [pc, #40] ; (8000904 <HAL_RCC_OscConfig+0x274>)
80008dc: 2200 movs r2, #0
80008de: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80008e0: f7ff fde8 bl 80004b4 <HAL_GetTick>
80008e4: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80008e6: e00f b.n 8000908 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80008e8: f7ff fde4 bl 80004b4 <HAL_GetTick>
80008ec: 4602 mov r2, r0
80008ee: 693b ldr r3, [r7, #16]
80008f0: 1ad3 subs r3, r2, r3
80008f2: 2b02 cmp r3, #2
80008f4: d908 bls.n 8000908 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
80008f6: 2303 movs r3, #3
80008f8: e140 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
80008fa: bf00 nop
80008fc: 40021000 .word 0x40021000
8000900: 42420000 .word 0x42420000
8000904: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000908: 4b9e ldr r3, [pc, #632] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
800090a: 6a5b ldr r3, [r3, #36] ; 0x24
800090c: f003 0302 and.w r3, r3, #2
8000910: 2b00 cmp r3, #0
8000912: d1e9 bne.n 80008e8 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000914: 687b ldr r3, [r7, #4]
8000916: 681b ldr r3, [r3, #0]
8000918: f003 0304 and.w r3, r3, #4
800091c: 2b00 cmp r3, #0
800091e: f000 80a6 beq.w 8000a6e <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8000922: 2300 movs r3, #0
8000924: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8000926: 4b97 ldr r3, [pc, #604] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000928: 69db ldr r3, [r3, #28]
800092a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800092e: 2b00 cmp r3, #0
8000930: d10d bne.n 800094e <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000932: 4b94 ldr r3, [pc, #592] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000934: 69db ldr r3, [r3, #28]
8000936: 4a93 ldr r2, [pc, #588] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000938: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800093c: 61d3 str r3, [r2, #28]
800093e: 4b91 ldr r3, [pc, #580] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000940: 69db ldr r3, [r3, #28]
8000942: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000946: 60bb str r3, [r7, #8]
8000948: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800094a: 2301 movs r3, #1
800094c: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800094e: 4b8e ldr r3, [pc, #568] ; (8000b88 <HAL_RCC_OscConfig+0x4f8>)
8000950: 681b ldr r3, [r3, #0]
8000952: f403 7380 and.w r3, r3, #256 ; 0x100
8000956: 2b00 cmp r3, #0
8000958: d118 bne.n 800098c <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800095a: 4b8b ldr r3, [pc, #556] ; (8000b88 <HAL_RCC_OscConfig+0x4f8>)
800095c: 681b ldr r3, [r3, #0]
800095e: 4a8a ldr r2, [pc, #552] ; (8000b88 <HAL_RCC_OscConfig+0x4f8>)
8000960: f443 7380 orr.w r3, r3, #256 ; 0x100
8000964: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000966: f7ff fda5 bl 80004b4 <HAL_GetTick>
800096a: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800096c: e008 b.n 8000980 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800096e: f7ff fda1 bl 80004b4 <HAL_GetTick>
8000972: 4602 mov r2, r0
8000974: 693b ldr r3, [r7, #16]
8000976: 1ad3 subs r3, r2, r3
8000978: 2b64 cmp r3, #100 ; 0x64
800097a: d901 bls.n 8000980 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
800097c: 2303 movs r3, #3
800097e: e0fd b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000980: 4b81 ldr r3, [pc, #516] ; (8000b88 <HAL_RCC_OscConfig+0x4f8>)
8000982: 681b ldr r3, [r3, #0]
8000984: f403 7380 and.w r3, r3, #256 ; 0x100
8000988: 2b00 cmp r3, #0
800098a: d0f0 beq.n 800096e <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800098c: 687b ldr r3, [r7, #4]
800098e: 68db ldr r3, [r3, #12]
8000990: 2b01 cmp r3, #1
8000992: d106 bne.n 80009a2 <HAL_RCC_OscConfig+0x312>
8000994: 4b7b ldr r3, [pc, #492] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000996: 6a1b ldr r3, [r3, #32]
8000998: 4a7a ldr r2, [pc, #488] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
800099a: f043 0301 orr.w r3, r3, #1
800099e: 6213 str r3, [r2, #32]
80009a0: e02d b.n 80009fe <HAL_RCC_OscConfig+0x36e>
80009a2: 687b ldr r3, [r7, #4]
80009a4: 68db ldr r3, [r3, #12]
80009a6: 2b00 cmp r3, #0
80009a8: d10c bne.n 80009c4 <HAL_RCC_OscConfig+0x334>
80009aa: 4b76 ldr r3, [pc, #472] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009ac: 6a1b ldr r3, [r3, #32]
80009ae: 4a75 ldr r2, [pc, #468] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009b0: f023 0301 bic.w r3, r3, #1
80009b4: 6213 str r3, [r2, #32]
80009b6: 4b73 ldr r3, [pc, #460] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009b8: 6a1b ldr r3, [r3, #32]
80009ba: 4a72 ldr r2, [pc, #456] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009bc: f023 0304 bic.w r3, r3, #4
80009c0: 6213 str r3, [r2, #32]
80009c2: e01c b.n 80009fe <HAL_RCC_OscConfig+0x36e>
80009c4: 687b ldr r3, [r7, #4]
80009c6: 68db ldr r3, [r3, #12]
80009c8: 2b05 cmp r3, #5
80009ca: d10c bne.n 80009e6 <HAL_RCC_OscConfig+0x356>
80009cc: 4b6d ldr r3, [pc, #436] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009ce: 6a1b ldr r3, [r3, #32]
80009d0: 4a6c ldr r2, [pc, #432] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009d2: f043 0304 orr.w r3, r3, #4
80009d6: 6213 str r3, [r2, #32]
80009d8: 4b6a ldr r3, [pc, #424] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009da: 6a1b ldr r3, [r3, #32]
80009dc: 4a69 ldr r2, [pc, #420] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009de: f043 0301 orr.w r3, r3, #1
80009e2: 6213 str r3, [r2, #32]
80009e4: e00b b.n 80009fe <HAL_RCC_OscConfig+0x36e>
80009e6: 4b67 ldr r3, [pc, #412] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009e8: 6a1b ldr r3, [r3, #32]
80009ea: 4a66 ldr r2, [pc, #408] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009ec: f023 0301 bic.w r3, r3, #1
80009f0: 6213 str r3, [r2, #32]
80009f2: 4b64 ldr r3, [pc, #400] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009f4: 6a1b ldr r3, [r3, #32]
80009f6: 4a63 ldr r2, [pc, #396] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
80009f8: f023 0304 bic.w r3, r3, #4
80009fc: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80009fe: 687b ldr r3, [r7, #4]
8000a00: 68db ldr r3, [r3, #12]
8000a02: 2b00 cmp r3, #0
8000a04: d015 beq.n 8000a32 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a06: f7ff fd55 bl 80004b4 <HAL_GetTick>
8000a0a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000a0c: e00a b.n 8000a24 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000a0e: f7ff fd51 bl 80004b4 <HAL_GetTick>
8000a12: 4602 mov r2, r0
8000a14: 693b ldr r3, [r7, #16]
8000a16: 1ad3 subs r3, r2, r3
8000a18: f241 3288 movw r2, #5000 ; 0x1388
8000a1c: 4293 cmp r3, r2
8000a1e: d901 bls.n 8000a24 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8000a20: 2303 movs r3, #3
8000a22: e0ab b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000a24: 4b57 ldr r3, [pc, #348] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000a26: 6a1b ldr r3, [r3, #32]
8000a28: f003 0302 and.w r3, r3, #2
8000a2c: 2b00 cmp r3, #0
8000a2e: d0ee beq.n 8000a0e <HAL_RCC_OscConfig+0x37e>
8000a30: e014 b.n 8000a5c <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a32: f7ff fd3f bl 80004b4 <HAL_GetTick>
8000a36: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000a38: e00a b.n 8000a50 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000a3a: f7ff fd3b bl 80004b4 <HAL_GetTick>
8000a3e: 4602 mov r2, r0
8000a40: 693b ldr r3, [r7, #16]
8000a42: 1ad3 subs r3, r2, r3
8000a44: f241 3288 movw r2, #5000 ; 0x1388
8000a48: 4293 cmp r3, r2
8000a4a: d901 bls.n 8000a50 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8000a4c: 2303 movs r3, #3
8000a4e: e095 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000a50: 4b4c ldr r3, [pc, #304] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000a52: 6a1b ldr r3, [r3, #32]
8000a54: f003 0302 and.w r3, r3, #2
8000a58: 2b00 cmp r3, #0
8000a5a: d1ee bne.n 8000a3a <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8000a5c: 7dfb ldrb r3, [r7, #23]
8000a5e: 2b01 cmp r3, #1
8000a60: d105 bne.n 8000a6e <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000a62: 4b48 ldr r3, [pc, #288] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000a64: 69db ldr r3, [r3, #28]
8000a66: 4a47 ldr r2, [pc, #284] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000a68: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8000a6c: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000a6e: 687b ldr r3, [r7, #4]
8000a70: 69db ldr r3, [r3, #28]
8000a72: 2b00 cmp r3, #0
8000a74: f000 8081 beq.w 8000b7a <HAL_RCC_OscConfig+0x4ea>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000a78: 4b42 ldr r3, [pc, #264] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000a7a: 685b ldr r3, [r3, #4]
8000a7c: f003 030c and.w r3, r3, #12
8000a80: 2b08 cmp r3, #8
8000a82: d061 beq.n 8000b48 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000a84: 687b ldr r3, [r7, #4]
8000a86: 69db ldr r3, [r3, #28]
8000a88: 2b02 cmp r3, #2
8000a8a: d146 bne.n 8000b1a <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000a8c: 4b3f ldr r3, [pc, #252] ; (8000b8c <HAL_RCC_OscConfig+0x4fc>)
8000a8e: 2200 movs r2, #0
8000a90: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a92: f7ff fd0f bl 80004b4 <HAL_GetTick>
8000a96: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000a98: e008 b.n 8000aac <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000a9a: f7ff fd0b bl 80004b4 <HAL_GetTick>
8000a9e: 4602 mov r2, r0
8000aa0: 693b ldr r3, [r7, #16]
8000aa2: 1ad3 subs r3, r2, r3
8000aa4: 2b02 cmp r3, #2
8000aa6: d901 bls.n 8000aac <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8000aa8: 2303 movs r3, #3
8000aaa: e067 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000aac: 4b35 ldr r3, [pc, #212] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000aae: 681b ldr r3, [r3, #0]
8000ab0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000ab4: 2b00 cmp r3, #0
8000ab6: d1f0 bne.n 8000a9a <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8000ab8: 687b ldr r3, [r7, #4]
8000aba: 6a1b ldr r3, [r3, #32]
8000abc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000ac0: d108 bne.n 8000ad4 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8000ac2: 4b30 ldr r3, [pc, #192] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000ac4: 685b ldr r3, [r3, #4]
8000ac6: f423 3200 bic.w r2, r3, #131072 ; 0x20000
8000aca: 687b ldr r3, [r7, #4]
8000acc: 689b ldr r3, [r3, #8]
8000ace: 492d ldr r1, [pc, #180] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000ad0: 4313 orrs r3, r2
8000ad2: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000ad4: 4b2b ldr r3, [pc, #172] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000ad6: 685b ldr r3, [r3, #4]
8000ad8: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
8000adc: 687b ldr r3, [r7, #4]
8000ade: 6a19 ldr r1, [r3, #32]
8000ae0: 687b ldr r3, [r7, #4]
8000ae2: 6a5b ldr r3, [r3, #36] ; 0x24
8000ae4: 430b orrs r3, r1
8000ae6: 4927 ldr r1, [pc, #156] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000ae8: 4313 orrs r3, r2
8000aea: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8000aec: 4b27 ldr r3, [pc, #156] ; (8000b8c <HAL_RCC_OscConfig+0x4fc>)
8000aee: 2201 movs r2, #1
8000af0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000af2: f7ff fcdf bl 80004b4 <HAL_GetTick>
8000af6: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000af8: e008 b.n 8000b0c <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000afa: f7ff fcdb bl 80004b4 <HAL_GetTick>
8000afe: 4602 mov r2, r0
8000b00: 693b ldr r3, [r7, #16]
8000b02: 1ad3 subs r3, r2, r3
8000b04: 2b02 cmp r3, #2
8000b06: d901 bls.n 8000b0c <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8000b08: 2303 movs r3, #3
8000b0a: e037 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000b0c: 4b1d ldr r3, [pc, #116] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000b0e: 681b ldr r3, [r3, #0]
8000b10: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000b14: 2b00 cmp r3, #0
8000b16: d0f0 beq.n 8000afa <HAL_RCC_OscConfig+0x46a>
8000b18: e02f b.n 8000b7a <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000b1a: 4b1c ldr r3, [pc, #112] ; (8000b8c <HAL_RCC_OscConfig+0x4fc>)
8000b1c: 2200 movs r2, #0
8000b1e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000b20: f7ff fcc8 bl 80004b4 <HAL_GetTick>
8000b24: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000b26: e008 b.n 8000b3a <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000b28: f7ff fcc4 bl 80004b4 <HAL_GetTick>
8000b2c: 4602 mov r2, r0
8000b2e: 693b ldr r3, [r7, #16]
8000b30: 1ad3 subs r3, r2, r3
8000b32: 2b02 cmp r3, #2
8000b34: d901 bls.n 8000b3a <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8000b36: 2303 movs r3, #3
8000b38: e020 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000b3a: 4b12 ldr r3, [pc, #72] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000b3c: 681b ldr r3, [r3, #0]
8000b3e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000b42: 2b00 cmp r3, #0
8000b44: d1f0 bne.n 8000b28 <HAL_RCC_OscConfig+0x498>
8000b46: e018 b.n 8000b7a <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8000b48: 687b ldr r3, [r7, #4]
8000b4a: 69db ldr r3, [r3, #28]
8000b4c: 2b01 cmp r3, #1
8000b4e: d101 bne.n 8000b54 <HAL_RCC_OscConfig+0x4c4>
{
return HAL_ERROR;
8000b50: 2301 movs r3, #1
8000b52: e013 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8000b54: 4b0b ldr r3, [pc, #44] ; (8000b84 <HAL_RCC_OscConfig+0x4f4>)
8000b56: 685b ldr r3, [r3, #4]
8000b58: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000b5a: 68fb ldr r3, [r7, #12]
8000b5c: f403 3280 and.w r2, r3, #65536 ; 0x10000
8000b60: 687b ldr r3, [r7, #4]
8000b62: 6a1b ldr r3, [r3, #32]
8000b64: 429a cmp r2, r3
8000b66: d106 bne.n 8000b76 <HAL_RCC_OscConfig+0x4e6>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8000b68: 68fb ldr r3, [r7, #12]
8000b6a: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8000b6e: 687b ldr r3, [r7, #4]
8000b70: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000b72: 429a cmp r2, r3
8000b74: d001 beq.n 8000b7a <HAL_RCC_OscConfig+0x4ea>
{
return HAL_ERROR;
8000b76: 2301 movs r3, #1
8000b78: e000 b.n 8000b7c <HAL_RCC_OscConfig+0x4ec>
}
}
}
}
return HAL_OK;
8000b7a: 2300 movs r3, #0
}
8000b7c: 4618 mov r0, r3
8000b7e: 3718 adds r7, #24
8000b80: 46bd mov sp, r7
8000b82: bd80 pop {r7, pc}
8000b84: 40021000 .word 0x40021000
8000b88: 40007000 .word 0x40007000
8000b8c: 42420060 .word 0x42420060
08000b90 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8000b90: b580 push {r7, lr}
8000b92: b084 sub sp, #16
8000b94: af00 add r7, sp, #0
8000b96: 6078 str r0, [r7, #4]
8000b98: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8000b9a: 687b ldr r3, [r7, #4]
8000b9c: 2b00 cmp r3, #0
8000b9e: d101 bne.n 8000ba4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8000ba0: 2301 movs r3, #1
8000ba2: e0d0 b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8000ba4: 4b6a ldr r3, [pc, #424] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000ba6: 681b ldr r3, [r3, #0]
8000ba8: f003 0307 and.w r3, r3, #7
8000bac: 683a ldr r2, [r7, #0]
8000bae: 429a cmp r2, r3
8000bb0: d910 bls.n 8000bd4 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000bb2: 4b67 ldr r3, [pc, #412] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000bb4: 681b ldr r3, [r3, #0]
8000bb6: f023 0207 bic.w r2, r3, #7
8000bba: 4965 ldr r1, [pc, #404] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000bbc: 683b ldr r3, [r7, #0]
8000bbe: 4313 orrs r3, r2
8000bc0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8000bc2: 4b63 ldr r3, [pc, #396] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000bc4: 681b ldr r3, [r3, #0]
8000bc6: f003 0307 and.w r3, r3, #7
8000bca: 683a ldr r2, [r7, #0]
8000bcc: 429a cmp r2, r3
8000bce: d001 beq.n 8000bd4 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8000bd0: 2301 movs r3, #1
8000bd2: e0b8 b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8000bd4: 687b ldr r3, [r7, #4]
8000bd6: 681b ldr r3, [r3, #0]
8000bd8: f003 0302 and.w r3, r3, #2
8000bdc: 2b00 cmp r3, #0
8000bde: d020 beq.n 8000c22 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000be0: 687b ldr r3, [r7, #4]
8000be2: 681b ldr r3, [r3, #0]
8000be4: f003 0304 and.w r3, r3, #4
8000be8: 2b00 cmp r3, #0
8000bea: d005 beq.n 8000bf8 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8000bec: 4b59 ldr r3, [pc, #356] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000bee: 685b ldr r3, [r3, #4]
8000bf0: 4a58 ldr r2, [pc, #352] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000bf2: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8000bf6: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8000bf8: 687b ldr r3, [r7, #4]
8000bfa: 681b ldr r3, [r3, #0]
8000bfc: f003 0308 and.w r3, r3, #8
8000c00: 2b00 cmp r3, #0
8000c02: d005 beq.n 8000c10 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8000c04: 4b53 ldr r3, [pc, #332] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c06: 685b ldr r3, [r3, #4]
8000c08: 4a52 ldr r2, [pc, #328] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c0a: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8000c0e: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8000c10: 4b50 ldr r3, [pc, #320] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c12: 685b ldr r3, [r3, #4]
8000c14: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 689b ldr r3, [r3, #8]
8000c1c: 494d ldr r1, [pc, #308] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c1e: 4313 orrs r3, r2
8000c20: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8000c22: 687b ldr r3, [r7, #4]
8000c24: 681b ldr r3, [r3, #0]
8000c26: f003 0301 and.w r3, r3, #1
8000c2a: 2b00 cmp r3, #0
8000c2c: d040 beq.n 8000cb0 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8000c2e: 687b ldr r3, [r7, #4]
8000c30: 685b ldr r3, [r3, #4]
8000c32: 2b01 cmp r3, #1
8000c34: d107 bne.n 8000c46 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000c36: 4b47 ldr r3, [pc, #284] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c38: 681b ldr r3, [r3, #0]
8000c3a: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000c3e: 2b00 cmp r3, #0
8000c40: d115 bne.n 8000c6e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8000c42: 2301 movs r3, #1
8000c44: e07f b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8000c46: 687b ldr r3, [r7, #4]
8000c48: 685b ldr r3, [r3, #4]
8000c4a: 2b02 cmp r3, #2
8000c4c: d107 bne.n 8000c5e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000c4e: 4b41 ldr r3, [pc, #260] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c50: 681b ldr r3, [r3, #0]
8000c52: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000c56: 2b00 cmp r3, #0
8000c58: d109 bne.n 8000c6e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8000c5a: 2301 movs r3, #1
8000c5c: e073 b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000c5e: 4b3d ldr r3, [pc, #244] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c60: 681b ldr r3, [r3, #0]
8000c62: f003 0302 and.w r3, r3, #2
8000c66: 2b00 cmp r3, #0
8000c68: d101 bne.n 8000c6e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8000c6a: 2301 movs r3, #1
8000c6c: e06b b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8000c6e: 4b39 ldr r3, [pc, #228] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c70: 685b ldr r3, [r3, #4]
8000c72: f023 0203 bic.w r2, r3, #3
8000c76: 687b ldr r3, [r7, #4]
8000c78: 685b ldr r3, [r3, #4]
8000c7a: 4936 ldr r1, [pc, #216] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000c7c: 4313 orrs r3, r2
8000c7e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c80: f7ff fc18 bl 80004b4 <HAL_GetTick>
8000c84: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8000c86: e00a b.n 8000c9e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8000c88: f7ff fc14 bl 80004b4 <HAL_GetTick>
8000c8c: 4602 mov r2, r0
8000c8e: 68fb ldr r3, [r7, #12]
8000c90: 1ad3 subs r3, r2, r3
8000c92: f241 3288 movw r2, #5000 ; 0x1388
8000c96: 4293 cmp r3, r2
8000c98: d901 bls.n 8000c9e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8000c9a: 2303 movs r3, #3
8000c9c: e053 b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8000c9e: 4b2d ldr r3, [pc, #180] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000ca0: 685b ldr r3, [r3, #4]
8000ca2: f003 020c and.w r2, r3, #12
8000ca6: 687b ldr r3, [r7, #4]
8000ca8: 685b ldr r3, [r3, #4]
8000caa: 009b lsls r3, r3, #2
8000cac: 429a cmp r2, r3
8000cae: d1eb bne.n 8000c88 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8000cb0: 4b27 ldr r3, [pc, #156] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000cb2: 681b ldr r3, [r3, #0]
8000cb4: f003 0307 and.w r3, r3, #7
8000cb8: 683a ldr r2, [r7, #0]
8000cba: 429a cmp r2, r3
8000cbc: d210 bcs.n 8000ce0 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000cbe: 4b24 ldr r3, [pc, #144] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000cc0: 681b ldr r3, [r3, #0]
8000cc2: f023 0207 bic.w r2, r3, #7
8000cc6: 4922 ldr r1, [pc, #136] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000cc8: 683b ldr r3, [r7, #0]
8000cca: 4313 orrs r3, r2
8000ccc: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8000cce: 4b20 ldr r3, [pc, #128] ; (8000d50 <HAL_RCC_ClockConfig+0x1c0>)
8000cd0: 681b ldr r3, [r3, #0]
8000cd2: f003 0307 and.w r3, r3, #7
8000cd6: 683a ldr r2, [r7, #0]
8000cd8: 429a cmp r2, r3
8000cda: d001 beq.n 8000ce0 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8000cdc: 2301 movs r3, #1
8000cde: e032 b.n 8000d46 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000ce0: 687b ldr r3, [r7, #4]
8000ce2: 681b ldr r3, [r3, #0]
8000ce4: f003 0304 and.w r3, r3, #4
8000ce8: 2b00 cmp r3, #0
8000cea: d008 beq.n 8000cfe <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8000cec: 4b19 ldr r3, [pc, #100] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000cee: 685b ldr r3, [r3, #4]
8000cf0: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 68db ldr r3, [r3, #12]
8000cf8: 4916 ldr r1, [pc, #88] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000cfa: 4313 orrs r3, r2
8000cfc: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8000cfe: 687b ldr r3, [r7, #4]
8000d00: 681b ldr r3, [r3, #0]
8000d02: f003 0308 and.w r3, r3, #8
8000d06: 2b00 cmp r3, #0
8000d08: d009 beq.n 8000d1e <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8000d0a: 4b12 ldr r3, [pc, #72] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000d0c: 685b ldr r3, [r3, #4]
8000d0e: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8000d12: 687b ldr r3, [r7, #4]
8000d14: 691b ldr r3, [r3, #16]
8000d16: 00db lsls r3, r3, #3
8000d18: 490e ldr r1, [pc, #56] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000d1a: 4313 orrs r3, r2
8000d1c: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8000d1e: f000 f821 bl 8000d64 <HAL_RCC_GetSysClockFreq>
8000d22: 4602 mov r2, r0
8000d24: 4b0b ldr r3, [pc, #44] ; (8000d54 <HAL_RCC_ClockConfig+0x1c4>)
8000d26: 685b ldr r3, [r3, #4]
8000d28: 091b lsrs r3, r3, #4
8000d2a: f003 030f and.w r3, r3, #15
8000d2e: 490a ldr r1, [pc, #40] ; (8000d58 <HAL_RCC_ClockConfig+0x1c8>)
8000d30: 5ccb ldrb r3, [r1, r3]
8000d32: fa22 f303 lsr.w r3, r2, r3
8000d36: 4a09 ldr r2, [pc, #36] ; (8000d5c <HAL_RCC_ClockConfig+0x1cc>)
8000d38: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8000d3a: 4b09 ldr r3, [pc, #36] ; (8000d60 <HAL_RCC_ClockConfig+0x1d0>)
8000d3c: 681b ldr r3, [r3, #0]
8000d3e: 4618 mov r0, r3
8000d40: f7ff fb76 bl 8000430 <HAL_InitTick>
return HAL_OK;
8000d44: 2300 movs r3, #0
}
8000d46: 4618 mov r0, r3
8000d48: 3710 adds r7, #16
8000d4a: 46bd mov sp, r7
8000d4c: bd80 pop {r7, pc}
8000d4e: bf00 nop
8000d50: 40022000 .word 0x40022000
8000d54: 40021000 .word 0x40021000
8000d58: 08000ee0 .word 0x08000ee0
8000d5c: 20000000 .word 0x20000000
8000d60: 20000004 .word 0x20000004
08000d64 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8000d64: b490 push {r4, r7}
8000d66: b08a sub sp, #40 ; 0x28
8000d68: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
8000d6a: 4b2a ldr r3, [pc, #168] ; (8000e14 <HAL_RCC_GetSysClockFreq+0xb0>)
8000d6c: 1d3c adds r4, r7, #4
8000d6e: cb0f ldmia r3, {r0, r1, r2, r3}
8000d70: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
8000d74: f240 2301 movw r3, #513 ; 0x201
8000d78: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8000d7a: 2300 movs r3, #0
8000d7c: 61fb str r3, [r7, #28]
8000d7e: 2300 movs r3, #0
8000d80: 61bb str r3, [r7, #24]
8000d82: 2300 movs r3, #0
8000d84: 627b str r3, [r7, #36] ; 0x24
8000d86: 2300 movs r3, #0
8000d88: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8000d8a: 2300 movs r3, #0
8000d8c: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8000d8e: 4b22 ldr r3, [pc, #136] ; (8000e18 <HAL_RCC_GetSysClockFreq+0xb4>)
8000d90: 685b ldr r3, [r3, #4]
8000d92: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8000d94: 69fb ldr r3, [r7, #28]
8000d96: f003 030c and.w r3, r3, #12
8000d9a: 2b04 cmp r3, #4
8000d9c: d002 beq.n 8000da4 <HAL_RCC_GetSysClockFreq+0x40>
8000d9e: 2b08 cmp r3, #8
8000da0: d003 beq.n 8000daa <HAL_RCC_GetSysClockFreq+0x46>
8000da2: e02d b.n 8000e00 <HAL_RCC_GetSysClockFreq+0x9c>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8000da4: 4b1d ldr r3, [pc, #116] ; (8000e1c <HAL_RCC_GetSysClockFreq+0xb8>)
8000da6: 623b str r3, [r7, #32]
break;
8000da8: e02d b.n 8000e06 <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8000daa: 69fb ldr r3, [r7, #28]
8000dac: 0c9b lsrs r3, r3, #18
8000dae: f003 030f and.w r3, r3, #15
8000db2: f107 0228 add.w r2, r7, #40 ; 0x28
8000db6: 4413 add r3, r2
8000db8: f813 3c24 ldrb.w r3, [r3, #-36]
8000dbc: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8000dbe: 69fb ldr r3, [r7, #28]
8000dc0: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000dc4: 2b00 cmp r3, #0
8000dc6: d013 beq.n 8000df0 <HAL_RCC_GetSysClockFreq+0x8c>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8000dc8: 4b13 ldr r3, [pc, #76] ; (8000e18 <HAL_RCC_GetSysClockFreq+0xb4>)
8000dca: 685b ldr r3, [r3, #4]
8000dcc: 0c5b lsrs r3, r3, #17
8000dce: f003 0301 and.w r3, r3, #1
8000dd2: f107 0228 add.w r2, r7, #40 ; 0x28
8000dd6: 4413 add r3, r2
8000dd8: f813 3c28 ldrb.w r3, [r3, #-40]
8000ddc: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8000dde: 697b ldr r3, [r7, #20]
8000de0: 4a0e ldr r2, [pc, #56] ; (8000e1c <HAL_RCC_GetSysClockFreq+0xb8>)
8000de2: fb02 f203 mul.w r2, r2, r3
8000de6: 69bb ldr r3, [r7, #24]
8000de8: fbb2 f3f3 udiv r3, r2, r3
8000dec: 627b str r3, [r7, #36] ; 0x24
8000dee: e004 b.n 8000dfa <HAL_RCC_GetSysClockFreq+0x96>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8000df0: 697b ldr r3, [r7, #20]
8000df2: 4a0b ldr r2, [pc, #44] ; (8000e20 <HAL_RCC_GetSysClockFreq+0xbc>)
8000df4: fb02 f303 mul.w r3, r2, r3
8000df8: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
8000dfa: 6a7b ldr r3, [r7, #36] ; 0x24
8000dfc: 623b str r3, [r7, #32]
break;
8000dfe: e002 b.n 8000e06 <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8000e00: 4b06 ldr r3, [pc, #24] ; (8000e1c <HAL_RCC_GetSysClockFreq+0xb8>)
8000e02: 623b str r3, [r7, #32]
break;
8000e04: bf00 nop
}
}
return sysclockfreq;
8000e06: 6a3b ldr r3, [r7, #32]
}
8000e08: 4618 mov r0, r3
8000e0a: 3728 adds r7, #40 ; 0x28
8000e0c: 46bd mov sp, r7
8000e0e: bc90 pop {r4, r7}
8000e10: 4770 bx lr
8000e12: bf00 nop
8000e14: 08000ed0 .word 0x08000ed0
8000e18: 40021000 .word 0x40021000
8000e1c: 007a1200 .word 0x007a1200
8000e20: 003d0900 .word 0x003d0900
08000e24 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8000e24: b480 push {r7}
8000e26: b085 sub sp, #20
8000e28: af00 add r7, sp, #0
8000e2a: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8000e2c: 4b0a ldr r3, [pc, #40] ; (8000e58 <RCC_Delay+0x34>)
8000e2e: 681b ldr r3, [r3, #0]
8000e30: 4a0a ldr r2, [pc, #40] ; (8000e5c <RCC_Delay+0x38>)
8000e32: fba2 2303 umull r2, r3, r2, r3
8000e36: 0a5b lsrs r3, r3, #9
8000e38: 687a ldr r2, [r7, #4]
8000e3a: fb02 f303 mul.w r3, r2, r3
8000e3e: 60fb str r3, [r7, #12]
do
{
__NOP();
8000e40: bf00 nop
}
while (Delay --);
8000e42: 68fb ldr r3, [r7, #12]
8000e44: 1e5a subs r2, r3, #1
8000e46: 60fa str r2, [r7, #12]
8000e48: 2b00 cmp r3, #0
8000e4a: d1f9 bne.n 8000e40 <RCC_Delay+0x1c>
}
8000e4c: bf00 nop
8000e4e: bf00 nop
8000e50: 3714 adds r7, #20
8000e52: 46bd mov sp, r7
8000e54: bc80 pop {r7}
8000e56: 4770 bx lr
8000e58: 20000000 .word 0x20000000
8000e5c: 10624dd3 .word 0x10624dd3
08000e60 <__libc_init_array>:
8000e60: b570 push {r4, r5, r6, lr}
8000e62: 2600 movs r6, #0
8000e64: 4d0c ldr r5, [pc, #48] ; (8000e98 <__libc_init_array+0x38>)
8000e66: 4c0d ldr r4, [pc, #52] ; (8000e9c <__libc_init_array+0x3c>)
8000e68: 1b64 subs r4, r4, r5
8000e6a: 10a4 asrs r4, r4, #2
8000e6c: 42a6 cmp r6, r4
8000e6e: d109 bne.n 8000e84 <__libc_init_array+0x24>
8000e70: f000 f822 bl 8000eb8 <_init>
8000e74: 2600 movs r6, #0
8000e76: 4d0a ldr r5, [pc, #40] ; (8000ea0 <__libc_init_array+0x40>)
8000e78: 4c0a ldr r4, [pc, #40] ; (8000ea4 <__libc_init_array+0x44>)
8000e7a: 1b64 subs r4, r4, r5
8000e7c: 10a4 asrs r4, r4, #2
8000e7e: 42a6 cmp r6, r4
8000e80: d105 bne.n 8000e8e <__libc_init_array+0x2e>
8000e82: bd70 pop {r4, r5, r6, pc}
8000e84: f855 3b04 ldr.w r3, [r5], #4
8000e88: 4798 blx r3
8000e8a: 3601 adds r6, #1
8000e8c: e7ee b.n 8000e6c <__libc_init_array+0xc>
8000e8e: f855 3b04 ldr.w r3, [r5], #4
8000e92: 4798 blx r3
8000e94: 3601 adds r6, #1
8000e96: e7f2 b.n 8000e7e <__libc_init_array+0x1e>
8000e98: 08000ef0 .word 0x08000ef0
8000e9c: 08000ef0 .word 0x08000ef0
8000ea0: 08000ef0 .word 0x08000ef0
8000ea4: 08000ef4 .word 0x08000ef4
08000ea8 <memset>:
8000ea8: 4603 mov r3, r0
8000eaa: 4402 add r2, r0
8000eac: 4293 cmp r3, r2
8000eae: d100 bne.n 8000eb2 <memset+0xa>
8000eb0: 4770 bx lr
8000eb2: f803 1b01 strb.w r1, [r3], #1
8000eb6: e7f9 b.n 8000eac <memset+0x4>
08000eb8 <_init>:
8000eb8: b5f8 push {r3, r4, r5, r6, r7, lr}
8000eba: bf00 nop
8000ebc: bcf8 pop {r3, r4, r5, r6, r7}
8000ebe: bc08 pop {r3}
8000ec0: 469e mov lr, r3
8000ec2: 4770 bx lr
08000ec4 <_fini>:
8000ec4: b5f8 push {r3, r4, r5, r6, r7, lr}
8000ec6: bf00 nop
8000ec8: bcf8 pop {r3, r4, r5, r6, r7}
8000eca: bc08 pop {r3}
8000ecc: 469e mov lr, r3
8000ece: 4770 bx lr
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