移植了LCD屏幕，FLASH字库
字库还有偏移问题未解决 Signed-off-by: 无闻风 <53944749+wuwenfengmi1998@users.noreply.github.com>
This commit is contained in:
无闻风
@@ -0,0 +1,731 @@
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/**
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******************************************************************************
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* @file stm32f1xx_hal_spi.h
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* @author MCD Application Team
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* @brief Header file of SPI HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32F1xx_HAL_SPI_H
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#define STM32F1xx_HAL_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup SPI
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup SPI_Exported_Types SPI Exported Types
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* @{
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*/
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/**
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* @brief SPI Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Mode; /*!< Specifies the SPI operating mode.
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This parameter can be a value of @ref SPI_Mode */
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uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
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This parameter can be a value of @ref SPI_Direction */
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uint32_t DataSize; /*!< Specifies the SPI data size.
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This parameter can be a value of @ref SPI_Data_Size */
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uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
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This parameter can be a value of @ref SPI_Clock_Polarity */
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uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
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This parameter can be a value of @ref SPI_Clock_Phase */
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uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
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hardware (NSS pin) or by software using the SSI bit.
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This parameter can be a value of @ref SPI_Slave_Select_management */
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uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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used to configure the transmit and receive SCK clock.
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This parameter can be a value of @ref SPI_BaudRate_Prescaler
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@note The communication clock is derived from the master
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clock. The slave clock does not need to be set. */
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uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
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This parameter can be a value of @ref SPI_MSB_LSB_transmission */
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uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
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This parameter can be a value of @ref SPI_TI_mode */
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uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
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This parameter can be a value of @ref SPI_CRC_Calculation */
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uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
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This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
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} SPI_InitTypeDef;
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/**
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* @brief HAL SPI State structure definition
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*/
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typedef enum
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{
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HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
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HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
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HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
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HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
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HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
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HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
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HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
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HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
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} HAL_SPI_StateTypeDef;
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/**
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* @brief SPI handle Structure definition
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*/
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typedef struct __SPI_HandleTypeDef
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{
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SPI_TypeDef *Instance; /*!< SPI registers base address */
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SPI_InitTypeDef Init; /*!< SPI communication parameters */
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uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
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uint16_t TxXferSize; /*!< SPI Tx Transfer size */
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__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
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uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
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uint16_t RxXferSize; /*!< SPI Rx Transfer size */
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__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
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void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
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void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
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DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
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DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
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HAL_LockTypeDef Lock; /*!< Locking object */
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__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
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__IO uint32_t ErrorCode; /*!< SPI Error code */
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#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
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void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
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void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
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void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
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void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
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void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
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void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
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void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
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void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
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void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
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void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
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#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
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} SPI_HandleTypeDef;
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#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
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/**
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* @brief HAL SPI Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
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HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
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HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
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HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
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HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
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HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
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HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
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HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
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HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
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HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
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} HAL_SPI_CallbackIDTypeDef;
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/**
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* @brief HAL SPI Callback pointer definition
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*/
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typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
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#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SPI_Exported_Constants SPI Exported Constants
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* @{
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*/
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/** @defgroup SPI_Error_Code SPI Error Code
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* @{
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*/
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#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
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#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
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#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
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#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
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#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
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#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */
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#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
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#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
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#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
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#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @defgroup SPI_Mode SPI Mode
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* @{
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*/
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#define SPI_MODE_SLAVE (0x00000000U)
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#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
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/**
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* @}
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*/
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/** @defgroup SPI_Direction SPI Direction Mode
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* @{
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*/
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#define SPI_DIRECTION_2LINES (0x00000000U)
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#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
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#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
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/**
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* @}
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*/
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/** @defgroup SPI_Data_Size SPI Data Size
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* @{
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*/
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#define SPI_DATASIZE_8BIT (0x00000000U)
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#define SPI_DATASIZE_16BIT SPI_CR1_DFF
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/**
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* @}
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*/
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/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
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* @{
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*/
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#define SPI_POLARITY_LOW (0x00000000U)
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#define SPI_POLARITY_HIGH SPI_CR1_CPOL
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/**
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* @}
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*/
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/** @defgroup SPI_Clock_Phase SPI Clock Phase
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* @{
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*/
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#define SPI_PHASE_1EDGE (0x00000000U)
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#define SPI_PHASE_2EDGE SPI_CR1_CPHA
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/**
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* @}
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*/
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/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
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* @{
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*/
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#define SPI_NSS_SOFT SPI_CR1_SSM
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#define SPI_NSS_HARD_INPUT (0x00000000U)
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#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
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/**
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* @}
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*/
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/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
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* @{
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*/
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#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
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#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
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#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
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#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
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#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
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#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
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#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
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#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
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/**
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* @}
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*/
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/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
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* @{
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*/
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#define SPI_FIRSTBIT_MSB (0x00000000U)
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#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
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/**
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* @}
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*/
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/** @defgroup SPI_TI_mode SPI TI Mode
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* @{
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*/
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#define SPI_TIMODE_DISABLE (0x00000000U)
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/**
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* @}
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*/
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/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
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* @{
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*/
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#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
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#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
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/**
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* @}
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*/
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/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
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* @{
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*/
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#define SPI_IT_TXE SPI_CR2_TXEIE
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#define SPI_IT_RXNE SPI_CR2_RXNEIE
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#define SPI_IT_ERR SPI_CR2_ERRIE
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/**
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* @}
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*/
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/** @defgroup SPI_Flags_definition SPI Flags Definition
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* @{
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*/
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#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
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#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
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#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
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#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
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#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
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#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
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#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\
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| SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros -----------------------------------------------------------*/
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/** @defgroup SPI_Exported_Macros SPI Exported Macros
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* @{
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*/
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/** @brief Reset SPI handle state.
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* @param __HANDLE__ specifies the SPI Handle.
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* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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* @retval None
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*/
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#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
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#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
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(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
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(__HANDLE__)->MspInitCallback = NULL; \
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(__HANDLE__)->MspDeInitCallback = NULL; \
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} while(0)
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#else
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#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
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#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
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/** @brief Enable the specified SPI interrupts.
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* @param __HANDLE__ specifies the SPI Handle.
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* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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* @param __INTERRUPT__ specifies the interrupt source to enable.
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* This parameter can be one of the following values:
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* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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* @arg SPI_IT_ERR: Error interrupt enable
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* @retval None
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*/
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#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
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/** @brief Disable the specified SPI interrupts.
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* @param __HANDLE__ specifies the SPI handle.
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* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
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* @param __INTERRUPT__ specifies the interrupt source to disable.
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* This parameter can be one of the following values:
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* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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* @arg SPI_IT_ERR: Error interrupt enable
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* @retval None
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*/
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#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
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/** @brief Check whether the specified SPI interrupt source is enabled or not.
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* @param __HANDLE__ specifies the SPI Handle.
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* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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* @param __INTERRUPT__ specifies the SPI interrupt source to check.
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* This parameter can be one of the following values:
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* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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* @arg SPI_IT_ERR: Error interrupt enable
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* @retval The new state of __IT__ (TRUE or FALSE).
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*/
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#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
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& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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/** @brief Check whether the specified SPI flag is set or not.
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* @param __HANDLE__ specifies the SPI Handle.
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* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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* @param __FLAG__ specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
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* @arg SPI_FLAG_TXE: Transmit buffer empty flag
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* @arg SPI_FLAG_CRCERR: CRC error flag
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* @arg SPI_FLAG_MODF: Mode fault flag
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* @arg SPI_FLAG_OVR: Overrun flag
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* @arg SPI_FLAG_BSY: Busy flag
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* @retval The new state of __FLAG__ (TRUE or FALSE).
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*/
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#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
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/** @brief Clear the SPI CRCERR pending flag.
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* @param __HANDLE__ specifies the SPI Handle.
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* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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* @retval None
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*/
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#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
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/** @brief Clear the SPI MODF pending flag.
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* @param __HANDLE__ specifies the SPI Handle.
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* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
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* @retval None
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*/
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#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
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do{ \
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__IO uint32_t tmpreg_modf = 0x00U; \
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tmpreg_modf = (__HANDLE__)->Instance->SR; \
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CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
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UNUSED(tmpreg_modf); \
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} while(0U)
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/** @brief Clear the SPI OVR pending flag.
|
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* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
||||
|
||||
/** @brief Disable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Constants SPI Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
|
||||
#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Set the SPI transmit-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Set the SPI receive-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Reset the CRC calculation of the SPI.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
* This parameter can be a value of @ref SPI_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* This parameter can be a value of @ref SPI_Direction
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
||||
|
||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
||||
* @param __DATASIZE__ specifies the SPI Data Size.
|
||||
* This parameter can be a value of @ref SPI_Data_Size
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_8BIT))
|
||||
|
||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the SPI serial clock steady state.
|
||||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
|
||||
|
||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
||||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
|
||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
/** @brief Checks if SPI TI mode parameter is disabled.
|
||||
* @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode.
|
||||
* This parameter can be a value of @ref SPI_TI_mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
|
||||
|
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
||||
* This parameter can be a value of @ref SPI_CRC_Calculation
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
|
||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
|
||||
|
||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
||||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
|
||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Functions SPI Private Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_SPI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,235 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_sram.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_SRAM_H
|
||||
#define STM32F1xx_HAL_SRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined FSMC_BANK1
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_fsmc.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup SRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
|
||||
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
|
||||
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
|
||||
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
|
||||
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
|
||||
|
||||
} HAL_SRAM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SRAM handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __SRAM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
||||
{
|
||||
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SRAM locking object */
|
||||
|
||||
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
|
||||
|
||||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
|
||||
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
|
||||
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
|
||||
#endif
|
||||
} SRAM_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL SRAM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
|
||||
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
|
||||
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
|
||||
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
|
||||
} HAL_SRAM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
|
||||
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SRAM handle state
|
||||
* @param __HANDLE__ SRAM handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
||||
uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
||||
uint32_t BufferSize);
|
||||
|
||||
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
|
||||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
||||
/* SRAM callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
|
||||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
||||
pSRAM_DmaCallbackTypeDef pCallback);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM State functions ******************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_SRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,963 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FSMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_LL_FSMC_H
|
||||
#define STM32F1xx_LL_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined FSMC_BANK1
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
|
||||
((__BANK__) == FSMC_NORSRAM_BANK2) || \
|
||||
((__BANK__) == FSMC_NORSRAM_BANK3) || \
|
||||
((__BANK__) == FSMC_NORSRAM_BANK4))
|
||||
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
|
||||
((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
|
||||
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
|
||||
((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
|
||||
((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
|
||||
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
|
||||
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
|
||||
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
|
||||
#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_128) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_256) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_512) || \
|
||||
((__SIZE__) == FSMC_PAGE_SIZE_1024))
|
||||
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
|
||||
((__MODE__) == FSMC_ACCESS_MODE_B) || \
|
||||
((__MODE__) == FSMC_ACCESS_MODE_C) || \
|
||||
((__MODE__) == FSMC_ACCESS_MODE_D))
|
||||
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
|
||||
((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
|
||||
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
|
||||
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
|
||||
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
|
||||
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
|
||||
((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
|
||||
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
|
||||
((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
|
||||
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
|
||||
((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
|
||||
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
|
||||
((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
|
||||
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
|
||||
((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
|
||||
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
|
||||
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
|
||||
((__BURST__) == FSMC_WRITE_BURST_ENABLE))
|
||||
#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
|
||||
((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
|
||||
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
|
||||
#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
|
||||
#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
|
||||
#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
|
||||
#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
|
||||
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
|
||||
|
||||
#endif /* FSMC_BANK1 */
|
||||
#if defined(FSMC_BANK3)
|
||||
|
||||
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
|
||||
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
||||
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
||||
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
||||
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
||||
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
|
||||
((__STATE__) == FSMC_NAND_ECC_ENABLE))
|
||||
|
||||
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
|
||||
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
|
||||
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
|
||||
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
|
||||
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
|
||||
#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
|
||||
|
||||
#endif /* FSMC_BANK3 */
|
||||
#if defined(FSMC_BANK4)
|
||||
#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
|
||||
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined FSMC_BANK1
|
||||
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
|
||||
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
|
||||
#endif /* FSMC_BANK1 */
|
||||
#if defined(FSMC_BANK3)
|
||||
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
|
||||
#endif /* FSMC_BANK3 */
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
#if defined FSMC_BANK1
|
||||
#define FSMC_NORSRAM_DEVICE FSMC_Bank1
|
||||
#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
|
||||
#endif /* FSMC_BANK1 */
|
||||
#if defined(FSMC_BANK3)
|
||||
#define FSMC_NAND_DEVICE FSMC_Bank2_3
|
||||
#endif /* FSMC_BANK3 */
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCCARD_DEVICE FSMC_Bank4
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
#if defined FSMC_BANK1
|
||||
/**
|
||||
* @brief FSMC NORSRAM Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the data bus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory device.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
|
||||
|
||||
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
|
||||
uint32_t PageSize; /*!< Specifies the memory page size.
|
||||
This parameter can be a value of @ref FSMC_Page_Size */
|
||||
} FSMC_NORSRAM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NORSRAM Timing parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
|
||||
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
|
||||
NOR Flash memories. */
|
||||
|
||||
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
|
||||
@note This parameter is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
|
||||
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
|
||||
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
|
||||
accesses. */
|
||||
|
||||
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The parameter value depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
} FSMC_NORSRAM_TimingTypeDef;
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
/**
|
||||
* @brief FSMC NAND Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||
|
||||
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_NAND_Data_Width */
|
||||
|
||||
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */
|
||||
|
||||
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||
|
||||
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
|
||||
|
||||
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
} FSMC_NAND_InitTypeDef;
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
/**
|
||||
* @brief FSMC NAND Timing parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
|
||||
|
||||
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
|
||||
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command de-assertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
|
||||
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
data bus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||||
} FSMC_NAND_PCC_TimingTypeDef;
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/**
|
||||
* @brief FSMC PCCARD Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
|
||||
|
||||
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
}FSMC_PCCARD_InitTypeDef;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#if defined FSMC_BANK1
|
||||
|
||||
/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_BANK1 (0x00000000U)
|
||||
#define FSMC_NORSRAM_BANK2 (0x00000002U)
|
||||
#define FSMC_NORSRAM_BANK3 (0x00000004U)
|
||||
#define FSMC_NORSRAM_BANK4 (0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
|
||||
#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type FSMC Memory Type
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
|
||||
#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
|
||||
#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
|
||||
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
|
||||
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
|
||||
#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation FSMC Write Operation
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
|
||||
#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
|
||||
#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
|
||||
#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
|
||||
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Page_Size FSMC Page Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_PAGE_SIZE_NONE (0x00000000U)
|
||||
#define FSMC_PAGE_SIZE_128 (0x00010000U)
|
||||
#define FSMC_PAGE_SIZE_256 (0x00020000U)
|
||||
#define FSMC_PAGE_SIZE_512 (0x00030000U)
|
||||
#define FSMC_PAGE_SIZE_1024 (0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst FSMC Write Burst
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
|
||||
#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
|
||||
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode FSMC Access Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ACCESS_MODE_A (0x00000000U)
|
||||
#define FSMC_ACCESS_MODE_B (0x10000000U)
|
||||
#define FSMC_ACCESS_MODE_C (0x20000000U)
|
||||
#define FSMC_ACCESS_MODE_D (0x30000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
|
||||
/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_BANK2 (0x00000010U)
|
||||
#define FSMC_NAND_BANK3 (0x00000100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_feature FSMC Wait feature
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
|
||||
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK4)
|
||||
#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
|
||||
#endif
|
||||
#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
|
||||
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC FSMC ECC
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_ECC_DISABLE (0x00000000U)
|
||||
#define FSMC_NAND_ECC_ENABLE (0x00000040U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
|
||||
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
|
||||
/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
#define FSMC_IT_RISING_EDGE (0x00000008U)
|
||||
#define FSMC_IT_LEVEL (0x00000010U)
|
||||
#define FSMC_IT_FALLING_EDGE (0x00000020U)
|
||||
#endif /* FSMC_BANK3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
|
||||
#define FSMC_FLAG_RISING_EDGE (0x00000001U)
|
||||
#define FSMC_FLAG_LEVEL (0x00000002U)
|
||||
#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
|
||||
#define FSMC_FLAG_FEMPT (0x00000040U)
|
||||
#endif /* FSMC_BANK3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined FSMC_BANK1
|
||||
/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
|
||||
* @brief macros to handle NOR device enable/disable and read/write operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NORSRAM device access.
|
||||
* @param __INSTANCE__ FSMC_NORSRAM Instance
|
||||
* @param __BANK__ FSMC_NORSRAM Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||||
|= FSMC_BCRx_MBKEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the NORSRAM device access.
|
||||
* @param __INSTANCE__ FSMC_NORSRAM Instance
|
||||
* @param __BANK__ FSMC_NORSRAM Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||||
&= ~FSMC_BCRx_MBKEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
|
||||
* @brief macros to handle NAND device enable/disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NAND device access.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \
|
||||
((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
|
||||
|
||||
/**
|
||||
* @brief Disable the NAND device access.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
|
||||
CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
|
||||
* @brief macros to handle PCCARD read/write operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the PCCARD device access.
|
||||
* @param __INSTANCE__ FSMC_PCCARD Instance
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the PCCARD device access.
|
||||
* @param __INSTANCE__ FSMC_PCCARD Instance
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
|
||||
* @brief macros to handle NAND interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the NAND device interrupt.
|
||||
* @param __INSTANCE__ FSMC_NAND instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __INTERRUPT__ FSMC_NAND interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
|
||||
((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the NAND device interrupt.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __INTERRUPT__ FSMC_NAND interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
|
||||
((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Get flag status of the NAND device.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __FLAG__ FSMC_NAND flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
|
||||
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear flag status of the NAND device.
|
||||
* @param __INSTANCE__ FSMC_NAND Instance
|
||||
* @param __BANK__ FSMC_NAND Bank
|
||||
* @param __FLAG__ FSMC_NAND flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
|
||||
((__INSTANCE__)->SR3 &= ~(__FLAG__)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
|
||||
* @brief macros to handle PCCARD interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the PCCARD device interrupt.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __INTERRUPT__ FSMC_PCCARD interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the PCCARD device interrupt.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __INTERRUPT__ FSMC_PCCARD interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
||||
* @arg FSMC_IT_LEVEL: Interrupt level.
|
||||
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get flag status of the PCCARD device.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __FLAG__ FSMC_PCCARD flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear flag status of the PCCARD device.
|
||||
* @param __INSTANCE__ FSMC_PCCARD instance
|
||||
* @param __FLAG__ FSMC_PCCARD flag
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||||
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
||||
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||||
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined FSMC_BANK1
|
||||
/** @defgroup FSMC_LL_NORSRAM NOR SRAM
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
|
||||
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
|
||||
FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK1 */
|
||||
|
||||
#if defined(FSMC_BANK3)
|
||||
/** @defgroup FSMC_LL_NAND NAND
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK3 */
|
||||
|
||||
#if defined(FSMC_BANK4)
|
||||
/** @defgroup FSMC_LL_PCCARD PCCARD
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
|
||||
FSMC_NAND_PCC_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FSMC_BANK4 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_LL_FSMC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user