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04b4a6fd020eaa415853e6be38a47fdf0fdf93d3
smartbooks/103ze/Debug/103ze_code.list
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无闻风 04b4a6fd02 移植了LCD屏幕，FLASH字库 
字库还有偏移问题未解决

Signed-off-by: 无闻风 <53944749+wuwenfengmi1998@users.noreply.github.com>
2021-03-11 22:33:36 +08:00

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This file contains ambiguous Unicode characters
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103ze_code.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001e4 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003a80 080001e4 080001e4 000101e4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000a98 08003c64 08003c64 00013c64 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080046fc 080046fc 00020024 2**0
CONTENTS
4 .ARM 00000000 080046fc 080046fc 00020024 2**0
CONTENTS
5 .preinit_array 00000000 080046fc 080046fc 00020024 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080046fc 080046fc 000146fc 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08004700 08004700 00014700 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000024 20000000 08004704 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000056c 20000024 08004728 00020024 2**2
ALLOC
10 ._user_heap_stack 00001000 20000590 08004728 00020590 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00020024 2**0
CONTENTS, READONLY
12 .debug_info 0000bb02 00000000 00000000 0002004d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000026e2 00000000 00000000 0002bb4f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000009c8 00000000 00000000 0002e238 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000890 00000000 00000000 0002ec00 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001a202 00000000 00000000 0002f490 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000c6fc 00000000 00000000 00049692 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00092d57 00000000 00000000 00055d8e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 000e8ae5 2**0
CONTENTS, READONLY
20 .debug_frame 000024c8 00000000 00000000 000e8b38 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001e4 <__do_global_dtors_aux>:
80001e4: b510 push {r4, lr}
80001e6: 4c05 ldr r4, [pc, #20] ; (80001fc <__do_global_dtors_aux+0x18>)
80001e8: 7823 ldrb r3, [r4, #0]
80001ea: b933 cbnz r3, 80001fa <__do_global_dtors_aux+0x16>
80001ec: 4b04 ldr r3, [pc, #16] ; (8000200 <__do_global_dtors_aux+0x1c>)
80001ee: b113 cbz r3, 80001f6 <__do_global_dtors_aux+0x12>
80001f0: 4804 ldr r0, [pc, #16] ; (8000204 <__do_global_dtors_aux+0x20>)
80001f2: f3af 8000 nop.w
80001f6: 2301 movs r3, #1
80001f8: 7023 strb r3, [r4, #0]
80001fa: bd10 pop {r4, pc}
80001fc: 20000024 .word 0x20000024
8000200: 00000000 .word 0x00000000
8000204: 08003c4c .word 0x08003c4c
08000208 <frame_dummy>:
8000208: b508 push {r3, lr}
800020a: 4b03 ldr r3, [pc, #12] ; (8000218 <frame_dummy+0x10>)
800020c: b11b cbz r3, 8000216 <frame_dummy+0xe>
800020e: 4903 ldr r1, [pc, #12] ; (800021c <frame_dummy+0x14>)
8000210: 4803 ldr r0, [pc, #12] ; (8000220 <frame_dummy+0x18>)
8000212: f3af 8000 nop.w
8000216: bd08 pop {r3, pc}
8000218: 00000000 .word 0x00000000
800021c: 20000028 .word 0x20000028
8000220: 08003c4c .word 0x08003c4c
08000224 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000224: b580 push {r7, lr}
8000226: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000228: f000 faa8 bl 800077c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800022c: f000 f80b bl 8000246 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000230: f000 f884 bl 800033c <MX_GPIO_Init>
MX_FSMC_Init();
8000234: f000 f908 bl 8000448 <MX_FSMC_Init>
MX_SPI2_Init();
8000238: f000 f84a bl 80002d0 <MX_SPI2_Init>
MX_FATFS_Init();
800023c: f002 f838 bl 80022b0 <MX_FATFS_Init>
/* USER CODE BEGIN 2 */
my_main();
8000240: f002 f90a bl 8002458 <my_main>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000244: e7fe b.n 8000244 <main+0x20>
08000246 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000246: b580 push {r7, lr}
8000248: b090 sub sp, #64 ; 0x40
800024a: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800024c: f107 0318 add.w r3, r7, #24
8000250: 2228 movs r2, #40 ; 0x28
8000252: 2100 movs r1, #0
8000254: 4618 mov r0, r3
8000256: f003 fcf1 bl 8003c3c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800025a: 1d3b adds r3, r7, #4
800025c: 2200 movs r2, #0
800025e: 601a str r2, [r3, #0]
8000260: 605a str r2, [r3, #4]
8000262: 609a str r2, [r3, #8]
8000264: 60da str r2, [r3, #12]
8000266: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000268: 2301 movs r3, #1
800026a: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
800026c: f44f 3380 mov.w r3, #65536 ; 0x10000
8000270: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
8000272: 2300 movs r3, #0
8000274: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000276: 2301 movs r3, #1
8000278: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800027a: 2302 movs r3, #2
800027c: 637b str r3, [r7, #52] ; 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
800027e: f44f 3380 mov.w r3, #65536 ; 0x10000
8000282: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
8000284: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
8000288: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800028a: f107 0318 add.w r3, r7, #24
800028e: 4618 mov r0, r3
8000290: f000 fd8a bl 8000da8 <HAL_RCC_OscConfig>
8000294: 4603 mov r3, r0
8000296: 2b00 cmp r3, #0
8000298: d001 beq.n 800029e <SystemClock_Config+0x58>
{
Error_Handler();
800029a: f000 f939 bl 8000510 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800029e: 230f movs r3, #15
80002a0: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80002a2: 2302 movs r3, #2
80002a4: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002a6: 2300 movs r3, #0
80002a8: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80002aa: f44f 6380 mov.w r3, #1024 ; 0x400
80002ae: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80002b0: 2300 movs r3, #0
80002b2: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80002b4: 1d3b adds r3, r7, #4
80002b6: 2102 movs r1, #2
80002b8: 4618 mov r0, r3
80002ba: f000 fff5 bl 80012a8 <HAL_RCC_ClockConfig>
80002be: 4603 mov r3, r0
80002c0: 2b00 cmp r3, #0
80002c2: d001 beq.n 80002c8 <SystemClock_Config+0x82>
{
Error_Handler();
80002c4: f000 f924 bl 8000510 <Error_Handler>
}
}
80002c8: bf00 nop
80002ca: 3740 adds r7, #64 ; 0x40
80002cc: 46bd mov sp, r7
80002ce: bd80 pop {r7, pc}
080002d0 <MX_SPI2_Init>:
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
80002d0: b580 push {r7, lr}
80002d2: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
80002d4: 4b17 ldr r3, [pc, #92] ; (8000334 <MX_SPI2_Init+0x64>)
80002d6: 4a18 ldr r2, [pc, #96] ; (8000338 <MX_SPI2_Init+0x68>)
80002d8: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
80002da: 4b16 ldr r3, [pc, #88] ; (8000334 <MX_SPI2_Init+0x64>)
80002dc: f44f 7282 mov.w r2, #260 ; 0x104
80002e0: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
80002e2: 4b14 ldr r3, [pc, #80] ; (8000334 <MX_SPI2_Init+0x64>)
80002e4: 2200 movs r2, #0
80002e6: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
80002e8: 4b12 ldr r3, [pc, #72] ; (8000334 <MX_SPI2_Init+0x64>)
80002ea: 2200 movs r2, #0
80002ec: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
80002ee: 4b11 ldr r3, [pc, #68] ; (8000334 <MX_SPI2_Init+0x64>)
80002f0: 2200 movs r2, #0
80002f2: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
80002f4: 4b0f ldr r3, [pc, #60] ; (8000334 <MX_SPI2_Init+0x64>)
80002f6: 2200 movs r2, #0
80002f8: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_SOFT;
80002fa: 4b0e ldr r3, [pc, #56] ; (8000334 <MX_SPI2_Init+0x64>)
80002fc: f44f 7200 mov.w r2, #512 ; 0x200
8000300: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8000302: 4b0c ldr r3, [pc, #48] ; (8000334 <MX_SPI2_Init+0x64>)
8000304: 2200 movs r2, #0
8000306: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000308: 4b0a ldr r3, [pc, #40] ; (8000334 <MX_SPI2_Init+0x64>)
800030a: 2200 movs r2, #0
800030c: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
800030e: 4b09 ldr r3, [pc, #36] ; (8000334 <MX_SPI2_Init+0x64>)
8000310: 2200 movs r2, #0
8000312: 625a str r2, [r3, #36] ; 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000314: 4b07 ldr r3, [pc, #28] ; (8000334 <MX_SPI2_Init+0x64>)
8000316: 2200 movs r2, #0
8000318: 629a str r2, [r3, #40] ; 0x28
hspi2.Init.CRCPolynomial = 10;
800031a: 4b06 ldr r3, [pc, #24] ; (8000334 <MX_SPI2_Init+0x64>)
800031c: 220a movs r2, #10
800031e: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi2) != HAL_OK)
8000320: 4804 ldr r0, [pc, #16] ; (8000334 <MX_SPI2_Init+0x64>)
8000322: f001 f929 bl 8001578 <HAL_SPI_Init>
8000326: 4603 mov r3, r0
8000328: 2b00 cmp r3, #0
800032a: d001 beq.n 8000330 <MX_SPI2_Init+0x60>
{
Error_Handler();
800032c: f000 f8f0 bl 8000510 <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
8000330: bf00 nop
8000332: bd80 pop {r7, pc}
8000334: 20000054 .word 0x20000054
8000338: 40003800 .word 0x40003800
0800033c <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
800033c: b580 push {r7, lr}
800033e: b08a sub sp, #40 ; 0x28
8000340: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000342: f107 0318 add.w r3, r7, #24
8000346: 2200 movs r2, #0
8000348: 601a str r2, [r3, #0]
800034a: 605a str r2, [r3, #4]
800034c: 609a str r2, [r3, #8]
800034e: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
8000350: 4b3a ldr r3, [pc, #232] ; (800043c <MX_GPIO_Init+0x100>)
8000352: 699b ldr r3, [r3, #24]
8000354: 4a39 ldr r2, [pc, #228] ; (800043c <MX_GPIO_Init+0x100>)
8000356: f043 0308 orr.w r3, r3, #8
800035a: 6193 str r3, [r2, #24]
800035c: 4b37 ldr r3, [pc, #220] ; (800043c <MX_GPIO_Init+0x100>)
800035e: 699b ldr r3, [r3, #24]
8000360: f003 0308 and.w r3, r3, #8
8000364: 617b str r3, [r7, #20]
8000366: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000368: 4b34 ldr r3, [pc, #208] ; (800043c <MX_GPIO_Init+0x100>)
800036a: 699b ldr r3, [r3, #24]
800036c: 4a33 ldr r2, [pc, #204] ; (800043c <MX_GPIO_Init+0x100>)
800036e: f443 7380 orr.w r3, r3, #256 ; 0x100
8000372: 6193 str r3, [r2, #24]
8000374: 4b31 ldr r3, [pc, #196] ; (800043c <MX_GPIO_Init+0x100>)
8000376: 699b ldr r3, [r3, #24]
8000378: f403 7380 and.w r3, r3, #256 ; 0x100
800037c: 613b str r3, [r7, #16]
800037e: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
8000380: 4b2e ldr r3, [pc, #184] ; (800043c <MX_GPIO_Init+0x100>)
8000382: 699b ldr r3, [r3, #24]
8000384: 4a2d ldr r2, [pc, #180] ; (800043c <MX_GPIO_Init+0x100>)
8000386: f043 0340 orr.w r3, r3, #64 ; 0x40
800038a: 6193 str r3, [r2, #24]
800038c: 4b2b ldr r3, [pc, #172] ; (800043c <MX_GPIO_Init+0x100>)
800038e: 699b ldr r3, [r3, #24]
8000390: f003 0340 and.w r3, r3, #64 ; 0x40
8000394: 60fb str r3, [r7, #12]
8000396: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000398: 4b28 ldr r3, [pc, #160] ; (800043c <MX_GPIO_Init+0x100>)
800039a: 699b ldr r3, [r3, #24]
800039c: 4a27 ldr r2, [pc, #156] ; (800043c <MX_GPIO_Init+0x100>)
800039e: f043 0320 orr.w r3, r3, #32
80003a2: 6193 str r3, [r2, #24]
80003a4: 4b25 ldr r3, [pc, #148] ; (800043c <MX_GPIO_Init+0x100>)
80003a6: 699b ldr r3, [r3, #24]
80003a8: f003 0320 and.w r3, r3, #32
80003ac: 60bb str r3, [r7, #8]
80003ae: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80003b0: 4b22 ldr r3, [pc, #136] ; (800043c <MX_GPIO_Init+0x100>)
80003b2: 699b ldr r3, [r3, #24]
80003b4: 4a21 ldr r2, [pc, #132] ; (800043c <MX_GPIO_Init+0x100>)
80003b6: f043 0304 orr.w r3, r3, #4
80003ba: 6193 str r3, [r2, #24]
80003bc: 4b1f ldr r3, [pc, #124] ; (800043c <MX_GPIO_Init+0x100>)
80003be: 699b ldr r3, [r3, #24]
80003c0: f003 0304 and.w r3, r3, #4
80003c4: 607b str r3, [r7, #4]
80003c6: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, LCD_BL_Pin|FLASH_E_Pin, GPIO_PIN_RESET);
80003c8: 2200 movs r2, #0
80003ca: f241 0101 movw r1, #4097 ; 0x1001
80003ce: 481c ldr r0, [pc, #112] ; (8000440 <MX_GPIO_Init+0x104>)
80003d0: f000 fcd2 bl 8000d78 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(SD_E_GPIO_Port, SD_E_Pin, GPIO_PIN_RESET);
80003d4: 2200 movs r2, #0
80003d6: 2104 movs r1, #4
80003d8: 481a ldr r0, [pc, #104] ; (8000444 <MX_GPIO_Init+0x108>)
80003da: f000 fccd bl 8000d78 <HAL_GPIO_WritePin>
/*Configure GPIO pin : LCD_BL_Pin */
GPIO_InitStruct.Pin = LCD_BL_Pin;
80003de: 2301 movs r3, #1
80003e0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80003e2: 2301 movs r3, #1
80003e4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80003e6: 2300 movs r3, #0
80003e8: 623b str r3, [r7, #32]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80003ea: 2302 movs r3, #2
80003ec: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(LCD_BL_GPIO_Port, &GPIO_InitStruct);
80003ee: f107 0318 add.w r3, r7, #24
80003f2: 4619 mov r1, r3
80003f4: 4812 ldr r0, [pc, #72] ; (8000440 <MX_GPIO_Init+0x104>)
80003f6: f000 fb2b bl 8000a50 <HAL_GPIO_Init>
/*Configure GPIO pin : FLASH_E_Pin */
GPIO_InitStruct.Pin = FLASH_E_Pin;
80003fa: f44f 5380 mov.w r3, #4096 ; 0x1000
80003fe: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000400: 2301 movs r3, #1
8000402: 61fb str r3, [r7, #28]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000404: 2300 movs r3, #0
8000406: 623b str r3, [r7, #32]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000408: 2303 movs r3, #3
800040a: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(FLASH_E_GPIO_Port, &GPIO_InitStruct);
800040c: f107 0318 add.w r3, r7, #24
8000410: 4619 mov r1, r3
8000412: 480b ldr r0, [pc, #44] ; (8000440 <MX_GPIO_Init+0x104>)
8000414: f000 fb1c bl 8000a50 <HAL_GPIO_Init>
/*Configure GPIO pin : SD_E_Pin */
GPIO_InitStruct.Pin = SD_E_Pin;
8000418: 2304 movs r3, #4
800041a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800041c: 2301 movs r3, #1
800041e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000420: 2300 movs r3, #0
8000422: 623b str r3, [r7, #32]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000424: 2303 movs r3, #3
8000426: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(SD_E_GPIO_Port, &GPIO_InitStruct);
8000428: f107 0318 add.w r3, r7, #24
800042c: 4619 mov r1, r3
800042e: 4805 ldr r0, [pc, #20] ; (8000444 <MX_GPIO_Init+0x108>)
8000430: f000 fb0e bl 8000a50 <HAL_GPIO_Init>
}
8000434: bf00 nop
8000436: 3728 adds r7, #40 ; 0x28
8000438: 46bd mov sp, r7
800043a: bd80 pop {r7, pc}
800043c: 40021000 .word 0x40021000
8000440: 40010c00 .word 0x40010c00
8000444: 40011400 .word 0x40011400
08000448 <MX_FSMC_Init>:
/* FSMC initialization function */
static void MX_FSMC_Init(void)
{
8000448: b580 push {r7, lr}
800044a: b088 sub sp, #32
800044c: af00 add r7, sp, #0
/* USER CODE BEGIN FSMC_Init 0 */
/* USER CODE END FSMC_Init 0 */
FSMC_NORSRAM_TimingTypeDef Timing = {0};
800044e: 1d3b adds r3, r7, #4
8000450: 2200 movs r2, #0
8000452: 601a str r2, [r3, #0]
8000454: 605a str r2, [r3, #4]
8000456: 609a str r2, [r3, #8]
8000458: 60da str r2, [r3, #12]
800045a: 611a str r2, [r3, #16]
800045c: 615a str r2, [r3, #20]
800045e: 619a str r2, [r3, #24]
/* USER CODE END FSMC_Init 1 */
/** Perform the SRAM1 memory initialization sequence
*/
hsram1.Instance = FSMC_NORSRAM_DEVICE;
8000460: 4b28 ldr r3, [pc, #160] ; (8000504 <MX_FSMC_Init+0xbc>)
8000462: f04f 4220 mov.w r2, #2684354560 ; 0xa0000000
8000466: 601a str r2, [r3, #0]
hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
8000468: 4b26 ldr r3, [pc, #152] ; (8000504 <MX_FSMC_Init+0xbc>)
800046a: 4a27 ldr r2, [pc, #156] ; (8000508 <MX_FSMC_Init+0xc0>)
800046c: 605a str r2, [r3, #4]
/* hsram1.Init */
hsram1.Init.NSBank = FSMC_NORSRAM_BANK4;
800046e: 4b25 ldr r3, [pc, #148] ; (8000504 <MX_FSMC_Init+0xbc>)
8000470: 2206 movs r2, #6
8000472: 609a str r2, [r3, #8]
hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
8000474: 4b23 ldr r3, [pc, #140] ; (8000504 <MX_FSMC_Init+0xbc>)
8000476: 2200 movs r2, #0
8000478: 60da str r2, [r3, #12]
hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
800047a: 4b22 ldr r3, [pc, #136] ; (8000504 <MX_FSMC_Init+0xbc>)
800047c: 2200 movs r2, #0
800047e: 611a str r2, [r3, #16]
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
8000480: 4b20 ldr r3, [pc, #128] ; (8000504 <MX_FSMC_Init+0xbc>)
8000482: 2210 movs r2, #16
8000484: 615a str r2, [r3, #20]
hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
8000486: 4b1f ldr r3, [pc, #124] ; (8000504 <MX_FSMC_Init+0xbc>)
8000488: 2200 movs r2, #0
800048a: 619a str r2, [r3, #24]
hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
800048c: 4b1d ldr r3, [pc, #116] ; (8000504 <MX_FSMC_Init+0xbc>)
800048e: 2200 movs r2, #0
8000490: 61da str r2, [r3, #28]
hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
8000492: 4b1c ldr r3, [pc, #112] ; (8000504 <MX_FSMC_Init+0xbc>)
8000494: 2200 movs r2, #0
8000496: 621a str r2, [r3, #32]
hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
8000498: 4b1a ldr r3, [pc, #104] ; (8000504 <MX_FSMC_Init+0xbc>)
800049a: 2200 movs r2, #0
800049c: 625a str r2, [r3, #36] ; 0x24
hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
800049e: 4b19 ldr r3, [pc, #100] ; (8000504 <MX_FSMC_Init+0xbc>)
80004a0: f44f 5280 mov.w r2, #4096 ; 0x1000
80004a4: 629a str r2, [r3, #40] ; 0x28
hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
80004a6: 4b17 ldr r3, [pc, #92] ; (8000504 <MX_FSMC_Init+0xbc>)
80004a8: 2200 movs r2, #0
80004aa: 62da str r2, [r3, #44] ; 0x2c
hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
80004ac: 4b15 ldr r3, [pc, #84] ; (8000504 <MX_FSMC_Init+0xbc>)
80004ae: 2200 movs r2, #0
80004b0: 631a str r2, [r3, #48] ; 0x30
hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
80004b2: 4b14 ldr r3, [pc, #80] ; (8000504 <MX_FSMC_Init+0xbc>)
80004b4: 2200 movs r2, #0
80004b6: 635a str r2, [r3, #52] ; 0x34
hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
80004b8: 4b12 ldr r3, [pc, #72] ; (8000504 <MX_FSMC_Init+0xbc>)
80004ba: 2200 movs r2, #0
80004bc: 639a str r2, [r3, #56] ; 0x38
/* Timing */
Timing.AddressSetupTime = 0;
80004be: 2300 movs r3, #0
80004c0: 607b str r3, [r7, #4]
Timing.AddressHoldTime = 15;
80004c2: 230f movs r3, #15
80004c4: 60bb str r3, [r7, #8]
Timing.DataSetupTime = 1;
80004c6: 2301 movs r3, #1
80004c8: 60fb str r3, [r7, #12]
Timing.BusTurnAroundDuration = 15;
80004ca: 230f movs r3, #15
80004cc: 613b str r3, [r7, #16]
Timing.CLKDivision = 16;
80004ce: 2310 movs r3, #16
80004d0: 617b str r3, [r7, #20]
Timing.DataLatency = 17;
80004d2: 2311 movs r3, #17
80004d4: 61bb str r3, [r7, #24]
Timing.AccessMode = FSMC_ACCESS_MODE_A;
80004d6: 2300 movs r3, #0
80004d8: 61fb str r3, [r7, #28]
/* ExtTiming */
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
80004da: 1d3b adds r3, r7, #4
80004dc: 2200 movs r2, #0
80004de: 4619 mov r1, r3
80004e0: 4808 ldr r0, [pc, #32] ; (8000504 <MX_FSMC_Init+0xbc>)
80004e2: f001 fdc1 bl 8002068 <HAL_SRAM_Init>
80004e6: 4603 mov r3, r0
80004e8: 2b00 cmp r3, #0
80004ea: d001 beq.n 80004f0 <MX_FSMC_Init+0xa8>
{
Error_Handler( );
80004ec: f000 f810 bl 8000510 <Error_Handler>
}
/** Disconnect NADV
*/
__HAL_AFIO_FSMCNADV_DISCONNECTED();
80004f0: 4b06 ldr r3, [pc, #24] ; (800050c <MX_FSMC_Init+0xc4>)
80004f2: 69db ldr r3, [r3, #28]
80004f4: 4a05 ldr r2, [pc, #20] ; (800050c <MX_FSMC_Init+0xc4>)
80004f6: f443 6380 orr.w r3, r3, #1024 ; 0x400
80004fa: 61d3 str r3, [r2, #28]
/* USER CODE BEGIN FSMC_Init 2 */
/* USER CODE END FSMC_Init 2 */
}
80004fc: bf00 nop
80004fe: 3720 adds r7, #32
8000500: 46bd mov sp, r7
8000502: bd80 pop {r7, pc}
8000504: 200000ac .word 0x200000ac
8000508: a0000104 .word 0xa0000104
800050c: 40010000 .word 0x40010000
08000510 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000510: b480 push {r7}
8000512: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000514: b672 cpsid i
}
8000516: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000518: e7fe b.n 8000518 <Error_Handler+0x8>
...
0800051c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800051c: b480 push {r7}
800051e: b085 sub sp, #20
8000520: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8000522: 4b15 ldr r3, [pc, #84] ; (8000578 <HAL_MspInit+0x5c>)
8000524: 699b ldr r3, [r3, #24]
8000526: 4a14 ldr r2, [pc, #80] ; (8000578 <HAL_MspInit+0x5c>)
8000528: f043 0301 orr.w r3, r3, #1
800052c: 6193 str r3, [r2, #24]
800052e: 4b12 ldr r3, [pc, #72] ; (8000578 <HAL_MspInit+0x5c>)
8000530: 699b ldr r3, [r3, #24]
8000532: f003 0301 and.w r3, r3, #1
8000536: 60bb str r3, [r7, #8]
8000538: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800053a: 4b0f ldr r3, [pc, #60] ; (8000578 <HAL_MspInit+0x5c>)
800053c: 69db ldr r3, [r3, #28]
800053e: 4a0e ldr r2, [pc, #56] ; (8000578 <HAL_MspInit+0x5c>)
8000540: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000544: 61d3 str r3, [r2, #28]
8000546: 4b0c ldr r3, [pc, #48] ; (8000578 <HAL_MspInit+0x5c>)
8000548: 69db ldr r3, [r3, #28]
800054a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800054e: 607b str r3, [r7, #4]
8000550: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8000552: 4b0a ldr r3, [pc, #40] ; (800057c <HAL_MspInit+0x60>)
8000554: 685b ldr r3, [r3, #4]
8000556: 60fb str r3, [r7, #12]
8000558: 68fb ldr r3, [r7, #12]
800055a: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
800055e: 60fb str r3, [r7, #12]
8000560: 68fb ldr r3, [r7, #12]
8000562: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8000566: 60fb str r3, [r7, #12]
8000568: 4a04 ldr r2, [pc, #16] ; (800057c <HAL_MspInit+0x60>)
800056a: 68fb ldr r3, [r7, #12]
800056c: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800056e: bf00 nop
8000570: 3714 adds r7, #20
8000572: 46bd mov sp, r7
8000574: bc80 pop {r7}
8000576: 4770 bx lr
8000578: 40021000 .word 0x40021000
800057c: 40010000 .word 0x40010000
08000580 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8000580: b580 push {r7, lr}
8000582: b088 sub sp, #32
8000584: af00 add r7, sp, #0
8000586: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000588: f107 0310 add.w r3, r7, #16
800058c: 2200 movs r2, #0
800058e: 601a str r2, [r3, #0]
8000590: 605a str r2, [r3, #4]
8000592: 609a str r2, [r3, #8]
8000594: 60da str r2, [r3, #12]
if(hspi->Instance==SPI2)
8000596: 687b ldr r3, [r7, #4]
8000598: 681b ldr r3, [r3, #0]
800059a: 4a1c ldr r2, [pc, #112] ; (800060c <HAL_SPI_MspInit+0x8c>)
800059c: 4293 cmp r3, r2
800059e: d131 bne.n 8000604 <HAL_SPI_MspInit+0x84>
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
80005a0: 4b1b ldr r3, [pc, #108] ; (8000610 <HAL_SPI_MspInit+0x90>)
80005a2: 69db ldr r3, [r3, #28]
80005a4: 4a1a ldr r2, [pc, #104] ; (8000610 <HAL_SPI_MspInit+0x90>)
80005a6: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80005aa: 61d3 str r3, [r2, #28]
80005ac: 4b18 ldr r3, [pc, #96] ; (8000610 <HAL_SPI_MspInit+0x90>)
80005ae: 69db ldr r3, [r3, #28]
80005b0: f403 4380 and.w r3, r3, #16384 ; 0x4000
80005b4: 60fb str r3, [r7, #12]
80005b6: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
80005b8: 4b15 ldr r3, [pc, #84] ; (8000610 <HAL_SPI_MspInit+0x90>)
80005ba: 699b ldr r3, [r3, #24]
80005bc: 4a14 ldr r2, [pc, #80] ; (8000610 <HAL_SPI_MspInit+0x90>)
80005be: f043 0308 orr.w r3, r3, #8
80005c2: 6193 str r3, [r2, #24]
80005c4: 4b12 ldr r3, [pc, #72] ; (8000610 <HAL_SPI_MspInit+0x90>)
80005c6: 699b ldr r3, [r3, #24]
80005c8: f003 0308 and.w r3, r3, #8
80005cc: 60bb str r3, [r7, #8]
80005ce: 68bb ldr r3, [r7, #8]
/**SPI2 GPIO Configuration
PB13 ------> SPI2_SCK
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15;
80005d0: f44f 4320 mov.w r3, #40960 ; 0xa000
80005d4: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80005d6: 2302 movs r3, #2
80005d8: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80005da: 2303 movs r3, #3
80005dc: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80005de: f107 0310 add.w r3, r7, #16
80005e2: 4619 mov r1, r3
80005e4: 480b ldr r0, [pc, #44] ; (8000614 <HAL_SPI_MspInit+0x94>)
80005e6: f000 fa33 bl 8000a50 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_14;
80005ea: f44f 4380 mov.w r3, #16384 ; 0x4000
80005ee: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80005f0: 2300 movs r3, #0
80005f2: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005f4: 2300 movs r3, #0
80005f6: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80005f8: f107 0310 add.w r3, r7, #16
80005fc: 4619 mov r1, r3
80005fe: 4805 ldr r0, [pc, #20] ; (8000614 <HAL_SPI_MspInit+0x94>)
8000600: f000 fa26 bl 8000a50 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8000604: bf00 nop
8000606: 3720 adds r7, #32
8000608: 46bd mov sp, r7
800060a: bd80 pop {r7, pc}
800060c: 40003800 .word 0x40003800
8000610: 40021000 .word 0x40021000
8000614: 40010c00 .word 0x40010c00
08000618 <HAL_FSMC_MspInit>:
}
static uint32_t FSMC_Initialized = 0;
static void HAL_FSMC_MspInit(void){
8000618: b580 push {r7, lr}
800061a: b086 sub sp, #24
800061c: af00 add r7, sp, #0
/* USER CODE BEGIN FSMC_MspInit 0 */
/* USER CODE END FSMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
800061e: f107 0308 add.w r3, r7, #8
8000622: 2200 movs r2, #0
8000624: 601a str r2, [r3, #0]
8000626: 605a str r2, [r3, #4]
8000628: 609a str r2, [r3, #8]
800062a: 60da str r2, [r3, #12]
if (FSMC_Initialized) {
800062c: 4b1f ldr r3, [pc, #124] ; (80006ac <HAL_FSMC_MspInit+0x94>)
800062e: 681b ldr r3, [r3, #0]
8000630: 2b00 cmp r3, #0
8000632: d136 bne.n 80006a2 <HAL_FSMC_MspInit+0x8a>
return;
}
FSMC_Initialized = 1;
8000634: 4b1d ldr r3, [pc, #116] ; (80006ac <HAL_FSMC_MspInit+0x94>)
8000636: 2201 movs r2, #1
8000638: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FSMC_CLK_ENABLE();
800063a: 4b1d ldr r3, [pc, #116] ; (80006b0 <HAL_FSMC_MspInit+0x98>)
800063c: 695b ldr r3, [r3, #20]
800063e: 4a1c ldr r2, [pc, #112] ; (80006b0 <HAL_FSMC_MspInit+0x98>)
8000640: f443 7380 orr.w r3, r3, #256 ; 0x100
8000644: 6153 str r3, [r2, #20]
8000646: 4b1a ldr r3, [pc, #104] ; (80006b0 <HAL_FSMC_MspInit+0x98>)
8000648: 695b ldr r3, [r3, #20]
800064a: f403 7380 and.w r3, r3, #256 ; 0x100
800064e: 607b str r3, [r7, #4]
8000650: 687b ldr r3, [r7, #4]
PD1 ------> FSMC_D3
PD4 ------> FSMC_NOE
PD5 ------> FSMC_NWE
PG12 ------> FSMC_NE4
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_12;
8000652: f241 0301 movw r3, #4097 ; 0x1001
8000656: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000658: 2302 movs r3, #2
800065a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800065c: 2303 movs r3, #3
800065e: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000660: f107 0308 add.w r3, r7, #8
8000664: 4619 mov r1, r3
8000666: 4813 ldr r0, [pc, #76] ; (80006b4 <HAL_FSMC_MspInit+0x9c>)
8000668: f000 f9f2 bl 8000a50 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
800066c: f64f 7380 movw r3, #65408 ; 0xff80
8000670: 60bb str r3, [r7, #8]
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000672: 2302 movs r3, #2
8000674: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000676: 2303 movs r3, #3
8000678: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
800067a: f107 0308 add.w r3, r7, #8
800067e: 4619 mov r1, r3
8000680: 480d ldr r0, [pc, #52] ; (80006b8 <HAL_FSMC_MspInit+0xa0>)
8000682: f000 f9e5 bl 8000a50 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
8000686: f24c 7333 movw r3, #50995 ; 0xc733
800068a: 60bb str r3, [r7, #8]
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4
|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800068c: 2302 movs r3, #2
800068e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000690: 2303 movs r3, #3
8000692: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000694: f107 0308 add.w r3, r7, #8
8000698: 4619 mov r1, r3
800069a: 4808 ldr r0, [pc, #32] ; (80006bc <HAL_FSMC_MspInit+0xa4>)
800069c: f000 f9d8 bl 8000a50 <HAL_GPIO_Init>
80006a0: e000 b.n 80006a4 <HAL_FSMC_MspInit+0x8c>
return;
80006a2: bf00 nop
/* USER CODE BEGIN FSMC_MspInit 1 */
/* USER CODE END FSMC_MspInit 1 */
}
80006a4: 3718 adds r7, #24
80006a6: 46bd mov sp, r7
80006a8: bd80 pop {r7, pc}
80006aa: bf00 nop
80006ac: 20000040 .word 0x20000040
80006b0: 40021000 .word 0x40021000
80006b4: 40012000 .word 0x40012000
80006b8: 40011800 .word 0x40011800
80006bc: 40011400 .word 0x40011400
080006c0 <HAL_SRAM_MspInit>:
void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
80006c0: b580 push {r7, lr}
80006c2: b082 sub sp, #8
80006c4: af00 add r7, sp, #0
80006c6: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SRAM_MspInit 0 */
/* USER CODE END SRAM_MspInit 0 */
HAL_FSMC_MspInit();
80006c8: f7ff ffa6 bl 8000618 <HAL_FSMC_MspInit>
/* USER CODE BEGIN SRAM_MspInit 1 */
/* USER CODE END SRAM_MspInit 1 */
}
80006cc: bf00 nop
80006ce: 3708 adds r7, #8
80006d0: 46bd mov sp, r7
80006d2: bd80 pop {r7, pc}
080006d4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80006d4: b480 push {r7}
80006d6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80006d8: e7fe b.n 80006d8 <NMI_Handler+0x4>
080006da <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80006da: b480 push {r7}
80006dc: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80006de: e7fe b.n 80006de <HardFault_Handler+0x4>
080006e0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80006e0: b480 push {r7}
80006e2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80006e4: e7fe b.n 80006e4 <MemManage_Handler+0x4>
080006e6 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80006e6: b480 push {r7}
80006e8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80006ea: e7fe b.n 80006ea <BusFault_Handler+0x4>
080006ec <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80006ec: b480 push {r7}
80006ee: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80006f0: e7fe b.n 80006f0 <UsageFault_Handler+0x4>
080006f2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80006f2: b480 push {r7}
80006f4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80006f6: bf00 nop
80006f8: 46bd mov sp, r7
80006fa: bc80 pop {r7}
80006fc: 4770 bx lr
080006fe <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80006fe: b480 push {r7}
8000700: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000702: bf00 nop
8000704: 46bd mov sp, r7
8000706: bc80 pop {r7}
8000708: 4770 bx lr
0800070a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800070a: b480 push {r7}
800070c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800070e: bf00 nop
8000710: 46bd mov sp, r7
8000712: bc80 pop {r7}
8000714: 4770 bx lr
08000716 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000716: b580 push {r7, lr}
8000718: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800071a: f000 f875 bl 8000808 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800071e: bf00 nop
8000720: bd80 pop {r7, pc}
08000722 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8000722: b480 push {r7}
8000724: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000726: bf00 nop
8000728: 46bd mov sp, r7
800072a: bc80 pop {r7}
800072c: 4770 bx lr
...
08000730 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8000730: 2100 movs r1, #0
b LoopCopyDataInit
8000732: e003 b.n 800073c <LoopCopyDataInit>
08000734 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8000734: 4b0b ldr r3, [pc, #44] ; (8000764 <LoopFillZerobss+0x14>)
ldr r3, [r3, r1]
8000736: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8000738: 5043 str r3, [r0, r1]
adds r1, r1, #4
800073a: 3104 adds r1, #4
0800073c <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
800073c: 480a ldr r0, [pc, #40] ; (8000768 <LoopFillZerobss+0x18>)
ldr r3, =_edata
800073e: 4b0b ldr r3, [pc, #44] ; (800076c <LoopFillZerobss+0x1c>)
adds r2, r0, r1
8000740: 1842 adds r2, r0, r1
cmp r2, r3
8000742: 429a cmp r2, r3
bcc CopyDataInit
8000744: d3f6 bcc.n 8000734 <CopyDataInit>
ldr r2, =_sbss
8000746: 4a0a ldr r2, [pc, #40] ; (8000770 <LoopFillZerobss+0x20>)
b LoopFillZerobss
8000748: e002 b.n 8000750 <LoopFillZerobss>
0800074a <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
800074a: 2300 movs r3, #0
str r3, [r2], #4
800074c: f842 3b04 str.w r3, [r2], #4
08000750 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8000750: 4b08 ldr r3, [pc, #32] ; (8000774 <LoopFillZerobss+0x24>)
cmp r2, r3
8000752: 429a cmp r2, r3
bcc FillZerobss
8000754: d3f9 bcc.n 800074a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000756: f7ff ffe4 bl 8000722 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800075a: f003 fa4b bl 8003bf4 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800075e: f7ff fd61 bl 8000224 <main>
bx lr
8000762: 4770 bx lr
ldr r3, =_sidata
8000764: 08004704 .word 0x08004704
ldr r0, =_sdata
8000768: 20000000 .word 0x20000000
ldr r3, =_edata
800076c: 20000024 .word 0x20000024
ldr r2, =_sbss
8000770: 20000024 .word 0x20000024
ldr r3, = _ebss
8000774: 20000590 .word 0x20000590
08000778 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000778: e7fe b.n 8000778 <ADC1_2_IRQHandler>
...
0800077c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800077c: b580 push {r7, lr}
800077e: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000780: 4b08 ldr r3, [pc, #32] ; (80007a4 <HAL_Init+0x28>)
8000782: 681b ldr r3, [r3, #0]
8000784: 4a07 ldr r2, [pc, #28] ; (80007a4 <HAL_Init+0x28>)
8000786: f043 0310 orr.w r3, r3, #16
800078a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800078c: 2003 movs r0, #3
800078e: f000 f92b bl 80009e8 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000792: 2000 movs r0, #0
8000794: f000 f808 bl 80007a8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000798: f7ff fec0 bl 800051c <HAL_MspInit>
/* Return function status */
return HAL_OK;
800079c: 2300 movs r3, #0
}
800079e: 4618 mov r0, r3
80007a0: bd80 pop {r7, pc}
80007a2: bf00 nop
80007a4: 40022000 .word 0x40022000
080007a8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80007a8: b580 push {r7, lr}
80007aa: b082 sub sp, #8
80007ac: af00 add r7, sp, #0
80007ae: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80007b0: 4b12 ldr r3, [pc, #72] ; (80007fc <HAL_InitTick+0x54>)
80007b2: 681a ldr r2, [r3, #0]
80007b4: 4b12 ldr r3, [pc, #72] ; (8000800 <HAL_InitTick+0x58>)
80007b6: 781b ldrb r3, [r3, #0]
80007b8: 4619 mov r1, r3
80007ba: f44f 737a mov.w r3, #1000 ; 0x3e8
80007be: fbb3 f3f1 udiv r3, r3, r1
80007c2: fbb2 f3f3 udiv r3, r2, r3
80007c6: 4618 mov r0, r3
80007c8: f000 f935 bl 8000a36 <HAL_SYSTICK_Config>
80007cc: 4603 mov r3, r0
80007ce: 2b00 cmp r3, #0
80007d0: d001 beq.n 80007d6 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
80007d2: 2301 movs r3, #1
80007d4: e00e b.n 80007f4 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80007d6: 687b ldr r3, [r7, #4]
80007d8: 2b0f cmp r3, #15
80007da: d80a bhi.n 80007f2 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80007dc: 2200 movs r2, #0
80007de: 6879 ldr r1, [r7, #4]
80007e0: f04f 30ff mov.w r0, #4294967295
80007e4: f000 f90b bl 80009fe <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80007e8: 4a06 ldr r2, [pc, #24] ; (8000804 <HAL_InitTick+0x5c>)
80007ea: 687b ldr r3, [r7, #4]
80007ec: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80007ee: 2300 movs r3, #0
80007f0: e000 b.n 80007f4 <HAL_InitTick+0x4c>
return HAL_ERROR;
80007f2: 2301 movs r3, #1
}
80007f4: 4618 mov r0, r3
80007f6: 3708 adds r7, #8
80007f8: 46bd mov sp, r7
80007fa: bd80 pop {r7, pc}
80007fc: 20000000 .word 0x20000000
8000800: 20000008 .word 0x20000008
8000804: 20000004 .word 0x20000004
08000808 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000808: b480 push {r7}
800080a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800080c: 4b05 ldr r3, [pc, #20] ; (8000824 <HAL_IncTick+0x1c>)
800080e: 781b ldrb r3, [r3, #0]
8000810: 461a mov r2, r3
8000812: 4b05 ldr r3, [pc, #20] ; (8000828 <HAL_IncTick+0x20>)
8000814: 681b ldr r3, [r3, #0]
8000816: 4413 add r3, r2
8000818: 4a03 ldr r2, [pc, #12] ; (8000828 <HAL_IncTick+0x20>)
800081a: 6013 str r3, [r2, #0]
}
800081c: bf00 nop
800081e: 46bd mov sp, r7
8000820: bc80 pop {r7}
8000822: 4770 bx lr
8000824: 20000008 .word 0x20000008
8000828: 200000f4 .word 0x200000f4
0800082c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800082c: b480 push {r7}
800082e: af00 add r7, sp, #0
return uwTick;
8000830: 4b02 ldr r3, [pc, #8] ; (800083c <HAL_GetTick+0x10>)
8000832: 681b ldr r3, [r3, #0]
}
8000834: 4618 mov r0, r3
8000836: 46bd mov sp, r7
8000838: bc80 pop {r7}
800083a: 4770 bx lr
800083c: 200000f4 .word 0x200000f4
08000840 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000840: b580 push {r7, lr}
8000842: b084 sub sp, #16
8000844: af00 add r7, sp, #0
8000846: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000848: f7ff fff0 bl 800082c <HAL_GetTick>
800084c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
800084e: 687b ldr r3, [r7, #4]
8000850: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000852: 68fb ldr r3, [r7, #12]
8000854: f1b3 3fff cmp.w r3, #4294967295
8000858: d005 beq.n 8000866 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
800085a: 4b0a ldr r3, [pc, #40] ; (8000884 <HAL_Delay+0x44>)
800085c: 781b ldrb r3, [r3, #0]
800085e: 461a mov r2, r3
8000860: 68fb ldr r3, [r7, #12]
8000862: 4413 add r3, r2
8000864: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8000866: bf00 nop
8000868: f7ff ffe0 bl 800082c <HAL_GetTick>
800086c: 4602 mov r2, r0
800086e: 68bb ldr r3, [r7, #8]
8000870: 1ad3 subs r3, r2, r3
8000872: 68fa ldr r2, [r7, #12]
8000874: 429a cmp r2, r3
8000876: d8f7 bhi.n 8000868 <HAL_Delay+0x28>
{
}
}
8000878: bf00 nop
800087a: bf00 nop
800087c: 3710 adds r7, #16
800087e: 46bd mov sp, r7
8000880: bd80 pop {r7, pc}
8000882: bf00 nop
8000884: 20000008 .word 0x20000008
08000888 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000888: b480 push {r7}
800088a: b085 sub sp, #20
800088c: af00 add r7, sp, #0
800088e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000890: 687b ldr r3, [r7, #4]
8000892: f003 0307 and.w r3, r3, #7
8000896: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000898: 4b0c ldr r3, [pc, #48] ; (80008cc <__NVIC_SetPriorityGrouping+0x44>)
800089a: 68db ldr r3, [r3, #12]
800089c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800089e: 68ba ldr r2, [r7, #8]
80008a0: f64f 03ff movw r3, #63743 ; 0xf8ff
80008a4: 4013 ands r3, r2
80008a6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80008a8: 68fb ldr r3, [r7, #12]
80008aa: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80008ac: 68bb ldr r3, [r7, #8]
80008ae: 4313 orrs r3, r2
reg_value = (reg_value |
80008b0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80008b4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80008b8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80008ba: 4a04 ldr r2, [pc, #16] ; (80008cc <__NVIC_SetPriorityGrouping+0x44>)
80008bc: 68bb ldr r3, [r7, #8]
80008be: 60d3 str r3, [r2, #12]
}
80008c0: bf00 nop
80008c2: 3714 adds r7, #20
80008c4: 46bd mov sp, r7
80008c6: bc80 pop {r7}
80008c8: 4770 bx lr
80008ca: bf00 nop
80008cc: e000ed00 .word 0xe000ed00
080008d0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80008d0: b480 push {r7}
80008d2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80008d4: 4b04 ldr r3, [pc, #16] ; (80008e8 <__NVIC_GetPriorityGrouping+0x18>)
80008d6: 68db ldr r3, [r3, #12]
80008d8: 0a1b lsrs r3, r3, #8
80008da: f003 0307 and.w r3, r3, #7
}
80008de: 4618 mov r0, r3
80008e0: 46bd mov sp, r7
80008e2: bc80 pop {r7}
80008e4: 4770 bx lr
80008e6: bf00 nop
80008e8: e000ed00 .word 0xe000ed00
080008ec <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80008ec: b480 push {r7}
80008ee: b083 sub sp, #12
80008f0: af00 add r7, sp, #0
80008f2: 4603 mov r3, r0
80008f4: 6039 str r1, [r7, #0]
80008f6: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80008f8: f997 3007 ldrsb.w r3, [r7, #7]
80008fc: 2b00 cmp r3, #0
80008fe: db0a blt.n 8000916 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000900: 683b ldr r3, [r7, #0]
8000902: b2da uxtb r2, r3
8000904: 490c ldr r1, [pc, #48] ; (8000938 <__NVIC_SetPriority+0x4c>)
8000906: f997 3007 ldrsb.w r3, [r7, #7]
800090a: 0112 lsls r2, r2, #4
800090c: b2d2 uxtb r2, r2
800090e: 440b add r3, r1
8000910: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000914: e00a b.n 800092c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000916: 683b ldr r3, [r7, #0]
8000918: b2da uxtb r2, r3
800091a: 4908 ldr r1, [pc, #32] ; (800093c <__NVIC_SetPriority+0x50>)
800091c: 79fb ldrb r3, [r7, #7]
800091e: f003 030f and.w r3, r3, #15
8000922: 3b04 subs r3, #4
8000924: 0112 lsls r2, r2, #4
8000926: b2d2 uxtb r2, r2
8000928: 440b add r3, r1
800092a: 761a strb r2, [r3, #24]
}
800092c: bf00 nop
800092e: 370c adds r7, #12
8000930: 46bd mov sp, r7
8000932: bc80 pop {r7}
8000934: 4770 bx lr
8000936: bf00 nop
8000938: e000e100 .word 0xe000e100
800093c: e000ed00 .word 0xe000ed00
08000940 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000940: b480 push {r7}
8000942: b089 sub sp, #36 ; 0x24
8000944: af00 add r7, sp, #0
8000946: 60f8 str r0, [r7, #12]
8000948: 60b9 str r1, [r7, #8]
800094a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800094c: 68fb ldr r3, [r7, #12]
800094e: f003 0307 and.w r3, r3, #7
8000952: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000954: 69fb ldr r3, [r7, #28]
8000956: f1c3 0307 rsb r3, r3, #7
800095a: 2b04 cmp r3, #4
800095c: bf28 it cs
800095e: 2304 movcs r3, #4
8000960: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000962: 69fb ldr r3, [r7, #28]
8000964: 3304 adds r3, #4
8000966: 2b06 cmp r3, #6
8000968: d902 bls.n 8000970 <NVIC_EncodePriority+0x30>
800096a: 69fb ldr r3, [r7, #28]
800096c: 3b03 subs r3, #3
800096e: e000 b.n 8000972 <NVIC_EncodePriority+0x32>
8000970: 2300 movs r3, #0
8000972: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000974: f04f 32ff mov.w r2, #4294967295
8000978: 69bb ldr r3, [r7, #24]
800097a: fa02 f303 lsl.w r3, r2, r3
800097e: 43da mvns r2, r3
8000980: 68bb ldr r3, [r7, #8]
8000982: 401a ands r2, r3
8000984: 697b ldr r3, [r7, #20]
8000986: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000988: f04f 31ff mov.w r1, #4294967295
800098c: 697b ldr r3, [r7, #20]
800098e: fa01 f303 lsl.w r3, r1, r3
8000992: 43d9 mvns r1, r3
8000994: 687b ldr r3, [r7, #4]
8000996: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000998: 4313 orrs r3, r2
);
}
800099a: 4618 mov r0, r3
800099c: 3724 adds r7, #36 ; 0x24
800099e: 46bd mov sp, r7
80009a0: bc80 pop {r7}
80009a2: 4770 bx lr
080009a4 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80009a4: b580 push {r7, lr}
80009a6: b082 sub sp, #8
80009a8: af00 add r7, sp, #0
80009aa: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80009ac: 687b ldr r3, [r7, #4]
80009ae: 3b01 subs r3, #1
80009b0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80009b4: d301 bcc.n 80009ba <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80009b6: 2301 movs r3, #1
80009b8: e00f b.n 80009da <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80009ba: 4a0a ldr r2, [pc, #40] ; (80009e4 <SysTick_Config+0x40>)
80009bc: 687b ldr r3, [r7, #4]
80009be: 3b01 subs r3, #1
80009c0: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80009c2: 210f movs r1, #15
80009c4: f04f 30ff mov.w r0, #4294967295
80009c8: f7ff ff90 bl 80008ec <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80009cc: 4b05 ldr r3, [pc, #20] ; (80009e4 <SysTick_Config+0x40>)
80009ce: 2200 movs r2, #0
80009d0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80009d2: 4b04 ldr r3, [pc, #16] ; (80009e4 <SysTick_Config+0x40>)
80009d4: 2207 movs r2, #7
80009d6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80009d8: 2300 movs r3, #0
}
80009da: 4618 mov r0, r3
80009dc: 3708 adds r7, #8
80009de: 46bd mov sp, r7
80009e0: bd80 pop {r7, pc}
80009e2: bf00 nop
80009e4: e000e010 .word 0xe000e010
080009e8 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80009e8: b580 push {r7, lr}
80009ea: b082 sub sp, #8
80009ec: af00 add r7, sp, #0
80009ee: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80009f0: 6878 ldr r0, [r7, #4]
80009f2: f7ff ff49 bl 8000888 <__NVIC_SetPriorityGrouping>
}
80009f6: bf00 nop
80009f8: 3708 adds r7, #8
80009fa: 46bd mov sp, r7
80009fc: bd80 pop {r7, pc}
080009fe <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80009fe: b580 push {r7, lr}
8000a00: b086 sub sp, #24
8000a02: af00 add r7, sp, #0
8000a04: 4603 mov r3, r0
8000a06: 60b9 str r1, [r7, #8]
8000a08: 607a str r2, [r7, #4]
8000a0a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000a0c: 2300 movs r3, #0
8000a0e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000a10: f7ff ff5e bl 80008d0 <__NVIC_GetPriorityGrouping>
8000a14: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000a16: 687a ldr r2, [r7, #4]
8000a18: 68b9 ldr r1, [r7, #8]
8000a1a: 6978 ldr r0, [r7, #20]
8000a1c: f7ff ff90 bl 8000940 <NVIC_EncodePriority>
8000a20: 4602 mov r2, r0
8000a22: f997 300f ldrsb.w r3, [r7, #15]
8000a26: 4611 mov r1, r2
8000a28: 4618 mov r0, r3
8000a2a: f7ff ff5f bl 80008ec <__NVIC_SetPriority>
}
8000a2e: bf00 nop
8000a30: 3718 adds r7, #24
8000a32: 46bd mov sp, r7
8000a34: bd80 pop {r7, pc}
08000a36 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000a36: b580 push {r7, lr}
8000a38: b082 sub sp, #8
8000a3a: af00 add r7, sp, #0
8000a3c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000a3e: 6878 ldr r0, [r7, #4]
8000a40: f7ff ffb0 bl 80009a4 <SysTick_Config>
8000a44: 4603 mov r3, r0
}
8000a46: 4618 mov r0, r3
8000a48: 3708 adds r7, #8
8000a4a: 46bd mov sp, r7
8000a4c: bd80 pop {r7, pc}
...
08000a50 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000a50: b480 push {r7}
8000a52: b08b sub sp, #44 ; 0x2c
8000a54: af00 add r7, sp, #0
8000a56: 6078 str r0, [r7, #4]
8000a58: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000a5a: 2300 movs r3, #0
8000a5c: 627b str r3, [r7, #36] ; 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8000a5e: 2300 movs r3, #0
8000a60: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000a62: e179 b.n 8000d58 <HAL_GPIO_Init+0x308>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8000a64: 2201 movs r2, #1
8000a66: 6a7b ldr r3, [r7, #36] ; 0x24
8000a68: fa02 f303 lsl.w r3, r2, r3
8000a6c: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000a6e: 683b ldr r3, [r7, #0]
8000a70: 681b ldr r3, [r3, #0]
8000a72: 69fa ldr r2, [r7, #28]
8000a74: 4013 ands r3, r2
8000a76: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8000a78: 69ba ldr r2, [r7, #24]
8000a7a: 69fb ldr r3, [r7, #28]
8000a7c: 429a cmp r2, r3
8000a7e: f040 8168 bne.w 8000d52 <HAL_GPIO_Init+0x302>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
8000a82: 683b ldr r3, [r7, #0]
8000a84: 685b ldr r3, [r3, #4]
8000a86: 4aa0 ldr r2, [pc, #640] ; (8000d08 <HAL_GPIO_Init+0x2b8>)
8000a88: 4293 cmp r3, r2
8000a8a: d05e beq.n 8000b4a <HAL_GPIO_Init+0xfa>
8000a8c: 4a9e ldr r2, [pc, #632] ; (8000d08 <HAL_GPIO_Init+0x2b8>)
8000a8e: 4293 cmp r3, r2
8000a90: d875 bhi.n 8000b7e <HAL_GPIO_Init+0x12e>
8000a92: 4a9e ldr r2, [pc, #632] ; (8000d0c <HAL_GPIO_Init+0x2bc>)
8000a94: 4293 cmp r3, r2
8000a96: d058 beq.n 8000b4a <HAL_GPIO_Init+0xfa>
8000a98: 4a9c ldr r2, [pc, #624] ; (8000d0c <HAL_GPIO_Init+0x2bc>)
8000a9a: 4293 cmp r3, r2
8000a9c: d86f bhi.n 8000b7e <HAL_GPIO_Init+0x12e>
8000a9e: 4a9c ldr r2, [pc, #624] ; (8000d10 <HAL_GPIO_Init+0x2c0>)
8000aa0: 4293 cmp r3, r2
8000aa2: d052 beq.n 8000b4a <HAL_GPIO_Init+0xfa>
8000aa4: 4a9a ldr r2, [pc, #616] ; (8000d10 <HAL_GPIO_Init+0x2c0>)
8000aa6: 4293 cmp r3, r2
8000aa8: d869 bhi.n 8000b7e <HAL_GPIO_Init+0x12e>
8000aaa: 4a9a ldr r2, [pc, #616] ; (8000d14 <HAL_GPIO_Init+0x2c4>)
8000aac: 4293 cmp r3, r2
8000aae: d04c beq.n 8000b4a <HAL_GPIO_Init+0xfa>
8000ab0: 4a98 ldr r2, [pc, #608] ; (8000d14 <HAL_GPIO_Init+0x2c4>)
8000ab2: 4293 cmp r3, r2
8000ab4: d863 bhi.n 8000b7e <HAL_GPIO_Init+0x12e>
8000ab6: 4a98 ldr r2, [pc, #608] ; (8000d18 <HAL_GPIO_Init+0x2c8>)
8000ab8: 4293 cmp r3, r2
8000aba: d046 beq.n 8000b4a <HAL_GPIO_Init+0xfa>
8000abc: 4a96 ldr r2, [pc, #600] ; (8000d18 <HAL_GPIO_Init+0x2c8>)
8000abe: 4293 cmp r3, r2
8000ac0: d85d bhi.n 8000b7e <HAL_GPIO_Init+0x12e>
8000ac2: 2b12 cmp r3, #18
8000ac4: d82a bhi.n 8000b1c <HAL_GPIO_Init+0xcc>
8000ac6: 2b12 cmp r3, #18
8000ac8: d859 bhi.n 8000b7e <HAL_GPIO_Init+0x12e>
8000aca: a201 add r2, pc, #4 ; (adr r2, 8000ad0 <HAL_GPIO_Init+0x80>)
8000acc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000ad0: 08000b4b .word 0x08000b4b
8000ad4: 08000b25 .word 0x08000b25
8000ad8: 08000b37 .word 0x08000b37
8000adc: 08000b79 .word 0x08000b79
8000ae0: 08000b7f .word 0x08000b7f
8000ae4: 08000b7f .word 0x08000b7f
8000ae8: 08000b7f .word 0x08000b7f
8000aec: 08000b7f .word 0x08000b7f
8000af0: 08000b7f .word 0x08000b7f
8000af4: 08000b7f .word 0x08000b7f
8000af8: 08000b7f .word 0x08000b7f
8000afc: 08000b7f .word 0x08000b7f
8000b00: 08000b7f .word 0x08000b7f
8000b04: 08000b7f .word 0x08000b7f
8000b08: 08000b7f .word 0x08000b7f
8000b0c: 08000b7f .word 0x08000b7f
8000b10: 08000b7f .word 0x08000b7f
8000b14: 08000b2d .word 0x08000b2d
8000b18: 08000b41 .word 0x08000b41
8000b1c: 4a7f ldr r2, [pc, #508] ; (8000d1c <HAL_GPIO_Init+0x2cc>)
8000b1e: 4293 cmp r3, r2
8000b20: d013 beq.n 8000b4a <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8000b22: e02c b.n 8000b7e <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8000b24: 683b ldr r3, [r7, #0]
8000b26: 68db ldr r3, [r3, #12]
8000b28: 623b str r3, [r7, #32]
break;
8000b2a: e029 b.n 8000b80 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8000b2c: 683b ldr r3, [r7, #0]
8000b2e: 68db ldr r3, [r3, #12]
8000b30: 3304 adds r3, #4
8000b32: 623b str r3, [r7, #32]
break;
8000b34: e024 b.n 8000b80 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8000b36: 683b ldr r3, [r7, #0]
8000b38: 68db ldr r3, [r3, #12]
8000b3a: 3308 adds r3, #8
8000b3c: 623b str r3, [r7, #32]
break;
8000b3e: e01f b.n 8000b80 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8000b40: 683b ldr r3, [r7, #0]
8000b42: 68db ldr r3, [r3, #12]
8000b44: 330c adds r3, #12
8000b46: 623b str r3, [r7, #32]
break;
8000b48: e01a b.n 8000b80 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8000b4a: 683b ldr r3, [r7, #0]
8000b4c: 689b ldr r3, [r3, #8]
8000b4e: 2b00 cmp r3, #0
8000b50: d102 bne.n 8000b58 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8000b52: 2304 movs r3, #4
8000b54: 623b str r3, [r7, #32]
break;
8000b56: e013 b.n 8000b80 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8000b58: 683b ldr r3, [r7, #0]
8000b5a: 689b ldr r3, [r3, #8]
8000b5c: 2b01 cmp r3, #1
8000b5e: d105 bne.n 8000b6c <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000b60: 2308 movs r3, #8
8000b62: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8000b64: 687b ldr r3, [r7, #4]
8000b66: 69fa ldr r2, [r7, #28]
8000b68: 611a str r2, [r3, #16]
break;
8000b6a: e009 b.n 8000b80 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000b6c: 2308 movs r3, #8
8000b6e: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8000b70: 687b ldr r3, [r7, #4]
8000b72: 69fa ldr r2, [r7, #28]
8000b74: 615a str r2, [r3, #20]
break;
8000b76: e003 b.n 8000b80 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8000b78: 2300 movs r3, #0
8000b7a: 623b str r3, [r7, #32]
break;
8000b7c: e000 b.n 8000b80 <HAL_GPIO_Init+0x130>
break;
8000b7e: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8000b80: 69bb ldr r3, [r7, #24]
8000b82: 2bff cmp r3, #255 ; 0xff
8000b84: d801 bhi.n 8000b8a <HAL_GPIO_Init+0x13a>
8000b86: 687b ldr r3, [r7, #4]
8000b88: e001 b.n 8000b8e <HAL_GPIO_Init+0x13e>
8000b8a: 687b ldr r3, [r7, #4]
8000b8c: 3304 adds r3, #4
8000b8e: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8000b90: 69bb ldr r3, [r7, #24]
8000b92: 2bff cmp r3, #255 ; 0xff
8000b94: d802 bhi.n 8000b9c <HAL_GPIO_Init+0x14c>
8000b96: 6a7b ldr r3, [r7, #36] ; 0x24
8000b98: 009b lsls r3, r3, #2
8000b9a: e002 b.n 8000ba2 <HAL_GPIO_Init+0x152>
8000b9c: 6a7b ldr r3, [r7, #36] ; 0x24
8000b9e: 3b08 subs r3, #8
8000ba0: 009b lsls r3, r3, #2
8000ba2: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8000ba4: 697b ldr r3, [r7, #20]
8000ba6: 681a ldr r2, [r3, #0]
8000ba8: 210f movs r1, #15
8000baa: 693b ldr r3, [r7, #16]
8000bac: fa01 f303 lsl.w r3, r1, r3
8000bb0: 43db mvns r3, r3
8000bb2: 401a ands r2, r3
8000bb4: 6a39 ldr r1, [r7, #32]
8000bb6: 693b ldr r3, [r7, #16]
8000bb8: fa01 f303 lsl.w r3, r1, r3
8000bbc: 431a orrs r2, r3
8000bbe: 697b ldr r3, [r7, #20]
8000bc0: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8000bc2: 683b ldr r3, [r7, #0]
8000bc4: 685b ldr r3, [r3, #4]
8000bc6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000bca: 2b00 cmp r3, #0
8000bcc: f000 80c1 beq.w 8000d52 <HAL_GPIO_Init+0x302>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8000bd0: 4b53 ldr r3, [pc, #332] ; (8000d20 <HAL_GPIO_Init+0x2d0>)
8000bd2: 699b ldr r3, [r3, #24]
8000bd4: 4a52 ldr r2, [pc, #328] ; (8000d20 <HAL_GPIO_Init+0x2d0>)
8000bd6: f043 0301 orr.w r3, r3, #1
8000bda: 6193 str r3, [r2, #24]
8000bdc: 4b50 ldr r3, [pc, #320] ; (8000d20 <HAL_GPIO_Init+0x2d0>)
8000bde: 699b ldr r3, [r3, #24]
8000be0: f003 0301 and.w r3, r3, #1
8000be4: 60bb str r3, [r7, #8]
8000be6: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8000be8: 4a4e ldr r2, [pc, #312] ; (8000d24 <HAL_GPIO_Init+0x2d4>)
8000bea: 6a7b ldr r3, [r7, #36] ; 0x24
8000bec: 089b lsrs r3, r3, #2
8000bee: 3302 adds r3, #2
8000bf0: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000bf4: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8000bf6: 6a7b ldr r3, [r7, #36] ; 0x24
8000bf8: f003 0303 and.w r3, r3, #3
8000bfc: 009b lsls r3, r3, #2
8000bfe: 220f movs r2, #15
8000c00: fa02 f303 lsl.w r3, r2, r3
8000c04: 43db mvns r3, r3
8000c06: 68fa ldr r2, [r7, #12]
8000c08: 4013 ands r3, r2
8000c0a: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8000c0c: 687b ldr r3, [r7, #4]
8000c0e: 4a46 ldr r2, [pc, #280] ; (8000d28 <HAL_GPIO_Init+0x2d8>)
8000c10: 4293 cmp r3, r2
8000c12: d01f beq.n 8000c54 <HAL_GPIO_Init+0x204>
8000c14: 687b ldr r3, [r7, #4]
8000c16: 4a45 ldr r2, [pc, #276] ; (8000d2c <HAL_GPIO_Init+0x2dc>)
8000c18: 4293 cmp r3, r2
8000c1a: d019 beq.n 8000c50 <HAL_GPIO_Init+0x200>
8000c1c: 687b ldr r3, [r7, #4]
8000c1e: 4a44 ldr r2, [pc, #272] ; (8000d30 <HAL_GPIO_Init+0x2e0>)
8000c20: 4293 cmp r3, r2
8000c22: d013 beq.n 8000c4c <HAL_GPIO_Init+0x1fc>
8000c24: 687b ldr r3, [r7, #4]
8000c26: 4a43 ldr r2, [pc, #268] ; (8000d34 <HAL_GPIO_Init+0x2e4>)
8000c28: 4293 cmp r3, r2
8000c2a: d00d beq.n 8000c48 <HAL_GPIO_Init+0x1f8>
8000c2c: 687b ldr r3, [r7, #4]
8000c2e: 4a42 ldr r2, [pc, #264] ; (8000d38 <HAL_GPIO_Init+0x2e8>)
8000c30: 4293 cmp r3, r2
8000c32: d007 beq.n 8000c44 <HAL_GPIO_Init+0x1f4>
8000c34: 687b ldr r3, [r7, #4]
8000c36: 4a41 ldr r2, [pc, #260] ; (8000d3c <HAL_GPIO_Init+0x2ec>)
8000c38: 4293 cmp r3, r2
8000c3a: d101 bne.n 8000c40 <HAL_GPIO_Init+0x1f0>
8000c3c: 2305 movs r3, #5
8000c3e: e00a b.n 8000c56 <HAL_GPIO_Init+0x206>
8000c40: 2306 movs r3, #6
8000c42: e008 b.n 8000c56 <HAL_GPIO_Init+0x206>
8000c44: 2304 movs r3, #4
8000c46: e006 b.n 8000c56 <HAL_GPIO_Init+0x206>
8000c48: 2303 movs r3, #3
8000c4a: e004 b.n 8000c56 <HAL_GPIO_Init+0x206>
8000c4c: 2302 movs r3, #2
8000c4e: e002 b.n 8000c56 <HAL_GPIO_Init+0x206>
8000c50: 2301 movs r3, #1
8000c52: e000 b.n 8000c56 <HAL_GPIO_Init+0x206>
8000c54: 2300 movs r3, #0
8000c56: 6a7a ldr r2, [r7, #36] ; 0x24
8000c58: f002 0203 and.w r2, r2, #3
8000c5c: 0092 lsls r2, r2, #2
8000c5e: 4093 lsls r3, r2
8000c60: 68fa ldr r2, [r7, #12]
8000c62: 4313 orrs r3, r2
8000c64: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8000c66: 492f ldr r1, [pc, #188] ; (8000d24 <HAL_GPIO_Init+0x2d4>)
8000c68: 6a7b ldr r3, [r7, #36] ; 0x24
8000c6a: 089b lsrs r3, r3, #2
8000c6c: 3302 adds r3, #2
8000c6e: 68fa ldr r2, [r7, #12]
8000c70: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000c74: 683b ldr r3, [r7, #0]
8000c76: 685b ldr r3, [r3, #4]
8000c78: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000c7c: 2b00 cmp r3, #0
8000c7e: d006 beq.n 8000c8e <HAL_GPIO_Init+0x23e>
{
SET_BIT(EXTI->IMR, iocurrent);
8000c80: 4b2f ldr r3, [pc, #188] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000c82: 681a ldr r2, [r3, #0]
8000c84: 492e ldr r1, [pc, #184] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000c86: 69bb ldr r3, [r7, #24]
8000c88: 4313 orrs r3, r2
8000c8a: 600b str r3, [r1, #0]
8000c8c: e006 b.n 8000c9c <HAL_GPIO_Init+0x24c>
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8000c8e: 4b2c ldr r3, [pc, #176] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000c90: 681a ldr r2, [r3, #0]
8000c92: 69bb ldr r3, [r7, #24]
8000c94: 43db mvns r3, r3
8000c96: 492a ldr r1, [pc, #168] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000c98: 4013 ands r3, r2
8000c9a: 600b str r3, [r1, #0]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000c9c: 683b ldr r3, [r7, #0]
8000c9e: 685b ldr r3, [r3, #4]
8000ca0: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000ca4: 2b00 cmp r3, #0
8000ca6: d006 beq.n 8000cb6 <HAL_GPIO_Init+0x266>
{
SET_BIT(EXTI->EMR, iocurrent);
8000ca8: 4b25 ldr r3, [pc, #148] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000caa: 685a ldr r2, [r3, #4]
8000cac: 4924 ldr r1, [pc, #144] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cae: 69bb ldr r3, [r7, #24]
8000cb0: 4313 orrs r3, r2
8000cb2: 604b str r3, [r1, #4]
8000cb4: e006 b.n 8000cc4 <HAL_GPIO_Init+0x274>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8000cb6: 4b22 ldr r3, [pc, #136] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cb8: 685a ldr r2, [r3, #4]
8000cba: 69bb ldr r3, [r7, #24]
8000cbc: 43db mvns r3, r3
8000cbe: 4920 ldr r1, [pc, #128] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cc0: 4013 ands r3, r2
8000cc2: 604b str r3, [r1, #4]
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000cc4: 683b ldr r3, [r7, #0]
8000cc6: 685b ldr r3, [r3, #4]
8000cc8: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000ccc: 2b00 cmp r3, #0
8000cce: d006 beq.n 8000cde <HAL_GPIO_Init+0x28e>
{
SET_BIT(EXTI->RTSR, iocurrent);
8000cd0: 4b1b ldr r3, [pc, #108] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cd2: 689a ldr r2, [r3, #8]
8000cd4: 491a ldr r1, [pc, #104] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cd6: 69bb ldr r3, [r7, #24]
8000cd8: 4313 orrs r3, r2
8000cda: 608b str r3, [r1, #8]
8000cdc: e006 b.n 8000cec <HAL_GPIO_Init+0x29c>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8000cde: 4b18 ldr r3, [pc, #96] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000ce0: 689a ldr r2, [r3, #8]
8000ce2: 69bb ldr r3, [r7, #24]
8000ce4: 43db mvns r3, r3
8000ce6: 4916 ldr r1, [pc, #88] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000ce8: 4013 ands r3, r2
8000cea: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000cec: 683b ldr r3, [r7, #0]
8000cee: 685b ldr r3, [r3, #4]
8000cf0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000cf4: 2b00 cmp r3, #0
8000cf6: d025 beq.n 8000d44 <HAL_GPIO_Init+0x2f4>
{
SET_BIT(EXTI->FTSR, iocurrent);
8000cf8: 4b11 ldr r3, [pc, #68] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cfa: 68da ldr r2, [r3, #12]
8000cfc: 4910 ldr r1, [pc, #64] ; (8000d40 <HAL_GPIO_Init+0x2f0>)
8000cfe: 69bb ldr r3, [r7, #24]
8000d00: 4313 orrs r3, r2
8000d02: 60cb str r3, [r1, #12]
8000d04: e025 b.n 8000d52 <HAL_GPIO_Init+0x302>
8000d06: bf00 nop
8000d08: 10320000 .word 0x10320000
8000d0c: 10310000 .word 0x10310000
8000d10: 10220000 .word 0x10220000
8000d14: 10210000 .word 0x10210000
8000d18: 10120000 .word 0x10120000
8000d1c: 10110000 .word 0x10110000
8000d20: 40021000 .word 0x40021000
8000d24: 40010000 .word 0x40010000
8000d28: 40010800 .word 0x40010800
8000d2c: 40010c00 .word 0x40010c00
8000d30: 40011000 .word 0x40011000
8000d34: 40011400 .word 0x40011400
8000d38: 40011800 .word 0x40011800
8000d3c: 40011c00 .word 0x40011c00
8000d40: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8000d44: 4b0b ldr r3, [pc, #44] ; (8000d74 <HAL_GPIO_Init+0x324>)
8000d46: 68da ldr r2, [r3, #12]
8000d48: 69bb ldr r3, [r7, #24]
8000d4a: 43db mvns r3, r3
8000d4c: 4909 ldr r1, [pc, #36] ; (8000d74 <HAL_GPIO_Init+0x324>)
8000d4e: 4013 ands r3, r2
8000d50: 60cb str r3, [r1, #12]
}
}
}
position++;
8000d52: 6a7b ldr r3, [r7, #36] ; 0x24
8000d54: 3301 adds r3, #1
8000d56: 627b str r3, [r7, #36] ; 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000d58: 683b ldr r3, [r7, #0]
8000d5a: 681a ldr r2, [r3, #0]
8000d5c: 6a7b ldr r3, [r7, #36] ; 0x24
8000d5e: fa22 f303 lsr.w r3, r2, r3
8000d62: 2b00 cmp r3, #0
8000d64: f47f ae7e bne.w 8000a64 <HAL_GPIO_Init+0x14>
}
}
8000d68: bf00 nop
8000d6a: bf00 nop
8000d6c: 372c adds r7, #44 ; 0x2c
8000d6e: 46bd mov sp, r7
8000d70: bc80 pop {r7}
8000d72: 4770 bx lr
8000d74: 40010400 .word 0x40010400
08000d78 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000d78: b480 push {r7}
8000d7a: b083 sub sp, #12
8000d7c: af00 add r7, sp, #0
8000d7e: 6078 str r0, [r7, #4]
8000d80: 460b mov r3, r1
8000d82: 807b strh r3, [r7, #2]
8000d84: 4613 mov r3, r2
8000d86: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8000d88: 787b ldrb r3, [r7, #1]
8000d8a: 2b00 cmp r3, #0
8000d8c: d003 beq.n 8000d96 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8000d8e: 887a ldrh r2, [r7, #2]
8000d90: 687b ldr r3, [r7, #4]
8000d92: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8000d94: e003 b.n 8000d9e <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8000d96: 887b ldrh r3, [r7, #2]
8000d98: 041a lsls r2, r3, #16
8000d9a: 687b ldr r3, [r7, #4]
8000d9c: 611a str r2, [r3, #16]
}
8000d9e: bf00 nop
8000da0: 370c adds r7, #12
8000da2: 46bd mov sp, r7
8000da4: bc80 pop {r7}
8000da6: 4770 bx lr
08000da8 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000da8: b580 push {r7, lr}
8000daa: b086 sub sp, #24
8000dac: af00 add r7, sp, #0
8000dae: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000db0: 687b ldr r3, [r7, #4]
8000db2: 2b00 cmp r3, #0
8000db4: d101 bne.n 8000dba <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000db6: 2301 movs r3, #1
8000db8: e26c b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000dba: 687b ldr r3, [r7, #4]
8000dbc: 681b ldr r3, [r3, #0]
8000dbe: f003 0301 and.w r3, r3, #1
8000dc2: 2b00 cmp r3, #0
8000dc4: f000 8087 beq.w 8000ed6 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000dc8: 4b92 ldr r3, [pc, #584] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000dca: 685b ldr r3, [r3, #4]
8000dcc: f003 030c and.w r3, r3, #12
8000dd0: 2b04 cmp r3, #4
8000dd2: d00c beq.n 8000dee <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000dd4: 4b8f ldr r3, [pc, #572] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000dd6: 685b ldr r3, [r3, #4]
8000dd8: f003 030c and.w r3, r3, #12
8000ddc: 2b08 cmp r3, #8
8000dde: d112 bne.n 8000e06 <HAL_RCC_OscConfig+0x5e>
8000de0: 4b8c ldr r3, [pc, #560] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000de2: 685b ldr r3, [r3, #4]
8000de4: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000de8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000dec: d10b bne.n 8000e06 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000dee: 4b89 ldr r3, [pc, #548] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000df0: 681b ldr r3, [r3, #0]
8000df2: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000df6: 2b00 cmp r3, #0
8000df8: d06c beq.n 8000ed4 <HAL_RCC_OscConfig+0x12c>
8000dfa: 687b ldr r3, [r7, #4]
8000dfc: 685b ldr r3, [r3, #4]
8000dfe: 2b00 cmp r3, #0
8000e00: d168 bne.n 8000ed4 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000e02: 2301 movs r3, #1
8000e04: e246 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000e06: 687b ldr r3, [r7, #4]
8000e08: 685b ldr r3, [r3, #4]
8000e0a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000e0e: d106 bne.n 8000e1e <HAL_RCC_OscConfig+0x76>
8000e10: 4b80 ldr r3, [pc, #512] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e12: 681b ldr r3, [r3, #0]
8000e14: 4a7f ldr r2, [pc, #508] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e16: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000e1a: 6013 str r3, [r2, #0]
8000e1c: e02e b.n 8000e7c <HAL_RCC_OscConfig+0xd4>
8000e1e: 687b ldr r3, [r7, #4]
8000e20: 685b ldr r3, [r3, #4]
8000e22: 2b00 cmp r3, #0
8000e24: d10c bne.n 8000e40 <HAL_RCC_OscConfig+0x98>
8000e26: 4b7b ldr r3, [pc, #492] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e28: 681b ldr r3, [r3, #0]
8000e2a: 4a7a ldr r2, [pc, #488] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e2c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000e30: 6013 str r3, [r2, #0]
8000e32: 4b78 ldr r3, [pc, #480] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e34: 681b ldr r3, [r3, #0]
8000e36: 4a77 ldr r2, [pc, #476] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e38: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000e3c: 6013 str r3, [r2, #0]
8000e3e: e01d b.n 8000e7c <HAL_RCC_OscConfig+0xd4>
8000e40: 687b ldr r3, [r7, #4]
8000e42: 685b ldr r3, [r3, #4]
8000e44: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000e48: d10c bne.n 8000e64 <HAL_RCC_OscConfig+0xbc>
8000e4a: 4b72 ldr r3, [pc, #456] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e4c: 681b ldr r3, [r3, #0]
8000e4e: 4a71 ldr r2, [pc, #452] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e50: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000e54: 6013 str r3, [r2, #0]
8000e56: 4b6f ldr r3, [pc, #444] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e58: 681b ldr r3, [r3, #0]
8000e5a: 4a6e ldr r2, [pc, #440] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e5c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000e60: 6013 str r3, [r2, #0]
8000e62: e00b b.n 8000e7c <HAL_RCC_OscConfig+0xd4>
8000e64: 4b6b ldr r3, [pc, #428] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e66: 681b ldr r3, [r3, #0]
8000e68: 4a6a ldr r2, [pc, #424] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e6a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000e6e: 6013 str r3, [r2, #0]
8000e70: 4b68 ldr r3, [pc, #416] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e72: 681b ldr r3, [r3, #0]
8000e74: 4a67 ldr r2, [pc, #412] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000e76: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000e7a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000e7c: 687b ldr r3, [r7, #4]
8000e7e: 685b ldr r3, [r3, #4]
8000e80: 2b00 cmp r3, #0
8000e82: d013 beq.n 8000eac <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e84: f7ff fcd2 bl 800082c <HAL_GetTick>
8000e88: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000e8a: e008 b.n 8000e9e <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000e8c: f7ff fcce bl 800082c <HAL_GetTick>
8000e90: 4602 mov r2, r0
8000e92: 693b ldr r3, [r7, #16]
8000e94: 1ad3 subs r3, r2, r3
8000e96: 2b64 cmp r3, #100 ; 0x64
8000e98: d901 bls.n 8000e9e <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000e9a: 2303 movs r3, #3
8000e9c: e1fa b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000e9e: 4b5d ldr r3, [pc, #372] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000ea0: 681b ldr r3, [r3, #0]
8000ea2: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000ea6: 2b00 cmp r3, #0
8000ea8: d0f0 beq.n 8000e8c <HAL_RCC_OscConfig+0xe4>
8000eaa: e014 b.n 8000ed6 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000eac: f7ff fcbe bl 800082c <HAL_GetTick>
8000eb0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000eb2: e008 b.n 8000ec6 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000eb4: f7ff fcba bl 800082c <HAL_GetTick>
8000eb8: 4602 mov r2, r0
8000eba: 693b ldr r3, [r7, #16]
8000ebc: 1ad3 subs r3, r2, r3
8000ebe: 2b64 cmp r3, #100 ; 0x64
8000ec0: d901 bls.n 8000ec6 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000ec2: 2303 movs r3, #3
8000ec4: e1e6 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000ec6: 4b53 ldr r3, [pc, #332] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000ec8: 681b ldr r3, [r3, #0]
8000eca: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000ece: 2b00 cmp r3, #0
8000ed0: d1f0 bne.n 8000eb4 <HAL_RCC_OscConfig+0x10c>
8000ed2: e000 b.n 8000ed6 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000ed4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000ed6: 687b ldr r3, [r7, #4]
8000ed8: 681b ldr r3, [r3, #0]
8000eda: f003 0302 and.w r3, r3, #2
8000ede: 2b00 cmp r3, #0
8000ee0: d063 beq.n 8000faa <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000ee2: 4b4c ldr r3, [pc, #304] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000ee4: 685b ldr r3, [r3, #4]
8000ee6: f003 030c and.w r3, r3, #12
8000eea: 2b00 cmp r3, #0
8000eec: d00b beq.n 8000f06 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8000eee: 4b49 ldr r3, [pc, #292] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000ef0: 685b ldr r3, [r3, #4]
8000ef2: f003 030c and.w r3, r3, #12
8000ef6: 2b08 cmp r3, #8
8000ef8: d11c bne.n 8000f34 <HAL_RCC_OscConfig+0x18c>
8000efa: 4b46 ldr r3, [pc, #280] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000efc: 685b ldr r3, [r3, #4]
8000efe: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000f02: 2b00 cmp r3, #0
8000f04: d116 bne.n 8000f34 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000f06: 4b43 ldr r3, [pc, #268] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000f08: 681b ldr r3, [r3, #0]
8000f0a: f003 0302 and.w r3, r3, #2
8000f0e: 2b00 cmp r3, #0
8000f10: d005 beq.n 8000f1e <HAL_RCC_OscConfig+0x176>
8000f12: 687b ldr r3, [r7, #4]
8000f14: 691b ldr r3, [r3, #16]
8000f16: 2b01 cmp r3, #1
8000f18: d001 beq.n 8000f1e <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000f1a: 2301 movs r3, #1
8000f1c: e1ba b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000f1e: 4b3d ldr r3, [pc, #244] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000f20: 681b ldr r3, [r3, #0]
8000f22: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000f26: 687b ldr r3, [r7, #4]
8000f28: 695b ldr r3, [r3, #20]
8000f2a: 00db lsls r3, r3, #3
8000f2c: 4939 ldr r1, [pc, #228] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000f2e: 4313 orrs r3, r2
8000f30: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000f32: e03a b.n 8000faa <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000f34: 687b ldr r3, [r7, #4]
8000f36: 691b ldr r3, [r3, #16]
8000f38: 2b00 cmp r3, #0
8000f3a: d020 beq.n 8000f7e <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000f3c: 4b36 ldr r3, [pc, #216] ; (8001018 <HAL_RCC_OscConfig+0x270>)
8000f3e: 2201 movs r2, #1
8000f40: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f42: f7ff fc73 bl 800082c <HAL_GetTick>
8000f46: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000f48: e008 b.n 8000f5c <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000f4a: f7ff fc6f bl 800082c <HAL_GetTick>
8000f4e: 4602 mov r2, r0
8000f50: 693b ldr r3, [r7, #16]
8000f52: 1ad3 subs r3, r2, r3
8000f54: 2b02 cmp r3, #2
8000f56: d901 bls.n 8000f5c <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000f58: 2303 movs r3, #3
8000f5a: e19b b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000f5c: 4b2d ldr r3, [pc, #180] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000f5e: 681b ldr r3, [r3, #0]
8000f60: f003 0302 and.w r3, r3, #2
8000f64: 2b00 cmp r3, #0
8000f66: d0f0 beq.n 8000f4a <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000f68: 4b2a ldr r3, [pc, #168] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000f6a: 681b ldr r3, [r3, #0]
8000f6c: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000f70: 687b ldr r3, [r7, #4]
8000f72: 695b ldr r3, [r3, #20]
8000f74: 00db lsls r3, r3, #3
8000f76: 4927 ldr r1, [pc, #156] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000f78: 4313 orrs r3, r2
8000f7a: 600b str r3, [r1, #0]
8000f7c: e015 b.n 8000faa <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000f7e: 4b26 ldr r3, [pc, #152] ; (8001018 <HAL_RCC_OscConfig+0x270>)
8000f80: 2200 movs r2, #0
8000f82: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f84: f7ff fc52 bl 800082c <HAL_GetTick>
8000f88: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000f8a: e008 b.n 8000f9e <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000f8c: f7ff fc4e bl 800082c <HAL_GetTick>
8000f90: 4602 mov r2, r0
8000f92: 693b ldr r3, [r7, #16]
8000f94: 1ad3 subs r3, r2, r3
8000f96: 2b02 cmp r3, #2
8000f98: d901 bls.n 8000f9e <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000f9a: 2303 movs r3, #3
8000f9c: e17a b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000f9e: 4b1d ldr r3, [pc, #116] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000fa0: 681b ldr r3, [r3, #0]
8000fa2: f003 0302 and.w r3, r3, #2
8000fa6: 2b00 cmp r3, #0
8000fa8: d1f0 bne.n 8000f8c <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000faa: 687b ldr r3, [r7, #4]
8000fac: 681b ldr r3, [r3, #0]
8000fae: f003 0308 and.w r3, r3, #8
8000fb2: 2b00 cmp r3, #0
8000fb4: d03a beq.n 800102c <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000fb6: 687b ldr r3, [r7, #4]
8000fb8: 699b ldr r3, [r3, #24]
8000fba: 2b00 cmp r3, #0
8000fbc: d019 beq.n 8000ff2 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000fbe: 4b17 ldr r3, [pc, #92] ; (800101c <HAL_RCC_OscConfig+0x274>)
8000fc0: 2201 movs r2, #1
8000fc2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fc4: f7ff fc32 bl 800082c <HAL_GetTick>
8000fc8: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000fca: e008 b.n 8000fde <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000fcc: f7ff fc2e bl 800082c <HAL_GetTick>
8000fd0: 4602 mov r2, r0
8000fd2: 693b ldr r3, [r7, #16]
8000fd4: 1ad3 subs r3, r2, r3
8000fd6: 2b02 cmp r3, #2
8000fd8: d901 bls.n 8000fde <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8000fda: 2303 movs r3, #3
8000fdc: e15a b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000fde: 4b0d ldr r3, [pc, #52] ; (8001014 <HAL_RCC_OscConfig+0x26c>)
8000fe0: 6a5b ldr r3, [r3, #36] ; 0x24
8000fe2: f003 0302 and.w r3, r3, #2
8000fe6: 2b00 cmp r3, #0
8000fe8: d0f0 beq.n 8000fcc <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8000fea: 2001 movs r0, #1
8000fec: f000 faa6 bl 800153c <RCC_Delay>
8000ff0: e01c b.n 800102c <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000ff2: 4b0a ldr r3, [pc, #40] ; (800101c <HAL_RCC_OscConfig+0x274>)
8000ff4: 2200 movs r2, #0
8000ff6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ff8: f7ff fc18 bl 800082c <HAL_GetTick>
8000ffc: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000ffe: e00f b.n 8001020 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001000: f7ff fc14 bl 800082c <HAL_GetTick>
8001004: 4602 mov r2, r0
8001006: 693b ldr r3, [r7, #16]
8001008: 1ad3 subs r3, r2, r3
800100a: 2b02 cmp r3, #2
800100c: d908 bls.n 8001020 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
800100e: 2303 movs r3, #3
8001010: e140 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
8001012: bf00 nop
8001014: 40021000 .word 0x40021000
8001018: 42420000 .word 0x42420000
800101c: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001020: 4b9e ldr r3, [pc, #632] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001022: 6a5b ldr r3, [r3, #36] ; 0x24
8001024: f003 0302 and.w r3, r3, #2
8001028: 2b00 cmp r3, #0
800102a: d1e9 bne.n 8001000 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800102c: 687b ldr r3, [r7, #4]
800102e: 681b ldr r3, [r3, #0]
8001030: f003 0304 and.w r3, r3, #4
8001034: 2b00 cmp r3, #0
8001036: f000 80a6 beq.w 8001186 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
800103a: 2300 movs r3, #0
800103c: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800103e: 4b97 ldr r3, [pc, #604] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001040: 69db ldr r3, [r3, #28]
8001042: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001046: 2b00 cmp r3, #0
8001048: d10d bne.n 8001066 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
800104a: 4b94 ldr r3, [pc, #592] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
800104c: 69db ldr r3, [r3, #28]
800104e: 4a93 ldr r2, [pc, #588] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001050: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001054: 61d3 str r3, [r2, #28]
8001056: 4b91 ldr r3, [pc, #580] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001058: 69db ldr r3, [r3, #28]
800105a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800105e: 60bb str r3, [r7, #8]
8001060: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001062: 2301 movs r3, #1
8001064: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001066: 4b8e ldr r3, [pc, #568] ; (80012a0 <HAL_RCC_OscConfig+0x4f8>)
8001068: 681b ldr r3, [r3, #0]
800106a: f403 7380 and.w r3, r3, #256 ; 0x100
800106e: 2b00 cmp r3, #0
8001070: d118 bne.n 80010a4 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001072: 4b8b ldr r3, [pc, #556] ; (80012a0 <HAL_RCC_OscConfig+0x4f8>)
8001074: 681b ldr r3, [r3, #0]
8001076: 4a8a ldr r2, [pc, #552] ; (80012a0 <HAL_RCC_OscConfig+0x4f8>)
8001078: f443 7380 orr.w r3, r3, #256 ; 0x100
800107c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800107e: f7ff fbd5 bl 800082c <HAL_GetTick>
8001082: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001084: e008 b.n 8001098 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001086: f7ff fbd1 bl 800082c <HAL_GetTick>
800108a: 4602 mov r2, r0
800108c: 693b ldr r3, [r7, #16]
800108e: 1ad3 subs r3, r2, r3
8001090: 2b64 cmp r3, #100 ; 0x64
8001092: d901 bls.n 8001098 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8001094: 2303 movs r3, #3
8001096: e0fd b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001098: 4b81 ldr r3, [pc, #516] ; (80012a0 <HAL_RCC_OscConfig+0x4f8>)
800109a: 681b ldr r3, [r3, #0]
800109c: f403 7380 and.w r3, r3, #256 ; 0x100
80010a0: 2b00 cmp r3, #0
80010a2: d0f0 beq.n 8001086 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80010a4: 687b ldr r3, [r7, #4]
80010a6: 68db ldr r3, [r3, #12]
80010a8: 2b01 cmp r3, #1
80010aa: d106 bne.n 80010ba <HAL_RCC_OscConfig+0x312>
80010ac: 4b7b ldr r3, [pc, #492] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010ae: 6a1b ldr r3, [r3, #32]
80010b0: 4a7a ldr r2, [pc, #488] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010b2: f043 0301 orr.w r3, r3, #1
80010b6: 6213 str r3, [r2, #32]
80010b8: e02d b.n 8001116 <HAL_RCC_OscConfig+0x36e>
80010ba: 687b ldr r3, [r7, #4]
80010bc: 68db ldr r3, [r3, #12]
80010be: 2b00 cmp r3, #0
80010c0: d10c bne.n 80010dc <HAL_RCC_OscConfig+0x334>
80010c2: 4b76 ldr r3, [pc, #472] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010c4: 6a1b ldr r3, [r3, #32]
80010c6: 4a75 ldr r2, [pc, #468] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010c8: f023 0301 bic.w r3, r3, #1
80010cc: 6213 str r3, [r2, #32]
80010ce: 4b73 ldr r3, [pc, #460] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010d0: 6a1b ldr r3, [r3, #32]
80010d2: 4a72 ldr r2, [pc, #456] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010d4: f023 0304 bic.w r3, r3, #4
80010d8: 6213 str r3, [r2, #32]
80010da: e01c b.n 8001116 <HAL_RCC_OscConfig+0x36e>
80010dc: 687b ldr r3, [r7, #4]
80010de: 68db ldr r3, [r3, #12]
80010e0: 2b05 cmp r3, #5
80010e2: d10c bne.n 80010fe <HAL_RCC_OscConfig+0x356>
80010e4: 4b6d ldr r3, [pc, #436] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010e6: 6a1b ldr r3, [r3, #32]
80010e8: 4a6c ldr r2, [pc, #432] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010ea: f043 0304 orr.w r3, r3, #4
80010ee: 6213 str r3, [r2, #32]
80010f0: 4b6a ldr r3, [pc, #424] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010f2: 6a1b ldr r3, [r3, #32]
80010f4: 4a69 ldr r2, [pc, #420] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80010f6: f043 0301 orr.w r3, r3, #1
80010fa: 6213 str r3, [r2, #32]
80010fc: e00b b.n 8001116 <HAL_RCC_OscConfig+0x36e>
80010fe: 4b67 ldr r3, [pc, #412] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001100: 6a1b ldr r3, [r3, #32]
8001102: 4a66 ldr r2, [pc, #408] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001104: f023 0301 bic.w r3, r3, #1
8001108: 6213 str r3, [r2, #32]
800110a: 4b64 ldr r3, [pc, #400] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
800110c: 6a1b ldr r3, [r3, #32]
800110e: 4a63 ldr r2, [pc, #396] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001110: f023 0304 bic.w r3, r3, #4
8001114: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001116: 687b ldr r3, [r7, #4]
8001118: 68db ldr r3, [r3, #12]
800111a: 2b00 cmp r3, #0
800111c: d015 beq.n 800114a <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800111e: f7ff fb85 bl 800082c <HAL_GetTick>
8001122: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001124: e00a b.n 800113c <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001126: f7ff fb81 bl 800082c <HAL_GetTick>
800112a: 4602 mov r2, r0
800112c: 693b ldr r3, [r7, #16]
800112e: 1ad3 subs r3, r2, r3
8001130: f241 3288 movw r2, #5000 ; 0x1388
8001134: 4293 cmp r3, r2
8001136: d901 bls.n 800113c <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8001138: 2303 movs r3, #3
800113a: e0ab b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800113c: 4b57 ldr r3, [pc, #348] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
800113e: 6a1b ldr r3, [r3, #32]
8001140: f003 0302 and.w r3, r3, #2
8001144: 2b00 cmp r3, #0
8001146: d0ee beq.n 8001126 <HAL_RCC_OscConfig+0x37e>
8001148: e014 b.n 8001174 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800114a: f7ff fb6f bl 800082c <HAL_GetTick>
800114e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001150: e00a b.n 8001168 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001152: f7ff fb6b bl 800082c <HAL_GetTick>
8001156: 4602 mov r2, r0
8001158: 693b ldr r3, [r7, #16]
800115a: 1ad3 subs r3, r2, r3
800115c: f241 3288 movw r2, #5000 ; 0x1388
8001160: 4293 cmp r3, r2
8001162: d901 bls.n 8001168 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8001164: 2303 movs r3, #3
8001166: e095 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001168: 4b4c ldr r3, [pc, #304] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
800116a: 6a1b ldr r3, [r3, #32]
800116c: f003 0302 and.w r3, r3, #2
8001170: 2b00 cmp r3, #0
8001172: d1ee bne.n 8001152 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8001174: 7dfb ldrb r3, [r7, #23]
8001176: 2b01 cmp r3, #1
8001178: d105 bne.n 8001186 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
800117a: 4b48 ldr r3, [pc, #288] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
800117c: 69db ldr r3, [r3, #28]
800117e: 4a47 ldr r2, [pc, #284] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001180: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001184: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001186: 687b ldr r3, [r7, #4]
8001188: 69db ldr r3, [r3, #28]
800118a: 2b00 cmp r3, #0
800118c: f000 8081 beq.w 8001292 <HAL_RCC_OscConfig+0x4ea>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001190: 4b42 ldr r3, [pc, #264] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001192: 685b ldr r3, [r3, #4]
8001194: f003 030c and.w r3, r3, #12
8001198: 2b08 cmp r3, #8
800119a: d061 beq.n 8001260 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800119c: 687b ldr r3, [r7, #4]
800119e: 69db ldr r3, [r3, #28]
80011a0: 2b02 cmp r3, #2
80011a2: d146 bne.n 8001232 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80011a4: 4b3f ldr r3, [pc, #252] ; (80012a4 <HAL_RCC_OscConfig+0x4fc>)
80011a6: 2200 movs r2, #0
80011a8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011aa: f7ff fb3f bl 800082c <HAL_GetTick>
80011ae: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80011b0: e008 b.n 80011c4 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80011b2: f7ff fb3b bl 800082c <HAL_GetTick>
80011b6: 4602 mov r2, r0
80011b8: 693b ldr r3, [r7, #16]
80011ba: 1ad3 subs r3, r2, r3
80011bc: 2b02 cmp r3, #2
80011be: d901 bls.n 80011c4 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
80011c0: 2303 movs r3, #3
80011c2: e067 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80011c4: 4b35 ldr r3, [pc, #212] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80011c6: 681b ldr r3, [r3, #0]
80011c8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80011cc: 2b00 cmp r3, #0
80011ce: d1f0 bne.n 80011b2 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
80011d0: 687b ldr r3, [r7, #4]
80011d2: 6a1b ldr r3, [r3, #32]
80011d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80011d8: d108 bne.n 80011ec <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80011da: 4b30 ldr r3, [pc, #192] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80011dc: 685b ldr r3, [r3, #4]
80011de: f423 3200 bic.w r2, r3, #131072 ; 0x20000
80011e2: 687b ldr r3, [r7, #4]
80011e4: 689b ldr r3, [r3, #8]
80011e6: 492d ldr r1, [pc, #180] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80011e8: 4313 orrs r3, r2
80011ea: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80011ec: 4b2b ldr r3, [pc, #172] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
80011ee: 685b ldr r3, [r3, #4]
80011f0: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
80011f4: 687b ldr r3, [r7, #4]
80011f6: 6a19 ldr r1, [r3, #32]
80011f8: 687b ldr r3, [r7, #4]
80011fa: 6a5b ldr r3, [r3, #36] ; 0x24
80011fc: 430b orrs r3, r1
80011fe: 4927 ldr r1, [pc, #156] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001200: 4313 orrs r3, r2
8001202: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001204: 4b27 ldr r3, [pc, #156] ; (80012a4 <HAL_RCC_OscConfig+0x4fc>)
8001206: 2201 movs r2, #1
8001208: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800120a: f7ff fb0f bl 800082c <HAL_GetTick>
800120e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001210: e008 b.n 8001224 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001212: f7ff fb0b bl 800082c <HAL_GetTick>
8001216: 4602 mov r2, r0
8001218: 693b ldr r3, [r7, #16]
800121a: 1ad3 subs r3, r2, r3
800121c: 2b02 cmp r3, #2
800121e: d901 bls.n 8001224 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8001220: 2303 movs r3, #3
8001222: e037 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001224: 4b1d ldr r3, [pc, #116] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001226: 681b ldr r3, [r3, #0]
8001228: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800122c: 2b00 cmp r3, #0
800122e: d0f0 beq.n 8001212 <HAL_RCC_OscConfig+0x46a>
8001230: e02f b.n 8001292 <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001232: 4b1c ldr r3, [pc, #112] ; (80012a4 <HAL_RCC_OscConfig+0x4fc>)
8001234: 2200 movs r2, #0
8001236: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001238: f7ff faf8 bl 800082c <HAL_GetTick>
800123c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800123e: e008 b.n 8001252 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001240: f7ff faf4 bl 800082c <HAL_GetTick>
8001244: 4602 mov r2, r0
8001246: 693b ldr r3, [r7, #16]
8001248: 1ad3 subs r3, r2, r3
800124a: 2b02 cmp r3, #2
800124c: d901 bls.n 8001252 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
800124e: 2303 movs r3, #3
8001250: e020 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001252: 4b12 ldr r3, [pc, #72] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
8001254: 681b ldr r3, [r3, #0]
8001256: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800125a: 2b00 cmp r3, #0
800125c: d1f0 bne.n 8001240 <HAL_RCC_OscConfig+0x498>
800125e: e018 b.n 8001292 <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001260: 687b ldr r3, [r7, #4]
8001262: 69db ldr r3, [r3, #28]
8001264: 2b01 cmp r3, #1
8001266: d101 bne.n 800126c <HAL_RCC_OscConfig+0x4c4>
{
return HAL_ERROR;
8001268: 2301 movs r3, #1
800126a: e013 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800126c: 4b0b ldr r3, [pc, #44] ; (800129c <HAL_RCC_OscConfig+0x4f4>)
800126e: 685b ldr r3, [r3, #4]
8001270: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001272: 68fb ldr r3, [r7, #12]
8001274: f403 3280 and.w r2, r3, #65536 ; 0x10000
8001278: 687b ldr r3, [r7, #4]
800127a: 6a1b ldr r3, [r3, #32]
800127c: 429a cmp r2, r3
800127e: d106 bne.n 800128e <HAL_RCC_OscConfig+0x4e6>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8001280: 68fb ldr r3, [r7, #12]
8001282: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8001286: 687b ldr r3, [r7, #4]
8001288: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800128a: 429a cmp r2, r3
800128c: d001 beq.n 8001292 <HAL_RCC_OscConfig+0x4ea>
{
return HAL_ERROR;
800128e: 2301 movs r3, #1
8001290: e000 b.n 8001294 <HAL_RCC_OscConfig+0x4ec>
}
}
}
}
return HAL_OK;
8001292: 2300 movs r3, #0
}
8001294: 4618 mov r0, r3
8001296: 3718 adds r7, #24
8001298: 46bd mov sp, r7
800129a: bd80 pop {r7, pc}
800129c: 40021000 .word 0x40021000
80012a0: 40007000 .word 0x40007000
80012a4: 42420060 .word 0x42420060
080012a8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80012a8: b580 push {r7, lr}
80012aa: b084 sub sp, #16
80012ac: af00 add r7, sp, #0
80012ae: 6078 str r0, [r7, #4]
80012b0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80012b2: 687b ldr r3, [r7, #4]
80012b4: 2b00 cmp r3, #0
80012b6: d101 bne.n 80012bc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80012b8: 2301 movs r3, #1
80012ba: e0d0 b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80012bc: 4b6a ldr r3, [pc, #424] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80012be: 681b ldr r3, [r3, #0]
80012c0: f003 0307 and.w r3, r3, #7
80012c4: 683a ldr r2, [r7, #0]
80012c6: 429a cmp r2, r3
80012c8: d910 bls.n 80012ec <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80012ca: 4b67 ldr r3, [pc, #412] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80012cc: 681b ldr r3, [r3, #0]
80012ce: f023 0207 bic.w r2, r3, #7
80012d2: 4965 ldr r1, [pc, #404] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80012d4: 683b ldr r3, [r7, #0]
80012d6: 4313 orrs r3, r2
80012d8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80012da: 4b63 ldr r3, [pc, #396] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80012dc: 681b ldr r3, [r3, #0]
80012de: f003 0307 and.w r3, r3, #7
80012e2: 683a ldr r2, [r7, #0]
80012e4: 429a cmp r2, r3
80012e6: d001 beq.n 80012ec <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
80012e8: 2301 movs r3, #1
80012ea: e0b8 b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80012ec: 687b ldr r3, [r7, #4]
80012ee: 681b ldr r3, [r3, #0]
80012f0: f003 0302 and.w r3, r3, #2
80012f4: 2b00 cmp r3, #0
80012f6: d020 beq.n 800133a <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80012f8: 687b ldr r3, [r7, #4]
80012fa: 681b ldr r3, [r3, #0]
80012fc: f003 0304 and.w r3, r3, #4
8001300: 2b00 cmp r3, #0
8001302: d005 beq.n 8001310 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001304: 4b59 ldr r3, [pc, #356] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001306: 685b ldr r3, [r3, #4]
8001308: 4a58 ldr r2, [pc, #352] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
800130a: f443 63e0 orr.w r3, r3, #1792 ; 0x700
800130e: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001310: 687b ldr r3, [r7, #4]
8001312: 681b ldr r3, [r3, #0]
8001314: f003 0308 and.w r3, r3, #8
8001318: 2b00 cmp r3, #0
800131a: d005 beq.n 8001328 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800131c: 4b53 ldr r3, [pc, #332] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
800131e: 685b ldr r3, [r3, #4]
8001320: 4a52 ldr r2, [pc, #328] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001322: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8001326: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001328: 4b50 ldr r3, [pc, #320] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
800132a: 685b ldr r3, [r3, #4]
800132c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001330: 687b ldr r3, [r7, #4]
8001332: 689b ldr r3, [r3, #8]
8001334: 494d ldr r1, [pc, #308] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001336: 4313 orrs r3, r2
8001338: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800133a: 687b ldr r3, [r7, #4]
800133c: 681b ldr r3, [r3, #0]
800133e: f003 0301 and.w r3, r3, #1
8001342: 2b00 cmp r3, #0
8001344: d040 beq.n 80013c8 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001346: 687b ldr r3, [r7, #4]
8001348: 685b ldr r3, [r3, #4]
800134a: 2b01 cmp r3, #1
800134c: d107 bne.n 800135e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800134e: 4b47 ldr r3, [pc, #284] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001350: 681b ldr r3, [r3, #0]
8001352: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001356: 2b00 cmp r3, #0
8001358: d115 bne.n 8001386 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800135a: 2301 movs r3, #1
800135c: e07f b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800135e: 687b ldr r3, [r7, #4]
8001360: 685b ldr r3, [r3, #4]
8001362: 2b02 cmp r3, #2
8001364: d107 bne.n 8001376 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001366: 4b41 ldr r3, [pc, #260] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001368: 681b ldr r3, [r3, #0]
800136a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800136e: 2b00 cmp r3, #0
8001370: d109 bne.n 8001386 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001372: 2301 movs r3, #1
8001374: e073 b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001376: 4b3d ldr r3, [pc, #244] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001378: 681b ldr r3, [r3, #0]
800137a: f003 0302 and.w r3, r3, #2
800137e: 2b00 cmp r3, #0
8001380: d101 bne.n 8001386 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001382: 2301 movs r3, #1
8001384: e06b b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001386: 4b39 ldr r3, [pc, #228] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001388: 685b ldr r3, [r3, #4]
800138a: f023 0203 bic.w r2, r3, #3
800138e: 687b ldr r3, [r7, #4]
8001390: 685b ldr r3, [r3, #4]
8001392: 4936 ldr r1, [pc, #216] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001394: 4313 orrs r3, r2
8001396: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001398: f7ff fa48 bl 800082c <HAL_GetTick>
800139c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800139e: e00a b.n 80013b6 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80013a0: f7ff fa44 bl 800082c <HAL_GetTick>
80013a4: 4602 mov r2, r0
80013a6: 68fb ldr r3, [r7, #12]
80013a8: 1ad3 subs r3, r2, r3
80013aa: f241 3288 movw r2, #5000 ; 0x1388
80013ae: 4293 cmp r3, r2
80013b0: d901 bls.n 80013b6 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80013b2: 2303 movs r3, #3
80013b4: e053 b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80013b6: 4b2d ldr r3, [pc, #180] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
80013b8: 685b ldr r3, [r3, #4]
80013ba: f003 020c and.w r2, r3, #12
80013be: 687b ldr r3, [r7, #4]
80013c0: 685b ldr r3, [r3, #4]
80013c2: 009b lsls r3, r3, #2
80013c4: 429a cmp r2, r3
80013c6: d1eb bne.n 80013a0 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80013c8: 4b27 ldr r3, [pc, #156] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80013ca: 681b ldr r3, [r3, #0]
80013cc: f003 0307 and.w r3, r3, #7
80013d0: 683a ldr r2, [r7, #0]
80013d2: 429a cmp r2, r3
80013d4: d210 bcs.n 80013f8 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80013d6: 4b24 ldr r3, [pc, #144] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80013d8: 681b ldr r3, [r3, #0]
80013da: f023 0207 bic.w r2, r3, #7
80013de: 4922 ldr r1, [pc, #136] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80013e0: 683b ldr r3, [r7, #0]
80013e2: 4313 orrs r3, r2
80013e4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80013e6: 4b20 ldr r3, [pc, #128] ; (8001468 <HAL_RCC_ClockConfig+0x1c0>)
80013e8: 681b ldr r3, [r3, #0]
80013ea: f003 0307 and.w r3, r3, #7
80013ee: 683a ldr r2, [r7, #0]
80013f0: 429a cmp r2, r3
80013f2: d001 beq.n 80013f8 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
80013f4: 2301 movs r3, #1
80013f6: e032 b.n 800145e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80013f8: 687b ldr r3, [r7, #4]
80013fa: 681b ldr r3, [r3, #0]
80013fc: f003 0304 and.w r3, r3, #4
8001400: 2b00 cmp r3, #0
8001402: d008 beq.n 8001416 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001404: 4b19 ldr r3, [pc, #100] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001406: 685b ldr r3, [r3, #4]
8001408: f423 62e0 bic.w r2, r3, #1792 ; 0x700
800140c: 687b ldr r3, [r7, #4]
800140e: 68db ldr r3, [r3, #12]
8001410: 4916 ldr r1, [pc, #88] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001412: 4313 orrs r3, r2
8001414: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001416: 687b ldr r3, [r7, #4]
8001418: 681b ldr r3, [r3, #0]
800141a: f003 0308 and.w r3, r3, #8
800141e: 2b00 cmp r3, #0
8001420: d009 beq.n 8001436 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8001422: 4b12 ldr r3, [pc, #72] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001424: 685b ldr r3, [r3, #4]
8001426: f423 5260 bic.w r2, r3, #14336 ; 0x3800
800142a: 687b ldr r3, [r7, #4]
800142c: 691b ldr r3, [r3, #16]
800142e: 00db lsls r3, r3, #3
8001430: 490e ldr r1, [pc, #56] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
8001432: 4313 orrs r3, r2
8001434: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8001436: f000 f821 bl 800147c <HAL_RCC_GetSysClockFreq>
800143a: 4602 mov r2, r0
800143c: 4b0b ldr r3, [pc, #44] ; (800146c <HAL_RCC_ClockConfig+0x1c4>)
800143e: 685b ldr r3, [r3, #4]
8001440: 091b lsrs r3, r3, #4
8001442: f003 030f and.w r3, r3, #15
8001446: 490a ldr r1, [pc, #40] ; (8001470 <HAL_RCC_ClockConfig+0x1c8>)
8001448: 5ccb ldrb r3, [r1, r3]
800144a: fa22 f303 lsr.w r3, r2, r3
800144e: 4a09 ldr r2, [pc, #36] ; (8001474 <HAL_RCC_ClockConfig+0x1cc>)
8001450: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8001452: 4b09 ldr r3, [pc, #36] ; (8001478 <HAL_RCC_ClockConfig+0x1d0>)
8001454: 681b ldr r3, [r3, #0]
8001456: 4618 mov r0, r3
8001458: f7ff f9a6 bl 80007a8 <HAL_InitTick>
return HAL_OK;
800145c: 2300 movs r3, #0
}
800145e: 4618 mov r0, r3
8001460: 3710 adds r7, #16
8001462: 46bd mov sp, r7
8001464: bd80 pop {r7, pc}
8001466: bf00 nop
8001468: 40022000 .word 0x40022000
800146c: 40021000 .word 0x40021000
8001470: 08003c88 .word 0x08003c88
8001474: 20000000 .word 0x20000000
8001478: 20000004 .word 0x20000004
0800147c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800147c: b490 push {r4, r7}
800147e: b08a sub sp, #40 ; 0x28
8001480: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
8001482: 4b2a ldr r3, [pc, #168] ; (800152c <HAL_RCC_GetSysClockFreq+0xb0>)
8001484: 1d3c adds r4, r7, #4
8001486: cb0f ldmia r3, {r0, r1, r2, r3}
8001488: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
800148c: f240 2301 movw r3, #513 ; 0x201
8001490: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8001492: 2300 movs r3, #0
8001494: 61fb str r3, [r7, #28]
8001496: 2300 movs r3, #0
8001498: 61bb str r3, [r7, #24]
800149a: 2300 movs r3, #0
800149c: 627b str r3, [r7, #36] ; 0x24
800149e: 2300 movs r3, #0
80014a0: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
80014a2: 2300 movs r3, #0
80014a4: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80014a6: 4b22 ldr r3, [pc, #136] ; (8001530 <HAL_RCC_GetSysClockFreq+0xb4>)
80014a8: 685b ldr r3, [r3, #4]
80014aa: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80014ac: 69fb ldr r3, [r7, #28]
80014ae: f003 030c and.w r3, r3, #12
80014b2: 2b04 cmp r3, #4
80014b4: d002 beq.n 80014bc <HAL_RCC_GetSysClockFreq+0x40>
80014b6: 2b08 cmp r3, #8
80014b8: d003 beq.n 80014c2 <HAL_RCC_GetSysClockFreq+0x46>
80014ba: e02d b.n 8001518 <HAL_RCC_GetSysClockFreq+0x9c>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80014bc: 4b1d ldr r3, [pc, #116] ; (8001534 <HAL_RCC_GetSysClockFreq+0xb8>)
80014be: 623b str r3, [r7, #32]
break;
80014c0: e02d b.n 800151e <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80014c2: 69fb ldr r3, [r7, #28]
80014c4: 0c9b lsrs r3, r3, #18
80014c6: f003 030f and.w r3, r3, #15
80014ca: f107 0228 add.w r2, r7, #40 ; 0x28
80014ce: 4413 add r3, r2
80014d0: f813 3c24 ldrb.w r3, [r3, #-36]
80014d4: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80014d6: 69fb ldr r3, [r7, #28]
80014d8: f403 3380 and.w r3, r3, #65536 ; 0x10000
80014dc: 2b00 cmp r3, #0
80014de: d013 beq.n 8001508 <HAL_RCC_GetSysClockFreq+0x8c>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80014e0: 4b13 ldr r3, [pc, #76] ; (8001530 <HAL_RCC_GetSysClockFreq+0xb4>)
80014e2: 685b ldr r3, [r3, #4]
80014e4: 0c5b lsrs r3, r3, #17
80014e6: f003 0301 and.w r3, r3, #1
80014ea: f107 0228 add.w r2, r7, #40 ; 0x28
80014ee: 4413 add r3, r2
80014f0: f813 3c28 ldrb.w r3, [r3, #-40]
80014f4: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
80014f6: 697b ldr r3, [r7, #20]
80014f8: 4a0e ldr r2, [pc, #56] ; (8001534 <HAL_RCC_GetSysClockFreq+0xb8>)
80014fa: fb02 f203 mul.w r2, r2, r3
80014fe: 69bb ldr r3, [r7, #24]
8001500: fbb2 f3f3 udiv r3, r2, r3
8001504: 627b str r3, [r7, #36] ; 0x24
8001506: e004 b.n 8001512 <HAL_RCC_GetSysClockFreq+0x96>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8001508: 697b ldr r3, [r7, #20]
800150a: 4a0b ldr r2, [pc, #44] ; (8001538 <HAL_RCC_GetSysClockFreq+0xbc>)
800150c: fb02 f303 mul.w r3, r2, r3
8001510: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
8001512: 6a7b ldr r3, [r7, #36] ; 0x24
8001514: 623b str r3, [r7, #32]
break;
8001516: e002 b.n 800151e <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8001518: 4b06 ldr r3, [pc, #24] ; (8001534 <HAL_RCC_GetSysClockFreq+0xb8>)
800151a: 623b str r3, [r7, #32]
break;
800151c: bf00 nop
}
}
return sysclockfreq;
800151e: 6a3b ldr r3, [r7, #32]
}
8001520: 4618 mov r0, r3
8001522: 3728 adds r7, #40 ; 0x28
8001524: 46bd mov sp, r7
8001526: bc90 pop {r4, r7}
8001528: 4770 bx lr
800152a: bf00 nop
800152c: 08003c64 .word 0x08003c64
8001530: 40021000 .word 0x40021000
8001534: 007a1200 .word 0x007a1200
8001538: 003d0900 .word 0x003d0900
0800153c <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
800153c: b480 push {r7}
800153e: b085 sub sp, #20
8001540: af00 add r7, sp, #0
8001542: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8001544: 4b0a ldr r3, [pc, #40] ; (8001570 <RCC_Delay+0x34>)
8001546: 681b ldr r3, [r3, #0]
8001548: 4a0a ldr r2, [pc, #40] ; (8001574 <RCC_Delay+0x38>)
800154a: fba2 2303 umull r2, r3, r2, r3
800154e: 0a5b lsrs r3, r3, #9
8001550: 687a ldr r2, [r7, #4]
8001552: fb02 f303 mul.w r3, r2, r3
8001556: 60fb str r3, [r7, #12]
do
{
__NOP();
8001558: bf00 nop
}
while (Delay --);
800155a: 68fb ldr r3, [r7, #12]
800155c: 1e5a subs r2, r3, #1
800155e: 60fa str r2, [r7, #12]
8001560: 2b00 cmp r3, #0
8001562: d1f9 bne.n 8001558 <RCC_Delay+0x1c>
}
8001564: bf00 nop
8001566: bf00 nop
8001568: 3714 adds r7, #20
800156a: 46bd mov sp, r7
800156c: bc80 pop {r7}
800156e: 4770 bx lr
8001570: 20000000 .word 0x20000000
8001574: 10624dd3 .word 0x10624dd3
08001578 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8001578: b580 push {r7, lr}
800157a: b082 sub sp, #8
800157c: af00 add r7, sp, #0
800157e: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
8001580: 687b ldr r3, [r7, #4]
8001582: 2b00 cmp r3, #0
8001584: d101 bne.n 800158a <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8001586: 2301 movs r3, #1
8001588: e076 b.n 8001678 <HAL_SPI_Init+0x100>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
/* TI mode is not supported on this device.
TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
800158a: 687b ldr r3, [r7, #4]
800158c: 6a5b ldr r3, [r3, #36] ; 0x24
800158e: 2b00 cmp r3, #0
8001590: d108 bne.n 80015a4 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8001592: 687b ldr r3, [r7, #4]
8001594: 685b ldr r3, [r3, #4]
8001596: f5b3 7f82 cmp.w r3, #260 ; 0x104
800159a: d009 beq.n 80015b0 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
800159c: 687b ldr r3, [r7, #4]
800159e: 2200 movs r2, #0
80015a0: 61da str r2, [r3, #28]
80015a2: e005 b.n 80015b0 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
80015a4: 687b ldr r3, [r7, #4]
80015a6: 2200 movs r2, #0
80015a8: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
80015aa: 687b ldr r3, [r7, #4]
80015ac: 2200 movs r2, #0
80015ae: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80015b0: 687b ldr r3, [r7, #4]
80015b2: 2200 movs r2, #0
80015b4: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
80015b6: 687b ldr r3, [r7, #4]
80015b8: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80015bc: b2db uxtb r3, r3
80015be: 2b00 cmp r3, #0
80015c0: d106 bne.n 80015d0 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
80015c2: 687b ldr r3, [r7, #4]
80015c4: 2200 movs r2, #0
80015c6: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
80015ca: 6878 ldr r0, [r7, #4]
80015cc: f7fe ffd8 bl 8000580 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
80015d0: 687b ldr r3, [r7, #4]
80015d2: 2202 movs r2, #2
80015d4: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80015d8: 687b ldr r3, [r7, #4]
80015da: 681b ldr r3, [r3, #0]
80015dc: 681a ldr r2, [r3, #0]
80015de: 687b ldr r3, [r7, #4]
80015e0: 681b ldr r3, [r3, #0]
80015e2: f022 0240 bic.w r2, r2, #64 ; 0x40
80015e6: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80015e8: 687b ldr r3, [r7, #4]
80015ea: 685b ldr r3, [r3, #4]
80015ec: f403 7282 and.w r2, r3, #260 ; 0x104
80015f0: 687b ldr r3, [r7, #4]
80015f2: 689b ldr r3, [r3, #8]
80015f4: f403 4304 and.w r3, r3, #33792 ; 0x8400
80015f8: 431a orrs r2, r3
80015fa: 687b ldr r3, [r7, #4]
80015fc: 68db ldr r3, [r3, #12]
80015fe: f403 6300 and.w r3, r3, #2048 ; 0x800
8001602: 431a orrs r2, r3
8001604: 687b ldr r3, [r7, #4]
8001606: 691b ldr r3, [r3, #16]
8001608: f003 0302 and.w r3, r3, #2
800160c: 431a orrs r2, r3
800160e: 687b ldr r3, [r7, #4]
8001610: 695b ldr r3, [r3, #20]
8001612: f003 0301 and.w r3, r3, #1
8001616: 431a orrs r2, r3
8001618: 687b ldr r3, [r7, #4]
800161a: 699b ldr r3, [r3, #24]
800161c: f403 7300 and.w r3, r3, #512 ; 0x200
8001620: 431a orrs r2, r3
8001622: 687b ldr r3, [r7, #4]
8001624: 69db ldr r3, [r3, #28]
8001626: f003 0338 and.w r3, r3, #56 ; 0x38
800162a: 431a orrs r2, r3
800162c: 687b ldr r3, [r7, #4]
800162e: 6a1b ldr r3, [r3, #32]
8001630: f003 0380 and.w r3, r3, #128 ; 0x80
8001634: ea42 0103 orr.w r1, r2, r3
8001638: 687b ldr r3, [r7, #4]
800163a: 6a9b ldr r3, [r3, #40] ; 0x28
800163c: f403 5200 and.w r2, r3, #8192 ; 0x2000
8001640: 687b ldr r3, [r7, #4]
8001642: 681b ldr r3, [r3, #0]
8001644: 430a orrs r2, r1
8001646: 601a str r2, [r3, #0]
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management */
WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
8001648: 687b ldr r3, [r7, #4]
800164a: 699b ldr r3, [r3, #24]
800164c: 0c1a lsrs r2, r3, #16
800164e: 687b ldr r3, [r7, #4]
8001650: 681b ldr r3, [r3, #0]
8001652: f002 0204 and.w r2, r2, #4
8001656: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8001658: 687b ldr r3, [r7, #4]
800165a: 681b ldr r3, [r3, #0]
800165c: 69da ldr r2, [r3, #28]
800165e: 687b ldr r3, [r7, #4]
8001660: 681b ldr r3, [r3, #0]
8001662: f422 6200 bic.w r2, r2, #2048 ; 0x800
8001666: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001668: 687b ldr r3, [r7, #4]
800166a: 2200 movs r2, #0
800166c: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
800166e: 687b ldr r3, [r7, #4]
8001670: 2201 movs r2, #1
8001672: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
8001676: 2300 movs r3, #0
}
8001678: 4618 mov r0, r3
800167a: 3708 adds r7, #8
800167c: 46bd mov sp, r7
800167e: bd80 pop {r7, pc}
08001680 <HAL_SPI_Transmit>:
* @param Size amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8001680: b580 push {r7, lr}
8001682: b088 sub sp, #32
8001684: af00 add r7, sp, #0
8001686: 60f8 str r0, [r7, #12]
8001688: 60b9 str r1, [r7, #8]
800168a: 603b str r3, [r7, #0]
800168c: 4613 mov r3, r2
800168e: 80fb strh r3, [r7, #6]
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
8001690: 2300 movs r3, #0
8001692: 77fb strb r3, [r7, #31]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
8001694: 68fb ldr r3, [r7, #12]
8001696: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
800169a: 2b01 cmp r3, #1
800169c: d101 bne.n 80016a2 <HAL_SPI_Transmit+0x22>
800169e: 2302 movs r3, #2
80016a0: e126 b.n 80018f0 <HAL_SPI_Transmit+0x270>
80016a2: 68fb ldr r3, [r7, #12]
80016a4: 2201 movs r2, #1
80016a6: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80016aa: f7ff f8bf bl 800082c <HAL_GetTick>
80016ae: 61b8 str r0, [r7, #24]
initial_TxXferCount = Size;
80016b0: 88fb ldrh r3, [r7, #6]
80016b2: 82fb strh r3, [r7, #22]
if (hspi->State != HAL_SPI_STATE_READY)
80016b4: 68fb ldr r3, [r7, #12]
80016b6: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80016ba: b2db uxtb r3, r3
80016bc: 2b01 cmp r3, #1
80016be: d002 beq.n 80016c6 <HAL_SPI_Transmit+0x46>
{
errorcode = HAL_BUSY;
80016c0: 2302 movs r3, #2
80016c2: 77fb strb r3, [r7, #31]
goto error;
80016c4: e10b b.n 80018de <HAL_SPI_Transmit+0x25e>
}
if ((pData == NULL) || (Size == 0U))
80016c6: 68bb ldr r3, [r7, #8]
80016c8: 2b00 cmp r3, #0
80016ca: d002 beq.n 80016d2 <HAL_SPI_Transmit+0x52>
80016cc: 88fb ldrh r3, [r7, #6]
80016ce: 2b00 cmp r3, #0
80016d0: d102 bne.n 80016d8 <HAL_SPI_Transmit+0x58>
{
errorcode = HAL_ERROR;
80016d2: 2301 movs r3, #1
80016d4: 77fb strb r3, [r7, #31]
goto error;
80016d6: e102 b.n 80018de <HAL_SPI_Transmit+0x25e>
}
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
80016d8: 68fb ldr r3, [r7, #12]
80016da: 2203 movs r2, #3
80016dc: f883 2051 strb.w r2, [r3, #81] ; 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80016e0: 68fb ldr r3, [r7, #12]
80016e2: 2200 movs r2, #0
80016e4: 655a str r2, [r3, #84] ; 0x54
hspi->pTxBuffPtr = (uint8_t *)pData;
80016e6: 68fb ldr r3, [r7, #12]
80016e8: 68ba ldr r2, [r7, #8]
80016ea: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferSize = Size;
80016ec: 68fb ldr r3, [r7, #12]
80016ee: 88fa ldrh r2, [r7, #6]
80016f0: 869a strh r2, [r3, #52] ; 0x34
hspi->TxXferCount = Size;
80016f2: 68fb ldr r3, [r7, #12]
80016f4: 88fa ldrh r2, [r7, #6]
80016f6: 86da strh r2, [r3, #54] ; 0x36
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
80016f8: 68fb ldr r3, [r7, #12]
80016fa: 2200 movs r2, #0
80016fc: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferSize = 0U;
80016fe: 68fb ldr r3, [r7, #12]
8001700: 2200 movs r2, #0
8001702: 879a strh r2, [r3, #60] ; 0x3c
hspi->RxXferCount = 0U;
8001704: 68fb ldr r3, [r7, #12]
8001706: 2200 movs r2, #0
8001708: 87da strh r2, [r3, #62] ; 0x3e
hspi->TxISR = NULL;
800170a: 68fb ldr r3, [r7, #12]
800170c: 2200 movs r2, #0
800170e: 645a str r2, [r3, #68] ; 0x44
hspi->RxISR = NULL;
8001710: 68fb ldr r3, [r7, #12]
8001712: 2200 movs r2, #0
8001714: 641a str r2, [r3, #64] ; 0x40
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
8001716: 68fb ldr r3, [r7, #12]
8001718: 689b ldr r3, [r3, #8]
800171a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800171e: d10f bne.n 8001740 <HAL_SPI_Transmit+0xc0>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
8001720: 68fb ldr r3, [r7, #12]
8001722: 681b ldr r3, [r3, #0]
8001724: 681a ldr r2, [r3, #0]
8001726: 68fb ldr r3, [r7, #12]
8001728: 681b ldr r3, [r3, #0]
800172a: f022 0240 bic.w r2, r2, #64 ; 0x40
800172e: 601a str r2, [r3, #0]
SPI_1LINE_TX(hspi);
8001730: 68fb ldr r3, [r7, #12]
8001732: 681b ldr r3, [r3, #0]
8001734: 681a ldr r2, [r3, #0]
8001736: 68fb ldr r3, [r7, #12]
8001738: 681b ldr r3, [r3, #0]
800173a: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800173e: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8001740: 68fb ldr r3, [r7, #12]
8001742: 681b ldr r3, [r3, #0]
8001744: 681b ldr r3, [r3, #0]
8001746: f003 0340 and.w r3, r3, #64 ; 0x40
800174a: 2b40 cmp r3, #64 ; 0x40
800174c: d007 beq.n 800175e <HAL_SPI_Transmit+0xde>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
800174e: 68fb ldr r3, [r7, #12]
8001750: 681b ldr r3, [r3, #0]
8001752: 681a ldr r2, [r3, #0]
8001754: 68fb ldr r3, [r7, #12]
8001756: 681b ldr r3, [r3, #0]
8001758: f042 0240 orr.w r2, r2, #64 ; 0x40
800175c: 601a str r2, [r3, #0]
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
800175e: 68fb ldr r3, [r7, #12]
8001760: 68db ldr r3, [r3, #12]
8001762: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8001766: d14b bne.n 8001800 <HAL_SPI_Transmit+0x180>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8001768: 68fb ldr r3, [r7, #12]
800176a: 685b ldr r3, [r3, #4]
800176c: 2b00 cmp r3, #0
800176e: d002 beq.n 8001776 <HAL_SPI_Transmit+0xf6>
8001770: 8afb ldrh r3, [r7, #22]
8001772: 2b01 cmp r3, #1
8001774: d13e bne.n 80017f4 <HAL_SPI_Transmit+0x174>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8001776: 68fb ldr r3, [r7, #12]
8001778: 6b1b ldr r3, [r3, #48] ; 0x30
800177a: 881a ldrh r2, [r3, #0]
800177c: 68fb ldr r3, [r7, #12]
800177e: 681b ldr r3, [r3, #0]
8001780: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8001782: 68fb ldr r3, [r7, #12]
8001784: 6b1b ldr r3, [r3, #48] ; 0x30
8001786: 1c9a adds r2, r3, #2
8001788: 68fb ldr r3, [r7, #12]
800178a: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
800178c: 68fb ldr r3, [r7, #12]
800178e: 8edb ldrh r3, [r3, #54] ; 0x36
8001790: b29b uxth r3, r3
8001792: 3b01 subs r3, #1
8001794: b29a uxth r2, r3
8001796: 68fb ldr r3, [r7, #12]
8001798: 86da strh r2, [r3, #54] ; 0x36
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
800179a: e02b b.n 80017f4 <HAL_SPI_Transmit+0x174>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
800179c: 68fb ldr r3, [r7, #12]
800179e: 681b ldr r3, [r3, #0]
80017a0: 689b ldr r3, [r3, #8]
80017a2: f003 0302 and.w r3, r3, #2
80017a6: 2b02 cmp r3, #2
80017a8: d112 bne.n 80017d0 <HAL_SPI_Transmit+0x150>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
80017aa: 68fb ldr r3, [r7, #12]
80017ac: 6b1b ldr r3, [r3, #48] ; 0x30
80017ae: 881a ldrh r2, [r3, #0]
80017b0: 68fb ldr r3, [r7, #12]
80017b2: 681b ldr r3, [r3, #0]
80017b4: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
80017b6: 68fb ldr r3, [r7, #12]
80017b8: 6b1b ldr r3, [r3, #48] ; 0x30
80017ba: 1c9a adds r2, r3, #2
80017bc: 68fb ldr r3, [r7, #12]
80017be: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
80017c0: 68fb ldr r3, [r7, #12]
80017c2: 8edb ldrh r3, [r3, #54] ; 0x36
80017c4: b29b uxth r3, r3
80017c6: 3b01 subs r3, #1
80017c8: b29a uxth r2, r3
80017ca: 68fb ldr r3, [r7, #12]
80017cc: 86da strh r2, [r3, #54] ; 0x36
80017ce: e011 b.n 80017f4 <HAL_SPI_Transmit+0x174>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
80017d0: f7ff f82c bl 800082c <HAL_GetTick>
80017d4: 4602 mov r2, r0
80017d6: 69bb ldr r3, [r7, #24]
80017d8: 1ad3 subs r3, r2, r3
80017da: 683a ldr r2, [r7, #0]
80017dc: 429a cmp r2, r3
80017de: d803 bhi.n 80017e8 <HAL_SPI_Transmit+0x168>
80017e0: 683b ldr r3, [r7, #0]
80017e2: f1b3 3fff cmp.w r3, #4294967295
80017e6: d102 bne.n 80017ee <HAL_SPI_Transmit+0x16e>
80017e8: 683b ldr r3, [r7, #0]
80017ea: 2b00 cmp r3, #0
80017ec: d102 bne.n 80017f4 <HAL_SPI_Transmit+0x174>
{
errorcode = HAL_TIMEOUT;
80017ee: 2303 movs r3, #3
80017f0: 77fb strb r3, [r7, #31]
goto error;
80017f2: e074 b.n 80018de <HAL_SPI_Transmit+0x25e>
while (hspi->TxXferCount > 0U)
80017f4: 68fb ldr r3, [r7, #12]
80017f6: 8edb ldrh r3, [r3, #54] ; 0x36
80017f8: b29b uxth r3, r3
80017fa: 2b00 cmp r3, #0
80017fc: d1ce bne.n 800179c <HAL_SPI_Transmit+0x11c>
80017fe: e04c b.n 800189a <HAL_SPI_Transmit+0x21a>
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8001800: 68fb ldr r3, [r7, #12]
8001802: 685b ldr r3, [r3, #4]
8001804: 2b00 cmp r3, #0
8001806: d002 beq.n 800180e <HAL_SPI_Transmit+0x18e>
8001808: 8afb ldrh r3, [r7, #22]
800180a: 2b01 cmp r3, #1
800180c: d140 bne.n 8001890 <HAL_SPI_Transmit+0x210>
{
*((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
800180e: 68fb ldr r3, [r7, #12]
8001810: 6b1a ldr r2, [r3, #48] ; 0x30
8001812: 68fb ldr r3, [r7, #12]
8001814: 681b ldr r3, [r3, #0]
8001816: 330c adds r3, #12
8001818: 7812 ldrb r2, [r2, #0]
800181a: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
800181c: 68fb ldr r3, [r7, #12]
800181e: 6b1b ldr r3, [r3, #48] ; 0x30
8001820: 1c5a adds r2, r3, #1
8001822: 68fb ldr r3, [r7, #12]
8001824: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8001826: 68fb ldr r3, [r7, #12]
8001828: 8edb ldrh r3, [r3, #54] ; 0x36
800182a: b29b uxth r3, r3
800182c: 3b01 subs r3, #1
800182e: b29a uxth r2, r3
8001830: 68fb ldr r3, [r7, #12]
8001832: 86da strh r2, [r3, #54] ; 0x36
}
while (hspi->TxXferCount > 0U)
8001834: e02c b.n 8001890 <HAL_SPI_Transmit+0x210>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
8001836: 68fb ldr r3, [r7, #12]
8001838: 681b ldr r3, [r3, #0]
800183a: 689b ldr r3, [r3, #8]
800183c: f003 0302 and.w r3, r3, #2
8001840: 2b02 cmp r3, #2
8001842: d113 bne.n 800186c <HAL_SPI_Transmit+0x1ec>
{
*((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
8001844: 68fb ldr r3, [r7, #12]
8001846: 6b1a ldr r2, [r3, #48] ; 0x30
8001848: 68fb ldr r3, [r7, #12]
800184a: 681b ldr r3, [r3, #0]
800184c: 330c adds r3, #12
800184e: 7812 ldrb r2, [r2, #0]
8001850: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
8001852: 68fb ldr r3, [r7, #12]
8001854: 6b1b ldr r3, [r3, #48] ; 0x30
8001856: 1c5a adds r2, r3, #1
8001858: 68fb ldr r3, [r7, #12]
800185a: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
800185c: 68fb ldr r3, [r7, #12]
800185e: 8edb ldrh r3, [r3, #54] ; 0x36
8001860: b29b uxth r3, r3
8001862: 3b01 subs r3, #1
8001864: b29a uxth r2, r3
8001866: 68fb ldr r3, [r7, #12]
8001868: 86da strh r2, [r3, #54] ; 0x36
800186a: e011 b.n 8001890 <HAL_SPI_Transmit+0x210>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
800186c: f7fe ffde bl 800082c <HAL_GetTick>
8001870: 4602 mov r2, r0
8001872: 69bb ldr r3, [r7, #24]
8001874: 1ad3 subs r3, r2, r3
8001876: 683a ldr r2, [r7, #0]
8001878: 429a cmp r2, r3
800187a: d803 bhi.n 8001884 <HAL_SPI_Transmit+0x204>
800187c: 683b ldr r3, [r7, #0]
800187e: f1b3 3fff cmp.w r3, #4294967295
8001882: d102 bne.n 800188a <HAL_SPI_Transmit+0x20a>
8001884: 683b ldr r3, [r7, #0]
8001886: 2b00 cmp r3, #0
8001888: d102 bne.n 8001890 <HAL_SPI_Transmit+0x210>
{
errorcode = HAL_TIMEOUT;
800188a: 2303 movs r3, #3
800188c: 77fb strb r3, [r7, #31]
goto error;
800188e: e026 b.n 80018de <HAL_SPI_Transmit+0x25e>
while (hspi->TxXferCount > 0U)
8001890: 68fb ldr r3, [r7, #12]
8001892: 8edb ldrh r3, [r3, #54] ; 0x36
8001894: b29b uxth r3, r3
8001896: 2b00 cmp r3, #0
8001898: d1cd bne.n 8001836 <HAL_SPI_Transmit+0x1b6>
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
800189a: 69ba ldr r2, [r7, #24]
800189c: 6839 ldr r1, [r7, #0]
800189e: 68f8 ldr r0, [r7, #12]
80018a0: f000 fbc4 bl 800202c <SPI_EndRxTxTransaction>
80018a4: 4603 mov r3, r0
80018a6: 2b00 cmp r3, #0
80018a8: d002 beq.n 80018b0 <HAL_SPI_Transmit+0x230>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
80018aa: 68fb ldr r3, [r7, #12]
80018ac: 2220 movs r2, #32
80018ae: 655a str r2, [r3, #84] ; 0x54
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
80018b0: 68fb ldr r3, [r7, #12]
80018b2: 689b ldr r3, [r3, #8]
80018b4: 2b00 cmp r3, #0
80018b6: d10a bne.n 80018ce <HAL_SPI_Transmit+0x24e>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
80018b8: 2300 movs r3, #0
80018ba: 613b str r3, [r7, #16]
80018bc: 68fb ldr r3, [r7, #12]
80018be: 681b ldr r3, [r3, #0]
80018c0: 68db ldr r3, [r3, #12]
80018c2: 613b str r3, [r7, #16]
80018c4: 68fb ldr r3, [r7, #12]
80018c6: 681b ldr r3, [r3, #0]
80018c8: 689b ldr r3, [r3, #8]
80018ca: 613b str r3, [r7, #16]
80018cc: 693b ldr r3, [r7, #16]
}
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
80018ce: 68fb ldr r3, [r7, #12]
80018d0: 6d5b ldr r3, [r3, #84] ; 0x54
80018d2: 2b00 cmp r3, #0
80018d4: d002 beq.n 80018dc <HAL_SPI_Transmit+0x25c>
{
errorcode = HAL_ERROR;
80018d6: 2301 movs r3, #1
80018d8: 77fb strb r3, [r7, #31]
80018da: e000 b.n 80018de <HAL_SPI_Transmit+0x25e>
}
error:
80018dc: bf00 nop
hspi->State = HAL_SPI_STATE_READY;
80018de: 68fb ldr r3, [r7, #12]
80018e0: 2201 movs r2, #1
80018e2: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80018e6: 68fb ldr r3, [r7, #12]
80018e8: 2200 movs r2, #0
80018ea: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
80018ee: 7ffb ldrb r3, [r7, #31]
}
80018f0: 4618 mov r0, r3
80018f2: 3720 adds r7, #32
80018f4: 46bd mov sp, r7
80018f6: bd80 pop {r7, pc}
080018f8 <HAL_SPI_Receive>:
* @param Size amount of data to be received
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80018f8: b580 push {r7, lr}
80018fa: b088 sub sp, #32
80018fc: af02 add r7, sp, #8
80018fe: 60f8 str r0, [r7, #12]
8001900: 60b9 str r1, [r7, #8]
8001902: 603b str r3, [r7, #0]
8001904: 4613 mov r3, r2
8001906: 80fb strh r3, [r7, #6]
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
8001908: 2300 movs r3, #0
800190a: 75fb strb r3, [r7, #23]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
800190c: 68fb ldr r3, [r7, #12]
800190e: 685b ldr r3, [r3, #4]
8001910: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001914: d112 bne.n 800193c <HAL_SPI_Receive+0x44>
8001916: 68fb ldr r3, [r7, #12]
8001918: 689b ldr r3, [r3, #8]
800191a: 2b00 cmp r3, #0
800191c: d10e bne.n 800193c <HAL_SPI_Receive+0x44>
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
800191e: 68fb ldr r3, [r7, #12]
8001920: 2204 movs r2, #4
8001922: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
8001926: 88fa ldrh r2, [r7, #6]
8001928: 683b ldr r3, [r7, #0]
800192a: 9300 str r3, [sp, #0]
800192c: 4613 mov r3, r2
800192e: 68ba ldr r2, [r7, #8]
8001930: 68b9 ldr r1, [r7, #8]
8001932: 68f8 ldr r0, [r7, #12]
8001934: f000 f8f1 bl 8001b1a <HAL_SPI_TransmitReceive>
8001938: 4603 mov r3, r0
800193a: e0ea b.n 8001b12 <HAL_SPI_Receive+0x21a>
}
/* Process Locked */
__HAL_LOCK(hspi);
800193c: 68fb ldr r3, [r7, #12]
800193e: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
8001942: 2b01 cmp r3, #1
8001944: d101 bne.n 800194a <HAL_SPI_Receive+0x52>
8001946: 2302 movs r3, #2
8001948: e0e3 b.n 8001b12 <HAL_SPI_Receive+0x21a>
800194a: 68fb ldr r3, [r7, #12]
800194c: 2201 movs r2, #1
800194e: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8001952: f7fe ff6b bl 800082c <HAL_GetTick>
8001956: 6138 str r0, [r7, #16]
if (hspi->State != HAL_SPI_STATE_READY)
8001958: 68fb ldr r3, [r7, #12]
800195a: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
800195e: b2db uxtb r3, r3
8001960: 2b01 cmp r3, #1
8001962: d002 beq.n 800196a <HAL_SPI_Receive+0x72>
{
errorcode = HAL_BUSY;
8001964: 2302 movs r3, #2
8001966: 75fb strb r3, [r7, #23]
goto error;
8001968: e0ca b.n 8001b00 <HAL_SPI_Receive+0x208>
}
if ((pData == NULL) || (Size == 0U))
800196a: 68bb ldr r3, [r7, #8]
800196c: 2b00 cmp r3, #0
800196e: d002 beq.n 8001976 <HAL_SPI_Receive+0x7e>
8001970: 88fb ldrh r3, [r7, #6]
8001972: 2b00 cmp r3, #0
8001974: d102 bne.n 800197c <HAL_SPI_Receive+0x84>
{
errorcode = HAL_ERROR;
8001976: 2301 movs r3, #1
8001978: 75fb strb r3, [r7, #23]
goto error;
800197a: e0c1 b.n 8001b00 <HAL_SPI_Receive+0x208>
}
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
800197c: 68fb ldr r3, [r7, #12]
800197e: 2204 movs r2, #4
8001980: f883 2051 strb.w r2, [r3, #81] ; 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001984: 68fb ldr r3, [r7, #12]
8001986: 2200 movs r2, #0
8001988: 655a str r2, [r3, #84] ; 0x54
hspi->pRxBuffPtr = (uint8_t *)pData;
800198a: 68fb ldr r3, [r7, #12]
800198c: 68ba ldr r2, [r7, #8]
800198e: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferSize = Size;
8001990: 68fb ldr r3, [r7, #12]
8001992: 88fa ldrh r2, [r7, #6]
8001994: 879a strh r2, [r3, #60] ; 0x3c
hspi->RxXferCount = Size;
8001996: 68fb ldr r3, [r7, #12]
8001998: 88fa ldrh r2, [r7, #6]
800199a: 87da strh r2, [r3, #62] ; 0x3e
/*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
800199c: 68fb ldr r3, [r7, #12]
800199e: 2200 movs r2, #0
80019a0: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferSize = 0U;
80019a2: 68fb ldr r3, [r7, #12]
80019a4: 2200 movs r2, #0
80019a6: 869a strh r2, [r3, #52] ; 0x34
hspi->TxXferCount = 0U;
80019a8: 68fb ldr r3, [r7, #12]
80019aa: 2200 movs r2, #0
80019ac: 86da strh r2, [r3, #54] ; 0x36
hspi->RxISR = NULL;
80019ae: 68fb ldr r3, [r7, #12]
80019b0: 2200 movs r2, #0
80019b2: 641a str r2, [r3, #64] ; 0x40
hspi->TxISR = NULL;
80019b4: 68fb ldr r3, [r7, #12]
80019b6: 2200 movs r2, #0
80019b8: 645a str r2, [r3, #68] ; 0x44
hspi->RxXferCount--;
}
#endif /* USE_SPI_CRC */
/* Configure communication direction: 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
80019ba: 68fb ldr r3, [r7, #12]
80019bc: 689b ldr r3, [r3, #8]
80019be: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80019c2: d10f bne.n 80019e4 <HAL_SPI_Receive+0xec>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
80019c4: 68fb ldr r3, [r7, #12]
80019c6: 681b ldr r3, [r3, #0]
80019c8: 681a ldr r2, [r3, #0]
80019ca: 68fb ldr r3, [r7, #12]
80019cc: 681b ldr r3, [r3, #0]
80019ce: f022 0240 bic.w r2, r2, #64 ; 0x40
80019d2: 601a str r2, [r3, #0]
SPI_1LINE_RX(hspi);
80019d4: 68fb ldr r3, [r7, #12]
80019d6: 681b ldr r3, [r3, #0]
80019d8: 681a ldr r2, [r3, #0]
80019da: 68fb ldr r3, [r7, #12]
80019dc: 681b ldr r3, [r3, #0]
80019de: f422 4280 bic.w r2, r2, #16384 ; 0x4000
80019e2: 601a str r2, [r3, #0]
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
80019e4: 68fb ldr r3, [r7, #12]
80019e6: 681b ldr r3, [r3, #0]
80019e8: 681b ldr r3, [r3, #0]
80019ea: f003 0340 and.w r3, r3, #64 ; 0x40
80019ee: 2b40 cmp r3, #64 ; 0x40
80019f0: d007 beq.n 8001a02 <HAL_SPI_Receive+0x10a>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
80019f2: 68fb ldr r3, [r7, #12]
80019f4: 681b ldr r3, [r3, #0]
80019f6: 681a ldr r2, [r3, #0]
80019f8: 68fb ldr r3, [r7, #12]
80019fa: 681b ldr r3, [r3, #0]
80019fc: f042 0240 orr.w r2, r2, #64 ; 0x40
8001a00: 601a str r2, [r3, #0]
}
/* Receive data in 8 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
8001a02: 68fb ldr r3, [r7, #12]
8001a04: 68db ldr r3, [r3, #12]
8001a06: 2b00 cmp r3, #0
8001a08: d162 bne.n 8001ad0 <HAL_SPI_Receive+0x1d8>
{
/* Transfer loop */
while (hspi->RxXferCount > 0U)
8001a0a: e02e b.n 8001a6a <HAL_SPI_Receive+0x172>
{
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
8001a0c: 68fb ldr r3, [r7, #12]
8001a0e: 681b ldr r3, [r3, #0]
8001a10: 689b ldr r3, [r3, #8]
8001a12: f003 0301 and.w r3, r3, #1
8001a16: 2b01 cmp r3, #1
8001a18: d115 bne.n 8001a46 <HAL_SPI_Receive+0x14e>
{
/* read the received data */
(* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
8001a1a: 68fb ldr r3, [r7, #12]
8001a1c: 681b ldr r3, [r3, #0]
8001a1e: f103 020c add.w r2, r3, #12
8001a22: 68fb ldr r3, [r7, #12]
8001a24: 6b9b ldr r3, [r3, #56] ; 0x38
8001a26: 7812 ldrb r2, [r2, #0]
8001a28: b2d2 uxtb r2, r2
8001a2a: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint8_t);
8001a2c: 68fb ldr r3, [r7, #12]
8001a2e: 6b9b ldr r3, [r3, #56] ; 0x38
8001a30: 1c5a adds r2, r3, #1
8001a32: 68fb ldr r3, [r7, #12]
8001a34: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8001a36: 68fb ldr r3, [r7, #12]
8001a38: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001a3a: b29b uxth r3, r3
8001a3c: 3b01 subs r3, #1
8001a3e: b29a uxth r2, r3
8001a40: 68fb ldr r3, [r7, #12]
8001a42: 87da strh r2, [r3, #62] ; 0x3e
8001a44: e011 b.n 8001a6a <HAL_SPI_Receive+0x172>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
8001a46: f7fe fef1 bl 800082c <HAL_GetTick>
8001a4a: 4602 mov r2, r0
8001a4c: 693b ldr r3, [r7, #16]
8001a4e: 1ad3 subs r3, r2, r3
8001a50: 683a ldr r2, [r7, #0]
8001a52: 429a cmp r2, r3
8001a54: d803 bhi.n 8001a5e <HAL_SPI_Receive+0x166>
8001a56: 683b ldr r3, [r7, #0]
8001a58: f1b3 3fff cmp.w r3, #4294967295
8001a5c: d102 bne.n 8001a64 <HAL_SPI_Receive+0x16c>
8001a5e: 683b ldr r3, [r7, #0]
8001a60: 2b00 cmp r3, #0
8001a62: d102 bne.n 8001a6a <HAL_SPI_Receive+0x172>
{
errorcode = HAL_TIMEOUT;
8001a64: 2303 movs r3, #3
8001a66: 75fb strb r3, [r7, #23]
goto error;
8001a68: e04a b.n 8001b00 <HAL_SPI_Receive+0x208>
while (hspi->RxXferCount > 0U)
8001a6a: 68fb ldr r3, [r7, #12]
8001a6c: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001a6e: b29b uxth r3, r3
8001a70: 2b00 cmp r3, #0
8001a72: d1cb bne.n 8001a0c <HAL_SPI_Receive+0x114>
8001a74: e031 b.n 8001ada <HAL_SPI_Receive+0x1e2>
{
/* Transfer loop */
while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
8001a76: 68fb ldr r3, [r7, #12]
8001a78: 681b ldr r3, [r3, #0]
8001a7a: 689b ldr r3, [r3, #8]
8001a7c: f003 0301 and.w r3, r3, #1
8001a80: 2b01 cmp r3, #1
8001a82: d113 bne.n 8001aac <HAL_SPI_Receive+0x1b4>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8001a84: 68fb ldr r3, [r7, #12]
8001a86: 681b ldr r3, [r3, #0]
8001a88: 68da ldr r2, [r3, #12]
8001a8a: 68fb ldr r3, [r7, #12]
8001a8c: 6b9b ldr r3, [r3, #56] ; 0x38
8001a8e: b292 uxth r2, r2
8001a90: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8001a92: 68fb ldr r3, [r7, #12]
8001a94: 6b9b ldr r3, [r3, #56] ; 0x38
8001a96: 1c9a adds r2, r3, #2
8001a98: 68fb ldr r3, [r7, #12]
8001a9a: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8001a9c: 68fb ldr r3, [r7, #12]
8001a9e: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001aa0: b29b uxth r3, r3
8001aa2: 3b01 subs r3, #1
8001aa4: b29a uxth r2, r3
8001aa6: 68fb ldr r3, [r7, #12]
8001aa8: 87da strh r2, [r3, #62] ; 0x3e
8001aaa: e011 b.n 8001ad0 <HAL_SPI_Receive+0x1d8>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
8001aac: f7fe febe bl 800082c <HAL_GetTick>
8001ab0: 4602 mov r2, r0
8001ab2: 693b ldr r3, [r7, #16]
8001ab4: 1ad3 subs r3, r2, r3
8001ab6: 683a ldr r2, [r7, #0]
8001ab8: 429a cmp r2, r3
8001aba: d803 bhi.n 8001ac4 <HAL_SPI_Receive+0x1cc>
8001abc: 683b ldr r3, [r7, #0]
8001abe: f1b3 3fff cmp.w r3, #4294967295
8001ac2: d102 bne.n 8001aca <HAL_SPI_Receive+0x1d2>
8001ac4: 683b ldr r3, [r7, #0]
8001ac6: 2b00 cmp r3, #0
8001ac8: d102 bne.n 8001ad0 <HAL_SPI_Receive+0x1d8>
{
errorcode = HAL_TIMEOUT;
8001aca: 2303 movs r3, #3
8001acc: 75fb strb r3, [r7, #23]
goto error;
8001ace: e017 b.n 8001b00 <HAL_SPI_Receive+0x208>
while (hspi->RxXferCount > 0U)
8001ad0: 68fb ldr r3, [r7, #12]
8001ad2: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001ad4: b29b uxth r3, r3
8001ad6: 2b00 cmp r3, #0
8001ad8: d1cd bne.n 8001a76 <HAL_SPI_Receive+0x17e>
READ_REG(hspi->Instance->DR);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8001ada: 693a ldr r2, [r7, #16]
8001adc: 6839 ldr r1, [r7, #0]
8001ade: 68f8 ldr r0, [r7, #12]
8001ae0: f000 fa52 bl 8001f88 <SPI_EndRxTransaction>
8001ae4: 4603 mov r3, r0
8001ae6: 2b00 cmp r3, #0
8001ae8: d002 beq.n 8001af0 <HAL_SPI_Receive+0x1f8>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
8001aea: 68fb ldr r3, [r7, #12]
8001aec: 2220 movs r2, #32
8001aee: 655a str r2, [r3, #84] ; 0x54
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
8001af0: 68fb ldr r3, [r7, #12]
8001af2: 6d5b ldr r3, [r3, #84] ; 0x54
8001af4: 2b00 cmp r3, #0
8001af6: d002 beq.n 8001afe <HAL_SPI_Receive+0x206>
{
errorcode = HAL_ERROR;
8001af8: 2301 movs r3, #1
8001afa: 75fb strb r3, [r7, #23]
8001afc: e000 b.n 8001b00 <HAL_SPI_Receive+0x208>
}
error :
8001afe: bf00 nop
hspi->State = HAL_SPI_STATE_READY;
8001b00: 68fb ldr r3, [r7, #12]
8001b02: 2201 movs r2, #1
8001b04: f883 2051 strb.w r2, [r3, #81] ; 0x51
__HAL_UNLOCK(hspi);
8001b08: 68fb ldr r3, [r7, #12]
8001b0a: 2200 movs r2, #0
8001b0c: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
8001b10: 7dfb ldrb r3, [r7, #23]
}
8001b12: 4618 mov r0, r3
8001b14: 3718 adds r7, #24
8001b16: 46bd mov sp, r7
8001b18: bd80 pop {r7, pc}
08001b1a <HAL_SPI_TransmitReceive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
8001b1a: b580 push {r7, lr}
8001b1c: b08c sub sp, #48 ; 0x30
8001b1e: af00 add r7, sp, #0
8001b20: 60f8 str r0, [r7, #12]
8001b22: 60b9 str r1, [r7, #8]
8001b24: 607a str r2, [r7, #4]
8001b26: 807b strh r3, [r7, #2]
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
uint32_t tickstart;
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
8001b28: 2301 movs r3, #1
8001b2a: 62fb str r3, [r7, #44] ; 0x2c
HAL_StatusTypeDef errorcode = HAL_OK;
8001b2c: 2300 movs r3, #0
8001b2e: f887 302b strb.w r3, [r7, #43] ; 0x2b
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
8001b32: 68fb ldr r3, [r7, #12]
8001b34: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
8001b38: 2b01 cmp r3, #1
8001b3a: d101 bne.n 8001b40 <HAL_SPI_TransmitReceive+0x26>
8001b3c: 2302 movs r3, #2
8001b3e: e18a b.n 8001e56 <HAL_SPI_TransmitReceive+0x33c>
8001b40: 68fb ldr r3, [r7, #12]
8001b42: 2201 movs r2, #1
8001b44: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8001b48: f7fe fe70 bl 800082c <HAL_GetTick>
8001b4c: 6278 str r0, [r7, #36] ; 0x24
/* Init temporary variables */
tmp_state = hspi->State;
8001b4e: 68fb ldr r3, [r7, #12]
8001b50: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8001b54: f887 3023 strb.w r3, [r7, #35] ; 0x23
tmp_mode = hspi->Init.Mode;
8001b58: 68fb ldr r3, [r7, #12]
8001b5a: 685b ldr r3, [r3, #4]
8001b5c: 61fb str r3, [r7, #28]
initial_TxXferCount = Size;
8001b5e: 887b ldrh r3, [r7, #2]
8001b60: 837b strh r3, [r7, #26]
if (!((tmp_state == HAL_SPI_STATE_READY) || \
8001b62: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
8001b66: 2b01 cmp r3, #1
8001b68: d00f beq.n 8001b8a <HAL_SPI_TransmitReceive+0x70>
8001b6a: 69fb ldr r3, [r7, #28]
8001b6c: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001b70: d107 bne.n 8001b82 <HAL_SPI_TransmitReceive+0x68>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
8001b72: 68fb ldr r3, [r7, #12]
8001b74: 689b ldr r3, [r3, #8]
8001b76: 2b00 cmp r3, #0
8001b78: d103 bne.n 8001b82 <HAL_SPI_TransmitReceive+0x68>
8001b7a: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
8001b7e: 2b04 cmp r3, #4
8001b80: d003 beq.n 8001b8a <HAL_SPI_TransmitReceive+0x70>
{
errorcode = HAL_BUSY;
8001b82: 2302 movs r3, #2
8001b84: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8001b88: e15b b.n 8001e42 <HAL_SPI_TransmitReceive+0x328>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
8001b8a: 68bb ldr r3, [r7, #8]
8001b8c: 2b00 cmp r3, #0
8001b8e: d005 beq.n 8001b9c <HAL_SPI_TransmitReceive+0x82>
8001b90: 687b ldr r3, [r7, #4]
8001b92: 2b00 cmp r3, #0
8001b94: d002 beq.n 8001b9c <HAL_SPI_TransmitReceive+0x82>
8001b96: 887b ldrh r3, [r7, #2]
8001b98: 2b00 cmp r3, #0
8001b9a: d103 bne.n 8001ba4 <HAL_SPI_TransmitReceive+0x8a>
{
errorcode = HAL_ERROR;
8001b9c: 2301 movs r3, #1
8001b9e: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8001ba2: e14e b.n 8001e42 <HAL_SPI_TransmitReceive+0x328>
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
8001ba4: 68fb ldr r3, [r7, #12]
8001ba6: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8001baa: b2db uxtb r3, r3
8001bac: 2b04 cmp r3, #4
8001bae: d003 beq.n 8001bb8 <HAL_SPI_TransmitReceive+0x9e>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
8001bb0: 68fb ldr r3, [r7, #12]
8001bb2: 2205 movs r2, #5
8001bb4: f883 2051 strb.w r2, [r3, #81] ; 0x51
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001bb8: 68fb ldr r3, [r7, #12]
8001bba: 2200 movs r2, #0
8001bbc: 655a str r2, [r3, #84] ; 0x54
hspi->pRxBuffPtr = (uint8_t *)pRxData;
8001bbe: 68fb ldr r3, [r7, #12]
8001bc0: 687a ldr r2, [r7, #4]
8001bc2: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount = Size;
8001bc4: 68fb ldr r3, [r7, #12]
8001bc6: 887a ldrh r2, [r7, #2]
8001bc8: 87da strh r2, [r3, #62] ; 0x3e
hspi->RxXferSize = Size;
8001bca: 68fb ldr r3, [r7, #12]
8001bcc: 887a ldrh r2, [r7, #2]
8001bce: 879a strh r2, [r3, #60] ; 0x3c
hspi->pTxBuffPtr = (uint8_t *)pTxData;
8001bd0: 68fb ldr r3, [r7, #12]
8001bd2: 68ba ldr r2, [r7, #8]
8001bd4: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount = Size;
8001bd6: 68fb ldr r3, [r7, #12]
8001bd8: 887a ldrh r2, [r7, #2]
8001bda: 86da strh r2, [r3, #54] ; 0x36
hspi->TxXferSize = Size;
8001bdc: 68fb ldr r3, [r7, #12]
8001bde: 887a ldrh r2, [r7, #2]
8001be0: 869a strh r2, [r3, #52] ; 0x34
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
8001be2: 68fb ldr r3, [r7, #12]
8001be4: 2200 movs r2, #0
8001be6: 641a str r2, [r3, #64] ; 0x40
hspi->TxISR = NULL;
8001be8: 68fb ldr r3, [r7, #12]
8001bea: 2200 movs r2, #0
8001bec: 645a str r2, [r3, #68] ; 0x44
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8001bee: 68fb ldr r3, [r7, #12]
8001bf0: 681b ldr r3, [r3, #0]
8001bf2: 681b ldr r3, [r3, #0]
8001bf4: f003 0340 and.w r3, r3, #64 ; 0x40
8001bf8: 2b40 cmp r3, #64 ; 0x40
8001bfa: d007 beq.n 8001c0c <HAL_SPI_TransmitReceive+0xf2>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8001bfc: 68fb ldr r3, [r7, #12]
8001bfe: 681b ldr r3, [r3, #0]
8001c00: 681a ldr r2, [r3, #0]
8001c02: 68fb ldr r3, [r7, #12]
8001c04: 681b ldr r3, [r3, #0]
8001c06: f042 0240 orr.w r2, r2, #64 ; 0x40
8001c0a: 601a str r2, [r3, #0]
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
8001c0c: 68fb ldr r3, [r7, #12]
8001c0e: 68db ldr r3, [r3, #12]
8001c10: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8001c14: d178 bne.n 8001d08 <HAL_SPI_TransmitReceive+0x1ee>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8001c16: 68fb ldr r3, [r7, #12]
8001c18: 685b ldr r3, [r3, #4]
8001c1a: 2b00 cmp r3, #0
8001c1c: d002 beq.n 8001c24 <HAL_SPI_TransmitReceive+0x10a>
8001c1e: 8b7b ldrh r3, [r7, #26]
8001c20: 2b01 cmp r3, #1
8001c22: d166 bne.n 8001cf2 <HAL_SPI_TransmitReceive+0x1d8>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8001c24: 68fb ldr r3, [r7, #12]
8001c26: 6b1b ldr r3, [r3, #48] ; 0x30
8001c28: 881a ldrh r2, [r3, #0]
8001c2a: 68fb ldr r3, [r7, #12]
8001c2c: 681b ldr r3, [r3, #0]
8001c2e: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8001c30: 68fb ldr r3, [r7, #12]
8001c32: 6b1b ldr r3, [r3, #48] ; 0x30
8001c34: 1c9a adds r2, r3, #2
8001c36: 68fb ldr r3, [r7, #12]
8001c38: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8001c3a: 68fb ldr r3, [r7, #12]
8001c3c: 8edb ldrh r3, [r3, #54] ; 0x36
8001c3e: b29b uxth r3, r3
8001c40: 3b01 subs r3, #1
8001c42: b29a uxth r2, r3
8001c44: 68fb ldr r3, [r7, #12]
8001c46: 86da strh r2, [r3, #54] ; 0x36
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8001c48: e053 b.n 8001cf2 <HAL_SPI_TransmitReceive+0x1d8>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8001c4a: 68fb ldr r3, [r7, #12]
8001c4c: 681b ldr r3, [r3, #0]
8001c4e: 689b ldr r3, [r3, #8]
8001c50: f003 0302 and.w r3, r3, #2
8001c54: 2b02 cmp r3, #2
8001c56: d11b bne.n 8001c90 <HAL_SPI_TransmitReceive+0x176>
8001c58: 68fb ldr r3, [r7, #12]
8001c5a: 8edb ldrh r3, [r3, #54] ; 0x36
8001c5c: b29b uxth r3, r3
8001c5e: 2b00 cmp r3, #0
8001c60: d016 beq.n 8001c90 <HAL_SPI_TransmitReceive+0x176>
8001c62: 6afb ldr r3, [r7, #44] ; 0x2c
8001c64: 2b01 cmp r3, #1
8001c66: d113 bne.n 8001c90 <HAL_SPI_TransmitReceive+0x176>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8001c68: 68fb ldr r3, [r7, #12]
8001c6a: 6b1b ldr r3, [r3, #48] ; 0x30
8001c6c: 881a ldrh r2, [r3, #0]
8001c6e: 68fb ldr r3, [r7, #12]
8001c70: 681b ldr r3, [r3, #0]
8001c72: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8001c74: 68fb ldr r3, [r7, #12]
8001c76: 6b1b ldr r3, [r3, #48] ; 0x30
8001c78: 1c9a adds r2, r3, #2
8001c7a: 68fb ldr r3, [r7, #12]
8001c7c: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8001c7e: 68fb ldr r3, [r7, #12]
8001c80: 8edb ldrh r3, [r3, #54] ; 0x36
8001c82: b29b uxth r3, r3
8001c84: 3b01 subs r3, #1
8001c86: b29a uxth r2, r3
8001c88: 68fb ldr r3, [r7, #12]
8001c8a: 86da strh r2, [r3, #54] ; 0x36
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8001c8c: 2300 movs r3, #0
8001c8e: 62fb str r3, [r7, #44] ; 0x2c
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
8001c90: 68fb ldr r3, [r7, #12]
8001c92: 681b ldr r3, [r3, #0]
8001c94: 689b ldr r3, [r3, #8]
8001c96: f003 0301 and.w r3, r3, #1
8001c9a: 2b01 cmp r3, #1
8001c9c: d119 bne.n 8001cd2 <HAL_SPI_TransmitReceive+0x1b8>
8001c9e: 68fb ldr r3, [r7, #12]
8001ca0: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001ca2: b29b uxth r3, r3
8001ca4: 2b00 cmp r3, #0
8001ca6: d014 beq.n 8001cd2 <HAL_SPI_TransmitReceive+0x1b8>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8001ca8: 68fb ldr r3, [r7, #12]
8001caa: 681b ldr r3, [r3, #0]
8001cac: 68da ldr r2, [r3, #12]
8001cae: 68fb ldr r3, [r7, #12]
8001cb0: 6b9b ldr r3, [r3, #56] ; 0x38
8001cb2: b292 uxth r2, r2
8001cb4: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8001cb6: 68fb ldr r3, [r7, #12]
8001cb8: 6b9b ldr r3, [r3, #56] ; 0x38
8001cba: 1c9a adds r2, r3, #2
8001cbc: 68fb ldr r3, [r7, #12]
8001cbe: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8001cc0: 68fb ldr r3, [r7, #12]
8001cc2: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001cc4: b29b uxth r3, r3
8001cc6: 3b01 subs r3, #1
8001cc8: b29a uxth r2, r3
8001cca: 68fb ldr r3, [r7, #12]
8001ccc: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8001cce: 2301 movs r3, #1
8001cd0: 62fb str r3, [r7, #44] ; 0x2c
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
8001cd2: f7fe fdab bl 800082c <HAL_GetTick>
8001cd6: 4602 mov r2, r0
8001cd8: 6a7b ldr r3, [r7, #36] ; 0x24
8001cda: 1ad3 subs r3, r2, r3
8001cdc: 6bba ldr r2, [r7, #56] ; 0x38
8001cde: 429a cmp r2, r3
8001ce0: d807 bhi.n 8001cf2 <HAL_SPI_TransmitReceive+0x1d8>
8001ce2: 6bbb ldr r3, [r7, #56] ; 0x38
8001ce4: f1b3 3fff cmp.w r3, #4294967295
8001ce8: d003 beq.n 8001cf2 <HAL_SPI_TransmitReceive+0x1d8>
{
errorcode = HAL_TIMEOUT;
8001cea: 2303 movs r3, #3
8001cec: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8001cf0: e0a7 b.n 8001e42 <HAL_SPI_TransmitReceive+0x328>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8001cf2: 68fb ldr r3, [r7, #12]
8001cf4: 8edb ldrh r3, [r3, #54] ; 0x36
8001cf6: b29b uxth r3, r3
8001cf8: 2b00 cmp r3, #0
8001cfa: d1a6 bne.n 8001c4a <HAL_SPI_TransmitReceive+0x130>
8001cfc: 68fb ldr r3, [r7, #12]
8001cfe: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001d00: b29b uxth r3, r3
8001d02: 2b00 cmp r3, #0
8001d04: d1a1 bne.n 8001c4a <HAL_SPI_TransmitReceive+0x130>
8001d06: e07c b.n 8001e02 <HAL_SPI_TransmitReceive+0x2e8>
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8001d08: 68fb ldr r3, [r7, #12]
8001d0a: 685b ldr r3, [r3, #4]
8001d0c: 2b00 cmp r3, #0
8001d0e: d002 beq.n 8001d16 <HAL_SPI_TransmitReceive+0x1fc>
8001d10: 8b7b ldrh r3, [r7, #26]
8001d12: 2b01 cmp r3, #1
8001d14: d16b bne.n 8001dee <HAL_SPI_TransmitReceive+0x2d4>
{
*((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
8001d16: 68fb ldr r3, [r7, #12]
8001d18: 6b1a ldr r2, [r3, #48] ; 0x30
8001d1a: 68fb ldr r3, [r7, #12]
8001d1c: 681b ldr r3, [r3, #0]
8001d1e: 330c adds r3, #12
8001d20: 7812 ldrb r2, [r2, #0]
8001d22: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
8001d24: 68fb ldr r3, [r7, #12]
8001d26: 6b1b ldr r3, [r3, #48] ; 0x30
8001d28: 1c5a adds r2, r3, #1
8001d2a: 68fb ldr r3, [r7, #12]
8001d2c: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8001d2e: 68fb ldr r3, [r7, #12]
8001d30: 8edb ldrh r3, [r3, #54] ; 0x36
8001d32: b29b uxth r3, r3
8001d34: 3b01 subs r3, #1
8001d36: b29a uxth r2, r3
8001d38: 68fb ldr r3, [r7, #12]
8001d3a: 86da strh r2, [r3, #54] ; 0x36
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8001d3c: e057 b.n 8001dee <HAL_SPI_TransmitReceive+0x2d4>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8001d3e: 68fb ldr r3, [r7, #12]
8001d40: 681b ldr r3, [r3, #0]
8001d42: 689b ldr r3, [r3, #8]
8001d44: f003 0302 and.w r3, r3, #2
8001d48: 2b02 cmp r3, #2
8001d4a: d11c bne.n 8001d86 <HAL_SPI_TransmitReceive+0x26c>
8001d4c: 68fb ldr r3, [r7, #12]
8001d4e: 8edb ldrh r3, [r3, #54] ; 0x36
8001d50: b29b uxth r3, r3
8001d52: 2b00 cmp r3, #0
8001d54: d017 beq.n 8001d86 <HAL_SPI_TransmitReceive+0x26c>
8001d56: 6afb ldr r3, [r7, #44] ; 0x2c
8001d58: 2b01 cmp r3, #1
8001d5a: d114 bne.n 8001d86 <HAL_SPI_TransmitReceive+0x26c>
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
8001d5c: 68fb ldr r3, [r7, #12]
8001d5e: 6b1a ldr r2, [r3, #48] ; 0x30
8001d60: 68fb ldr r3, [r7, #12]
8001d62: 681b ldr r3, [r3, #0]
8001d64: 330c adds r3, #12
8001d66: 7812 ldrb r2, [r2, #0]
8001d68: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
8001d6a: 68fb ldr r3, [r7, #12]
8001d6c: 6b1b ldr r3, [r3, #48] ; 0x30
8001d6e: 1c5a adds r2, r3, #1
8001d70: 68fb ldr r3, [r7, #12]
8001d72: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8001d74: 68fb ldr r3, [r7, #12]
8001d76: 8edb ldrh r3, [r3, #54] ; 0x36
8001d78: b29b uxth r3, r3
8001d7a: 3b01 subs r3, #1
8001d7c: b29a uxth r2, r3
8001d7e: 68fb ldr r3, [r7, #12]
8001d80: 86da strh r2, [r3, #54] ; 0x36
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8001d82: 2300 movs r3, #0
8001d84: 62fb str r3, [r7, #44] ; 0x2c
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
8001d86: 68fb ldr r3, [r7, #12]
8001d88: 681b ldr r3, [r3, #0]
8001d8a: 689b ldr r3, [r3, #8]
8001d8c: f003 0301 and.w r3, r3, #1
8001d90: 2b01 cmp r3, #1
8001d92: d119 bne.n 8001dc8 <HAL_SPI_TransmitReceive+0x2ae>
8001d94: 68fb ldr r3, [r7, #12]
8001d96: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001d98: b29b uxth r3, r3
8001d9a: 2b00 cmp r3, #0
8001d9c: d014 beq.n 8001dc8 <HAL_SPI_TransmitReceive+0x2ae>
{
(*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
8001d9e: 68fb ldr r3, [r7, #12]
8001da0: 681b ldr r3, [r3, #0]
8001da2: 68da ldr r2, [r3, #12]
8001da4: 68fb ldr r3, [r7, #12]
8001da6: 6b9b ldr r3, [r3, #56] ; 0x38
8001da8: b2d2 uxtb r2, r2
8001daa: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr++;
8001dac: 68fb ldr r3, [r7, #12]
8001dae: 6b9b ldr r3, [r3, #56] ; 0x38
8001db0: 1c5a adds r2, r3, #1
8001db2: 68fb ldr r3, [r7, #12]
8001db4: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8001db6: 68fb ldr r3, [r7, #12]
8001db8: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001dba: b29b uxth r3, r3
8001dbc: 3b01 subs r3, #1
8001dbe: b29a uxth r2, r3
8001dc0: 68fb ldr r3, [r7, #12]
8001dc2: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8001dc4: 2301 movs r3, #1
8001dc6: 62fb str r3, [r7, #44] ; 0x2c
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
8001dc8: f7fe fd30 bl 800082c <HAL_GetTick>
8001dcc: 4602 mov r2, r0
8001dce: 6a7b ldr r3, [r7, #36] ; 0x24
8001dd0: 1ad3 subs r3, r2, r3
8001dd2: 6bba ldr r2, [r7, #56] ; 0x38
8001dd4: 429a cmp r2, r3
8001dd6: d803 bhi.n 8001de0 <HAL_SPI_TransmitReceive+0x2c6>
8001dd8: 6bbb ldr r3, [r7, #56] ; 0x38
8001dda: f1b3 3fff cmp.w r3, #4294967295
8001dde: d102 bne.n 8001de6 <HAL_SPI_TransmitReceive+0x2cc>
8001de0: 6bbb ldr r3, [r7, #56] ; 0x38
8001de2: 2b00 cmp r3, #0
8001de4: d103 bne.n 8001dee <HAL_SPI_TransmitReceive+0x2d4>
{
errorcode = HAL_TIMEOUT;
8001de6: 2303 movs r3, #3
8001de8: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8001dec: e029 b.n 8001e42 <HAL_SPI_TransmitReceive+0x328>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8001dee: 68fb ldr r3, [r7, #12]
8001df0: 8edb ldrh r3, [r3, #54] ; 0x36
8001df2: b29b uxth r3, r3
8001df4: 2b00 cmp r3, #0
8001df6: d1a2 bne.n 8001d3e <HAL_SPI_TransmitReceive+0x224>
8001df8: 68fb ldr r3, [r7, #12]
8001dfa: 8fdb ldrh r3, [r3, #62] ; 0x3e
8001dfc: b29b uxth r3, r3
8001dfe: 2b00 cmp r3, #0
8001e00: d19d bne.n 8001d3e <HAL_SPI_TransmitReceive+0x224>
}
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8001e02: 6a7a ldr r2, [r7, #36] ; 0x24
8001e04: 6bb9 ldr r1, [r7, #56] ; 0x38
8001e06: 68f8 ldr r0, [r7, #12]
8001e08: f000 f910 bl 800202c <SPI_EndRxTxTransaction>
8001e0c: 4603 mov r3, r0
8001e0e: 2b00 cmp r3, #0
8001e10: d006 beq.n 8001e20 <HAL_SPI_TransmitReceive+0x306>
{
errorcode = HAL_ERROR;
8001e12: 2301 movs r3, #1
8001e14: f887 302b strb.w r3, [r7, #43] ; 0x2b
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
8001e18: 68fb ldr r3, [r7, #12]
8001e1a: 2220 movs r2, #32
8001e1c: 655a str r2, [r3, #84] ; 0x54
goto error;
8001e1e: e010 b.n 8001e42 <HAL_SPI_TransmitReceive+0x328>
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
8001e20: 68fb ldr r3, [r7, #12]
8001e22: 689b ldr r3, [r3, #8]
8001e24: 2b00 cmp r3, #0
8001e26: d10b bne.n 8001e40 <HAL_SPI_TransmitReceive+0x326>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
8001e28: 2300 movs r3, #0
8001e2a: 617b str r3, [r7, #20]
8001e2c: 68fb ldr r3, [r7, #12]
8001e2e: 681b ldr r3, [r3, #0]
8001e30: 68db ldr r3, [r3, #12]
8001e32: 617b str r3, [r7, #20]
8001e34: 68fb ldr r3, [r7, #12]
8001e36: 681b ldr r3, [r3, #0]
8001e38: 689b ldr r3, [r3, #8]
8001e3a: 617b str r3, [r7, #20]
8001e3c: 697b ldr r3, [r7, #20]
8001e3e: e000 b.n 8001e42 <HAL_SPI_TransmitReceive+0x328>
}
error :
8001e40: bf00 nop
hspi->State = HAL_SPI_STATE_READY;
8001e42: 68fb ldr r3, [r7, #12]
8001e44: 2201 movs r2, #1
8001e46: f883 2051 strb.w r2, [r3, #81] ; 0x51
__HAL_UNLOCK(hspi);
8001e4a: 68fb ldr r3, [r7, #12]
8001e4c: 2200 movs r2, #0
8001e4e: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
8001e52: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
}
8001e56: 4618 mov r0, r3
8001e58: 3730 adds r7, #48 ; 0x30
8001e5a: 46bd mov sp, r7
8001e5c: bd80 pop {r7, pc}
08001e5e <HAL_SPI_GetState>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
8001e5e: b480 push {r7}
8001e60: b083 sub sp, #12
8001e62: af00 add r7, sp, #0
8001e64: 6078 str r0, [r7, #4]
/* Return SPI handle state */
return hspi->State;
8001e66: 687b ldr r3, [r7, #4]
8001e68: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8001e6c: b2db uxtb r3, r3
}
8001e6e: 4618 mov r0, r3
8001e70: 370c adds r7, #12
8001e72: 46bd mov sp, r7
8001e74: bc80 pop {r7}
8001e76: 4770 bx lr
08001e78 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8001e78: b580 push {r7, lr}
8001e7a: b088 sub sp, #32
8001e7c: af00 add r7, sp, #0
8001e7e: 60f8 str r0, [r7, #12]
8001e80: 60b9 str r1, [r7, #8]
8001e82: 603b str r3, [r7, #0]
8001e84: 4613 mov r3, r2
8001e86: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8001e88: f7fe fcd0 bl 800082c <HAL_GetTick>
8001e8c: 4602 mov r2, r0
8001e8e: 6abb ldr r3, [r7, #40] ; 0x28
8001e90: 1a9b subs r3, r3, r2
8001e92: 683a ldr r2, [r7, #0]
8001e94: 4413 add r3, r2
8001e96: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
8001e98: f7fe fcc8 bl 800082c <HAL_GetTick>
8001e9c: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
8001e9e: 4b39 ldr r3, [pc, #228] ; (8001f84 <SPI_WaitFlagStateUntilTimeout+0x10c>)
8001ea0: 681b ldr r3, [r3, #0]
8001ea2: 015b lsls r3, r3, #5
8001ea4: 0d1b lsrs r3, r3, #20
8001ea6: 69fa ldr r2, [r7, #28]
8001ea8: fb02 f303 mul.w r3, r2, r3
8001eac: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8001eae: e054 b.n 8001f5a <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
8001eb0: 683b ldr r3, [r7, #0]
8001eb2: f1b3 3fff cmp.w r3, #4294967295
8001eb6: d050 beq.n 8001f5a <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8001eb8: f7fe fcb8 bl 800082c <HAL_GetTick>
8001ebc: 4602 mov r2, r0
8001ebe: 69bb ldr r3, [r7, #24]
8001ec0: 1ad3 subs r3, r2, r3
8001ec2: 69fa ldr r2, [r7, #28]
8001ec4: 429a cmp r2, r3
8001ec6: d902 bls.n 8001ece <SPI_WaitFlagStateUntilTimeout+0x56>
8001ec8: 69fb ldr r3, [r7, #28]
8001eca: 2b00 cmp r3, #0
8001ecc: d13d bne.n 8001f4a <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8001ece: 68fb ldr r3, [r7, #12]
8001ed0: 681b ldr r3, [r3, #0]
8001ed2: 685a ldr r2, [r3, #4]
8001ed4: 68fb ldr r3, [r7, #12]
8001ed6: 681b ldr r3, [r3, #0]
8001ed8: f022 02e0 bic.w r2, r2, #224 ; 0xe0
8001edc: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8001ede: 68fb ldr r3, [r7, #12]
8001ee0: 685b ldr r3, [r3, #4]
8001ee2: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001ee6: d111 bne.n 8001f0c <SPI_WaitFlagStateUntilTimeout+0x94>
8001ee8: 68fb ldr r3, [r7, #12]
8001eea: 689b ldr r3, [r3, #8]
8001eec: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8001ef0: d004 beq.n 8001efc <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8001ef2: 68fb ldr r3, [r7, #12]
8001ef4: 689b ldr r3, [r3, #8]
8001ef6: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8001efa: d107 bne.n 8001f0c <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8001efc: 68fb ldr r3, [r7, #12]
8001efe: 681b ldr r3, [r3, #0]
8001f00: 681a ldr r2, [r3, #0]
8001f02: 68fb ldr r3, [r7, #12]
8001f04: 681b ldr r3, [r3, #0]
8001f06: f022 0240 bic.w r2, r2, #64 ; 0x40
8001f0a: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8001f0c: 68fb ldr r3, [r7, #12]
8001f0e: 6a9b ldr r3, [r3, #40] ; 0x28
8001f10: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8001f14: d10f bne.n 8001f36 <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
8001f16: 68fb ldr r3, [r7, #12]
8001f18: 681b ldr r3, [r3, #0]
8001f1a: 681a ldr r2, [r3, #0]
8001f1c: 68fb ldr r3, [r7, #12]
8001f1e: 681b ldr r3, [r3, #0]
8001f20: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8001f24: 601a str r2, [r3, #0]
8001f26: 68fb ldr r3, [r7, #12]
8001f28: 681b ldr r3, [r3, #0]
8001f2a: 681a ldr r2, [r3, #0]
8001f2c: 68fb ldr r3, [r7, #12]
8001f2e: 681b ldr r3, [r3, #0]
8001f30: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8001f34: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
8001f36: 68fb ldr r3, [r7, #12]
8001f38: 2201 movs r2, #1
8001f3a: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8001f3e: 68fb ldr r3, [r7, #12]
8001f40: 2200 movs r2, #0
8001f42: f883 2050 strb.w r2, [r3, #80] ; 0x50
return HAL_TIMEOUT;
8001f46: 2303 movs r3, #3
8001f48: e017 b.n 8001f7a <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if(count == 0U)
8001f4a: 697b ldr r3, [r7, #20]
8001f4c: 2b00 cmp r3, #0
8001f4e: d101 bne.n 8001f54 <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
8001f50: 2300 movs r3, #0
8001f52: 61fb str r3, [r7, #28]
}
count--;
8001f54: 697b ldr r3, [r7, #20]
8001f56: 3b01 subs r3, #1
8001f58: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8001f5a: 68fb ldr r3, [r7, #12]
8001f5c: 681b ldr r3, [r3, #0]
8001f5e: 689a ldr r2, [r3, #8]
8001f60: 68bb ldr r3, [r7, #8]
8001f62: 4013 ands r3, r2
8001f64: 68ba ldr r2, [r7, #8]
8001f66: 429a cmp r2, r3
8001f68: bf0c ite eq
8001f6a: 2301 moveq r3, #1
8001f6c: 2300 movne r3, #0
8001f6e: b2db uxtb r3, r3
8001f70: 461a mov r2, r3
8001f72: 79fb ldrb r3, [r7, #7]
8001f74: 429a cmp r2, r3
8001f76: d19b bne.n 8001eb0 <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
8001f78: 2300 movs r3, #0
}
8001f7a: 4618 mov r0, r3
8001f7c: 3720 adds r7, #32
8001f7e: 46bd mov sp, r7
8001f80: bd80 pop {r7, pc}
8001f82: bf00 nop
8001f84: 20000000 .word 0x20000000
08001f88 <SPI_EndRxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8001f88: b580 push {r7, lr}
8001f8a: b086 sub sp, #24
8001f8c: af02 add r7, sp, #8
8001f8e: 60f8 str r0, [r7, #12]
8001f90: 60b9 str r1, [r7, #8]
8001f92: 607a str r2, [r7, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8001f94: 68fb ldr r3, [r7, #12]
8001f96: 685b ldr r3, [r3, #4]
8001f98: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001f9c: d111 bne.n 8001fc2 <SPI_EndRxTransaction+0x3a>
8001f9e: 68fb ldr r3, [r7, #12]
8001fa0: 689b ldr r3, [r3, #8]
8001fa2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8001fa6: d004 beq.n 8001fb2 <SPI_EndRxTransaction+0x2a>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8001fa8: 68fb ldr r3, [r7, #12]
8001faa: 689b ldr r3, [r3, #8]
8001fac: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8001fb0: d107 bne.n 8001fc2 <SPI_EndRxTransaction+0x3a>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8001fb2: 68fb ldr r3, [r7, #12]
8001fb4: 681b ldr r3, [r3, #0]
8001fb6: 681a ldr r2, [r3, #0]
8001fb8: 68fb ldr r3, [r7, #12]
8001fba: 681b ldr r3, [r3, #0]
8001fbc: f022 0240 bic.w r2, r2, #64 ; 0x40
8001fc0: 601a str r2, [r3, #0]
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
8001fc2: 68fb ldr r3, [r7, #12]
8001fc4: 685b ldr r3, [r3, #4]
8001fc6: f5b3 7f82 cmp.w r3, #260 ; 0x104
8001fca: d117 bne.n 8001ffc <SPI_EndRxTransaction+0x74>
8001fcc: 68fb ldr r3, [r7, #12]
8001fce: 689b ldr r3, [r3, #8]
8001fd0: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8001fd4: d112 bne.n 8001ffc <SPI_EndRxTransaction+0x74>
{
/* Wait the RXNE reset */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
8001fd6: 687b ldr r3, [r7, #4]
8001fd8: 9300 str r3, [sp, #0]
8001fda: 68bb ldr r3, [r7, #8]
8001fdc: 2200 movs r2, #0
8001fde: 2101 movs r1, #1
8001fe0: 68f8 ldr r0, [r7, #12]
8001fe2: f7ff ff49 bl 8001e78 <SPI_WaitFlagStateUntilTimeout>
8001fe6: 4603 mov r3, r0
8001fe8: 2b00 cmp r3, #0
8001fea: d01a beq.n 8002022 <SPI_EndRxTransaction+0x9a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8001fec: 68fb ldr r3, [r7, #12]
8001fee: 6d5b ldr r3, [r3, #84] ; 0x54
8001ff0: f043 0220 orr.w r2, r3, #32
8001ff4: 68fb ldr r3, [r7, #12]
8001ff6: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
8001ff8: 2303 movs r3, #3
8001ffa: e013 b.n 8002024 <SPI_EndRxTransaction+0x9c>
}
}
else
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8001ffc: 687b ldr r3, [r7, #4]
8001ffe: 9300 str r3, [sp, #0]
8002000: 68bb ldr r3, [r7, #8]
8002002: 2200 movs r2, #0
8002004: 2180 movs r1, #128 ; 0x80
8002006: 68f8 ldr r0, [r7, #12]
8002008: f7ff ff36 bl 8001e78 <SPI_WaitFlagStateUntilTimeout>
800200c: 4603 mov r3, r0
800200e: 2b00 cmp r3, #0
8002010: d007 beq.n 8002022 <SPI_EndRxTransaction+0x9a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002012: 68fb ldr r3, [r7, #12]
8002014: 6d5b ldr r3, [r3, #84] ; 0x54
8002016: f043 0220 orr.w r2, r3, #32
800201a: 68fb ldr r3, [r7, #12]
800201c: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
800201e: 2303 movs r3, #3
8002020: e000 b.n 8002024 <SPI_EndRxTransaction+0x9c>
}
}
return HAL_OK;
8002022: 2300 movs r3, #0
}
8002024: 4618 mov r0, r3
8002026: 3710 adds r7, #16
8002028: 46bd mov sp, r7
800202a: bd80 pop {r7, pc}
0800202c <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
800202c: b580 push {r7, lr}
800202e: b086 sub sp, #24
8002030: af02 add r7, sp, #8
8002032: 60f8 str r0, [r7, #12]
8002034: 60b9 str r1, [r7, #8]
8002036: 607a str r2, [r7, #4]
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8002038: 687b ldr r3, [r7, #4]
800203a: 9300 str r3, [sp, #0]
800203c: 68bb ldr r3, [r7, #8]
800203e: 2200 movs r2, #0
8002040: 2180 movs r1, #128 ; 0x80
8002042: 68f8 ldr r0, [r7, #12]
8002044: f7ff ff18 bl 8001e78 <SPI_WaitFlagStateUntilTimeout>
8002048: 4603 mov r3, r0
800204a: 2b00 cmp r3, #0
800204c: d007 beq.n 800205e <SPI_EndRxTxTransaction+0x32>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800204e: 68fb ldr r3, [r7, #12]
8002050: 6d5b ldr r3, [r3, #84] ; 0x54
8002052: f043 0220 orr.w r2, r3, #32
8002056: 68fb ldr r3, [r7, #12]
8002058: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
800205a: 2303 movs r3, #3
800205c: e000 b.n 8002060 <SPI_EndRxTxTransaction+0x34>
}
return HAL_OK;
800205e: 2300 movs r3, #0
}
8002060: 4618 mov r0, r3
8002062: 3710 adds r7, #16
8002064: 46bd mov sp, r7
8002066: bd80 pop {r7, pc}
08002068 <HAL_SRAM_Init>:
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
8002068: b580 push {r7, lr}
800206a: b084 sub sp, #16
800206c: af00 add r7, sp, #0
800206e: 60f8 str r0, [r7, #12]
8002070: 60b9 str r1, [r7, #8]
8002072: 607a str r2, [r7, #4]
/* Check the SRAM handle parameter */
if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
8002074: 68fb ldr r3, [r7, #12]
8002076: 2b00 cmp r3, #0
8002078: d004 beq.n 8002084 <HAL_SRAM_Init+0x1c>
800207a: 68fb ldr r3, [r7, #12]
800207c: 699b ldr r3, [r3, #24]
800207e: f5b3 7f80 cmp.w r3, #256 ; 0x100
8002082: d101 bne.n 8002088 <HAL_SRAM_Init+0x20>
{
return HAL_ERROR;
8002084: 2301 movs r3, #1
8002086: e038 b.n 80020fa <HAL_SRAM_Init+0x92>
}
if (hsram->State == HAL_SRAM_STATE_RESET)
8002088: 68fb ldr r3, [r7, #12]
800208a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800208e: b2db uxtb r3, r3
8002090: 2b00 cmp r3, #0
8002092: d106 bne.n 80020a2 <HAL_SRAM_Init+0x3a>
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
8002094: 68fb ldr r3, [r7, #12]
8002096: 2200 movs r2, #0
8002098: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware */
hsram->MspInitCallback(hsram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
800209c: 68f8 ldr r0, [r7, #12]
800209e: f7fe fb0f bl 80006c0 <HAL_SRAM_MspInit>
#endif
}
/* Initialize SRAM control Interface */
(void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
80020a2: 68fb ldr r3, [r7, #12]
80020a4: 681a ldr r2, [r3, #0]
80020a6: 68fb ldr r3, [r7, #12]
80020a8: 3308 adds r3, #8
80020aa: 4619 mov r1, r3
80020ac: 4610 mov r0, r2
80020ae: f000 f829 bl 8002104 <FSMC_NORSRAM_Init>
/* Initialize SRAM timing Interface */
(void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
80020b2: 68fb ldr r3, [r7, #12]
80020b4: 6818 ldr r0, [r3, #0]
80020b6: 68fb ldr r3, [r7, #12]
80020b8: 689b ldr r3, [r3, #8]
80020ba: 461a mov r2, r3
80020bc: 68b9 ldr r1, [r7, #8]
80020be: f000 f88b bl 80021d8 <FSMC_NORSRAM_Timing_Init>
/* Initialize SRAM extended mode timing Interface */
(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
80020c2: 68fb ldr r3, [r7, #12]
80020c4: 6858 ldr r0, [r3, #4]
80020c6: 68fb ldr r3, [r7, #12]
80020c8: 689a ldr r2, [r3, #8]
80020ca: 68fb ldr r3, [r7, #12]
80020cc: 6b1b ldr r3, [r3, #48] ; 0x30
80020ce: 6879 ldr r1, [r7, #4]
80020d0: f000 f8b6 bl 8002240 <FSMC_NORSRAM_Extended_Timing_Init>
hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
80020d4: 68fb ldr r3, [r7, #12]
80020d6: 681b ldr r3, [r3, #0]
80020d8: 68fa ldr r2, [r7, #12]
80020da: 6892 ldr r2, [r2, #8]
80020dc: f853 1022 ldr.w r1, [r3, r2, lsl #2]
80020e0: 68fb ldr r3, [r7, #12]
80020e2: 681b ldr r3, [r3, #0]
80020e4: 68fa ldr r2, [r7, #12]
80020e6: 6892 ldr r2, [r2, #8]
80020e8: f041 0101 orr.w r1, r1, #1
80020ec: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Initialize the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
80020f0: 68fb ldr r3, [r7, #12]
80020f2: 2201 movs r2, #1
80020f4: f883 2041 strb.w r2, [r3, #65] ; 0x41
return HAL_OK;
80020f8: 2300 movs r3, #0
}
80020fa: 4618 mov r0, r3
80020fc: 3710 adds r7, #16
80020fe: 46bd mov sp, r7
8002100: bd80 pop {r7, pc}
...
08002104 <FSMC_NORSRAM_Init>:
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
FSMC_NORSRAM_InitTypeDef *Init)
{
8002104: b480 push {r7}
8002106: b087 sub sp, #28
8002108: af00 add r7, sp, #0
800210a: 6078 str r0, [r7, #4]
800210c: 6039 str r1, [r7, #0]
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
/* Disable NORSRAM Device */
__FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
800210e: 683b ldr r3, [r7, #0]
8002110: 681a ldr r2, [r3, #0]
8002112: 687b ldr r3, [r7, #4]
8002114: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8002118: 683a ldr r2, [r7, #0]
800211a: 6812 ldr r2, [r2, #0]
800211c: f023 0101 bic.w r1, r3, #1
8002120: 687b ldr r3, [r7, #4]
8002122: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Set NORSRAM device control parameters */
if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
8002126: 683b ldr r3, [r7, #0]
8002128: 689b ldr r3, [r3, #8]
800212a: 2b08 cmp r3, #8
800212c: d102 bne.n 8002134 <FSMC_NORSRAM_Init+0x30>
{
flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
800212e: 2340 movs r3, #64 ; 0x40
8002130: 617b str r3, [r7, #20]
8002132: e001 b.n 8002138 <FSMC_NORSRAM_Init+0x34>
}
else
{
flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
8002134: 2300 movs r3, #0
8002136: 617b str r3, [r7, #20]
}
btcr_reg = (flashaccess | \
Init->DataAddressMux | \
8002138: 683b ldr r3, [r7, #0]
800213a: 685a ldr r2, [r3, #4]
btcr_reg = (flashaccess | \
800213c: 697b ldr r3, [r7, #20]
800213e: 431a orrs r2, r3
Init->MemoryType | \
8002140: 683b ldr r3, [r7, #0]
8002142: 689b ldr r3, [r3, #8]
Init->DataAddressMux | \
8002144: 431a orrs r2, r3
Init->MemoryDataWidth | \
8002146: 683b ldr r3, [r7, #0]
8002148: 68db ldr r3, [r3, #12]
Init->MemoryType | \
800214a: 431a orrs r2, r3
Init->BurstAccessMode | \
800214c: 683b ldr r3, [r7, #0]
800214e: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth | \
8002150: 431a orrs r2, r3
Init->WaitSignalPolarity | \
8002152: 683b ldr r3, [r7, #0]
8002154: 695b ldr r3, [r3, #20]
Init->BurstAccessMode | \
8002156: 431a orrs r2, r3
Init->WaitSignalActive | \
8002158: 683b ldr r3, [r7, #0]
800215a: 69db ldr r3, [r3, #28]
Init->WaitSignalPolarity | \
800215c: 431a orrs r2, r3
Init->WriteOperation | \
800215e: 683b ldr r3, [r7, #0]
8002160: 6a1b ldr r3, [r3, #32]
Init->WaitSignalActive | \
8002162: 431a orrs r2, r3
Init->WaitSignal | \
8002164: 683b ldr r3, [r7, #0]
8002166: 6a5b ldr r3, [r3, #36] ; 0x24
Init->WriteOperation | \
8002168: 431a orrs r2, r3
Init->ExtendedMode | \
800216a: 683b ldr r3, [r7, #0]
800216c: 6a9b ldr r3, [r3, #40] ; 0x28
Init->WaitSignal | \
800216e: 431a orrs r2, r3
Init->AsynchronousWait | \
8002170: 683b ldr r3, [r7, #0]
8002172: 6adb ldr r3, [r3, #44] ; 0x2c
Init->ExtendedMode | \
8002174: 431a orrs r2, r3
Init->WriteBurst);
8002176: 683b ldr r3, [r7, #0]
8002178: 6b1b ldr r3, [r3, #48] ; 0x30
btcr_reg = (flashaccess | \
800217a: 4313 orrs r3, r2
800217c: 613b str r3, [r7, #16]
btcr_reg |= Init->WrapMode;
800217e: 683b ldr r3, [r7, #0]
8002180: 699b ldr r3, [r3, #24]
8002182: 693a ldr r2, [r7, #16]
8002184: 4313 orrs r3, r2
8002186: 613b str r3, [r7, #16]
btcr_reg |= Init->PageSize;
8002188: 683b ldr r3, [r7, #0]
800218a: 6b5b ldr r3, [r3, #52] ; 0x34
800218c: 693a ldr r2, [r7, #16]
800218e: 4313 orrs r3, r2
8002190: 613b str r3, [r7, #16]
mask = (FSMC_BCRx_MBKEN |
8002192: 4b10 ldr r3, [pc, #64] ; (80021d4 <FSMC_NORSRAM_Init+0xd0>)
8002194: 60fb str r3, [r7, #12]
FSMC_BCRx_WAITEN |
FSMC_BCRx_EXTMOD |
FSMC_BCRx_ASYNCWAIT |
FSMC_BCRx_CBURSTRW);
mask |= FSMC_BCRx_WRAPMOD;
8002196: 68fb ldr r3, [r7, #12]
8002198: f443 6380 orr.w r3, r3, #1024 ; 0x400
800219c: 60fb str r3, [r7, #12]
mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
800219e: 68fb ldr r3, [r7, #12]
80021a0: f443 23e0 orr.w r3, r3, #458752 ; 0x70000
80021a4: 60fb str r3, [r7, #12]
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
80021a6: 683b ldr r3, [r7, #0]
80021a8: 681a ldr r2, [r3, #0]
80021aa: 687b ldr r3, [r7, #4]
80021ac: f853 2022 ldr.w r2, [r3, r2, lsl #2]
80021b0: 68fb ldr r3, [r7, #12]
80021b2: 43db mvns r3, r3
80021b4: ea02 0103 and.w r1, r2, r3
80021b8: 683b ldr r3, [r7, #0]
80021ba: 681a ldr r2, [r3, #0]
80021bc: 693b ldr r3, [r7, #16]
80021be: 4319 orrs r1, r3
80021c0: 687b ldr r3, [r7, #4]
80021c2: f843 1022 str.w r1, [r3, r2, lsl #2]
return HAL_OK;
80021c6: 2300 movs r3, #0
}
80021c8: 4618 mov r0, r3
80021ca: 371c adds r7, #28
80021cc: 46bd mov sp, r7
80021ce: bc80 pop {r7}
80021d0: 4770 bx lr
80021d2: bf00 nop
80021d4: 0008fb7f .word 0x0008fb7f
080021d8 <FSMC_NORSRAM_Timing_Init>:
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
80021d8: b480 push {r7}
80021da: b085 sub sp, #20
80021dc: af00 add r7, sp, #0
80021de: 60f8 str r0, [r7, #12]
80021e0: 60b9 str r1, [r7, #8]
80021e2: 607a str r2, [r7, #4]
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set FSMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
80021e4: 687b ldr r3, [r7, #4]
80021e6: 1c5a adds r2, r3, #1
80021e8: 68fb ldr r3, [r7, #12]
80021ea: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80021ee: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000
80021f2: 68bb ldr r3, [r7, #8]
80021f4: 681a ldr r2, [r3, #0]
80021f6: 68bb ldr r3, [r7, #8]
80021f8: 685b ldr r3, [r3, #4]
80021fa: 011b lsls r3, r3, #4
80021fc: 431a orrs r2, r3
80021fe: 68bb ldr r3, [r7, #8]
8002200: 689b ldr r3, [r3, #8]
8002202: 021b lsls r3, r3, #8
8002204: 431a orrs r2, r3
8002206: 68bb ldr r3, [r7, #8]
8002208: 68db ldr r3, [r3, #12]
800220a: 041b lsls r3, r3, #16
800220c: 431a orrs r2, r3
800220e: 68bb ldr r3, [r7, #8]
8002210: 691b ldr r3, [r3, #16]
8002212: 3b01 subs r3, #1
8002214: 051b lsls r3, r3, #20
8002216: 431a orrs r2, r3
8002218: 68bb ldr r3, [r7, #8]
800221a: 695b ldr r3, [r3, #20]
800221c: 3b02 subs r3, #2
800221e: 061b lsls r3, r3, #24
8002220: 431a orrs r2, r3
8002222: 68bb ldr r3, [r7, #8]
8002224: 699b ldr r3, [r3, #24]
8002226: 4313 orrs r3, r2
8002228: 687a ldr r2, [r7, #4]
800222a: 3201 adds r2, #1
800222c: 4319 orrs r1, r3
800222e: 68fb ldr r3, [r7, #12]
8002230: f843 1022 str.w r1, [r3, r2, lsl #2]
((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) |
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
(((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) |
(Timing->AccessMode)));
return HAL_OK;
8002234: 2300 movs r3, #0
}
8002236: 4618 mov r0, r3
8002238: 3714 adds r7, #20
800223a: 46bd mov sp, r7
800223c: bc80 pop {r7}
800223e: 4770 bx lr
08002240 <FSMC_NORSRAM_Extended_Timing_Init>:
* @arg FSMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
8002240: b480 push {r7}
8002242: b085 sub sp, #20
8002244: af00 add r7, sp, #0
8002246: 60f8 str r0, [r7, #12]
8002248: 60b9 str r1, [r7, #8]
800224a: 607a str r2, [r7, #4]
800224c: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
800224e: 683b ldr r3, [r7, #0]
8002250: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
8002254: d11d bne.n 8002292 <FSMC_NORSRAM_Extended_Timing_Init+0x52>
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
8002256: 68fb ldr r3, [r7, #12]
8002258: 687a ldr r2, [r7, #4]
800225a: f853 2022 ldr.w r2, [r3, r2, lsl #2]
800225e: 4b13 ldr r3, [pc, #76] ; (80022ac <FSMC_NORSRAM_Extended_Timing_Init+0x6c>)
8002260: 4013 ands r3, r2
8002262: 68ba ldr r2, [r7, #8]
8002264: 6811 ldr r1, [r2, #0]
8002266: 68ba ldr r2, [r7, #8]
8002268: 6852 ldr r2, [r2, #4]
800226a: 0112 lsls r2, r2, #4
800226c: 4311 orrs r1, r2
800226e: 68ba ldr r2, [r7, #8]
8002270: 6892 ldr r2, [r2, #8]
8002272: 0212 lsls r2, r2, #8
8002274: 4311 orrs r1, r2
8002276: 68ba ldr r2, [r7, #8]
8002278: 6992 ldr r2, [r2, #24]
800227a: 4311 orrs r1, r2
800227c: 68ba ldr r2, [r7, #8]
800227e: 68d2 ldr r2, [r2, #12]
8002280: 0412 lsls r2, r2, #16
8002282: 430a orrs r2, r1
8002284: ea43 0102 orr.w r1, r3, r2
8002288: 68fb ldr r3, [r7, #12]
800228a: 687a ldr r2, [r7, #4]
800228c: f843 1022 str.w r1, [r3, r2, lsl #2]
8002290: e005 b.n 800229e <FSMC_NORSRAM_Extended_Timing_Init+0x5e>
(((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos)));
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
}
else
{
Device->BWTR[Bank] = 0x0FFFFFFFU;
8002292: 68fb ldr r3, [r7, #12]
8002294: 687a ldr r2, [r7, #4]
8002296: f06f 4170 mvn.w r1, #4026531840 ; 0xf0000000
800229a: f843 1022 str.w r1, [r3, r2, lsl #2]
}
return HAL_OK;
800229e: 2300 movs r3, #0
}
80022a0: 4618 mov r0, r3
80022a2: 3714 adds r7, #20
80022a4: 46bd mov sp, r7
80022a6: bc80 pop {r7}
80022a8: 4770 bx lr
80022aa: bf00 nop
80022ac: cff00000 .word 0xcff00000
080022b0 <MX_FATFS_Init>:
/* USER CODE BEGIN Variables */
/* USER CODE END Variables */
void MX_FATFS_Init(void)
{
80022b0: b580 push {r7, lr}
80022b2: af00 add r7, sp, #0
/*## FatFS: Link the USER driver ###########################*/
retUSER = FATFS_LinkDriver(&USER_Driver, USERPath);
80022b4: 4904 ldr r1, [pc, #16] ; (80022c8 <MX_FATFS_Init+0x18>)
80022b6: 4805 ldr r0, [pc, #20] ; (80022cc <MX_FATFS_Init+0x1c>)
80022b8: f000 f8be bl 8002438 <FATFS_LinkDriver>
80022bc: 4603 mov r3, r0
80022be: 461a mov r2, r3
80022c0: 4b03 ldr r3, [pc, #12] ; (80022d0 <MX_FATFS_Init+0x20>)
80022c2: 701a strb r2, [r3, #0]
/* USER CODE BEGIN Init */
/* additional user code for init */
/* USER CODE END Init */
}
80022c4: bf00 nop
80022c6: bd80 pop {r7, pc}
80022c8: 200000f8 .word 0x200000f8
80022cc: 2000000c .word 0x2000000c
80022d0: 200000fc .word 0x200000fc
080022d4 <USER_initialize>:
* @retval DSTATUS: Operation status
*/
DSTATUS USER_initialize (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
80022d4: b580 push {r7, lr}
80022d6: b082 sub sp, #8
80022d8: af00 add r7, sp, #0
80022da: 4603 mov r3, r0
80022dc: 71fb strb r3, [r7, #7]
/* USER CODE BEGIN INIT */
Stat = SD_disk_initialize(pdrv);
80022de: 79fb ldrb r3, [r7, #7]
80022e0: 4618 mov r0, r3
80022e2: f000 fadb bl 800289c <SD_disk_initialize>
80022e6: 4603 mov r3, r0
80022e8: 461a mov r2, r3
80022ea: 4b04 ldr r3, [pc, #16] ; (80022fc <USER_initialize+0x28>)
80022ec: 701a strb r2, [r3, #0]
return Stat;
80022ee: 4b03 ldr r3, [pc, #12] ; (80022fc <USER_initialize+0x28>)
80022f0: 781b ldrb r3, [r3, #0]
80022f2: b2db uxtb r3, r3
/* USER CODE END INIT */
}
80022f4: 4618 mov r0, r3
80022f6: 3708 adds r7, #8
80022f8: 46bd mov sp, r7
80022fa: bd80 pop {r7, pc}
80022fc: 20000009 .word 0x20000009
08002300 <USER_status>:
* @retval DSTATUS: Operation status
*/
DSTATUS USER_status (
BYTE pdrv /* Physical drive number to identify the drive */
)
{
8002300: b580 push {r7, lr}
8002302: b082 sub sp, #8
8002304: af00 add r7, sp, #0
8002306: 4603 mov r3, r0
8002308: 71fb strb r3, [r7, #7]
/* USER CODE BEGIN STATUS */
Stat = SD_disk_status (pdrv);
800230a: 79fb ldrb r3, [r7, #7]
800230c: 4618 mov r0, r3
800230e: f000 fbaf bl 8002a70 <SD_disk_status>
8002312: 4603 mov r3, r0
8002314: 461a mov r2, r3
8002316: 4b04 ldr r3, [pc, #16] ; (8002328 <USER_status+0x28>)
8002318: 701a strb r2, [r3, #0]
return Stat;
800231a: 4b03 ldr r3, [pc, #12] ; (8002328 <USER_status+0x28>)
800231c: 781b ldrb r3, [r3, #0]
800231e: b2db uxtb r3, r3
/* USER CODE END STATUS */
}
8002320: 4618 mov r0, r3
8002322: 3708 adds r7, #8
8002324: 46bd mov sp, r7
8002326: bd80 pop {r7, pc}
8002328: 20000009 .word 0x20000009
0800232c <USER_read>:
BYTE pdrv, /* Physical drive nmuber to identify the drive */
BYTE *buff, /* Data buffer to store read data */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to read */
)
{
800232c: b580 push {r7, lr}
800232e: b084 sub sp, #16
8002330: af00 add r7, sp, #0
8002332: 60b9 str r1, [r7, #8]
8002334: 607a str r2, [r7, #4]
8002336: 603b str r3, [r7, #0]
8002338: 4603 mov r3, r0
800233a: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN READ */
return SD_disk_read (pdrv, buff, sector, count);
800233c: 7bf8 ldrb r0, [r7, #15]
800233e: 683b ldr r3, [r7, #0]
8002340: 687a ldr r2, [r7, #4]
8002342: 68b9 ldr r1, [r7, #8]
8002344: f000 fba8 bl 8002a98 <SD_disk_read>
8002348: 4603 mov r3, r0
/* USER CODE END READ */
}
800234a: 4618 mov r0, r3
800234c: 3710 adds r7, #16
800234e: 46bd mov sp, r7
8002350: bd80 pop {r7, pc}
08002352 <USER_write>:
BYTE pdrv, /* Physical drive nmuber to identify the drive */
const BYTE *buff, /* Data to be written */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to write */
)
{
8002352: b580 push {r7, lr}
8002354: b084 sub sp, #16
8002356: af00 add r7, sp, #0
8002358: 60b9 str r1, [r7, #8]
800235a: 607a str r2, [r7, #4]
800235c: 603b str r3, [r7, #0]
800235e: 4603 mov r3, r0
8002360: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN WRITE */
/* USER CODE HERE */
return SD_disk_write (pdrv, buff, sector, count);
8002362: 7bf8 ldrb r0, [r7, #15]
8002364: 683b ldr r3, [r7, #0]
8002366: 687a ldr r2, [r7, #4]
8002368: 68b9 ldr r1, [r7, #8]
800236a: f000 fbff bl 8002b6c <SD_disk_write>
800236e: 4603 mov r3, r0
/* USER CODE END WRITE */
}
8002370: 4618 mov r0, r3
8002372: 3710 adds r7, #16
8002374: 46bd mov sp, r7
8002376: bd80 pop {r7, pc}
08002378 <USER_ioctl>:
DRESULT USER_ioctl (
BYTE pdrv, /* Physical drive nmuber (0..) */
BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
8002378: b580 push {r7, lr}
800237a: b084 sub sp, #16
800237c: af00 add r7, sp, #0
800237e: 4603 mov r3, r0
8002380: 603a str r2, [r7, #0]
8002382: 71fb strb r3, [r7, #7]
8002384: 460b mov r3, r1
8002386: 71bb strb r3, [r7, #6]
/* USER CODE BEGIN IOCTL */
DRESULT res = SD_disk_ioctl (pdrv, cmd, buff);
8002388: 79b9 ldrb r1, [r7, #6]
800238a: 79fb ldrb r3, [r7, #7]
800238c: 683a ldr r2, [r7, #0]
800238e: 4618 mov r0, r3
8002390: f000 fc70 bl 8002c74 <SD_disk_ioctl>
8002394: 4603 mov r3, r0
8002396: 73fb strb r3, [r7, #15]
return res;
8002398: 7bfb ldrb r3, [r7, #15]
/* USER CODE END IOCTL */
}
800239a: 4618 mov r0, r3
800239c: 3710 adds r7, #16
800239e: 46bd mov sp, r7
80023a0: bd80 pop {r7, pc}
...
080023a4 <FATFS_LinkDriverEx>:
* @param lun : only used for USB Key Disk to add multi-lun management
else the paramter must be equal to 0
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, uint8_t lun)
{
80023a4: b480 push {r7}
80023a6: b087 sub sp, #28
80023a8: af00 add r7, sp, #0
80023aa: 60f8 str r0, [r7, #12]
80023ac: 60b9 str r1, [r7, #8]
80023ae: 4613 mov r3, r2
80023b0: 71fb strb r3, [r7, #7]
uint8_t ret = 1;
80023b2: 2301 movs r3, #1
80023b4: 75fb strb r3, [r7, #23]
uint8_t DiskNum = 0;
80023b6: 2300 movs r3, #0
80023b8: 75bb strb r3, [r7, #22]
if(disk.nbr <= _VOLUMES)
80023ba: 4b1e ldr r3, [pc, #120] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023bc: 7a5b ldrb r3, [r3, #9]
80023be: b2db uxtb r3, r3
80023c0: 2b01 cmp r3, #1
80023c2: d831 bhi.n 8002428 <FATFS_LinkDriverEx+0x84>
{
disk.is_initialized[disk.nbr] = 0;
80023c4: 4b1b ldr r3, [pc, #108] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023c6: 7a5b ldrb r3, [r3, #9]
80023c8: b2db uxtb r3, r3
80023ca: 461a mov r2, r3
80023cc: 4b19 ldr r3, [pc, #100] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023ce: 2100 movs r1, #0
80023d0: 5499 strb r1, [r3, r2]
disk.drv[disk.nbr] = drv;
80023d2: 4b18 ldr r3, [pc, #96] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023d4: 7a5b ldrb r3, [r3, #9]
80023d6: b2db uxtb r3, r3
80023d8: 4a16 ldr r2, [pc, #88] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023da: 009b lsls r3, r3, #2
80023dc: 4413 add r3, r2
80023de: 68fa ldr r2, [r7, #12]
80023e0: 605a str r2, [r3, #4]
disk.lun[disk.nbr] = lun;
80023e2: 4b14 ldr r3, [pc, #80] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023e4: 7a5b ldrb r3, [r3, #9]
80023e6: b2db uxtb r3, r3
80023e8: 461a mov r2, r3
80023ea: 4b12 ldr r3, [pc, #72] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023ec: 4413 add r3, r2
80023ee: 79fa ldrb r2, [r7, #7]
80023f0: 721a strb r2, [r3, #8]
DiskNum = disk.nbr++;
80023f2: 4b10 ldr r3, [pc, #64] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023f4: 7a5b ldrb r3, [r3, #9]
80023f6: b2db uxtb r3, r3
80023f8: 1c5a adds r2, r3, #1
80023fa: b2d1 uxtb r1, r2
80023fc: 4a0d ldr r2, [pc, #52] ; (8002434 <FATFS_LinkDriverEx+0x90>)
80023fe: 7251 strb r1, [r2, #9]
8002400: 75bb strb r3, [r7, #22]
path[0] = DiskNum + '0';
8002402: 7dbb ldrb r3, [r7, #22]
8002404: 3330 adds r3, #48 ; 0x30
8002406: b2da uxtb r2, r3
8002408: 68bb ldr r3, [r7, #8]
800240a: 701a strb r2, [r3, #0]
path[1] = ':';
800240c: 68bb ldr r3, [r7, #8]
800240e: 3301 adds r3, #1
8002410: 223a movs r2, #58 ; 0x3a
8002412: 701a strb r2, [r3, #0]
path[2] = '/';
8002414: 68bb ldr r3, [r7, #8]
8002416: 3302 adds r3, #2
8002418: 222f movs r2, #47 ; 0x2f
800241a: 701a strb r2, [r3, #0]
path[3] = 0;
800241c: 68bb ldr r3, [r7, #8]
800241e: 3303 adds r3, #3
8002420: 2200 movs r2, #0
8002422: 701a strb r2, [r3, #0]
ret = 0;
8002424: 2300 movs r3, #0
8002426: 75fb strb r3, [r7, #23]
}
return ret;
8002428: 7dfb ldrb r3, [r7, #23]
}
800242a: 4618 mov r0, r3
800242c: 371c adds r7, #28
800242e: 46bd mov sp, r7
8002430: bc80 pop {r7}
8002432: 4770 bx lr
8002434: 20000044 .word 0x20000044
08002438 <FATFS_LinkDriver>:
* @param drv: pointer to the disk IO Driver structure
* @param path: pointer to the logical drive path
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriver(Diskio_drvTypeDef *drv, char *path)
{
8002438: b580 push {r7, lr}
800243a: b082 sub sp, #8
800243c: af00 add r7, sp, #0
800243e: 6078 str r0, [r7, #4]
8002440: 6039 str r1, [r7, #0]
return FATFS_LinkDriverEx(drv, path, 0);
8002442: 2200 movs r2, #0
8002444: 6839 ldr r1, [r7, #0]
8002446: 6878 ldr r0, [r7, #4]
8002448: f7ff ffac bl 80023a4 <FATFS_LinkDriverEx>
800244c: 4603 mov r3, r0
}
800244e: 4618 mov r0, r3
8002450: 3708 adds r7, #8
8002452: 46bd mov sp, r7
8002454: bd80 pop {r7, pc}
...
08002458 <my_main>:
#include "fatfs.h"
#include "fatfs_sd.h"
FATFS SD;
int my_main()
{
8002458: b580 push {r7, lr}
800245a: f5ad 7d22 sub.w sp, sp, #648 ; 0x288
800245e: af02 add r7, sp, #8
uint8_t res;
FIL fil;
char fil_buff[64];
uint16_t br=0;
8002460: 2300 movs r3, #0
8002462: f8a7 327e strh.w r3, [r7, #638] ; 0x27e
char str[16];
LCD_BL(0);
8002466: 2200 movs r2, #0
8002468: 2101 movs r1, #1
800246a: 4812 ldr r0, [pc, #72] ; (80024b4 <my_main+0x5c>)
800246c: f7fe fc84 bl 8000d78 <HAL_GPIO_WritePin>
LCDx_Init();
8002470: f000 ffae bl 80033d0 <LCDx_Init>
if(font_init())
8002474: f001 f9a4 bl 80037c0 <font_init>
8002478: 4603 mov r3, r0
800247a: 2b00 cmp r3, #0
800247c: d00a beq.n 8002494 <my_main+0x3c>
{
LCD_ShowString(0,16,(uint8_t *)"erro",16,RED,BLUE);
800247e: 231f movs r3, #31
8002480: 9301 str r3, [sp, #4]
8002482: f44f 4378 mov.w r3, #63488 ; 0xf800
8002486: 9300 str r3, [sp, #0]
8002488: 2310 movs r3, #16
800248a: 4a0b ldr r2, [pc, #44] ; (80024b8 <my_main+0x60>)
800248c: 2110 movs r1, #16
800248e: 2000 movs r0, #0
8002490: f001 fb4a bl 8003b28 <LCD_ShowString>
}
LCD_Clear(GRAY);
8002494: f248 4030 movw r0, #33840 ; 0x8430
8002498: f001 f940 bl 800371c <LCD_Clear>
res=f_open(&fil,"0:/demo.txt",FA_READ);
res=f_read(&fil,fil_buff,16,(UINT*)&br);
sprintf(str,"%s\0\0",fil_buff);
LCD_ShowString(0,0,str,16,RED,BLUE);
*/
LCD_ShowString(0,0,"123dsjvn��",12,RED,BLUE);
800249c: 231f movs r3, #31
800249e: 9301 str r3, [sp, #4]
80024a0: f44f 4378 mov.w r3, #63488 ; 0xf800
80024a4: 9300 str r3, [sp, #0]
80024a6: 230c movs r3, #12
80024a8: 4a04 ldr r2, [pc, #16] ; (80024bc <my_main+0x64>)
80024aa: 2100 movs r1, #0
80024ac: 2000 movs r0, #0
80024ae: f001 fb3b bl 8003b28 <LCD_ShowString>
while(1)
80024b2: e7fe b.n 80024b2 <my_main+0x5a>
80024b4: 40010c00 .word 0x40010c00
80024b8: 08003c74 .word 0x08003c74
80024bc: 08003c7c .word 0x08003c7c
080024c0 <W25QXX_Read>:
//ReadAddr:��ʼ��ȡ�ĵ�ַ(24bit)
//NumByteToRead:Ҫ��ȡ���ֽ���(����65535)
void W25QXX_Read(uint8_t* pBuffer,uint32_t ReadAddr,uint16_t NumByteToRead)
{
80024c0: b580 push {r7, lr}
80024c2: b086 sub sp, #24
80024c4: af00 add r7, sp, #0
80024c6: 60f8 str r0, [r7, #12]
80024c8: 60b9 str r1, [r7, #8]
80024ca: 4613 mov r3, r2
80024cc: 80fb strh r3, [r7, #6]
unsigned char buff[4];
HAL_GPIO_WritePin(FLASH_E_GPIO_Port,FLASH_E_Pin,0);
80024ce: 2200 movs r2, #0
80024d0: f44f 5180 mov.w r1, #4096 ; 0x1000
80024d4: 4813 ldr r0, [pc, #76] ; (8002524 <W25QXX_Read+0x64>)
80024d6: f7fe fc4f bl 8000d78 <HAL_GPIO_WritePin>
buff[0]=W25X_ReadData;
80024da: 2303 movs r3, #3
80024dc: 753b strb r3, [r7, #20]
buff[1]=(uint8_t)((ReadAddr)>>16);
80024de: 68bb ldr r3, [r7, #8]
80024e0: 0c1b lsrs r3, r3, #16
80024e2: b2db uxtb r3, r3
80024e4: 757b strb r3, [r7, #21]
buff[2]=(uint8_t)((ReadAddr)>>8);
80024e6: 68bb ldr r3, [r7, #8]
80024e8: 0a1b lsrs r3, r3, #8
80024ea: b2db uxtb r3, r3
80024ec: 75bb strb r3, [r7, #22]
buff[3]=(uint8_t)ReadAddr;
80024ee: 68bb ldr r3, [r7, #8]
80024f0: b2db uxtb r3, r3
80024f2: 75fb strb r3, [r7, #23]
HAL_SPI_Transmit(&hspi2,buff,4,100); //���Ͷ�ȡ����
80024f4: f107 0114 add.w r1, r7, #20
80024f8: 2364 movs r3, #100 ; 0x64
80024fa: 2204 movs r2, #4
80024fc: 480a ldr r0, [pc, #40] ; (8002528 <W25QXX_Read+0x68>)
80024fe: f7ff f8bf bl 8001680 <HAL_SPI_Transmit>
HAL_SPI_Receive(&hspi2,pBuffer,NumByteToRead,100);
8002502: 88fa ldrh r2, [r7, #6]
8002504: 2364 movs r3, #100 ; 0x64
8002506: 68f9 ldr r1, [r7, #12]
8002508: 4807 ldr r0, [pc, #28] ; (8002528 <W25QXX_Read+0x68>)
800250a: f7ff f9f5 bl 80018f8 <HAL_SPI_Receive>
HAL_GPIO_WritePin(FLASH_E_GPIO_Port,FLASH_E_Pin,1);
800250e: 2201 movs r2, #1
8002510: f44f 5180 mov.w r1, #4096 ; 0x1000
8002514: 4803 ldr r0, [pc, #12] ; (8002524 <W25QXX_Read+0x64>)
8002516: f7fe fc2f bl 8000d78 <HAL_GPIO_WritePin>
}
800251a: bf00 nop
800251c: 3718 adds r7, #24
800251e: 46bd mov sp, r7
8002520: bd80 pop {r7, pc}
8002522: bf00 nop
8002524: 40010c00 .word 0x40010c00
8002528: 20000054 .word 0x20000054
0800252c <SELECT>:
Timer2--;
}
/* SPI Chip Select */
static void SELECT(void)
{
800252c: b580 push {r7, lr}
800252e: af00 add r7, sp, #0
HAL_GPIO_WritePin(SD_CS_GPIO_Port, SD_CS_Pin, GPIO_PIN_RESET);
8002530: 2200 movs r2, #0
8002532: 2104 movs r1, #4
8002534: 4802 ldr r0, [pc, #8] ; (8002540 <SELECT+0x14>)
8002536: f7fe fc1f bl 8000d78 <HAL_GPIO_WritePin>
}
800253a: bf00 nop
800253c: bd80 pop {r7, pc}
800253e: bf00 nop
8002540: 40011400 .word 0x40011400
08002544 <DESELECT>:
/* SPI Chip Deselect */
static void DESELECT(void)
{
8002544: b580 push {r7, lr}
8002546: af00 add r7, sp, #0
HAL_GPIO_WritePin(SD_CS_GPIO_Port, SD_CS_Pin, GPIO_PIN_SET);
8002548: 2201 movs r2, #1
800254a: 2104 movs r1, #4
800254c: 4802 ldr r0, [pc, #8] ; (8002558 <DESELECT+0x14>)
800254e: f7fe fc13 bl 8000d78 <HAL_GPIO_WritePin>
}
8002552: bf00 nop
8002554: bd80 pop {r7, pc}
8002556: bf00 nop
8002558: 40011400 .word 0x40011400
0800255c <SPI_TxByte>:
static void SPI_TxByte(BYTE data)
{
800255c: b580 push {r7, lr}
800255e: b082 sub sp, #8
8002560: af00 add r7, sp, #0
8002562: 4603 mov r3, r0
8002564: 71fb strb r3, [r7, #7]
while (HAL_SPI_GetState(&hspi2) != HAL_SPI_STATE_READY);
8002566: bf00 nop
8002568: 4808 ldr r0, [pc, #32] ; (800258c <SPI_TxByte+0x30>)
800256a: f7ff fc78 bl 8001e5e <HAL_SPI_GetState>
800256e: 4603 mov r3, r0
8002570: 2b01 cmp r3, #1
8002572: d1f9 bne.n 8002568 <SPI_TxByte+0xc>
HAL_SPI_Transmit(&hspi2, &data, 1, SPI_TIMEOUT);
8002574: 1df9 adds r1, r7, #7
8002576: f44f 737a mov.w r3, #1000 ; 0x3e8
800257a: 2201 movs r2, #1
800257c: 4803 ldr r0, [pc, #12] ; (800258c <SPI_TxByte+0x30>)
800257e: f7ff f87f bl 8001680 <HAL_SPI_Transmit>
}
8002582: bf00 nop
8002584: 3708 adds r7, #8
8002586: 46bd mov sp, r7
8002588: bd80 pop {r7, pc}
800258a: bf00 nop
800258c: 20000054 .word 0x20000054
08002590 <SPI_RxByte>:
static uint8_t SPI_RxByte(void)
{
8002590: b580 push {r7, lr}
8002592: b084 sub sp, #16
8002594: af02 add r7, sp, #8
uint8_t dummy, data;
dummy = 0xFF;
8002596: 23ff movs r3, #255 ; 0xff
8002598: 71fb strb r3, [r7, #7]
data = 0;
800259a: 2300 movs r3, #0
800259c: 71bb strb r3, [r7, #6]
while ((HAL_SPI_GetState(&hspi2) != HAL_SPI_STATE_READY));
800259e: bf00 nop
80025a0: 4809 ldr r0, [pc, #36] ; (80025c8 <SPI_RxByte+0x38>)
80025a2: f7ff fc5c bl 8001e5e <HAL_SPI_GetState>
80025a6: 4603 mov r3, r0
80025a8: 2b01 cmp r3, #1
80025aa: d1f9 bne.n 80025a0 <SPI_RxByte+0x10>
HAL_SPI_TransmitReceive(&hspi2, &dummy, &data, 1, SPI_TIMEOUT);
80025ac: 1dba adds r2, r7, #6
80025ae: 1df9 adds r1, r7, #7
80025b0: f44f 737a mov.w r3, #1000 ; 0x3e8
80025b4: 9300 str r3, [sp, #0]
80025b6: 2301 movs r3, #1
80025b8: 4803 ldr r0, [pc, #12] ; (80025c8 <SPI_RxByte+0x38>)
80025ba: f7ff faae bl 8001b1a <HAL_SPI_TransmitReceive>
return data;
80025be: 79bb ldrb r3, [r7, #6]
}
80025c0: 4618 mov r0, r3
80025c2: 3708 adds r7, #8
80025c4: 46bd mov sp, r7
80025c6: bd80 pop {r7, pc}
80025c8: 20000054 .word 0x20000054
080025cc <SPI_RxBytePtr>:
static void SPI_RxBytePtr(uint8_t *buff)
{
80025cc: b580 push {r7, lr}
80025ce: b082 sub sp, #8
80025d0: af00 add r7, sp, #0
80025d2: 6078 str r0, [r7, #4]
*buff = SPI_RxByte();
80025d4: f7ff ffdc bl 8002590 <SPI_RxByte>
80025d8: 4603 mov r3, r0
80025da: 461a mov r2, r3
80025dc: 687b ldr r3, [r7, #4]
80025de: 701a strb r2, [r3, #0]
}
80025e0: bf00 nop
80025e2: 3708 adds r7, #8
80025e4: 46bd mov sp, r7
80025e6: bd80 pop {r7, pc}
080025e8 <SD_ReadyWait>:
static uint8_t SD_ReadyWait(void)
{
80025e8: b580 push {r7, lr}
80025ea: b082 sub sp, #8
80025ec: af00 add r7, sp, #0
uint8_t res;
Timer2 = 50;
80025ee: 4b0b ldr r3, [pc, #44] ; (800261c <SD_ReadyWait+0x34>)
80025f0: 2232 movs r2, #50 ; 0x32
80025f2: 701a strb r2, [r3, #0]
SPI_RxByte();
80025f4: f7ff ffcc bl 8002590 <SPI_RxByte>
do
{
res = SPI_RxByte();
80025f8: f7ff ffca bl 8002590 <SPI_RxByte>
80025fc: 4603 mov r3, r0
80025fe: 71fb strb r3, [r7, #7]
} while ((res != 0xFF) && Timer2);
8002600: 79fb ldrb r3, [r7, #7]
8002602: 2bff cmp r3, #255 ; 0xff
8002604: d004 beq.n 8002610 <SD_ReadyWait+0x28>
8002606: 4b05 ldr r3, [pc, #20] ; (800261c <SD_ReadyWait+0x34>)
8002608: 781b ldrb r3, [r3, #0]
800260a: b2db uxtb r3, r3
800260c: 2b00 cmp r3, #0
800260e: d1f3 bne.n 80025f8 <SD_ReadyWait+0x10>
return res;
8002610: 79fb ldrb r3, [r7, #7]
}
8002612: 4618 mov r0, r3
8002614: 3708 adds r7, #8
8002616: 46bd mov sp, r7
8002618: bd80 pop {r7, pc}
800261a: bf00 nop
800261c: 2000055c .word 0x2000055c
08002620 <SD_PowerOn>:
static void SD_PowerOn(void)
{
8002620: b580 push {r7, lr}
8002622: b086 sub sp, #24
8002624: af00 add r7, sp, #0
uint8_t cmd_arg[6];
uint32_t Count = 0x1FFF;
8002626: f641 73ff movw r3, #8191 ; 0x1fff
800262a: 617b str r3, [r7, #20]
DESELECT();
800262c: f7ff ff8a bl 8002544 <DESELECT>
for(int i = 0; i < 10; i++)
8002630: 2300 movs r3, #0
8002632: 613b str r3, [r7, #16]
8002634: e005 b.n 8002642 <SD_PowerOn+0x22>
{
SPI_TxByte(0xFF);
8002636: 20ff movs r0, #255 ; 0xff
8002638: f7ff ff90 bl 800255c <SPI_TxByte>
for(int i = 0; i < 10; i++)
800263c: 693b ldr r3, [r7, #16]
800263e: 3301 adds r3, #1
8002640: 613b str r3, [r7, #16]
8002642: 693b ldr r3, [r7, #16]
8002644: 2b09 cmp r3, #9
8002646: ddf6 ble.n 8002636 <SD_PowerOn+0x16>
}
/* SPI Chips Select */
SELECT();
8002648: f7ff ff70 bl 800252c <SELECT>
cmd_arg[0] = (CMD0 | 0x40);
800264c: 2340 movs r3, #64 ; 0x40
800264e: 713b strb r3, [r7, #4]
cmd_arg[1] = 0;
8002650: 2300 movs r3, #0
8002652: 717b strb r3, [r7, #5]
cmd_arg[2] = 0;
8002654: 2300 movs r3, #0
8002656: 71bb strb r3, [r7, #6]
cmd_arg[3] = 0;
8002658: 2300 movs r3, #0
800265a: 71fb strb r3, [r7, #7]
cmd_arg[4] = 0;
800265c: 2300 movs r3, #0
800265e: 723b strb r3, [r7, #8]
cmd_arg[5] = 0x95;
8002660: 2395 movs r3, #149 ; 0x95
8002662: 727b strb r3, [r7, #9]
for (int i = 0; i < 6; i++)
8002664: 2300 movs r3, #0
8002666: 60fb str r3, [r7, #12]
8002668: e009 b.n 800267e <SD_PowerOn+0x5e>
{
SPI_TxByte(cmd_arg[i]);
800266a: 1d3a adds r2, r7, #4
800266c: 68fb ldr r3, [r7, #12]
800266e: 4413 add r3, r2
8002670: 781b ldrb r3, [r3, #0]
8002672: 4618 mov r0, r3
8002674: f7ff ff72 bl 800255c <SPI_TxByte>
for (int i = 0; i < 6; i++)
8002678: 68fb ldr r3, [r7, #12]
800267a: 3301 adds r3, #1
800267c: 60fb str r3, [r7, #12]
800267e: 68fb ldr r3, [r7, #12]
8002680: 2b05 cmp r3, #5
8002682: ddf2 ble.n 800266a <SD_PowerOn+0x4a>
}
while ((SPI_RxByte() != 0x01) && Count)
8002684: e002 b.n 800268c <SD_PowerOn+0x6c>
{
Count--;
8002686: 697b ldr r3, [r7, #20]
8002688: 3b01 subs r3, #1
800268a: 617b str r3, [r7, #20]
while ((SPI_RxByte() != 0x01) && Count)
800268c: f7ff ff80 bl 8002590 <SPI_RxByte>
8002690: 4603 mov r3, r0
8002692: 2b01 cmp r3, #1
8002694: d002 beq.n 800269c <SD_PowerOn+0x7c>
8002696: 697b ldr r3, [r7, #20]
8002698: 2b00 cmp r3, #0
800269a: d1f4 bne.n 8002686 <SD_PowerOn+0x66>
}
DESELECT();
800269c: f7ff ff52 bl 8002544 <DESELECT>
SPI_TxByte(0XFF);
80026a0: 20ff movs r0, #255 ; 0xff
80026a2: f7ff ff5b bl 800255c <SPI_TxByte>
PowerFlag = 1;
80026a6: 4b03 ldr r3, [pc, #12] ; (80026b4 <SD_PowerOn+0x94>)
80026a8: 2201 movs r2, #1
80026aa: 701a strb r2, [r3, #0]
}
80026ac: bf00 nop
80026ae: 3718 adds r7, #24
80026b0: 46bd mov sp, r7
80026b2: bd80 pop {r7, pc}
80026b4: 20000051 .word 0x20000051
080026b8 <SD_PowerOff>:
static void SD_PowerOff(void)
{
80026b8: b480 push {r7}
80026ba: af00 add r7, sp, #0
PowerFlag = 0;
80026bc: 4b03 ldr r3, [pc, #12] ; (80026cc <SD_PowerOff+0x14>)
80026be: 2200 movs r2, #0
80026c0: 701a strb r2, [r3, #0]
}
80026c2: bf00 nop
80026c4: 46bd mov sp, r7
80026c6: bc80 pop {r7}
80026c8: 4770 bx lr
80026ca: bf00 nop
80026cc: 20000051 .word 0x20000051
080026d0 <SD_CheckPower>:
static uint8_t SD_CheckPower(void)
{
80026d0: b480 push {r7}
80026d2: af00 add r7, sp, #0
/* 0=off, 1=on */
return PowerFlag;
80026d4: 4b02 ldr r3, [pc, #8] ; (80026e0 <SD_CheckPower+0x10>)
80026d6: 781b ldrb r3, [r3, #0]
}
80026d8: 4618 mov r0, r3
80026da: 46bd mov sp, r7
80026dc: bc80 pop {r7}
80026de: 4770 bx lr
80026e0: 20000051 .word 0x20000051
080026e4 <SD_RxDataBlock>:
static bool SD_RxDataBlock(BYTE *buff, UINT btr)
{
80026e4: b580 push {r7, lr}
80026e6: b084 sub sp, #16
80026e8: af00 add r7, sp, #0
80026ea: 6078 str r0, [r7, #4]
80026ec: 6039 str r1, [r7, #0]
uint8_t token;
Timer1 = 10;
80026ee: 4b17 ldr r3, [pc, #92] ; (800274c <SD_RxDataBlock+0x68>)
80026f0: 220a movs r2, #10
80026f2: 701a strb r2, [r3, #0]
do
{
token = SPI_RxByte();
80026f4: f7ff ff4c bl 8002590 <SPI_RxByte>
80026f8: 4603 mov r3, r0
80026fa: 73fb strb r3, [r7, #15]
} while((token == 0xFF) && Timer1);
80026fc: 7bfb ldrb r3, [r7, #15]
80026fe: 2bff cmp r3, #255 ; 0xff
8002700: d104 bne.n 800270c <SD_RxDataBlock+0x28>
8002702: 4b12 ldr r3, [pc, #72] ; (800274c <SD_RxDataBlock+0x68>)
8002704: 781b ldrb r3, [r3, #0]
8002706: b2db uxtb r3, r3
8002708: 2b00 cmp r3, #0
800270a: d1f3 bne.n 80026f4 <SD_RxDataBlock+0x10>
if(token != 0xFE)
800270c: 7bfb ldrb r3, [r7, #15]
800270e: 2bfe cmp r3, #254 ; 0xfe
8002710: d001 beq.n 8002716 <SD_RxDataBlock+0x32>
return FALSE;
8002712: 2300 movs r3, #0
8002714: e016 b.n 8002744 <SD_RxDataBlock+0x60>
do
{
SPI_RxBytePtr(buff++);
8002716: 687b ldr r3, [r7, #4]
8002718: 1c5a adds r2, r3, #1
800271a: 607a str r2, [r7, #4]
800271c: 4618 mov r0, r3
800271e: f7ff ff55 bl 80025cc <SPI_RxBytePtr>
SPI_RxBytePtr(buff++);
8002722: 687b ldr r3, [r7, #4]
8002724: 1c5a adds r2, r3, #1
8002726: 607a str r2, [r7, #4]
8002728: 4618 mov r0, r3
800272a: f7ff ff4f bl 80025cc <SPI_RxBytePtr>
} while(btr -= 2);
800272e: 683b ldr r3, [r7, #0]
8002730: 3b02 subs r3, #2
8002732: 603b str r3, [r7, #0]
8002734: 683b ldr r3, [r7, #0]
8002736: 2b00 cmp r3, #0
8002738: d1ed bne.n 8002716 <SD_RxDataBlock+0x32>
SPI_RxByte();
800273a: f7ff ff29 bl 8002590 <SPI_RxByte>
SPI_RxByte();
800273e: f7ff ff27 bl 8002590 <SPI_RxByte>
return TRUE;
8002742: 2301 movs r3, #1
}
8002744: 4618 mov r0, r3
8002746: 3710 adds r7, #16
8002748: 46bd mov sp, r7
800274a: bd80 pop {r7, pc}
800274c: 2000055d .word 0x2000055d
08002750 <SD_TxDataBlock>:
#if _READONLY == 0
static bool SD_TxDataBlock(const BYTE *buff, BYTE token)
{
8002750: b580 push {r7, lr}
8002752: b084 sub sp, #16
8002754: af00 add r7, sp, #0
8002756: 6078 str r0, [r7, #4]
8002758: 460b mov r3, r1
800275a: 70fb strb r3, [r7, #3]
uint8_t resp, wc;
uint8_t i = 0;
800275c: 2300 movs r3, #0
800275e: 737b strb r3, [r7, #13]
if (SD_ReadyWait() != 0xFF)
8002760: f7ff ff42 bl 80025e8 <SD_ReadyWait>
8002764: 4603 mov r3, r0
8002766: 2bff cmp r3, #255 ; 0xff
8002768: d001 beq.n 800276e <SD_TxDataBlock+0x1e>
return FALSE;
800276a: 2300 movs r3, #0
800276c: e040 b.n 80027f0 <SD_TxDataBlock+0xa0>
SPI_TxByte(token);
800276e: 78fb ldrb r3, [r7, #3]
8002770: 4618 mov r0, r3
8002772: f7ff fef3 bl 800255c <SPI_TxByte>
if (token != 0xFD)
8002776: 78fb ldrb r3, [r7, #3]
8002778: 2bfd cmp r3, #253 ; 0xfd
800277a: d031 beq.n 80027e0 <SD_TxDataBlock+0x90>
{
wc = 0;
800277c: 2300 movs r3, #0
800277e: 73bb strb r3, [r7, #14]
do
{
SPI_TxByte(*buff++);
8002780: 687b ldr r3, [r7, #4]
8002782: 1c5a adds r2, r3, #1
8002784: 607a str r2, [r7, #4]
8002786: 781b ldrb r3, [r3, #0]
8002788: 4618 mov r0, r3
800278a: f7ff fee7 bl 800255c <SPI_TxByte>
SPI_TxByte(*buff++);
800278e: 687b ldr r3, [r7, #4]
8002790: 1c5a adds r2, r3, #1
8002792: 607a str r2, [r7, #4]
8002794: 781b ldrb r3, [r3, #0]
8002796: 4618 mov r0, r3
8002798: f7ff fee0 bl 800255c <SPI_TxByte>
} while (--wc);
800279c: 7bbb ldrb r3, [r7, #14]
800279e: 3b01 subs r3, #1
80027a0: 73bb strb r3, [r7, #14]
80027a2: 7bbb ldrb r3, [r7, #14]
80027a4: 2b00 cmp r3, #0
80027a6: d1eb bne.n 8002780 <SD_TxDataBlock+0x30>
SPI_RxByte();
80027a8: f7ff fef2 bl 8002590 <SPI_RxByte>
SPI_RxByte();
80027ac: f7ff fef0 bl 8002590 <SPI_RxByte>
while (i <= 64)
80027b0: e00b b.n 80027ca <SD_TxDataBlock+0x7a>
{
resp = SPI_RxByte();
80027b2: f7ff feed bl 8002590 <SPI_RxByte>
80027b6: 4603 mov r3, r0
80027b8: 73fb strb r3, [r7, #15]
if ((resp & 0x1F) == 0x05)
80027ba: 7bfb ldrb r3, [r7, #15]
80027bc: f003 031f and.w r3, r3, #31
80027c0: 2b05 cmp r3, #5
80027c2: d006 beq.n 80027d2 <SD_TxDataBlock+0x82>
break;
i++;
80027c4: 7b7b ldrb r3, [r7, #13]
80027c6: 3301 adds r3, #1
80027c8: 737b strb r3, [r7, #13]
while (i <= 64)
80027ca: 7b7b ldrb r3, [r7, #13]
80027cc: 2b40 cmp r3, #64 ; 0x40
80027ce: d9f0 bls.n 80027b2 <SD_TxDataBlock+0x62>
80027d0: e000 b.n 80027d4 <SD_TxDataBlock+0x84>
break;
80027d2: bf00 nop
}
while (SPI_RxByte() == 0);
80027d4: bf00 nop
80027d6: f7ff fedb bl 8002590 <SPI_RxByte>
80027da: 4603 mov r3, r0
80027dc: 2b00 cmp r3, #0
80027de: d0fa beq.n 80027d6 <SD_TxDataBlock+0x86>
}
if ((resp & 0x1F) == 0x05)
80027e0: 7bfb ldrb r3, [r7, #15]
80027e2: f003 031f and.w r3, r3, #31
80027e6: 2b05 cmp r3, #5
80027e8: d101 bne.n 80027ee <SD_TxDataBlock+0x9e>
return TRUE;
80027ea: 2301 movs r3, #1
80027ec: e000 b.n 80027f0 <SD_TxDataBlock+0xa0>
else
return FALSE;
80027ee: 2300 movs r3, #0
}
80027f0: 4618 mov r0, r3
80027f2: 3710 adds r7, #16
80027f4: 46bd mov sp, r7
80027f6: bd80 pop {r7, pc}
080027f8 <SD_SendCmd>:
#endif /* _READONLY */
static BYTE SD_SendCmd(BYTE cmd, DWORD arg)
{
80027f8: b580 push {r7, lr}
80027fa: b084 sub sp, #16
80027fc: af00 add r7, sp, #0
80027fe: 4603 mov r3, r0
8002800: 6039 str r1, [r7, #0]
8002802: 71fb strb r3, [r7, #7]
uint8_t crc, res;
if (SD_ReadyWait() != 0xFF)
8002804: f7ff fef0 bl 80025e8 <SD_ReadyWait>
8002808: 4603 mov r3, r0
800280a: 2bff cmp r3, #255 ; 0xff
800280c: d001 beq.n 8002812 <SD_SendCmd+0x1a>
return 0xFF;
800280e: 23ff movs r3, #255 ; 0xff
8002810: e040 b.n 8002894 <SD_SendCmd+0x9c>
SPI_TxByte(cmd); /* Command */
8002812: 79fb ldrb r3, [r7, #7]
8002814: 4618 mov r0, r3
8002816: f7ff fea1 bl 800255c <SPI_TxByte>
SPI_TxByte((BYTE) (arg >> 24)); /* Argument[31..24] */
800281a: 683b ldr r3, [r7, #0]
800281c: 0e1b lsrs r3, r3, #24
800281e: b2db uxtb r3, r3
8002820: 4618 mov r0, r3
8002822: f7ff fe9b bl 800255c <SPI_TxByte>
SPI_TxByte((BYTE) (arg >> 16)); /* Argument[23..16] */
8002826: 683b ldr r3, [r7, #0]
8002828: 0c1b lsrs r3, r3, #16
800282a: b2db uxtb r3, r3
800282c: 4618 mov r0, r3
800282e: f7ff fe95 bl 800255c <SPI_TxByte>
SPI_TxByte((BYTE) (arg >> 8)); /* Argument[15..8] */
8002832: 683b ldr r3, [r7, #0]
8002834: 0a1b lsrs r3, r3, #8
8002836: b2db uxtb r3, r3
8002838: 4618 mov r0, r3
800283a: f7ff fe8f bl 800255c <SPI_TxByte>
SPI_TxByte((BYTE) arg); /* Argument[7..0] */
800283e: 683b ldr r3, [r7, #0]
8002840: b2db uxtb r3, r3
8002842: 4618 mov r0, r3
8002844: f7ff fe8a bl 800255c <SPI_TxByte>
crc = 0;
8002848: 2300 movs r3, #0
800284a: 73fb strb r3, [r7, #15]
if (cmd == CMD0)
800284c: 79fb ldrb r3, [r7, #7]
800284e: 2b40 cmp r3, #64 ; 0x40
8002850: d101 bne.n 8002856 <SD_SendCmd+0x5e>
crc = 0x95; /* CRC for CMD0(0) */
8002852: 2395 movs r3, #149 ; 0x95
8002854: 73fb strb r3, [r7, #15]
if (cmd == CMD8)
8002856: 79fb ldrb r3, [r7, #7]
8002858: 2b48 cmp r3, #72 ; 0x48
800285a: d101 bne.n 8002860 <SD_SendCmd+0x68>
crc = 0x87; /* CRC for CMD8(0x1AA) */
800285c: 2387 movs r3, #135 ; 0x87
800285e: 73fb strb r3, [r7, #15]
SPI_TxByte(crc);
8002860: 7bfb ldrb r3, [r7, #15]
8002862: 4618 mov r0, r3
8002864: f7ff fe7a bl 800255c <SPI_TxByte>
if (cmd == CMD12)
8002868: 79fb ldrb r3, [r7, #7]
800286a: 2b4c cmp r3, #76 ; 0x4c
800286c: d101 bne.n 8002872 <SD_SendCmd+0x7a>
SPI_RxByte();
800286e: f7ff fe8f bl 8002590 <SPI_RxByte>
uint8_t n = 10;
8002872: 230a movs r3, #10
8002874: 73bb strb r3, [r7, #14]
do
{
res = SPI_RxByte();
8002876: f7ff fe8b bl 8002590 <SPI_RxByte>
800287a: 4603 mov r3, r0
800287c: 737b strb r3, [r7, #13]
} while ((res & 0x80) && --n);
800287e: f997 300d ldrsb.w r3, [r7, #13]
8002882: 2b00 cmp r3, #0
8002884: da05 bge.n 8002892 <SD_SendCmd+0x9a>
8002886: 7bbb ldrb r3, [r7, #14]
8002888: 3b01 subs r3, #1
800288a: 73bb strb r3, [r7, #14]
800288c: 7bbb ldrb r3, [r7, #14]
800288e: 2b00 cmp r3, #0
8002890: d1f1 bne.n 8002876 <SD_SendCmd+0x7e>
return res;
8002892: 7b7b ldrb r3, [r7, #13]
}
8002894: 4618 mov r0, r3
8002896: 3710 adds r7, #16
8002898: 46bd mov sp, r7
800289a: bd80 pop {r7, pc}
0800289c <SD_disk_initialize>:
-----------------------------------------------------------------------*/
DSTATUS SD_disk_initialize(BYTE drv)
{
800289c: b590 push {r4, r7, lr}
800289e: b085 sub sp, #20
80028a0: af00 add r7, sp, #0
80028a2: 4603 mov r3, r0
80028a4: 71fb strb r3, [r7, #7]
uint8_t n, type, ocr[4];
if(drv)
80028a6: 79fb ldrb r3, [r7, #7]
80028a8: 2b00 cmp r3, #0
80028aa: d001 beq.n 80028b0 <SD_disk_initialize+0x14>
return STA_NOINIT;
80028ac: 2301 movs r3, #1
80028ae: e0d5 b.n 8002a5c <SD_disk_initialize+0x1c0>
if(Stat & STA_NODISK)
80028b0: 4b6c ldr r3, [pc, #432] ; (8002a64 <SD_disk_initialize+0x1c8>)
80028b2: 781b ldrb r3, [r3, #0]
80028b4: b2db uxtb r3, r3
80028b6: f003 0302 and.w r3, r3, #2
80028ba: 2b00 cmp r3, #0
80028bc: d003 beq.n 80028c6 <SD_disk_initialize+0x2a>
return Stat;
80028be: 4b69 ldr r3, [pc, #420] ; (8002a64 <SD_disk_initialize+0x1c8>)
80028c0: 781b ldrb r3, [r3, #0]
80028c2: b2db uxtb r3, r3
80028c4: e0ca b.n 8002a5c <SD_disk_initialize+0x1c0>
SD_PowerOn();
80028c6: f7ff feab bl 8002620 <SD_PowerOn>
SELECT();
80028ca: f7ff fe2f bl 800252c <SELECT>
type = 0;
80028ce: 2300 movs r3, #0
80028d0: 73bb strb r3, [r7, #14]
if (SD_SendCmd(CMD0, 0) == 1)
80028d2: 2100 movs r1, #0
80028d4: 2040 movs r0, #64 ; 0x40
80028d6: f7ff ff8f bl 80027f8 <SD_SendCmd>
80028da: 4603 mov r3, r0
80028dc: 2b01 cmp r3, #1
80028de: f040 80a5 bne.w 8002a2c <SD_disk_initialize+0x190>
{
Timer1 = 100;
80028e2: 4b61 ldr r3, [pc, #388] ; (8002a68 <SD_disk_initialize+0x1cc>)
80028e4: 2264 movs r2, #100 ; 0x64
80028e6: 701a strb r2, [r3, #0]
if (SD_SendCmd(CMD8, 0x1AA) == 1)
80028e8: f44f 71d5 mov.w r1, #426 ; 0x1aa
80028ec: 2048 movs r0, #72 ; 0x48
80028ee: f7ff ff83 bl 80027f8 <SD_SendCmd>
80028f2: 4603 mov r3, r0
80028f4: 2b01 cmp r3, #1
80028f6: d158 bne.n 80029aa <SD_disk_initialize+0x10e>
{
/* SDC Ver2+ */
for (n = 0; n < 4; n++)
80028f8: 2300 movs r3, #0
80028fa: 73fb strb r3, [r7, #15]
80028fc: e00c b.n 8002918 <SD_disk_initialize+0x7c>
{
ocr[n] = SPI_RxByte();
80028fe: 7bfc ldrb r4, [r7, #15]
8002900: f7ff fe46 bl 8002590 <SPI_RxByte>
8002904: 4603 mov r3, r0
8002906: 461a mov r2, r3
8002908: f107 0310 add.w r3, r7, #16
800290c: 4423 add r3, r4
800290e: f803 2c08 strb.w r2, [r3, #-8]
for (n = 0; n < 4; n++)
8002912: 7bfb ldrb r3, [r7, #15]
8002914: 3301 adds r3, #1
8002916: 73fb strb r3, [r7, #15]
8002918: 7bfb ldrb r3, [r7, #15]
800291a: 2b03 cmp r3, #3
800291c: d9ef bls.n 80028fe <SD_disk_initialize+0x62>
}
if (ocr[2] == 0x01 && ocr[3] == 0xAA)
800291e: 7abb ldrb r3, [r7, #10]
8002920: 2b01 cmp r3, #1
8002922: f040 8083 bne.w 8002a2c <SD_disk_initialize+0x190>
8002926: 7afb ldrb r3, [r7, #11]
8002928: 2baa cmp r3, #170 ; 0xaa
800292a: d17f bne.n 8002a2c <SD_disk_initialize+0x190>
{
do {
if (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 1UL << 30) == 0)
800292c: 2100 movs r1, #0
800292e: 2077 movs r0, #119 ; 0x77
8002930: f7ff ff62 bl 80027f8 <SD_SendCmd>
8002934: 4603 mov r3, r0
8002936: 2b01 cmp r3, #1
8002938: d807 bhi.n 800294a <SD_disk_initialize+0xae>
800293a: f04f 4180 mov.w r1, #1073741824 ; 0x40000000
800293e: 2069 movs r0, #105 ; 0x69
8002940: f7ff ff5a bl 80027f8 <SD_SendCmd>
8002944: 4603 mov r3, r0
8002946: 2b00 cmp r3, #0
8002948: d005 beq.n 8002956 <SD_disk_initialize+0xba>
break; /* ACMD41 with HCS bit */
} while (Timer1);
800294a: 4b47 ldr r3, [pc, #284] ; (8002a68 <SD_disk_initialize+0x1cc>)
800294c: 781b ldrb r3, [r3, #0]
800294e: b2db uxtb r3, r3
8002950: 2b00 cmp r3, #0
8002952: d1eb bne.n 800292c <SD_disk_initialize+0x90>
8002954: e000 b.n 8002958 <SD_disk_initialize+0xbc>
break; /* ACMD41 with HCS bit */
8002956: bf00 nop
if (Timer1 && SD_SendCmd(CMD58, 0) == 0)
8002958: 4b43 ldr r3, [pc, #268] ; (8002a68 <SD_disk_initialize+0x1cc>)
800295a: 781b ldrb r3, [r3, #0]
800295c: b2db uxtb r3, r3
800295e: 2b00 cmp r3, #0
8002960: d064 beq.n 8002a2c <SD_disk_initialize+0x190>
8002962: 2100 movs r1, #0
8002964: 207a movs r0, #122 ; 0x7a
8002966: f7ff ff47 bl 80027f8 <SD_SendCmd>
800296a: 4603 mov r3, r0
800296c: 2b00 cmp r3, #0
800296e: d15d bne.n 8002a2c <SD_disk_initialize+0x190>
{
/* Check CCS bit */
for (n = 0; n < 4; n++)
8002970: 2300 movs r3, #0
8002972: 73fb strb r3, [r7, #15]
8002974: e00c b.n 8002990 <SD_disk_initialize+0xf4>
{
ocr[n] = SPI_RxByte();
8002976: 7bfc ldrb r4, [r7, #15]
8002978: f7ff fe0a bl 8002590 <SPI_RxByte>
800297c: 4603 mov r3, r0
800297e: 461a mov r2, r3
8002980: f107 0310 add.w r3, r7, #16
8002984: 4423 add r3, r4
8002986: f803 2c08 strb.w r2, [r3, #-8]
for (n = 0; n < 4; n++)
800298a: 7bfb ldrb r3, [r7, #15]
800298c: 3301 adds r3, #1
800298e: 73fb strb r3, [r7, #15]
8002990: 7bfb ldrb r3, [r7, #15]
8002992: 2b03 cmp r3, #3
8002994: d9ef bls.n 8002976 <SD_disk_initialize+0xda>
}
type = (ocr[0] & 0x40) ? 6 : 2;
8002996: 7a3b ldrb r3, [r7, #8]
8002998: f003 0340 and.w r3, r3, #64 ; 0x40
800299c: 2b00 cmp r3, #0
800299e: d001 beq.n 80029a4 <SD_disk_initialize+0x108>
80029a0: 2306 movs r3, #6
80029a2: e000 b.n 80029a6 <SD_disk_initialize+0x10a>
80029a4: 2302 movs r3, #2
80029a6: 73bb strb r3, [r7, #14]
80029a8: e040 b.n 8002a2c <SD_disk_initialize+0x190>
}
}
else
{
/* SDC Ver1 or MMC */
type = (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 0) <= 1) ? 2 : 1; /* SDC : MMC */
80029aa: 2100 movs r1, #0
80029ac: 2077 movs r0, #119 ; 0x77
80029ae: f7ff ff23 bl 80027f8 <SD_SendCmd>
80029b2: 4603 mov r3, r0
80029b4: 2b01 cmp r3, #1
80029b6: d808 bhi.n 80029ca <SD_disk_initialize+0x12e>
80029b8: 2100 movs r1, #0
80029ba: 2069 movs r0, #105 ; 0x69
80029bc: f7ff ff1c bl 80027f8 <SD_SendCmd>
80029c0: 4603 mov r3, r0
80029c2: 2b01 cmp r3, #1
80029c4: d801 bhi.n 80029ca <SD_disk_initialize+0x12e>
80029c6: 2302 movs r3, #2
80029c8: e000 b.n 80029cc <SD_disk_initialize+0x130>
80029ca: 2301 movs r3, #1
80029cc: 73bb strb r3, [r7, #14]
do {
if (type == 2)
80029ce: 7bbb ldrb r3, [r7, #14]
80029d0: 2b02 cmp r3, #2
80029d2: d10e bne.n 80029f2 <SD_disk_initialize+0x156>
{
if (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 0) == 0)
80029d4: 2100 movs r1, #0
80029d6: 2077 movs r0, #119 ; 0x77
80029d8: f7ff ff0e bl 80027f8 <SD_SendCmd>
80029dc: 4603 mov r3, r0
80029de: 2b01 cmp r3, #1
80029e0: d80e bhi.n 8002a00 <SD_disk_initialize+0x164>
80029e2: 2100 movs r1, #0
80029e4: 2069 movs r0, #105 ; 0x69
80029e6: f7ff ff07 bl 80027f8 <SD_SendCmd>
80029ea: 4603 mov r3, r0
80029ec: 2b00 cmp r3, #0
80029ee: d107 bne.n 8002a00 <SD_disk_initialize+0x164>
break; /* ACMD41 */
80029f0: e00d b.n 8002a0e <SD_disk_initialize+0x172>
}
else
{
if (SD_SendCmd(CMD1, 0) == 0)
80029f2: 2100 movs r1, #0
80029f4: 2041 movs r0, #65 ; 0x41
80029f6: f7ff feff bl 80027f8 <SD_SendCmd>
80029fa: 4603 mov r3, r0
80029fc: 2b00 cmp r3, #0
80029fe: d005 beq.n 8002a0c <SD_disk_initialize+0x170>
break; /* CMD1 */
}
} while (Timer1);
8002a00: 4b19 ldr r3, [pc, #100] ; (8002a68 <SD_disk_initialize+0x1cc>)
8002a02: 781b ldrb r3, [r3, #0]
8002a04: b2db uxtb r3, r3
8002a06: 2b00 cmp r3, #0
8002a08: d1e1 bne.n 80029ce <SD_disk_initialize+0x132>
8002a0a: e000 b.n 8002a0e <SD_disk_initialize+0x172>
break; /* CMD1 */
8002a0c: bf00 nop
if (!Timer1 || SD_SendCmd(CMD16, 512) != 0)
8002a0e: 4b16 ldr r3, [pc, #88] ; (8002a68 <SD_disk_initialize+0x1cc>)
8002a10: 781b ldrb r3, [r3, #0]
8002a12: b2db uxtb r3, r3
8002a14: 2b00 cmp r3, #0
8002a16: d007 beq.n 8002a28 <SD_disk_initialize+0x18c>
8002a18: f44f 7100 mov.w r1, #512 ; 0x200
8002a1c: 2050 movs r0, #80 ; 0x50
8002a1e: f7ff feeb bl 80027f8 <SD_SendCmd>
8002a22: 4603 mov r3, r0
8002a24: 2b00 cmp r3, #0
8002a26: d001 beq.n 8002a2c <SD_disk_initialize+0x190>
{
type = 0;
8002a28: 2300 movs r3, #0
8002a2a: 73bb strb r3, [r7, #14]
}
}
}
CardType = type;
8002a2c: 4a0f ldr r2, [pc, #60] ; (8002a6c <SD_disk_initialize+0x1d0>)
8002a2e: 7bbb ldrb r3, [r7, #14]
8002a30: 7013 strb r3, [r2, #0]
DESELECT();
8002a32: f7ff fd87 bl 8002544 <DESELECT>
SPI_RxByte();
8002a36: f7ff fdab bl 8002590 <SPI_RxByte>
if (type)
8002a3a: 7bbb ldrb r3, [r7, #14]
8002a3c: 2b00 cmp r3, #0
8002a3e: d008 beq.n 8002a52 <SD_disk_initialize+0x1b6>
{
/* Clear STA_NOINIT */
Stat &= ~STA_NOINIT;
8002a40: 4b08 ldr r3, [pc, #32] ; (8002a64 <SD_disk_initialize+0x1c8>)
8002a42: 781b ldrb r3, [r3, #0]
8002a44: b2db uxtb r3, r3
8002a46: f023 0301 bic.w r3, r3, #1
8002a4a: b2da uxtb r2, r3
8002a4c: 4b05 ldr r3, [pc, #20] ; (8002a64 <SD_disk_initialize+0x1c8>)
8002a4e: 701a strb r2, [r3, #0]
8002a50: e001 b.n 8002a56 <SD_disk_initialize+0x1ba>
}
else
{
/* Initialization failed */
SD_PowerOff();
8002a52: f7ff fe31 bl 80026b8 <SD_PowerOff>
}
return Stat;
8002a56: 4b03 ldr r3, [pc, #12] ; (8002a64 <SD_disk_initialize+0x1c8>)
8002a58: 781b ldrb r3, [r3, #0]
8002a5a: b2db uxtb r3, r3
}
8002a5c: 4618 mov r0, r3
8002a5e: 3714 adds r7, #20
8002a60: 46bd mov sp, r7
8002a62: bd90 pop {r4, r7, pc}
8002a64: 20000020 .word 0x20000020
8002a68: 2000055d .word 0x2000055d
8002a6c: 20000050 .word 0x20000050
08002a70 <SD_disk_status>:
DSTATUS SD_disk_status(BYTE drv)
{
8002a70: b480 push {r7}
8002a72: b083 sub sp, #12
8002a74: af00 add r7, sp, #0
8002a76: 4603 mov r3, r0
8002a78: 71fb strb r3, [r7, #7]
if (drv)
8002a7a: 79fb ldrb r3, [r7, #7]
8002a7c: 2b00 cmp r3, #0
8002a7e: d001 beq.n 8002a84 <SD_disk_status+0x14>
return STA_NOINIT;
8002a80: 2301 movs r3, #1
8002a82: e002 b.n 8002a8a <SD_disk_status+0x1a>
return Stat;
8002a84: 4b03 ldr r3, [pc, #12] ; (8002a94 <SD_disk_status+0x24>)
8002a86: 781b ldrb r3, [r3, #0]
8002a88: b2db uxtb r3, r3
}
8002a8a: 4618 mov r0, r3
8002a8c: 370c adds r7, #12
8002a8e: 46bd mov sp, r7
8002a90: bc80 pop {r7}
8002a92: 4770 bx lr
8002a94: 20000020 .word 0x20000020
08002a98 <SD_disk_read>:
DRESULT SD_disk_read(BYTE pdrv, BYTE* buff, DWORD sector, UINT count)
{
8002a98: b580 push {r7, lr}
8002a9a: b084 sub sp, #16
8002a9c: af00 add r7, sp, #0
8002a9e: 60b9 str r1, [r7, #8]
8002aa0: 607a str r2, [r7, #4]
8002aa2: 603b str r3, [r7, #0]
8002aa4: 4603 mov r3, r0
8002aa6: 73fb strb r3, [r7, #15]
if (pdrv || !count)
8002aa8: 7bfb ldrb r3, [r7, #15]
8002aaa: 2b00 cmp r3, #0
8002aac: d102 bne.n 8002ab4 <SD_disk_read+0x1c>
8002aae: 683b ldr r3, [r7, #0]
8002ab0: 2b00 cmp r3, #0
8002ab2: d101 bne.n 8002ab8 <SD_disk_read+0x20>
return RES_PARERR;
8002ab4: 2304 movs r3, #4
8002ab6: e051 b.n 8002b5c <SD_disk_read+0xc4>
if (Stat & STA_NOINIT)
8002ab8: 4b2a ldr r3, [pc, #168] ; (8002b64 <SD_disk_read+0xcc>)
8002aba: 781b ldrb r3, [r3, #0]
8002abc: b2db uxtb r3, r3
8002abe: f003 0301 and.w r3, r3, #1
8002ac2: 2b00 cmp r3, #0
8002ac4: d001 beq.n 8002aca <SD_disk_read+0x32>
return RES_NOTRDY;
8002ac6: 2303 movs r3, #3
8002ac8: e048 b.n 8002b5c <SD_disk_read+0xc4>
if (!(CardType & 4))
8002aca: 4b27 ldr r3, [pc, #156] ; (8002b68 <SD_disk_read+0xd0>)
8002acc: 781b ldrb r3, [r3, #0]
8002ace: f003 0304 and.w r3, r3, #4
8002ad2: 2b00 cmp r3, #0
8002ad4: d102 bne.n 8002adc <SD_disk_read+0x44>
sector *= 512;
8002ad6: 687b ldr r3, [r7, #4]
8002ad8: 025b lsls r3, r3, #9
8002ada: 607b str r3, [r7, #4]
SELECT();
8002adc: f7ff fd26 bl 800252c <SELECT>
if (count == 1)
8002ae0: 683b ldr r3, [r7, #0]
8002ae2: 2b01 cmp r3, #1
8002ae4: d111 bne.n 8002b0a <SD_disk_read+0x72>
{
if ((SD_SendCmd(CMD17, sector) == 0) && SD_RxDataBlock(buff, 512))
8002ae6: 6879 ldr r1, [r7, #4]
8002ae8: 2051 movs r0, #81 ; 0x51
8002aea: f7ff fe85 bl 80027f8 <SD_SendCmd>
8002aee: 4603 mov r3, r0
8002af0: 2b00 cmp r3, #0
8002af2: d129 bne.n 8002b48 <SD_disk_read+0xb0>
8002af4: f44f 7100 mov.w r1, #512 ; 0x200
8002af8: 68b8 ldr r0, [r7, #8]
8002afa: f7ff fdf3 bl 80026e4 <SD_RxDataBlock>
8002afe: 4603 mov r3, r0
8002b00: 2b00 cmp r3, #0
8002b02: d021 beq.n 8002b48 <SD_disk_read+0xb0>
count = 0;
8002b04: 2300 movs r3, #0
8002b06: 603b str r3, [r7, #0]
8002b08: e01e b.n 8002b48 <SD_disk_read+0xb0>
}
else
{
if (SD_SendCmd(CMD18, sector) == 0)
8002b0a: 6879 ldr r1, [r7, #4]
8002b0c: 2052 movs r0, #82 ; 0x52
8002b0e: f7ff fe73 bl 80027f8 <SD_SendCmd>
8002b12: 4603 mov r3, r0
8002b14: 2b00 cmp r3, #0
8002b16: d117 bne.n 8002b48 <SD_disk_read+0xb0>
{
do {
if (!SD_RxDataBlock(buff, 512))
8002b18: f44f 7100 mov.w r1, #512 ; 0x200
8002b1c: 68b8 ldr r0, [r7, #8]
8002b1e: f7ff fde1 bl 80026e4 <SD_RxDataBlock>
8002b22: 4603 mov r3, r0
8002b24: 2b00 cmp r3, #0
8002b26: d00a beq.n 8002b3e <SD_disk_read+0xa6>
break;
buff += 512;
8002b28: 68bb ldr r3, [r7, #8]
8002b2a: f503 7300 add.w r3, r3, #512 ; 0x200
8002b2e: 60bb str r3, [r7, #8]
} while (--count);
8002b30: 683b ldr r3, [r7, #0]
8002b32: 3b01 subs r3, #1
8002b34: 603b str r3, [r7, #0]
8002b36: 683b ldr r3, [r7, #0]
8002b38: 2b00 cmp r3, #0
8002b3a: d1ed bne.n 8002b18 <SD_disk_read+0x80>
8002b3c: e000 b.n 8002b40 <SD_disk_read+0xa8>
break;
8002b3e: bf00 nop
SD_SendCmd(CMD12, 0);
8002b40: 2100 movs r1, #0
8002b42: 204c movs r0, #76 ; 0x4c
8002b44: f7ff fe58 bl 80027f8 <SD_SendCmd>
}
}
DESELECT();
8002b48: f7ff fcfc bl 8002544 <DESELECT>
SPI_RxByte();
8002b4c: f7ff fd20 bl 8002590 <SPI_RxByte>
return count ? RES_ERROR : RES_OK;
8002b50: 683b ldr r3, [r7, #0]
8002b52: 2b00 cmp r3, #0
8002b54: bf14 ite ne
8002b56: 2301 movne r3, #1
8002b58: 2300 moveq r3, #0
8002b5a: b2db uxtb r3, r3
}
8002b5c: 4618 mov r0, r3
8002b5e: 3710 adds r7, #16
8002b60: 46bd mov sp, r7
8002b62: bd80 pop {r7, pc}
8002b64: 20000020 .word 0x20000020
8002b68: 20000050 .word 0x20000050
08002b6c <SD_disk_write>:
#if _READONLY == 0
DRESULT SD_disk_write(BYTE pdrv, const BYTE* buff, DWORD sector, UINT count)
{
8002b6c: b580 push {r7, lr}
8002b6e: b084 sub sp, #16
8002b70: af00 add r7, sp, #0
8002b72: 60b9 str r1, [r7, #8]
8002b74: 607a str r2, [r7, #4]
8002b76: 603b str r3, [r7, #0]
8002b78: 4603 mov r3, r0
8002b7a: 73fb strb r3, [r7, #15]
if (pdrv || !count)
8002b7c: 7bfb ldrb r3, [r7, #15]
8002b7e: 2b00 cmp r3, #0
8002b80: d102 bne.n 8002b88 <SD_disk_write+0x1c>
8002b82: 683b ldr r3, [r7, #0]
8002b84: 2b00 cmp r3, #0
8002b86: d101 bne.n 8002b8c <SD_disk_write+0x20>
return RES_PARERR;
8002b88: 2304 movs r3, #4
8002b8a: e06b b.n 8002c64 <SD_disk_write+0xf8>
if (Stat & STA_NOINIT)
8002b8c: 4b37 ldr r3, [pc, #220] ; (8002c6c <SD_disk_write+0x100>)
8002b8e: 781b ldrb r3, [r3, #0]
8002b90: b2db uxtb r3, r3
8002b92: f003 0301 and.w r3, r3, #1
8002b96: 2b00 cmp r3, #0
8002b98: d001 beq.n 8002b9e <SD_disk_write+0x32>
return RES_NOTRDY;
8002b9a: 2303 movs r3, #3
8002b9c: e062 b.n 8002c64 <SD_disk_write+0xf8>
if (Stat & STA_PROTECT)
8002b9e: 4b33 ldr r3, [pc, #204] ; (8002c6c <SD_disk_write+0x100>)
8002ba0: 781b ldrb r3, [r3, #0]
8002ba2: b2db uxtb r3, r3
8002ba4: f003 0304 and.w r3, r3, #4
8002ba8: 2b00 cmp r3, #0
8002baa: d001 beq.n 8002bb0 <SD_disk_write+0x44>
return RES_WRPRT;
8002bac: 2302 movs r3, #2
8002bae: e059 b.n 8002c64 <SD_disk_write+0xf8>
if (!(CardType & 4))
8002bb0: 4b2f ldr r3, [pc, #188] ; (8002c70 <SD_disk_write+0x104>)
8002bb2: 781b ldrb r3, [r3, #0]
8002bb4: f003 0304 and.w r3, r3, #4
8002bb8: 2b00 cmp r3, #0
8002bba: d102 bne.n 8002bc2 <SD_disk_write+0x56>
sector *= 512;
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 025b lsls r3, r3, #9
8002bc0: 607b str r3, [r7, #4]
SELECT();
8002bc2: f7ff fcb3 bl 800252c <SELECT>
if (count == 1)
8002bc6: 683b ldr r3, [r7, #0]
8002bc8: 2b01 cmp r3, #1
8002bca: d110 bne.n 8002bee <SD_disk_write+0x82>
{
if ((SD_SendCmd(CMD24, sector) == 0) && SD_TxDataBlock(buff, 0xFE))
8002bcc: 6879 ldr r1, [r7, #4]
8002bce: 2058 movs r0, #88 ; 0x58
8002bd0: f7ff fe12 bl 80027f8 <SD_SendCmd>
8002bd4: 4603 mov r3, r0
8002bd6: 2b00 cmp r3, #0
8002bd8: d13a bne.n 8002c50 <SD_disk_write+0xe4>
8002bda: 21fe movs r1, #254 ; 0xfe
8002bdc: 68b8 ldr r0, [r7, #8]
8002bde: f7ff fdb7 bl 8002750 <SD_TxDataBlock>
8002be2: 4603 mov r3, r0
8002be4: 2b00 cmp r3, #0
8002be6: d033 beq.n 8002c50 <SD_disk_write+0xe4>
count = 0;
8002be8: 2300 movs r3, #0
8002bea: 603b str r3, [r7, #0]
8002bec: e030 b.n 8002c50 <SD_disk_write+0xe4>
}
else
{
if (CardType & 2)
8002bee: 4b20 ldr r3, [pc, #128] ; (8002c70 <SD_disk_write+0x104>)
8002bf0: 781b ldrb r3, [r3, #0]
8002bf2: f003 0302 and.w r3, r3, #2
8002bf6: 2b00 cmp r3, #0
8002bf8: d007 beq.n 8002c0a <SD_disk_write+0x9e>
{
SD_SendCmd(CMD55, 0);
8002bfa: 2100 movs r1, #0
8002bfc: 2077 movs r0, #119 ; 0x77
8002bfe: f7ff fdfb bl 80027f8 <SD_SendCmd>
SD_SendCmd(CMD23, count); /* ACMD23 */
8002c02: 6839 ldr r1, [r7, #0]
8002c04: 2057 movs r0, #87 ; 0x57
8002c06: f7ff fdf7 bl 80027f8 <SD_SendCmd>
}
if (SD_SendCmd(CMD25, sector) == 0)
8002c0a: 6879 ldr r1, [r7, #4]
8002c0c: 2059 movs r0, #89 ; 0x59
8002c0e: f7ff fdf3 bl 80027f8 <SD_SendCmd>
8002c12: 4603 mov r3, r0
8002c14: 2b00 cmp r3, #0
8002c16: d11b bne.n 8002c50 <SD_disk_write+0xe4>
{
do {
if(!SD_TxDataBlock(buff, 0xFC))
8002c18: 21fc movs r1, #252 ; 0xfc
8002c1a: 68b8 ldr r0, [r7, #8]
8002c1c: f7ff fd98 bl 8002750 <SD_TxDataBlock>
8002c20: 4603 mov r3, r0
8002c22: 2b00 cmp r3, #0
8002c24: d00a beq.n 8002c3c <SD_disk_write+0xd0>
break;
buff += 512;
8002c26: 68bb ldr r3, [r7, #8]
8002c28: f503 7300 add.w r3, r3, #512 ; 0x200
8002c2c: 60bb str r3, [r7, #8]
} while (--count);
8002c2e: 683b ldr r3, [r7, #0]
8002c30: 3b01 subs r3, #1
8002c32: 603b str r3, [r7, #0]
8002c34: 683b ldr r3, [r7, #0]
8002c36: 2b00 cmp r3, #0
8002c38: d1ee bne.n 8002c18 <SD_disk_write+0xac>
8002c3a: e000 b.n 8002c3e <SD_disk_write+0xd2>
break;
8002c3c: bf00 nop
if(!SD_TxDataBlock(0, 0xFD))
8002c3e: 21fd movs r1, #253 ; 0xfd
8002c40: 2000 movs r0, #0
8002c42: f7ff fd85 bl 8002750 <SD_TxDataBlock>
8002c46: 4603 mov r3, r0
8002c48: 2b00 cmp r3, #0
8002c4a: d101 bne.n 8002c50 <SD_disk_write+0xe4>
{
count = 1;
8002c4c: 2301 movs r3, #1
8002c4e: 603b str r3, [r7, #0]
}
}
}
DESELECT();
8002c50: f7ff fc78 bl 8002544 <DESELECT>
SPI_RxByte();
8002c54: f7ff fc9c bl 8002590 <SPI_RxByte>
return count ? RES_ERROR : RES_OK;
8002c58: 683b ldr r3, [r7, #0]
8002c5a: 2b00 cmp r3, #0
8002c5c: bf14 ite ne
8002c5e: 2301 movne r3, #1
8002c60: 2300 moveq r3, #0
8002c62: b2db uxtb r3, r3
}
8002c64: 4618 mov r0, r3
8002c66: 3710 adds r7, #16
8002c68: 46bd mov sp, r7
8002c6a: bd80 pop {r7, pc}
8002c6c: 20000020 .word 0x20000020
8002c70: 20000050 .word 0x20000050
08002c74 <SD_disk_ioctl>:
#endif /* _READONLY */
DRESULT SD_disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
{
8002c74: b590 push {r4, r7, lr}
8002c76: b08b sub sp, #44 ; 0x2c
8002c78: af00 add r7, sp, #0
8002c7a: 4603 mov r3, r0
8002c7c: 603a str r2, [r7, #0]
8002c7e: 71fb strb r3, [r7, #7]
8002c80: 460b mov r3, r1
8002c82: 71bb strb r3, [r7, #6]
DRESULT res;
BYTE n, csd[16], *ptr = buff;
8002c84: 683b ldr r3, [r7, #0]
8002c86: 623b str r3, [r7, #32]
WORD csize;
if (drv)
8002c88: 79fb ldrb r3, [r7, #7]
8002c8a: 2b00 cmp r3, #0
8002c8c: d001 beq.n 8002c92 <SD_disk_ioctl+0x1e>
return RES_PARERR;
8002c8e: 2304 movs r3, #4
8002c90: e11b b.n 8002eca <SD_disk_ioctl+0x256>
res = RES_ERROR;
8002c92: 2301 movs r3, #1
8002c94: f887 3027 strb.w r3, [r7, #39] ; 0x27
if (ctrl == CTRL_POWER)
8002c98: 79bb ldrb r3, [r7, #6]
8002c9a: 2b05 cmp r3, #5
8002c9c: d129 bne.n 8002cf2 <SD_disk_ioctl+0x7e>
{
switch (*ptr)
8002c9e: 6a3b ldr r3, [r7, #32]
8002ca0: 781b ldrb r3, [r3, #0]
8002ca2: 2b02 cmp r3, #2
8002ca4: d017 beq.n 8002cd6 <SD_disk_ioctl+0x62>
8002ca6: 2b02 cmp r3, #2
8002ca8: dc1f bgt.n 8002cea <SD_disk_ioctl+0x76>
8002caa: 2b00 cmp r3, #0
8002cac: d002 beq.n 8002cb4 <SD_disk_ioctl+0x40>
8002cae: 2b01 cmp r3, #1
8002cb0: d00b beq.n 8002cca <SD_disk_ioctl+0x56>
8002cb2: e01a b.n 8002cea <SD_disk_ioctl+0x76>
{
case 0:
if (SD_CheckPower())
8002cb4: f7ff fd0c bl 80026d0 <SD_CheckPower>
8002cb8: 4603 mov r3, r0
8002cba: 2b00 cmp r3, #0
8002cbc: d001 beq.n 8002cc2 <SD_disk_ioctl+0x4e>
SD_PowerOff(); /* Power Off */
8002cbe: f7ff fcfb bl 80026b8 <SD_PowerOff>
res = RES_OK;
8002cc2: 2300 movs r3, #0
8002cc4: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002cc8: e0fd b.n 8002ec6 <SD_disk_ioctl+0x252>
case 1:
SD_PowerOn(); /* Power On */
8002cca: f7ff fca9 bl 8002620 <SD_PowerOn>
res = RES_OK;
8002cce: 2300 movs r3, #0
8002cd0: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002cd4: e0f7 b.n 8002ec6 <SD_disk_ioctl+0x252>
case 2:
*(ptr + 1) = (BYTE) SD_CheckPower();
8002cd6: 6a3b ldr r3, [r7, #32]
8002cd8: 1c5c adds r4, r3, #1
8002cda: f7ff fcf9 bl 80026d0 <SD_CheckPower>
8002cde: 4603 mov r3, r0
8002ce0: 7023 strb r3, [r4, #0]
res = RES_OK; /* Power Check */
8002ce2: 2300 movs r3, #0
8002ce4: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002ce8: e0ed b.n 8002ec6 <SD_disk_ioctl+0x252>
default:
res = RES_PARERR;
8002cea: 2304 movs r3, #4
8002cec: f887 3027 strb.w r3, [r7, #39] ; 0x27
8002cf0: e0e9 b.n 8002ec6 <SD_disk_ioctl+0x252>
}
}
else
{
if (Stat & STA_NOINIT)
8002cf2: 4b78 ldr r3, [pc, #480] ; (8002ed4 <SD_disk_ioctl+0x260>)
8002cf4: 781b ldrb r3, [r3, #0]
8002cf6: b2db uxtb r3, r3
8002cf8: f003 0301 and.w r3, r3, #1
8002cfc: 2b00 cmp r3, #0
8002cfe: d001 beq.n 8002d04 <SD_disk_ioctl+0x90>
return RES_NOTRDY;
8002d00: 2303 movs r3, #3
8002d02: e0e2 b.n 8002eca <SD_disk_ioctl+0x256>
SELECT();
8002d04: f7ff fc12 bl 800252c <SELECT>
switch (ctrl)
8002d08: 79bb ldrb r3, [r7, #6]
8002d0a: 2b0d cmp r3, #13
8002d0c: f200 80cc bhi.w 8002ea8 <SD_disk_ioctl+0x234>
8002d10: a201 add r2, pc, #4 ; (adr r2, 8002d18 <SD_disk_ioctl+0xa4>)
8002d12: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002d16: bf00 nop
8002d18: 08002e13 .word 0x08002e13
8002d1c: 08002d51 .word 0x08002d51
8002d20: 08002e03 .word 0x08002e03
8002d24: 08002ea9 .word 0x08002ea9
8002d28: 08002ea9 .word 0x08002ea9
8002d2c: 08002ea9 .word 0x08002ea9
8002d30: 08002ea9 .word 0x08002ea9
8002d34: 08002ea9 .word 0x08002ea9
8002d38: 08002ea9 .word 0x08002ea9
8002d3c: 08002ea9 .word 0x08002ea9
8002d40: 08002ea9 .word 0x08002ea9
8002d44: 08002e25 .word 0x08002e25
8002d48: 08002e49 .word 0x08002e49
8002d4c: 08002e6d .word 0x08002e6d
{
case GET_SECTOR_COUNT:
if ((SD_SendCmd(CMD9, 0) == 0) && SD_RxDataBlock(csd, 16))
8002d50: 2100 movs r1, #0
8002d52: 2049 movs r0, #73 ; 0x49
8002d54: f7ff fd50 bl 80027f8 <SD_SendCmd>
8002d58: 4603 mov r3, r0
8002d5a: 2b00 cmp r3, #0
8002d5c: f040 80a8 bne.w 8002eb0 <SD_disk_ioctl+0x23c>
8002d60: f107 030c add.w r3, r7, #12
8002d64: 2110 movs r1, #16
8002d66: 4618 mov r0, r3
8002d68: f7ff fcbc bl 80026e4 <SD_RxDataBlock>
8002d6c: 4603 mov r3, r0
8002d6e: 2b00 cmp r3, #0
8002d70: f000 809e beq.w 8002eb0 <SD_disk_ioctl+0x23c>
{
if ((csd[0] >> 6) == 1)
8002d74: 7b3b ldrb r3, [r7, #12]
8002d76: 099b lsrs r3, r3, #6
8002d78: b2db uxtb r3, r3
8002d7a: 2b01 cmp r3, #1
8002d7c: d10e bne.n 8002d9c <SD_disk_ioctl+0x128>
{
/* SDC ver 2.00 */
csize = csd[9] + ((WORD) csd[8] << 8) + 1;
8002d7e: 7d7b ldrb r3, [r7, #21]
8002d80: b29a uxth r2, r3
8002d82: 7d3b ldrb r3, [r7, #20]
8002d84: b29b uxth r3, r3
8002d86: 021b lsls r3, r3, #8
8002d88: b29b uxth r3, r3
8002d8a: 4413 add r3, r2
8002d8c: b29b uxth r3, r3
8002d8e: 3301 adds r3, #1
8002d90: 83fb strh r3, [r7, #30]
*(DWORD*) buff = (DWORD) csize << 10;
8002d92: 8bfb ldrh r3, [r7, #30]
8002d94: 029a lsls r2, r3, #10
8002d96: 683b ldr r3, [r7, #0]
8002d98: 601a str r2, [r3, #0]
8002d9a: e02e b.n 8002dfa <SD_disk_ioctl+0x186>
}
else
{
/* MMC or SDC ver 1.XX */
n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
8002d9c: 7c7b ldrb r3, [r7, #17]
8002d9e: f003 030f and.w r3, r3, #15
8002da2: b2da uxtb r2, r3
8002da4: 7dbb ldrb r3, [r7, #22]
8002da6: 09db lsrs r3, r3, #7
8002da8: b2db uxtb r3, r3
8002daa: 4413 add r3, r2
8002dac: b2da uxtb r2, r3
8002dae: 7d7b ldrb r3, [r7, #21]
8002db0: 005b lsls r3, r3, #1
8002db2: b2db uxtb r3, r3
8002db4: f003 0306 and.w r3, r3, #6
8002db8: b2db uxtb r3, r3
8002dba: 4413 add r3, r2
8002dbc: b2db uxtb r3, r3
8002dbe: 3302 adds r3, #2
8002dc0: f887 3026 strb.w r3, [r7, #38] ; 0x26
csize = (csd[8] >> 6) + ((WORD) csd[7] << 2) + ((WORD) (csd[6] & 3) << 10) + 1;
8002dc4: 7d3b ldrb r3, [r7, #20]
8002dc6: 099b lsrs r3, r3, #6
8002dc8: b2db uxtb r3, r3
8002dca: b29a uxth r2, r3
8002dcc: 7cfb ldrb r3, [r7, #19]
8002dce: b29b uxth r3, r3
8002dd0: 009b lsls r3, r3, #2
8002dd2: b29b uxth r3, r3
8002dd4: 4413 add r3, r2
8002dd6: b29a uxth r2, r3
8002dd8: 7cbb ldrb r3, [r7, #18]
8002dda: 029b lsls r3, r3, #10
8002ddc: b29b uxth r3, r3
8002dde: f403 6340 and.w r3, r3, #3072 ; 0xc00
8002de2: b29b uxth r3, r3
8002de4: 4413 add r3, r2
8002de6: b29b uxth r3, r3
8002de8: 3301 adds r3, #1
8002dea: 83fb strh r3, [r7, #30]
*(DWORD*) buff = (DWORD) csize << (n - 9);
8002dec: 8bfa ldrh r2, [r7, #30]
8002dee: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8002df2: 3b09 subs r3, #9
8002df4: 409a lsls r2, r3
8002df6: 683b ldr r3, [r7, #0]
8002df8: 601a str r2, [r3, #0]
}
res = RES_OK;
8002dfa: 2300 movs r3, #0
8002dfc: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
break;
8002e00: e056 b.n 8002eb0 <SD_disk_ioctl+0x23c>
case GET_SECTOR_SIZE:
*(WORD*) buff = 512;
8002e02: 683b ldr r3, [r7, #0]
8002e04: f44f 7200 mov.w r2, #512 ; 0x200
8002e08: 801a strh r2, [r3, #0]
res = RES_OK;
8002e0a: 2300 movs r3, #0
8002e0c: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002e10: e055 b.n 8002ebe <SD_disk_ioctl+0x24a>
case CTRL_SYNC:
if (SD_ReadyWait() == 0xFF)
8002e12: f7ff fbe9 bl 80025e8 <SD_ReadyWait>
8002e16: 4603 mov r3, r0
8002e18: 2bff cmp r3, #255 ; 0xff
8002e1a: d14b bne.n 8002eb4 <SD_disk_ioctl+0x240>
res = RES_OK;
8002e1c: 2300 movs r3, #0
8002e1e: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002e22: e047 b.n 8002eb4 <SD_disk_ioctl+0x240>
case MMC_GET_CSD:
if (SD_SendCmd(CMD9, 0) == 0 && SD_RxDataBlock(ptr, 16))
8002e24: 2100 movs r1, #0
8002e26: 2049 movs r0, #73 ; 0x49
8002e28: f7ff fce6 bl 80027f8 <SD_SendCmd>
8002e2c: 4603 mov r3, r0
8002e2e: 2b00 cmp r3, #0
8002e30: d142 bne.n 8002eb8 <SD_disk_ioctl+0x244>
8002e32: 2110 movs r1, #16
8002e34: 6a38 ldr r0, [r7, #32]
8002e36: f7ff fc55 bl 80026e4 <SD_RxDataBlock>
8002e3a: 4603 mov r3, r0
8002e3c: 2b00 cmp r3, #0
8002e3e: d03b beq.n 8002eb8 <SD_disk_ioctl+0x244>
res = RES_OK;
8002e40: 2300 movs r3, #0
8002e42: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002e46: e037 b.n 8002eb8 <SD_disk_ioctl+0x244>
case MMC_GET_CID:
if (SD_SendCmd(CMD10, 0) == 0 && SD_RxDataBlock(ptr, 16))
8002e48: 2100 movs r1, #0
8002e4a: 204a movs r0, #74 ; 0x4a
8002e4c: f7ff fcd4 bl 80027f8 <SD_SendCmd>
8002e50: 4603 mov r3, r0
8002e52: 2b00 cmp r3, #0
8002e54: d132 bne.n 8002ebc <SD_disk_ioctl+0x248>
8002e56: 2110 movs r1, #16
8002e58: 6a38 ldr r0, [r7, #32]
8002e5a: f7ff fc43 bl 80026e4 <SD_RxDataBlock>
8002e5e: 4603 mov r3, r0
8002e60: 2b00 cmp r3, #0
8002e62: d02b beq.n 8002ebc <SD_disk_ioctl+0x248>
res = RES_OK;
8002e64: 2300 movs r3, #0
8002e66: f887 3027 strb.w r3, [r7, #39] ; 0x27
break;
8002e6a: e027 b.n 8002ebc <SD_disk_ioctl+0x248>
case MMC_GET_OCR:
if (SD_SendCmd(CMD58, 0) == 0)
8002e6c: 2100 movs r1, #0
8002e6e: 207a movs r0, #122 ; 0x7a
8002e70: f7ff fcc2 bl 80027f8 <SD_SendCmd>
8002e74: 4603 mov r3, r0
8002e76: 2b00 cmp r3, #0
8002e78: d116 bne.n 8002ea8 <SD_disk_ioctl+0x234>
{
for (n = 0; n < 4; n++)
8002e7a: 2300 movs r3, #0
8002e7c: f887 3026 strb.w r3, [r7, #38] ; 0x26
8002e80: e00b b.n 8002e9a <SD_disk_ioctl+0x226>
{
*ptr++ = SPI_RxByte();
8002e82: 6a3c ldr r4, [r7, #32]
8002e84: 1c63 adds r3, r4, #1
8002e86: 623b str r3, [r7, #32]
8002e88: f7ff fb82 bl 8002590 <SPI_RxByte>
8002e8c: 4603 mov r3, r0
8002e8e: 7023 strb r3, [r4, #0]
for (n = 0; n < 4; n++)
8002e90: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8002e94: 3301 adds r3, #1
8002e96: f887 3026 strb.w r3, [r7, #38] ; 0x26
8002e9a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8002e9e: 2b03 cmp r3, #3
8002ea0: d9ef bls.n 8002e82 <SD_disk_ioctl+0x20e>
}
res = RES_OK;
8002ea2: 2300 movs r3, #0
8002ea4: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
default:
res = RES_PARERR;
8002ea8: 2304 movs r3, #4
8002eaa: f887 3027 strb.w r3, [r7, #39] ; 0x27
8002eae: e006 b.n 8002ebe <SD_disk_ioctl+0x24a>
break;
8002eb0: bf00 nop
8002eb2: e004 b.n 8002ebe <SD_disk_ioctl+0x24a>
break;
8002eb4: bf00 nop
8002eb6: e002 b.n 8002ebe <SD_disk_ioctl+0x24a>
break;
8002eb8: bf00 nop
8002eba: e000 b.n 8002ebe <SD_disk_ioctl+0x24a>
break;
8002ebc: bf00 nop
}
DESELECT();
8002ebe: f7ff fb41 bl 8002544 <DESELECT>
SPI_RxByte();
8002ec2: f7ff fb65 bl 8002590 <SPI_RxByte>
}
return res;
8002ec6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
}
8002eca: 4618 mov r0, r3
8002ecc: 372c adds r7, #44 ; 0x2c
8002ece: 46bd mov sp, r7
8002ed0: bd90 pop {r4, r7, pc}
8002ed2: bf00 nop
8002ed4: 20000020 .word 0x20000020
08002ed8 <LCD_WR_REG>:
_lcd_dev lcddev; //����LCD��Ҫ����
//**************************************************���ֿ��ٽӿ�
//д�Ĵ�������
//regval:�Ĵ���ֵ
void LCD_WR_REG(uint16_t regval)
{
8002ed8: b480 push {r7}
8002eda: b083 sub sp, #12
8002edc: af00 add r7, sp, #0
8002ede: 4603 mov r3, r0
8002ee0: 80fb strh r3, [r7, #6]
LCD_REG_ADDRESS=regval;//д��Ҫд�ļĴ�������
8002ee2: f04f 42d8 mov.w r2, #1811939328 ; 0x6c000000
8002ee6: 88fb ldrh r3, [r7, #6]
8002ee8: 8013 strh r3, [r2, #0]
}
8002eea: bf00 nop
8002eec: 370c adds r7, #12
8002eee: 46bd mov sp, r7
8002ef0: bc80 pop {r7}
8002ef2: 4770 bx lr
08002ef4 <LCD_WR_DATA>:
//дLCD����
//data:Ҫд����ֵ
void LCD_WR_DATA(uint16_t data)
{
8002ef4: b480 push {r7}
8002ef6: b083 sub sp, #12
8002ef8: af00 add r7, sp, #0
8002efa: 4603 mov r3, r0
8002efc: 80fb strh r3, [r7, #6]
LCD_DATA_ADDRESS=data;
8002efe: 4a04 ldr r2, [pc, #16] ; (8002f10 <LCD_WR_DATA+0x1c>)
8002f00: 88fb ldrh r3, [r7, #6]
8002f02: 8013 strh r3, [r2, #0]
}
8002f04: bf00 nop
8002f06: 370c adds r7, #12
8002f08: 46bd mov sp, r7
8002f0a: bc80 pop {r7}
8002f0c: 4770 bx lr
8002f0e: bf00 nop
8002f10: 6c000800 .word 0x6c000800
08002f14 <LCD_WriteReg>:
}
//д�Ĵ���
//LCD_Reg:�Ĵ�����ַ
//LCD_RegValue:Ҫд��������
void LCD_WriteReg(uint16_t LCD_Reg, uint16_t LCD_RegValue)
{
8002f14: b480 push {r7}
8002f16: b083 sub sp, #12
8002f18: af00 add r7, sp, #0
8002f1a: 4603 mov r3, r0
8002f1c: 460a mov r2, r1
8002f1e: 80fb strh r3, [r7, #6]
8002f20: 4613 mov r3, r2
8002f22: 80bb strh r3, [r7, #4]
LCD_REG_ADDRESS = LCD_Reg; //д��Ҫд�ļĴ�������
8002f24: f04f 42d8 mov.w r2, #1811939328 ; 0x6c000000
8002f28: 88fb ldrh r3, [r7, #6]
8002f2a: 8013 strh r3, [r2, #0]
LCD_DATA_ADDRESS = LCD_RegValue;//�����
8002f2c: 4a03 ldr r2, [pc, #12] ; (8002f3c <LCD_WriteReg+0x28>)
8002f2e: 88bb ldrh r3, [r7, #4]
8002f30: 8013 strh r3, [r2, #0]
}
8002f32: bf00 nop
8002f34: 370c adds r7, #12
8002f36: 46bd mov sp, r7
8002f38: bc80 pop {r7}
8002f3a: 4770 bx lr
8002f3c: 6c000800 .word 0x6c000800
08002f40 <LCD_ReadReg>:
//���Ĵ���
//LCD_Reg:�Ĵ�����ַ
//����ֵ:����������
uint16_t LCD_ReadReg(uint16_t LCD_Reg)
{
8002f40: b480 push {r7}
8002f42: b083 sub sp, #12
8002f44: af00 add r7, sp, #0
8002f46: 4603 mov r3, r0
8002f48: 80fb strh r3, [r7, #6]
LCD_REG_ADDRESS=LCD_Reg; //д��Ҫ���ļĴ�������
8002f4a: f04f 42d8 mov.w r2, #1811939328 ; 0x6c000000
8002f4e: 88fb ldrh r3, [r7, #6]
8002f50: 8013 strh r3, [r2, #0]
//delay_us(5);
return LCD_DATA_ADDRESS; //���ض�����ֵ
8002f52: 4b04 ldr r3, [pc, #16] ; (8002f64 <LCD_ReadReg+0x24>)
8002f54: 881b ldrh r3, [r3, #0]
8002f56: b29b uxth r3, r3
}
8002f58: 4618 mov r0, r3
8002f5a: 370c adds r7, #12
8002f5c: 46bd mov sp, r7
8002f5e: bc80 pop {r7}
8002f60: 4770 bx lr
8002f62: bf00 nop
8002f64: 6c000800 .word 0x6c000800
08002f68 <LCD_Scan_Dir>:
//ע��:�����������ܻ��ܵ��˺������õ�Ӱ��(������9341/6804����������),
//����,һ������ΪL2R_U2D����,��������Ϊ����ɨ�跽ʽ,���ܵ�����ʾ������.
//dir:0~7,����8������(���嶨����lcd.h)
//9320/9325/9328/4531/4535/1505/b505/8989/5408/9341/5310��IC�Ѿ�ʵ�ʲ���
void LCD_Scan_Dir(uint8_t dir)
{
8002f68: b580 push {r7, lr}
8002f6a: b084 sub sp, #16
8002f6c: af00 add r7, sp, #0
8002f6e: 4603 mov r3, r0
8002f70: 71fb strb r3, [r7, #7]
uint16_t regval=0;
8002f72: 2300 movs r3, #0
8002f74: 81fb strh r3, [r7, #14]
uint8_t dirreg=0;
8002f76: 2300 movs r3, #0
8002f78: 737b strb r3, [r7, #13]
uint16_t temp;
if(lcddev.dir==1&&lcddev.id!=0X6804)//����ʱ����6804���ı�ɨ�跽����
8002f7a: 4ba8 ldr r3, [pc, #672] ; (800321c <LCD_Scan_Dir+0x2b4>)
8002f7c: 799b ldrb r3, [r3, #6]
8002f7e: 2b01 cmp r3, #1
8002f80: d134 bne.n 8002fec <LCD_Scan_Dir+0x84>
8002f82: 4ba6 ldr r3, [pc, #664] ; (800321c <LCD_Scan_Dir+0x2b4>)
8002f84: 889b ldrh r3, [r3, #4]
8002f86: f646 0204 movw r2, #26628 ; 0x6804
8002f8a: 4293 cmp r3, r2
8002f8c: d02e beq.n 8002fec <LCD_Scan_Dir+0x84>
{
switch(dir)//����ת��
8002f8e: 79fb ldrb r3, [r7, #7]
8002f90: 2b07 cmp r3, #7
8002f92: d82c bhi.n 8002fee <LCD_Scan_Dir+0x86>
8002f94: a201 add r2, pc, #4 ; (adr r2, 8002f9c <LCD_Scan_Dir+0x34>)
8002f96: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002f9a: bf00 nop
8002f9c: 08002fbd .word 0x08002fbd
8002fa0: 08002fc3 .word 0x08002fc3
8002fa4: 08002fc9 .word 0x08002fc9
8002fa8: 08002fcf .word 0x08002fcf
8002fac: 08002fd5 .word 0x08002fd5
8002fb0: 08002fdb .word 0x08002fdb
8002fb4: 08002fe1 .word 0x08002fe1
8002fb8: 08002fe7 .word 0x08002fe7
{
case 0:dir=6;break;
8002fbc: 2306 movs r3, #6
8002fbe: 71fb strb r3, [r7, #7]
8002fc0: e015 b.n 8002fee <LCD_Scan_Dir+0x86>
case 1:dir=7;break;
8002fc2: 2307 movs r3, #7
8002fc4: 71fb strb r3, [r7, #7]
8002fc6: e012 b.n 8002fee <LCD_Scan_Dir+0x86>
case 2:dir=4;break;
8002fc8: 2304 movs r3, #4
8002fca: 71fb strb r3, [r7, #7]
8002fcc: e00f b.n 8002fee <LCD_Scan_Dir+0x86>
case 3:dir=5;break;
8002fce: 2305 movs r3, #5
8002fd0: 71fb strb r3, [r7, #7]
8002fd2: e00c b.n 8002fee <LCD_Scan_Dir+0x86>
case 4:dir=1;break;
8002fd4: 2301 movs r3, #1
8002fd6: 71fb strb r3, [r7, #7]
8002fd8: e009 b.n 8002fee <LCD_Scan_Dir+0x86>
case 5:dir=0;break;
8002fda: 2300 movs r3, #0
8002fdc: 71fb strb r3, [r7, #7]
8002fde: e006 b.n 8002fee <LCD_Scan_Dir+0x86>
case 6:dir=3;break;
8002fe0: 2303 movs r3, #3
8002fe2: 71fb strb r3, [r7, #7]
8002fe4: e003 b.n 8002fee <LCD_Scan_Dir+0x86>
case 7:dir=2;break;
8002fe6: 2302 movs r3, #2
8002fe8: 71fb strb r3, [r7, #7]
8002fea: e000 b.n 8002fee <LCD_Scan_Dir+0x86>
}
}
8002fec: bf00 nop
if(lcddev.id==0x9341||lcddev.id==0X6804||lcddev.id==0X5310)//9341/6804/5310,������
8002fee: 4b8b ldr r3, [pc, #556] ; (800321c <LCD_Scan_Dir+0x2b4>)
8002ff0: 889b ldrh r3, [r3, #4]
8002ff2: f249 3241 movw r2, #37697 ; 0x9341
8002ff6: 4293 cmp r3, r2
8002ff8: d00c beq.n 8003014 <LCD_Scan_Dir+0xac>
8002ffa: 4b88 ldr r3, [pc, #544] ; (800321c <LCD_Scan_Dir+0x2b4>)
8002ffc: 889b ldrh r3, [r3, #4]
8002ffe: f646 0204 movw r2, #26628 ; 0x6804
8003002: 4293 cmp r3, r2
8003004: d006 beq.n 8003014 <LCD_Scan_Dir+0xac>
8003006: 4b85 ldr r3, [pc, #532] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003008: 889b ldrh r3, [r3, #4]
800300a: f245 3210 movw r2, #21264 ; 0x5310
800300e: 4293 cmp r3, r2
8003010: f040 80bb bne.w 800318a <LCD_Scan_Dir+0x222>
{
switch(dir)
8003014: 79fb ldrb r3, [r7, #7]
8003016: 2b07 cmp r3, #7
8003018: d835 bhi.n 8003086 <LCD_Scan_Dir+0x11e>
800301a: a201 add r2, pc, #4 ; (adr r2, 8003020 <LCD_Scan_Dir+0xb8>)
800301c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003020: 08003087 .word 0x08003087
8003024: 08003041 .word 0x08003041
8003028: 0800304b .word 0x0800304b
800302c: 08003055 .word 0x08003055
8003030: 0800305f .word 0x0800305f
8003034: 08003069 .word 0x08003069
8003038: 08003073 .word 0x08003073
800303c: 0800307d .word 0x0800307d
{
case L2R_U2D://��������,���ϵ���
regval|=(0<<7)|(0<<6)|(0<<5);
break;
case L2R_D2U://��������,���µ���
regval|=(1<<7)|(0<<6)|(0<<5);
8003040: 89fb ldrh r3, [r7, #14]
8003042: f043 0380 orr.w r3, r3, #128 ; 0x80
8003046: 81fb strh r3, [r7, #14]
break;
8003048: e01d b.n 8003086 <LCD_Scan_Dir+0x11e>
case R2L_U2D://���ҵ���,���ϵ���
regval|=(0<<7)|(1<<6)|(0<<5);
800304a: 89fb ldrh r3, [r7, #14]
800304c: f043 0340 orr.w r3, r3, #64 ; 0x40
8003050: 81fb strh r3, [r7, #14]
break;
8003052: e018 b.n 8003086 <LCD_Scan_Dir+0x11e>
case R2L_D2U://���ҵ���,���µ���
regval|=(1<<7)|(1<<6)|(0<<5);
8003054: 89fb ldrh r3, [r7, #14]
8003056: f043 03c0 orr.w r3, r3, #192 ; 0xc0
800305a: 81fb strh r3, [r7, #14]
break;
800305c: e013 b.n 8003086 <LCD_Scan_Dir+0x11e>
case U2D_L2R://���ϵ���,��������
regval|=(0<<7)|(0<<6)|(1<<5);
800305e: 89fb ldrh r3, [r7, #14]
8003060: f043 0320 orr.w r3, r3, #32
8003064: 81fb strh r3, [r7, #14]
break;
8003066: e00e b.n 8003086 <LCD_Scan_Dir+0x11e>
case U2D_R2L://���ϵ���,���ҵ���
regval|=(0<<7)|(1<<6)|(1<<5);
8003068: 89fb ldrh r3, [r7, #14]
800306a: f043 0360 orr.w r3, r3, #96 ; 0x60
800306e: 81fb strh r3, [r7, #14]
break;
8003070: e009 b.n 8003086 <LCD_Scan_Dir+0x11e>
case D2U_L2R://���µ���,��������
regval|=(1<<7)|(0<<6)|(1<<5);
8003072: 89fb ldrh r3, [r7, #14]
8003074: f043 03a0 orr.w r3, r3, #160 ; 0xa0
8003078: 81fb strh r3, [r7, #14]
break;
800307a: e004 b.n 8003086 <LCD_Scan_Dir+0x11e>
case D2U_R2L://���µ���,���ҵ���
regval|=(1<<7)|(1<<6)|(1<<5);
800307c: 89fb ldrh r3, [r7, #14]
800307e: f043 03e0 orr.w r3, r3, #224 ; 0xe0
8003082: 81fb strh r3, [r7, #14]
break;
8003084: bf00 nop
}
dirreg=0X36;
8003086: 2336 movs r3, #54 ; 0x36
8003088: 737b strb r3, [r7, #13]
if(lcddev.id!=0X5310)regval|=0X08;//5310����ҪBGR
800308a: 4b64 ldr r3, [pc, #400] ; (800321c <LCD_Scan_Dir+0x2b4>)
800308c: 889b ldrh r3, [r3, #4]
800308e: f245 3210 movw r2, #21264 ; 0x5310
8003092: 4293 cmp r3, r2
8003094: d003 beq.n 800309e <LCD_Scan_Dir+0x136>
8003096: 89fb ldrh r3, [r7, #14]
8003098: f043 0308 orr.w r3, r3, #8
800309c: 81fb strh r3, [r7, #14]
if(lcddev.id==0X6804)regval|=0x02;//6804��BIT6��9341�ķ���
800309e: 4b5f ldr r3, [pc, #380] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030a0: 889b ldrh r3, [r3, #4]
80030a2: f646 0204 movw r2, #26628 ; 0x6804
80030a6: 4293 cmp r3, r2
80030a8: d103 bne.n 80030b2 <LCD_Scan_Dir+0x14a>
80030aa: 89fb ldrh r3, [r7, #14]
80030ac: f043 0302 orr.w r3, r3, #2
80030b0: 81fb strh r3, [r7, #14]
LCD_WriteReg(dirreg,regval);
80030b2: 7b7b ldrb r3, [r7, #13]
80030b4: b29b uxth r3, r3
80030b6: 89fa ldrh r2, [r7, #14]
80030b8: 4611 mov r1, r2
80030ba: 4618 mov r0, r3
80030bc: f7ff ff2a bl 8002f14 <LCD_WriteReg>
if((regval&0X20)||lcddev.dir==1)
80030c0: 89fb ldrh r3, [r7, #14]
80030c2: f003 0320 and.w r3, r3, #32
80030c6: 2b00 cmp r3, #0
80030c8: d103 bne.n 80030d2 <LCD_Scan_Dir+0x16a>
80030ca: 4b54 ldr r3, [pc, #336] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030cc: 799b ldrb r3, [r3, #6]
80030ce: 2b01 cmp r3, #1
80030d0: d110 bne.n 80030f4 <LCD_Scan_Dir+0x18c>
{
if(lcddev.width<lcddev.height)//����X,Y
80030d2: 4b52 ldr r3, [pc, #328] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030d4: 881a ldrh r2, [r3, #0]
80030d6: 4b51 ldr r3, [pc, #324] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030d8: 885b ldrh r3, [r3, #2]
80030da: 429a cmp r2, r3
80030dc: d21a bcs.n 8003114 <LCD_Scan_Dir+0x1ac>
{
temp=lcddev.width;
80030de: 4b4f ldr r3, [pc, #316] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030e0: 881b ldrh r3, [r3, #0]
80030e2: 817b strh r3, [r7, #10]
lcddev.width=lcddev.height;
80030e4: 4b4d ldr r3, [pc, #308] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030e6: 885a ldrh r2, [r3, #2]
80030e8: 4b4c ldr r3, [pc, #304] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030ea: 801a strh r2, [r3, #0]
lcddev.height=temp;
80030ec: 4a4b ldr r2, [pc, #300] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030ee: 897b ldrh r3, [r7, #10]
80030f0: 8053 strh r3, [r2, #2]
if(lcddev.width<lcddev.height)//����X,Y
80030f2: e00f b.n 8003114 <LCD_Scan_Dir+0x1ac>
}
}else
{
if(lcddev.width>lcddev.height)//����X,Y
80030f4: 4b49 ldr r3, [pc, #292] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030f6: 881a ldrh r2, [r3, #0]
80030f8: 4b48 ldr r3, [pc, #288] ; (800321c <LCD_Scan_Dir+0x2b4>)
80030fa: 885b ldrh r3, [r3, #2]
80030fc: 429a cmp r2, r3
80030fe: d909 bls.n 8003114 <LCD_Scan_Dir+0x1ac>
{
temp=lcddev.width;
8003100: 4b46 ldr r3, [pc, #280] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003102: 881b ldrh r3, [r3, #0]
8003104: 817b strh r3, [r7, #10]
lcddev.width=lcddev.height;
8003106: 4b45 ldr r3, [pc, #276] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003108: 885a ldrh r2, [r3, #2]
800310a: 4b44 ldr r3, [pc, #272] ; (800321c <LCD_Scan_Dir+0x2b4>)
800310c: 801a strh r2, [r3, #0]
lcddev.height=temp;
800310e: 4a43 ldr r2, [pc, #268] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003110: 897b ldrh r3, [r7, #10]
8003112: 8053 strh r3, [r2, #2]
}
}
LCD_WR_REG(lcddev.setxcmd);
8003114: 4b41 ldr r3, [pc, #260] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003116: 7a1b ldrb r3, [r3, #8]
8003118: b29b uxth r3, r3
800311a: 4618 mov r0, r3
800311c: f7ff fedc bl 8002ed8 <LCD_WR_REG>
LCD_WR_DATA(0);LCD_WR_DATA(0);
8003120: 2000 movs r0, #0
8003122: f7ff fee7 bl 8002ef4 <LCD_WR_DATA>
8003126: 2000 movs r0, #0
8003128: f7ff fee4 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_DATA((lcddev.width-1)>>8);LCD_WR_DATA((lcddev.width-1)&0XFF);
800312c: 4b3b ldr r3, [pc, #236] ; (800321c <LCD_Scan_Dir+0x2b4>)
800312e: 881b ldrh r3, [r3, #0]
8003130: 3b01 subs r3, #1
8003132: 121b asrs r3, r3, #8
8003134: b29b uxth r3, r3
8003136: 4618 mov r0, r3
8003138: f7ff fedc bl 8002ef4 <LCD_WR_DATA>
800313c: 4b37 ldr r3, [pc, #220] ; (800321c <LCD_Scan_Dir+0x2b4>)
800313e: 881b ldrh r3, [r3, #0]
8003140: 3b01 subs r3, #1
8003142: b29b uxth r3, r3
8003144: b2db uxtb r3, r3
8003146: b29b uxth r3, r3
8003148: 4618 mov r0, r3
800314a: f7ff fed3 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_REG(lcddev.setycmd);
800314e: 4b33 ldr r3, [pc, #204] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003150: 7a5b ldrb r3, [r3, #9]
8003152: b29b uxth r3, r3
8003154: 4618 mov r0, r3
8003156: f7ff febf bl 8002ed8 <LCD_WR_REG>
LCD_WR_DATA(0);LCD_WR_DATA(0);
800315a: 2000 movs r0, #0
800315c: f7ff feca bl 8002ef4 <LCD_WR_DATA>
8003160: 2000 movs r0, #0
8003162: f7ff fec7 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_DATA((lcddev.height-1)>>8);LCD_WR_DATA((lcddev.height-1)&0XFF);
8003166: 4b2d ldr r3, [pc, #180] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003168: 885b ldrh r3, [r3, #2]
800316a: 3b01 subs r3, #1
800316c: 121b asrs r3, r3, #8
800316e: b29b uxth r3, r3
8003170: 4618 mov r0, r3
8003172: f7ff febf bl 8002ef4 <LCD_WR_DATA>
8003176: 4b29 ldr r3, [pc, #164] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003178: 885b ldrh r3, [r3, #2]
800317a: 3b01 subs r3, #1
800317c: b29b uxth r3, r3
800317e: b2db uxtb r3, r3
8003180: b29b uxth r3, r3
8003182: 4618 mov r0, r3
8003184: f7ff feb6 bl 8002ef4 <LCD_WR_DATA>
8003188: e058 b.n 800323c <LCD_Scan_Dir+0x2d4>
}else
{
switch(dir)
800318a: 79fb ldrb r3, [r7, #7]
800318c: 2b07 cmp r3, #7
800318e: d836 bhi.n 80031fe <LCD_Scan_Dir+0x296>
8003190: a201 add r2, pc, #4 ; (adr r2, 8003198 <LCD_Scan_Dir+0x230>)
8003192: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003196: bf00 nop
8003198: 080031b9 .word 0x080031b9
800319c: 080031c3 .word 0x080031c3
80031a0: 080031cd .word 0x080031cd
80031a4: 080031ff .word 0x080031ff
80031a8: 080031d7 .word 0x080031d7
80031ac: 080031e1 .word 0x080031e1
80031b0: 080031eb .word 0x080031eb
80031b4: 080031f5 .word 0x080031f5
{
case L2R_U2D://��������,���ϵ���
regval|=(1<<5)|(1<<4)|(0<<3);
80031b8: 89fb ldrh r3, [r7, #14]
80031ba: f043 0330 orr.w r3, r3, #48 ; 0x30
80031be: 81fb strh r3, [r7, #14]
break;
80031c0: e01d b.n 80031fe <LCD_Scan_Dir+0x296>
case L2R_D2U://��������,���µ���
regval|=(0<<5)|(1<<4)|(0<<3);
80031c2: 89fb ldrh r3, [r7, #14]
80031c4: f043 0310 orr.w r3, r3, #16
80031c8: 81fb strh r3, [r7, #14]
break;
80031ca: e018 b.n 80031fe <LCD_Scan_Dir+0x296>
case R2L_U2D://���ҵ���,���ϵ���
regval|=(1<<5)|(0<<4)|(0<<3);
80031cc: 89fb ldrh r3, [r7, #14]
80031ce: f043 0320 orr.w r3, r3, #32
80031d2: 81fb strh r3, [r7, #14]
break;
80031d4: e013 b.n 80031fe <LCD_Scan_Dir+0x296>
case R2L_D2U://���ҵ���,���µ���
regval|=(0<<5)|(0<<4)|(0<<3);
break;
case U2D_L2R://���ϵ���,��������
regval|=(1<<5)|(1<<4)|(1<<3);
80031d6: 89fb ldrh r3, [r7, #14]
80031d8: f043 0338 orr.w r3, r3, #56 ; 0x38
80031dc: 81fb strh r3, [r7, #14]
break;
80031de: e00e b.n 80031fe <LCD_Scan_Dir+0x296>
case U2D_R2L://���ϵ���,���ҵ���
regval|=(1<<5)|(0<<4)|(1<<3);
80031e0: 89fb ldrh r3, [r7, #14]
80031e2: f043 0328 orr.w r3, r3, #40 ; 0x28
80031e6: 81fb strh r3, [r7, #14]
break;
80031e8: e009 b.n 80031fe <LCD_Scan_Dir+0x296>
case D2U_L2R://���µ���,��������
regval|=(0<<5)|(1<<4)|(1<<3);
80031ea: 89fb ldrh r3, [r7, #14]
80031ec: f043 0318 orr.w r3, r3, #24
80031f0: 81fb strh r3, [r7, #14]
break;
80031f2: e004 b.n 80031fe <LCD_Scan_Dir+0x296>
case D2U_R2L://���µ���,���ҵ���
regval|=(0<<5)|(0<<4)|(1<<3);
80031f4: 89fb ldrh r3, [r7, #14]
80031f6: f043 0308 orr.w r3, r3, #8
80031fa: 81fb strh r3, [r7, #14]
break;
80031fc: bf00 nop
}
if(lcddev.id==0x8989)//8989 IC
80031fe: 4b07 ldr r3, [pc, #28] ; (800321c <LCD_Scan_Dir+0x2b4>)
8003200: 889b ldrh r3, [r3, #4]
8003202: f648 1289 movw r2, #35209 ; 0x8989
8003206: 4293 cmp r3, r2
8003208: d10a bne.n 8003220 <LCD_Scan_Dir+0x2b8>
{
dirreg=0X11;
800320a: 2311 movs r3, #17
800320c: 737b strb r3, [r7, #13]
regval|=0X6040; //65K
800320e: 89fb ldrh r3, [r7, #14]
8003210: f443 43c0 orr.w r3, r3, #24576 ; 0x6000
8003214: f043 0340 orr.w r3, r3, #64 ; 0x40
8003218: 81fb strh r3, [r7, #14]
800321a: e007 b.n 800322c <LCD_Scan_Dir+0x2c4>
800321c: 20000560 .word 0x20000560
}else//��������IC
{
dirreg=0X03;
8003220: 2303 movs r3, #3
8003222: 737b strb r3, [r7, #13]
regval|=1<<12;
8003224: 89fb ldrh r3, [r7, #14]
8003226: f443 5380 orr.w r3, r3, #4096 ; 0x1000
800322a: 81fb strh r3, [r7, #14]
}
LCD_WriteReg(dirreg,regval);
800322c: 7b7b ldrb r3, [r7, #13]
800322e: b29b uxth r3, r3
8003230: 89fa ldrh r2, [r7, #14]
8003232: 4611 mov r1, r2
8003234: 4618 mov r0, r3
8003236: f7ff fe6d bl 8002f14 <LCD_WriteReg>
}
}
800323a: bf00 nop
800323c: bf00 nop
800323e: 3710 adds r7, #16
8003240: 46bd mov sp, r7
8003242: bd80 pop {r7, pc}
08003244 <LCD_Display_Dir>:
//����LCD��ʾ����
//dir:0,������1,����
void LCD_Display_Dir(uint8_t dir)
{
8003244: b580 push {r7, lr}
8003246: b082 sub sp, #8
8003248: af00 add r7, sp, #0
800324a: 4603 mov r3, r0
800324c: 71fb strb r3, [r7, #7]
if(dir==0) //����
800324e: 79fb ldrb r3, [r7, #7]
8003250: 2b00 cmp r3, #0
8003252: d154 bne.n 80032fe <LCD_Display_Dir+0xba>
{
lcddev.dir=0; //����
8003254: 4b5d ldr r3, [pc, #372] ; (80033cc <LCD_Display_Dir+0x188>)
8003256: 2200 movs r2, #0
8003258: 719a strb r2, [r3, #6]
lcddev.width=240;
800325a: 4b5c ldr r3, [pc, #368] ; (80033cc <LCD_Display_Dir+0x188>)
800325c: 22f0 movs r2, #240 ; 0xf0
800325e: 801a strh r2, [r3, #0]
lcddev.height=320;
8003260: 4b5a ldr r3, [pc, #360] ; (80033cc <LCD_Display_Dir+0x188>)
8003262: f44f 72a0 mov.w r2, #320 ; 0x140
8003266: 805a strh r2, [r3, #2]
if(lcddev.id==0X9341||lcddev.id==0X6804||lcddev.id==0X5310)
8003268: 4b58 ldr r3, [pc, #352] ; (80033cc <LCD_Display_Dir+0x188>)
800326a: 889b ldrh r3, [r3, #4]
800326c: f249 3241 movw r2, #37697 ; 0x9341
8003270: 4293 cmp r3, r2
8003272: d00b beq.n 800328c <LCD_Display_Dir+0x48>
8003274: 4b55 ldr r3, [pc, #340] ; (80033cc <LCD_Display_Dir+0x188>)
8003276: 889b ldrh r3, [r3, #4]
8003278: f646 0204 movw r2, #26628 ; 0x6804
800327c: 4293 cmp r3, r2
800327e: d005 beq.n 800328c <LCD_Display_Dir+0x48>
8003280: 4b52 ldr r3, [pc, #328] ; (80033cc <LCD_Display_Dir+0x188>)
8003282: 889b ldrh r3, [r3, #4]
8003284: f245 3210 movw r2, #21264 ; 0x5310
8003288: 4293 cmp r3, r2
800328a: d11e bne.n 80032ca <LCD_Display_Dir+0x86>
{
lcddev.wramcmd=0X2C;
800328c: 4b4f ldr r3, [pc, #316] ; (80033cc <LCD_Display_Dir+0x188>)
800328e: 222c movs r2, #44 ; 0x2c
8003290: 71da strb r2, [r3, #7]
lcddev.setxcmd=0X2A;
8003292: 4b4e ldr r3, [pc, #312] ; (80033cc <LCD_Display_Dir+0x188>)
8003294: 222a movs r2, #42 ; 0x2a
8003296: 721a strb r2, [r3, #8]
lcddev.setycmd=0X2B;
8003298: 4b4c ldr r3, [pc, #304] ; (80033cc <LCD_Display_Dir+0x188>)
800329a: 222b movs r2, #43 ; 0x2b
800329c: 725a strb r2, [r3, #9]
if(lcddev.id==0X6804||lcddev.id==0X5310)
800329e: 4b4b ldr r3, [pc, #300] ; (80033cc <LCD_Display_Dir+0x188>)
80032a0: 889b ldrh r3, [r3, #4]
80032a2: f646 0204 movw r2, #26628 ; 0x6804
80032a6: 4293 cmp r3, r2
80032a8: d006 beq.n 80032b8 <LCD_Display_Dir+0x74>
80032aa: 4b48 ldr r3, [pc, #288] ; (80033cc <LCD_Display_Dir+0x188>)
80032ac: 889b ldrh r3, [r3, #4]
80032ae: f245 3210 movw r2, #21264 ; 0x5310
80032b2: 4293 cmp r3, r2
80032b4: f040 8081 bne.w 80033ba <LCD_Display_Dir+0x176>
{
lcddev.width=320;
80032b8: 4b44 ldr r3, [pc, #272] ; (80033cc <LCD_Display_Dir+0x188>)
80032ba: f44f 72a0 mov.w r2, #320 ; 0x140
80032be: 801a strh r2, [r3, #0]
lcddev.height=480;
80032c0: 4b42 ldr r3, [pc, #264] ; (80033cc <LCD_Display_Dir+0x188>)
80032c2: f44f 72f0 mov.w r2, #480 ; 0x1e0
80032c6: 805a strh r2, [r3, #2]
if(lcddev.id==0X6804||lcddev.id==0X5310)
80032c8: e077 b.n 80033ba <LCD_Display_Dir+0x176>
}
}else if(lcddev.id==0X8989)
80032ca: 4b40 ldr r3, [pc, #256] ; (80033cc <LCD_Display_Dir+0x188>)
80032cc: 889b ldrh r3, [r3, #4]
80032ce: f648 1289 movw r2, #35209 ; 0x8989
80032d2: 4293 cmp r3, r2
80032d4: d109 bne.n 80032ea <LCD_Display_Dir+0xa6>
{
lcddev.wramcmd=R34;
80032d6: 4b3d ldr r3, [pc, #244] ; (80033cc <LCD_Display_Dir+0x188>)
80032d8: 2222 movs r2, #34 ; 0x22
80032da: 71da strb r2, [r3, #7]
lcddev.setxcmd=0X4E;
80032dc: 4b3b ldr r3, [pc, #236] ; (80033cc <LCD_Display_Dir+0x188>)
80032de: 224e movs r2, #78 ; 0x4e
80032e0: 721a strb r2, [r3, #8]
lcddev.setycmd=0X4F;
80032e2: 4b3a ldr r3, [pc, #232] ; (80033cc <LCD_Display_Dir+0x188>)
80032e4: 224f movs r2, #79 ; 0x4f
80032e6: 725a strb r2, [r3, #9]
80032e8: e068 b.n 80033bc <LCD_Display_Dir+0x178>
}else
{
lcddev.wramcmd=R34;
80032ea: 4b38 ldr r3, [pc, #224] ; (80033cc <LCD_Display_Dir+0x188>)
80032ec: 2222 movs r2, #34 ; 0x22
80032ee: 71da strb r2, [r3, #7]
lcddev.setxcmd=R32;
80032f0: 4b36 ldr r3, [pc, #216] ; (80033cc <LCD_Display_Dir+0x188>)
80032f2: 2220 movs r2, #32
80032f4: 721a strb r2, [r3, #8]
lcddev.setycmd=R33;
80032f6: 4b35 ldr r3, [pc, #212] ; (80033cc <LCD_Display_Dir+0x188>)
80032f8: 2221 movs r2, #33 ; 0x21
80032fa: 725a strb r2, [r3, #9]
80032fc: e05e b.n 80033bc <LCD_Display_Dir+0x178>
}
}else //����
{
lcddev.dir=1; //����
80032fe: 4b33 ldr r3, [pc, #204] ; (80033cc <LCD_Display_Dir+0x188>)
8003300: 2201 movs r2, #1
8003302: 719a strb r2, [r3, #6]
lcddev.width=320;
8003304: 4b31 ldr r3, [pc, #196] ; (80033cc <LCD_Display_Dir+0x188>)
8003306: f44f 72a0 mov.w r2, #320 ; 0x140
800330a: 801a strh r2, [r3, #0]
lcddev.height=240;
800330c: 4b2f ldr r3, [pc, #188] ; (80033cc <LCD_Display_Dir+0x188>)
800330e: 22f0 movs r2, #240 ; 0xf0
8003310: 805a strh r2, [r3, #2]
if(lcddev.id==0X9341||lcddev.id==0X5310)
8003312: 4b2e ldr r3, [pc, #184] ; (80033cc <LCD_Display_Dir+0x188>)
8003314: 889b ldrh r3, [r3, #4]
8003316: f249 3241 movw r2, #37697 ; 0x9341
800331a: 4293 cmp r3, r2
800331c: d005 beq.n 800332a <LCD_Display_Dir+0xe6>
800331e: 4b2b ldr r3, [pc, #172] ; (80033cc <LCD_Display_Dir+0x188>)
8003320: 889b ldrh r3, [r3, #4]
8003322: f245 3210 movw r2, #21264 ; 0x5310
8003326: 4293 cmp r3, r2
8003328: d109 bne.n 800333e <LCD_Display_Dir+0xfa>
{
lcddev.wramcmd=0X2C;
800332a: 4b28 ldr r3, [pc, #160] ; (80033cc <LCD_Display_Dir+0x188>)
800332c: 222c movs r2, #44 ; 0x2c
800332e: 71da strb r2, [r3, #7]
lcddev.setxcmd=0X2A;
8003330: 4b26 ldr r3, [pc, #152] ; (80033cc <LCD_Display_Dir+0x188>)
8003332: 222a movs r2, #42 ; 0x2a
8003334: 721a strb r2, [r3, #8]
lcddev.setycmd=0X2B;
8003336: 4b25 ldr r3, [pc, #148] ; (80033cc <LCD_Display_Dir+0x188>)
8003338: 222b movs r2, #43 ; 0x2b
800333a: 725a strb r2, [r3, #9]
800333c: e028 b.n 8003390 <LCD_Display_Dir+0x14c>
}else if(lcddev.id==0X6804)
800333e: 4b23 ldr r3, [pc, #140] ; (80033cc <LCD_Display_Dir+0x188>)
8003340: 889b ldrh r3, [r3, #4]
8003342: f646 0204 movw r2, #26628 ; 0x6804
8003346: 4293 cmp r3, r2
8003348: d109 bne.n 800335e <LCD_Display_Dir+0x11a>
{
lcddev.wramcmd=0X2C;
800334a: 4b20 ldr r3, [pc, #128] ; (80033cc <LCD_Display_Dir+0x188>)
800334c: 222c movs r2, #44 ; 0x2c
800334e: 71da strb r2, [r3, #7]
lcddev.setxcmd=0X2B;
8003350: 4b1e ldr r3, [pc, #120] ; (80033cc <LCD_Display_Dir+0x188>)
8003352: 222b movs r2, #43 ; 0x2b
8003354: 721a strb r2, [r3, #8]
lcddev.setycmd=0X2A;
8003356: 4b1d ldr r3, [pc, #116] ; (80033cc <LCD_Display_Dir+0x188>)
8003358: 222a movs r2, #42 ; 0x2a
800335a: 725a strb r2, [r3, #9]
800335c: e018 b.n 8003390 <LCD_Display_Dir+0x14c>
}else if(lcddev.id==0X8989)
800335e: 4b1b ldr r3, [pc, #108] ; (80033cc <LCD_Display_Dir+0x188>)
8003360: 889b ldrh r3, [r3, #4]
8003362: f648 1289 movw r2, #35209 ; 0x8989
8003366: 4293 cmp r3, r2
8003368: d109 bne.n 800337e <LCD_Display_Dir+0x13a>
{
lcddev.wramcmd=R34;
800336a: 4b18 ldr r3, [pc, #96] ; (80033cc <LCD_Display_Dir+0x188>)
800336c: 2222 movs r2, #34 ; 0x22
800336e: 71da strb r2, [r3, #7]
lcddev.setxcmd=0X4F;
8003370: 4b16 ldr r3, [pc, #88] ; (80033cc <LCD_Display_Dir+0x188>)
8003372: 224f movs r2, #79 ; 0x4f
8003374: 721a strb r2, [r3, #8]
lcddev.setycmd=0X4E;
8003376: 4b15 ldr r3, [pc, #84] ; (80033cc <LCD_Display_Dir+0x188>)
8003378: 224e movs r2, #78 ; 0x4e
800337a: 725a strb r2, [r3, #9]
800337c: e008 b.n 8003390 <LCD_Display_Dir+0x14c>
}else
{
lcddev.wramcmd=R34;
800337e: 4b13 ldr r3, [pc, #76] ; (80033cc <LCD_Display_Dir+0x188>)
8003380: 2222 movs r2, #34 ; 0x22
8003382: 71da strb r2, [r3, #7]
lcddev.setxcmd=R33;
8003384: 4b11 ldr r3, [pc, #68] ; (80033cc <LCD_Display_Dir+0x188>)
8003386: 2221 movs r2, #33 ; 0x21
8003388: 721a strb r2, [r3, #8]
lcddev.setycmd=R32;
800338a: 4b10 ldr r3, [pc, #64] ; (80033cc <LCD_Display_Dir+0x188>)
800338c: 2220 movs r2, #32
800338e: 725a strb r2, [r3, #9]
}
if(lcddev.id==0X6804||lcddev.id==0X5310)
8003390: 4b0e ldr r3, [pc, #56] ; (80033cc <LCD_Display_Dir+0x188>)
8003392: 889b ldrh r3, [r3, #4]
8003394: f646 0204 movw r2, #26628 ; 0x6804
8003398: 4293 cmp r3, r2
800339a: d005 beq.n 80033a8 <LCD_Display_Dir+0x164>
800339c: 4b0b ldr r3, [pc, #44] ; (80033cc <LCD_Display_Dir+0x188>)
800339e: 889b ldrh r3, [r3, #4]
80033a0: f245 3210 movw r2, #21264 ; 0x5310
80033a4: 4293 cmp r3, r2
80033a6: d109 bne.n 80033bc <LCD_Display_Dir+0x178>
{
lcddev.width=480;
80033a8: 4b08 ldr r3, [pc, #32] ; (80033cc <LCD_Display_Dir+0x188>)
80033aa: f44f 72f0 mov.w r2, #480 ; 0x1e0
80033ae: 801a strh r2, [r3, #0]
lcddev.height=320;
80033b0: 4b06 ldr r3, [pc, #24] ; (80033cc <LCD_Display_Dir+0x188>)
80033b2: f44f 72a0 mov.w r2, #320 ; 0x140
80033b6: 805a strh r2, [r3, #2]
80033b8: e000 b.n 80033bc <LCD_Display_Dir+0x178>
if(lcddev.id==0X6804||lcddev.id==0X5310)
80033ba: bf00 nop
}
}
LCD_Scan_Dir(DFT_SCAN_DIR); //Ĭ��ɨ�跽��
80033bc: 2000 movs r0, #0
80033be: f7ff fdd3 bl 8002f68 <LCD_Scan_Dir>
}
80033c2: bf00 nop
80033c4: 3708 adds r7, #8
80033c6: 46bd mov sp, r7
80033c8: bd80 pop {r7, pc}
80033ca: bf00 nop
80033cc: 20000560 .word 0x20000560
080033d0 <LCDx_Init>:
//��ʼ��lcd
//�ó�ʼ���������Գ�ʼ������Һ��!
void LCDx_Init(void)
{
80033d0: b580 push {r7, lr}
80033d2: af00 add r7, sp, #0
LCD_BL(0);
80033d4: 2200 movs r2, #0
80033d6: 2101 movs r1, #1
80033d8: 4876 ldr r0, [pc, #472] ; (80035b4 <LCDx_Init+0x1e4>)
80033da: f7fd fccd bl 8000d78 <HAL_GPIO_WritePin>
HAL_Delay(50); // delay 50 ms
80033de: 2032 movs r0, #50 ; 0x32
80033e0: f7fd fa2e bl 8000840 <HAL_Delay>
LCD_WriteReg(0x0000,0x0001);
80033e4: 2101 movs r1, #1
80033e6: 2000 movs r0, #0
80033e8: f7ff fd94 bl 8002f14 <LCD_WriteReg>
HAL_Delay(50); // delay 50 ms
80033ec: 2032 movs r0, #50 ; 0x32
80033ee: f7fd fa27 bl 8000840 <HAL_Delay>
lcddev.id = LCD_ReadReg(0x0000);
80033f2: 2000 movs r0, #0
80033f4: f7ff fda4 bl 8002f40 <LCD_ReadReg>
80033f8: 4603 mov r3, r0
80033fa: 461a mov r2, r3
80033fc: 4b6e ldr r3, [pc, #440] ; (80035b8 <LCDx_Init+0x1e8>)
80033fe: 809a strh r2, [r3, #4]
LCD_WriteReg(0x00E5,0x78F0);
8003400: f647 01f0 movw r1, #30960 ; 0x78f0
8003404: 20e5 movs r0, #229 ; 0xe5
8003406: f7ff fd85 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0001,0x0100);
800340a: f44f 7180 mov.w r1, #256 ; 0x100
800340e: 2001 movs r0, #1
8003410: f7ff fd80 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0002,0x0700);
8003414: f44f 61e0 mov.w r1, #1792 ; 0x700
8003418: 2002 movs r0, #2
800341a: f7ff fd7b bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0003,0x1030);
800341e: f241 0130 movw r1, #4144 ; 0x1030
8003422: 2003 movs r0, #3
8003424: f7ff fd76 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0004,0x0000);
8003428: 2100 movs r1, #0
800342a: 2004 movs r0, #4
800342c: f7ff fd72 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0008,0x0202);
8003430: f240 2102 movw r1, #514 ; 0x202
8003434: 2008 movs r0, #8
8003436: f7ff fd6d bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0009,0x0000);
800343a: 2100 movs r1, #0
800343c: 2009 movs r0, #9
800343e: f7ff fd69 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x000A,0x0000);
8003442: 2100 movs r1, #0
8003444: 200a movs r0, #10
8003446: f7ff fd65 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x000C,0x0000);
800344a: 2100 movs r1, #0
800344c: 200c movs r0, #12
800344e: f7ff fd61 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x000D,0x0000);
8003452: 2100 movs r1, #0
8003454: 200d movs r0, #13
8003456: f7ff fd5d bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x000F,0x0000);
800345a: 2100 movs r1, #0
800345c: 200f movs r0, #15
800345e: f7ff fd59 bl 8002f14 <LCD_WriteReg>
//power on sequence VGHVGL
LCD_WriteReg(0x0010,0x0000);
8003462: 2100 movs r1, #0
8003464: 2010 movs r0, #16
8003466: f7ff fd55 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0011,0x0007);
800346a: 2107 movs r1, #7
800346c: 2011 movs r0, #17
800346e: f7ff fd51 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0012,0x0000);
8003472: 2100 movs r1, #0
8003474: 2012 movs r0, #18
8003476: f7ff fd4d bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0013,0x0000);
800347a: 2100 movs r1, #0
800347c: 2013 movs r0, #19
800347e: f7ff fd49 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0007,0x0000);
8003482: 2100 movs r1, #0
8003484: 2007 movs r0, #7
8003486: f7ff fd45 bl 8002f14 <LCD_WriteReg>
//vgh
LCD_WriteReg(0x0010,0x1690);
800348a: f241 6190 movw r1, #5776 ; 0x1690
800348e: 2010 movs r0, #16
8003490: f7ff fd40 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0011,0x0227);
8003494: f240 2127 movw r1, #551 ; 0x227
8003498: 2011 movs r0, #17
800349a: f7ff fd3b bl 8002f14 <LCD_WriteReg>
//delayms(100);
//vregiout
LCD_WriteReg(0x0012,0x009D); //0x001b
800349e: 219d movs r1, #157 ; 0x9d
80034a0: 2012 movs r0, #18
80034a2: f7ff fd37 bl 8002f14 <LCD_WriteReg>
//delayms(100);
//vom amplitude
LCD_WriteReg(0x0013,0x1900);
80034a6: f44f 51c8 mov.w r1, #6400 ; 0x1900
80034aa: 2013 movs r0, #19
80034ac: f7ff fd32 bl 8002f14 <LCD_WriteReg>
//delayms(100);
//vom H
LCD_WriteReg(0x0029,0x0025);
80034b0: 2125 movs r1, #37 ; 0x25
80034b2: 2029 movs r0, #41 ; 0x29
80034b4: f7ff fd2e bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x002B,0x000D);
80034b8: 210d movs r1, #13
80034ba: 202b movs r0, #43 ; 0x2b
80034bc: f7ff fd2a bl 8002f14 <LCD_WriteReg>
//gamma
LCD_WriteReg(0x0030,0x0007);
80034c0: 2107 movs r1, #7
80034c2: 2030 movs r0, #48 ; 0x30
80034c4: f7ff fd26 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0031,0x0303);
80034c8: f240 3103 movw r1, #771 ; 0x303
80034cc: 2031 movs r0, #49 ; 0x31
80034ce: f7ff fd21 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0032,0x0003);// 0006
80034d2: 2103 movs r1, #3
80034d4: 2032 movs r0, #50 ; 0x32
80034d6: f7ff fd1d bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0035,0x0206);
80034da: f240 2106 movw r1, #518 ; 0x206
80034de: 2035 movs r0, #53 ; 0x35
80034e0: f7ff fd18 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0036,0x0008);
80034e4: 2108 movs r1, #8
80034e6: 2036 movs r0, #54 ; 0x36
80034e8: f7ff fd14 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0037,0x0406);
80034ec: f240 4106 movw r1, #1030 ; 0x406
80034f0: 2037 movs r0, #55 ; 0x37
80034f2: f7ff fd0f bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0038,0x0304);//0200
80034f6: f44f 7141 mov.w r1, #772 ; 0x304
80034fa: 2038 movs r0, #56 ; 0x38
80034fc: f7ff fd0a bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0039,0x0007);
8003500: 2107 movs r1, #7
8003502: 2039 movs r0, #57 ; 0x39
8003504: f7ff fd06 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x003C,0x0602);// 0504
8003508: f240 6102 movw r1, #1538 ; 0x602
800350c: 203c movs r0, #60 ; 0x3c
800350e: f7ff fd01 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x003D,0x0008);
8003512: 2108 movs r1, #8
8003514: 203d movs r0, #61 ; 0x3d
8003516: f7ff fcfd bl 8002f14 <LCD_WriteReg>
//ram
LCD_WriteReg(0x0050,0x0000);
800351a: 2100 movs r1, #0
800351c: 2050 movs r0, #80 ; 0x50
800351e: f7ff fcf9 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0051,0x00EF);
8003522: 21ef movs r1, #239 ; 0xef
8003524: 2051 movs r0, #81 ; 0x51
8003526: f7ff fcf5 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0052,0x0000);
800352a: 2100 movs r1, #0
800352c: 2052 movs r0, #82 ; 0x52
800352e: f7ff fcf1 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0053,0x013F);
8003532: f240 113f movw r1, #319 ; 0x13f
8003536: 2053 movs r0, #83 ; 0x53
8003538: f7ff fcec bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0060,0xA700);
800353c: f44f 4127 mov.w r1, #42752 ; 0xa700
8003540: 2060 movs r0, #96 ; 0x60
8003542: f7ff fce7 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0061,0x0001);
8003546: 2101 movs r1, #1
8003548: 2061 movs r0, #97 ; 0x61
800354a: f7ff fce3 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x006A,0x0000);
800354e: 2100 movs r1, #0
8003550: 206a movs r0, #106 ; 0x6a
8003552: f7ff fcdf bl 8002f14 <LCD_WriteReg>
//
LCD_WriteReg(0x0080,0x0000);
8003556: 2100 movs r1, #0
8003558: 2080 movs r0, #128 ; 0x80
800355a: f7ff fcdb bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0081,0x0000);
800355e: 2100 movs r1, #0
8003560: 2081 movs r0, #129 ; 0x81
8003562: f7ff fcd7 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0082,0x0000);
8003566: 2100 movs r1, #0
8003568: 2082 movs r0, #130 ; 0x82
800356a: f7ff fcd3 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0083,0x0000);
800356e: 2100 movs r1, #0
8003570: 2083 movs r0, #131 ; 0x83
8003572: f7ff fccf bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0084,0x0000);
8003576: 2100 movs r1, #0
8003578: 2084 movs r0, #132 ; 0x84
800357a: f7ff fccb bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0085,0x0000);
800357e: 2100 movs r1, #0
8003580: 2085 movs r0, #133 ; 0x85
8003582: f7ff fcc7 bl 8002f14 <LCD_WriteReg>
//
LCD_WriteReg(0x0090,0x0010);
8003586: 2110 movs r1, #16
8003588: 2090 movs r0, #144 ; 0x90
800358a: f7ff fcc3 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0092,0x0600);
800358e: f44f 61c0 mov.w r1, #1536 ; 0x600
8003592: 2092 movs r0, #146 ; 0x92
8003594: f7ff fcbe bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x0007,0x0133);
8003598: f240 1133 movw r1, #307 ; 0x133
800359c: 2007 movs r0, #7
800359e: f7ff fcb9 bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(0x00,0x0022);//
80035a2: 2122 movs r1, #34 ; 0x22
80035a4: 2000 movs r0, #0
80035a6: f7ff fcb5 bl 8002f14 <LCD_WriteReg>
LCD_Display_Dir(1); //Ĭ��Ϊh��
80035aa: 2001 movs r0, #1
80035ac: f7ff fe4a bl 8003244 <LCD_Display_Dir>
}
80035b0: bf00 nop
80035b2: bd80 pop {r7, pc}
80035b4: 40010c00 .word 0x40010c00
80035b8: 20000560 .word 0x20000560
080035bc <LCD_SetCursor>:
//***********************************************************���� ���� ʲô��
//���ù���λ��
//Xpos:������
//Ypos:������
void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos)
{
80035bc: b580 push {r7, lr}
80035be: b082 sub sp, #8
80035c0: af00 add r7, sp, #0
80035c2: 4603 mov r3, r0
80035c4: 460a mov r2, r1
80035c6: 80fb strh r3, [r7, #6]
80035c8: 4613 mov r3, r2
80035ca: 80bb strh r3, [r7, #4]
if(lcddev.id==0X9341||lcddev.id==0X5310)
80035cc: 4b42 ldr r3, [pc, #264] ; (80036d8 <LCD_SetCursor+0x11c>)
80035ce: 889b ldrh r3, [r3, #4]
80035d0: f249 3241 movw r2, #37697 ; 0x9341
80035d4: 4293 cmp r3, r2
80035d6: d005 beq.n 80035e4 <LCD_SetCursor+0x28>
80035d8: 4b3f ldr r3, [pc, #252] ; (80036d8 <LCD_SetCursor+0x11c>)
80035da: 889b ldrh r3, [r3, #4]
80035dc: f245 3210 movw r2, #21264 ; 0x5310
80035e0: 4293 cmp r3, r2
80035e2: d124 bne.n 800362e <LCD_SetCursor+0x72>
{
LCD_WR_REG(lcddev.setxcmd);
80035e4: 4b3c ldr r3, [pc, #240] ; (80036d8 <LCD_SetCursor+0x11c>)
80035e6: 7a1b ldrb r3, [r3, #8]
80035e8: b29b uxth r3, r3
80035ea: 4618 mov r0, r3
80035ec: f7ff fc74 bl 8002ed8 <LCD_WR_REG>
LCD_WR_DATA(Xpos>>8);
80035f0: 88fb ldrh r3, [r7, #6]
80035f2: 0a1b lsrs r3, r3, #8
80035f4: b29b uxth r3, r3
80035f6: 4618 mov r0, r3
80035f8: f7ff fc7c bl 8002ef4 <LCD_WR_DATA>
LCD_WR_DATA(Xpos&0XFF);
80035fc: 88fb ldrh r3, [r7, #6]
80035fe: b2db uxtb r3, r3
8003600: b29b uxth r3, r3
8003602: 4618 mov r0, r3
8003604: f7ff fc76 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_REG(lcddev.setycmd);
8003608: 4b33 ldr r3, [pc, #204] ; (80036d8 <LCD_SetCursor+0x11c>)
800360a: 7a5b ldrb r3, [r3, #9]
800360c: b29b uxth r3, r3
800360e: 4618 mov r0, r3
8003610: f7ff fc62 bl 8002ed8 <LCD_WR_REG>
LCD_WR_DATA(Ypos>>8);
8003614: 88bb ldrh r3, [r7, #4]
8003616: 0a1b lsrs r3, r3, #8
8003618: b29b uxth r3, r3
800361a: 4618 mov r0, r3
800361c: f7ff fc6a bl 8002ef4 <LCD_WR_DATA>
LCD_WR_DATA(Ypos&0XFF);
8003620: 88bb ldrh r3, [r7, #4]
8003622: b2db uxtb r3, r3
8003624: b29b uxth r3, r3
8003626: 4618 mov r0, r3
8003628: f7ff fc64 bl 8002ef4 <LCD_WR_DATA>
{
if(lcddev.dir==1)Xpos=lcddev.width-1-Xpos;//������ʵ���ǵ�תx,y����
LCD_WriteReg(lcddev.setxcmd, Xpos);
LCD_WriteReg(lcddev.setycmd, Ypos);
}
}
800362c: e050 b.n 80036d0 <LCD_SetCursor+0x114>
}else if(lcddev.id==0X6804)
800362e: 4b2a ldr r3, [pc, #168] ; (80036d8 <LCD_SetCursor+0x11c>)
8003630: 889b ldrh r3, [r3, #4]
8003632: f646 0204 movw r2, #26628 ; 0x6804
8003636: 4293 cmp r3, r2
8003638: d12f bne.n 800369a <LCD_SetCursor+0xde>
if(lcddev.dir==1)Xpos=lcddev.width-1-Xpos;//����ʱ����
800363a: 4b27 ldr r3, [pc, #156] ; (80036d8 <LCD_SetCursor+0x11c>)
800363c: 799b ldrb r3, [r3, #6]
800363e: 2b01 cmp r3, #1
8003640: d106 bne.n 8003650 <LCD_SetCursor+0x94>
8003642: 4b25 ldr r3, [pc, #148] ; (80036d8 <LCD_SetCursor+0x11c>)
8003644: 881a ldrh r2, [r3, #0]
8003646: 88fb ldrh r3, [r7, #6]
8003648: 1ad3 subs r3, r2, r3
800364a: b29b uxth r3, r3
800364c: 3b01 subs r3, #1
800364e: 80fb strh r3, [r7, #6]
LCD_WR_REG(lcddev.setxcmd);
8003650: 4b21 ldr r3, [pc, #132] ; (80036d8 <LCD_SetCursor+0x11c>)
8003652: 7a1b ldrb r3, [r3, #8]
8003654: b29b uxth r3, r3
8003656: 4618 mov r0, r3
8003658: f7ff fc3e bl 8002ed8 <LCD_WR_REG>
LCD_WR_DATA(Xpos>>8);
800365c: 88fb ldrh r3, [r7, #6]
800365e: 0a1b lsrs r3, r3, #8
8003660: b29b uxth r3, r3
8003662: 4618 mov r0, r3
8003664: f7ff fc46 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_DATA(Xpos&0XFF);
8003668: 88fb ldrh r3, [r7, #6]
800366a: b2db uxtb r3, r3
800366c: b29b uxth r3, r3
800366e: 4618 mov r0, r3
8003670: f7ff fc40 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_REG(lcddev.setycmd);
8003674: 4b18 ldr r3, [pc, #96] ; (80036d8 <LCD_SetCursor+0x11c>)
8003676: 7a5b ldrb r3, [r3, #9]
8003678: b29b uxth r3, r3
800367a: 4618 mov r0, r3
800367c: f7ff fc2c bl 8002ed8 <LCD_WR_REG>
LCD_WR_DATA(Ypos>>8);
8003680: 88bb ldrh r3, [r7, #4]
8003682: 0a1b lsrs r3, r3, #8
8003684: b29b uxth r3, r3
8003686: 4618 mov r0, r3
8003688: f7ff fc34 bl 8002ef4 <LCD_WR_DATA>
LCD_WR_DATA(Ypos&0XFF);
800368c: 88bb ldrh r3, [r7, #4]
800368e: b2db uxtb r3, r3
8003690: b29b uxth r3, r3
8003692: 4618 mov r0, r3
8003694: f7ff fc2e bl 8002ef4 <LCD_WR_DATA>
}
8003698: e01a b.n 80036d0 <LCD_SetCursor+0x114>
if(lcddev.dir==1)Xpos=lcddev.width-1-Xpos;//������ʵ���ǵ�תx,y����
800369a: 4b0f ldr r3, [pc, #60] ; (80036d8 <LCD_SetCursor+0x11c>)
800369c: 799b ldrb r3, [r3, #6]
800369e: 2b01 cmp r3, #1
80036a0: d106 bne.n 80036b0 <LCD_SetCursor+0xf4>
80036a2: 4b0d ldr r3, [pc, #52] ; (80036d8 <LCD_SetCursor+0x11c>)
80036a4: 881a ldrh r2, [r3, #0]
80036a6: 88fb ldrh r3, [r7, #6]
80036a8: 1ad3 subs r3, r2, r3
80036aa: b29b uxth r3, r3
80036ac: 3b01 subs r3, #1
80036ae: 80fb strh r3, [r7, #6]
LCD_WriteReg(lcddev.setxcmd, Xpos);
80036b0: 4b09 ldr r3, [pc, #36] ; (80036d8 <LCD_SetCursor+0x11c>)
80036b2: 7a1b ldrb r3, [r3, #8]
80036b4: b29b uxth r3, r3
80036b6: 88fa ldrh r2, [r7, #6]
80036b8: 4611 mov r1, r2
80036ba: 4618 mov r0, r3
80036bc: f7ff fc2a bl 8002f14 <LCD_WriteReg>
LCD_WriteReg(lcddev.setycmd, Ypos);
80036c0: 4b05 ldr r3, [pc, #20] ; (80036d8 <LCD_SetCursor+0x11c>)
80036c2: 7a5b ldrb r3, [r3, #9]
80036c4: b29b uxth r3, r3
80036c6: 88ba ldrh r2, [r7, #4]
80036c8: 4611 mov r1, r2
80036ca: 4618 mov r0, r3
80036cc: f7ff fc22 bl 8002f14 <LCD_WriteReg>
}
80036d0: bf00 nop
80036d2: 3708 adds r7, #8
80036d4: 46bd mov sp, r7
80036d6: bd80 pop {r7, pc}
80036d8: 20000560 .word 0x20000560
080036dc <LCD_set_dot>:
}
//����
//x,y:����
//POINT_COLOR:�˵�����ɫ
void LCD_set_dot(uint16_t x,uint16_t y,uint16_t color)
{
80036dc: b580 push {r7, lr}
80036de: b082 sub sp, #8
80036e0: af00 add r7, sp, #0
80036e2: 4603 mov r3, r0
80036e4: 80fb strh r3, [r7, #6]
80036e6: 460b mov r3, r1
80036e8: 80bb strh r3, [r7, #4]
80036ea: 4613 mov r3, r2
80036ec: 807b strh r3, [r7, #2]
LCD_SetCursor(x,y); //���ù���λ��
80036ee: 88ba ldrh r2, [r7, #4]
80036f0: 88fb ldrh r3, [r7, #6]
80036f2: 4611 mov r1, r2
80036f4: 4618 mov r0, r3
80036f6: f7ff ff61 bl 80035bc <LCD_SetCursor>
LCD_REG_ADDRESS=lcddev.wramcmd; //��ʼд��GRAM
80036fa: 4b06 ldr r3, [pc, #24] ; (8003714 <LCD_set_dot+0x38>)
80036fc: 79da ldrb r2, [r3, #7]
80036fe: f04f 43d8 mov.w r3, #1811939328 ; 0x6c000000
8003702: b292 uxth r2, r2
8003704: 801a strh r2, [r3, #0]
LCD_DATA_ADDRESS=color;
8003706: 4a04 ldr r2, [pc, #16] ; (8003718 <LCD_set_dot+0x3c>)
8003708: 887b ldrh r3, [r7, #2]
800370a: 8013 strh r3, [r2, #0]
}
800370c: bf00 nop
800370e: 3708 adds r7, #8
8003710: 46bd mov sp, r7
8003712: bd80 pop {r7, pc}
8003714: 20000560 .word 0x20000560
8003718: 6c000800 .word 0x6c000800
0800371c <LCD_Clear>:
//��������
//color:Ҫ����������ɫ
void LCD_Clear(uint16_t color)
{
800371c: b580 push {r7, lr}
800371e: b084 sub sp, #16
8003720: af00 add r7, sp, #0
8003722: 4603 mov r3, r0
8003724: 80fb strh r3, [r7, #6]
uint32_t index=0;
8003726: 2300 movs r3, #0
8003728: 60fb str r3, [r7, #12]
uint32_t totalpoint=lcddev.width;
800372a: 4b23 ldr r3, [pc, #140] ; (80037b8 <LCD_Clear+0x9c>)
800372c: 881b ldrh r3, [r3, #0]
800372e: 60bb str r3, [r7, #8]
totalpoint*=lcddev.height; //�õ��ܵ���
8003730: 4b21 ldr r3, [pc, #132] ; (80037b8 <LCD_Clear+0x9c>)
8003732: 885b ldrh r3, [r3, #2]
8003734: 461a mov r2, r3
8003736: 68bb ldr r3, [r7, #8]
8003738: fb02 f303 mul.w r3, r2, r3
800373c: 60bb str r3, [r7, #8]
if((lcddev.id==0X6804)&&(lcddev.dir==1))//6804������ʱ�����⴦��
800373e: 4b1e ldr r3, [pc, #120] ; (80037b8 <LCD_Clear+0x9c>)
8003740: 889b ldrh r3, [r3, #4]
8003742: f646 0204 movw r2, #26628 ; 0x6804
8003746: 4293 cmp r3, r2
8003748: d11a bne.n 8003780 <LCD_Clear+0x64>
800374a: 4b1b ldr r3, [pc, #108] ; (80037b8 <LCD_Clear+0x9c>)
800374c: 799b ldrb r3, [r3, #6]
800374e: 2b01 cmp r3, #1
8003750: d116 bne.n 8003780 <LCD_Clear+0x64>
{
lcddev.dir=0;
8003752: 4b19 ldr r3, [pc, #100] ; (80037b8 <LCD_Clear+0x9c>)
8003754: 2200 movs r2, #0
8003756: 719a strb r2, [r3, #6]
lcddev.setxcmd=0X2A;
8003758: 4b17 ldr r3, [pc, #92] ; (80037b8 <LCD_Clear+0x9c>)
800375a: 222a movs r2, #42 ; 0x2a
800375c: 721a strb r2, [r3, #8]
lcddev.setycmd=0X2B;
800375e: 4b16 ldr r3, [pc, #88] ; (80037b8 <LCD_Clear+0x9c>)
8003760: 222b movs r2, #43 ; 0x2b
8003762: 725a strb r2, [r3, #9]
LCD_SetCursor(0x00,0x0000); //���ù���λ��
8003764: 2100 movs r1, #0
8003766: 2000 movs r0, #0
8003768: f7ff ff28 bl 80035bc <LCD_SetCursor>
lcddev.dir=1;
800376c: 4b12 ldr r3, [pc, #72] ; (80037b8 <LCD_Clear+0x9c>)
800376e: 2201 movs r2, #1
8003770: 719a strb r2, [r3, #6]
lcddev.setxcmd=0X2B;
8003772: 4b11 ldr r3, [pc, #68] ; (80037b8 <LCD_Clear+0x9c>)
8003774: 222b movs r2, #43 ; 0x2b
8003776: 721a strb r2, [r3, #8]
lcddev.setycmd=0X2A;
8003778: 4b0f ldr r3, [pc, #60] ; (80037b8 <LCD_Clear+0x9c>)
800377a: 222a movs r2, #42 ; 0x2a
800377c: 725a strb r2, [r3, #9]
800377e: e003 b.n 8003788 <LCD_Clear+0x6c>
}else LCD_SetCursor(0x00,0x0000); //���ù���λ��
8003780: 2100 movs r1, #0
8003782: 2000 movs r0, #0
8003784: f7ff ff1a bl 80035bc <LCD_SetCursor>
LCD_REG_ADDRESS=lcddev.wramcmd; //��ʼд��GRAM
8003788: 4b0b ldr r3, [pc, #44] ; (80037b8 <LCD_Clear+0x9c>)
800378a: 79da ldrb r2, [r3, #7]
800378c: f04f 43d8 mov.w r3, #1811939328 ; 0x6c000000
8003790: b292 uxth r2, r2
8003792: 801a strh r2, [r3, #0]
for(index=0;index<totalpoint;index++)
8003794: 2300 movs r3, #0
8003796: 60fb str r3, [r7, #12]
8003798: e005 b.n 80037a6 <LCD_Clear+0x8a>
{
LCD_DATA_ADDRESS=color;
800379a: 4a08 ldr r2, [pc, #32] ; (80037bc <LCD_Clear+0xa0>)
800379c: 88fb ldrh r3, [r7, #6]
800379e: 8013 strh r3, [r2, #0]
for(index=0;index<totalpoint;index++)
80037a0: 68fb ldr r3, [r7, #12]
80037a2: 3301 adds r3, #1
80037a4: 60fb str r3, [r7, #12]
80037a6: 68fa ldr r2, [r7, #12]
80037a8: 68bb ldr r3, [r7, #8]
80037aa: 429a cmp r2, r3
80037ac: d3f5 bcc.n 800379a <LCD_Clear+0x7e>
}
}
80037ae: bf00 nop
80037b0: bf00 nop
80037b2: 3710 adds r7, #16
80037b4: 46bd mov sp, r7
80037b6: bd80 pop {r7, pc}
80037b8: 20000560 .word 0x20000560
80037bc: 6c000800 .word 0x6c000800
080037c0 <font_init>:
//��ʼ������
//����ֵ:0,�ֿ�����.
// ����,�ֿⶪʧ
uint8_t font_init(void)
{
80037c0: b580 push {r7, lr}
80037c2: b082 sub sp, #8
80037c4: af00 add r7, sp, #0
uint8_t t=0;
80037c6: 2300 movs r3, #0
80037c8: 71fb strb r3, [r7, #7]
while(t<10)//������ȡ10��,���Ǵ���,˵��ȷʵ��������,�ø����ֿ���
80037ca: e013 b.n 80037f4 <font_init+0x34>
{
t++;
80037cc: 79fb ldrb r3, [r7, #7]
80037ce: 3301 adds r3, #1
80037d0: 71fb strb r3, [r7, #7]
W25QXX_Read((uint8_t*)&ftinfo,FONTINFOADDR,sizeof(ftinfo));//����ftinfo�ṹ������
80037d2: 2224 movs r2, #36 ; 0x24
80037d4: f44f 0180 mov.w r1, #4194304 ; 0x400000
80037d8: 480d ldr r0, [pc, #52] ; (8003810 <font_init+0x50>)
80037da: f7fe fe71 bl 80024c0 <W25QXX_Read>
if(ftinfo.fontok==0XAA)
80037de: 4b0c ldr r3, [pc, #48] ; (8003810 <font_init+0x50>)
80037e0: 781b ldrb r3, [r3, #0]
80037e2: 2baa cmp r3, #170 ; 0xaa
80037e4: d106 bne.n 80037f4 <font_init+0x34>
{
ftinfo.f12addr+=1;
80037e6: 4b0a ldr r3, [pc, #40] ; (8003810 <font_init+0x50>)
80037e8: 68db ldr r3, [r3, #12]
80037ea: 3301 adds r3, #1
80037ec: 4a08 ldr r2, [pc, #32] ; (8003810 <font_init+0x50>)
80037ee: 60d3 str r3, [r2, #12]
return 0;
80037f0: 2300 movs r3, #0
80037f2: e008 b.n 8003806 <font_init+0x46>
while(t<10)//������ȡ10��,���Ǵ���,˵��ȷʵ��������,�ø����ֿ���
80037f4: 79fb ldrb r3, [r7, #7]
80037f6: 2b09 cmp r3, #9
80037f8: d9e8 bls.n 80037cc <font_init+0xc>
}
}
if(ftinfo.fontok!=0XAA)return 1;
80037fa: 4b05 ldr r3, [pc, #20] ; (8003810 <font_init+0x50>)
80037fc: 781b ldrb r3, [r3, #0]
80037fe: 2baa cmp r3, #170 ; 0xaa
8003800: d001 beq.n 8003806 <font_init+0x46>
8003802: 2301 movs r3, #1
8003804: e7ff b.n 8003806 <font_init+0x46>
}
8003806: 4618 mov r0, r3
8003808: 3708 adds r7, #8
800380a: 46bd mov sp, r7
800380c: bd80 pop {r7, pc}
800380e: bf00 nop
8003810: 2000056c .word 0x2000056c
08003814 <Get_HzMat>:
//���ֿ��в��ҳ���ģ
//code �ַ����Ŀ�ʼ��ַ,GBK��
//mat ���ݴ��ŵ�ַ (size/8+((size%8)?1:0))*(size) bytes��С
//size:������С
void Get_HzMat(unsigned char *code,unsigned char *mat,uint8_t size)
{
8003814: b580 push {r7, lr}
8003816: b086 sub sp, #24
8003818: af00 add r7, sp, #0
800381a: 60f8 str r0, [r7, #12]
800381c: 60b9 str r1, [r7, #8]
800381e: 4613 mov r3, r2
8003820: 71fb strb r3, [r7, #7]
unsigned char qh,ql;
unsigned char i;
unsigned long foffset;
uint8_t csize=(size/8+((size%8)?1:0))*(size);//�õ�����һ���ַ���Ӧ��������ռ���ֽ���
8003822: 79fb ldrb r3, [r7, #7]
8003824: 08db lsrs r3, r3, #3
8003826: b2db uxtb r3, r3
8003828: 461a mov r2, r3
800382a: 79fb ldrb r3, [r7, #7]
800382c: f003 0307 and.w r3, r3, #7
8003830: b2db uxtb r3, r3
8003832: 2b00 cmp r3, #0
8003834: bf14 ite ne
8003836: 2301 movne r3, #1
8003838: 2300 moveq r3, #0
800383a: b2db uxtb r3, r3
800383c: 4413 add r3, r2
800383e: b2db uxtb r3, r3
8003840: 79fa ldrb r2, [r7, #7]
8003842: fb02 f303 mul.w r3, r2, r3
8003846: 757b strb r3, [r7, #21]
qh=*code;
8003848: 68fb ldr r3, [r7, #12]
800384a: 781b ldrb r3, [r3, #0]
800384c: 753b strb r3, [r7, #20]
ql=*(++code);
800384e: 68fb ldr r3, [r7, #12]
8003850: 3301 adds r3, #1
8003852: 60fb str r3, [r7, #12]
8003854: 68fb ldr r3, [r7, #12]
8003856: 781b ldrb r3, [r3, #0]
8003858: 75fb strb r3, [r7, #23]
if(qh<0x81||ql<0x40||ql==0xff||qh==0xff)//�� ���ú���
800385a: 7d3b ldrb r3, [r7, #20]
800385c: 2b80 cmp r3, #128 ; 0x80
800385e: d908 bls.n 8003872 <Get_HzMat+0x5e>
8003860: 7dfb ldrb r3, [r7, #23]
8003862: 2b3f cmp r3, #63 ; 0x3f
8003864: d905 bls.n 8003872 <Get_HzMat+0x5e>
8003866: 7dfb ldrb r3, [r7, #23]
8003868: 2bff cmp r3, #255 ; 0xff
800386a: d002 beq.n 8003872 <Get_HzMat+0x5e>
800386c: 7d3b ldrb r3, [r7, #20]
800386e: 2bff cmp r3, #255 ; 0xff
8003870: d10f bne.n 8003892 <Get_HzMat+0x7e>
{
for(i=0;i<csize;i++)*mat++=0x00;//��������
8003872: 2300 movs r3, #0
8003874: 75bb strb r3, [r7, #22]
8003876: e007 b.n 8003888 <Get_HzMat+0x74>
8003878: 68bb ldr r3, [r7, #8]
800387a: 1c5a adds r2, r3, #1
800387c: 60ba str r2, [r7, #8]
800387e: 2200 movs r2, #0
8003880: 701a strb r2, [r3, #0]
8003882: 7dbb ldrb r3, [r7, #22]
8003884: 3301 adds r3, #1
8003886: 75bb strb r3, [r7, #22]
8003888: 7dba ldrb r2, [r7, #22]
800388a: 7d7b ldrb r3, [r7, #21]
800388c: 429a cmp r2, r3
800388e: d3f3 bcc.n 8003878 <Get_HzMat+0x64>
return; //��������
8003890: e041 b.n 8003916 <Get_HzMat+0x102>
}
if(ql<0x7f)ql-=0x40;//ע��!
8003892: 7dfb ldrb r3, [r7, #23]
8003894: 2b7e cmp r3, #126 ; 0x7e
8003896: d803 bhi.n 80038a0 <Get_HzMat+0x8c>
8003898: 7dfb ldrb r3, [r7, #23]
800389a: 3b40 subs r3, #64 ; 0x40
800389c: 75fb strb r3, [r7, #23]
800389e: e002 b.n 80038a6 <Get_HzMat+0x92>
else ql-=0x41;
80038a0: 7dfb ldrb r3, [r7, #23]
80038a2: 3b41 subs r3, #65 ; 0x41
80038a4: 75fb strb r3, [r7, #23]
qh-=0x81;
80038a6: 7d3b ldrb r3, [r7, #20]
80038a8: 337f adds r3, #127 ; 0x7f
80038aa: 753b strb r3, [r7, #20]
foffset=((unsigned long)190*qh+ql)*csize; //�õ��ֿ��е��ֽ�ƫ����
80038ac: 7d3b ldrb r3, [r7, #20]
80038ae: 22be movs r2, #190 ; 0xbe
80038b0: fb02 f203 mul.w r2, r2, r3
80038b4: 7dfb ldrb r3, [r7, #23]
80038b6: 4413 add r3, r2
80038b8: 7d7a ldrb r2, [r7, #21]
80038ba: fb02 f303 mul.w r3, r2, r3
80038be: 613b str r3, [r7, #16]
switch(size)
80038c0: 79fb ldrb r3, [r7, #7]
80038c2: 2b18 cmp r3, #24
80038c4: d01c beq.n 8003900 <Get_HzMat+0xec>
80038c6: 2b18 cmp r3, #24
80038c8: dc25 bgt.n 8003916 <Get_HzMat+0x102>
80038ca: 2b0c cmp r3, #12
80038cc: d002 beq.n 80038d4 <Get_HzMat+0xc0>
80038ce: 2b10 cmp r3, #16
80038d0: d00b beq.n 80038ea <Get_HzMat+0xd6>
80038d2: e020 b.n 8003916 <Get_HzMat+0x102>
{
case 12:
W25QXX_Read(mat,foffset+ftinfo.f12addr,csize);
80038d4: 4b11 ldr r3, [pc, #68] ; (800391c <Get_HzMat+0x108>)
80038d6: 68da ldr r2, [r3, #12]
80038d8: 693b ldr r3, [r7, #16]
80038da: 4413 add r3, r2
80038dc: 7d7a ldrb r2, [r7, #21]
80038de: b292 uxth r2, r2
80038e0: 4619 mov r1, r3
80038e2: 68b8 ldr r0, [r7, #8]
80038e4: f7fe fdec bl 80024c0 <W25QXX_Read>
break;
80038e8: e015 b.n 8003916 <Get_HzMat+0x102>
case 16:
W25QXX_Read(mat,foffset+ftinfo.f16addr,csize);
80038ea: 4b0c ldr r3, [pc, #48] ; (800391c <Get_HzMat+0x108>)
80038ec: 695a ldr r2, [r3, #20]
80038ee: 693b ldr r3, [r7, #16]
80038f0: 4413 add r3, r2
80038f2: 7d7a ldrb r2, [r7, #21]
80038f4: b292 uxth r2, r2
80038f6: 4619 mov r1, r3
80038f8: 68b8 ldr r0, [r7, #8]
80038fa: f7fe fde1 bl 80024c0 <W25QXX_Read>
break;
80038fe: e00a b.n 8003916 <Get_HzMat+0x102>
case 24:
W25QXX_Read(mat,foffset+ftinfo.f24addr,csize);
8003900: 4b06 ldr r3, [pc, #24] ; (800391c <Get_HzMat+0x108>)
8003902: 69da ldr r2, [r3, #28]
8003904: 693b ldr r3, [r7, #16]
8003906: 4413 add r3, r2
8003908: 7d7a ldrb r2, [r7, #21]
800390a: b292 uxth r2, r2
800390c: 4619 mov r1, r3
800390e: 68b8 ldr r0, [r7, #8]
8003910: f7fe fdd6 bl 80024c0 <W25QXX_Read>
break;
8003914: bf00 nop
}
}
8003916: 3718 adds r7, #24
8003918: 46bd mov sp, r7
800391a: bd80 pop {r7, pc}
800391c: 2000056c .word 0x2000056c
08003920 <Show_Font>:
//x,y :���ֵ�����
//font:����GBK��
//size:������С
//mode:0,������ʾ,1,������ʾ
void Show_Font(uint16_t x,uint16_t y,uint8_t *font,uint8_t size,uint16_t bg,uint16_t color)
{
8003920: b580 push {r7, lr}
8003922: b098 sub sp, #96 ; 0x60
8003924: af00 add r7, sp, #0
8003926: 60ba str r2, [r7, #8]
8003928: 461a mov r2, r3
800392a: 4603 mov r3, r0
800392c: 81fb strh r3, [r7, #14]
800392e: 460b mov r3, r1
8003930: 81bb strh r3, [r7, #12]
8003932: 4613 mov r3, r2
8003934: 71fb strb r3, [r7, #7]
uint8_t temp,t,t1;
uint16_t y0=y;
8003936: 89bb ldrh r3, [r7, #12]
8003938: f8a7 305a strh.w r3, [r7, #90] ; 0x5a
uint8_t dzk[72];
uint8_t csize=(size/8+((size%8)?1:0))*(size);//�õ�����һ���ַ���Ӧ��������ռ���ֽ���
800393c: 79fb ldrb r3, [r7, #7]
800393e: 08db lsrs r3, r3, #3
8003940: b2db uxtb r3, r3
8003942: 461a mov r2, r3
8003944: 79fb ldrb r3, [r7, #7]
8003946: f003 0307 and.w r3, r3, #7
800394a: b2db uxtb r3, r3
800394c: 2b00 cmp r3, #0
800394e: bf14 ite ne
8003950: 2301 movne r3, #1
8003952: 2300 moveq r3, #0
8003954: b2db uxtb r3, r3
8003956: 4413 add r3, r2
8003958: b2db uxtb r3, r3
800395a: 79fa ldrb r2, [r7, #7]
800395c: fb02 f303 mul.w r3, r2, r3
8003960: f887 3059 strb.w r3, [r7, #89] ; 0x59
if(size!=12&&size!=16)return; //��֧�ֵ�size
8003964: 79fb ldrb r3, [r7, #7]
8003966: 2b0c cmp r3, #12
8003968: d002 beq.n 8003970 <Show_Font+0x50>
800396a: 79fb ldrb r3, [r7, #7]
800396c: 2b10 cmp r3, #16
800396e: d15b bne.n 8003a28 <Show_Font+0x108>
Get_HzMat(font,dzk,size); //�õ���Ӧ��С�ĵ�������
8003970: 79fa ldrb r2, [r7, #7]
8003972: f107 0310 add.w r3, r7, #16
8003976: 4619 mov r1, r3
8003978: 68b8 ldr r0, [r7, #8]
800397a: f7ff ff4b bl 8003814 <Get_HzMat>
for(t=0;t<csize;t++)
800397e: 2300 movs r3, #0
8003980: f887 305e strb.w r3, [r7, #94] ; 0x5e
8003984: e049 b.n 8003a1a <Show_Font+0xfa>
{
temp=dzk[t]; //�õ���������
8003986: f897 305e ldrb.w r3, [r7, #94] ; 0x5e
800398a: f107 0260 add.w r2, r7, #96 ; 0x60
800398e: 4413 add r3, r2
8003990: f813 3c50 ldrb.w r3, [r3, #-80]
8003994: f887 305f strb.w r3, [r7, #95] ; 0x5f
for(t1=0;t1<8;t1++)
8003998: 2300 movs r3, #0
800399a: f887 305d strb.w r3, [r7, #93] ; 0x5d
800399e: e033 b.n 8003a08 <Show_Font+0xe8>
{
if(temp&0x80){LCD_set_dot(x,y,color);}else{if(bg!=color){LCD_set_dot(x,y,bg);}}
80039a0: f997 305f ldrsb.w r3, [r7, #95] ; 0x5f
80039a4: 2b00 cmp r3, #0
80039a6: da07 bge.n 80039b8 <Show_Font+0x98>
80039a8: f8b7 206c ldrh.w r2, [r7, #108] ; 0x6c
80039ac: 89b9 ldrh r1, [r7, #12]
80039ae: 89fb ldrh r3, [r7, #14]
80039b0: 4618 mov r0, r3
80039b2: f7ff fe93 bl 80036dc <LCD_set_dot>
80039b6: e00c b.n 80039d2 <Show_Font+0xb2>
80039b8: f8b7 2068 ldrh.w r2, [r7, #104] ; 0x68
80039bc: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c
80039c0: 429a cmp r2, r3
80039c2: d006 beq.n 80039d2 <Show_Font+0xb2>
80039c4: f8b7 2068 ldrh.w r2, [r7, #104] ; 0x68
80039c8: 89b9 ldrh r1, [r7, #12]
80039ca: 89fb ldrh r3, [r7, #14]
80039cc: 4618 mov r0, r3
80039ce: f7ff fe85 bl 80036dc <LCD_set_dot>
temp<<=1;
80039d2: f897 305f ldrb.w r3, [r7, #95] ; 0x5f
80039d6: 005b lsls r3, r3, #1
80039d8: f887 305f strb.w r3, [r7, #95] ; 0x5f
y++;
80039dc: 89bb ldrh r3, [r7, #12]
80039de: 3301 adds r3, #1
80039e0: 81bb strh r3, [r7, #12]
if((y-y0)==size)
80039e2: 89ba ldrh r2, [r7, #12]
80039e4: f8b7 305a ldrh.w r3, [r7, #90] ; 0x5a
80039e8: 1ad2 subs r2, r2, r3
80039ea: 79fb ldrb r3, [r7, #7]
80039ec: 429a cmp r2, r3
80039ee: d106 bne.n 80039fe <Show_Font+0xde>
{
y=y0;
80039f0: f8b7 305a ldrh.w r3, [r7, #90] ; 0x5a
80039f4: 81bb strh r3, [r7, #12]
x++;
80039f6: 89fb ldrh r3, [r7, #14]
80039f8: 3301 adds r3, #1
80039fa: 81fb strh r3, [r7, #14]
break;
80039fc: e008 b.n 8003a10 <Show_Font+0xf0>
for(t1=0;t1<8;t1++)
80039fe: f897 305d ldrb.w r3, [r7, #93] ; 0x5d
8003a02: 3301 adds r3, #1
8003a04: f887 305d strb.w r3, [r7, #93] ; 0x5d
8003a08: f897 305d ldrb.w r3, [r7, #93] ; 0x5d
8003a0c: 2b07 cmp r3, #7
8003a0e: d9c7 bls.n 80039a0 <Show_Font+0x80>
for(t=0;t<csize;t++)
8003a10: f897 305e ldrb.w r3, [r7, #94] ; 0x5e
8003a14: 3301 adds r3, #1
8003a16: f887 305e strb.w r3, [r7, #94] ; 0x5e
8003a1a: f897 205e ldrb.w r2, [r7, #94] ; 0x5e
8003a1e: f897 3059 ldrb.w r3, [r7, #89] ; 0x59
8003a22: 429a cmp r2, r3
8003a24: d3af bcc.n 8003986 <Show_Font+0x66>
8003a26: e000 b.n 8003a2a <Show_Font+0x10a>
if(size!=12&&size!=16)return; //��֧�ֵ�size
8003a28: bf00 nop
}
}
}
}
8003a2a: 3760 adds r7, #96 ; 0x60
8003a2c: 46bd mov sp, r7
8003a2e: bd80 pop {r7, pc}
08003a30 <LCD_ShowChar>:
//num:Ҫ��ʾ���ַ�:" "--->"~"
//size:������С 12/16
//mode:���ӷ�ʽ(1)���Ƿǵ��ӷ�ʽ(0)
void LCD_ShowChar(uint16_t x,uint16_t y,uint8_t num,uint8_t size,uint16_t bg,uint16_t color)
{
8003a30: b590 push {r4, r7, lr}
8003a32: b085 sub sp, #20
8003a34: af00 add r7, sp, #0
8003a36: 4604 mov r4, r0
8003a38: 4608 mov r0, r1
8003a3a: 4611 mov r1, r2
8003a3c: 461a mov r2, r3
8003a3e: 4623 mov r3, r4
8003a40: 80fb strh r3, [r7, #6]
8003a42: 4603 mov r3, r0
8003a44: 80bb strh r3, [r7, #4]
8003a46: 460b mov r3, r1
8003a48: 70fb strb r3, [r7, #3]
8003a4a: 4613 mov r3, r2
8003a4c: 70bb strb r3, [r7, #2]
uint8_t temp,t1,t;
uint16_t y0=y;
8003a4e: 88bb ldrh r3, [r7, #4]
8003a50: 817b strh r3, [r7, #10]
//����
num=num-' ';//�õ�ƫ�ƺ���ֵ
8003a52: 78fb ldrb r3, [r7, #3]
8003a54: 3b20 subs r3, #32
8003a56: 70fb strb r3, [r7, #3]
for(t=0;t<size;t++)
8003a58: 2300 movs r3, #0
8003a5a: 737b strb r3, [r7, #13]
8003a5c: e055 b.n 8003b0a <LCD_ShowChar+0xda>
{
if(size==12){temp=asc2_1206[num][t];} //����1206����
8003a5e: 78bb ldrb r3, [r7, #2]
8003a60: 2b0c cmp r3, #12
8003a62: d10b bne.n 8003a7c <LCD_ShowChar+0x4c>
8003a64: 78fa ldrb r2, [r7, #3]
8003a66: 7b79 ldrb r1, [r7, #13]
8003a68: 482c ldr r0, [pc, #176] ; (8003b1c <LCD_ShowChar+0xec>)
8003a6a: 4613 mov r3, r2
8003a6c: 005b lsls r3, r3, #1
8003a6e: 4413 add r3, r2
8003a70: 009b lsls r3, r3, #2
8003a72: 4403 add r3, r0
8003a74: 440b add r3, r1
8003a76: 781b ldrb r3, [r3, #0]
8003a78: 73fb strb r3, [r7, #15]
8003a7a: e007 b.n 8003a8c <LCD_ShowChar+0x5c>
else{ temp=asc2_1608[num][t]; } //����1608����
8003a7c: 78fa ldrb r2, [r7, #3]
8003a7e: 7b7b ldrb r3, [r7, #13]
8003a80: 4927 ldr r1, [pc, #156] ; (8003b20 <LCD_ShowChar+0xf0>)
8003a82: 0112 lsls r2, r2, #4
8003a84: 440a add r2, r1
8003a86: 4413 add r3, r2
8003a88: 781b ldrb r3, [r3, #0]
8003a8a: 73fb strb r3, [r7, #15]
for(t1=0;t1<8;t1++)
8003a8c: 2300 movs r3, #0
8003a8e: 73bb strb r3, [r7, #14]
8003a90: e033 b.n 8003afa <LCD_ShowChar+0xca>
{
if(temp&0x80){LCD_set_dot(x,y,color);}else{if(bg!=color){LCD_set_dot(x,y,bg);}}
8003a92: f997 300f ldrsb.w r3, [r7, #15]
8003a96: 2b00 cmp r3, #0
8003a98: da06 bge.n 8003aa8 <LCD_ShowChar+0x78>
8003a9a: 8cba ldrh r2, [r7, #36] ; 0x24
8003a9c: 88b9 ldrh r1, [r7, #4]
8003a9e: 88fb ldrh r3, [r7, #6]
8003aa0: 4618 mov r0, r3
8003aa2: f7ff fe1b bl 80036dc <LCD_set_dot>
8003aa6: e009 b.n 8003abc <LCD_ShowChar+0x8c>
8003aa8: 8c3a ldrh r2, [r7, #32]
8003aaa: 8cbb ldrh r3, [r7, #36] ; 0x24
8003aac: 429a cmp r2, r3
8003aae: d005 beq.n 8003abc <LCD_ShowChar+0x8c>
8003ab0: 8c3a ldrh r2, [r7, #32]
8003ab2: 88b9 ldrh r1, [r7, #4]
8003ab4: 88fb ldrh r3, [r7, #6]
8003ab6: 4618 mov r0, r3
8003ab8: f7ff fe10 bl 80036dc <LCD_set_dot>
temp<<=1;
8003abc: 7bfb ldrb r3, [r7, #15]
8003abe: 005b lsls r3, r3, #1
8003ac0: 73fb strb r3, [r7, #15]
y++;
8003ac2: 88bb ldrh r3, [r7, #4]
8003ac4: 3301 adds r3, #1
8003ac6: 80bb strh r3, [r7, #4]
if(x>=lcddev.width){return;}//��������
8003ac8: 4b16 ldr r3, [pc, #88] ; (8003b24 <LCD_ShowChar+0xf4>)
8003aca: 881b ldrh r3, [r3, #0]
8003acc: 88fa ldrh r2, [r7, #6]
8003ace: 429a cmp r2, r3
8003ad0: d220 bcs.n 8003b14 <LCD_ShowChar+0xe4>
if((y-y0)==size)
8003ad2: 88ba ldrh r2, [r7, #4]
8003ad4: 897b ldrh r3, [r7, #10]
8003ad6: 1ad2 subs r2, r2, r3
8003ad8: 78bb ldrb r3, [r7, #2]
8003ada: 429a cmp r2, r3
8003adc: d10a bne.n 8003af4 <LCD_ShowChar+0xc4>
{
y=y0;
8003ade: 897b ldrh r3, [r7, #10]
8003ae0: 80bb strh r3, [r7, #4]
x++;
8003ae2: 88fb ldrh r3, [r7, #6]
8003ae4: 3301 adds r3, #1
8003ae6: 80fb strh r3, [r7, #6]
if(x>=lcddev.width){return;}//��������
8003ae8: 4b0e ldr r3, [pc, #56] ; (8003b24 <LCD_ShowChar+0xf4>)
8003aea: 881b ldrh r3, [r3, #0]
8003aec: 88fa ldrh r2, [r7, #6]
8003aee: 429a cmp r2, r3
8003af0: d307 bcc.n 8003b02 <LCD_ShowChar+0xd2>
8003af2: e010 b.n 8003b16 <LCD_ShowChar+0xe6>
for(t1=0;t1<8;t1++)
8003af4: 7bbb ldrb r3, [r7, #14]
8003af6: 3301 adds r3, #1
8003af8: 73bb strb r3, [r7, #14]
8003afa: 7bbb ldrb r3, [r7, #14]
8003afc: 2b07 cmp r3, #7
8003afe: d9c8 bls.n 8003a92 <LCD_ShowChar+0x62>
8003b00: e000 b.n 8003b04 <LCD_ShowChar+0xd4>
break;
8003b02: bf00 nop
for(t=0;t<size;t++)
8003b04: 7b7b ldrb r3, [r7, #13]
8003b06: 3301 adds r3, #1
8003b08: 737b strb r3, [r7, #13]
8003b0a: 7b7a ldrb r2, [r7, #13]
8003b0c: 78bb ldrb r3, [r7, #2]
8003b0e: 429a cmp r2, r3
8003b10: d3a5 bcc.n 8003a5e <LCD_ShowChar+0x2e>
8003b12: e000 b.n 8003b16 <LCD_ShowChar+0xe6>
if(x>=lcddev.width){return;}//��������
8003b14: bf00 nop
}
}
}
8003b16: 3714 adds r7, #20
8003b18: 46bd mov sp, r7
8003b1a: bd90 pop {r4, r7, pc}
8003b1c: 08003c98 .word 0x08003c98
8003b20: 0800410c .word 0x0800410c
8003b24: 20000560 .word 0x20000560
08003b28 <LCD_ShowString>:
//width,height:������С
//size:������С
//*p:�ַ�����ʼ��ַ
void LCD_ShowString(uint16_t x,uint16_t y,uint8_t *p,uint8_t size,uint16_t bg,uint16_t color)
{
8003b28: b590 push {r4, r7, lr}
8003b2a: b087 sub sp, #28
8003b2c: af02 add r7, sp, #8
8003b2e: 60ba str r2, [r7, #8]
8003b30: 461a mov r2, r3
8003b32: 4603 mov r3, r0
8003b34: 81fb strh r3, [r7, #14]
8003b36: 460b mov r3, r1
8003b38: 81bb strh r3, [r7, #12]
8003b3a: 4613 mov r3, r2
8003b3c: 71fb strb r3, [r7, #7]
while(*p!='\0')
8003b3e: e04e b.n 8003bde <LCD_ShowString+0xb6>
{
if(x>=lcddev.width)
8003b40: 4b2b ldr r3, [pc, #172] ; (8003bf0 <LCD_ShowString+0xc8>)
8003b42: 881b ldrh r3, [r3, #0]
8003b44: 89fa ldrh r2, [r7, #14]
8003b46: 429a cmp r2, r3
8003b48: d306 bcc.n 8003b58 <LCD_ShowString+0x30>
{
x=0;
8003b4a: 2300 movs r3, #0
8003b4c: 81fb strh r3, [r7, #14]
y+=size;
8003b4e: 79fb ldrb r3, [r7, #7]
8003b50: b29a uxth r2, r3
8003b52: 89bb ldrh r3, [r7, #12]
8003b54: 4413 add r3, r2
8003b56: 81bb strh r3, [r7, #12]
}
if(*p=='\r')
8003b58: 68bb ldr r3, [r7, #8]
8003b5a: 781b ldrb r3, [r3, #0]
8003b5c: 2b0d cmp r3, #13
8003b5e: d102 bne.n 8003b66 <LCD_ShowString+0x3e>
{
p++;
8003b60: 68bb ldr r3, [r7, #8]
8003b62: 3301 adds r3, #1
8003b64: 60bb str r3, [r7, #8]
}
if(*p=='\n')
8003b66: 68bb ldr r3, [r7, #8]
8003b68: 781b ldrb r3, [r3, #0]
8003b6a: 2b0a cmp r3, #10
8003b6c: d109 bne.n 8003b82 <LCD_ShowString+0x5a>
{
x=0;
8003b6e: 2300 movs r3, #0
8003b70: 81fb strh r3, [r7, #14]
y+=size;
8003b72: 79fb ldrb r3, [r7, #7]
8003b74: b29a uxth r2, r3
8003b76: 89bb ldrh r3, [r7, #12]
8003b78: 4413 add r3, r2
8003b7a: 81bb strh r3, [r7, #12]
p++;
8003b7c: 68bb ldr r3, [r7, #8]
8003b7e: 3301 adds r3, #1
8003b80: 60bb str r3, [r7, #8]
}
if(*p<127)
8003b82: 68bb ldr r3, [r7, #8]
8003b84: 781b ldrb r3, [r3, #0]
8003b86: 2b7e cmp r3, #126 ; 0x7e
8003b88: d813 bhi.n 8003bb2 <LCD_ShowString+0x8a>
{
LCD_ShowChar(x,y,*p,size,bg,color);
8003b8a: 68bb ldr r3, [r7, #8]
8003b8c: 781a ldrb r2, [r3, #0]
8003b8e: 79fc ldrb r4, [r7, #7]
8003b90: 89b9 ldrh r1, [r7, #12]
8003b92: 89f8 ldrh r0, [r7, #14]
8003b94: 8cbb ldrh r3, [r7, #36] ; 0x24
8003b96: 9301 str r3, [sp, #4]
8003b98: 8c3b ldrh r3, [r7, #32]
8003b9a: 9300 str r3, [sp, #0]
8003b9c: 4623 mov r3, r4
8003b9e: f7ff ff47 bl 8003a30 <LCD_ShowChar>
x+=(size/2);
8003ba2: 79fb ldrb r3, [r7, #7]
8003ba4: 085b lsrs r3, r3, #1
8003ba6: b2db uxtb r3, r3
8003ba8: b29a uxth r2, r3
8003baa: 89fb ldrh r3, [r7, #14]
8003bac: 4413 add r3, r2
8003bae: 81fb strh r3, [r7, #14]
8003bb0: e012 b.n 8003bd8 <LCD_ShowString+0xb0>
}else
{
Show_Font(x,y,p,size,bg,color);
8003bb2: 79fa ldrb r2, [r7, #7]
8003bb4: 89b9 ldrh r1, [r7, #12]
8003bb6: 89f8 ldrh r0, [r7, #14]
8003bb8: 8cbb ldrh r3, [r7, #36] ; 0x24
8003bba: 9301 str r3, [sp, #4]
8003bbc: 8c3b ldrh r3, [r7, #32]
8003bbe: 9300 str r3, [sp, #0]
8003bc0: 4613 mov r3, r2
8003bc2: 68ba ldr r2, [r7, #8]
8003bc4: f7ff feac bl 8003920 <Show_Font>
p++;
8003bc8: 68bb ldr r3, [r7, #8]
8003bca: 3301 adds r3, #1
8003bcc: 60bb str r3, [r7, #8]
x+=size;
8003bce: 79fb ldrb r3, [r7, #7]
8003bd0: b29a uxth r2, r3
8003bd2: 89fb ldrh r3, [r7, #14]
8003bd4: 4413 add r3, r2
8003bd6: 81fb strh r3, [r7, #14]
}
p++;
8003bd8: 68bb ldr r3, [r7, #8]
8003bda: 3301 adds r3, #1
8003bdc: 60bb str r3, [r7, #8]
while(*p!='\0')
8003bde: 68bb ldr r3, [r7, #8]
8003be0: 781b ldrb r3, [r3, #0]
8003be2: 2b00 cmp r3, #0
8003be4: d1ac bne.n 8003b40 <LCD_ShowString+0x18>
}
}
8003be6: bf00 nop
8003be8: bf00 nop
8003bea: 3714 adds r7, #20
8003bec: 46bd mov sp, r7
8003bee: bd90 pop {r4, r7, pc}
8003bf0: 20000560 .word 0x20000560
08003bf4 <__libc_init_array>:
8003bf4: b570 push {r4, r5, r6, lr}
8003bf6: 2600 movs r6, #0
8003bf8: 4d0c ldr r5, [pc, #48] ; (8003c2c <__libc_init_array+0x38>)
8003bfa: 4c0d ldr r4, [pc, #52] ; (8003c30 <__libc_init_array+0x3c>)
8003bfc: 1b64 subs r4, r4, r5
8003bfe: 10a4 asrs r4, r4, #2
8003c00: 42a6 cmp r6, r4
8003c02: d109 bne.n 8003c18 <__libc_init_array+0x24>
8003c04: f000 f822 bl 8003c4c <_init>
8003c08: 2600 movs r6, #0
8003c0a: 4d0a ldr r5, [pc, #40] ; (8003c34 <__libc_init_array+0x40>)
8003c0c: 4c0a ldr r4, [pc, #40] ; (8003c38 <__libc_init_array+0x44>)
8003c0e: 1b64 subs r4, r4, r5
8003c10: 10a4 asrs r4, r4, #2
8003c12: 42a6 cmp r6, r4
8003c14: d105 bne.n 8003c22 <__libc_init_array+0x2e>
8003c16: bd70 pop {r4, r5, r6, pc}
8003c18: f855 3b04 ldr.w r3, [r5], #4
8003c1c: 4798 blx r3
8003c1e: 3601 adds r6, #1
8003c20: e7ee b.n 8003c00 <__libc_init_array+0xc>
8003c22: f855 3b04 ldr.w r3, [r5], #4
8003c26: 4798 blx r3
8003c28: 3601 adds r6, #1
8003c2a: e7f2 b.n 8003c12 <__libc_init_array+0x1e>
8003c2c: 080046fc .word 0x080046fc
8003c30: 080046fc .word 0x080046fc
8003c34: 080046fc .word 0x080046fc
8003c38: 08004700 .word 0x08004700
08003c3c <memset>:
8003c3c: 4603 mov r3, r0
8003c3e: 4402 add r2, r0
8003c40: 4293 cmp r3, r2
8003c42: d100 bne.n 8003c46 <memset+0xa>
8003c44: 4770 bx lr
8003c46: f803 1b01 strb.w r1, [r3], #1
8003c4a: e7f9 b.n 8003c40 <memset+0x4>
08003c4c <_init>:
8003c4c: b5f8 push {r3, r4, r5, r6, r7, lr}
8003c4e: bf00 nop
8003c50: bcf8 pop {r3, r4, r5, r6, r7}
8003c52: bc08 pop {r3}
8003c54: 469e mov lr, r3
8003c56: 4770 bx lr
08003c58 <_fini>:
8003c58: b5f8 push {r3, r4, r5, r6, r7, lr}
8003c5a: bf00 nop
8003c5c: bcf8 pop {r3, r4, r5, r6, r7}
8003c5e: bc08 pop {r3}
8003c60: 469e mov lr, r3
8003c62: 4770 bx lr
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